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ALSA: hda - use usleep_range in link reset and change timeout check
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4
LT		 64#include "hda_codec.h"
65
66
5aba4f8e
TI		 67static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
68static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 69static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 70static char *model[SNDRV_CARDS];
1dac6695 71static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 72static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 73static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 74static int probe_only[SNDRV_CARDS];
26a6cb6c 75static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 76static bool single_cmd;
71623855 77static int enable_msi = -1;
4ea6fbc8
TI		 78#ifdef CONFIG_SND_HDA_PATCH_LOADER
79static char *patch[SNDRV_CARDS];
80#endif
2dca0bba 81#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 82static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 83 CONFIG_SND_HDA_INPUT_BEEP_MODE};
84#endif
1da177e4 85
5aba4f8e 86module_param_array(index, int, NULL, 0444);
1da177e4 87MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 88module_param_array(id, charp, NULL, 0444);
1da177e4 89MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 90module_param_array(enable, bool, NULL, 0444);
91MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
92module_param_array(model, charp, NULL, 0444);
1da177e4 93MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 94module_param_array(position_fix, int, NULL, 0444);
4cb36310 95MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 96 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 97module_param_array(bdl_pos_adj, int, NULL, 0644);
98MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 99module_param_array(probe_mask, int, NULL, 0444);
606ad75f 100MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 101module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 102MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 103module_param_array(jackpoll_ms, int, NULL, 0444);
104MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 105module_param(single_cmd, bool, 0444);
d01ce99f
TI		 106MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
107 "(for debugging only).");
ac9ef6cf 108module_param(enable_msi, bint, 0444);
134a11f0 109MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 110#ifdef CONFIG_SND_HDA_PATCH_LOADER
111module_param_array(patch, charp, NULL, 0444);
112MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
113#endif
2dca0bba 114#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 115module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 116MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 117 "(0=off, 1=on) (default=1).");
2dca0bba 118#endif
606ad75f 119
83012a7c 120#ifdef CONFIG_PM
65fcd41d
TI		 121static int param_set_xint(const char *val, const struct kernel_param *kp);
122static struct kernel_param_ops param_ops_xint = {
123 .set = param_set_xint,
124 .get = param_get_int,
125};
126#define param_check_xint param_check_int
127
fee2fba3 128static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 129module_param(power_save, xint, 0644);
fee2fba3
TI		 130MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
131 "(in second, 0 = disable).");
1da177e4 132
dee1b66c
TI		 133/* reset the HD-audio controller in power save mode.
134 * this may give more power-saving, but will take longer time to
135 * wake up.
136 */
a67ff6a5 137static bool power_save_controller = 1;
dee1b66c
TI		 138module_param(power_save_controller, bool, 0644);
139MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
83012a7c 140#endif /* CONFIG_PM */
dee1b66c 141
7bfe059e
TI		 142static int align_buffer_size = -1;
143module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 144MODULE_PARM_DESC(align_buffer_size,
145 "Force buffer and period sizes to be multiple of 128 bytes.");
146
27fe48d9
TI		 147#ifdef CONFIG_X86
148static bool hda_snoop = true;
149module_param_named(snoop, hda_snoop, bool, 0444);
150MODULE_PARM_DESC(snoop, "Enable/disable snooping");
151#define azx_snoop(chip) (chip)->snoop
152#else
153#define hda_snoop true
154#define azx_snoop(chip) true
155#endif
156
157
1da177e4
LT		 158MODULE_LICENSE("GPL");
159MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
160 "{Intel, ICH6M},"
2f1b3818 161 "{Intel, ICH7},"
f5d40b30 162 "{Intel, ESB2},"
d2981393 163 "{Intel, ICH8},"
f9cc8a8b 164 "{Intel, ICH9},"
c34f5a04 165 "{Intel, ICH10},"
b29c2360 166 "{Intel, PCH},"
d2f2fcd2 167 "{Intel, CPT},"
d2edeb7c 168 "{Intel, PPT},"
8bc039a1 169 "{Intel, LPT},"
144dad99 170 "{Intel, LPT_LP},"
e926f2c8 171 "{Intel, HPT},"
cea310e8 172 "{Intel, PBG},"
4979bca9 173 "{Intel, SCH},"
fc20a562 174 "{ATI, SB450},"
89be83f8 175 "{ATI, SB600},"
778b6e1b 176 "{ATI, RS600},"
5b15c95f 177 "{ATI, RS690},"
e6db1119
WL		 178 "{ATI, RS780},"
179 "{ATI, R600},"
2797f724
HRK		 180 "{ATI, RV630},"
181 "{ATI, RV610},"
27da1834
WL		 182 "{ATI, RV670},"
183 "{ATI, RV635},"
184 "{ATI, RV620},"
185 "{ATI, RV770},"
fc20a562 186 "{VIA, VT8251},"
47672310 187 "{VIA, VT8237A},"
07e4ca50
TI		 188 "{SiS, SIS966},"
189 "{ULI, M5461}}");
1da177e4
LT		 190MODULE_DESCRIPTION("Intel HDA driver");
191
4abc1cc2
TI		 192#ifdef CONFIG_SND_VERBOSE_PRINTK
193#define SFX /* nop */
194#else
445a51b3 195#define SFX "hda-intel "
4abc1cc2 196#endif
cb53c626 197
a82d51ed
TI		 198#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
199#ifdef CONFIG_SND_HDA_CODEC_HDMI
200#define SUPPORT_VGA_SWITCHEROO
201#endif
202#endif
203
204
1da177e4
LT		 205/*
206 * registers
207 */
208#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 209#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
210#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
211#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
212#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
213#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 214#define ICH6_REG_VMIN 0x02
215#define ICH6_REG_VMAJ 0x03
216#define ICH6_REG_OUTPAY 0x04
217#define ICH6_REG_INPAY 0x06
218#define ICH6_REG_GCTL 0x08
8a933ece 219#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 220#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
221#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 222#define ICH6_REG_WAKEEN 0x0c
223#define ICH6_REG_STATESTS 0x0e
224#define ICH6_REG_GSTS 0x10
b21fadb9 225#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 226#define ICH6_REG_INTCTL 0x20
227#define ICH6_REG_INTSTS 0x24
e5463720 228#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 229#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
230#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 231#define ICH6_REG_CORBLBASE 0x40
232#define ICH6_REG_CORBUBASE 0x44
233#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 234#define ICH6_REG_CORBRP 0x4a
235#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 236#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 237#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
238#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 239#define ICH6_REG_CORBSTS 0x4d
b21fadb9 240#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 241#define ICH6_REG_CORBSIZE 0x4e
242
243#define ICH6_REG_RIRBLBASE 0x50
244#define ICH6_REG_RIRBUBASE 0x54
245#define ICH6_REG_RIRBWP 0x58
b21fadb9 246#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 247#define ICH6_REG_RINTCNT 0x5a
248#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 249#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
250#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
251#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 252#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 253#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
254#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 255#define ICH6_REG_RIRBSIZE 0x5e
256
257#define ICH6_REG_IC 0x60
258#define ICH6_REG_IR 0x64
259#define ICH6_REG_IRS 0x68
260#define ICH6_IRS_VALID (1<<1)
261#define ICH6_IRS_BUSY (1<<0)
262
263#define ICH6_REG_DPLBASE 0x70
264#define ICH6_REG_DPUBASE 0x74
265#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
266
267/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
268enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
269
270/* stream register offsets from stream base */
271#define ICH6_REG_SD_CTL 0x00
272#define ICH6_REG_SD_STS 0x03
273#define ICH6_REG_SD_LPIB 0x04
274#define ICH6_REG_SD_CBL 0x08
275#define ICH6_REG_SD_LVI 0x0c
276#define ICH6_REG_SD_FIFOW 0x0e
277#define ICH6_REG_SD_FIFOSIZE 0x10
278#define ICH6_REG_SD_FORMAT 0x12
279#define ICH6_REG_SD_BDLPL 0x18
280#define ICH6_REG_SD_BDLPU 0x1c
281
282/* PCI space */
283#define ICH6_PCIREG_TCSEL 0x44
284
285/*
286 * other constants
287 */
288
289/* max number of SDs */
07e4ca50 290/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 291#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 292#define ICH6_NUM_PLAYBACK 4
293
294/* ULI has 6 playback and 5 capture */
07e4ca50 295#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 296#define ULI_NUM_PLAYBACK 6
297
778b6e1b 298/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 299#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 300#define ATIHDMI_NUM_PLAYBACK 1
301
f269002e
KY		 302/* TERA has 4 playback and 3 capture */
303#define TERA_NUM_CAPTURE 3
304#define TERA_NUM_PLAYBACK 4
305
07e4ca50
TI		 306/* this number is statically defined for simplicity */
307#define MAX_AZX_DEV 16
308
1da177e4 309/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 310#define BDL_SIZE 4096
311#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
312#define AZX_MAX_FRAG 32
1da177e4
LT		 313/* max buffer size - no h/w limit, you can increase as you like */
314#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 315
316/* RIRB int mask: overrun[2], response[0] */
317#define RIRB_INT_RESPONSE 0x01
318#define RIRB_INT_OVERRUN 0x04
319#define RIRB_INT_MASK 0x05
320
2f5983f2 321/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 322#define AZX_MAX_CODECS 8
323#define AZX_DEFAULT_CODECS 4
deadff16 324#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 325
326/* SD_CTL bits */
327#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
328#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 329#define SD_CTL_STRIPE (3 << 16) /* stripe control */
330#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
331#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 332#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
333#define SD_CTL_STREAM_TAG_SHIFT 20
334
335/* SD_CTL and SD_STS */
336#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
337#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
338#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 339#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
340 SD_INT_COMPLETE)
1da177e4
LT		 341
342/* SD_STS */
343#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
344
345/* INTCTL and INTSTS */
d01ce99f
TI		 346#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
347#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
348#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 349
1da177e4
LT		 350/* below are so far hardcoded - should read registers in future */
351#define ICH6_MAX_CORB_ENTRIES 256
352#define ICH6_MAX_RIRB_ENTRIES 256
353
c74db86b
TI		 354/* position fix mode */
355enum {
0be3b5d3 356 POS_FIX_AUTO,
d2e1c973 357 POS_FIX_LPIB,
0be3b5d3 358 POS_FIX_POSBUF,
4cb36310 359 POS_FIX_VIACOMBO,
a6f2fd55 360 POS_FIX_COMBO,
c74db86b 361};
1da177e4 362
f5d40b30 363/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 364#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
365#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
366
da3fca21
V		 367/* Defines for Nvidia HDA support */
368#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
369#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 370#define NVIDIA_HDA_ISTRM_COH 0x4d
371#define NVIDIA_HDA_OSTRM_COH 0x4c
372#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 373
90a5ad52
TI		 374/* Defines for Intel SCH HDA snoop control */
375#define INTEL_SCH_HDA_DEVC 0x78
376#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
377
0e153474
JC		 378/* Define IN stream 0 FIFO size offset in VIA controller */
379#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
380/* Define VIA HD Audio Device ID*/
381#define VIA_HDAC_DEVICE_ID 0x3288
382
c4da29ca
YL		 383/* HD Audio class code */
384#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 385
1da177e4
LT		 386/*
387 */
388
a98f90fd 389struct azx_dev {
4ce107b9 390 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 391 u32 *posbuf; /* position buffer pointer */
1da177e4 392
d01ce99f 393 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 394 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 395 unsigned int frags; /* number for period in the play buffer */
396 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 397 unsigned long start_wallclk; /* start + minimum wallclk */
398 unsigned long period_wallclk; /* wallclk for period */
1da177e4 399
d01ce99f 400 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 401
d01ce99f 402 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 403
404 /* pcm support */
d01ce99f
TI		 405 struct snd_pcm_substream *substream; /* assigned substream,
406 * set in PCM open
407 */
408 unsigned int format_val; /* format value to be set in the
409 * controller and the codec
410 */
1da177e4
LT		 411 unsigned char stream_tag; /* assigned stream */
412 unsigned char index; /* stream index */
d5cf9911 413 int assigned_key; /* last device# key assigned to */
1da177e4 414
927fc866
PM		 415 unsigned int opened :1;
416 unsigned int running :1;
675f25d4 417 unsigned int irq_pending :1;
0e153474
JC		 418 /*
419 * For VIA:
420 * A flag to ensure DMA position is 0
421 * when link position is not greater than FIFO size
422 */
423 unsigned int insufficient :1;
27fe48d9 424 unsigned int wc_marked:1;
915bf29e 425 unsigned int no_period_wakeup:1;
5d890f59
PLB		 426
427 struct timecounter azx_tc;
428 struct cyclecounter azx_cc;
1da177e4
LT		 429};
430
431/* CORB/RIRB */
a98f90fd 432struct azx_rb {
1da177e4
LT		 433 u32 *buf; /* CORB/RIRB buffer
434 * Each CORB entry is 4byte, RIRB is 8byte
435 */
436 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
437 /* for RIRB */
438 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 439 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
440 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 441};
442
01b65bfb
TI		 443struct azx_pcm {
444 struct azx *chip;
445 struct snd_pcm *pcm;
446 struct hda_codec *codec;
447 struct hda_pcm_stream *hinfo[2];
448 struct list_head list;
449};
450
a98f90fd
TI		 451struct azx {
452 struct snd_card *card;
1da177e4 453 struct pci_dev *pci;
555e219f 454 int dev_index;
1da177e4 455
07e4ca50
TI		 456 /* chip type specific */
457 int driver_type;
9477c58e 458 unsigned int driver_caps;
07e4ca50
TI		 459 int playback_streams;
460 int playback_index_offset;
461 int capture_streams;
462 int capture_index_offset;
463 int num_streams;
464
1da177e4
LT		 465 /* pci resources */
466 unsigned long addr;
467 void __iomem *remap_addr;
468 int irq;
469
470 /* locks */
471 spinlock_t reg_lock;
62932df8 472 struct mutex open_mutex;
f4c482a4 473 struct completion probe_wait;
1da177e4 474
07e4ca50 475 /* streams (x num_streams) */
a98f90fd 476 struct azx_dev *azx_dev;
1da177e4
LT		 477
478 /* PCM */
01b65bfb 479 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 480
481 /* HD codec */
482 unsigned short codec_mask;
f1eaaeec 483 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 484 struct hda_bus *bus;
2dca0bba 485 unsigned int beep_mode;
1da177e4
LT		 486
487 /* CORB/RIRB */
a98f90fd
TI		 488 struct azx_rb corb;
489 struct azx_rb rirb;
1da177e4 490
4ce107b9 491 /* CORB/RIRB and position buffers */
1da177e4
LT		 492 struct snd_dma_buffer rb;
493 struct snd_dma_buffer posbuf;
c74db86b 494
4918cdab
TI		 495#ifdef CONFIG_SND_HDA_PATCH_LOADER
496 const struct firmware *fw;
497#endif
498
c74db86b 499 /* flags */
beaffc39 500 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 501 int poll_count;
cb53c626 502 unsigned int running :1;
927fc866
PM		 503 unsigned int initialized :1;
504 unsigned int single_cmd :1;
505 unsigned int polling_mode :1;
68e7fffc 506 unsigned int msi :1;
a6a950a8 507 unsigned int irq_pending_warned :1;
6ce4a3bc 508 unsigned int probing :1; /* codec probing phase */
27fe48d9 509 unsigned int snoop:1;
52409aa6 510 unsigned int align_buffer_size:1;
a82d51ed
TI		 511 unsigned int region_requested:1;
512
513 /* VGA-switcheroo setup */
514 unsigned int use_vga_switcheroo:1;
128960a9 515 unsigned int vga_switcheroo_registered:1;
a82d51ed
TI		 516 unsigned int init_failed:1; /* delayed init failed */
517 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 518
519 /* for debugging */
feb27340 520 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 521
522 /* for pending irqs */
523 struct work_struct irq_pending_work;
0cbf0098
TI		 524
525 /* reboot notifier (for mysterious hangup problem at power-down) */
526 struct notifier_block reboot_notifier;
65fcd41d
TI		 527
528 /* card list (for power_save trigger) */
529 struct list_head list;
1da177e4
LT		 530};
531
1a8506d4
TI		 532#define CREATE_TRACE_POINTS
533#include "hda_intel_trace.h"
534
07e4ca50
TI		 535/* driver types */
536enum {
537 AZX_DRIVER_ICH,
32679f95 538 AZX_DRIVER_PCH,
4979bca9 539 AZX_DRIVER_SCH,
07e4ca50 540 AZX_DRIVER_ATI,
778b6e1b 541 AZX_DRIVER_ATIHDMI,
1815b34a 542 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 543 AZX_DRIVER_VIA,
544 AZX_DRIVER_SIS,
545 AZX_DRIVER_ULI,
da3fca21 546 AZX_DRIVER_NVIDIA,
f269002e 547 AZX_DRIVER_TERA,
14d34f16 548 AZX_DRIVER_CTX,
5ae763b1 549 AZX_DRIVER_CTHDA,
c4da29ca 550 AZX_DRIVER_GENERIC,
2f5983f2 551 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 552};
553
9477c58e
TI		 554/* driver quirks (capabilities) */
555/* bits 0-7 are used for indicating driver type */
556#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
557#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
558#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
559#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
560#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
561#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
562#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
563#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
564#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
565#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
566#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
567#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 568#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 569#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 570#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 571#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
90accc58 572#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
2ea3c6a2
TI		 573#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
574
575/* quirks for Intel PCH */
576#define AZX_DCAPS_INTEL_PCH \
577 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
578 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME)
9477c58e
TI		 579
580/* quirks for ATI SB / AMD Hudson */
581#define AZX_DCAPS_PRESET_ATI_SB \
582 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
583 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
584
585/* quirks for ATI/AMD HDMI */
586#define AZX_DCAPS_PRESET_ATI_HDMI \
587 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
588
589/* quirks for Nvidia */
590#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e
TI		 591 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
592 AZX_DCAPS_ALIGN_BUFSIZE)
9477c58e 593
5ae763b1
TI		 594#define AZX_DCAPS_PRESET_CTHDA \
595 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
596
a82d51ed
TI		 597/*
598 * VGA-switcher support
599 */
600#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 601#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
602#else
603#define use_vga_switcheroo(chip) 0
604#endif
605
48c8b0eb 606static char *driver_short_names[] = {
07e4ca50 607 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 608 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 609 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 610 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 611 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 612 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 613 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
614 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 615 [AZX_DRIVER_ULI] = "HDA ULI M5461",
616 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 617 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 618 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 619 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 620 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 621};
622
1da177e4
LT		 623/*
624 * macros for easy use
625 */
626#define azx_writel(chip,reg,value) \
627 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
628#define azx_readl(chip,reg) \
629 readl((chip)->remap_addr + ICH6_REG_##reg)
630#define azx_writew(chip,reg,value) \
631 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
632#define azx_readw(chip,reg) \
633 readw((chip)->remap_addr + ICH6_REG_##reg)
634#define azx_writeb(chip,reg,value) \
635 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
636#define azx_readb(chip,reg) \
637 readb((chip)->remap_addr + ICH6_REG_##reg)
638
639#define azx_sd_writel(dev,reg,value) \
640 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
641#define azx_sd_readl(dev,reg) \
642 readl((dev)->sd_addr + ICH6_REG_##reg)
643#define azx_sd_writew(dev,reg,value) \
644 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
645#define azx_sd_readw(dev,reg) \
646 readw((dev)->sd_addr + ICH6_REG_##reg)
647#define azx_sd_writeb(dev,reg,value) \
648 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
649#define azx_sd_readb(dev,reg) \
650 readb((dev)->sd_addr + ICH6_REG_##reg)
651
652/* for pcm support */
a98f90fd 653#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 654
27fe48d9
TI		 655#ifdef CONFIG_X86
656static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
657{
658 if (azx_snoop(chip))
659 return;
660 if (addr && size) {
661 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
662 if (on)
663 set_memory_wc((unsigned long)addr, pages);
664 else
665 set_memory_wb((unsigned long)addr, pages);
666 }
667}
668
669static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
670 bool on)
671{
672 __mark_pages_wc(chip, buf->area, buf->bytes, on);
673}
674static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
675 struct snd_pcm_runtime *runtime, bool on)
676{
677 if (azx_dev->wc_marked != on) {
678 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
679 azx_dev->wc_marked = on;
680 }
681}
682#else
683/* NOP for other archs */
684static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
685 bool on)
686{
687}
688static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
689 struct snd_pcm_runtime *runtime, bool on)
690{
691}
692#endif
693
68e7fffc 694static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 695static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 696/*
697 * Interface for HD codec
698 */
699
1da177e4
LT		 700/*
701 * CORB / RIRB interface
702 */
a98f90fd 703static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 704{
705 int err;
706
707 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 708 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
709 snd_dma_pci_data(chip->pci),
1da177e4
LT		 710 PAGE_SIZE, &chip->rb);
711 if (err < 0) {
445a51b3 712 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
1da177e4
LT		 713 return err;
714 }
27fe48d9 715 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 716 return 0;
717}
718
a98f90fd 719static void azx_init_cmd_io(struct azx *chip)
1da177e4 720{
cdb1fbf2 721 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 722 /* CORB set up */
723 chip->corb.addr = chip->rb.addr;
724 chip->corb.buf = (u32 *)chip->rb.area;
725 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 726 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 727
07e4ca50
TI		 728 /* set the corb size to 256 entries (ULI requires explicitly) */
729 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 730 /* set the corb write pointer to 0 */
731 azx_writew(chip, CORBWP, 0);
732 /* reset the corb hw read pointer */
b21fadb9 733 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 734 /* enable corb dma */
b21fadb9 735 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 736
737 /* RIRB set up */
738 chip->rirb.addr = chip->rb.addr + 2048;
739 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 740 chip->rirb.wp = chip->rirb.rp = 0;
741 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 742 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 743 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 744
07e4ca50
TI		 745 /* set the rirb size to 256 entries (ULI requires explicitly) */
746 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 747 /* reset the rirb hw write pointer */
b21fadb9 748 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 749 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 750 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 751 azx_writew(chip, RINTCNT, 0xc0);
752 else
753 azx_writew(chip, RINTCNT, 1);
1da177e4 754 /* enable rirb dma and response irq */
1da177e4 755 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 756 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 757}
758
a98f90fd 759static void azx_free_cmd_io(struct azx *chip)
1da177e4 760{
cdb1fbf2 761 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 762 /* disable ringbuffer DMAs */
763 azx_writeb(chip, RIRBCTL, 0);
764 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 765 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 766}
767
deadff16
WF		 768static unsigned int azx_command_addr(u32 cmd)
769{
770 unsigned int addr = cmd >> 28;
771
772 if (addr >= AZX_MAX_CODECS) {
773 snd_BUG();
774 addr = 0;
775 }
776
777 return addr;
778}
779
780static unsigned int azx_response_addr(u32 res)
781{
782 unsigned int addr = res & 0xf;
783
784 if (addr >= AZX_MAX_CODECS) {
785 snd_BUG();
786 addr = 0;
787 }
788
789 return addr;
1da177e4
LT		 790}
791
792/* send a command */
33fa35ed 793static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 794{
33fa35ed 795 struct azx *chip = bus->private_data;
deadff16 796 unsigned int addr = azx_command_addr(val);
1da177e4 797 unsigned int wp;
1da177e4 798
c32649fe
WF		 799 spin_lock_irq(&chip->reg_lock);
800
1da177e4
LT		 801 /* add command to corb */
802 wp = azx_readb(chip, CORBWP);
803 wp++;
804 wp %= ICH6_MAX_CORB_ENTRIES;
805
deadff16 806 chip->rirb.cmds[addr]++;
1da177e4
LT		 807 chip->corb.buf[wp] = cpu_to_le32(val);
808 azx_writel(chip, CORBWP, wp);
c32649fe 809
1da177e4
LT		 810 spin_unlock_irq(&chip->reg_lock);
811
812 return 0;
813}
814
815#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
816
817/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 818static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 819{
820 unsigned int rp, wp;
deadff16 821 unsigned int addr;
1da177e4
LT		 822 u32 res, res_ex;
823
824 wp = azx_readb(chip, RIRBWP);
825 if (wp == chip->rirb.wp)
826 return;
827 chip->rirb.wp = wp;
deadff16 828
1da177e4
LT		 829 while (chip->rirb.rp != wp) {
830 chip->rirb.rp++;
831 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
832
833 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
834 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
835 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 836 addr = azx_response_addr(res_ex);
1da177e4
LT		 837 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
838 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 839 else if (chip->rirb.cmds[addr]) {
840 chip->rirb.res[addr] = res;
2add9b92 841 smp_wmb();
deadff16 842 chip->rirb.cmds[addr]--;
e310bb06 843 } else
9e3d352b 844 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
e310bb06 845 "last cmd=%#08x\n",
9e3d352b 846 pci_name(chip->pci),
e310bb06
WF		 847 res, res_ex,
848 chip->last_cmd[addr]);
1da177e4
LT		 849 }
850}
851
852/* receive a response */
deadff16
WF		 853static unsigned int azx_rirb_get_response(struct hda_bus *bus,
854 unsigned int addr)
1da177e4 855{
33fa35ed 856 struct azx *chip = bus->private_data;
5c79b1f8 857 unsigned long timeout;
32cf4023 858 unsigned long loopcounter;
1eb6dc7d 859 int do_poll = 0;
1da177e4 860
5c79b1f8
TI		 861 again:
862 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 863
864 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 865 if (chip->polling_mode || do_poll) {
e96224ae
TI		 866 spin_lock_irq(&chip->reg_lock);
867 azx_update_rirb(chip);
868 spin_unlock_irq(&chip->reg_lock);
869 }
deadff16 870 if (!chip->rirb.cmds[addr]) {
2add9b92 871 smp_rmb();
b613291f 872 bus->rirb_error = 0;
1eb6dc7d
ML		 873
874 if (!do_poll)
875 chip->poll_count = 0;
deadff16 876 return chip->rirb.res[addr]; /* the last value */
2add9b92 877 }
28a0d9df
TI		 878 if (time_after(jiffies, timeout))
879 break;
32cf4023 880 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 881 msleep(2); /* temporary workaround */
882 else {
883 udelay(10);
884 cond_resched();
885 }
28a0d9df 886 }
5c79b1f8 887
1eb6dc7d 888 if (!chip->polling_mode && chip->poll_count < 2) {
445a51b3 889 snd_printdd(SFX "%s: azx_get_response timeout, "
1eb6dc7d 890 "polling the codec once: last cmd=0x%08x\n",
445a51b3 891 pci_name(chip->pci), chip->last_cmd[addr]);
1eb6dc7d
ML		 892 do_poll = 1;
893 chip->poll_count++;
894 goto again;
895 }
896
897
23c4a881 898 if (!chip->polling_mode) {
445a51b3 899 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
23c4a881 900 "switching to polling mode: last cmd=0x%08x\n",
445a51b3 901 pci_name(chip->pci), chip->last_cmd[addr]);
23c4a881
TI		 902 chip->polling_mode = 1;
903 goto again;
904 }
905
68e7fffc 906 if (chip->msi) {
445a51b3 907 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
feb27340 908 "disabling MSI: last cmd=0x%08x\n",
445a51b3 909 pci_name(chip->pci), chip->last_cmd[addr]);
68e7fffc
TI		 910 free_irq(chip->irq, chip);
911 chip->irq = -1;
912 pci_disable_msi(chip->pci);
913 chip->msi = 0;
b613291f
TI		 914 if (azx_acquire_irq(chip, 1) < 0) {
915 bus->rirb_error = 1;
68e7fffc 916 return -1;
b613291f 917 }
68e7fffc
TI		 918 goto again;
919 }
920
6ce4a3bc
TI		 921 if (chip->probing) {
922 /* If this critical timeout happens during the codec probing
923 * phase, this is likely an access to a non-existing codec
924 * slot. Better to return an error and reset the system.
925 */
926 return -1;
927 }
928
8dd78330
TI		 929 /* a fatal communication error; need either to reset or to fallback
930 * to the single_cmd mode
931 */
b613291f 932 bus->rirb_error = 1;
b20f3b83 933 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 934 bus->response_reset = 1;
935 return -1; /* give a chance to retry */
936 }
937
938 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
939 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 940 chip->last_cmd[addr]);
8dd78330
TI		 941 chip->single_cmd = 1;
942 bus->response_reset = 0;
1a696978 943 /* release CORB/RIRB */
4fcd3920 944 azx_free_cmd_io(chip);
1a696978
TI		 945 /* disable unsolicited responses */
946 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 947 return -1;
1da177e4
LT		 948}
949
1da177e4
LT		 950/*
951 * Use the single immediate command instead of CORB/RIRB for simplicity
952 *
953 * Note: according to Intel, this is not preferred use. The command was
954 * intended for the BIOS only, and may get confused with unsolicited
955 * responses. So, we shouldn't use it for normal operation from the
956 * driver.
957 * I left the codes, however, for debugging/testing purposes.
958 */
959
b05a7d4f 960/* receive a response */
deadff16 961static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 962{
963 int timeout = 50;
964
965 while (timeout--) {
966 /* check IRV busy bit */
967 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
968 /* reuse rirb.res as the response return value */
deadff16 969 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 970 return 0;
971 }
972 udelay(1);
973 }
974 if (printk_ratelimit())
445a51b3
DB		 975 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
976 pci_name(chip->pci), azx_readw(chip, IRS));
deadff16 977 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 978 return -EIO;
979}
980
1da177e4 981/* send a command */
33fa35ed 982static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 983{
33fa35ed 984 struct azx *chip = bus->private_data;
deadff16 985 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 986 int timeout = 50;
987
8dd78330 988 bus->rirb_error = 0;
1da177e4
LT		 989 while (timeout--) {
990 /* check ICB busy bit */
d01ce99f 991 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 992 /* Clear IRV valid bit */
d01ce99f
TI		 993 azx_writew(chip, IRS, azx_readw(chip, IRS) |
994 ICH6_IRS_VALID);
1da177e4 995 azx_writel(chip, IC, val);
d01ce99f
TI		 996 azx_writew(chip, IRS, azx_readw(chip, IRS) |
997 ICH6_IRS_BUSY);
deadff16 998 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 999 }
1000 udelay(1);
1001 }
1cfd52bc 1002 if (printk_ratelimit())
445a51b3
DB		 1003 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1004 pci_name(chip->pci), azx_readw(chip, IRS), val);
1da177e4
LT		 1005 return -EIO;
1006}
1007
1008/* receive a response */
deadff16
WF		 1009static unsigned int azx_single_get_response(struct hda_bus *bus,
1010 unsigned int addr)
1da177e4 1011{
33fa35ed 1012 struct azx *chip = bus->private_data;
deadff16 1013 return chip->rirb.res[addr];
1da177e4
LT		 1014}
1015
111d3af5
TI		 1016/*
1017 * The below are the main callbacks from hda_codec.
1018 *
1019 * They are just the skeleton to call sub-callbacks according to the
1020 * current setting of chip->single_cmd.
1021 */
1022
1023/* send a command */
33fa35ed 1024static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 1025{
33fa35ed 1026 struct azx *chip = bus->private_data;
43bbb6cc 1027
a82d51ed
TI		 1028 if (chip->disabled)
1029 return 0;
feb27340 1030 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 1031 if (chip->single_cmd)
33fa35ed 1032 return azx_single_send_cmd(bus, val);
111d3af5 1033 else
33fa35ed 1034 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 1035}
1036
1037/* get a response */
deadff16
WF		 1038static unsigned int azx_get_response(struct hda_bus *bus,
1039 unsigned int addr)
111d3af5 1040{
33fa35ed 1041 struct azx *chip = bus->private_data;
a82d51ed
TI		 1042 if (chip->disabled)
1043 return 0;
111d3af5 1044 if (chip->single_cmd)
deadff16 1045 return azx_single_get_response(bus, addr);
111d3af5 1046 else
deadff16 1047 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1048}
1049
83012a7c 1050#ifdef CONFIG_PM
68467f51 1051static void azx_power_notify(struct hda_bus *bus, bool power_up);
cb53c626 1052#endif
111d3af5 1053
1da177e4 1054/* reset codec link */
cd508fe5 1055static int azx_reset(struct azx *chip, int full_reset)
1da177e4 1056{
fa348da5 1057 unsigned long timeout;
1da177e4 1058
cd508fe5
JK		 1059 if (!full_reset)
1060 goto __skip;
1061
e8a7f136
DT		 1062 /* clear STATESTS */
1063 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1064
1da177e4
LT		 1065 /* reset controller */
1066 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1067
fa348da5
ML		 1068 timeout = jiffies + msecs_to_jiffies(100);
1069 while (azx_readb(chip, GCTL) &&
1070 time_before(jiffies, timeout))
1071 usleep_range(500, 1000);
1da177e4
LT		 1072
1073 /* delay for >= 100us for codec PLL to settle per spec
1074 * Rev 0.9 section 5.5.1
1075 */
fa348da5 1076 usleep_range(500, 1000);
1da177e4
LT		 1077
1078 /* Bring controller out of reset */
1079 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1080
fa348da5
ML		 1081 timeout = jiffies + msecs_to_jiffies(100);
1082 while (!azx_readb(chip, GCTL) &&
1083 time_before(jiffies, timeout))
1084 usleep_range(500, 1000);
1da177e4 1085
927fc866 1086 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
fa348da5 1087 usleep_range(1000, 1200);
1da177e4 1088
cd508fe5 1089 __skip:
1da177e4 1090 /* check to see if controller is ready */
927fc866 1091 if (!azx_readb(chip, GCTL)) {
445a51b3 1092 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1da177e4
LT		 1093 return -EBUSY;
1094 }
1095
41e2fce4 1096 /* Accept unsolicited responses */
1a696978
TI		 1097 if (!chip->single_cmd)
1098 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1099 ICH6_GCTL_UNSOL);
41e2fce4 1100
1da177e4 1101 /* detect codecs */
927fc866 1102 if (!chip->codec_mask) {
1da177e4 1103 chip->codec_mask = azx_readw(chip, STATESTS);
445a51b3 1104 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1da177e4
LT		 1105 }
1106
1107 return 0;
1108}
1109
1110
1111/*
1112 * Lowlevel interface
1113 */
1114
1115/* enable interrupts */
a98f90fd 1116static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1117{
1118 /* enable controller CIE and GIE */
1119 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1120 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1121}
1122
1123/* disable interrupts */
a98f90fd 1124static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1125{
1126 int i;
1127
1128 /* disable interrupts in stream descriptor */
07e4ca50 1129 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1130 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1131 azx_sd_writeb(azx_dev, SD_CTL,
1132 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1133 }
1134
1135 /* disable SIE for all streams */
1136 azx_writeb(chip, INTCTL, 0);
1137
1138 /* disable controller CIE and GIE */
1139 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1140 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1141}
1142
1143/* clear interrupts */
a98f90fd 1144static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1145{
1146 int i;
1147
1148 /* clear stream status */
07e4ca50 1149 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1150 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1151 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1152 }
1153
1154 /* clear STATESTS */
1155 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1156
1157 /* clear rirb status */
1158 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1159
1160 /* clear int status */
1161 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1162}
1163
1164/* start a stream */
a98f90fd 1165static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1166{
0e153474
JC		 1167 /*
1168 * Before stream start, initialize parameter
1169 */
1170 azx_dev->insufficient = 1;
1171
1da177e4 1172 /* enable SIE */
ccc5df05
WN		 1173 azx_writel(chip, INTCTL,
1174 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1175 /* set DMA start and interrupt mask */
1176 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1177 SD_CTL_DMA_START | SD_INT_MASK);
1178}
1179
1dddab40
TI		 1180/* stop DMA */
1181static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1182{
1da177e4
LT		 1183 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1184 ~(SD_CTL_DMA_START | SD_INT_MASK));
1185 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1186}
1187
1188/* stop a stream */
1189static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1190{
1191 azx_stream_clear(chip, azx_dev);
1da177e4 1192 /* disable SIE */
ccc5df05
WN		 1193 azx_writel(chip, INTCTL,
1194 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1195}
1196
1197
1198/*
cb53c626 1199 * reset and start the controller registers
1da177e4 1200 */
cd508fe5 1201static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1202{
cb53c626
TI		 1203 if (chip->initialized)
1204 return;
1da177e4
LT		 1205
1206 /* reset controller */
cd508fe5 1207 azx_reset(chip, full_reset);
1da177e4
LT		 1208
1209 /* initialize interrupts */
1210 azx_int_clear(chip);
1211 azx_int_enable(chip);
1212
1213 /* initialize the codec command I/O */
1a696978
TI		 1214 if (!chip->single_cmd)
1215 azx_init_cmd_io(chip);
1da177e4 1216
0be3b5d3
TI		 1217 /* program the position buffer */
1218 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1219 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1220
cb53c626
TI		 1221 chip->initialized = 1;
1222}
1223
1224/*
1225 * initialize the PCI registers
1226 */
1227/* update bits in a PCI register byte */
1228static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1229 unsigned char mask, unsigned char val)
1230{
1231 unsigned char data;
1232
1233 pci_read_config_byte(pci, reg, &data);
1234 data &= ~mask;
1235 data |= (val & mask);
1236 pci_write_config_byte(pci, reg, data);
1237}
1238
1239static void azx_init_pci(struct azx *chip)
1240{
1241 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1242 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1243 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1244 * codecs.
1245 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1246 */
46f2cc80 1247 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
445a51b3 1248 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
a09e89f6 1249 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1250 }
cb53c626 1251
9477c58e
TI		 1252 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1253 * we need to enable snoop.
1254 */
1255 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
445a51b3 1256 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626 1257 update_pci_byte(chip->pci,
27fe48d9
TI		 1258 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1259 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1260 }
1261
1262 /* For NVIDIA HDA, enable snoop */
1263 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
445a51b3 1264 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626
TI		 1265 update_pci_byte(chip->pci,
1266 NVIDIA_HDA_TRANSREG_ADDR,
1267 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1268 update_pci_byte(chip->pci,
1269 NVIDIA_HDA_ISTRM_COH,
1270 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1271 update_pci_byte(chip->pci,
1272 NVIDIA_HDA_OSTRM_COH,
1273 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1274 }
1275
1276 /* Enable SCH/PCH snoop if needed */
1277 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1278 unsigned short snoop;
90a5ad52 1279 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1280 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1281 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1282 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1283 if (!azx_snoop(chip))
1284 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1285 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1286 pci_read_config_word(chip->pci,
1287 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1288 }
445a51b3
DB		 1289 snd_printdd(SFX "%s: SCH snoop: %s\n",
1290 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
27fe48d9 1291 ? "Disabled" : "Enabled");
da3fca21 1292 }
1da177e4
LT		 1293}
1294
1295
9ad593f6
TI		 1296static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1297
1da177e4
LT		 1298/*
1299 * interrupt handler
1300 */
7d12e780 1301static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1302{
a98f90fd
TI		 1303 struct azx *chip = dev_id;
1304 struct azx_dev *azx_dev;
1da177e4 1305 u32 status;
9ef04066 1306 u8 sd_status;
fa00e046 1307 int i, ok;
1da177e4 1308
b8dfc462
ML		 1309#ifdef CONFIG_PM_RUNTIME
1310 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1311 return IRQ_NONE;
1312#endif
1313
1da177e4
LT		 1314 spin_lock(&chip->reg_lock);
1315
60911062
DC		 1316 if (chip->disabled) {
1317 spin_unlock(&chip->reg_lock);
a82d51ed 1318 return IRQ_NONE;
60911062 1319 }
a82d51ed 1320
1da177e4
LT		 1321 status = azx_readl(chip, INTSTS);
1322 if (status == 0) {
1323 spin_unlock(&chip->reg_lock);
1324 return IRQ_NONE;
1325 }
1326
07e4ca50 1327 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1328 azx_dev = &chip->azx_dev[i];
1329 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1330 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1331 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1332 if (!azx_dev->substream || !azx_dev->running ||
1333 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1334 continue;
1335 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1336 ok = azx_position_ok(chip, azx_dev);
1337 if (ok == 1) {
9ad593f6 1338 azx_dev->irq_pending = 0;
1da177e4
LT		 1339 spin_unlock(&chip->reg_lock);
1340 snd_pcm_period_elapsed(azx_dev->substream);
1341 spin_lock(&chip->reg_lock);
fa00e046 1342 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1343 /* bogus IRQ, process it later */
1344 azx_dev->irq_pending = 1;
6acaed38
TI		 1345 queue_work(chip->bus->workq,
1346 &chip->irq_pending_work);
1da177e4
LT		 1347 }
1348 }
1349 }
1350
1351 /* clear rirb int */
1352 status = azx_readb(chip, RIRBSTS);
1353 if (status & RIRB_INT_MASK) {
14d34f16 1354 if (status & RIRB_INT_RESPONSE) {
9477c58e 1355 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1356 udelay(80);
1da177e4 1357 azx_update_rirb(chip);
14d34f16 1358 }
1da177e4
LT		 1359 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1360 }
1361
1362#if 0
1363 /* clear state status int */
1364 if (azx_readb(chip, STATESTS) & 0x04)
1365 azx_writeb(chip, STATESTS, 0x04);
1366#endif
1367 spin_unlock(&chip->reg_lock);
1368
1369 return IRQ_HANDLED;
1370}
1371
1372
675f25d4
TI		 1373/*
1374 * set up a BDL entry
1375 */
5ae763b1
TI		 1376static int setup_bdle(struct azx *chip,
1377 struct snd_pcm_substream *substream,
675f25d4
TI		 1378 struct azx_dev *azx_dev, u32 **bdlp,
1379 int ofs, int size, int with_ioc)
1380{
675f25d4
TI		 1381 u32 *bdl = *bdlp;
1382
1383 while (size > 0) {
1384 dma_addr_t addr;
1385 int chunk;
1386
1387 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1388 return -EINVAL;
1389
77a23f26 1390 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1391 /* program the address field of the BDL entry */
1392 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1393 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1394 /* program the size field of the BDL entry */
fc4abee8 1395 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
5ae763b1
TI		 1396 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1397 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1398 u32 remain = 0x1000 - (ofs & 0xfff);
1399 if (chunk > remain)
1400 chunk = remain;
1401 }
675f25d4
TI		 1402 bdl[2] = cpu_to_le32(chunk);
1403 /* program the IOC to enable interrupt
1404 * only when the whole fragment is processed
1405 */
1406 size -= chunk;
1407 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1408 bdl += 4;
1409 azx_dev->frags++;
1410 ofs += chunk;
1411 }
1412 *bdlp = bdl;
1413 return ofs;
1414}
1415
1da177e4
LT		 1416/*
1417 * set up BDL entries
1418 */
555e219f
TI		 1419static int azx_setup_periods(struct azx *chip,
1420 struct snd_pcm_substream *substream,
4ce107b9 1421 struct azx_dev *azx_dev)
1da177e4 1422{
4ce107b9
TI		 1423 u32 *bdl;
1424 int i, ofs, periods, period_bytes;
555e219f 1425 int pos_adj;
1da177e4
LT		 1426
1427 /* reset BDL address */
1428 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1429 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1430
97b71c94 1431 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1432 periods = azx_dev->bufsize / period_bytes;
1433
1da177e4 1434 /* program the initial BDL entries */
4ce107b9
TI		 1435 bdl = (u32 *)azx_dev->bdl.area;
1436 ofs = 0;
1437 azx_dev->frags = 0;
555e219f 1438 pos_adj = bdl_pos_adj[chip->dev_index];
915bf29e 1439 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
675f25d4 1440 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1441 int pos_align = pos_adj;
555e219f 1442 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1443 if (!pos_adj)
e785d3d8
TI		 1444 pos_adj = pos_align;
1445 else
1446 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1447 pos_align;
675f25d4
TI		 1448 pos_adj = frames_to_bytes(runtime, pos_adj);
1449 if (pos_adj >= period_bytes) {
445a51b3
DB		 1450 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1451 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1452 pos_adj = 0;
1453 } else {
5ae763b1 1454 ofs = setup_bdle(chip, substream, azx_dev,
915bf29e 1455 &bdl, ofs, pos_adj, true);
675f25d4
TI		 1456 if (ofs < 0)
1457 goto error;
4ce107b9 1458 }
555e219f
TI		 1459 } else
1460 pos_adj = 0;
675f25d4
TI		 1461 for (i = 0; i < periods; i++) {
1462 if (i == periods - 1 && pos_adj)
5ae763b1 1463 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
675f25d4
TI		 1464 period_bytes - pos_adj, 0);
1465 else
5ae763b1 1466 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
7bb8fb70 1467 period_bytes,
915bf29e 1468 !azx_dev->no_period_wakeup);
675f25d4
TI		 1469 if (ofs < 0)
1470 goto error;
1da177e4 1471 }
4ce107b9 1472 return 0;
675f25d4
TI		 1473
1474 error:
445a51b3
DB		 1475 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1476 pci_name(chip->pci), azx_dev->bufsize, period_bytes);
675f25d4 1477 return -EINVAL;
1da177e4
LT		 1478}
1479
1dddab40
TI		 1480/* reset stream */
1481static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1482{
1483 unsigned char val;
1484 int timeout;
1485
1dddab40
TI		 1486 azx_stream_clear(chip, azx_dev);
1487
d01ce99f
TI		 1488 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1489 SD_CTL_STREAM_RESET);
1da177e4
LT		 1490 udelay(3);
1491 timeout = 300;
1492 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1493 --timeout)
1494 ;
1495 val &= ~SD_CTL_STREAM_RESET;
1496 azx_sd_writeb(azx_dev, SD_CTL, val);
1497 udelay(3);
1498
1499 timeout = 300;
1500 /* waiting for hardware to report that the stream is out of reset */
1501 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1502 --timeout)
1503 ;
fa00e046
JK		 1504
1505 /* reset first position - may not be synced with hw at this time */
1506 *azx_dev->posbuf = 0;
1dddab40 1507}
1da177e4 1508
1dddab40
TI		 1509/*
1510 * set up the SD for streaming
1511 */
1512static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1513{
27fe48d9 1514 unsigned int val;
1dddab40
TI		 1515 /* make sure the run bit is zero for SD */
1516 azx_stream_clear(chip, azx_dev);
1da177e4 1517 /* program the stream_tag */
27fe48d9
TI		 1518 val = azx_sd_readl(azx_dev, SD_CTL);
1519 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1520 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1521 if (!azx_snoop(chip))
1522 val |= SD_CTL_TRAFFIC_PRIO;
1523 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1524
1525 /* program the length of samples in cyclic buffer */
1526 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1527
1528 /* program the stream format */
1529 /* this value needs to be the same as the one programmed */
1530 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1531
1532 /* program the stream LVI (last valid index) of the BDL */
1533 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1534
1535 /* program the BDL address */
1536 /* lower BDL address */
4ce107b9 1537 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1538 /* upper BDL address */
766979e0 1539 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1540
0be3b5d3 1541 /* enable the position buffer */
4cb36310
DH		 1542 if (chip->position_fix[0] != POS_FIX_LPIB ||
1543 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1544 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1545 azx_writel(chip, DPLBASE,
1546 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1547 }
c74db86b 1548
1da177e4 1549 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1550 azx_sd_writel(azx_dev, SD_CTL,
1551 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1552
1553 return 0;
1554}
1555
6ce4a3bc
TI		 1556/*
1557 * Probe the given codec address
1558 */
1559static int probe_codec(struct azx *chip, int addr)
1560{
1561 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1562 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1563 unsigned int res;
1564
a678cdee 1565 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1566 chip->probing = 1;
1567 azx_send_cmd(chip->bus, cmd);
deadff16 1568 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1569 chip->probing = 0;
a678cdee 1570 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1571 if (res == -1)
1572 return -EIO;
445a51b3 1573 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
6ce4a3bc
TI		 1574 return 0;
1575}
1576
33fa35ed
TI		 1577static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1578 struct hda_pcm *cpcm);
6ce4a3bc 1579static void azx_stop_chip(struct azx *chip);
1da177e4 1580
8dd78330
TI		 1581static void azx_bus_reset(struct hda_bus *bus)
1582{
1583 struct azx *chip = bus->private_data;
8dd78330
TI		 1584
1585 bus->in_reset = 1;
1586 azx_stop_chip(chip);
cd508fe5 1587 azx_init_chip(chip, 1);
65f75983 1588#ifdef CONFIG_PM
8dd78330 1589 if (chip->initialized) {
01b65bfb
TI		 1590 struct azx_pcm *p;
1591 list_for_each_entry(p, &chip->pcm_list, list)
1592 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1593 snd_hda_suspend(chip->bus);
1594 snd_hda_resume(chip->bus);
1595 }
65f75983 1596#endif
8dd78330
TI		 1597 bus->in_reset = 0;
1598}
1599
26a6cb6c
DH		 1600static int get_jackpoll_interval(struct azx *chip)
1601{
1602 int i = jackpoll_ms[chip->dev_index];
1603 unsigned int j;
1604 if (i == 0)
1605 return 0;
1606 if (i < 50 || i > 60000)
1607 j = 0;
1608 else
1609 j = msecs_to_jiffies(i);
1610 if (j == 0)
1611 snd_printk(KERN_WARNING SFX
1612 "jackpoll_ms value out of range: %d\n", i);
1613 return j;
1614}
1615
1da177e4
LT		 1616/*
1617 * Codec initialization
1618 */
1619
2f5983f2 1620/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
48c8b0eb 1621static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
7445dfc1 1622 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1623 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1624};
1625
48c8b0eb 1626static int azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1627{
1628 struct hda_bus_template bus_temp;
34c25350
TI		 1629 int c, codecs, err;
1630 int max_slots;
1da177e4
LT		 1631
1632 memset(&bus_temp, 0, sizeof(bus_temp));
1633 bus_temp.private_data = chip;
1634 bus_temp.modelname = model;
1635 bus_temp.pci = chip->pci;
111d3af5
TI		 1636 bus_temp.ops.command = azx_send_cmd;
1637 bus_temp.ops.get_response = azx_get_response;
176d5335 1638 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1639 bus_temp.ops.bus_reset = azx_bus_reset;
83012a7c 1640#ifdef CONFIG_PM
11cd41b8 1641 bus_temp.power_save = &power_save;
cb53c626
TI		 1642 bus_temp.ops.pm_notify = azx_power_notify;
1643#endif
1da177e4 1644
d01ce99f
TI		 1645 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1646 if (err < 0)
1da177e4
LT		 1647 return err;
1648
9477c58e 1649 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
445a51b3 1650 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
dc9c8e21 1651 chip->bus->needs_damn_long_delay = 1;
9477c58e 1652 }
dc9c8e21 1653
34c25350 1654 codecs = 0;
2f5983f2
TI		 1655 max_slots = azx_max_codecs[chip->driver_type];
1656 if (!max_slots)
7445dfc1 1657 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1658
1659 /* First try to probe all given codec slots */
1660 for (c = 0; c < max_slots; c++) {
f1eaaeec 1661 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1662 if (probe_codec(chip, c) < 0) {
1663 /* Some BIOSen give you wrong codec addresses
1664 * that don't exist
1665 */
4abc1cc2 1666 snd_printk(KERN_WARNING SFX
445a51b3
DB		 1667 "%s: Codec #%d probe error; "
1668 "disabling it...\n", pci_name(chip->pci), c);
6ce4a3bc
TI		 1669 chip->codec_mask &= ~(1 << c);
1670 /* More badly, accessing to a non-existing
1671 * codec often screws up the controller chip,
2448158e 1672 * and disturbs the further communications.
6ce4a3bc
TI		 1673 * Thus if an error occurs during probing,
1674 * better to reset the controller chip to
1675 * get back to the sanity state.
1676 */
1677 azx_stop_chip(chip);
cd508fe5 1678 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1679 }
1680 }
1681 }
1682
d507cd66
TI		 1683 /* AMD chipsets often cause the communication stalls upon certain
1684 * sequence like the pin-detection. It seems that forcing the synced
1685 * access works around the stall. Grrr...
1686 */
9477c58e 1687 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
445a51b3
DB		 1688 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1689 pci_name(chip->pci));
d507cd66
TI		 1690 chip->bus->sync_write = 1;
1691 chip->bus->allow_bus_reset = 1;
1692 }
1693
6ce4a3bc 1694 /* Then create codec instances */
34c25350 1695 for (c = 0; c < max_slots; c++) {
f1eaaeec 1696 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1697 struct hda_codec *codec;
a1e21c90 1698 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1699 if (err < 0)
1700 continue;
26a6cb6c 1701 codec->jackpoll_interval = get_jackpoll_interval(chip);
2dca0bba 1702 codec->beep_mode = chip->beep_mode;
1da177e4 1703 codecs++;
19a982b6
TI		 1704 }
1705 }
1706 if (!codecs) {
445a51b3 1707 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1da177e4
LT		 1708 return -ENXIO;
1709 }
a1e21c90
TI		 1710 return 0;
1711}
1da177e4 1712
a1e21c90 1713/* configure each codec instance */
e23e7a14 1714static int azx_codec_configure(struct azx *chip)
a1e21c90
TI		 1715{
1716 struct hda_codec *codec;
1717 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1718 snd_hda_codec_configure(codec);
1719 }
1da177e4
LT		 1720 return 0;
1721}
1722
1723
1724/*
1725 * PCM support
1726 */
1727
1728/* assign a stream for the PCM */
ef18bede
WF		 1729static inline struct azx_dev *
1730azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1731{
07e4ca50 1732 int dev, i, nums;
ef18bede 1733 struct azx_dev *res = NULL;
d5cf9911
TI		 1734 /* make a non-zero unique key for the substream */
1735 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1736 (substream->stream + 1);
ef18bede
WF		 1737
1738 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1739 dev = chip->playback_index_offset;
1740 nums = chip->playback_streams;
1741 } else {
1742 dev = chip->capture_index_offset;
1743 nums = chip->capture_streams;
1744 }
1745 for (i = 0; i < nums; i++, dev++)
d01ce99f 1746 if (!chip->azx_dev[dev].opened) {
ef18bede 1747 res = &chip->azx_dev[dev];
d5cf9911 1748 if (res->assigned_key == key)
ef18bede 1749 break;
1da177e4 1750 }
ef18bede
WF		 1751 if (res) {
1752 res->opened = 1;
d5cf9911 1753 res->assigned_key = key;
ef18bede
WF		 1754 }
1755 return res;
1da177e4
LT		 1756}
1757
1758/* release the assigned stream */
a98f90fd 1759static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1760{
1761 azx_dev->opened = 0;
1762}
1763
5d890f59
PLB		 1764static cycle_t azx_cc_read(const struct cyclecounter *cc)
1765{
1766 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1767 struct snd_pcm_substream *substream = azx_dev->substream;
1768 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1769 struct azx *chip = apcm->chip;
1770
1771 return azx_readl(chip, WALLCLK);
1772}
1773
1774static void azx_timecounter_init(struct snd_pcm_substream *substream,
1775 bool force, cycle_t last)
1776{
1777 struct azx_dev *azx_dev = get_azx_dev(substream);
1778 struct timecounter *tc = &azx_dev->azx_tc;
1779 struct cyclecounter *cc = &azx_dev->azx_cc;
1780 u64 nsec;
1781
1782 cc->read = azx_cc_read;
1783 cc->mask = CLOCKSOURCE_MASK(32);
1784
1785 /*
1786 * Converting from 24 MHz to ns means applying a 125/3 factor.
1787 * To avoid any saturation issues in intermediate operations,
1788 * the 125 factor is applied first. The division is applied
1789 * last after reading the timecounter value.
1790 * Applying the 1/3 factor as part of the multiplication
1791 * requires at least 20 bits for a decent precision, however
1792 * overflows occur after about 4 hours or less, not a option.
1793 */
1794
1795 cc->mult = 125; /* saturation after 195 years */
1796 cc->shift = 0;
1797
1798 nsec = 0; /* audio time is elapsed time since trigger */
1799 timecounter_init(tc, cc, nsec);
1800 if (force)
1801 /*
1802 * force timecounter to use predefined value,
1803 * used for synchronized starts
1804 */
1805 tc->cycle_last = last;
1806}
1807
1808static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1809 struct timespec *ts)
1810{
1811 struct azx_dev *azx_dev = get_azx_dev(substream);
1812 u64 nsec;
1813
1814 nsec = timecounter_read(&azx_dev->azx_tc);
1815 nsec = div_u64(nsec, 3); /* can be optimized */
1816
1817 *ts = ns_to_timespec(nsec);
1818
1819 return 0;
1820}
1821
a98f90fd 1822static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1823 .info = (SNDRV_PCM_INFO_MMAP |
1824 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1825 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1826 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1827 /* No full-resume yet implemented */
1828 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1829 SNDRV_PCM_INFO_PAUSE |
7bb8fb70 1830 SNDRV_PCM_INFO_SYNC_START |
5d890f59 1831 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
7bb8fb70 1832 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1833 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1834 .rates = SNDRV_PCM_RATE_48000,
1835 .rate_min = 48000,
1836 .rate_max = 48000,
1837 .channels_min = 2,
1838 .channels_max = 2,
1839 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1840 .period_bytes_min = 128,
1841 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1842 .periods_min = 2,
1843 .periods_max = AZX_MAX_FRAG,
1844 .fifo_size = 0,
1845};
1846
a98f90fd 1847static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1848{
1849 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1850 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1851 struct azx *chip = apcm->chip;
1852 struct azx_dev *azx_dev;
1853 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1854 unsigned long flags;
1855 int err;
2ae66c26 1856 int buff_step;
1da177e4 1857
62932df8 1858 mutex_lock(&chip->open_mutex);
ef18bede 1859 azx_dev = azx_assign_device(chip, substream);
1da177e4 1860 if (azx_dev == NULL) {
62932df8 1861 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1862 return -EBUSY;
1863 }
1864 runtime->hw = azx_pcm_hw;
1865 runtime->hw.channels_min = hinfo->channels_min;
1866 runtime->hw.channels_max = hinfo->channels_max;
1867 runtime->hw.formats = hinfo->formats;
1868 runtime->hw.rates = hinfo->rates;
1869 snd_pcm_limit_hw_rates(runtime);
1870 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5d890f59
PLB		 1871
1872 /* avoid wrap-around with wall-clock */
1873 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1874 20,
1875 178000000);
1876
52409aa6 1877 if (chip->align_buffer_size)
2ae66c26
PLB		 1878 /* constrain buffer sizes to be multiple of 128
1879 bytes. This is more efficient in terms of memory
1880 access but isn't required by the HDA spec and
1881 prevents users from specifying exact period/buffer
1882 sizes. For example for 44.1kHz, a period size set
1883 to 20ms will be rounded to 19.59ms. */
1884 buff_step = 128;
1885 else
1886 /* Don't enforce steps on buffer sizes, still need to
1887 be multiple of 4 bytes (HDA spec). Tested on Intel
1888 HDA controllers, may not work on all devices where
1889 option needs to be disabled */
1890 buff_step = 4;
1891
5f1545bc 1892 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 1893 buff_step);
5f1545bc 1894 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 1895 buff_step);
b4a91cf0 1896 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 1897 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1898 if (err < 0) {
1da177e4 1899 azx_release_device(azx_dev);
cb53c626 1900 snd_hda_power_down(apcm->codec);
62932df8 1901 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1902 return err;
1903 }
70d321e6 1904 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1905 /* sanity check */
1906 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1907 snd_BUG_ON(!runtime->hw.channels_max) ||
1908 snd_BUG_ON(!runtime->hw.formats) ||
1909 snd_BUG_ON(!runtime->hw.rates)) {
1910 azx_release_device(azx_dev);
1911 hinfo->ops.close(hinfo, apcm->codec, substream);
1912 snd_hda_power_down(apcm->codec);
1913 mutex_unlock(&chip->open_mutex);
1914 return -EINVAL;
1915 }
5d890f59
PLB		 1916
1917 /* disable WALLCLOCK timestamps for capture streams
1918 until we figure out how to handle digital inputs */
1919 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1920 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1921
1da177e4
LT		 1922 spin_lock_irqsave(&chip->reg_lock, flags);
1923 azx_dev->substream = substream;
1924 azx_dev->running = 0;
1925 spin_unlock_irqrestore(&chip->reg_lock, flags);
1926
1927 runtime->private_data = azx_dev;
850f0e52 1928 snd_pcm_set_sync(substream);
62932df8 1929 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1930 return 0;
1931}
1932
a98f90fd 1933static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1934{
1935 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1936 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1937 struct azx *chip = apcm->chip;
1938 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1939 unsigned long flags;
1940
62932df8 1941 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1942 spin_lock_irqsave(&chip->reg_lock, flags);
1943 azx_dev->substream = NULL;
1944 azx_dev->running = 0;
1945 spin_unlock_irqrestore(&chip->reg_lock, flags);
1946 azx_release_device(azx_dev);
1947 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1948 snd_hda_power_down(apcm->codec);
62932df8 1949 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1950 return 0;
1951}
1952
d01ce99f
TI		 1953static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1954 struct snd_pcm_hw_params *hw_params)
1da177e4 1955{
27fe48d9
TI		 1956 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1957 struct azx *chip = apcm->chip;
1958 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94 1959 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 1960 int ret;
97b71c94 1961
27fe48d9 1962 mark_runtime_wc(chip, azx_dev, runtime, false);
97b71c94
TI		 1963 azx_dev->bufsize = 0;
1964 azx_dev->period_bytes = 0;
1965 azx_dev->format_val = 0;
27fe48d9 1966 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 1967 params_buffer_bytes(hw_params));
27fe48d9
TI		 1968 if (ret < 0)
1969 return ret;
1970 mark_runtime_wc(chip, azx_dev, runtime, true);
1971 return ret;
1da177e4
LT		 1972}
1973
a98f90fd 1974static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1975{
1976 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1977 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9
TI		 1978 struct azx *chip = apcm->chip;
1979 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1980 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1981
1982 /* reset BDL address */
1983 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1984 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1985 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1986 azx_dev->bufsize = 0;
1987 azx_dev->period_bytes = 0;
1988 azx_dev->format_val = 0;
1da177e4 1989
eb541337 1990 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 1991
27fe48d9 1992 mark_runtime_wc(chip, azx_dev, runtime, false);
1da177e4
LT		 1993 return snd_pcm_lib_free_pages(substream);
1994}
1995
a98f90fd 1996static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 1997{
1998 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 1999 struct azx *chip = apcm->chip;
2000 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 2001 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 2002 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 2003 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 2004 int err;
7c935976
SW		 2005 struct hda_spdif_out *spdif =
2006 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2007 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 2008
fa00e046 2009 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 2010 format_val = snd_hda_calc_stream_format(runtime->rate,
2011 runtime->channels,
2012 runtime->format,
32c168c8 2013 hinfo->maxbps,
7c935976 2014 ctls);
97b71c94 2015 if (!format_val) {
d01ce99f 2016 snd_printk(KERN_ERR SFX
445a51b3
DB		 2017 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2018 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
1da177e4
LT		 2019 return -EINVAL;
2020 }
2021
97b71c94
TI		 2022 bufsize = snd_pcm_lib_buffer_bytes(substream);
2023 period_bytes = snd_pcm_lib_period_bytes(substream);
2024
445a51b3
DB		 2025 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2026 pci_name(chip->pci), bufsize, format_val);
97b71c94
TI		 2027
2028 if (bufsize != azx_dev->bufsize ||
2029 period_bytes != azx_dev->period_bytes ||
915bf29e
TI		 2030 format_val != azx_dev->format_val ||
2031 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
97b71c94
TI		 2032 azx_dev->bufsize = bufsize;
2033 azx_dev->period_bytes = period_bytes;
2034 azx_dev->format_val = format_val;
915bf29e 2035 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
97b71c94
TI		 2036 err = azx_setup_periods(chip, substream, azx_dev);
2037 if (err < 0)
2038 return err;
2039 }
2040
e5463720
JK		 2041 /* wallclk has 24Mhz clock source */
2042 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2043 runtime->rate) * 1000);
1da177e4
LT		 2044 azx_setup_controller(chip, azx_dev);
2045 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2046 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2047 else
2048 azx_dev->fifo_size = 0;
2049
62b7e5e0
TI		 2050 stream_tag = azx_dev->stream_tag;
2051 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 2052 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 2053 stream_tag > chip->capture_streams)
2054 stream_tag -= chip->capture_streams;
2055 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 2056 azx_dev->format_val, substream);
1da177e4
LT		 2057}
2058
a98f90fd 2059static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 2060{
2061 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2062 struct azx *chip = apcm->chip;
850f0e52
TI		 2063 struct azx_dev *azx_dev;
2064 struct snd_pcm_substream *s;
fa00e046 2065 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 2066 int nwait, timeout;
1da177e4 2067
1a8506d4
TI		 2068 azx_dev = get_azx_dev(substream);
2069 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2070
1da177e4 2071 switch (cmd) {
fa00e046
JK		 2072 case SNDRV_PCM_TRIGGER_START:
2073 rstart = 1;
1da177e4
LT		 2074 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2075 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 2076 start = 1;
1da177e4
LT		 2077 break;
2078 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 2079 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 2080 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 2081 start = 0;
1da177e4
LT		 2082 break;
2083 default:
850f0e52
TI		 2084 return -EINVAL;
2085 }
2086
2087 snd_pcm_group_for_each_entry(s, substream) {
2088 if (s->pcm->card != substream->pcm->card)
2089 continue;
2090 azx_dev = get_azx_dev(s);
2091 sbits |= 1 << azx_dev->index;
2092 nsync++;
2093 snd_pcm_trigger_done(s, substream);
2094 }
2095
2096 spin_lock(&chip->reg_lock);
172d3b20
PLB		 2097
2098 /* first, set SYNC bits of corresponding streams */
2099 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2100 azx_writel(chip, OLD_SSYNC,
2101 azx_readl(chip, OLD_SSYNC) | sbits);
2102 else
2103 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2104
850f0e52
TI		 2105 snd_pcm_group_for_each_entry(s, substream) {
2106 if (s->pcm->card != substream->pcm->card)
2107 continue;
2108 azx_dev = get_azx_dev(s);
e5463720
JK		 2109 if (start) {
2110 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2111 if (!rstart)
2112 azx_dev->start_wallclk -=
2113 azx_dev->period_wallclk;
850f0e52 2114 azx_stream_start(chip, azx_dev);
e5463720 2115 } else {
850f0e52 2116 azx_stream_stop(chip, azx_dev);
e5463720 2117 }
850f0e52 2118 azx_dev->running = start;
1da177e4
LT		 2119 }
2120 spin_unlock(&chip->reg_lock);
850f0e52 2121 if (start) {
850f0e52
TI		 2122 /* wait until all FIFOs get ready */
2123 for (timeout = 5000; timeout; timeout--) {
2124 nwait = 0;
2125 snd_pcm_group_for_each_entry(s, substream) {
2126 if (s->pcm->card != substream->pcm->card)
2127 continue;
2128 azx_dev = get_azx_dev(s);
2129 if (!(azx_sd_readb(azx_dev, SD_STS) &
2130 SD_STS_FIFO_READY))
2131 nwait++;
2132 }
2133 if (!nwait)
2134 break;
2135 cpu_relax();
2136 }
2137 } else {
2138 /* wait until all RUN bits are cleared */
2139 for (timeout = 5000; timeout; timeout--) {
2140 nwait = 0;
2141 snd_pcm_group_for_each_entry(s, substream) {
2142 if (s->pcm->card != substream->pcm->card)
2143 continue;
2144 azx_dev = get_azx_dev(s);
2145 if (azx_sd_readb(azx_dev, SD_CTL) &
2146 SD_CTL_DMA_START)
2147 nwait++;
2148 }
2149 if (!nwait)
2150 break;
2151 cpu_relax();
2152 }
1da177e4 2153 }
172d3b20
PLB		 2154 spin_lock(&chip->reg_lock);
2155 /* reset SYNC bits */
2156 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2157 azx_writel(chip, OLD_SSYNC,
2158 azx_readl(chip, OLD_SSYNC) & ~sbits);
2159 else
2160 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
5d890f59
PLB		 2161 if (start) {
2162 azx_timecounter_init(substream, 0, 0);
2163 if (nsync > 1) {
2164 cycle_t cycle_last;
2165
2166 /* same start cycle for master and group */
2167 azx_dev = get_azx_dev(substream);
2168 cycle_last = azx_dev->azx_tc.cycle_last;
2169
2170 snd_pcm_group_for_each_entry(s, substream) {
2171 if (s->pcm->card != substream->pcm->card)
2172 continue;
2173 azx_timecounter_init(s, 1, cycle_last);
2174 }
2175 }
2176 }
172d3b20 2177 spin_unlock(&chip->reg_lock);
850f0e52 2178 return 0;
1da177e4
LT		 2179}
2180
0e153474
JC		 2181/* get the current DMA position with correction on VIA chips */
2182static unsigned int azx_via_get_position(struct azx *chip,
2183 struct azx_dev *azx_dev)
2184{
2185 unsigned int link_pos, mini_pos, bound_pos;
2186 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2187 unsigned int fifo_size;
2188
2189 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2190 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2191 /* Playback, no problem using link position */
2192 return link_pos;
2193 }
2194
2195 /* Capture */
2196 /* For new chipset,
2197 * use mod to get the DMA position just like old chipset
2198 */
2199 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2200 mod_dma_pos %= azx_dev->period_bytes;
2201
2202 /* azx_dev->fifo_size can't get FIFO size of in stream.
2203 * Get from base address + offset.
2204 */
2205 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2206
2207 if (azx_dev->insufficient) {
2208 /* Link position never gather than FIFO size */
2209 if (link_pos <= fifo_size)
2210 return 0;
2211
2212 azx_dev->insufficient = 0;
2213 }
2214
2215 if (link_pos <= fifo_size)
2216 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2217 else
2218 mini_pos = link_pos - fifo_size;
2219
2220 /* Find nearest previous boudary */
2221 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2222 mod_link_pos = link_pos % azx_dev->period_bytes;
2223 if (mod_link_pos >= fifo_size)
2224 bound_pos = link_pos - mod_link_pos;
2225 else if (mod_dma_pos >= mod_mini_pos)
2226 bound_pos = mini_pos - mod_mini_pos;
2227 else {
2228 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2229 if (bound_pos >= azx_dev->bufsize)
2230 bound_pos = 0;
2231 }
2232
2233 /* Calculate real DMA position we want */
2234 return bound_pos + mod_dma_pos;
2235}
2236
9ad593f6 2237static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2238 struct azx_dev *azx_dev,
2239 bool with_check)
1da177e4 2240{
1da177e4 2241 unsigned int pos;
4cb36310 2242 int stream = azx_dev->substream->stream;
1a8506d4 2243 int delay = 0;
1da177e4 2244
4cb36310
DH		 2245 switch (chip->position_fix[stream]) {
2246 case POS_FIX_LPIB:
2247 /* read LPIB */
2248 pos = azx_sd_readl(azx_dev, SD_LPIB);
2249 break;
2250 case POS_FIX_VIACOMBO:
0e153474 2251 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2252 break;
2253 default:
2254 /* use the position buffer */
2255 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2256 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2257 if (!pos || pos == (u32)-1) {
2258 printk(KERN_WARNING
2259 "hda-intel: Invalid position buffer, "
2260 "using LPIB read method instead.\n");
2261 chip->position_fix[stream] = POS_FIX_LPIB;
2262 pos = azx_sd_readl(azx_dev, SD_LPIB);
2263 } else
2264 chip->position_fix[stream] = POS_FIX_POSBUF;
2265 }
2266 break;
c74db86b 2267 }
4cb36310 2268
1da177e4
LT		 2269 if (pos >= azx_dev->bufsize)
2270 pos = 0;
90accc58
PLB		 2271
2272 /* calculate runtime delay from LPIB */
2273 if (azx_dev->substream->runtime &&
2274 chip->position_fix[stream] == POS_FIX_POSBUF &&
2275 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2276 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
90accc58
PLB		 2277 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2278 delay = pos - lpib_pos;
2279 else
2280 delay = lpib_pos - pos;
2281 if (delay < 0)
2282 delay += azx_dev->bufsize;
2283 if (delay >= azx_dev->period_bytes) {
1f04661f 2284 snd_printk(KERN_WARNING SFX
445a51b3 2285 "%s: Unstable LPIB (%d >= %d); "
1f04661f 2286 "disabling LPIB delay counting\n",
445a51b3 2287 pci_name(chip->pci), delay, azx_dev->period_bytes);
1f04661f
TI		 2288 delay = 0;
2289 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
90accc58
PLB		 2290 }
2291 azx_dev->substream->runtime->delay =
2292 bytes_to_frames(azx_dev->substream->runtime, delay);
2293 }
1a8506d4 2294 trace_azx_get_position(chip, azx_dev, pos, delay);
9ad593f6
TI		 2295 return pos;
2296}
2297
2298static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2299{
2300 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2301 struct azx *chip = apcm->chip;
2302 struct azx_dev *azx_dev = get_azx_dev(substream);
2303 return bytes_to_frames(substream->runtime,
798cb7e8 2304 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2305}
2306
2307/*
2308 * Check whether the current DMA position is acceptable for updating
2309 * periods. Returns non-zero if it's OK.
2310 *
2311 * Many HD-audio controllers appear pretty inaccurate about
2312 * the update-IRQ timing. The IRQ is issued before actually the
2313 * data is processed. So, we need to process it afterwords in a
2314 * workqueue.
2315 */
2316static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2317{
e5463720 2318 u32 wallclk;
9ad593f6
TI		 2319 unsigned int pos;
2320
f48f606d
JK		 2321 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2322 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2323 return -1; /* bogus (too early) interrupt */
fa00e046 2324
798cb7e8 2325 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2326
d6d8bf54
TI		 2327 if (WARN_ONCE(!azx_dev->period_bytes,
2328 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2329 return -1; /* this shouldn't happen! */
edb39935 2330 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2331 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2332 /* NG - it's below the first next period boundary */
2333 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2334 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2335 return 1; /* OK, it's fine */
2336}
2337
2338/*
2339 * The work for pending PCM period updates.
2340 */
2341static void azx_irq_pending_work(struct work_struct *work)
2342{
2343 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2344 int i, pending, ok;
9ad593f6 2345
a6a950a8
TI		 2346 if (!chip->irq_pending_warned) {
2347 printk(KERN_WARNING
2348 "hda-intel: IRQ timing workaround is activated "
2349 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2350 chip->card->number);
2351 chip->irq_pending_warned = 1;
2352 }
2353
9ad593f6
TI		 2354 for (;;) {
2355 pending = 0;
2356 spin_lock_irq(&chip->reg_lock);
2357 for (i = 0; i < chip->num_streams; i++) {
2358 struct azx_dev *azx_dev = &chip->azx_dev[i];
2359 if (!azx_dev->irq_pending ||
2360 !azx_dev->substream ||
2361 !azx_dev->running)
2362 continue;
e5463720
JK		 2363 ok = azx_position_ok(chip, azx_dev);
2364 if (ok > 0) {
9ad593f6
TI		 2365 azx_dev->irq_pending = 0;
2366 spin_unlock(&chip->reg_lock);
2367 snd_pcm_period_elapsed(azx_dev->substream);
2368 spin_lock(&chip->reg_lock);
e5463720
JK		 2369 } else if (ok < 0) {
2370 pending = 0; /* too early */
9ad593f6
TI		 2371 } else
2372 pending++;
2373 }
2374 spin_unlock_irq(&chip->reg_lock);
2375 if (!pending)
2376 return;
08af495f 2377 msleep(1);
9ad593f6
TI		 2378 }
2379}
2380
2381/* clear irq_pending flags and assure no on-going workq */
2382static void azx_clear_irq_pending(struct azx *chip)
2383{
2384 int i;
2385
2386 spin_lock_irq(&chip->reg_lock);
2387 for (i = 0; i < chip->num_streams; i++)
2388 chip->azx_dev[i].irq_pending = 0;
2389 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2390}
2391
27fe48d9
TI		 2392#ifdef CONFIG_X86
2393static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2394 struct vm_area_struct *area)
2395{
2396 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2397 struct azx *chip = apcm->chip;
2398 if (!azx_snoop(chip))
2399 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2400 return snd_pcm_lib_default_mmap(substream, area);
2401}
2402#else
2403#define azx_pcm_mmap NULL
2404#endif
2405
a98f90fd 2406static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2407 .open = azx_pcm_open,
2408 .close = azx_pcm_close,
2409 .ioctl = snd_pcm_lib_ioctl,
2410 .hw_params = azx_pcm_hw_params,
2411 .hw_free = azx_pcm_hw_free,
2412 .prepare = azx_pcm_prepare,
2413 .trigger = azx_pcm_trigger,
2414 .pointer = azx_pcm_pointer,
5d890f59 2415 .wall_clock = azx_get_wallclock_tstamp,
27fe48d9 2416 .mmap = azx_pcm_mmap,
4ce107b9 2417 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2418};
2419
a98f90fd 2420static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2421{
176d5335
TI		 2422 struct azx_pcm *apcm = pcm->private_data;
2423 if (apcm) {
01b65bfb 2424 list_del(&apcm->list);
176d5335
TI		 2425 kfree(apcm);
2426 }
1da177e4
LT		 2427}
2428
acfa634f
TI		 2429#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2430
176d5335 2431static int
33fa35ed
TI		 2432azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2433 struct hda_pcm *cpcm)
1da177e4 2434{
33fa35ed 2435 struct azx *chip = bus->private_data;
a98f90fd 2436 struct snd_pcm *pcm;
1da177e4 2437 struct azx_pcm *apcm;
176d5335 2438 int pcm_dev = cpcm->device;
acfa634f 2439 unsigned int size;
176d5335 2440 int s, err;
1da177e4 2441
01b65bfb
TI		 2442 list_for_each_entry(apcm, &chip->pcm_list, list) {
2443 if (apcm->pcm->device == pcm_dev) {
445a51b3
DB		 2444 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2445 pci_name(chip->pci), pcm_dev);
01b65bfb
TI		 2446 return -EBUSY;
2447 }
176d5335
TI		 2448 }
2449 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2450 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2451 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2452 &pcm);
2453 if (err < 0)
2454 return err;
18cb7109 2455 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2456 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2457 if (apcm == NULL)
2458 return -ENOMEM;
2459 apcm->chip = chip;
01b65bfb 2460 apcm->pcm = pcm;
1da177e4 2461 apcm->codec = codec;
1da177e4
LT		 2462 pcm->private_data = apcm;
2463 pcm->private_free = azx_pcm_free;
176d5335
TI		 2464 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2465 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2466 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2467 cpcm->pcm = pcm;
2468 for (s = 0; s < 2; s++) {
2469 apcm->hinfo[s] = &cpcm->stream[s];
2470 if (cpcm->stream[s].substreams)
2471 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2472 }
2473 /* buffer pre-allocation */
acfa634f
TI		 2474 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2475 if (size > MAX_PREALLOC_SIZE)
2476 size = MAX_PREALLOC_SIZE;
4ce107b9 2477 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2478 snd_dma_pci_data(chip->pci),
acfa634f 2479 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2480 return 0;
2481}
2482
2483/*
2484 * mixer creation - all stuff is implemented in hda module
2485 */
e23e7a14 2486static int azx_mixer_create(struct azx *chip)
1da177e4
LT		 2487{
2488 return snd_hda_build_controls(chip->bus);
2489}
2490
2491
2492/*
2493 * initialize SD streams
2494 */
e23e7a14 2495static int azx_init_stream(struct azx *chip)
1da177e4
LT		 2496{
2497 int i;
2498
2499 /* initialize each stream (aka device)
d01ce99f
TI		 2500 * assign the starting bdl address to each stream (device)
2501 * and initialize
1da177e4 2502 */
07e4ca50 2503 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2504 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2505 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2506 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2507 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2508 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2509 azx_dev->sd_int_sta_mask = 1 << i;
2510 /* stream tag: must be non-zero and unique */
2511 azx_dev->index = i;
2512 azx_dev->stream_tag = i + 1;
2513 }
2514
2515 return 0;
2516}
2517
68e7fffc
TI		 2518static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2519{
437a5a46
TI		 2520 if (request_irq(chip->pci->irq, azx_interrupt,
2521 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2522 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2523 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2524 "disabling device\n", chip->pci->irq);
2525 if (do_disconnect)
2526 snd_card_disconnect(chip->card);
2527 return -1;
2528 }
2529 chip->irq = chip->pci->irq;
69e13418 2530 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2531 return 0;
2532}
2533
1da177e4 2534
cb53c626
TI		 2535static void azx_stop_chip(struct azx *chip)
2536{
95e99fda 2537 if (!chip->initialized)
cb53c626
TI		 2538 return;
2539
2540 /* disable interrupts */
2541 azx_int_disable(chip);
2542 azx_int_clear(chip);
2543
2544 /* disable CORB/RIRB */
2545 azx_free_cmd_io(chip);
2546
2547 /* disable position buffer */
2548 azx_writel(chip, DPLBASE, 0);
2549 azx_writel(chip, DPUBASE, 0);
2550
2551 chip->initialized = 0;
2552}
2553
83012a7c 2554#ifdef CONFIG_PM
cb53c626 2555/* power-up/down the controller */
68467f51 2556static void azx_power_notify(struct hda_bus *bus, bool power_up)
cb53c626 2557{
33fa35ed 2558 struct azx *chip = bus->private_data;
cb53c626 2559
2ea3c6a2
TI		 2560 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2561 return;
2562
68467f51 2563 if (power_up)
b8dfc462
ML		 2564 pm_runtime_get_sync(&chip->pci->dev);
2565 else
2566 pm_runtime_put_sync(&chip->pci->dev);
cb53c626 2567}
65fcd41d
TI		 2568
2569static DEFINE_MUTEX(card_list_lock);
2570static LIST_HEAD(card_list);
2571
2572static void azx_add_card_list(struct azx *chip)
2573{
2574 mutex_lock(&card_list_lock);
2575 list_add(&chip->list, &card_list);
2576 mutex_unlock(&card_list_lock);
2577}
2578
2579static void azx_del_card_list(struct azx *chip)
2580{
2581 mutex_lock(&card_list_lock);
2582 list_del_init(&chip->list);
2583 mutex_unlock(&card_list_lock);
2584}
2585
2586/* trigger power-save check at writing parameter */
2587static int param_set_xint(const char *val, const struct kernel_param *kp)
2588{
2589 struct azx *chip;
2590 struct hda_codec *c;
2591 int prev = power_save;
2592 int ret = param_set_int(val, kp);
2593
2594 if (ret || prev == power_save)
2595 return ret;
2596
2597 mutex_lock(&card_list_lock);
2598 list_for_each_entry(chip, &card_list, list) {
2599 if (!chip->bus || chip->disabled)
2600 continue;
2601 list_for_each_entry(c, &chip->bus->codec_list, list)
2602 snd_hda_power_sync(c);
2603 }
2604 mutex_unlock(&card_list_lock);
2605 return 0;
2606}
2607#else
2608#define azx_add_card_list(chip) /* NOP */
2609#define azx_del_card_list(chip) /* NOP */
83012a7c 2610#endif /* CONFIG_PM */
5c0b9bec 2611
7ccbde57 2612#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 2613/*
2614 * power management
2615 */
68cb2b55 2616static int azx_suspend(struct device *dev)
1da177e4 2617{
68cb2b55
TI		 2618 struct pci_dev *pci = to_pci_dev(dev);
2619 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2620 struct azx *chip = card->private_data;
01b65bfb 2621 struct azx_pcm *p;
1da177e4 2622
421a1252 2623 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2624 azx_clear_irq_pending(chip);
01b65bfb
TI		 2625 list_for_each_entry(p, &chip->pcm_list, list)
2626 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2627 if (chip->initialized)
8dd78330 2628 snd_hda_suspend(chip->bus);
cb53c626 2629 azx_stop_chip(chip);
30b35399 2630 if (chip->irq >= 0) {
43001c95 2631 free_irq(chip->irq, chip);
30b35399
TI		 2632 chip->irq = -1;
2633 }
68e7fffc 2634 if (chip->msi)
43001c95 2635 pci_disable_msi(chip->pci);
421a1252
TI		 2636 pci_disable_device(pci);
2637 pci_save_state(pci);
68cb2b55 2638 pci_set_power_state(pci, PCI_D3hot);
1da177e4
LT		 2639 return 0;
2640}
2641
68cb2b55 2642static int azx_resume(struct device *dev)
1da177e4 2643{
68cb2b55
TI		 2644 struct pci_dev *pci = to_pci_dev(dev);
2645 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2646 struct azx *chip = card->private_data;
1da177e4 2647
d14a7e0b
TI		 2648 pci_set_power_state(pci, PCI_D0);
2649 pci_restore_state(pci);
30b35399
TI		 2650 if (pci_enable_device(pci) < 0) {
2651 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2652 "disabling device\n");
2653 snd_card_disconnect(card);
2654 return -EIO;
2655 }
2656 pci_set_master(pci);
68e7fffc
TI		 2657 if (chip->msi)
2658 if (pci_enable_msi(pci) < 0)
2659 chip->msi = 0;
2660 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2661 return -EIO;
cb53c626 2662 azx_init_pci(chip);
d804ad92 2663
7f30830b 2664 azx_init_chip(chip, 1);
d804ad92 2665
1da177e4 2666 snd_hda_resume(chip->bus);
421a1252 2667 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2668 return 0;
2669}
b8dfc462
ML		 2670#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2671
2672#ifdef CONFIG_PM_RUNTIME
2673static int azx_runtime_suspend(struct device *dev)
2674{
2675 struct snd_card *card = dev_get_drvdata(dev);
2676 struct azx *chip = card->private_data;
2677
2ea3c6a2
TI		 2678 if (!power_save_controller ||
2679 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
b8dfc462
ML		 2680 return -EAGAIN;
2681
2682 azx_stop_chip(chip);
2683 azx_clear_irq_pending(chip);
2684 return 0;
2685}
2686
2687static int azx_runtime_resume(struct device *dev)
2688{
2689 struct snd_card *card = dev_get_drvdata(dev);
2690 struct azx *chip = card->private_data;
2691
2692 azx_init_pci(chip);
2693 azx_init_chip(chip, 1);
2694 return 0;
2695}
2696#endif /* CONFIG_PM_RUNTIME */
2697
2698#ifdef CONFIG_PM
2699static const struct dev_pm_ops azx_pm = {
2700 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2701 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, NULL)
2702};
2703
68cb2b55
TI		 2704#define AZX_PM_OPS &azx_pm
2705#else
68cb2b55 2706#define AZX_PM_OPS NULL
b8dfc462 2707#endif /* CONFIG_PM */
1da177e4
LT		 2708
2709
0cbf0098
TI		 2710/*
2711 * reboot notifier for hang-up problem at power-down
2712 */
2713static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2714{
2715 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2716 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2717 azx_stop_chip(chip);
2718 return NOTIFY_OK;
2719}
2720
2721static void azx_notifier_register(struct azx *chip)
2722{
2723 chip->reboot_notifier.notifier_call = azx_halt;
2724 register_reboot_notifier(&chip->reboot_notifier);
2725}
2726
2727static void azx_notifier_unregister(struct azx *chip)
2728{
2729 if (chip->reboot_notifier.notifier_call)
2730 unregister_reboot_notifier(&chip->reboot_notifier);
2731}
2732
48c8b0eb
TI		 2733static int azx_first_init(struct azx *chip);
2734static int azx_probe_continue(struct azx *chip);
a82d51ed 2735
8393ec4a 2736#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 2737static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 2738
a82d51ed
TI		 2739static void azx_vs_set_state(struct pci_dev *pci,
2740 enum vga_switcheroo_state state)
2741{
2742 struct snd_card *card = pci_get_drvdata(pci);
2743 struct azx *chip = card->private_data;
2744 bool disabled;
2745
f4c482a4 2746 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 2747 if (chip->init_failed)
2748 return;
2749
2750 disabled = (state == VGA_SWITCHEROO_OFF);
2751 if (chip->disabled == disabled)
2752 return;
2753
2754 if (!chip->bus) {
2755 chip->disabled = disabled;
2756 if (!disabled) {
2757 snd_printk(KERN_INFO SFX
2758 "%s: Start delayed initialization\n",
2759 pci_name(chip->pci));
2760 if (azx_first_init(chip) < 0 ||
2761 azx_probe_continue(chip) < 0) {
2762 snd_printk(KERN_ERR SFX
2763 "%s: initialization error\n",
2764 pci_name(chip->pci));
2765 chip->init_failed = true;
2766 }
2767 }
2768 } else {
2769 snd_printk(KERN_INFO SFX
445a51b3
DB		 2770 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
2771 disabled ? "Disabling" : "Enabling");
a82d51ed 2772 if (disabled) {
68cb2b55 2773 azx_suspend(&pci->dev);
a82d51ed 2774 chip->disabled = true;
128960a9 2775 if (snd_hda_lock_devices(chip->bus))
445a51b3
DB		 2776 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
2777 pci_name(chip->pci));
a82d51ed
TI		 2778 } else {
2779 snd_hda_unlock_devices(chip->bus);
2780 chip->disabled = false;
68cb2b55 2781 azx_resume(&pci->dev);
a82d51ed
TI		 2782 }
2783 }
2784}
2785
2786static bool azx_vs_can_switch(struct pci_dev *pci)
2787{
2788 struct snd_card *card = pci_get_drvdata(pci);
2789 struct azx *chip = card->private_data;
2790
f4c482a4 2791 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 2792 if (chip->init_failed)
2793 return false;
2794 if (chip->disabled || !chip->bus)
2795 return true;
2796 if (snd_hda_lock_devices(chip->bus))
2797 return false;
2798 snd_hda_unlock_devices(chip->bus);
2799 return true;
2800}
2801
e23e7a14 2802static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 2803{
2804 struct pci_dev *p = get_bound_vga(chip->pci);
2805 if (p) {
2806 snd_printk(KERN_INFO SFX
2807 "%s: Handle VGA-switcheroo audio client\n",
2808 pci_name(chip->pci));
2809 chip->use_vga_switcheroo = 1;
2810 pci_dev_put(p);
2811 }
2812}
2813
2814static const struct vga_switcheroo_client_ops azx_vs_ops = {
2815 .set_gpu_state = azx_vs_set_state,
2816 .can_switch = azx_vs_can_switch,
2817};
2818
e23e7a14 2819static int register_vga_switcheroo(struct azx *chip)
a82d51ed 2820{
128960a9
TI		 2821 int err;
2822
a82d51ed
TI		 2823 if (!chip->use_vga_switcheroo)
2824 return 0;
2825 /* FIXME: currently only handling DIS controller
2826 * is there any machine with two switchable HDMI audio controllers?
2827 */
128960a9 2828 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 2829 VGA_SWITCHEROO_DIS,
2830 chip->bus != NULL);
128960a9
TI		 2831 if (err < 0)
2832 return err;
2833 chip->vga_switcheroo_registered = 1;
2834 return 0;
a82d51ed
TI		 2835}
2836#else
2837#define init_vga_switcheroo(chip) /* NOP */
2838#define register_vga_switcheroo(chip) 0
8393ec4a 2839#define check_hdmi_disabled(pci) false
a82d51ed
TI		 2840#endif /* SUPPORT_VGA_SWITCHER */
2841
1da177e4
LT		 2842/*
2843 * destructor
2844 */
a98f90fd 2845static int azx_free(struct azx *chip)
1da177e4 2846{
4ce107b9
TI		 2847 int i;
2848
65fcd41d
TI		 2849 azx_del_card_list(chip);
2850
0cbf0098
TI		 2851 azx_notifier_unregister(chip);
2852
f4c482a4
TI		 2853 chip->init_failed = 1; /* to be sure */
2854 complete(&chip->probe_wait);
2855
a82d51ed
TI		 2856 if (use_vga_switcheroo(chip)) {
2857 if (chip->disabled && chip->bus)
2858 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 2859 if (chip->vga_switcheroo_registered)
2860 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 2861 }
2862
ce43fbae 2863 if (chip->initialized) {
9ad593f6 2864 azx_clear_irq_pending(chip);
07e4ca50 2865 for (i = 0; i < chip->num_streams; i++)
1da177e4 2866 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2867 azx_stop_chip(chip);
1da177e4
LT		 2868 }
2869
f000fd80 2870 if (chip->irq >= 0)
1da177e4 2871 free_irq(chip->irq, (void*)chip);
68e7fffc 2872 if (chip->msi)
30b35399 2873 pci_disable_msi(chip->pci);
f079c25a
TI		 2874 if (chip->remap_addr)
2875 iounmap(chip->remap_addr);
1da177e4 2876
4ce107b9
TI		 2877 if (chip->azx_dev) {
2878 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 2879 if (chip->azx_dev[i].bdl.area) {
2880 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 2881 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 2882 }
4ce107b9 2883 }
27fe48d9
TI		 2884 if (chip->rb.area) {
2885 mark_pages_wc(chip, &chip->rb, false);
1da177e4 2886 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 2887 }
2888 if (chip->posbuf.area) {
2889 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 2890 snd_dma_free_pages(&chip->posbuf);
27fe48d9 2891 }
a82d51ed
TI		 2892 if (chip->region_requested)
2893 pci_release_regions(chip->pci);
1da177e4 2894 pci_disable_device(chip->pci);
07e4ca50 2895 kfree(chip->azx_dev);
4918cdab
TI		 2896#ifdef CONFIG_SND_HDA_PATCH_LOADER
2897 if (chip->fw)
2898 release_firmware(chip->fw);
2899#endif
1da177e4
LT		 2900 kfree(chip);
2901
2902 return 0;
2903}
2904
a98f90fd 2905static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2906{
2907 return azx_free(device->device_data);
2908}
2909
8393ec4a 2910#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 2911/*
2912 * Check of disabled HDMI controller by vga-switcheroo
2913 */
e23e7a14 2914static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 2915{
2916 struct pci_dev *p;
2917
2918 /* check only discrete GPU */
2919 switch (pci->vendor) {
2920 case PCI_VENDOR_ID_ATI:
2921 case PCI_VENDOR_ID_AMD:
2922 case PCI_VENDOR_ID_NVIDIA:
2923 if (pci->devfn == 1) {
2924 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2925 pci->bus->number, 0);
2926 if (p) {
2927 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2928 return p;
2929 pci_dev_put(p);
2930 }
2931 }
2932 break;
2933 }
2934 return NULL;
2935}
2936
e23e7a14 2937static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 2938{
2939 bool vga_inactive = false;
2940 struct pci_dev *p = get_bound_vga(pci);
2941
2942 if (p) {
12b78a7f 2943 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 2944 vga_inactive = true;
2945 pci_dev_put(p);
2946 }
2947 return vga_inactive;
2948}
8393ec4a 2949#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 2950
3372a153
TI		 2951/*
2952 * white/black-listing for position_fix
2953 */
e23e7a14 2954static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 2955 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2956 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2957 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2958 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 2959 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 2960 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 2961 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 2962 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 2963 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 2964 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2965 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 2966 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 2967 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 2968 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 2969 {}
2970};
2971
e23e7a14 2972static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 2973{
2974 const struct snd_pci_quirk *q;
2975
c673ba1c 2976 switch (fix) {
1dac6695 2977 case POS_FIX_AUTO:
c673ba1c
TI		 2978 case POS_FIX_LPIB:
2979 case POS_FIX_POSBUF:
4cb36310 2980 case POS_FIX_VIACOMBO:
a6f2fd55 2981 case POS_FIX_COMBO:
c673ba1c
TI		 2982 return fix;
2983 }
2984
c673ba1c
TI		 2985 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2986 if (q) {
2987 printk(KERN_INFO
2988 "hda_intel: position_fix set to %d "
2989 "for device %04x:%04x\n",
2990 q->value, q->subvendor, q->subdevice);
2991 return q->value;
3372a153 2992 }
bdd9ef24
DH		 2993
2994 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 2995 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
445a51b3 2996 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
bdd9ef24 2997 return POS_FIX_VIACOMBO;
9477c58e
TI		 2998 }
2999 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
445a51b3 3000 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
50e3bbf9 3001 return POS_FIX_LPIB;
bdd9ef24 3002 }
c673ba1c 3003 return POS_FIX_AUTO;
3372a153
TI		 3004}
3005
669ba27a
TI		 3006/*
3007 * black-lists for probe_mask
3008 */
e23e7a14 3009static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 3010 /* Thinkpad often breaks the controller communication when accessing
3011 * to the non-working (or non-existing) modem codec slot.
3012 */
3013 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3014 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3015 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 3016 /* broken BIOS */
3017 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 3018 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3019 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 3020 /* forced codec slots */
93574844 3021 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 3022 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 3023 /* WinFast VP200 H (Teradici) user reported broken communication */
3024 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 3025 {}
3026};
3027
f1eaaeec
TI		 3028#define AZX_FORCE_CODEC_MASK 0x100
3029
e23e7a14 3030static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 3031{
3032 const struct snd_pci_quirk *q;
3033
f1eaaeec
TI		 3034 chip->codec_probe_mask = probe_mask[dev];
3035 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 3036 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3037 if (q) {
3038 printk(KERN_INFO
3039 "hda_intel: probe_mask set to 0x%x "
3040 "for device %04x:%04x\n",
3041 q->value, q->subvendor, q->subdevice);
f1eaaeec 3042 chip->codec_probe_mask = q->value;
669ba27a
TI		 3043 }
3044 }
f1eaaeec
TI		 3045
3046 /* check forced option */
3047 if (chip->codec_probe_mask != -1 &&
3048 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3049 chip->codec_mask = chip->codec_probe_mask & 0xff;
3050 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3051 chip->codec_mask);
3052 }
669ba27a
TI		 3053}
3054
4d8e22e0 3055/*
71623855 3056 * white/black-list for enable_msi
4d8e22e0 3057 */
e23e7a14 3058static struct snd_pci_quirk msi_black_list[] = {
9dc8398b 3059 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 3060 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 3061 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 3062 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 3063 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 3064 {}
3065};
3066
e23e7a14 3067static void check_msi(struct azx *chip)
4d8e22e0
TI		 3068{
3069 const struct snd_pci_quirk *q;
3070
71623855
TI		 3071 if (enable_msi >= 0) {
3072 chip->msi = !!enable_msi;
4d8e22e0 3073 return;
71623855
TI		 3074 }
3075 chip->msi = 1; /* enable MSI as default */
3076 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 3077 if (q) {
3078 printk(KERN_INFO
3079 "hda_intel: msi for device %04x:%04x set to %d\n",
3080 q->subvendor, q->subdevice, q->value);
3081 chip->msi = q->value;
80c43ed7
TI		 3082 return;
3083 }
3084
3085 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 3086 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3087 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 3088 chip->msi = 0;
4d8e22e0
TI		 3089 }
3090}
3091
a1585d76 3092/* check the snoop mode availability */
e23e7a14 3093static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 3094{
3095 bool snoop = chip->snoop;
3096
3097 switch (chip->driver_type) {
3098 case AZX_DRIVER_VIA:
3099 /* force to non-snoop mode for a new VIA controller
3100 * when BIOS is set
3101 */
3102 if (snoop) {
3103 u8 val;
3104 pci_read_config_byte(chip->pci, 0x42, &val);
3105 if (!(val & 0x80) && chip->pci->revision == 0x30)
3106 snoop = false;
3107 }
3108 break;
3109 case AZX_DRIVER_ATIHDMI_NS:
3110 /* new ATI HDMI requires non-snoop */
3111 snoop = false;
3112 break;
3113 }
3114
3115 if (snoop != chip->snoop) {
445a51b3
DB		 3116 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3117 pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
a1585d76
TI		 3118 chip->snoop = snoop;
3119 }
3120}
669ba27a 3121
1da177e4
LT		 3122/*
3123 * constructor
3124 */
e23e7a14
BP		 3125static int azx_create(struct snd_card *card, struct pci_dev *pci,
3126 int dev, unsigned int driver_caps,
3127 struct azx **rchip)
1da177e4 3128{
a98f90fd 3129 static struct snd_device_ops ops = {
1da177e4
LT		 3130 .dev_free = azx_dev_free,
3131 };
a82d51ed
TI		 3132 struct azx *chip;
3133 int err;
1da177e4
LT		 3134
3135 *rchip = NULL;
bcd72003 3136
927fc866
PM		 3137 err = pci_enable_device(pci);
3138 if (err < 0)
1da177e4
LT		 3139 return err;
3140
e560d8d8 3141 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 3142 if (!chip) {
445a51b3 3143 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
1da177e4
LT		 3144 pci_disable_device(pci);
3145 return -ENOMEM;
3146 }
3147
3148 spin_lock_init(&chip->reg_lock);
62932df8 3149 mutex_init(&chip->open_mutex);
1da177e4
LT		 3150 chip->card = card;
3151 chip->pci = pci;
3152 chip->irq = -1;
9477c58e
TI		 3153 chip->driver_caps = driver_caps;
3154 chip->driver_type = driver_caps & 0xff;
4d8e22e0 3155 check_msi(chip);
555e219f 3156 chip->dev_index = dev;
9ad593f6 3157 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 3158 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 3159 INIT_LIST_HEAD(&chip->list);
a82d51ed 3160 init_vga_switcheroo(chip);
f4c482a4 3161 init_completion(&chip->probe_wait);
1da177e4 3162
beaffc39
SG		 3163 chip->position_fix[0] = chip->position_fix[1] =
3164 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 3165 /* combo mode uses LPIB for playback */
3166 if (chip->position_fix[0] == POS_FIX_COMBO) {
3167 chip->position_fix[0] = POS_FIX_LPIB;
3168 chip->position_fix[1] = POS_FIX_AUTO;
3169 }
3170
5aba4f8e 3171 check_probe_mask(chip, dev);
3372a153 3172
27346166 3173 chip->single_cmd = single_cmd;
27fe48d9 3174 chip->snoop = hda_snoop;
a1585d76 3175 azx_check_snoop_available(chip);
c74db86b 3176
5c0d7bc1
TI		 3177 if (bdl_pos_adj[dev] < 0) {
3178 switch (chip->driver_type) {
0c6341ac 3179 case AZX_DRIVER_ICH:
32679f95 3180 case AZX_DRIVER_PCH:
0c6341ac 3181 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 3182 break;
3183 default:
0c6341ac 3184 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 3185 break;
3186 }
3187 }
3188
a82d51ed
TI		 3189 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3190 if (err < 0) {
445a51b3
DB		 3191 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3192 pci_name(chip->pci));
a82d51ed
TI		 3193 azx_free(chip);
3194 return err;
3195 }
3196
3197 *rchip = chip;
3198 return 0;
3199}
3200
48c8b0eb 3201static int azx_first_init(struct azx *chip)
a82d51ed
TI		 3202{
3203 int dev = chip->dev_index;
3204 struct pci_dev *pci = chip->pci;
3205 struct snd_card *card = chip->card;
3206 int i, err;
3207 unsigned short gcap;
3208
07e4ca50
TI		 3209#if BITS_PER_LONG != 64
3210 /* Fix up base address on ULI M5461 */
3211 if (chip->driver_type == AZX_DRIVER_ULI) {
3212 u16 tmp3;
3213 pci_read_config_word(pci, 0x40, &tmp3);
3214 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3215 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3216 }
3217#endif
3218
927fc866 3219 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 3220 if (err < 0)
1da177e4 3221 return err;
a82d51ed 3222 chip->region_requested = 1;
1da177e4 3223
927fc866 3224 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 3225 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 3226 if (chip->remap_addr == NULL) {
445a51b3 3227 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
a82d51ed 3228 return -ENXIO;
1da177e4
LT		 3229 }
3230
68e7fffc
TI		 3231 if (chip->msi)
3232 if (pci_enable_msi(pci) < 0)
3233 chip->msi = 0;
7376d013 3234
a82d51ed
TI		 3235 if (azx_acquire_irq(chip, 0) < 0)
3236 return -EBUSY;
1da177e4
LT		 3237
3238 pci_set_master(pci);
3239 synchronize_irq(chip->irq);
3240
bcd72003 3241 gcap = azx_readw(chip, GCAP);
445a51b3 3242 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
bcd72003 3243
dc4c2e6b 3244 /* disable SB600 64bit support for safety */
9477c58e 3245 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3246 struct pci_dev *p_smbus;
3247 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3248 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3249 NULL);
3250 if (p_smbus) {
3251 if (p_smbus->revision < 0x30)
3252 gcap &= ~ICH6_GCAP_64OK;
3253 pci_dev_put(p_smbus);
3254 }
3255 }
09240cf4 3256
9477c58e
TI		 3257 /* disable 64bit DMA address on some devices */
3258 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
445a51b3 3259 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
396087ea 3260 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3261 }
396087ea 3262
2ae66c26 3263 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3264 if (align_buffer_size >= 0)
3265 chip->align_buffer_size = !!align_buffer_size;
3266 else {
3267 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3268 chip->align_buffer_size = 0;
3269 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3270 chip->align_buffer_size = 1;
3271 else
3272 chip->align_buffer_size = 1;
3273 }
2ae66c26 3274
cf7aaca8 3275 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3276 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3277 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3278 else {
e930438c
YH		 3279 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3280 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3281 }
cf7aaca8 3282
8b6ed8e7
TI		 3283 /* read number of streams from GCAP register instead of using
3284 * hardcoded value
3285 */
3286 chip->capture_streams = (gcap >> 8) & 0x0f;
3287 chip->playback_streams = (gcap >> 12) & 0x0f;
3288 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3289 /* gcap didn't give any info, switching to old method */
3290
3291 switch (chip->driver_type) {
3292 case AZX_DRIVER_ULI:
3293 chip->playback_streams = ULI_NUM_PLAYBACK;
3294 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3295 break;
3296 case AZX_DRIVER_ATIHDMI:
1815b34a 3297 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3298 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3299 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3300 break;
c4da29ca 3301 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3302 default:
3303 chip->playback_streams = ICH6_NUM_PLAYBACK;
3304 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3305 break;
3306 }
07e4ca50 3307 }
8b6ed8e7
TI		 3308 chip->capture_index_offset = 0;
3309 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3310 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3311 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3312 GFP_KERNEL);
927fc866 3313 if (!chip->azx_dev) {
445a51b3 3314 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
a82d51ed 3315 return -ENOMEM;
07e4ca50
TI		 3316 }
3317
4ce107b9
TI		 3318 for (i = 0; i < chip->num_streams; i++) {
3319 /* allocate memory for the BDL for each stream */
3320 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3321 snd_dma_pci_data(chip->pci),
3322 BDL_SIZE, &chip->azx_dev[i].bdl);
3323 if (err < 0) {
445a51b3 3324 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
a82d51ed 3325 return -ENOMEM;
4ce107b9 3326 }
27fe48d9 3327 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3328 }
0be3b5d3 3329 /* allocate memory for the position buffer */
d01ce99f
TI		 3330 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3331 snd_dma_pci_data(chip->pci),
3332 chip->num_streams * 8, &chip->posbuf);
3333 if (err < 0) {
445a51b3 3334 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
a82d51ed 3335 return -ENOMEM;
1da177e4 3336 }
27fe48d9 3337 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3338 /* allocate CORB/RIRB */
81740861
TI		 3339 err = azx_alloc_cmd_io(chip);
3340 if (err < 0)
a82d51ed 3341 return err;
1da177e4
LT		 3342
3343 /* initialize streams */
3344 azx_init_stream(chip);
3345
3346 /* initialize chip */
cb53c626 3347 azx_init_pci(chip);
10e77dda 3348 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3349
3350 /* codec detection */
927fc866 3351 if (!chip->codec_mask) {
445a51b3 3352 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
a82d51ed 3353 return -ENODEV;
1da177e4
LT		 3354 }
3355
07e4ca50 3356 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3357 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3358 sizeof(card->shortname));
3359 snprintf(card->longname, sizeof(card->longname),
3360 "%s at 0x%lx irq %i",
3361 card->shortname, chip->addr, chip->irq);
07e4ca50 3362
1da177e4 3363 return 0;
1da177e4
LT		 3364}
3365
cb53c626
TI		 3366static void power_down_all_codecs(struct azx *chip)
3367{
83012a7c 3368#ifdef CONFIG_PM
cb53c626
TI		 3369 /* The codecs were powered up in snd_hda_codec_new().
3370 * Now all initialization done, so turn them down if possible
3371 */
3372 struct hda_codec *codec;
3373 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3374 snd_hda_power_down(codec);
3375 }
3376#endif
3377}
3378
97c6a3d1 3379#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 3380/* callback from request_firmware_nowait() */
3381static void azx_firmware_cb(const struct firmware *fw, void *context)
3382{
3383 struct snd_card *card = context;
3384 struct azx *chip = card->private_data;
3385 struct pci_dev *pci = chip->pci;
3386
3387 if (!fw) {
445a51b3
DB		 3388 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3389 pci_name(chip->pci));
5cb543db
TI		 3390 goto error;
3391 }
3392
3393 chip->fw = fw;
3394 if (!chip->disabled) {
3395 /* continue probing */
3396 if (azx_probe_continue(chip))
3397 goto error;
3398 }
3399 return; /* OK */
3400
3401 error:
3402 snd_card_free(card);
3403 pci_set_drvdata(pci, NULL);
3404}
97c6a3d1 3405#endif
5cb543db 3406
e23e7a14
BP		 3407static int azx_probe(struct pci_dev *pci,
3408 const struct pci_device_id *pci_id)
1da177e4 3409{
5aba4f8e 3410 static int dev;
a98f90fd
TI		 3411 struct snd_card *card;
3412 struct azx *chip;
5cb543db 3413 bool probe_now;
927fc866 3414 int err;
1da177e4 3415
5aba4f8e
TI		 3416 if (dev >= SNDRV_CARDS)
3417 return -ENODEV;
3418 if (!enable[dev]) {
3419 dev++;
3420 return -ENOENT;
3421 }
3422
e58de7ba
TI		 3423 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3424 if (err < 0) {
445a51b3 3425 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
e58de7ba 3426 return err;
1da177e4
LT		 3427 }
3428
4ea6fbc8
TI		 3429 snd_card_set_dev(card, &pci->dev);
3430
5aba4f8e 3431 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3432 if (err < 0)
3433 goto out_free;
421a1252 3434 card->private_data = chip;
f4c482a4
TI		 3435
3436 pci_set_drvdata(pci, card);
3437
3438 err = register_vga_switcheroo(chip);
3439 if (err < 0) {
3440 snd_printk(KERN_ERR SFX
445a51b3 3441 "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
f4c482a4
TI		 3442 goto out_free;
3443 }
3444
3445 if (check_hdmi_disabled(pci)) {
445a51b3 3446 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
f4c482a4 3447 pci_name(pci));
445a51b3 3448 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
f4c482a4
TI		 3449 chip->disabled = true;
3450 }
3451
5cb543db 3452 probe_now = !chip->disabled;
f4c482a4
TI		 3453 if (probe_now) {
3454 err = azx_first_init(chip);
3455 if (err < 0)
3456 goto out_free;
3457 }
1da177e4 3458
4918cdab
TI		 3459#ifdef CONFIG_SND_HDA_PATCH_LOADER
3460 if (patch[dev] && *patch[dev]) {
445a51b3
DB		 3461 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3462 pci_name(pci), patch[dev]);
5cb543db
TI		 3463 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3464 &pci->dev, GFP_KERNEL, card,
3465 azx_firmware_cb);
4918cdab
TI		 3466 if (err < 0)
3467 goto out_free;
5cb543db 3468 probe_now = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 3469 }
3470#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3471
5cb543db 3472 if (probe_now) {
a82d51ed
TI		 3473 err = azx_probe_continue(chip);
3474 if (err < 0)
3475 goto out_free;
3476 }
3477
b8dfc462
ML		 3478 if (pci_dev_run_wake(pci))
3479 pm_runtime_put_noidle(&pci->dev);
3480
a82d51ed 3481 dev++;
f4c482a4 3482 complete(&chip->probe_wait);
a82d51ed
TI		 3483 return 0;
3484
3485out_free:
3486 snd_card_free(card);
f4c482a4 3487 pci_set_drvdata(pci, NULL);
a82d51ed
TI		 3488 return err;
3489}
3490
48c8b0eb 3491static int azx_probe_continue(struct azx *chip)
a82d51ed
TI		 3492{
3493 int dev = chip->dev_index;
3494 int err;
3495
2dca0bba
JK		 3496#ifdef CONFIG_SND_HDA_INPUT_BEEP
3497 chip->beep_mode = beep_mode[dev];
3498#endif
3499
1da177e4 3500 /* create codec instances */
a1e21c90 3501 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3502 if (err < 0)
3503 goto out_free;
4ea6fbc8 3504#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 3505 if (chip->fw) {
3506 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3507 chip->fw->data);
4ea6fbc8
TI		 3508 if (err < 0)
3509 goto out_free;
e39ae856 3510#ifndef CONFIG_PM
4918cdab
TI		 3511 release_firmware(chip->fw); /* no longer needed */
3512 chip->fw = NULL;
e39ae856 3513#endif
4ea6fbc8
TI		 3514 }
3515#endif
10e77dda 3516 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3517 err = azx_codec_configure(chip);
3518 if (err < 0)
3519 goto out_free;
3520 }
1da177e4
LT		 3521
3522 /* create PCM streams */
176d5335 3523 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3524 if (err < 0)
3525 goto out_free;
1da177e4
LT		 3526
3527 /* create mixer controls */
d01ce99f 3528 err = azx_mixer_create(chip);
41dda0fd
WF		 3529 if (err < 0)
3530 goto out_free;
1da177e4 3531
a82d51ed 3532 err = snd_card_register(chip->card);
41dda0fd
WF		 3533 if (err < 0)
3534 goto out_free;
1da177e4 3535
cb53c626
TI		 3536 chip->running = 1;
3537 power_down_all_codecs(chip);
0cbf0098 3538 azx_notifier_register(chip);
65fcd41d 3539 azx_add_card_list(chip);
1da177e4 3540
9121947d
TI		 3541 return 0;
3542
41dda0fd 3543out_free:
a82d51ed 3544 chip->init_failed = 1;
41dda0fd 3545 return err;
1da177e4
LT		 3546}
3547
e23e7a14 3548static void azx_remove(struct pci_dev *pci)
1da177e4 3549{
9121947d 3550 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462
ML		 3551
3552 if (pci_dev_run_wake(pci))
3553 pm_runtime_get_noresume(&pci->dev);
3554
9121947d
TI		 3555 if (card)
3556 snd_card_free(card);
1da177e4
LT		 3557 pci_set_drvdata(pci, NULL);
3558}
3559
3560/* PCI IDs */
cebe41d4 3561static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3562 /* CPT */
9477c58e 3563 { PCI_DEVICE(0x8086, 0x1c20),
2ea3c6a2 3564 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
cea310e8 3565 /* PBG */
9477c58e 3566 { PCI_DEVICE(0x8086, 0x1d20),
2ea3c6a2 3567 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
d2edeb7c 3568 /* Panther Point */
9477c58e 3569 { PCI_DEVICE(0x8086, 0x1e20),
2ea3c6a2 3570 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
8bc039a1
SH		 3571 /* Lynx Point */
3572 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 3573 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3574 /* Lynx Point-LP */
3575 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 3576 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3577 /* Lynx Point-LP */
3578 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 3579 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8
WX		 3580 /* Haswell */
3581 { PCI_DEVICE(0x8086, 0x0c0c),
2ea3c6a2 3582 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
d279fae8 3583 { PCI_DEVICE(0x8086, 0x0d0c),
2ea3c6a2 3584 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
99df18b3
PLB		 3585 /* 5 Series/3400 */
3586 { PCI_DEVICE(0x8086, 0x3b56),
2ea3c6a2 3587 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
87218e9c 3588 /* SCH */
9477c58e 3589 { PCI_DEVICE(0x8086, 0x811b),
2ae66c26 3590 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
645e9035 3591 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
09904b95
LP		 3592 { PCI_DEVICE(0x8086, 0x080a),
3593 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
716e5db4 3594 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
645e9035 3595 /* ICH */
8b0bd226 3596 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 3597 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3598 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 3599 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 3600 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3601 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 3602 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 3603 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3604 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 3605 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 3606 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3607 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 3608 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 3609 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3610 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3611 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 3612 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3613 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3614 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 3615 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3616 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 3617 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 3618 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3619 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 3620 /* Generic Intel */
3621 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3622 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3623 .class_mask = 0xffffff,
2ae66c26 3624 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 3625 /* ATI SB 450/600/700/800/900 */
3626 { PCI_DEVICE(0x1002, 0x437b),
3627 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3628 { PCI_DEVICE(0x1002, 0x4383),
3629 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3630 /* AMD Hudson */
3631 { PCI_DEVICE(0x1022, 0x780d),
3632 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 3633 /* ATI HDMI */
9477c58e
TI		 3634 { PCI_DEVICE(0x1002, 0x793b),
3635 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3636 { PCI_DEVICE(0x1002, 0x7919),
3637 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3638 { PCI_DEVICE(0x1002, 0x960f),
3639 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3640 { PCI_DEVICE(0x1002, 0x970f),
3641 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3642 { PCI_DEVICE(0x1002, 0xaa00),
3643 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3644 { PCI_DEVICE(0x1002, 0xaa08),
3645 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3646 { PCI_DEVICE(0x1002, 0xaa10),
3647 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3648 { PCI_DEVICE(0x1002, 0xaa18),
3649 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3650 { PCI_DEVICE(0x1002, 0xaa20),
3651 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3652 { PCI_DEVICE(0x1002, 0xaa28),
3653 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3654 { PCI_DEVICE(0x1002, 0xaa30),
3655 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3656 { PCI_DEVICE(0x1002, 0xaa38),
3657 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3658 { PCI_DEVICE(0x1002, 0xaa40),
3659 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3660 { PCI_DEVICE(0x1002, 0xaa48),
3661 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 3662 { PCI_DEVICE(0x1002, 0x9902),
3663 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3664 { PCI_DEVICE(0x1002, 0xaaa0),
3665 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3666 { PCI_DEVICE(0x1002, 0xaaa8),
3667 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3668 { PCI_DEVICE(0x1002, 0xaab0),
3669 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 3670 /* VIA VT8251/VT8237A */
9477c58e
TI		 3671 { PCI_DEVICE(0x1106, 0x3288),
3672 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 3673 /* VIA GFX VT7122/VX900 */
3674 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3675 /* VIA GFX VT6122/VX11 */
3676 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 3677 /* SIS966 */
3678 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3679 /* ULI M5461 */
3680 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3681 /* NVIDIA MCP */
0c2fd1bf
TI		 3682 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3683 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3684 .class_mask = 0xffffff,
9477c58e 3685 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 3686 /* Teradici */
9477c58e
TI		 3687 { PCI_DEVICE(0x6549, 0x1200),
3688 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 3689 { PCI_DEVICE(0x6549, 0x2200),
3690 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 3691 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 3692 /* CTHDA chips */
3693 { PCI_DEVICE(0x1102, 0x0010),
3694 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3695 { PCI_DEVICE(0x1102, 0x0012),
3696 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
313f6e2d
TI		 3697#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3698 /* the following entry conflicts with snd-ctxfi driver,
3699 * as ctxfi driver mutates from HD-audio to native mode with
3700 * a special command sequence.
3701 */
4e01f54b
TI		 3702 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3703 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3704 .class_mask = 0xffffff,
9477c58e 3705 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3706 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 3707#else
3708 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 3709 { PCI_DEVICE(0x1102, 0x0009),
3710 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3711 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 3712#endif
e35d4b11
OS		 3713 /* Vortex86MX */
3714 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 3715 /* VMware HDAudio */
3716 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 3717 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 3718 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3719 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3720 .class_mask = 0xffffff,
9477c58e 3721 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 3722 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3723 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3724 .class_mask = 0xffffff,
9477c58e 3725 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 3726 { 0, }
3727};
3728MODULE_DEVICE_TABLE(pci, azx_ids);
3729
3730/* pci_driver definition */
e9f66d9b 3731static struct pci_driver azx_driver = {
3733e424 3732 .name = KBUILD_MODNAME,
1da177e4
LT		 3733 .id_table = azx_ids,
3734 .probe = azx_probe,
e23e7a14 3735 .remove = azx_remove,
68cb2b55
TI		 3736 .driver = {
3737 .pm = AZX_PM_OPS,
3738 },
1da177e4
LT		 3739};
3740
e9f66d9b 3741module_pci_driver(azx_driver);
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