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ALSA: hda - fix inverted internal mic on Acer AOA150/ZG5
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
0cbf0098 47#include <linux/reboot.h>
27fe48d9 48#include <linux/io.h>
b8dfc462 49#include <linux/pm_runtime.h>
5d890f59
PLB		 50#include <linux/clocksource.h>
51#include <linux/time.h>
f4c482a4 52#include <linux/completion.h>
5d890f59 53
27fe48d9
TI		 54#ifdef CONFIG_X86
55/* for snoop control */
56#include <asm/pgtable.h>
57#include <asm/cacheflush.h>
58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
9121947d 61#include <linux/vgaarb.h>
a82d51ed 62#include <linux/vga_switcheroo.h>
4918cdab 63#include <linux/firmware.h>
1da177e4
LT		 64#include "hda_codec.h"
65
66
5aba4f8e
TI		 67static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
68static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 69static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 70static char *model[SNDRV_CARDS];
1dac6695 71static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 72static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 73static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 74static int probe_only[SNDRV_CARDS];
26a6cb6c 75static int jackpoll_ms[SNDRV_CARDS];
a67ff6a5 76static bool single_cmd;
71623855 77static int enable_msi = -1;
4ea6fbc8
TI		 78#ifdef CONFIG_SND_HDA_PATCH_LOADER
79static char *patch[SNDRV_CARDS];
80#endif
2dca0bba 81#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 82static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 83 CONFIG_SND_HDA_INPUT_BEEP_MODE};
84#endif
1da177e4 85
5aba4f8e 86module_param_array(index, int, NULL, 0444);
1da177e4 87MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 88module_param_array(id, charp, NULL, 0444);
1da177e4 89MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 90module_param_array(enable, bool, NULL, 0444);
91MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
92module_param_array(model, charp, NULL, 0444);
1da177e4 93MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 94module_param_array(position_fix, int, NULL, 0444);
4cb36310 95MODULE_PARM_DESC(position_fix, "DMA pointer read method."
1dac6695 96 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
555e219f
TI		 97module_param_array(bdl_pos_adj, int, NULL, 0644);
98MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 99module_param_array(probe_mask, int, NULL, 0444);
606ad75f 100MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 101module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 102MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 103module_param_array(jackpoll_ms, int, NULL, 0444);
104MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
27346166 105module_param(single_cmd, bool, 0444);
d01ce99f
TI		 106MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
107 "(for debugging only).");
ac9ef6cf 108module_param(enable_msi, bint, 0444);
134a11f0 109MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 110#ifdef CONFIG_SND_HDA_PATCH_LOADER
111module_param_array(patch, charp, NULL, 0444);
112MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
113#endif
2dca0bba 114#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 115module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 116MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 117 "(0=off, 1=on) (default=1).");
2dca0bba 118#endif
606ad75f 119
83012a7c 120#ifdef CONFIG_PM
65fcd41d
TI		 121static int param_set_xint(const char *val, const struct kernel_param *kp);
122static struct kernel_param_ops param_ops_xint = {
123 .set = param_set_xint,
124 .get = param_get_int,
125};
126#define param_check_xint param_check_int
127
fee2fba3 128static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 129module_param(power_save, xint, 0644);
fee2fba3
TI		 130MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
131 "(in second, 0 = disable).");
1da177e4 132
dee1b66c
TI		 133/* reset the HD-audio controller in power save mode.
134 * this may give more power-saving, but will take longer time to
135 * wake up.
136 */
a67ff6a5 137static bool power_save_controller = 1;
dee1b66c
TI		 138module_param(power_save_controller, bool, 0644);
139MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
83012a7c 140#endif /* CONFIG_PM */
dee1b66c 141
7bfe059e
TI		 142static int align_buffer_size = -1;
143module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 144MODULE_PARM_DESC(align_buffer_size,
145 "Force buffer and period sizes to be multiple of 128 bytes.");
146
27fe48d9
TI		 147#ifdef CONFIG_X86
148static bool hda_snoop = true;
149module_param_named(snoop, hda_snoop, bool, 0444);
150MODULE_PARM_DESC(snoop, "Enable/disable snooping");
151#define azx_snoop(chip) (chip)->snoop
152#else
153#define hda_snoop true
154#define azx_snoop(chip) true
155#endif
156
157
1da177e4
LT		 158MODULE_LICENSE("GPL");
159MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
160 "{Intel, ICH6M},"
2f1b3818 161 "{Intel, ICH7},"
f5d40b30 162 "{Intel, ESB2},"
d2981393 163 "{Intel, ICH8},"
f9cc8a8b 164 "{Intel, ICH9},"
c34f5a04 165 "{Intel, ICH10},"
b29c2360 166 "{Intel, PCH},"
d2f2fcd2 167 "{Intel, CPT},"
d2edeb7c 168 "{Intel, PPT},"
8bc039a1 169 "{Intel, LPT},"
144dad99 170 "{Intel, LPT_LP},"
e926f2c8 171 "{Intel, HPT},"
cea310e8 172 "{Intel, PBG},"
4979bca9 173 "{Intel, SCH},"
fc20a562 174 "{ATI, SB450},"
89be83f8 175 "{ATI, SB600},"
778b6e1b 176 "{ATI, RS600},"
5b15c95f 177 "{ATI, RS690},"
e6db1119
WL		 178 "{ATI, RS780},"
179 "{ATI, R600},"
2797f724
HRK		 180 "{ATI, RV630},"
181 "{ATI, RV610},"
27da1834
WL		 182 "{ATI, RV670},"
183 "{ATI, RV635},"
184 "{ATI, RV620},"
185 "{ATI, RV770},"
fc20a562 186 "{VIA, VT8251},"
47672310 187 "{VIA, VT8237A},"
07e4ca50
TI		 188 "{SiS, SIS966},"
189 "{ULI, M5461}}");
1da177e4
LT		 190MODULE_DESCRIPTION("Intel HDA driver");
191
4abc1cc2
TI		 192#ifdef CONFIG_SND_VERBOSE_PRINTK
193#define SFX /* nop */
194#else
445a51b3 195#define SFX "hda-intel "
4abc1cc2 196#endif
cb53c626 197
a82d51ed
TI		 198#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
199#ifdef CONFIG_SND_HDA_CODEC_HDMI
200#define SUPPORT_VGA_SWITCHEROO
201#endif
202#endif
203
204
1da177e4
LT		 205/*
206 * registers
207 */
208#define ICH6_REG_GCAP 0x00
b21fadb9
TI		 209#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
210#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
211#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
212#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
213#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
1da177e4
LT		 214#define ICH6_REG_VMIN 0x02
215#define ICH6_REG_VMAJ 0x03
216#define ICH6_REG_OUTPAY 0x04
217#define ICH6_REG_INPAY 0x06
218#define ICH6_REG_GCTL 0x08
8a933ece 219#define ICH6_GCTL_RESET (1 << 0) /* controller reset */
b21fadb9
TI		 220#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
221#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
1da177e4
LT		 222#define ICH6_REG_WAKEEN 0x0c
223#define ICH6_REG_STATESTS 0x0e
224#define ICH6_REG_GSTS 0x10
b21fadb9 225#define ICH6_GSTS_FSTS (1 << 1) /* flush status */
1da177e4
LT		 226#define ICH6_REG_INTCTL 0x20
227#define ICH6_REG_INTSTS 0x24
e5463720 228#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
8b0bd226
TI		 229#define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
230#define ICH6_REG_SSYNC 0x38
1da177e4
LT		 231#define ICH6_REG_CORBLBASE 0x40
232#define ICH6_REG_CORBUBASE 0x44
233#define ICH6_REG_CORBWP 0x48
b21fadb9
TI		 234#define ICH6_REG_CORBRP 0x4a
235#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
1da177e4 236#define ICH6_REG_CORBCTL 0x4c
b21fadb9
TI		 237#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
238#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
1da177e4 239#define ICH6_REG_CORBSTS 0x4d
b21fadb9 240#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
1da177e4
LT		 241#define ICH6_REG_CORBSIZE 0x4e
242
243#define ICH6_REG_RIRBLBASE 0x50
244#define ICH6_REG_RIRBUBASE 0x54
245#define ICH6_REG_RIRBWP 0x58
b21fadb9 246#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
1da177e4
LT		 247#define ICH6_REG_RINTCNT 0x5a
248#define ICH6_REG_RIRBCTL 0x5c
b21fadb9
TI		 249#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
250#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
251#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
1da177e4 252#define ICH6_REG_RIRBSTS 0x5d
b21fadb9
TI		 253#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
254#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
1da177e4
LT		 255#define ICH6_REG_RIRBSIZE 0x5e
256
257#define ICH6_REG_IC 0x60
258#define ICH6_REG_IR 0x64
259#define ICH6_REG_IRS 0x68
260#define ICH6_IRS_VALID (1<<1)
261#define ICH6_IRS_BUSY (1<<0)
262
263#define ICH6_REG_DPLBASE 0x70
264#define ICH6_REG_DPUBASE 0x74
265#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
266
267/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
268enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
269
270/* stream register offsets from stream base */
271#define ICH6_REG_SD_CTL 0x00
272#define ICH6_REG_SD_STS 0x03
273#define ICH6_REG_SD_LPIB 0x04
274#define ICH6_REG_SD_CBL 0x08
275#define ICH6_REG_SD_LVI 0x0c
276#define ICH6_REG_SD_FIFOW 0x0e
277#define ICH6_REG_SD_FIFOSIZE 0x10
278#define ICH6_REG_SD_FORMAT 0x12
279#define ICH6_REG_SD_BDLPL 0x18
280#define ICH6_REG_SD_BDLPU 0x1c
281
282/* PCI space */
283#define ICH6_PCIREG_TCSEL 0x44
284
285/*
286 * other constants
287 */
288
289/* max number of SDs */
07e4ca50 290/* ICH, ATI and VIA have 4 playback and 4 capture */
07e4ca50 291#define ICH6_NUM_CAPTURE 4
07e4ca50
TI		 292#define ICH6_NUM_PLAYBACK 4
293
294/* ULI has 6 playback and 5 capture */
07e4ca50 295#define ULI_NUM_CAPTURE 5
07e4ca50
TI		 296#define ULI_NUM_PLAYBACK 6
297
778b6e1b 298/* ATI HDMI has 1 playback and 0 capture */
778b6e1b 299#define ATIHDMI_NUM_CAPTURE 0
778b6e1b
FK		 300#define ATIHDMI_NUM_PLAYBACK 1
301
f269002e
KY		 302/* TERA has 4 playback and 3 capture */
303#define TERA_NUM_CAPTURE 3
304#define TERA_NUM_PLAYBACK 4
305
07e4ca50
TI		 306/* this number is statically defined for simplicity */
307#define MAX_AZX_DEV 16
308
1da177e4 309/* max number of fragments - we may use more if allocating more pages for BDL */
4ce107b9
TI		 310#define BDL_SIZE 4096
311#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
312#define AZX_MAX_FRAG 32
1da177e4
LT		 313/* max buffer size - no h/w limit, you can increase as you like */
314#define AZX_MAX_BUF_SIZE (1024*1024*1024)
1da177e4
LT		 315
316/* RIRB int mask: overrun[2], response[0] */
317#define RIRB_INT_RESPONSE 0x01
318#define RIRB_INT_OVERRUN 0x04
319#define RIRB_INT_MASK 0x05
320
2f5983f2 321/* STATESTS int mask: S3,SD2,SD1,SD0 */
7445dfc1
WN		 322#define AZX_MAX_CODECS 8
323#define AZX_DEFAULT_CODECS 4
deadff16 324#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
1da177e4
LT		 325
326/* SD_CTL bits */
327#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
328#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
850f0e52
TI		 329#define SD_CTL_STRIPE (3 << 16) /* stripe control */
330#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
331#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
1da177e4
LT		 332#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
333#define SD_CTL_STREAM_TAG_SHIFT 20
334
335/* SD_CTL and SD_STS */
336#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
337#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
338#define SD_INT_COMPLETE 0x04 /* completion interrupt */
d01ce99f
TI		 339#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
340 SD_INT_COMPLETE)
1da177e4
LT		 341
342/* SD_STS */
343#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
344
345/* INTCTL and INTSTS */
d01ce99f
TI		 346#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
347#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
348#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
1da177e4 349
1da177e4
LT		 350/* below are so far hardcoded - should read registers in future */
351#define ICH6_MAX_CORB_ENTRIES 256
352#define ICH6_MAX_RIRB_ENTRIES 256
353
c74db86b
TI		 354/* position fix mode */
355enum {
0be3b5d3 356 POS_FIX_AUTO,
d2e1c973 357 POS_FIX_LPIB,
0be3b5d3 358 POS_FIX_POSBUF,
4cb36310 359 POS_FIX_VIACOMBO,
a6f2fd55 360 POS_FIX_COMBO,
c74db86b 361};
1da177e4 362
f5d40b30 363/* Defines for ATI HD Audio support in SB450 south bridge */
f5d40b30
FL		 364#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
365#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
366
da3fca21
V		 367/* Defines for Nvidia HDA support */
368#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
369#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
320dcc30
PC		 370#define NVIDIA_HDA_ISTRM_COH 0x4d
371#define NVIDIA_HDA_OSTRM_COH 0x4c
372#define NVIDIA_HDA_ENABLE_COHBIT 0x01
f5d40b30 373
90a5ad52
TI		 374/* Defines for Intel SCH HDA snoop control */
375#define INTEL_SCH_HDA_DEVC 0x78
376#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
377
0e153474
JC		 378/* Define IN stream 0 FIFO size offset in VIA controller */
379#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
380/* Define VIA HD Audio Device ID*/
381#define VIA_HDAC_DEVICE_ID 0x3288
382
c4da29ca
YL		 383/* HD Audio class code */
384#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
90a5ad52 385
1da177e4
LT		 386/*
387 */
388
a98f90fd 389struct azx_dev {
4ce107b9 390 struct snd_dma_buffer bdl; /* BDL buffer */
d01ce99f 391 u32 *posbuf; /* position buffer pointer */
1da177e4 392
d01ce99f 393 unsigned int bufsize; /* size of the play buffer in bytes */
9ad593f6 394 unsigned int period_bytes; /* size of the period in bytes */
d01ce99f
TI		 395 unsigned int frags; /* number for period in the play buffer */
396 unsigned int fifo_size; /* FIFO size */
e5463720
JK		 397 unsigned long start_wallclk; /* start + minimum wallclk */
398 unsigned long period_wallclk; /* wallclk for period */
1da177e4 399
d01ce99f 400 void __iomem *sd_addr; /* stream descriptor pointer */
1da177e4 401
d01ce99f 402 u32 sd_int_sta_mask; /* stream int status mask */
1da177e4
LT		 403
404 /* pcm support */
d01ce99f
TI		 405 struct snd_pcm_substream *substream; /* assigned substream,
406 * set in PCM open
407 */
408 unsigned int format_val; /* format value to be set in the
409 * controller and the codec
410 */
1da177e4
LT		 411 unsigned char stream_tag; /* assigned stream */
412 unsigned char index; /* stream index */
d5cf9911 413 int assigned_key; /* last device# key assigned to */
1da177e4 414
927fc866
PM		 415 unsigned int opened :1;
416 unsigned int running :1;
675f25d4 417 unsigned int irq_pending :1;
0e153474
JC		 418 /*
419 * For VIA:
420 * A flag to ensure DMA position is 0
421 * when link position is not greater than FIFO size
422 */
423 unsigned int insufficient :1;
27fe48d9 424 unsigned int wc_marked:1;
915bf29e 425 unsigned int no_period_wakeup:1;
5d890f59
PLB		 426
427 struct timecounter azx_tc;
428 struct cyclecounter azx_cc;
1da177e4
LT		 429};
430
431/* CORB/RIRB */
a98f90fd 432struct azx_rb {
1da177e4
LT		 433 u32 *buf; /* CORB/RIRB buffer
434 * Each CORB entry is 4byte, RIRB is 8byte
435 */
436 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
437 /* for RIRB */
438 unsigned short rp, wp; /* read/write pointers */
deadff16
WF		 439 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
440 u32 res[AZX_MAX_CODECS]; /* last read value */
1da177e4
LT		 441};
442
01b65bfb
TI		 443struct azx_pcm {
444 struct azx *chip;
445 struct snd_pcm *pcm;
446 struct hda_codec *codec;
447 struct hda_pcm_stream *hinfo[2];
448 struct list_head list;
449};
450
a98f90fd
TI		 451struct azx {
452 struct snd_card *card;
1da177e4 453 struct pci_dev *pci;
555e219f 454 int dev_index;
1da177e4 455
07e4ca50
TI		 456 /* chip type specific */
457 int driver_type;
9477c58e 458 unsigned int driver_caps;
07e4ca50
TI		 459 int playback_streams;
460 int playback_index_offset;
461 int capture_streams;
462 int capture_index_offset;
463 int num_streams;
464
1da177e4
LT		 465 /* pci resources */
466 unsigned long addr;
467 void __iomem *remap_addr;
468 int irq;
469
470 /* locks */
471 spinlock_t reg_lock;
62932df8 472 struct mutex open_mutex;
f4c482a4 473 struct completion probe_wait;
1da177e4 474
07e4ca50 475 /* streams (x num_streams) */
a98f90fd 476 struct azx_dev *azx_dev;
1da177e4
LT		 477
478 /* PCM */
01b65bfb 479 struct list_head pcm_list; /* azx_pcm list */
1da177e4
LT		 480
481 /* HD codec */
482 unsigned short codec_mask;
f1eaaeec 483 int codec_probe_mask; /* copied from probe_mask option */
1da177e4 484 struct hda_bus *bus;
2dca0bba 485 unsigned int beep_mode;
1da177e4
LT		 486
487 /* CORB/RIRB */
a98f90fd
TI		 488 struct azx_rb corb;
489 struct azx_rb rirb;
1da177e4 490
4ce107b9 491 /* CORB/RIRB and position buffers */
1da177e4
LT		 492 struct snd_dma_buffer rb;
493 struct snd_dma_buffer posbuf;
c74db86b 494
4918cdab
TI		 495#ifdef CONFIG_SND_HDA_PATCH_LOADER
496 const struct firmware *fw;
497#endif
498
c74db86b 499 /* flags */
beaffc39 500 int position_fix[2]; /* for both playback/capture streams */
1eb6dc7d 501 int poll_count;
cb53c626 502 unsigned int running :1;
927fc866
PM		 503 unsigned int initialized :1;
504 unsigned int single_cmd :1;
505 unsigned int polling_mode :1;
68e7fffc 506 unsigned int msi :1;
a6a950a8 507 unsigned int irq_pending_warned :1;
6ce4a3bc 508 unsigned int probing :1; /* codec probing phase */
27fe48d9 509 unsigned int snoop:1;
52409aa6 510 unsigned int align_buffer_size:1;
a82d51ed
TI		 511 unsigned int region_requested:1;
512
513 /* VGA-switcheroo setup */
514 unsigned int use_vga_switcheroo:1;
128960a9 515 unsigned int vga_switcheroo_registered:1;
a82d51ed
TI		 516 unsigned int init_failed:1; /* delayed init failed */
517 unsigned int disabled:1; /* disabled by VGA-switcher */
43bbb6cc
TI		 518
519 /* for debugging */
feb27340 520 unsigned int last_cmd[AZX_MAX_CODECS];
9ad593f6
TI		 521
522 /* for pending irqs */
523 struct work_struct irq_pending_work;
0cbf0098
TI		 524
525 /* reboot notifier (for mysterious hangup problem at power-down) */
526 struct notifier_block reboot_notifier;
65fcd41d
TI		 527
528 /* card list (for power_save trigger) */
529 struct list_head list;
1da177e4
LT		 530};
531
1a8506d4
TI		 532#define CREATE_TRACE_POINTS
533#include "hda_intel_trace.h"
534
07e4ca50
TI		 535/* driver types */
536enum {
537 AZX_DRIVER_ICH,
32679f95 538 AZX_DRIVER_PCH,
4979bca9 539 AZX_DRIVER_SCH,
07e4ca50 540 AZX_DRIVER_ATI,
778b6e1b 541 AZX_DRIVER_ATIHDMI,
1815b34a 542 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 543 AZX_DRIVER_VIA,
544 AZX_DRIVER_SIS,
545 AZX_DRIVER_ULI,
da3fca21 546 AZX_DRIVER_NVIDIA,
f269002e 547 AZX_DRIVER_TERA,
14d34f16 548 AZX_DRIVER_CTX,
5ae763b1 549 AZX_DRIVER_CTHDA,
c4da29ca 550 AZX_DRIVER_GENERIC,
2f5983f2 551 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 552};
553
9477c58e
TI		 554/* driver quirks (capabilities) */
555/* bits 0-7 are used for indicating driver type */
556#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
557#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
558#define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
559#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
560#define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
561#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
562#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
563#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
564#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
565#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
566#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
567#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
8b0bd226 568#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
2ae66c26 569#define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
7bfe059e 570#define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
5ae763b1 571#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
90accc58 572#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
2ea3c6a2
TI		 573#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
574
575/* quirks for Intel PCH */
d7dab4db 576#define AZX_DCAPS_INTEL_PCH_NOPM \
2ea3c6a2 577 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
d7dab4db
TI		 578 AZX_DCAPS_COUNT_LPIB_DELAY)
579
580#define AZX_DCAPS_INTEL_PCH \
581 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
9477c58e
TI		 582
583/* quirks for ATI SB / AMD Hudson */
584#define AZX_DCAPS_PRESET_ATI_SB \
585 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
586 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
587
588/* quirks for ATI/AMD HDMI */
589#define AZX_DCAPS_PRESET_ATI_HDMI \
590 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
591
592/* quirks for Nvidia */
593#define AZX_DCAPS_PRESET_NVIDIA \
7bfe059e
TI		 594 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
595 AZX_DCAPS_ALIGN_BUFSIZE)
9477c58e 596
5ae763b1
TI		 597#define AZX_DCAPS_PRESET_CTHDA \
598 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
599
a82d51ed
TI		 600/*
601 * VGA-switcher support
602 */
603#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 604#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
605#else
606#define use_vga_switcheroo(chip) 0
607#endif
608
48c8b0eb 609static char *driver_short_names[] = {
07e4ca50 610 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 611 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 612 [AZX_DRIVER_SCH] = "HDA Intel MID",
07e4ca50 613 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 614 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 615 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 616 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
617 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 618 [AZX_DRIVER_ULI] = "HDA ULI M5461",
619 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 620 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 621 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 622 [AZX_DRIVER_CTHDA] = "HDA Creative",
c4da29ca 623 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 624};
625
1da177e4
LT		 626/*
627 * macros for easy use
628 */
629#define azx_writel(chip,reg,value) \
630 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
631#define azx_readl(chip,reg) \
632 readl((chip)->remap_addr + ICH6_REG_##reg)
633#define azx_writew(chip,reg,value) \
634 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
635#define azx_readw(chip,reg) \
636 readw((chip)->remap_addr + ICH6_REG_##reg)
637#define azx_writeb(chip,reg,value) \
638 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
639#define azx_readb(chip,reg) \
640 readb((chip)->remap_addr + ICH6_REG_##reg)
641
642#define azx_sd_writel(dev,reg,value) \
643 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
644#define azx_sd_readl(dev,reg) \
645 readl((dev)->sd_addr + ICH6_REG_##reg)
646#define azx_sd_writew(dev,reg,value) \
647 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
648#define azx_sd_readw(dev,reg) \
649 readw((dev)->sd_addr + ICH6_REG_##reg)
650#define azx_sd_writeb(dev,reg,value) \
651 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
652#define azx_sd_readb(dev,reg) \
653 readb((dev)->sd_addr + ICH6_REG_##reg)
654
655/* for pcm support */
a98f90fd 656#define get_azx_dev(substream) (substream->runtime->private_data)
1da177e4 657
27fe48d9
TI		 658#ifdef CONFIG_X86
659static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
660{
661 if (azx_snoop(chip))
662 return;
663 if (addr && size) {
664 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
665 if (on)
666 set_memory_wc((unsigned long)addr, pages);
667 else
668 set_memory_wb((unsigned long)addr, pages);
669 }
670}
671
672static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
673 bool on)
674{
675 __mark_pages_wc(chip, buf->area, buf->bytes, on);
676}
677static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
678 struct snd_pcm_runtime *runtime, bool on)
679{
680 if (azx_dev->wc_marked != on) {
681 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
682 azx_dev->wc_marked = on;
683 }
684}
685#else
686/* NOP for other archs */
687static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
688 bool on)
689{
690}
691static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
692 struct snd_pcm_runtime *runtime, bool on)
693{
694}
695#endif
696
68e7fffc 697static int azx_acquire_irq(struct azx *chip, int do_disconnect);
1eb6dc7d 698static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
1da177e4
LT		 699/*
700 * Interface for HD codec
701 */
702
1da177e4
LT		 703/*
704 * CORB / RIRB interface
705 */
a98f90fd 706static int azx_alloc_cmd_io(struct azx *chip)
1da177e4
LT		 707{
708 int err;
709
710 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
d01ce99f
TI		 711 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
712 snd_dma_pci_data(chip->pci),
1da177e4
LT		 713 PAGE_SIZE, &chip->rb);
714 if (err < 0) {
445a51b3 715 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
1da177e4
LT		 716 return err;
717 }
27fe48d9 718 mark_pages_wc(chip, &chip->rb, true);
1da177e4
LT		 719 return 0;
720}
721
a98f90fd 722static void azx_init_cmd_io(struct azx *chip)
1da177e4 723{
cdb1fbf2 724 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 725 /* CORB set up */
726 chip->corb.addr = chip->rb.addr;
727 chip->corb.buf = (u32 *)chip->rb.area;
728 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766979e0 729 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
1da177e4 730
07e4ca50
TI		 731 /* set the corb size to 256 entries (ULI requires explicitly) */
732 azx_writeb(chip, CORBSIZE, 0x02);
1da177e4
LT		 733 /* set the corb write pointer to 0 */
734 azx_writew(chip, CORBWP, 0);
735 /* reset the corb hw read pointer */
b21fadb9 736 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
1da177e4 737 /* enable corb dma */
b21fadb9 738 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
1da177e4
LT		 739
740 /* RIRB set up */
741 chip->rirb.addr = chip->rb.addr + 2048;
742 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
deadff16
WF		 743 chip->rirb.wp = chip->rirb.rp = 0;
744 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
1da177e4 745 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
766979e0 746 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
1da177e4 747
07e4ca50
TI		 748 /* set the rirb size to 256 entries (ULI requires explicitly) */
749 azx_writeb(chip, RIRBSIZE, 0x02);
1da177e4 750 /* reset the rirb hw write pointer */
b21fadb9 751 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
1da177e4 752 /* set N=1, get RIRB response interrupt for new entry */
9477c58e 753 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
14d34f16
TI		 754 azx_writew(chip, RINTCNT, 0xc0);
755 else
756 azx_writew(chip, RINTCNT, 1);
1da177e4 757 /* enable rirb dma and response irq */
1da177e4 758 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
cdb1fbf2 759 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 760}
761
a98f90fd 762static void azx_free_cmd_io(struct azx *chip)
1da177e4 763{
cdb1fbf2 764 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 765 /* disable ringbuffer DMAs */
766 azx_writeb(chip, RIRBCTL, 0);
767 azx_writeb(chip, CORBCTL, 0);
cdb1fbf2 768 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 769}
770
deadff16
WF		 771static unsigned int azx_command_addr(u32 cmd)
772{
773 unsigned int addr = cmd >> 28;
774
775 if (addr >= AZX_MAX_CODECS) {
776 snd_BUG();
777 addr = 0;
778 }
779
780 return addr;
781}
782
783static unsigned int azx_response_addr(u32 res)
784{
785 unsigned int addr = res & 0xf;
786
787 if (addr >= AZX_MAX_CODECS) {
788 snd_BUG();
789 addr = 0;
790 }
791
792 return addr;
1da177e4
LT		 793}
794
795/* send a command */
33fa35ed 796static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 797{
33fa35ed 798 struct azx *chip = bus->private_data;
deadff16 799 unsigned int addr = azx_command_addr(val);
1da177e4 800 unsigned int wp;
1da177e4 801
c32649fe
WF		 802 spin_lock_irq(&chip->reg_lock);
803
1da177e4 804 /* add command to corb */
cc5ede3e
TI		 805 wp = azx_readw(chip, CORBWP);
806 if (wp == 0xffff) {
807 /* something wrong, controller likely turned to D3 */
808 spin_unlock_irq(&chip->reg_lock);
809 return -1;
810 }
1da177e4
LT		 811 wp++;
812 wp %= ICH6_MAX_CORB_ENTRIES;
813
deadff16 814 chip->rirb.cmds[addr]++;
1da177e4
LT		 815 chip->corb.buf[wp] = cpu_to_le32(val);
816 azx_writel(chip, CORBWP, wp);
c32649fe 817
1da177e4
LT		 818 spin_unlock_irq(&chip->reg_lock);
819
820 return 0;
821}
822
823#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
824
825/* retrieve RIRB entry - called from interrupt handler */
a98f90fd 826static void azx_update_rirb(struct azx *chip)
1da177e4
LT		 827{
828 unsigned int rp, wp;
deadff16 829 unsigned int addr;
1da177e4
LT		 830 u32 res, res_ex;
831
cc5ede3e
TI		 832 wp = azx_readw(chip, RIRBWP);
833 if (wp == 0xffff) {
834 /* something wrong, controller likely turned to D3 */
835 return;
836 }
837
1da177e4
LT		 838 if (wp == chip->rirb.wp)
839 return;
840 chip->rirb.wp = wp;
deadff16 841
1da177e4
LT		 842 while (chip->rirb.rp != wp) {
843 chip->rirb.rp++;
844 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
845
846 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
847 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
848 res = le32_to_cpu(chip->rirb.buf[rp]);
deadff16 849 addr = azx_response_addr(res_ex);
1da177e4
LT		 850 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
851 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
deadff16
WF		 852 else if (chip->rirb.cmds[addr]) {
853 chip->rirb.res[addr] = res;
2add9b92 854 smp_wmb();
deadff16 855 chip->rirb.cmds[addr]--;
e310bb06 856 } else
9e3d352b 857 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
e310bb06 858 "last cmd=%#08x\n",
9e3d352b 859 pci_name(chip->pci),
e310bb06
WF		 860 res, res_ex,
861 chip->last_cmd[addr]);
1da177e4
LT		 862 }
863}
864
865/* receive a response */
deadff16
WF		 866static unsigned int azx_rirb_get_response(struct hda_bus *bus,
867 unsigned int addr)
1da177e4 868{
33fa35ed 869 struct azx *chip = bus->private_data;
5c79b1f8 870 unsigned long timeout;
32cf4023 871 unsigned long loopcounter;
1eb6dc7d 872 int do_poll = 0;
1da177e4 873
5c79b1f8
TI		 874 again:
875 timeout = jiffies + msecs_to_jiffies(1000);
32cf4023
DH		 876
877 for (loopcounter = 0;; loopcounter++) {
1eb6dc7d 878 if (chip->polling_mode || do_poll) {
e96224ae
TI		 879 spin_lock_irq(&chip->reg_lock);
880 azx_update_rirb(chip);
881 spin_unlock_irq(&chip->reg_lock);
882 }
deadff16 883 if (!chip->rirb.cmds[addr]) {
2add9b92 884 smp_rmb();
b613291f 885 bus->rirb_error = 0;
1eb6dc7d
ML		 886
887 if (!do_poll)
888 chip->poll_count = 0;
deadff16 889 return chip->rirb.res[addr]; /* the last value */
2add9b92 890 }
28a0d9df
TI		 891 if (time_after(jiffies, timeout))
892 break;
32cf4023 893 if (bus->needs_damn_long_delay || loopcounter > 3000)
52987656
TI		 894 msleep(2); /* temporary workaround */
895 else {
896 udelay(10);
897 cond_resched();
898 }
28a0d9df 899 }
5c79b1f8 900
1eb6dc7d 901 if (!chip->polling_mode && chip->poll_count < 2) {
445a51b3 902 snd_printdd(SFX "%s: azx_get_response timeout, "
1eb6dc7d 903 "polling the codec once: last cmd=0x%08x\n",
445a51b3 904 pci_name(chip->pci), chip->last_cmd[addr]);
1eb6dc7d
ML		 905 do_poll = 1;
906 chip->poll_count++;
907 goto again;
908 }
909
910
23c4a881 911 if (!chip->polling_mode) {
445a51b3 912 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
23c4a881 913 "switching to polling mode: last cmd=0x%08x\n",
445a51b3 914 pci_name(chip->pci), chip->last_cmd[addr]);
23c4a881
TI		 915 chip->polling_mode = 1;
916 goto again;
917 }
918
68e7fffc 919 if (chip->msi) {
445a51b3 920 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
feb27340 921 "disabling MSI: last cmd=0x%08x\n",
445a51b3 922 pci_name(chip->pci), chip->last_cmd[addr]);
68e7fffc
TI		 923 free_irq(chip->irq, chip);
924 chip->irq = -1;
925 pci_disable_msi(chip->pci);
926 chip->msi = 0;
b613291f
TI		 927 if (azx_acquire_irq(chip, 1) < 0) {
928 bus->rirb_error = 1;
68e7fffc 929 return -1;
b613291f 930 }
68e7fffc
TI		 931 goto again;
932 }
933
6ce4a3bc
TI		 934 if (chip->probing) {
935 /* If this critical timeout happens during the codec probing
936 * phase, this is likely an access to a non-existing codec
937 * slot. Better to return an error and reset the system.
938 */
939 return -1;
940 }
941
8dd78330
TI		 942 /* a fatal communication error; need either to reset or to fallback
943 * to the single_cmd mode
944 */
b613291f 945 bus->rirb_error = 1;
b20f3b83 946 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
8dd78330
TI		 947 bus->response_reset = 1;
948 return -1; /* give a chance to retry */
949 }
950
951 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
952 "switching to single_cmd mode: last cmd=0x%08x\n",
feb27340 953 chip->last_cmd[addr]);
8dd78330
TI		 954 chip->single_cmd = 1;
955 bus->response_reset = 0;
1a696978 956 /* release CORB/RIRB */
4fcd3920 957 azx_free_cmd_io(chip);
1a696978
TI		 958 /* disable unsolicited responses */
959 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
5c79b1f8 960 return -1;
1da177e4
LT		 961}
962
1da177e4
LT		 963/*
964 * Use the single immediate command instead of CORB/RIRB for simplicity
965 *
966 * Note: according to Intel, this is not preferred use. The command was
967 * intended for the BIOS only, and may get confused with unsolicited
968 * responses. So, we shouldn't use it for normal operation from the
969 * driver.
970 * I left the codes, however, for debugging/testing purposes.
971 */
972
b05a7d4f 973/* receive a response */
deadff16 974static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
b05a7d4f
TI		 975{
976 int timeout = 50;
977
978 while (timeout--) {
979 /* check IRV busy bit */
980 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
981 /* reuse rirb.res as the response return value */
deadff16 982 chip->rirb.res[addr] = azx_readl(chip, IR);
b05a7d4f
TI		 983 return 0;
984 }
985 udelay(1);
986 }
987 if (printk_ratelimit())
445a51b3
DB		 988 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
989 pci_name(chip->pci), azx_readw(chip, IRS));
deadff16 990 chip->rirb.res[addr] = -1;
b05a7d4f
TI		 991 return -EIO;
992}
993
1da177e4 994/* send a command */
33fa35ed 995static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1da177e4 996{
33fa35ed 997 struct azx *chip = bus->private_data;
deadff16 998 unsigned int addr = azx_command_addr(val);
1da177e4
LT		 999 int timeout = 50;
1000
8dd78330 1001 bus->rirb_error = 0;
1da177e4
LT		 1002 while (timeout--) {
1003 /* check ICB busy bit */
d01ce99f 1004 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1da177e4 1005 /* Clear IRV valid bit */
d01ce99f
TI		 1006 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1007 ICH6_IRS_VALID);
1da177e4 1008 azx_writel(chip, IC, val);
d01ce99f
TI		 1009 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1010 ICH6_IRS_BUSY);
deadff16 1011 return azx_single_wait_for_response(chip, addr);
1da177e4
LT		 1012 }
1013 udelay(1);
1014 }
1cfd52bc 1015 if (printk_ratelimit())
445a51b3
DB		 1016 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1017 pci_name(chip->pci), azx_readw(chip, IRS), val);
1da177e4
LT		 1018 return -EIO;
1019}
1020
1021/* receive a response */
deadff16
WF		 1022static unsigned int azx_single_get_response(struct hda_bus *bus,
1023 unsigned int addr)
1da177e4 1024{
33fa35ed 1025 struct azx *chip = bus->private_data;
deadff16 1026 return chip->rirb.res[addr];
1da177e4
LT		 1027}
1028
111d3af5
TI		 1029/*
1030 * The below are the main callbacks from hda_codec.
1031 *
1032 * They are just the skeleton to call sub-callbacks according to the
1033 * current setting of chip->single_cmd.
1034 */
1035
1036/* send a command */
33fa35ed 1037static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
111d3af5 1038{
33fa35ed 1039 struct azx *chip = bus->private_data;
43bbb6cc 1040
a82d51ed
TI		 1041 if (chip->disabled)
1042 return 0;
feb27340 1043 chip->last_cmd[azx_command_addr(val)] = val;
111d3af5 1044 if (chip->single_cmd)
33fa35ed 1045 return azx_single_send_cmd(bus, val);
111d3af5 1046 else
33fa35ed 1047 return azx_corb_send_cmd(bus, val);
111d3af5
TI		 1048}
1049
1050/* get a response */
deadff16
WF		 1051static unsigned int azx_get_response(struct hda_bus *bus,
1052 unsigned int addr)
111d3af5 1053{
33fa35ed 1054 struct azx *chip = bus->private_data;
a82d51ed
TI		 1055 if (chip->disabled)
1056 return 0;
111d3af5 1057 if (chip->single_cmd)
deadff16 1058 return azx_single_get_response(bus, addr);
111d3af5 1059 else
deadff16 1060 return azx_rirb_get_response(bus, addr);
111d3af5
TI		 1061}
1062
83012a7c 1063#ifdef CONFIG_PM
68467f51 1064static void azx_power_notify(struct hda_bus *bus, bool power_up);
cb53c626 1065#endif
111d3af5 1066
1da177e4 1067/* reset codec link */
cd508fe5 1068static int azx_reset(struct azx *chip, int full_reset)
1da177e4 1069{
fa348da5 1070 unsigned long timeout;
1da177e4 1071
cd508fe5
JK		 1072 if (!full_reset)
1073 goto __skip;
1074
e8a7f136
DT		 1075 /* clear STATESTS */
1076 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1077
1da177e4
LT		 1078 /* reset controller */
1079 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1080
fa348da5
ML		 1081 timeout = jiffies + msecs_to_jiffies(100);
1082 while (azx_readb(chip, GCTL) &&
1083 time_before(jiffies, timeout))
1084 usleep_range(500, 1000);
1da177e4
LT		 1085
1086 /* delay for >= 100us for codec PLL to settle per spec
1087 * Rev 0.9 section 5.5.1
1088 */
fa348da5 1089 usleep_range(500, 1000);
1da177e4
LT		 1090
1091 /* Bring controller out of reset */
1092 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1093
fa348da5
ML		 1094 timeout = jiffies + msecs_to_jiffies(100);
1095 while (!azx_readb(chip, GCTL) &&
1096 time_before(jiffies, timeout))
1097 usleep_range(500, 1000);
1da177e4 1098
927fc866 1099 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
fa348da5 1100 usleep_range(1000, 1200);
1da177e4 1101
cd508fe5 1102 __skip:
1da177e4 1103 /* check to see if controller is ready */
927fc866 1104 if (!azx_readb(chip, GCTL)) {
445a51b3 1105 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1da177e4
LT		 1106 return -EBUSY;
1107 }
1108
41e2fce4 1109 /* Accept unsolicited responses */
1a696978
TI		 1110 if (!chip->single_cmd)
1111 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1112 ICH6_GCTL_UNSOL);
41e2fce4 1113
1da177e4 1114 /* detect codecs */
927fc866 1115 if (!chip->codec_mask) {
1da177e4 1116 chip->codec_mask = azx_readw(chip, STATESTS);
445a51b3 1117 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1da177e4
LT		 1118 }
1119
1120 return 0;
1121}
1122
1123
1124/*
1125 * Lowlevel interface
1126 */
1127
1128/* enable interrupts */
a98f90fd 1129static void azx_int_enable(struct azx *chip)
1da177e4
LT		 1130{
1131 /* enable controller CIE and GIE */
1132 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1133 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1134}
1135
1136/* disable interrupts */
a98f90fd 1137static void azx_int_disable(struct azx *chip)
1da177e4
LT		 1138{
1139 int i;
1140
1141 /* disable interrupts in stream descriptor */
07e4ca50 1142 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1143 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1144 azx_sd_writeb(azx_dev, SD_CTL,
1145 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1146 }
1147
1148 /* disable SIE for all streams */
1149 azx_writeb(chip, INTCTL, 0);
1150
1151 /* disable controller CIE and GIE */
1152 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1153 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1154}
1155
1156/* clear interrupts */
a98f90fd 1157static void azx_int_clear(struct azx *chip)
1da177e4
LT		 1158{
1159 int i;
1160
1161 /* clear stream status */
07e4ca50 1162 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 1163 struct azx_dev *azx_dev = &chip->azx_dev[i];
1da177e4
LT		 1164 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1165 }
1166
1167 /* clear STATESTS */
1168 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1169
1170 /* clear rirb status */
1171 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1172
1173 /* clear int status */
1174 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1175}
1176
1177/* start a stream */
a98f90fd 1178static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1179{
0e153474
JC		 1180 /*
1181 * Before stream start, initialize parameter
1182 */
1183 azx_dev->insufficient = 1;
1184
1da177e4 1185 /* enable SIE */
ccc5df05
WN		 1186 azx_writel(chip, INTCTL,
1187 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1da177e4
LT		 1188 /* set DMA start and interrupt mask */
1189 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1190 SD_CTL_DMA_START | SD_INT_MASK);
1191}
1192
1dddab40
TI		 1193/* stop DMA */
1194static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1da177e4 1195{
1da177e4
LT		 1196 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1197 ~(SD_CTL_DMA_START | SD_INT_MASK));
1198 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1dddab40
TI		 1199}
1200
1201/* stop a stream */
1202static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1203{
1204 azx_stream_clear(chip, azx_dev);
1da177e4 1205 /* disable SIE */
ccc5df05
WN		 1206 azx_writel(chip, INTCTL,
1207 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1da177e4
LT		 1208}
1209
1210
1211/*
cb53c626 1212 * reset and start the controller registers
1da177e4 1213 */
cd508fe5 1214static void azx_init_chip(struct azx *chip, int full_reset)
1da177e4 1215{
cb53c626
TI		 1216 if (chip->initialized)
1217 return;
1da177e4
LT		 1218
1219 /* reset controller */
cd508fe5 1220 azx_reset(chip, full_reset);
1da177e4
LT		 1221
1222 /* initialize interrupts */
1223 azx_int_clear(chip);
1224 azx_int_enable(chip);
1225
1226 /* initialize the codec command I/O */
1a696978
TI		 1227 if (!chip->single_cmd)
1228 azx_init_cmd_io(chip);
1da177e4 1229
0be3b5d3
TI		 1230 /* program the position buffer */
1231 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
766979e0 1232 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
f5d40b30 1233
cb53c626
TI		 1234 chip->initialized = 1;
1235}
1236
1237/*
1238 * initialize the PCI registers
1239 */
1240/* update bits in a PCI register byte */
1241static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1242 unsigned char mask, unsigned char val)
1243{
1244 unsigned char data;
1245
1246 pci_read_config_byte(pci, reg, &data);
1247 data &= ~mask;
1248 data |= (val & mask);
1249 pci_write_config_byte(pci, reg, data);
1250}
1251
1252static void azx_init_pci(struct azx *chip)
1253{
1254 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1255 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1256 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 1257 * codecs.
1258 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 1259 */
46f2cc80 1260 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
445a51b3 1261 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
a09e89f6 1262 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
9477c58e 1263 }
cb53c626 1264
9477c58e
TI		 1265 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1266 * we need to enable snoop.
1267 */
1268 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
445a51b3 1269 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626 1270 update_pci_byte(chip->pci,
27fe48d9
TI		 1271 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1272 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 1273 }
1274
1275 /* For NVIDIA HDA, enable snoop */
1276 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
445a51b3 1277 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
cb53c626
TI		 1278 update_pci_byte(chip->pci,
1279 NVIDIA_HDA_TRANSREG_ADDR,
1280 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 1281 update_pci_byte(chip->pci,
1282 NVIDIA_HDA_ISTRM_COH,
1283 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1284 update_pci_byte(chip->pci,
1285 NVIDIA_HDA_OSTRM_COH,
1286 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 1287 }
1288
1289 /* Enable SCH/PCH snoop if needed */
1290 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
27fe48d9 1291 unsigned short snoop;
90a5ad52 1292 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 1293 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1294 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1295 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1296 if (!azx_snoop(chip))
1297 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1298 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 1299 pci_read_config_word(chip->pci,
1300 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 1301 }
445a51b3
DB		 1302 snd_printdd(SFX "%s: SCH snoop: %s\n",
1303 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
27fe48d9 1304 ? "Disabled" : "Enabled");
da3fca21 1305 }
1da177e4
LT		 1306}
1307
1308
9ad593f6
TI		 1309static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1310
1da177e4
LT		 1311/*
1312 * interrupt handler
1313 */
7d12e780 1314static irqreturn_t azx_interrupt(int irq, void *dev_id)
1da177e4 1315{
a98f90fd
TI		 1316 struct azx *chip = dev_id;
1317 struct azx_dev *azx_dev;
1da177e4 1318 u32 status;
9ef04066 1319 u8 sd_status;
fa00e046 1320 int i, ok;
1da177e4 1321
b8dfc462
ML		 1322#ifdef CONFIG_PM_RUNTIME
1323 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1324 return IRQ_NONE;
1325#endif
1326
1da177e4
LT		 1327 spin_lock(&chip->reg_lock);
1328
60911062
DC		 1329 if (chip->disabled) {
1330 spin_unlock(&chip->reg_lock);
a82d51ed 1331 return IRQ_NONE;
60911062 1332 }
a82d51ed 1333
1da177e4
LT		 1334 status = azx_readl(chip, INTSTS);
1335 if (status == 0) {
1336 spin_unlock(&chip->reg_lock);
1337 return IRQ_NONE;
1338 }
1339
07e4ca50 1340 for (i = 0; i < chip->num_streams; i++) {
1da177e4
LT		 1341 azx_dev = &chip->azx_dev[i];
1342 if (status & azx_dev->sd_int_sta_mask) {
9ef04066 1343 sd_status = azx_sd_readb(azx_dev, SD_STS);
1da177e4 1344 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
9ef04066
CL		 1345 if (!azx_dev->substream || !azx_dev->running ||
1346 !(sd_status & SD_INT_COMPLETE))
9ad593f6
TI		 1347 continue;
1348 /* check whether this IRQ is really acceptable */
fa00e046
JK		 1349 ok = azx_position_ok(chip, azx_dev);
1350 if (ok == 1) {
9ad593f6 1351 azx_dev->irq_pending = 0;
1da177e4
LT		 1352 spin_unlock(&chip->reg_lock);
1353 snd_pcm_period_elapsed(azx_dev->substream);
1354 spin_lock(&chip->reg_lock);
fa00e046 1355 } else if (ok == 0 && chip->bus && chip->bus->workq) {
9ad593f6
TI		 1356 /* bogus IRQ, process it later */
1357 azx_dev->irq_pending = 1;
6acaed38
TI		 1358 queue_work(chip->bus->workq,
1359 &chip->irq_pending_work);
1da177e4
LT		 1360 }
1361 }
1362 }
1363
1364 /* clear rirb int */
1365 status = azx_readb(chip, RIRBSTS);
1366 if (status & RIRB_INT_MASK) {
14d34f16 1367 if (status & RIRB_INT_RESPONSE) {
9477c58e 1368 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
14d34f16 1369 udelay(80);
1da177e4 1370 azx_update_rirb(chip);
14d34f16 1371 }
1da177e4
LT		 1372 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1373 }
1374
1375#if 0
1376 /* clear state status int */
1377 if (azx_readb(chip, STATESTS) & 0x04)
1378 azx_writeb(chip, STATESTS, 0x04);
1379#endif
1380 spin_unlock(&chip->reg_lock);
1381
1382 return IRQ_HANDLED;
1383}
1384
1385
675f25d4
TI		 1386/*
1387 * set up a BDL entry
1388 */
5ae763b1
TI		 1389static int setup_bdle(struct azx *chip,
1390 struct snd_pcm_substream *substream,
675f25d4
TI		 1391 struct azx_dev *azx_dev, u32 **bdlp,
1392 int ofs, int size, int with_ioc)
1393{
675f25d4
TI		 1394 u32 *bdl = *bdlp;
1395
1396 while (size > 0) {
1397 dma_addr_t addr;
1398 int chunk;
1399
1400 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1401 return -EINVAL;
1402
77a23f26 1403 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
675f25d4
TI		 1404 /* program the address field of the BDL entry */
1405 bdl[0] = cpu_to_le32((u32)addr);
766979e0 1406 bdl[1] = cpu_to_le32(upper_32_bits(addr));
675f25d4 1407 /* program the size field of the BDL entry */
fc4abee8 1408 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
5ae763b1
TI		 1409 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1410 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1411 u32 remain = 0x1000 - (ofs & 0xfff);
1412 if (chunk > remain)
1413 chunk = remain;
1414 }
675f25d4
TI		 1415 bdl[2] = cpu_to_le32(chunk);
1416 /* program the IOC to enable interrupt
1417 * only when the whole fragment is processed
1418 */
1419 size -= chunk;
1420 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1421 bdl += 4;
1422 azx_dev->frags++;
1423 ofs += chunk;
1424 }
1425 *bdlp = bdl;
1426 return ofs;
1427}
1428
1da177e4
LT		 1429/*
1430 * set up BDL entries
1431 */
555e219f
TI		 1432static int azx_setup_periods(struct azx *chip,
1433 struct snd_pcm_substream *substream,
4ce107b9 1434 struct azx_dev *azx_dev)
1da177e4 1435{
4ce107b9
TI		 1436 u32 *bdl;
1437 int i, ofs, periods, period_bytes;
555e219f 1438 int pos_adj;
1da177e4
LT		 1439
1440 /* reset BDL address */
1441 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1442 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1443
97b71c94 1444 period_bytes = azx_dev->period_bytes;
4ce107b9
TI		 1445 periods = azx_dev->bufsize / period_bytes;
1446
1da177e4 1447 /* program the initial BDL entries */
4ce107b9
TI		 1448 bdl = (u32 *)azx_dev->bdl.area;
1449 ofs = 0;
1450 azx_dev->frags = 0;
555e219f 1451 pos_adj = bdl_pos_adj[chip->dev_index];
915bf29e 1452 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
675f25d4 1453 struct snd_pcm_runtime *runtime = substream->runtime;
e785d3d8 1454 int pos_align = pos_adj;
555e219f 1455 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
675f25d4 1456 if (!pos_adj)
e785d3d8
TI		 1457 pos_adj = pos_align;
1458 else
1459 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1460 pos_align;
675f25d4
TI		 1461 pos_adj = frames_to_bytes(runtime, pos_adj);
1462 if (pos_adj >= period_bytes) {
445a51b3
DB		 1463 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1464 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
675f25d4
TI		 1465 pos_adj = 0;
1466 } else {
5ae763b1 1467 ofs = setup_bdle(chip, substream, azx_dev,
915bf29e 1468 &bdl, ofs, pos_adj, true);
675f25d4
TI		 1469 if (ofs < 0)
1470 goto error;
4ce107b9 1471 }
555e219f
TI		 1472 } else
1473 pos_adj = 0;
675f25d4
TI		 1474 for (i = 0; i < periods; i++) {
1475 if (i == periods - 1 && pos_adj)
5ae763b1 1476 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
675f25d4
TI		 1477 period_bytes - pos_adj, 0);
1478 else
5ae763b1 1479 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
7bb8fb70 1480 period_bytes,
915bf29e 1481 !azx_dev->no_period_wakeup);
675f25d4
TI		 1482 if (ofs < 0)
1483 goto error;
1da177e4 1484 }
4ce107b9 1485 return 0;
675f25d4
TI		 1486
1487 error:
445a51b3
DB		 1488 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1489 pci_name(chip->pci), azx_dev->bufsize, period_bytes);
675f25d4 1490 return -EINVAL;
1da177e4
LT		 1491}
1492
1dddab40
TI		 1493/* reset stream */
1494static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1da177e4
LT		 1495{
1496 unsigned char val;
1497 int timeout;
1498
1dddab40
TI		 1499 azx_stream_clear(chip, azx_dev);
1500
d01ce99f
TI		 1501 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1502 SD_CTL_STREAM_RESET);
1da177e4
LT		 1503 udelay(3);
1504 timeout = 300;
1505 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1506 --timeout)
1507 ;
1508 val &= ~SD_CTL_STREAM_RESET;
1509 azx_sd_writeb(azx_dev, SD_CTL, val);
1510 udelay(3);
1511
1512 timeout = 300;
1513 /* waiting for hardware to report that the stream is out of reset */
1514 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1515 --timeout)
1516 ;
fa00e046
JK		 1517
1518 /* reset first position - may not be synced with hw at this time */
1519 *azx_dev->posbuf = 0;
1dddab40 1520}
1da177e4 1521
1dddab40
TI		 1522/*
1523 * set up the SD for streaming
1524 */
1525static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1526{
27fe48d9 1527 unsigned int val;
1dddab40
TI		 1528 /* make sure the run bit is zero for SD */
1529 azx_stream_clear(chip, azx_dev);
1da177e4 1530 /* program the stream_tag */
27fe48d9
TI		 1531 val = azx_sd_readl(azx_dev, SD_CTL);
1532 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1533 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1534 if (!azx_snoop(chip))
1535 val |= SD_CTL_TRAFFIC_PRIO;
1536 azx_sd_writel(azx_dev, SD_CTL, val);
1da177e4
LT		 1537
1538 /* program the length of samples in cyclic buffer */
1539 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1540
1541 /* program the stream format */
1542 /* this value needs to be the same as the one programmed */
1543 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1544
1545 /* program the stream LVI (last valid index) of the BDL */
1546 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1547
1548 /* program the BDL address */
1549 /* lower BDL address */
4ce107b9 1550 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1da177e4 1551 /* upper BDL address */
766979e0 1552 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1da177e4 1553
0be3b5d3 1554 /* enable the position buffer */
4cb36310
DH		 1555 if (chip->position_fix[0] != POS_FIX_LPIB ||
1556 chip->position_fix[1] != POS_FIX_LPIB) {
ee9d6b9a
TI		 1557 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1558 azx_writel(chip, DPLBASE,
1559 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1560 }
c74db86b 1561
1da177e4 1562 /* set the interrupt enable bits in the descriptor control register */
d01ce99f
TI		 1563 azx_sd_writel(azx_dev, SD_CTL,
1564 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1da177e4
LT		 1565
1566 return 0;
1567}
1568
6ce4a3bc
TI		 1569/*
1570 * Probe the given codec address
1571 */
1572static int probe_codec(struct azx *chip, int addr)
1573{
1574 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1575 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1576 unsigned int res;
1577
a678cdee 1578 mutex_lock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1579 chip->probing = 1;
1580 azx_send_cmd(chip->bus, cmd);
deadff16 1581 res = azx_get_response(chip->bus, addr);
6ce4a3bc 1582 chip->probing = 0;
a678cdee 1583 mutex_unlock(&chip->bus->cmd_mutex);
6ce4a3bc
TI		 1584 if (res == -1)
1585 return -EIO;
445a51b3 1586 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
6ce4a3bc
TI		 1587 return 0;
1588}
1589
33fa35ed
TI		 1590static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1591 struct hda_pcm *cpcm);
6ce4a3bc 1592static void azx_stop_chip(struct azx *chip);
1da177e4 1593
8dd78330
TI		 1594static void azx_bus_reset(struct hda_bus *bus)
1595{
1596 struct azx *chip = bus->private_data;
8dd78330
TI		 1597
1598 bus->in_reset = 1;
1599 azx_stop_chip(chip);
cd508fe5 1600 azx_init_chip(chip, 1);
65f75983 1601#ifdef CONFIG_PM
8dd78330 1602 if (chip->initialized) {
01b65bfb
TI		 1603 struct azx_pcm *p;
1604 list_for_each_entry(p, &chip->pcm_list, list)
1605 snd_pcm_suspend_all(p->pcm);
8dd78330
TI		 1606 snd_hda_suspend(chip->bus);
1607 snd_hda_resume(chip->bus);
1608 }
65f75983 1609#endif
8dd78330
TI		 1610 bus->in_reset = 0;
1611}
1612
26a6cb6c
DH		 1613static int get_jackpoll_interval(struct azx *chip)
1614{
1615 int i = jackpoll_ms[chip->dev_index];
1616 unsigned int j;
1617 if (i == 0)
1618 return 0;
1619 if (i < 50 || i > 60000)
1620 j = 0;
1621 else
1622 j = msecs_to_jiffies(i);
1623 if (j == 0)
1624 snd_printk(KERN_WARNING SFX
1625 "jackpoll_ms value out of range: %d\n", i);
1626 return j;
1627}
1628
1da177e4
LT		 1629/*
1630 * Codec initialization
1631 */
1632
2f5983f2 1633/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
48c8b0eb 1634static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
7445dfc1 1635 [AZX_DRIVER_NVIDIA] = 8,
f269002e 1636 [AZX_DRIVER_TERA] = 1,
a9995a35
TI		 1637};
1638
48c8b0eb 1639static int azx_codec_create(struct azx *chip, const char *model)
1da177e4
LT		 1640{
1641 struct hda_bus_template bus_temp;
34c25350
TI		 1642 int c, codecs, err;
1643 int max_slots;
1da177e4
LT		 1644
1645 memset(&bus_temp, 0, sizeof(bus_temp));
1646 bus_temp.private_data = chip;
1647 bus_temp.modelname = model;
1648 bus_temp.pci = chip->pci;
111d3af5
TI		 1649 bus_temp.ops.command = azx_send_cmd;
1650 bus_temp.ops.get_response = azx_get_response;
176d5335 1651 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
8dd78330 1652 bus_temp.ops.bus_reset = azx_bus_reset;
83012a7c 1653#ifdef CONFIG_PM
11cd41b8 1654 bus_temp.power_save = &power_save;
cb53c626
TI		 1655 bus_temp.ops.pm_notify = azx_power_notify;
1656#endif
1da177e4 1657
d01ce99f
TI		 1658 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1659 if (err < 0)
1da177e4
LT		 1660 return err;
1661
9477c58e 1662 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
445a51b3 1663 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
dc9c8e21 1664 chip->bus->needs_damn_long_delay = 1;
9477c58e 1665 }
dc9c8e21 1666
34c25350 1667 codecs = 0;
2f5983f2
TI		 1668 max_slots = azx_max_codecs[chip->driver_type];
1669 if (!max_slots)
7445dfc1 1670 max_slots = AZX_DEFAULT_CODECS;
6ce4a3bc
TI		 1671
1672 /* First try to probe all given codec slots */
1673 for (c = 0; c < max_slots; c++) {
f1eaaeec 1674 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
6ce4a3bc
TI		 1675 if (probe_codec(chip, c) < 0) {
1676 /* Some BIOSen give you wrong codec addresses
1677 * that don't exist
1678 */
4abc1cc2 1679 snd_printk(KERN_WARNING SFX
445a51b3
DB		 1680 "%s: Codec #%d probe error; "
1681 "disabling it...\n", pci_name(chip->pci), c);
6ce4a3bc
TI		 1682 chip->codec_mask &= ~(1 << c);
1683 /* More badly, accessing to a non-existing
1684 * codec often screws up the controller chip,
2448158e 1685 * and disturbs the further communications.
6ce4a3bc
TI		 1686 * Thus if an error occurs during probing,
1687 * better to reset the controller chip to
1688 * get back to the sanity state.
1689 */
1690 azx_stop_chip(chip);
cd508fe5 1691 azx_init_chip(chip, 1);
6ce4a3bc
TI		 1692 }
1693 }
1694 }
1695
d507cd66
TI		 1696 /* AMD chipsets often cause the communication stalls upon certain
1697 * sequence like the pin-detection. It seems that forcing the synced
1698 * access works around the stall. Grrr...
1699 */
9477c58e 1700 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
445a51b3
DB		 1701 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1702 pci_name(chip->pci));
d507cd66
TI		 1703 chip->bus->sync_write = 1;
1704 chip->bus->allow_bus_reset = 1;
1705 }
1706
6ce4a3bc 1707 /* Then create codec instances */
34c25350 1708 for (c = 0; c < max_slots; c++) {
f1eaaeec 1709 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
bccad14e 1710 struct hda_codec *codec;
a1e21c90 1711 err = snd_hda_codec_new(chip->bus, c, &codec);
1da177e4
LT		 1712 if (err < 0)
1713 continue;
26a6cb6c 1714 codec->jackpoll_interval = get_jackpoll_interval(chip);
2dca0bba 1715 codec->beep_mode = chip->beep_mode;
1da177e4 1716 codecs++;
19a982b6
TI		 1717 }
1718 }
1719 if (!codecs) {
445a51b3 1720 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1da177e4
LT		 1721 return -ENXIO;
1722 }
a1e21c90
TI		 1723 return 0;
1724}
1da177e4 1725
a1e21c90 1726/* configure each codec instance */
e23e7a14 1727static int azx_codec_configure(struct azx *chip)
a1e21c90
TI		 1728{
1729 struct hda_codec *codec;
1730 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1731 snd_hda_codec_configure(codec);
1732 }
1da177e4
LT		 1733 return 0;
1734}
1735
1736
1737/*
1738 * PCM support
1739 */
1740
1741/* assign a stream for the PCM */
ef18bede
WF		 1742static inline struct azx_dev *
1743azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1da177e4 1744{
07e4ca50 1745 int dev, i, nums;
ef18bede 1746 struct azx_dev *res = NULL;
d5cf9911
TI		 1747 /* make a non-zero unique key for the substream */
1748 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1749 (substream->stream + 1);
ef18bede
WF		 1750
1751 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
07e4ca50
TI		 1752 dev = chip->playback_index_offset;
1753 nums = chip->playback_streams;
1754 } else {
1755 dev = chip->capture_index_offset;
1756 nums = chip->capture_streams;
1757 }
1758 for (i = 0; i < nums; i++, dev++)
d01ce99f 1759 if (!chip->azx_dev[dev].opened) {
ef18bede 1760 res = &chip->azx_dev[dev];
d5cf9911 1761 if (res->assigned_key == key)
ef18bede 1762 break;
1da177e4 1763 }
ef18bede
WF		 1764 if (res) {
1765 res->opened = 1;
d5cf9911 1766 res->assigned_key = key;
ef18bede
WF		 1767 }
1768 return res;
1da177e4
LT		 1769}
1770
1771/* release the assigned stream */
a98f90fd 1772static inline void azx_release_device(struct azx_dev *azx_dev)
1da177e4
LT		 1773{
1774 azx_dev->opened = 0;
1775}
1776
5d890f59
PLB		 1777static cycle_t azx_cc_read(const struct cyclecounter *cc)
1778{
1779 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1780 struct snd_pcm_substream *substream = azx_dev->substream;
1781 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1782 struct azx *chip = apcm->chip;
1783
1784 return azx_readl(chip, WALLCLK);
1785}
1786
1787static void azx_timecounter_init(struct snd_pcm_substream *substream,
1788 bool force, cycle_t last)
1789{
1790 struct azx_dev *azx_dev = get_azx_dev(substream);
1791 struct timecounter *tc = &azx_dev->azx_tc;
1792 struct cyclecounter *cc = &azx_dev->azx_cc;
1793 u64 nsec;
1794
1795 cc->read = azx_cc_read;
1796 cc->mask = CLOCKSOURCE_MASK(32);
1797
1798 /*
1799 * Converting from 24 MHz to ns means applying a 125/3 factor.
1800 * To avoid any saturation issues in intermediate operations,
1801 * the 125 factor is applied first. The division is applied
1802 * last after reading the timecounter value.
1803 * Applying the 1/3 factor as part of the multiplication
1804 * requires at least 20 bits for a decent precision, however
1805 * overflows occur after about 4 hours or less, not a option.
1806 */
1807
1808 cc->mult = 125; /* saturation after 195 years */
1809 cc->shift = 0;
1810
1811 nsec = 0; /* audio time is elapsed time since trigger */
1812 timecounter_init(tc, cc, nsec);
1813 if (force)
1814 /*
1815 * force timecounter to use predefined value,
1816 * used for synchronized starts
1817 */
1818 tc->cycle_last = last;
1819}
1820
1821static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1822 struct timespec *ts)
1823{
1824 struct azx_dev *azx_dev = get_azx_dev(substream);
1825 u64 nsec;
1826
1827 nsec = timecounter_read(&azx_dev->azx_tc);
1828 nsec = div_u64(nsec, 3); /* can be optimized */
1829
1830 *ts = ns_to_timespec(nsec);
1831
1832 return 0;
1833}
1834
a98f90fd 1835static struct snd_pcm_hardware azx_pcm_hw = {
d01ce99f
TI		 1836 .info = (SNDRV_PCM_INFO_MMAP |
1837 SNDRV_PCM_INFO_INTERLEAVED |
1da177e4
LT		 1838 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1839 SNDRV_PCM_INFO_MMAP_VALID |
927fc866
PM		 1840 /* No full-resume yet implemented */
1841 /* SNDRV_PCM_INFO_RESUME |*/
850f0e52 1842 SNDRV_PCM_INFO_PAUSE |
7bb8fb70 1843 SNDRV_PCM_INFO_SYNC_START |
5d890f59 1844 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
7bb8fb70 1845 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1da177e4
LT		 1846 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1847 .rates = SNDRV_PCM_RATE_48000,
1848 .rate_min = 48000,
1849 .rate_max = 48000,
1850 .channels_min = 2,
1851 .channels_max = 2,
1852 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1853 .period_bytes_min = 128,
1854 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1855 .periods_min = 2,
1856 .periods_max = AZX_MAX_FRAG,
1857 .fifo_size = 0,
1858};
1859
a98f90fd 1860static int azx_pcm_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1861{
1862 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1863 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1864 struct azx *chip = apcm->chip;
1865 struct azx_dev *azx_dev;
1866 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1867 unsigned long flags;
1868 int err;
2ae66c26 1869 int buff_step;
1da177e4 1870
62932df8 1871 mutex_lock(&chip->open_mutex);
ef18bede 1872 azx_dev = azx_assign_device(chip, substream);
1da177e4 1873 if (azx_dev == NULL) {
62932df8 1874 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1875 return -EBUSY;
1876 }
1877 runtime->hw = azx_pcm_hw;
1878 runtime->hw.channels_min = hinfo->channels_min;
1879 runtime->hw.channels_max = hinfo->channels_max;
1880 runtime->hw.formats = hinfo->formats;
1881 runtime->hw.rates = hinfo->rates;
1882 snd_pcm_limit_hw_rates(runtime);
1883 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
5d890f59
PLB		 1884
1885 /* avoid wrap-around with wall-clock */
1886 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1887 20,
1888 178000000);
1889
52409aa6 1890 if (chip->align_buffer_size)
2ae66c26
PLB		 1891 /* constrain buffer sizes to be multiple of 128
1892 bytes. This is more efficient in terms of memory
1893 access but isn't required by the HDA spec and
1894 prevents users from specifying exact period/buffer
1895 sizes. For example for 44.1kHz, a period size set
1896 to 20ms will be rounded to 19.59ms. */
1897 buff_step = 128;
1898 else
1899 /* Don't enforce steps on buffer sizes, still need to
1900 be multiple of 4 bytes (HDA spec). Tested on Intel
1901 HDA controllers, may not work on all devices where
1902 option needs to be disabled */
1903 buff_step = 4;
1904
5f1545bc 1905 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2ae66c26 1906 buff_step);
5f1545bc 1907 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2ae66c26 1908 buff_step);
b4a91cf0 1909 snd_hda_power_up_d3wait(apcm->codec);
d01ce99f
TI		 1910 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1911 if (err < 0) {
1da177e4 1912 azx_release_device(azx_dev);
cb53c626 1913 snd_hda_power_down(apcm->codec);
62932df8 1914 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1915 return err;
1916 }
70d321e6 1917 snd_pcm_limit_hw_rates(runtime);
aba66536
TI		 1918 /* sanity check */
1919 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1920 snd_BUG_ON(!runtime->hw.channels_max) ||
1921 snd_BUG_ON(!runtime->hw.formats) ||
1922 snd_BUG_ON(!runtime->hw.rates)) {
1923 azx_release_device(azx_dev);
1924 hinfo->ops.close(hinfo, apcm->codec, substream);
1925 snd_hda_power_down(apcm->codec);
1926 mutex_unlock(&chip->open_mutex);
1927 return -EINVAL;
1928 }
5d890f59
PLB		 1929
1930 /* disable WALLCLOCK timestamps for capture streams
1931 until we figure out how to handle digital inputs */
1932 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1933 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1934
1da177e4
LT		 1935 spin_lock_irqsave(&chip->reg_lock, flags);
1936 azx_dev->substream = substream;
1937 azx_dev->running = 0;
1938 spin_unlock_irqrestore(&chip->reg_lock, flags);
1939
1940 runtime->private_data = azx_dev;
850f0e52 1941 snd_pcm_set_sync(substream);
62932df8 1942 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1943 return 0;
1944}
1945
a98f90fd 1946static int azx_pcm_close(struct snd_pcm_substream *substream)
1da177e4
LT		 1947{
1948 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1949 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd
TI		 1950 struct azx *chip = apcm->chip;
1951 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4
LT		 1952 unsigned long flags;
1953
62932df8 1954 mutex_lock(&chip->open_mutex);
1da177e4
LT		 1955 spin_lock_irqsave(&chip->reg_lock, flags);
1956 azx_dev->substream = NULL;
1957 azx_dev->running = 0;
1958 spin_unlock_irqrestore(&chip->reg_lock, flags);
1959 azx_release_device(azx_dev);
1960 hinfo->ops.close(hinfo, apcm->codec, substream);
cb53c626 1961 snd_hda_power_down(apcm->codec);
62932df8 1962 mutex_unlock(&chip->open_mutex);
1da177e4
LT		 1963 return 0;
1964}
1965
d01ce99f
TI		 1966static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1967 struct snd_pcm_hw_params *hw_params)
1da177e4 1968{
27fe48d9
TI		 1969 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1970 struct azx *chip = apcm->chip;
1971 struct snd_pcm_runtime *runtime = substream->runtime;
97b71c94 1972 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9 1973 int ret;
97b71c94 1974
27fe48d9 1975 mark_runtime_wc(chip, azx_dev, runtime, false);
97b71c94
TI		 1976 azx_dev->bufsize = 0;
1977 azx_dev->period_bytes = 0;
1978 azx_dev->format_val = 0;
27fe48d9 1979 ret = snd_pcm_lib_malloc_pages(substream,
d01ce99f 1980 params_buffer_bytes(hw_params));
27fe48d9
TI		 1981 if (ret < 0)
1982 return ret;
1983 mark_runtime_wc(chip, azx_dev, runtime, true);
1984 return ret;
1da177e4
LT		 1985}
1986
a98f90fd 1987static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 1988{
1989 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 1990 struct azx_dev *azx_dev = get_azx_dev(substream);
27fe48d9
TI		 1991 struct azx *chip = apcm->chip;
1992 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1993 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1994
1995 /* reset BDL address */
1996 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1997 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1998 azx_sd_writel(azx_dev, SD_CTL, 0);
97b71c94
TI		 1999 azx_dev->bufsize = 0;
2000 azx_dev->period_bytes = 0;
2001 azx_dev->format_val = 0;
1da177e4 2002
eb541337 2003 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1da177e4 2004
27fe48d9 2005 mark_runtime_wc(chip, azx_dev, runtime, false);
1da177e4
LT		 2006 return snd_pcm_lib_free_pages(substream);
2007}
2008
a98f90fd 2009static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4
LT		 2010{
2011 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd
TI		 2012 struct azx *chip = apcm->chip;
2013 struct azx_dev *azx_dev = get_azx_dev(substream);
1da177e4 2014 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
a98f90fd 2015 struct snd_pcm_runtime *runtime = substream->runtime;
62b7e5e0 2016 unsigned int bufsize, period_bytes, format_val, stream_tag;
97b71c94 2017 int err;
7c935976
SW		 2018 struct hda_spdif_out *spdif =
2019 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2020 unsigned short ctls = spdif ? spdif->ctls : 0;
1da177e4 2021
fa00e046 2022 azx_stream_reset(chip, azx_dev);
97b71c94
TI		 2023 format_val = snd_hda_calc_stream_format(runtime->rate,
2024 runtime->channels,
2025 runtime->format,
32c168c8 2026 hinfo->maxbps,
7c935976 2027 ctls);
97b71c94 2028 if (!format_val) {
d01ce99f 2029 snd_printk(KERN_ERR SFX
445a51b3
DB		 2030 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2031 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
1da177e4
LT		 2032 return -EINVAL;
2033 }
2034
97b71c94
TI		 2035 bufsize = snd_pcm_lib_buffer_bytes(substream);
2036 period_bytes = snd_pcm_lib_period_bytes(substream);
2037
445a51b3
DB		 2038 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2039 pci_name(chip->pci), bufsize, format_val);
97b71c94
TI		 2040
2041 if (bufsize != azx_dev->bufsize ||
2042 period_bytes != azx_dev->period_bytes ||
915bf29e
TI		 2043 format_val != azx_dev->format_val ||
2044 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
97b71c94
TI		 2045 azx_dev->bufsize = bufsize;
2046 azx_dev->period_bytes = period_bytes;
2047 azx_dev->format_val = format_val;
915bf29e 2048 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
97b71c94
TI		 2049 err = azx_setup_periods(chip, substream, azx_dev);
2050 if (err < 0)
2051 return err;
2052 }
2053
e5463720
JK		 2054 /* wallclk has 24Mhz clock source */
2055 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2056 runtime->rate) * 1000);
1da177e4
LT		 2057 azx_setup_controller(chip, azx_dev);
2058 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2059 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2060 else
2061 azx_dev->fifo_size = 0;
2062
62b7e5e0
TI		 2063 stream_tag = azx_dev->stream_tag;
2064 /* CA-IBG chips need the playback stream starting from 1 */
9477c58e 2065 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
62b7e5e0
TI		 2066 stream_tag > chip->capture_streams)
2067 stream_tag -= chip->capture_streams;
2068 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
eb541337 2069 azx_dev->format_val, substream);
1da177e4
LT		 2070}
2071
a98f90fd 2072static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4
LT		 2073{
2074 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
a98f90fd 2075 struct azx *chip = apcm->chip;
850f0e52
TI		 2076 struct azx_dev *azx_dev;
2077 struct snd_pcm_substream *s;
fa00e046 2078 int rstart = 0, start, nsync = 0, sbits = 0;
850f0e52 2079 int nwait, timeout;
1da177e4 2080
1a8506d4
TI		 2081 azx_dev = get_azx_dev(substream);
2082 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2083
1da177e4 2084 switch (cmd) {
fa00e046
JK		 2085 case SNDRV_PCM_TRIGGER_START:
2086 rstart = 1;
1da177e4
LT		 2087 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2088 case SNDRV_PCM_TRIGGER_RESUME:
850f0e52 2089 start = 1;
1da177e4
LT		 2090 break;
2091 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
47123197 2092 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4 2093 case SNDRV_PCM_TRIGGER_STOP:
850f0e52 2094 start = 0;
1da177e4
LT		 2095 break;
2096 default:
850f0e52
TI		 2097 return -EINVAL;
2098 }
2099
2100 snd_pcm_group_for_each_entry(s, substream) {
2101 if (s->pcm->card != substream->pcm->card)
2102 continue;
2103 azx_dev = get_azx_dev(s);
2104 sbits |= 1 << azx_dev->index;
2105 nsync++;
2106 snd_pcm_trigger_done(s, substream);
2107 }
2108
2109 spin_lock(&chip->reg_lock);
172d3b20
PLB		 2110
2111 /* first, set SYNC bits of corresponding streams */
2112 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2113 azx_writel(chip, OLD_SSYNC,
2114 azx_readl(chip, OLD_SSYNC) | sbits);
2115 else
2116 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2117
850f0e52
TI		 2118 snd_pcm_group_for_each_entry(s, substream) {
2119 if (s->pcm->card != substream->pcm->card)
2120 continue;
2121 azx_dev = get_azx_dev(s);
e5463720
JK		 2122 if (start) {
2123 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2124 if (!rstart)
2125 azx_dev->start_wallclk -=
2126 azx_dev->period_wallclk;
850f0e52 2127 azx_stream_start(chip, azx_dev);
e5463720 2128 } else {
850f0e52 2129 azx_stream_stop(chip, azx_dev);
e5463720 2130 }
850f0e52 2131 azx_dev->running = start;
1da177e4
LT		 2132 }
2133 spin_unlock(&chip->reg_lock);
850f0e52 2134 if (start) {
850f0e52
TI		 2135 /* wait until all FIFOs get ready */
2136 for (timeout = 5000; timeout; timeout--) {
2137 nwait = 0;
2138 snd_pcm_group_for_each_entry(s, substream) {
2139 if (s->pcm->card != substream->pcm->card)
2140 continue;
2141 azx_dev = get_azx_dev(s);
2142 if (!(azx_sd_readb(azx_dev, SD_STS) &
2143 SD_STS_FIFO_READY))
2144 nwait++;
2145 }
2146 if (!nwait)
2147 break;
2148 cpu_relax();
2149 }
2150 } else {
2151 /* wait until all RUN bits are cleared */
2152 for (timeout = 5000; timeout; timeout--) {
2153 nwait = 0;
2154 snd_pcm_group_for_each_entry(s, substream) {
2155 if (s->pcm->card != substream->pcm->card)
2156 continue;
2157 azx_dev = get_azx_dev(s);
2158 if (azx_sd_readb(azx_dev, SD_CTL) &
2159 SD_CTL_DMA_START)
2160 nwait++;
2161 }
2162 if (!nwait)
2163 break;
2164 cpu_relax();
2165 }
1da177e4 2166 }
172d3b20
PLB		 2167 spin_lock(&chip->reg_lock);
2168 /* reset SYNC bits */
2169 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2170 azx_writel(chip, OLD_SSYNC,
2171 azx_readl(chip, OLD_SSYNC) & ~sbits);
2172 else
2173 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
5d890f59
PLB		 2174 if (start) {
2175 azx_timecounter_init(substream, 0, 0);
2176 if (nsync > 1) {
2177 cycle_t cycle_last;
2178
2179 /* same start cycle for master and group */
2180 azx_dev = get_azx_dev(substream);
2181 cycle_last = azx_dev->azx_tc.cycle_last;
2182
2183 snd_pcm_group_for_each_entry(s, substream) {
2184 if (s->pcm->card != substream->pcm->card)
2185 continue;
2186 azx_timecounter_init(s, 1, cycle_last);
2187 }
2188 }
2189 }
172d3b20 2190 spin_unlock(&chip->reg_lock);
850f0e52 2191 return 0;
1da177e4
LT		 2192}
2193
0e153474
JC		 2194/* get the current DMA position with correction on VIA chips */
2195static unsigned int azx_via_get_position(struct azx *chip,
2196 struct azx_dev *azx_dev)
2197{
2198 unsigned int link_pos, mini_pos, bound_pos;
2199 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2200 unsigned int fifo_size;
2201
2202 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
b4a655e8 2203 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
0e153474
JC		 2204 /* Playback, no problem using link position */
2205 return link_pos;
2206 }
2207
2208 /* Capture */
2209 /* For new chipset,
2210 * use mod to get the DMA position just like old chipset
2211 */
2212 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2213 mod_dma_pos %= azx_dev->period_bytes;
2214
2215 /* azx_dev->fifo_size can't get FIFO size of in stream.
2216 * Get from base address + offset.
2217 */
2218 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2219
2220 if (azx_dev->insufficient) {
2221 /* Link position never gather than FIFO size */
2222 if (link_pos <= fifo_size)
2223 return 0;
2224
2225 azx_dev->insufficient = 0;
2226 }
2227
2228 if (link_pos <= fifo_size)
2229 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2230 else
2231 mini_pos = link_pos - fifo_size;
2232
2233 /* Find nearest previous boudary */
2234 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2235 mod_link_pos = link_pos % azx_dev->period_bytes;
2236 if (mod_link_pos >= fifo_size)
2237 bound_pos = link_pos - mod_link_pos;
2238 else if (mod_dma_pos >= mod_mini_pos)
2239 bound_pos = mini_pos - mod_mini_pos;
2240 else {
2241 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2242 if (bound_pos >= azx_dev->bufsize)
2243 bound_pos = 0;
2244 }
2245
2246 /* Calculate real DMA position we want */
2247 return bound_pos + mod_dma_pos;
2248}
2249
9ad593f6 2250static unsigned int azx_get_position(struct azx *chip,
798cb7e8
TI		 2251 struct azx_dev *azx_dev,
2252 bool with_check)
1da177e4 2253{
1da177e4 2254 unsigned int pos;
4cb36310 2255 int stream = azx_dev->substream->stream;
1a8506d4 2256 int delay = 0;
1da177e4 2257
4cb36310
DH		 2258 switch (chip->position_fix[stream]) {
2259 case POS_FIX_LPIB:
2260 /* read LPIB */
2261 pos = azx_sd_readl(azx_dev, SD_LPIB);
2262 break;
2263 case POS_FIX_VIACOMBO:
0e153474 2264 pos = azx_via_get_position(chip, azx_dev);
4cb36310
DH		 2265 break;
2266 default:
2267 /* use the position buffer */
2268 pos = le32_to_cpu(*azx_dev->posbuf);
798cb7e8 2269 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
a810364a
TI		 2270 if (!pos || pos == (u32)-1) {
2271 printk(KERN_WARNING
2272 "hda-intel: Invalid position buffer, "
2273 "using LPIB read method instead.\n");
2274 chip->position_fix[stream] = POS_FIX_LPIB;
2275 pos = azx_sd_readl(azx_dev, SD_LPIB);
2276 } else
2277 chip->position_fix[stream] = POS_FIX_POSBUF;
2278 }
2279 break;
c74db86b 2280 }
4cb36310 2281
1da177e4
LT		 2282 if (pos >= azx_dev->bufsize)
2283 pos = 0;
90accc58
PLB		 2284
2285 /* calculate runtime delay from LPIB */
2286 if (azx_dev->substream->runtime &&
2287 chip->position_fix[stream] == POS_FIX_POSBUF &&
2288 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2289 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
90accc58
PLB		 2290 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2291 delay = pos - lpib_pos;
2292 else
2293 delay = lpib_pos - pos;
2294 if (delay < 0)
2295 delay += azx_dev->bufsize;
2296 if (delay >= azx_dev->period_bytes) {
1f04661f 2297 snd_printk(KERN_WARNING SFX
445a51b3 2298 "%s: Unstable LPIB (%d >= %d); "
1f04661f 2299 "disabling LPIB delay counting\n",
445a51b3 2300 pci_name(chip->pci), delay, azx_dev->period_bytes);
1f04661f
TI		 2301 delay = 0;
2302 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
90accc58
PLB		 2303 }
2304 azx_dev->substream->runtime->delay =
2305 bytes_to_frames(azx_dev->substream->runtime, delay);
2306 }
1a8506d4 2307 trace_azx_get_position(chip, azx_dev, pos, delay);
9ad593f6
TI		 2308 return pos;
2309}
2310
2311static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2312{
2313 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2314 struct azx *chip = apcm->chip;
2315 struct azx_dev *azx_dev = get_azx_dev(substream);
2316 return bytes_to_frames(substream->runtime,
798cb7e8 2317 azx_get_position(chip, azx_dev, false));
9ad593f6
TI		 2318}
2319
2320/*
2321 * Check whether the current DMA position is acceptable for updating
2322 * periods. Returns non-zero if it's OK.
2323 *
2324 * Many HD-audio controllers appear pretty inaccurate about
2325 * the update-IRQ timing. The IRQ is issued before actually the
2326 * data is processed. So, we need to process it afterwords in a
2327 * workqueue.
2328 */
2329static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2330{
e5463720 2331 u32 wallclk;
9ad593f6
TI		 2332 unsigned int pos;
2333
f48f606d
JK		 2334 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2335 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
fa00e046 2336 return -1; /* bogus (too early) interrupt */
fa00e046 2337
798cb7e8 2338 pos = azx_get_position(chip, azx_dev, true);
9ad593f6 2339
d6d8bf54
TI		 2340 if (WARN_ONCE(!azx_dev->period_bytes,
2341 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 2342 return -1; /* this shouldn't happen! */
edb39935 2343 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
f48f606d
JK		 2344 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2345 /* NG - it's below the first next period boundary */
2346 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
edb39935 2347 azx_dev->start_wallclk += wallclk;
9ad593f6
TI		 2348 return 1; /* OK, it's fine */
2349}
2350
2351/*
2352 * The work for pending PCM period updates.
2353 */
2354static void azx_irq_pending_work(struct work_struct *work)
2355{
2356 struct azx *chip = container_of(work, struct azx, irq_pending_work);
e5463720 2357 int i, pending, ok;
9ad593f6 2358
a6a950a8
TI		 2359 if (!chip->irq_pending_warned) {
2360 printk(KERN_WARNING
2361 "hda-intel: IRQ timing workaround is activated "
2362 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2363 chip->card->number);
2364 chip->irq_pending_warned = 1;
2365 }
2366
9ad593f6
TI		 2367 for (;;) {
2368 pending = 0;
2369 spin_lock_irq(&chip->reg_lock);
2370 for (i = 0; i < chip->num_streams; i++) {
2371 struct azx_dev *azx_dev = &chip->azx_dev[i];
2372 if (!azx_dev->irq_pending ||
2373 !azx_dev->substream ||
2374 !azx_dev->running)
2375 continue;
e5463720
JK		 2376 ok = azx_position_ok(chip, azx_dev);
2377 if (ok > 0) {
9ad593f6
TI		 2378 azx_dev->irq_pending = 0;
2379 spin_unlock(&chip->reg_lock);
2380 snd_pcm_period_elapsed(azx_dev->substream);
2381 spin_lock(&chip->reg_lock);
e5463720
JK		 2382 } else if (ok < 0) {
2383 pending = 0; /* too early */
9ad593f6
TI		 2384 } else
2385 pending++;
2386 }
2387 spin_unlock_irq(&chip->reg_lock);
2388 if (!pending)
2389 return;
08af495f 2390 msleep(1);
9ad593f6
TI		 2391 }
2392}
2393
2394/* clear irq_pending flags and assure no on-going workq */
2395static void azx_clear_irq_pending(struct azx *chip)
2396{
2397 int i;
2398
2399 spin_lock_irq(&chip->reg_lock);
2400 for (i = 0; i < chip->num_streams; i++)
2401 chip->azx_dev[i].irq_pending = 0;
2402 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 2403}
2404
27fe48d9
TI		 2405#ifdef CONFIG_X86
2406static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2407 struct vm_area_struct *area)
2408{
2409 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2410 struct azx *chip = apcm->chip;
2411 if (!azx_snoop(chip))
2412 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2413 return snd_pcm_lib_default_mmap(substream, area);
2414}
2415#else
2416#define azx_pcm_mmap NULL
2417#endif
2418
a98f90fd 2419static struct snd_pcm_ops azx_pcm_ops = {
1da177e4
LT		 2420 .open = azx_pcm_open,
2421 .close = azx_pcm_close,
2422 .ioctl = snd_pcm_lib_ioctl,
2423 .hw_params = azx_pcm_hw_params,
2424 .hw_free = azx_pcm_hw_free,
2425 .prepare = azx_pcm_prepare,
2426 .trigger = azx_pcm_trigger,
2427 .pointer = azx_pcm_pointer,
5d890f59 2428 .wall_clock = azx_get_wallclock_tstamp,
27fe48d9 2429 .mmap = azx_pcm_mmap,
4ce107b9 2430 .page = snd_pcm_sgbuf_ops_page,
1da177e4
LT		 2431};
2432
a98f90fd 2433static void azx_pcm_free(struct snd_pcm *pcm)
1da177e4 2434{
176d5335
TI		 2435 struct azx_pcm *apcm = pcm->private_data;
2436 if (apcm) {
01b65bfb 2437 list_del(&apcm->list);
176d5335
TI		 2438 kfree(apcm);
2439 }
1da177e4
LT		 2440}
2441
acfa634f
TI		 2442#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2443
176d5335 2444static int
33fa35ed
TI		 2445azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2446 struct hda_pcm *cpcm)
1da177e4 2447{
33fa35ed 2448 struct azx *chip = bus->private_data;
a98f90fd 2449 struct snd_pcm *pcm;
1da177e4 2450 struct azx_pcm *apcm;
176d5335 2451 int pcm_dev = cpcm->device;
acfa634f 2452 unsigned int size;
176d5335 2453 int s, err;
1da177e4 2454
01b65bfb
TI		 2455 list_for_each_entry(apcm, &chip->pcm_list, list) {
2456 if (apcm->pcm->device == pcm_dev) {
445a51b3
DB		 2457 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2458 pci_name(chip->pci), pcm_dev);
01b65bfb
TI		 2459 return -EBUSY;
2460 }
176d5335
TI		 2461 }
2462 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2463 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2464 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1da177e4
LT		 2465 &pcm);
2466 if (err < 0)
2467 return err;
18cb7109 2468 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
176d5335 2469 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1da177e4
LT		 2470 if (apcm == NULL)
2471 return -ENOMEM;
2472 apcm->chip = chip;
01b65bfb 2473 apcm->pcm = pcm;
1da177e4 2474 apcm->codec = codec;
1da177e4
LT		 2475 pcm->private_data = apcm;
2476 pcm->private_free = azx_pcm_free;
176d5335
TI		 2477 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2478 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
01b65bfb 2479 list_add_tail(&apcm->list, &chip->pcm_list);
176d5335
TI		 2480 cpcm->pcm = pcm;
2481 for (s = 0; s < 2; s++) {
2482 apcm->hinfo[s] = &cpcm->stream[s];
2483 if (cpcm->stream[s].substreams)
2484 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2485 }
2486 /* buffer pre-allocation */
acfa634f
TI		 2487 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2488 if (size > MAX_PREALLOC_SIZE)
2489 size = MAX_PREALLOC_SIZE;
4ce107b9 2490 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1da177e4 2491 snd_dma_pci_data(chip->pci),
acfa634f 2492 size, MAX_PREALLOC_SIZE);
1da177e4
LT		 2493 return 0;
2494}
2495
2496/*
2497 * mixer creation - all stuff is implemented in hda module
2498 */
e23e7a14 2499static int azx_mixer_create(struct azx *chip)
1da177e4
LT		 2500{
2501 return snd_hda_build_controls(chip->bus);
2502}
2503
2504
2505/*
2506 * initialize SD streams
2507 */
e23e7a14 2508static int azx_init_stream(struct azx *chip)
1da177e4
LT		 2509{
2510 int i;
2511
2512 /* initialize each stream (aka device)
d01ce99f
TI		 2513 * assign the starting bdl address to each stream (device)
2514 * and initialize
1da177e4 2515 */
07e4ca50 2516 for (i = 0; i < chip->num_streams; i++) {
a98f90fd 2517 struct azx_dev *azx_dev = &chip->azx_dev[i];
929861c6 2518 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1da177e4
LT		 2519 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2520 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2521 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2522 azx_dev->sd_int_sta_mask = 1 << i;
2523 /* stream tag: must be non-zero and unique */
2524 azx_dev->index = i;
2525 azx_dev->stream_tag = i + 1;
2526 }
2527
2528 return 0;
2529}
2530
68e7fffc
TI		 2531static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2532{
437a5a46
TI		 2533 if (request_irq(chip->pci->irq, azx_interrupt,
2534 chip->msi ? 0 : IRQF_SHARED,
934c2b6d 2535 KBUILD_MODNAME, chip)) {
68e7fffc
TI		 2536 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2537 "disabling device\n", chip->pci->irq);
2538 if (do_disconnect)
2539 snd_card_disconnect(chip->card);
2540 return -1;
2541 }
2542 chip->irq = chip->pci->irq;
69e13418 2543 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 2544 return 0;
2545}
2546
1da177e4 2547
cb53c626
TI		 2548static void azx_stop_chip(struct azx *chip)
2549{
95e99fda 2550 if (!chip->initialized)
cb53c626
TI		 2551 return;
2552
2553 /* disable interrupts */
2554 azx_int_disable(chip);
2555 azx_int_clear(chip);
2556
2557 /* disable CORB/RIRB */
2558 azx_free_cmd_io(chip);
2559
2560 /* disable position buffer */
2561 azx_writel(chip, DPLBASE, 0);
2562 azx_writel(chip, DPUBASE, 0);
2563
2564 chip->initialized = 0;
2565}
2566
83012a7c 2567#ifdef CONFIG_PM
cb53c626 2568/* power-up/down the controller */
68467f51 2569static void azx_power_notify(struct hda_bus *bus, bool power_up)
cb53c626 2570{
33fa35ed 2571 struct azx *chip = bus->private_data;
cb53c626 2572
2ea3c6a2
TI		 2573 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2574 return;
2575
68467f51 2576 if (power_up)
b8dfc462
ML		 2577 pm_runtime_get_sync(&chip->pci->dev);
2578 else
2579 pm_runtime_put_sync(&chip->pci->dev);
cb53c626 2580}
65fcd41d
TI		 2581
2582static DEFINE_MUTEX(card_list_lock);
2583static LIST_HEAD(card_list);
2584
2585static void azx_add_card_list(struct azx *chip)
2586{
2587 mutex_lock(&card_list_lock);
2588 list_add(&chip->list, &card_list);
2589 mutex_unlock(&card_list_lock);
2590}
2591
2592static void azx_del_card_list(struct azx *chip)
2593{
2594 mutex_lock(&card_list_lock);
2595 list_del_init(&chip->list);
2596 mutex_unlock(&card_list_lock);
2597}
2598
2599/* trigger power-save check at writing parameter */
2600static int param_set_xint(const char *val, const struct kernel_param *kp)
2601{
2602 struct azx *chip;
2603 struct hda_codec *c;
2604 int prev = power_save;
2605 int ret = param_set_int(val, kp);
2606
2607 if (ret || prev == power_save)
2608 return ret;
2609
2610 mutex_lock(&card_list_lock);
2611 list_for_each_entry(chip, &card_list, list) {
2612 if (!chip->bus || chip->disabled)
2613 continue;
2614 list_for_each_entry(c, &chip->bus->codec_list, list)
2615 snd_hda_power_sync(c);
2616 }
2617 mutex_unlock(&card_list_lock);
2618 return 0;
2619}
2620#else
2621#define azx_add_card_list(chip) /* NOP */
2622#define azx_del_card_list(chip) /* NOP */
83012a7c 2623#endif /* CONFIG_PM */
5c0b9bec 2624
7ccbde57 2625#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 2626/*
2627 * power management
2628 */
68cb2b55 2629static int azx_suspend(struct device *dev)
1da177e4 2630{
68cb2b55
TI		 2631 struct pci_dev *pci = to_pci_dev(dev);
2632 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2633 struct azx *chip = card->private_data;
01b65bfb 2634 struct azx_pcm *p;
1da177e4 2635
c5c21523
TI		 2636 if (chip->disabled)
2637 return 0;
2638
421a1252 2639 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 2640 azx_clear_irq_pending(chip);
01b65bfb
TI		 2641 list_for_each_entry(p, &chip->pcm_list, list)
2642 snd_pcm_suspend_all(p->pcm);
0b7a2e9c 2643 if (chip->initialized)
8dd78330 2644 snd_hda_suspend(chip->bus);
cb53c626 2645 azx_stop_chip(chip);
30b35399 2646 if (chip->irq >= 0) {
43001c95 2647 free_irq(chip->irq, chip);
30b35399
TI		 2648 chip->irq = -1;
2649 }
68e7fffc 2650 if (chip->msi)
43001c95 2651 pci_disable_msi(chip->pci);
421a1252
TI		 2652 pci_disable_device(pci);
2653 pci_save_state(pci);
68cb2b55 2654 pci_set_power_state(pci, PCI_D3hot);
1da177e4
LT		 2655 return 0;
2656}
2657
68cb2b55 2658static int azx_resume(struct device *dev)
1da177e4 2659{
68cb2b55
TI		 2660 struct pci_dev *pci = to_pci_dev(dev);
2661 struct snd_card *card = dev_get_drvdata(dev);
421a1252 2662 struct azx *chip = card->private_data;
1da177e4 2663
c5c21523
TI		 2664 if (chip->disabled)
2665 return 0;
2666
d14a7e0b
TI		 2667 pci_set_power_state(pci, PCI_D0);
2668 pci_restore_state(pci);
30b35399
TI		 2669 if (pci_enable_device(pci) < 0) {
2670 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2671 "disabling device\n");
2672 snd_card_disconnect(card);
2673 return -EIO;
2674 }
2675 pci_set_master(pci);
68e7fffc
TI		 2676 if (chip->msi)
2677 if (pci_enable_msi(pci) < 0)
2678 chip->msi = 0;
2679 if (azx_acquire_irq(chip, 1) < 0)
30b35399 2680 return -EIO;
cb53c626 2681 azx_init_pci(chip);
d804ad92 2682
7f30830b 2683 azx_init_chip(chip, 1);
d804ad92 2684
1da177e4 2685 snd_hda_resume(chip->bus);
421a1252 2686 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2687 return 0;
2688}
b8dfc462
ML		 2689#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2690
2691#ifdef CONFIG_PM_RUNTIME
2692static int azx_runtime_suspend(struct device *dev)
2693{
2694 struct snd_card *card = dev_get_drvdata(dev);
2695 struct azx *chip = card->private_data;
2696
b8dfc462
ML		 2697 azx_stop_chip(chip);
2698 azx_clear_irq_pending(chip);
2699 return 0;
2700}
2701
2702static int azx_runtime_resume(struct device *dev)
2703{
2704 struct snd_card *card = dev_get_drvdata(dev);
2705 struct azx *chip = card->private_data;
2706
2707 azx_init_pci(chip);
2708 azx_init_chip(chip, 1);
2709 return 0;
2710}
6eb827d2
TI		 2711
2712static int azx_runtime_idle(struct device *dev)
2713{
2714 struct snd_card *card = dev_get_drvdata(dev);
2715 struct azx *chip = card->private_data;
2716
2717 if (!power_save_controller ||
2718 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2719 return -EBUSY;
2720
2721 return 0;
2722}
2723
b8dfc462
ML		 2724#endif /* CONFIG_PM_RUNTIME */
2725
2726#ifdef CONFIG_PM
2727static const struct dev_pm_ops azx_pm = {
2728 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
6eb827d2 2729 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 2730};
2731
68cb2b55
TI		 2732#define AZX_PM_OPS &azx_pm
2733#else
68cb2b55 2734#define AZX_PM_OPS NULL
b8dfc462 2735#endif /* CONFIG_PM */
1da177e4
LT		 2736
2737
0cbf0098
TI		 2738/*
2739 * reboot notifier for hang-up problem at power-down
2740 */
2741static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2742{
2743 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
fb8d1a34 2744 snd_hda_bus_reboot_notify(chip->bus);
0cbf0098
TI		 2745 azx_stop_chip(chip);
2746 return NOTIFY_OK;
2747}
2748
2749static void azx_notifier_register(struct azx *chip)
2750{
2751 chip->reboot_notifier.notifier_call = azx_halt;
2752 register_reboot_notifier(&chip->reboot_notifier);
2753}
2754
2755static void azx_notifier_unregister(struct azx *chip)
2756{
2757 if (chip->reboot_notifier.notifier_call)
2758 unregister_reboot_notifier(&chip->reboot_notifier);
2759}
2760
48c8b0eb
TI		 2761static int azx_first_init(struct azx *chip);
2762static int azx_probe_continue(struct azx *chip);
a82d51ed 2763
8393ec4a 2764#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 2765static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 2766
a82d51ed
TI		 2767static void azx_vs_set_state(struct pci_dev *pci,
2768 enum vga_switcheroo_state state)
2769{
2770 struct snd_card *card = pci_get_drvdata(pci);
2771 struct azx *chip = card->private_data;
2772 bool disabled;
2773
f4c482a4 2774 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 2775 if (chip->init_failed)
2776 return;
2777
2778 disabled = (state == VGA_SWITCHEROO_OFF);
2779 if (chip->disabled == disabled)
2780 return;
2781
2782 if (!chip->bus) {
2783 chip->disabled = disabled;
2784 if (!disabled) {
2785 snd_printk(KERN_INFO SFX
2786 "%s: Start delayed initialization\n",
2787 pci_name(chip->pci));
2788 if (azx_first_init(chip) < 0 ||
2789 azx_probe_continue(chip) < 0) {
2790 snd_printk(KERN_ERR SFX
2791 "%s: initialization error\n",
2792 pci_name(chip->pci));
2793 chip->init_failed = true;
2794 }
2795 }
2796 } else {
2797 snd_printk(KERN_INFO SFX
445a51b3
DB		 2798 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
2799 disabled ? "Disabling" : "Enabling");
a82d51ed 2800 if (disabled) {
68cb2b55 2801 azx_suspend(&pci->dev);
a82d51ed 2802 chip->disabled = true;
128960a9 2803 if (snd_hda_lock_devices(chip->bus))
445a51b3
DB		 2804 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
2805 pci_name(chip->pci));
a82d51ed
TI		 2806 } else {
2807 snd_hda_unlock_devices(chip->bus);
2808 chip->disabled = false;
68cb2b55 2809 azx_resume(&pci->dev);
a82d51ed
TI		 2810 }
2811 }
2812}
2813
2814static bool azx_vs_can_switch(struct pci_dev *pci)
2815{
2816 struct snd_card *card = pci_get_drvdata(pci);
2817 struct azx *chip = card->private_data;
2818
f4c482a4 2819 wait_for_completion(&chip->probe_wait);
a82d51ed
TI		 2820 if (chip->init_failed)
2821 return false;
2822 if (chip->disabled || !chip->bus)
2823 return true;
2824 if (snd_hda_lock_devices(chip->bus))
2825 return false;
2826 snd_hda_unlock_devices(chip->bus);
2827 return true;
2828}
2829
e23e7a14 2830static void init_vga_switcheroo(struct azx *chip)
a82d51ed
TI		 2831{
2832 struct pci_dev *p = get_bound_vga(chip->pci);
2833 if (p) {
2834 snd_printk(KERN_INFO SFX
2835 "%s: Handle VGA-switcheroo audio client\n",
2836 pci_name(chip->pci));
2837 chip->use_vga_switcheroo = 1;
2838 pci_dev_put(p);
2839 }
2840}
2841
2842static const struct vga_switcheroo_client_ops azx_vs_ops = {
2843 .set_gpu_state = azx_vs_set_state,
2844 .can_switch = azx_vs_can_switch,
2845};
2846
e23e7a14 2847static int register_vga_switcheroo(struct azx *chip)
a82d51ed 2848{
128960a9
TI		 2849 int err;
2850
a82d51ed
TI		 2851 if (!chip->use_vga_switcheroo)
2852 return 0;
2853 /* FIXME: currently only handling DIS controller
2854 * is there any machine with two switchable HDMI audio controllers?
2855 */
128960a9 2856 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
a82d51ed
TI		 2857 VGA_SWITCHEROO_DIS,
2858 chip->bus != NULL);
128960a9
TI		 2859 if (err < 0)
2860 return err;
2861 chip->vga_switcheroo_registered = 1;
2862 return 0;
a82d51ed
TI		 2863}
2864#else
2865#define init_vga_switcheroo(chip) /* NOP */
2866#define register_vga_switcheroo(chip) 0
8393ec4a 2867#define check_hdmi_disabled(pci) false
a82d51ed
TI		 2868#endif /* SUPPORT_VGA_SWITCHER */
2869
1da177e4
LT		 2870/*
2871 * destructor
2872 */
a98f90fd 2873static int azx_free(struct azx *chip)
1da177e4 2874{
4ce107b9
TI		 2875 int i;
2876
65fcd41d
TI		 2877 azx_del_card_list(chip);
2878
0cbf0098
TI		 2879 azx_notifier_unregister(chip);
2880
f4c482a4 2881 chip->init_failed = 1; /* to be sure */
44728e97 2882 complete_all(&chip->probe_wait);
f4c482a4 2883
a82d51ed
TI		 2884 if (use_vga_switcheroo(chip)) {
2885 if (chip->disabled && chip->bus)
2886 snd_hda_unlock_devices(chip->bus);
128960a9
TI		 2887 if (chip->vga_switcheroo_registered)
2888 vga_switcheroo_unregister_client(chip->pci);
a82d51ed
TI		 2889 }
2890
ce43fbae 2891 if (chip->initialized) {
9ad593f6 2892 azx_clear_irq_pending(chip);
07e4ca50 2893 for (i = 0; i < chip->num_streams; i++)
1da177e4 2894 azx_stream_stop(chip, &chip->azx_dev[i]);
cb53c626 2895 azx_stop_chip(chip);
1da177e4
LT		 2896 }
2897
f000fd80 2898 if (chip->irq >= 0)
1da177e4 2899 free_irq(chip->irq, (void*)chip);
68e7fffc 2900 if (chip->msi)
30b35399 2901 pci_disable_msi(chip->pci);
f079c25a
TI		 2902 if (chip->remap_addr)
2903 iounmap(chip->remap_addr);
1da177e4 2904
4ce107b9
TI		 2905 if (chip->azx_dev) {
2906 for (i = 0; i < chip->num_streams; i++)
27fe48d9
TI		 2907 if (chip->azx_dev[i].bdl.area) {
2908 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
4ce107b9 2909 snd_dma_free_pages(&chip->azx_dev[i].bdl);
27fe48d9 2910 }
4ce107b9 2911 }
27fe48d9
TI		 2912 if (chip->rb.area) {
2913 mark_pages_wc(chip, &chip->rb, false);
1da177e4 2914 snd_dma_free_pages(&chip->rb);
27fe48d9
TI		 2915 }
2916 if (chip->posbuf.area) {
2917 mark_pages_wc(chip, &chip->posbuf, false);
1da177e4 2918 snd_dma_free_pages(&chip->posbuf);
27fe48d9 2919 }
a82d51ed
TI		 2920 if (chip->region_requested)
2921 pci_release_regions(chip->pci);
1da177e4 2922 pci_disable_device(chip->pci);
07e4ca50 2923 kfree(chip->azx_dev);
4918cdab
TI		 2924#ifdef CONFIG_SND_HDA_PATCH_LOADER
2925 if (chip->fw)
2926 release_firmware(chip->fw);
2927#endif
1da177e4
LT		 2928 kfree(chip);
2929
2930 return 0;
2931}
2932
a98f90fd 2933static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 2934{
2935 return azx_free(device->device_data);
2936}
2937
8393ec4a 2938#ifdef SUPPORT_VGA_SWITCHEROO
9121947d
TI		 2939/*
2940 * Check of disabled HDMI controller by vga-switcheroo
2941 */
e23e7a14 2942static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 2943{
2944 struct pci_dev *p;
2945
2946 /* check only discrete GPU */
2947 switch (pci->vendor) {
2948 case PCI_VENDOR_ID_ATI:
2949 case PCI_VENDOR_ID_AMD:
2950 case PCI_VENDOR_ID_NVIDIA:
2951 if (pci->devfn == 1) {
2952 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2953 pci->bus->number, 0);
2954 if (p) {
2955 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2956 return p;
2957 pci_dev_put(p);
2958 }
2959 }
2960 break;
2961 }
2962 return NULL;
2963}
2964
e23e7a14 2965static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 2966{
2967 bool vga_inactive = false;
2968 struct pci_dev *p = get_bound_vga(pci);
2969
2970 if (p) {
12b78a7f 2971 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 2972 vga_inactive = true;
2973 pci_dev_put(p);
2974 }
2975 return vga_inactive;
2976}
8393ec4a 2977#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 2978
3372a153
TI		 2979/*
2980 * white/black-listing for position_fix
2981 */
e23e7a14 2982static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 2983 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2984 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 2985 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 2986 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 2987 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 2988 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 2989 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 2990 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 2991 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 2992 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 2993 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 2994 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 2995 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 2996 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 2997 {}
2998};
2999
e23e7a14 3000static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 3001{
3002 const struct snd_pci_quirk *q;
3003
c673ba1c 3004 switch (fix) {
1dac6695 3005 case POS_FIX_AUTO:
c673ba1c
TI		 3006 case POS_FIX_LPIB:
3007 case POS_FIX_POSBUF:
4cb36310 3008 case POS_FIX_VIACOMBO:
a6f2fd55 3009 case POS_FIX_COMBO:
c673ba1c
TI		 3010 return fix;
3011 }
3012
c673ba1c
TI		 3013 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3014 if (q) {
3015 printk(KERN_INFO
3016 "hda_intel: position_fix set to %d "
3017 "for device %04x:%04x\n",
3018 q->value, q->subvendor, q->subdevice);
3019 return q->value;
3372a153 3020 }
bdd9ef24
DH		 3021
3022 /* Check VIA/ATI HD Audio Controller exist */
9477c58e 3023 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
445a51b3 3024 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
bdd9ef24 3025 return POS_FIX_VIACOMBO;
9477c58e
TI		 3026 }
3027 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
445a51b3 3028 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
50e3bbf9 3029 return POS_FIX_LPIB;
bdd9ef24 3030 }
c673ba1c 3031 return POS_FIX_AUTO;
3372a153
TI		 3032}
3033
669ba27a
TI		 3034/*
3035 * black-lists for probe_mask
3036 */
e23e7a14 3037static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 3038 /* Thinkpad often breaks the controller communication when accessing
3039 * to the non-working (or non-existing) modem codec slot.
3040 */
3041 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3042 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3043 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 3044 /* broken BIOS */
3045 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 3046 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3047 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 3048 /* forced codec slots */
93574844 3049 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 3050 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 3051 /* WinFast VP200 H (Teradici) user reported broken communication */
3052 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 3053 {}
3054};
3055
f1eaaeec
TI		 3056#define AZX_FORCE_CODEC_MASK 0x100
3057
e23e7a14 3058static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 3059{
3060 const struct snd_pci_quirk *q;
3061
f1eaaeec
TI		 3062 chip->codec_probe_mask = probe_mask[dev];
3063 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 3064 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3065 if (q) {
3066 printk(KERN_INFO
3067 "hda_intel: probe_mask set to 0x%x "
3068 "for device %04x:%04x\n",
3069 q->value, q->subvendor, q->subdevice);
f1eaaeec 3070 chip->codec_probe_mask = q->value;
669ba27a
TI		 3071 }
3072 }
f1eaaeec
TI		 3073
3074 /* check forced option */
3075 if (chip->codec_probe_mask != -1 &&
3076 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3077 chip->codec_mask = chip->codec_probe_mask & 0xff;
3078 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3079 chip->codec_mask);
3080 }
669ba27a
TI		 3081}
3082
4d8e22e0 3083/*
71623855 3084 * white/black-list for enable_msi
4d8e22e0 3085 */
e23e7a14 3086static struct snd_pci_quirk msi_black_list[] = {
9dc8398b 3087 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 3088 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 3089 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
4193d13b 3090 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 3091 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 3092 {}
3093};
3094
e23e7a14 3095static void check_msi(struct azx *chip)
4d8e22e0
TI		 3096{
3097 const struct snd_pci_quirk *q;
3098
71623855
TI		 3099 if (enable_msi >= 0) {
3100 chip->msi = !!enable_msi;
4d8e22e0 3101 return;
71623855
TI		 3102 }
3103 chip->msi = 1; /* enable MSI as default */
3104 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0
TI		 3105 if (q) {
3106 printk(KERN_INFO
3107 "hda_intel: msi for device %04x:%04x set to %d\n",
3108 q->subvendor, q->subdevice, q->value);
3109 chip->msi = q->value;
80c43ed7
TI		 3110 return;
3111 }
3112
3113 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e
TI		 3114 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3115 printk(KERN_INFO "hda_intel: Disabling MSI\n");
80c43ed7 3116 chip->msi = 0;
4d8e22e0
TI		 3117 }
3118}
3119
a1585d76 3120/* check the snoop mode availability */
e23e7a14 3121static void azx_check_snoop_available(struct azx *chip)
a1585d76
TI		 3122{
3123 bool snoop = chip->snoop;
3124
3125 switch (chip->driver_type) {
3126 case AZX_DRIVER_VIA:
3127 /* force to non-snoop mode for a new VIA controller
3128 * when BIOS is set
3129 */
3130 if (snoop) {
3131 u8 val;
3132 pci_read_config_byte(chip->pci, 0x42, &val);
3133 if (!(val & 0x80) && chip->pci->revision == 0x30)
3134 snoop = false;
3135 }
3136 break;
3137 case AZX_DRIVER_ATIHDMI_NS:
3138 /* new ATI HDMI requires non-snoop */
3139 snoop = false;
3140 break;
3141 }
3142
3143 if (snoop != chip->snoop) {
445a51b3
DB		 3144 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3145 pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
a1585d76
TI		 3146 chip->snoop = snoop;
3147 }
3148}
669ba27a 3149
1da177e4
LT		 3150/*
3151 * constructor
3152 */
e23e7a14
BP		 3153static int azx_create(struct snd_card *card, struct pci_dev *pci,
3154 int dev, unsigned int driver_caps,
3155 struct azx **rchip)
1da177e4 3156{
a98f90fd 3157 static struct snd_device_ops ops = {
1da177e4
LT		 3158 .dev_free = azx_dev_free,
3159 };
a82d51ed
TI		 3160 struct azx *chip;
3161 int err;
1da177e4
LT		 3162
3163 *rchip = NULL;
bcd72003 3164
927fc866
PM		 3165 err = pci_enable_device(pci);
3166 if (err < 0)
1da177e4
LT		 3167 return err;
3168
e560d8d8 3169 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
927fc866 3170 if (!chip) {
445a51b3 3171 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
1da177e4
LT		 3172 pci_disable_device(pci);
3173 return -ENOMEM;
3174 }
3175
3176 spin_lock_init(&chip->reg_lock);
62932df8 3177 mutex_init(&chip->open_mutex);
1da177e4
LT		 3178 chip->card = card;
3179 chip->pci = pci;
3180 chip->irq = -1;
9477c58e
TI		 3181 chip->driver_caps = driver_caps;
3182 chip->driver_type = driver_caps & 0xff;
4d8e22e0 3183 check_msi(chip);
555e219f 3184 chip->dev_index = dev;
9ad593f6 3185 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
01b65bfb 3186 INIT_LIST_HEAD(&chip->pcm_list);
65fcd41d 3187 INIT_LIST_HEAD(&chip->list);
a82d51ed 3188 init_vga_switcheroo(chip);
f4c482a4 3189 init_completion(&chip->probe_wait);
1da177e4 3190
beaffc39
SG		 3191 chip->position_fix[0] = chip->position_fix[1] =
3192 check_position_fix(chip, position_fix[dev]);
a6f2fd55
TI		 3193 /* combo mode uses LPIB for playback */
3194 if (chip->position_fix[0] == POS_FIX_COMBO) {
3195 chip->position_fix[0] = POS_FIX_LPIB;
3196 chip->position_fix[1] = POS_FIX_AUTO;
3197 }
3198
5aba4f8e 3199 check_probe_mask(chip, dev);
3372a153 3200
27346166 3201 chip->single_cmd = single_cmd;
27fe48d9 3202 chip->snoop = hda_snoop;
a1585d76 3203 azx_check_snoop_available(chip);
c74db86b 3204
5c0d7bc1
TI		 3205 if (bdl_pos_adj[dev] < 0) {
3206 switch (chip->driver_type) {
0c6341ac 3207 case AZX_DRIVER_ICH:
32679f95 3208 case AZX_DRIVER_PCH:
0c6341ac 3209 bdl_pos_adj[dev] = 1;
5c0d7bc1
TI		 3210 break;
3211 default:
0c6341ac 3212 bdl_pos_adj[dev] = 32;
5c0d7bc1
TI		 3213 break;
3214 }
3215 }
3216
a82d51ed
TI		 3217 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3218 if (err < 0) {
445a51b3
DB		 3219 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3220 pci_name(chip->pci));
a82d51ed
TI		 3221 azx_free(chip);
3222 return err;
3223 }
3224
3225 *rchip = chip;
3226 return 0;
3227}
3228
48c8b0eb 3229static int azx_first_init(struct azx *chip)
a82d51ed
TI		 3230{
3231 int dev = chip->dev_index;
3232 struct pci_dev *pci = chip->pci;
3233 struct snd_card *card = chip->card;
3234 int i, err;
3235 unsigned short gcap;
3236
07e4ca50
TI		 3237#if BITS_PER_LONG != 64
3238 /* Fix up base address on ULI M5461 */
3239 if (chip->driver_type == AZX_DRIVER_ULI) {
3240 u16 tmp3;
3241 pci_read_config_word(pci, 0x40, &tmp3);
3242 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3243 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3244 }
3245#endif
3246
927fc866 3247 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 3248 if (err < 0)
1da177e4 3249 return err;
a82d51ed 3250 chip->region_requested = 1;
1da177e4 3251
927fc866 3252 chip->addr = pci_resource_start(pci, 0);
2f5ad54e 3253 chip->remap_addr = pci_ioremap_bar(pci, 0);
1da177e4 3254 if (chip->remap_addr == NULL) {
445a51b3 3255 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
a82d51ed 3256 return -ENXIO;
1da177e4
LT		 3257 }
3258
68e7fffc
TI		 3259 if (chip->msi)
3260 if (pci_enable_msi(pci) < 0)
3261 chip->msi = 0;
7376d013 3262
a82d51ed
TI		 3263 if (azx_acquire_irq(chip, 0) < 0)
3264 return -EBUSY;
1da177e4
LT		 3265
3266 pci_set_master(pci);
3267 synchronize_irq(chip->irq);
3268
bcd72003 3269 gcap = azx_readw(chip, GCAP);
445a51b3 3270 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
bcd72003 3271
dc4c2e6b 3272 /* disable SB600 64bit support for safety */
9477c58e 3273 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b
AB		 3274 struct pci_dev *p_smbus;
3275 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3276 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3277 NULL);
3278 if (p_smbus) {
3279 if (p_smbus->revision < 0x30)
3280 gcap &= ~ICH6_GCAP_64OK;
3281 pci_dev_put(p_smbus);
3282 }
3283 }
09240cf4 3284
9477c58e
TI		 3285 /* disable 64bit DMA address on some devices */
3286 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
445a51b3 3287 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
396087ea 3288 gcap &= ~ICH6_GCAP_64OK;
9477c58e 3289 }
396087ea 3290
2ae66c26 3291 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 3292 if (align_buffer_size >= 0)
3293 chip->align_buffer_size = !!align_buffer_size;
3294 else {
3295 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3296 chip->align_buffer_size = 0;
3297 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3298 chip->align_buffer_size = 1;
3299 else
3300 chip->align_buffer_size = 1;
3301 }
2ae66c26 3302
cf7aaca8 3303 /* allow 64bit DMA address if supported by H/W */
b21fadb9 3304 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
e930438c 3305 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
09240cf4 3306 else {
e930438c
YH		 3307 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3308 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
09240cf4 3309 }
cf7aaca8 3310
8b6ed8e7
TI		 3311 /* read number of streams from GCAP register instead of using
3312 * hardcoded value
3313 */
3314 chip->capture_streams = (gcap >> 8) & 0x0f;
3315 chip->playback_streams = (gcap >> 12) & 0x0f;
3316 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 3317 /* gcap didn't give any info, switching to old method */
3318
3319 switch (chip->driver_type) {
3320 case AZX_DRIVER_ULI:
3321 chip->playback_streams = ULI_NUM_PLAYBACK;
3322 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 3323 break;
3324 case AZX_DRIVER_ATIHDMI:
1815b34a 3325 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 3326 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3327 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 3328 break;
c4da29ca 3329 case AZX_DRIVER_GENERIC:
bcd72003
TD		 3330 default:
3331 chip->playback_streams = ICH6_NUM_PLAYBACK;
3332 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 3333 break;
3334 }
07e4ca50 3335 }
8b6ed8e7
TI		 3336 chip->capture_index_offset = 0;
3337 chip->playback_index_offset = chip->capture_streams;
07e4ca50 3338 chip->num_streams = chip->playback_streams + chip->capture_streams;
d01ce99f
TI		 3339 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3340 GFP_KERNEL);
927fc866 3341 if (!chip->azx_dev) {
445a51b3 3342 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
a82d51ed 3343 return -ENOMEM;
07e4ca50
TI		 3344 }
3345
4ce107b9
TI		 3346 for (i = 0; i < chip->num_streams; i++) {
3347 /* allocate memory for the BDL for each stream */
3348 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3349 snd_dma_pci_data(chip->pci),
3350 BDL_SIZE, &chip->azx_dev[i].bdl);
3351 if (err < 0) {
445a51b3 3352 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
a82d51ed 3353 return -ENOMEM;
4ce107b9 3354 }
27fe48d9 3355 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
1da177e4 3356 }
0be3b5d3 3357 /* allocate memory for the position buffer */
d01ce99f
TI		 3358 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3359 snd_dma_pci_data(chip->pci),
3360 chip->num_streams * 8, &chip->posbuf);
3361 if (err < 0) {
445a51b3 3362 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
a82d51ed 3363 return -ENOMEM;
1da177e4 3364 }
27fe48d9 3365 mark_pages_wc(chip, &chip->posbuf, true);
1da177e4 3366 /* allocate CORB/RIRB */
81740861
TI		 3367 err = azx_alloc_cmd_io(chip);
3368 if (err < 0)
a82d51ed 3369 return err;
1da177e4
LT		 3370
3371 /* initialize streams */
3372 azx_init_stream(chip);
3373
3374 /* initialize chip */
cb53c626 3375 azx_init_pci(chip);
10e77dda 3376 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 3377
3378 /* codec detection */
927fc866 3379 if (!chip->codec_mask) {
445a51b3 3380 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
a82d51ed 3381 return -ENODEV;
1da177e4
LT		 3382 }
3383
07e4ca50 3384 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 3385 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3386 sizeof(card->shortname));
3387 snprintf(card->longname, sizeof(card->longname),
3388 "%s at 0x%lx irq %i",
3389 card->shortname, chip->addr, chip->irq);
07e4ca50 3390
1da177e4 3391 return 0;
1da177e4
LT		 3392}
3393
cb53c626
TI		 3394static void power_down_all_codecs(struct azx *chip)
3395{
83012a7c 3396#ifdef CONFIG_PM
cb53c626
TI		 3397 /* The codecs were powered up in snd_hda_codec_new().
3398 * Now all initialization done, so turn them down if possible
3399 */
3400 struct hda_codec *codec;
3401 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3402 snd_hda_power_down(codec);
3403 }
3404#endif
3405}
3406
97c6a3d1 3407#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 3408/* callback from request_firmware_nowait() */
3409static void azx_firmware_cb(const struct firmware *fw, void *context)
3410{
3411 struct snd_card *card = context;
3412 struct azx *chip = card->private_data;
3413 struct pci_dev *pci = chip->pci;
3414
3415 if (!fw) {
445a51b3
DB		 3416 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3417 pci_name(chip->pci));
5cb543db
TI		 3418 goto error;
3419 }
3420
3421 chip->fw = fw;
3422 if (!chip->disabled) {
3423 /* continue probing */
3424 if (azx_probe_continue(chip))
3425 goto error;
3426 }
3427 return; /* OK */
3428
3429 error:
3430 snd_card_free(card);
3431 pci_set_drvdata(pci, NULL);
3432}
97c6a3d1 3433#endif
5cb543db 3434
e23e7a14
BP		 3435static int azx_probe(struct pci_dev *pci,
3436 const struct pci_device_id *pci_id)
1da177e4 3437{
5aba4f8e 3438 static int dev;
a98f90fd
TI		 3439 struct snd_card *card;
3440 struct azx *chip;
5cb543db 3441 bool probe_now;
927fc866 3442 int err;
1da177e4 3443
5aba4f8e
TI		 3444 if (dev >= SNDRV_CARDS)
3445 return -ENODEV;
3446 if (!enable[dev]) {
3447 dev++;
3448 return -ENOENT;
3449 }
3450
e58de7ba
TI		 3451 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3452 if (err < 0) {
445a51b3 3453 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
e58de7ba 3454 return err;
1da177e4
LT		 3455 }
3456
4ea6fbc8
TI		 3457 snd_card_set_dev(card, &pci->dev);
3458
5aba4f8e 3459 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 3460 if (err < 0)
3461 goto out_free;
421a1252 3462 card->private_data = chip;
f4c482a4
TI		 3463
3464 pci_set_drvdata(pci, card);
3465
3466 err = register_vga_switcheroo(chip);
3467 if (err < 0) {
3468 snd_printk(KERN_ERR SFX
445a51b3 3469 "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
f4c482a4
TI		 3470 goto out_free;
3471 }
3472
3473 if (check_hdmi_disabled(pci)) {
445a51b3 3474 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
f4c482a4 3475 pci_name(pci));
445a51b3 3476 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
f4c482a4
TI		 3477 chip->disabled = true;
3478 }
3479
5cb543db 3480 probe_now = !chip->disabled;
f4c482a4
TI		 3481 if (probe_now) {
3482 err = azx_first_init(chip);
3483 if (err < 0)
3484 goto out_free;
3485 }
1da177e4 3486
4918cdab
TI		 3487#ifdef CONFIG_SND_HDA_PATCH_LOADER
3488 if (patch[dev] && *patch[dev]) {
445a51b3
DB		 3489 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3490 pci_name(pci), patch[dev]);
5cb543db
TI		 3491 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3492 &pci->dev, GFP_KERNEL, card,
3493 azx_firmware_cb);
4918cdab
TI		 3494 if (err < 0)
3495 goto out_free;
5cb543db 3496 probe_now = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 3497 }
3498#endif /* CONFIG_SND_HDA_PATCH_LOADER */
3499
5cb543db 3500 if (probe_now) {
a82d51ed
TI		 3501 err = azx_probe_continue(chip);
3502 if (err < 0)
3503 goto out_free;
3504 }
3505
b8dfc462
ML		 3506 if (pci_dev_run_wake(pci))
3507 pm_runtime_put_noidle(&pci->dev);
3508
a82d51ed 3509 dev++;
44728e97 3510 complete_all(&chip->probe_wait);
a82d51ed
TI		 3511 return 0;
3512
3513out_free:
3514 snd_card_free(card);
f4c482a4 3515 pci_set_drvdata(pci, NULL);
a82d51ed
TI		 3516 return err;
3517}
3518
48c8b0eb 3519static int azx_probe_continue(struct azx *chip)
a82d51ed
TI		 3520{
3521 int dev = chip->dev_index;
3522 int err;
3523
2dca0bba
JK		 3524#ifdef CONFIG_SND_HDA_INPUT_BEEP
3525 chip->beep_mode = beep_mode[dev];
3526#endif
3527
1da177e4 3528 /* create codec instances */
a1e21c90 3529 err = azx_codec_create(chip, model[dev]);
41dda0fd
WF		 3530 if (err < 0)
3531 goto out_free;
4ea6fbc8 3532#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab
TI		 3533 if (chip->fw) {
3534 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3535 chip->fw->data);
4ea6fbc8
TI		 3536 if (err < 0)
3537 goto out_free;
e39ae856 3538#ifndef CONFIG_PM
4918cdab
TI		 3539 release_firmware(chip->fw); /* no longer needed */
3540 chip->fw = NULL;
e39ae856 3541#endif
4ea6fbc8
TI		 3542 }
3543#endif
10e77dda 3544 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 3545 err = azx_codec_configure(chip);
3546 if (err < 0)
3547 goto out_free;
3548 }
1da177e4
LT		 3549
3550 /* create PCM streams */
176d5335 3551 err = snd_hda_build_pcms(chip->bus);
41dda0fd
WF		 3552 if (err < 0)
3553 goto out_free;
1da177e4
LT		 3554
3555 /* create mixer controls */
d01ce99f 3556 err = azx_mixer_create(chip);
41dda0fd
WF		 3557 if (err < 0)
3558 goto out_free;
1da177e4 3559
a82d51ed 3560 err = snd_card_register(chip->card);
41dda0fd
WF		 3561 if (err < 0)
3562 goto out_free;
1da177e4 3563
cb53c626
TI		 3564 chip->running = 1;
3565 power_down_all_codecs(chip);
0cbf0098 3566 azx_notifier_register(chip);
65fcd41d 3567 azx_add_card_list(chip);
1da177e4 3568
9121947d
TI		 3569 return 0;
3570
41dda0fd 3571out_free:
a82d51ed 3572 chip->init_failed = 1;
41dda0fd 3573 return err;
1da177e4
LT		 3574}
3575
e23e7a14 3576static void azx_remove(struct pci_dev *pci)
1da177e4 3577{
9121947d 3578 struct snd_card *card = pci_get_drvdata(pci);
b8dfc462
ML		 3579
3580 if (pci_dev_run_wake(pci))
3581 pm_runtime_get_noresume(&pci->dev);
3582
9121947d
TI		 3583 if (card)
3584 snd_card_free(card);
1da177e4
LT		 3585 pci_set_drvdata(pci, NULL);
3586}
3587
3588/* PCI IDs */
cebe41d4 3589static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
d2f2fcd2 3590 /* CPT */
9477c58e 3591 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 3592 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 3593 /* PBG */
9477c58e 3594 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 3595 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 3596 /* Panther Point */
9477c58e 3597 { PCI_DEVICE(0x8086, 0x1e20),
d7dab4db 3598 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 3599 /* Lynx Point */
3600 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 3601 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3602 /* Lynx Point-LP */
3603 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 3604 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 3605 /* Lynx Point-LP */
3606 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 3607 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
e926f2c8
WX		 3608 /* Haswell */
3609 { PCI_DEVICE(0x8086, 0x0c0c),
2ea3c6a2 3610 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
d279fae8 3611 { PCI_DEVICE(0x8086, 0x0d0c),
2ea3c6a2 3612 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
99df18b3
PLB		 3613 /* 5 Series/3400 */
3614 { PCI_DEVICE(0x8086, 0x3b56),
2ea3c6a2 3615 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
87218e9c 3616 /* SCH */
9477c58e 3617 { PCI_DEVICE(0x8086, 0x811b),
2ae66c26 3618 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
645e9035 3619 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
09904b95
LP		 3620 { PCI_DEVICE(0x8086, 0x080a),
3621 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
716e5db4 3622 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
645e9035 3623 /* ICH */
8b0bd226 3624 { PCI_DEVICE(0x8086, 0x2668),
2ae66c26
PLB		 3625 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3626 AZX_DCAPS_BUFSIZE }, /* ICH6 */
8b0bd226 3627 { PCI_DEVICE(0x8086, 0x27d8),
2ae66c26
PLB		 3628 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3629 AZX_DCAPS_BUFSIZE }, /* ICH7 */
8b0bd226 3630 { PCI_DEVICE(0x8086, 0x269a),
2ae66c26
PLB		 3631 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3632 AZX_DCAPS_BUFSIZE }, /* ESB2 */
8b0bd226 3633 { PCI_DEVICE(0x8086, 0x284b),
2ae66c26
PLB		 3634 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3635 AZX_DCAPS_BUFSIZE }, /* ICH8 */
8b0bd226 3636 { PCI_DEVICE(0x8086, 0x293e),
2ae66c26
PLB		 3637 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3638 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3639 { PCI_DEVICE(0x8086, 0x293f),
2ae66c26
PLB		 3640 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3641 AZX_DCAPS_BUFSIZE }, /* ICH9 */
8b0bd226 3642 { PCI_DEVICE(0x8086, 0x3a3e),
2ae66c26
PLB		 3643 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3644 AZX_DCAPS_BUFSIZE }, /* ICH10 */
8b0bd226 3645 { PCI_DEVICE(0x8086, 0x3a6e),
2ae66c26
PLB		 3646 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3647 AZX_DCAPS_BUFSIZE }, /* ICH10 */
b6864535
TI		 3648 /* Generic Intel */
3649 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3650 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3651 .class_mask = 0xffffff,
2ae66c26 3652 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
9477c58e
TI		 3653 /* ATI SB 450/600/700/800/900 */
3654 { PCI_DEVICE(0x1002, 0x437b),
3655 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3656 { PCI_DEVICE(0x1002, 0x4383),
3657 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3658 /* AMD Hudson */
3659 { PCI_DEVICE(0x1022, 0x780d),
3660 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 3661 /* ATI HDMI */
9477c58e
TI		 3662 { PCI_DEVICE(0x1002, 0x793b),
3663 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3664 { PCI_DEVICE(0x1002, 0x7919),
3665 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3666 { PCI_DEVICE(0x1002, 0x960f),
3667 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3668 { PCI_DEVICE(0x1002, 0x970f),
3669 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3670 { PCI_DEVICE(0x1002, 0xaa00),
3671 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3672 { PCI_DEVICE(0x1002, 0xaa08),
3673 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3674 { PCI_DEVICE(0x1002, 0xaa10),
3675 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3676 { PCI_DEVICE(0x1002, 0xaa18),
3677 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3678 { PCI_DEVICE(0x1002, 0xaa20),
3679 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3680 { PCI_DEVICE(0x1002, 0xaa28),
3681 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3682 { PCI_DEVICE(0x1002, 0xaa30),
3683 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3684 { PCI_DEVICE(0x1002, 0xaa38),
3685 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3686 { PCI_DEVICE(0x1002, 0xaa40),
3687 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3688 { PCI_DEVICE(0x1002, 0xaa48),
3689 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a
AX		 3690 { PCI_DEVICE(0x1002, 0x9902),
3691 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3692 { PCI_DEVICE(0x1002, 0xaaa0),
3693 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3694 { PCI_DEVICE(0x1002, 0xaaa8),
3695 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3696 { PCI_DEVICE(0x1002, 0xaab0),
3697 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
87218e9c 3698 /* VIA VT8251/VT8237A */
9477c58e
TI		 3699 { PCI_DEVICE(0x1106, 0x3288),
3700 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
754fdff8
AL		 3701 /* VIA GFX VT7122/VX900 */
3702 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3703 /* VIA GFX VT6122/VX11 */
3704 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 3705 /* SIS966 */
3706 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3707 /* ULI M5461 */
3708 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3709 /* NVIDIA MCP */
0c2fd1bf
TI		 3710 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3711 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3712 .class_mask = 0xffffff,
9477c58e 3713 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 3714 /* Teradici */
9477c58e
TI		 3715 { PCI_DEVICE(0x6549, 0x1200),
3716 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 3717 { PCI_DEVICE(0x6549, 0x2200),
3718 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 3719 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 3720 /* CTHDA chips */
3721 { PCI_DEVICE(0x1102, 0x0010),
3722 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3723 { PCI_DEVICE(0x1102, 0x0012),
3724 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
313f6e2d
TI		 3725#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3726 /* the following entry conflicts with snd-ctxfi driver,
3727 * as ctxfi driver mutates from HD-audio to native mode with
3728 * a special command sequence.
3729 */
4e01f54b
TI		 3730 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3731 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3732 .class_mask = 0xffffff,
9477c58e 3733 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3734 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 3735#else
3736 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 3737 { PCI_DEVICE(0x1102, 0x0009),
3738 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
69f9ba9b 3739 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 3740#endif
e35d4b11
OS		 3741 /* Vortex86MX */
3742 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 3743 /* VMware HDAudio */
3744 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 3745 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 3746 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3747 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3748 .class_mask = 0xffffff,
9477c58e 3749 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 3750 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3751 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3752 .class_mask = 0xffffff,
9477c58e 3753 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 3754 { 0, }
3755};
3756MODULE_DEVICE_TABLE(pci, azx_ids);
3757
3758/* pci_driver definition */
e9f66d9b 3759static struct pci_driver azx_driver = {
3733e424 3760 .name = KBUILD_MODNAME,
1da177e4
LT		 3761 .id_table = azx_ids,
3762 .probe = azx_probe,
e23e7a14 3763 .remove = azx_remove,
68cb2b55
TI		 3764 .driver = {
3765 .pm = AZX_PM_OPS,
3766 },
1da177e4
LT		 3767};
3768
e9f66d9b 3769module_pci_driver(azx_driver);
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