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[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
CommitLineData
1da177e4
LT		 1/*
2 *
d01ce99f
TI		 3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
1da177e4
LT		 5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
1da177e4
LT		 37#include <linux/delay.h>
38#include <linux/interrupt.h>
362775e2 39#include <linux/kernel.h>
1da177e4 40#include <linux/module.h>
24982c5f 41#include <linux/dma-mapping.h>
1da177e4
LT		 42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
62932df8 46#include <linux/mutex.h>
27fe48d9 47#include <linux/io.h>
b8dfc462 48#include <linux/pm_runtime.h>
5d890f59
PLB		 49#include <linux/clocksource.h>
50#include <linux/time.h>
f4c482a4 51#include <linux/completion.h>
5d890f59 52
27fe48d9
TI		 53#ifdef CONFIG_X86
54/* for snoop control */
55#include <asm/pgtable.h>
7f80f513 56#include <asm/set_memory.h>
50279d9b 57#include <asm/cpufeature.h>
27fe48d9 58#endif
1da177e4
LT		 59#include <sound/core.h>
60#include <sound/initval.h>
98d8fc6c
ML		 61#include <sound/hdaudio.h>
62#include <sound/hda_i915.h>
9121947d 63#include <linux/vgaarb.h>
a82d51ed 64#include <linux/vga_switcheroo.h>
4918cdab 65#include <linux/firmware.h>
1da177e4 66#include "hda_codec.h"
05e84878 67#include "hda_controller.h"
347de1f8 68#include "hda_intel.h"
1da177e4 69
785d8c4b
LY		 70#define CREATE_TRACE_POINTS
71#include "hda_intel_trace.h"
72
b6050ef6
TI		 73/* position fix mode */
74enum {
75 POS_FIX_AUTO,
76 POS_FIX_LPIB,
77 POS_FIX_POSBUF,
78 POS_FIX_VIACOMBO,
79 POS_FIX_COMBO,
f87e7f25 80 POS_FIX_SKL,
b6050ef6
TI		 81};
82
9a34af4a
TI		 83/* Defines for ATI HD Audio support in SB450 south bridge */
84#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
85#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
86
87/* Defines for Nvidia HDA support */
88#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
89#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
90#define NVIDIA_HDA_ISTRM_COH 0x4d
91#define NVIDIA_HDA_OSTRM_COH 0x4c
92#define NVIDIA_HDA_ENABLE_COHBIT 0x01
93
94/* Defines for Intel SCH HDA snoop control */
6639484d
LY		 95#define INTEL_HDA_CGCTL 0x48
96#define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
9a34af4a
TI		 97#define INTEL_SCH_HDA_DEVC 0x78
98#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
99
100/* Define IN stream 0 FIFO size offset in VIA controller */
101#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
102/* Define VIA HD Audio Device ID*/
103#define VIA_HDAC_DEVICE_ID 0x3288
104
33124929
TI		 105/* max number of SDs */
106/* ICH, ATI and VIA have 4 playback and 4 capture */
107#define ICH6_NUM_CAPTURE 4
108#define ICH6_NUM_PLAYBACK 4
109
110/* ULI has 6 playback and 5 capture */
111#define ULI_NUM_CAPTURE 5
112#define ULI_NUM_PLAYBACK 6
113
114/* ATI HDMI may have up to 8 playbacks and 0 capture */
115#define ATIHDMI_NUM_CAPTURE 0
116#define ATIHDMI_NUM_PLAYBACK 8
117
118/* TERA has 4 playback and 3 capture */
119#define TERA_NUM_CAPTURE 3
120#define TERA_NUM_PLAYBACK 4
121
1da177e4 122
5aba4f8e
TI		 123static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
124static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
a67ff6a5 125static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
5aba4f8e 126static char *model[SNDRV_CARDS];
1dac6695 127static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5c0d7bc1 128static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
5aba4f8e 129static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
d4d9cd03 130static int probe_only[SNDRV_CARDS];
26a6cb6c 131static int jackpoll_ms[SNDRV_CARDS];
41438f13 132static int single_cmd = -1;
71623855 133static int enable_msi = -1;
4ea6fbc8
TI		 134#ifdef CONFIG_SND_HDA_PATCH_LOADER
135static char *patch[SNDRV_CARDS];
136#endif
2dca0bba 137#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 138static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
2dca0bba
JK		 139 CONFIG_SND_HDA_INPUT_BEEP_MODE};
140#endif
1da177e4 141
5aba4f8e 142module_param_array(index, int, NULL, 0444);
1da177e4 143MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
5aba4f8e 144module_param_array(id, charp, NULL, 0444);
1da177e4 145MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
5aba4f8e
TI		 146module_param_array(enable, bool, NULL, 0444);
147MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
148module_param_array(model, charp, NULL, 0444);
1da177e4 149MODULE_PARM_DESC(model, "Use the given board model.");
5aba4f8e 150module_param_array(position_fix, int, NULL, 0444);
4cb36310 151MODULE_PARM_DESC(position_fix, "DMA pointer read method."
f87e7f25 152 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
555e219f
TI		 153module_param_array(bdl_pos_adj, int, NULL, 0644);
154MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
5aba4f8e 155module_param_array(probe_mask, int, NULL, 0444);
606ad75f 156MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
079e683e 157module_param_array(probe_only, int, NULL, 0444);
d4d9cd03 158MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
26a6cb6c
DH		 159module_param_array(jackpoll_ms, int, NULL, 0444);
160MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
41438f13 161module_param(single_cmd, bint, 0444);
d01ce99f
TI		 162MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
163 "(for debugging only).");
ac9ef6cf 164module_param(enable_msi, bint, 0444);
134a11f0 165MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
4ea6fbc8
TI		 166#ifdef CONFIG_SND_HDA_PATCH_LOADER
167module_param_array(patch, charp, NULL, 0444);
168MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
169#endif
2dca0bba 170#ifdef CONFIG_SND_HDA_INPUT_BEEP
0920c9b4 171module_param_array(beep_mode, bool, NULL, 0444);
2dca0bba 172MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
0920c9b4 173 "(0=off, 1=on) (default=1).");
2dca0bba 174#endif
606ad75f 175
83012a7c 176#ifdef CONFIG_PM
65fcd41d 177static int param_set_xint(const char *val, const struct kernel_param *kp);
9c27847d 178static const struct kernel_param_ops param_ops_xint = {
65fcd41d
TI		 179 .set = param_set_xint,
180 .get = param_get_int,
181};
182#define param_check_xint param_check_int
183
fee2fba3 184static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
65fcd41d 185module_param(power_save, xint, 0644);
fee2fba3
TI		 186MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
187 "(in second, 0 = disable).");
1da177e4 188
dee1b66c
TI		 189/* reset the HD-audio controller in power save mode.
190 * this may give more power-saving, but will take longer time to
191 * wake up.
192 */
8fc24426
TI		 193static bool power_save_controller = 1;
194module_param(power_save_controller, bool, 0644);
dee1b66c 195MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
e62a42ae 196#else
bb573928 197#define power_save 0
83012a7c 198#endif /* CONFIG_PM */
dee1b66c 199
7bfe059e
TI		 200static int align_buffer_size = -1;
201module_param(align_buffer_size, bint, 0644);
2ae66c26
PLB		 202MODULE_PARM_DESC(align_buffer_size,
203 "Force buffer and period sizes to be multiple of 128 bytes.");
204
27fe48d9 205#ifdef CONFIG_X86
7c732015
TI		 206static int hda_snoop = -1;
207module_param_named(snoop, hda_snoop, bint, 0444);
27fe48d9 208MODULE_PARM_DESC(snoop, "Enable/disable snooping");
27fe48d9
TI		 209#else
210#define hda_snoop true
27fe48d9
TI		 211#endif
212
213
1da177e4
LT		 214MODULE_LICENSE("GPL");
215MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
216 "{Intel, ICH6M},"
2f1b3818 217 "{Intel, ICH7},"
f5d40b30 218 "{Intel, ESB2},"
d2981393 219 "{Intel, ICH8},"
f9cc8a8b 220 "{Intel, ICH9},"
c34f5a04 221 "{Intel, ICH10},"
b29c2360 222 "{Intel, PCH},"
d2f2fcd2 223 "{Intel, CPT},"
d2edeb7c 224 "{Intel, PPT},"
8bc039a1 225 "{Intel, LPT},"
144dad99 226 "{Intel, LPT_LP},"
4eeca499 227 "{Intel, WPT_LP},"
c8b00fd2 228 "{Intel, SPT},"
b4565913 229 "{Intel, SPT_LP},"
e926f2c8 230 "{Intel, HPT},"
cea310e8 231 "{Intel, PBG},"
4979bca9 232 "{Intel, SCH},"
fc20a562 233 "{ATI, SB450},"
89be83f8 234 "{ATI, SB600},"
778b6e1b 235 "{ATI, RS600},"
5b15c95f 236 "{ATI, RS690},"
e6db1119
WL		 237 "{ATI, RS780},"
238 "{ATI, R600},"
2797f724
HRK		 239 "{ATI, RV630},"
240 "{ATI, RV610},"
27da1834
WL		 241 "{ATI, RV670},"
242 "{ATI, RV635},"
243 "{ATI, RV620},"
244 "{ATI, RV770},"
fc20a562 245 "{VIA, VT8251},"
47672310 246 "{VIA, VT8237A},"
07e4ca50
TI		 247 "{SiS, SIS966},"
248 "{ULI, M5461}}");
1da177e4
LT		 249MODULE_DESCRIPTION("Intel HDA driver");
250
a82d51ed 251#if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
f8f1becf 252#if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
a82d51ed
TI		 253#define SUPPORT_VGA_SWITCHEROO
254#endif
255#endif
256
257
1da177e4 258/*
1da177e4 259 */
1da177e4 260
07e4ca50
TI		 261/* driver types */
262enum {
263 AZX_DRIVER_ICH,
32679f95 264 AZX_DRIVER_PCH,
4979bca9 265 AZX_DRIVER_SCH,
a4b4793f 266 AZX_DRIVER_SKL,
fab1285a 267 AZX_DRIVER_HDMI,
07e4ca50 268 AZX_DRIVER_ATI,
778b6e1b 269 AZX_DRIVER_ATIHDMI,
1815b34a 270 AZX_DRIVER_ATIHDMI_NS,
07e4ca50
TI		 271 AZX_DRIVER_VIA,
272 AZX_DRIVER_SIS,
273 AZX_DRIVER_ULI,
da3fca21 274 AZX_DRIVER_NVIDIA,
f269002e 275 AZX_DRIVER_TERA,
14d34f16 276 AZX_DRIVER_CTX,
5ae763b1 277 AZX_DRIVER_CTHDA,
c563f473 278 AZX_DRIVER_CMEDIA,
c4da29ca 279 AZX_DRIVER_GENERIC,
2f5983f2 280 AZX_NUM_DRIVERS, /* keep this as last entry */
07e4ca50
TI		 281};
282
37e661ee
TI		 283#define azx_get_snoop_type(chip) \
284 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
285#define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
286
b42b4afb
TI		 287/* quirks for old Intel chipsets */
288#define AZX_DCAPS_INTEL_ICH \
103884a3 289 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
b42b4afb 290
2ea3c6a2 291/* quirks for Intel PCH */
6603249d 292#define AZX_DCAPS_INTEL_PCH_BASE \
103884a3 293 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
bcb337d1 294 AZX_DCAPS_SNOOP_TYPE(SCH))
d7dab4db 295
dba9b7b6 296/* PCH up to IVB; no runtime PM; bind with i915 gfx */
6603249d 297#define AZX_DCAPS_INTEL_PCH_NOPM \
dba9b7b6 298 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
6603249d 299
55913110 300/* PCH for HSW/BDW; with runtime PM */
dba9b7b6 301/* no i915 binding for this as HSW/BDW has another controller for HDMI */
d7dab4db 302#define AZX_DCAPS_INTEL_PCH \
6603249d 303 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
9477c58e 304
6603249d 305/* HSW HDMI */
33499a15 306#define AZX_DCAPS_INTEL_HASWELL \
103884a3 307 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
dba9b7b6
TI		 308 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
309 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
33499a15 310
54a0405d
LY		 311/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
312#define AZX_DCAPS_INTEL_BROADWELL \
103884a3 313 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
dba9b7b6
TI		 314 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
315 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
54a0405d 316
40cc2392 317#define AZX_DCAPS_INTEL_BAYTRAIL \
dba9b7b6
TI		 318 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
319 AZX_DCAPS_I915_POWERWELL)
40cc2392 320
2d846c74 321#define AZX_DCAPS_INTEL_BRASWELL \
dba9b7b6
TI		 322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
323 AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
2d846c74 324
d6795827 325#define AZX_DCAPS_INTEL_SKYLAKE \
dba9b7b6
TI		 326 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
327 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
2d846c74 328 AZX_DCAPS_I915_POWERWELL)
d6795827 329
c87693da 330#define AZX_DCAPS_INTEL_BROXTON \
dba9b7b6
TI		 331 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
332 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
c87693da
LH		 333 AZX_DCAPS_I915_POWERWELL)
334
9477c58e
TI		 335/* quirks for ATI SB / AMD Hudson */
336#define AZX_DCAPS_PRESET_ATI_SB \
37e661ee
TI		 337 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
338 AZX_DCAPS_SNOOP_TYPE(ATI))
9477c58e
TI		 339
340/* quirks for ATI/AMD HDMI */
341#define AZX_DCAPS_PRESET_ATI_HDMI \
db79afa1
BH		 342 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
343 AZX_DCAPS_NO_MSI64)
9477c58e 344
37e661ee
TI		 345/* quirks for ATI HDMI with snoop off */
346#define AZX_DCAPS_PRESET_ATI_HDMI_NS \
347 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
348
9477c58e
TI		 349/* quirks for Nvidia */
350#define AZX_DCAPS_PRESET_NVIDIA \
3ab7511e 351 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
37e661ee 352 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
9477c58e 353
5ae763b1 354#define AZX_DCAPS_PRESET_CTHDA \
37e661ee 355 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
cadd16ea 356 AZX_DCAPS_NO_64BIT |\
37e661ee 357 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
5ae763b1 358
a82d51ed 359/*
2b760d88 360 * vga_switcheroo support
a82d51ed
TI		 361 */
362#ifdef SUPPORT_VGA_SWITCHEROO
5cb543db
TI		 363#define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
364#else
365#define use_vga_switcheroo(chip) 0
366#endif
367
03b135ce
LY		 368#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
369 ((pci)->device == 0x0c0c) || \
370 ((pci)->device == 0x0d0c) || \
371 ((pci)->device == 0x160c))
372
7e31a015 373#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
9ae118db 374#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
7c23b7c1 375
48c8b0eb 376static char *driver_short_names[] = {
07e4ca50 377 [AZX_DRIVER_ICH] = "HDA Intel",
32679f95 378 [AZX_DRIVER_PCH] = "HDA Intel PCH",
4979bca9 379 [AZX_DRIVER_SCH] = "HDA Intel MID",
a4b4793f 380 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
fab1285a 381 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
07e4ca50 382 [AZX_DRIVER_ATI] = "HDA ATI SB",
778b6e1b 383 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
1815b34a 384 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
07e4ca50
TI		 385 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
386 [AZX_DRIVER_SIS] = "HDA SIS966",
da3fca21
V		 387 [AZX_DRIVER_ULI] = "HDA ULI M5461",
388 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
f269002e 389 [AZX_DRIVER_TERA] = "HDA Teradici",
14d34f16 390 [AZX_DRIVER_CTX] = "HDA Creative",
5ae763b1 391 [AZX_DRIVER_CTHDA] = "HDA Creative",
c563f473 392 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
c4da29ca 393 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
07e4ca50
TI		 394};
395
27fe48d9 396#ifdef CONFIG_X86
9ddf1aeb 397static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
27fe48d9 398{
9ddf1aeb
TI		 399 int pages;
400
27fe48d9
TI		 401 if (azx_snoop(chip))
402 return;
9ddf1aeb
TI		 403 if (!dmab || !dmab->area || !dmab->bytes)
404 return;
405
406#ifdef CONFIG_SND_DMA_SGBUF
407 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
408 struct snd_sg_buf *sgbuf = dmab->private_data;
3b70bdba
TI		 409 if (chip->driver_type == AZX_DRIVER_CMEDIA)
410 return; /* deal with only CORB/RIRB buffers */
27fe48d9 411 if (on)
9ddf1aeb 412 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
27fe48d9 413 else
9ddf1aeb
TI		 414 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
415 return;
27fe48d9 416 }
9ddf1aeb
TI		 417#endif
418
419 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
420 if (on)
421 set_memory_wc((unsigned long)dmab->area, pages);
422 else
423 set_memory_wb((unsigned long)dmab->area, pages);
27fe48d9
TI		 424}
425
426static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
427 bool on)
428{
9ddf1aeb 429 __mark_pages_wc(chip, buf, on);
27fe48d9
TI		 430}
431static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 432 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 433{
434 if (azx_dev->wc_marked != on) {
9ddf1aeb 435 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
27fe48d9
TI		 436 azx_dev->wc_marked = on;
437 }
438}
439#else
440/* NOP for other archs */
441static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
442 bool on)
443{
444}
445static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
9ddf1aeb 446 struct snd_pcm_substream *substream, bool on)
27fe48d9
TI		 447{
448}
449#endif
450
68e7fffc 451static int azx_acquire_irq(struct azx *chip, int do_disconnect);
111d3af5 452
cb53c626
TI		 453/*
454 * initialize the PCI registers
455 */
456/* update bits in a PCI register byte */
457static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
458 unsigned char mask, unsigned char val)
459{
460 unsigned char data;
461
462 pci_read_config_byte(pci, reg, &data);
463 data &= ~mask;
464 data |= (val & mask);
465 pci_write_config_byte(pci, reg, data);
466}
467
468static void azx_init_pci(struct azx *chip)
469{
37e661ee
TI		 470 int snoop_type = azx_get_snoop_type(chip);
471
cb53c626
TI		 472 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
473 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
474 * Ensuring these bits are 0 clears playback static on some HD Audio
a09e89f6
AL		 475 * codecs.
476 * The PCI register TCSEL is defined in the Intel manuals.
cb53c626 477 */
46f2cc80 478 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
4e76a883 479 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
fb1d8ac2 480 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
9477c58e 481 }
cb53c626 482
9477c58e
TI		 483 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
484 * we need to enable snoop.
485 */
37e661ee 486 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
4e76a883
TI		 487 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
488 azx_snoop(chip));
cb53c626 489 update_pci_byte(chip->pci,
27fe48d9
TI		 490 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
491 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
9477c58e
TI		 492 }
493
494 /* For NVIDIA HDA, enable snoop */
37e661ee 495 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
4e76a883
TI		 496 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
497 azx_snoop(chip));
cb53c626
TI		 498 update_pci_byte(chip->pci,
499 NVIDIA_HDA_TRANSREG_ADDR,
500 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
320dcc30
PC		 501 update_pci_byte(chip->pci,
502 NVIDIA_HDA_ISTRM_COH,
503 0x01, NVIDIA_HDA_ENABLE_COHBIT);
504 update_pci_byte(chip->pci,
505 NVIDIA_HDA_OSTRM_COH,
506 0x01, NVIDIA_HDA_ENABLE_COHBIT);
9477c58e
TI		 507 }
508
509 /* Enable SCH/PCH snoop if needed */
37e661ee 510 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
27fe48d9 511 unsigned short snoop;
90a5ad52 512 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
27fe48d9
TI		 513 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
514 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
515 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
516 if (!azx_snoop(chip))
517 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
518 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
90a5ad52
TI		 519 pci_read_config_word(chip->pci,
520 INTEL_SCH_HDA_DEVC, &snoop);
90a5ad52 521 }
4e76a883
TI		 522 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
523 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
524 "Disabled" : "Enabled");
da3fca21 525 }
1da177e4
LT		 526}
527
7c23b7c1
LH		 528/*
529 * In BXT-P A0, HD-Audio DMA requests is later than expected,
530 * and makes an audio stream sensitive to system latencies when
531 * 24/32 bits are playing.
532 * Adjusting threshold of DMA fifo to force the DMA request
533 * sooner to improve latency tolerance at the expense of power.
534 */
535static void bxt_reduce_dma_latency(struct azx *chip)
536{
537 u32 val;
538
70eafad8 539 val = azx_readl(chip, VS_EM4L);
7c23b7c1 540 val &= (0x3 << 20);
70eafad8 541 azx_writel(chip, VS_EM4L, val);
7c23b7c1
LH		 542}
543
1f9d3d98
LY		 544/*
545 * ML_LCAP bits:
546 * bit 0: 6 MHz Supported
547 * bit 1: 12 MHz Supported
548 * bit 2: 24 MHz Supported
549 * bit 3: 48 MHz Supported
550 * bit 4: 96 MHz Supported
551 * bit 5: 192 MHz Supported
552 */
553static int intel_get_lctl_scf(struct azx *chip)
554{
555 struct hdac_bus *bus = azx_bus(chip);
556 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
557 u32 val, t;
558 int i;
559
560 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
561
562 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
563 t = preferred_bits[i];
564 if (val & (1 << t))
565 return t;
566 }
567
568 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
569 return 0;
570}
571
572static int intel_ml_lctl_set_power(struct azx *chip, int state)
573{
574 struct hdac_bus *bus = azx_bus(chip);
575 u32 val;
576 int timeout;
577
578 /*
579 * the codecs are sharing the first link setting by default
580 * If other links are enabled for stream, they need similar fix
581 */
582 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
583 val &= ~AZX_MLCTL_SPA;
584 val |= state << AZX_MLCTL_SPA_SHIFT;
585 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
586 /* wait for CPA */
587 timeout = 50;
588 while (timeout) {
589 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
590 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
591 return 0;
592 timeout--;
593 udelay(10);
594 }
595
596 return -1;
597}
598
599static void intel_init_lctl(struct azx *chip)
600{
601 struct hdac_bus *bus = azx_bus(chip);
602 u32 val;
603 int ret;
604
605 /* 0. check lctl register value is correct or not */
606 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
607 /* if SCF is already set, let's use it */
608 if ((val & ML_LCTL_SCF_MASK) != 0)
609 return;
610
611 /*
612 * Before operating on SPA, CPA must match SPA.
613 * Any deviation may result in undefined behavior.
614 */
615 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
616 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
617 return;
618
619 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
620 ret = intel_ml_lctl_set_power(chip, 0);
621 udelay(100);
622 if (ret)
623 goto set_spa;
624
625 /* 2. update SCF to select a properly audio clock*/
626 val &= ~ML_LCTL_SCF_MASK;
627 val |= intel_get_lctl_scf(chip);
628 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
629
630set_spa:
631 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
632 intel_ml_lctl_set_power(chip, 1);
633 udelay(100);
634}
635
0a673521
LH		 636static void hda_intel_init_chip(struct azx *chip, bool full_reset)
637{
98d8fc6c 638 struct hdac_bus *bus = azx_bus(chip);
7c23b7c1 639 struct pci_dev *pci = chip->pci;
6639484d 640 u32 val;
0a673521
LH		 641
642 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 643 snd_hdac_set_codec_wakeup(bus, true);
a4b4793f 644 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 645 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
646 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
647 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
648 }
0a673521 649 azx_init_chip(chip, full_reset);
a4b4793f 650 if (chip->driver_type == AZX_DRIVER_SKL) {
6639484d
LY		 651 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
652 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
653 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
654 }
0a673521 655 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
98d8fc6c 656 snd_hdac_set_codec_wakeup(bus, false);
7c23b7c1
LH		 657
658 /* reduce dma latency to avoid noise */
7e31a015 659 if (IS_BXT(pci))
7c23b7c1 660 bxt_reduce_dma_latency(chip);
1f9d3d98
LY		 661
662 if (bus->mlcap != NULL)
663 intel_init_lctl(chip);
0a673521
LH		 664}
665
b6050ef6
TI		 666/* calculate runtime delay from LPIB */
667static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
668 unsigned int pos)
669{
7833c3f8 670 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6
TI		 671 int stream = substream->stream;
672 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
673 int delay;
674
675 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
676 delay = pos - lpib_pos;
677 else
678 delay = lpib_pos - pos;
679 if (delay < 0) {
7833c3f8 680 if (delay >= azx_dev->core.delay_negative_threshold)
b6050ef6
TI		 681 delay = 0;
682 else
7833c3f8 683 delay += azx_dev->core.bufsize;
b6050ef6
TI		 684 }
685
7833c3f8 686 if (delay >= azx_dev->core.period_bytes) {
b6050ef6
TI		 687 dev_info(chip->card->dev,
688 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
7833c3f8 689 delay, azx_dev->core.period_bytes);
b6050ef6
TI		 690 delay = 0;
691 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
692 chip->get_delay[stream] = NULL;
693 }
694
695 return bytes_to_frames(substream->runtime, delay);
696}
697
9ad593f6
TI		 698static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
699
7ca954a8
DR		 700/* called from IRQ */
701static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
702{
9a34af4a 703 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
7ca954a8
DR		 704 int ok;
705
706 ok = azx_position_ok(chip, azx_dev);
707 if (ok == 1) {
708 azx_dev->irq_pending = 0;
709 return ok;
2f35c630 710 } else if (ok == 0) {
7ca954a8
DR		 711 /* bogus IRQ, process it later */
712 azx_dev->irq_pending = 1;
2f35c630 713 schedule_work(&hda->irq_pending_work);
7ca954a8
DR		 714 }
715 return 0;
716}
717
17eccb27
ML		 718/* Enable/disable i915 display power for the link */
719static int azx_intel_link_power(struct azx *chip, bool enable)
720{
98d8fc6c 721 struct hdac_bus *bus = azx_bus(chip);
17eccb27 722
98d8fc6c 723 return snd_hdac_display_power(bus, enable);
17eccb27
ML		 724}
725
9ad593f6
TI		 726/*
727 * Check whether the current DMA position is acceptable for updating
728 * periods. Returns non-zero if it's OK.
729 *
730 * Many HD-audio controllers appear pretty inaccurate about
731 * the update-IRQ timing. The IRQ is issued before actually the
732 * data is processed. So, we need to process it afterwords in a
733 * workqueue.
734 */
735static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
736{
7833c3f8 737 struct snd_pcm_substream *substream = azx_dev->core.substream;
b6050ef6 738 int stream = substream->stream;
e5463720 739 u32 wallclk;
9ad593f6
TI		 740 unsigned int pos;
741
7833c3f8
TI		 742 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
743 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
fa00e046 744 return -1; /* bogus (too early) interrupt */
fa00e046 745
b6050ef6
TI		 746 if (chip->get_position[stream])
747 pos = chip->get_position[stream](chip, azx_dev);
748 else { /* use the position buffer as default */
749 pos = azx_get_pos_posbuf(chip, azx_dev);
750 if (!pos || pos == (u32)-1) {
751 dev_info(chip->card->dev,
752 "Invalid position buffer, using LPIB read method instead.\n");
753 chip->get_position[stream] = azx_get_pos_lpib;
ccc98865
TI		 754 if (chip->get_position[0] == azx_get_pos_lpib &&
755 chip->get_position[1] == azx_get_pos_lpib)
756 azx_bus(chip)->use_posbuf = false;
b6050ef6
TI		 757 pos = azx_get_pos_lpib(chip, azx_dev);
758 chip->get_delay[stream] = NULL;
759 } else {
760 chip->get_position[stream] = azx_get_pos_posbuf;
761 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
762 chip->get_delay[stream] = azx_get_delay_from_lpib;
763 }
764 }
765
7833c3f8 766 if (pos >= azx_dev->core.bufsize)
b6050ef6 767 pos = 0;
9ad593f6 768
7833c3f8 769 if (WARN_ONCE(!azx_dev->core.period_bytes,
d6d8bf54 770 "hda-intel: zero azx_dev->period_bytes"))
f48f606d 771 return -1; /* this shouldn't happen! */
7833c3f8
TI		 772 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
773 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
f48f606d 774 /* NG - it's below the first next period boundary */
4f0189be 775 return chip->bdl_pos_adj ? 0 : -1;
7833c3f8 776 azx_dev->core.start_wallclk += wallclk;
9ad593f6
TI		 777 return 1; /* OK, it's fine */
778}
779
780/*
781 * The work for pending PCM period updates.
782 */
783static void azx_irq_pending_work(struct work_struct *work)
784{
9a34af4a
TI		 785 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
786 struct azx *chip = &hda->chip;
7833c3f8
TI		 787 struct hdac_bus *bus = azx_bus(chip);
788 struct hdac_stream *s;
789 int pending, ok;
9ad593f6 790
9a34af4a 791 if (!hda->irq_pending_warned) {
4e76a883
TI		 792 dev_info(chip->card->dev,
793 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
794 chip->card->number);
9a34af4a 795 hda->irq_pending_warned = 1;
a6a950a8
TI		 796 }
797
9ad593f6
TI		 798 for (;;) {
799 pending = 0;
a41d1224 800 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 801 list_for_each_entry(s, &bus->stream_list, list) {
802 struct azx_dev *azx_dev = stream_to_azx_dev(s);
9ad593f6 803 if (!azx_dev->irq_pending ||
7833c3f8
TI		 804 !s->substream ||
805 !s->running)
9ad593f6 806 continue;
e5463720
JK		 807 ok = azx_position_ok(chip, azx_dev);
808 if (ok > 0) {
9ad593f6 809 azx_dev->irq_pending = 0;
a41d1224 810 spin_unlock(&bus->reg_lock);
7833c3f8 811 snd_pcm_period_elapsed(s->substream);
a41d1224 812 spin_lock(&bus->reg_lock);
e5463720
JK		 813 } else if (ok < 0) {
814 pending = 0; /* too early */
9ad593f6
TI		 815 } else
816 pending++;
817 }
a41d1224 818 spin_unlock_irq(&bus->reg_lock);
9ad593f6
TI		 819 if (!pending)
820 return;
08af495f 821 msleep(1);
9ad593f6
TI		 822 }
823}
824
825/* clear irq_pending flags and assure no on-going workq */
826static void azx_clear_irq_pending(struct azx *chip)
827{
7833c3f8
TI		 828 struct hdac_bus *bus = azx_bus(chip);
829 struct hdac_stream *s;
9ad593f6 830
a41d1224 831 spin_lock_irq(&bus->reg_lock);
7833c3f8
TI		 832 list_for_each_entry(s, &bus->stream_list, list) {
833 struct azx_dev *azx_dev = stream_to_azx_dev(s);
834 azx_dev->irq_pending = 0;
835 }
a41d1224 836 spin_unlock_irq(&bus->reg_lock);
1da177e4
LT		 837}
838
68e7fffc
TI		 839static int azx_acquire_irq(struct azx *chip, int do_disconnect)
840{
a41d1224
TI		 841 struct hdac_bus *bus = azx_bus(chip);
842
437a5a46
TI		 843 if (request_irq(chip->pci->irq, azx_interrupt,
844 chip->msi ? 0 : IRQF_SHARED,
de65360b 845 chip->card->irq_descr, chip)) {
4e76a883
TI		 846 dev_err(chip->card->dev,
847 "unable to grab IRQ %d, disabling device\n",
848 chip->pci->irq);
68e7fffc
TI		 849 if (do_disconnect)
850 snd_card_disconnect(chip->card);
851 return -1;
852 }
a41d1224 853 bus->irq = chip->pci->irq;
69e13418 854 pci_intx(chip->pci, !chip->msi);
68e7fffc
TI		 855 return 0;
856}
857
b6050ef6
TI		 858/* get the current DMA position with correction on VIA chips */
859static unsigned int azx_via_get_position(struct azx *chip,
860 struct azx_dev *azx_dev)
861{
862 unsigned int link_pos, mini_pos, bound_pos;
863 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
864 unsigned int fifo_size;
865
1604eeee 866 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
7833c3f8 867 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
b6050ef6
TI		 868 /* Playback, no problem using link position */
869 return link_pos;
870 }
871
872 /* Capture */
873 /* For new chipset,
874 * use mod to get the DMA position just like old chipset
875 */
7833c3f8
TI		 876 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
877 mod_dma_pos %= azx_dev->core.period_bytes;
b6050ef6
TI		 878
879 /* azx_dev->fifo_size can't get FIFO size of in stream.
880 * Get from base address + offset.
881 */
a41d1224
TI		 882 fifo_size = readw(azx_bus(chip)->remap_addr +
883 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
b6050ef6
TI		 884
885 if (azx_dev->insufficient) {
886 /* Link position never gather than FIFO size */
887 if (link_pos <= fifo_size)
888 return 0;
889
890 azx_dev->insufficient = 0;
891 }
892
893 if (link_pos <= fifo_size)
7833c3f8 894 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
b6050ef6
TI		 895 else
896 mini_pos = link_pos - fifo_size;
897
898 /* Find nearest previous boudary */
7833c3f8
TI		 899 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
900 mod_link_pos = link_pos % azx_dev->core.period_bytes;
b6050ef6
TI		 901 if (mod_link_pos >= fifo_size)
902 bound_pos = link_pos - mod_link_pos;
903 else if (mod_dma_pos >= mod_mini_pos)
904 bound_pos = mini_pos - mod_mini_pos;
905 else {
7833c3f8
TI		 906 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
907 if (bound_pos >= azx_dev->core.bufsize)
b6050ef6
TI		 908 bound_pos = 0;
909 }
910
911 /* Calculate real DMA position we want */
912 return bound_pos + mod_dma_pos;
913}
914
f87e7f25
TI		 915static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
916 struct azx_dev *azx_dev)
917{
918 return _snd_hdac_chip_readl(azx_bus(chip),
919 AZX_REG_VS_SDXDPIB_XBASE +
920 (AZX_REG_VS_SDXDPIB_XINTERVAL *
921 azx_dev->core.index));
922}
923
924/* get the current DMA position with correction on SKL+ chips */
925static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
926{
927 /* DPIB register gives a more accurate position for playback */
928 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
929 return azx_skl_get_dpib_pos(chip, azx_dev);
930
931 /* For capture, we need to read posbuf, but it requires a delay
932 * for the possible boundary overlap; the read of DPIB fetches the
933 * actual posbuf
934 */
935 udelay(20);
936 azx_skl_get_dpib_pos(chip, azx_dev);
937 return azx_get_pos_posbuf(chip, azx_dev);
938}
939
83012a7c 940#ifdef CONFIG_PM
65fcd41d
TI		 941static DEFINE_MUTEX(card_list_lock);
942static LIST_HEAD(card_list);
943
944static void azx_add_card_list(struct azx *chip)
945{
9a34af4a 946 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 947 mutex_lock(&card_list_lock);
9a34af4a 948 list_add(&hda->list, &card_list);
65fcd41d
TI		 949 mutex_unlock(&card_list_lock);
950}
951
952static void azx_del_card_list(struct azx *chip)
953{
9a34af4a 954 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
65fcd41d 955 mutex_lock(&card_list_lock);
9a34af4a 956 list_del_init(&hda->list);
65fcd41d
TI		 957 mutex_unlock(&card_list_lock);
958}
959
960/* trigger power-save check at writing parameter */
961static int param_set_xint(const char *val, const struct kernel_param *kp)
962{
9a34af4a 963 struct hda_intel *hda;
65fcd41d 964 struct azx *chip;
65fcd41d
TI		 965 int prev = power_save;
966 int ret = param_set_int(val, kp);
967
968 if (ret || prev == power_save)
969 return ret;
970
971 mutex_lock(&card_list_lock);
9a34af4a
TI		 972 list_for_each_entry(hda, &card_list, list) {
973 chip = &hda->chip;
a41d1224 974 if (!hda->probe_continued || chip->disabled)
65fcd41d 975 continue;
a41d1224 976 snd_hda_set_power_save(&chip->bus, power_save * 1000);
65fcd41d
TI		 977 }
978 mutex_unlock(&card_list_lock);
979 return 0;
980}
981#else
982#define azx_add_card_list(chip) /* NOP */
983#define azx_del_card_list(chip) /* NOP */
83012a7c 984#endif /* CONFIG_PM */
5c0b9bec 985
7ccbde57 986#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
5c0b9bec
TI		 987/*
988 * power management
989 */
68cb2b55 990static int azx_suspend(struct device *dev)
1da177e4 991{
68cb2b55 992 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 993 struct azx *chip;
994 struct hda_intel *hda;
a41d1224 995 struct hdac_bus *bus;
1da177e4 996
2d9772ef
TI		 997 if (!card)
998 return 0;
999
1000 chip = card->private_data;
1001 hda = container_of(chip, struct hda_intel, chip);
342e8449 1002 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 1003 return 0;
1004
a41d1224 1005 bus = azx_bus(chip);
421a1252 1006 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
9ad593f6 1007 azx_clear_irq_pending(chip);
cb53c626 1008 azx_stop_chip(chip);
7295b264 1009 azx_enter_link_reset(chip);
a41d1224
TI		 1010 if (bus->irq >= 0) {
1011 free_irq(bus->irq, chip);
1012 bus->irq = -1;
30b35399 1013 }
a07187c9 1014
68e7fffc 1015 if (chip->msi)
43001c95 1016 pci_disable_msi(chip->pci);
dba9b7b6 1017 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
795614dd 1018 && hda->need_i915_power)
98d8fc6c 1019 snd_hdac_display_power(bus, false);
785d8c4b
LY		 1020
1021 trace_azx_suspend(chip);
1da177e4
LT		 1022 return 0;
1023}
1024
68cb2b55 1025static int azx_resume(struct device *dev)
1da177e4 1026{
68cb2b55
TI		 1027 struct pci_dev *pci = to_pci_dev(dev);
1028 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1029 struct azx *chip;
1030 struct hda_intel *hda;
a52ff34e 1031 struct hdac_bus *bus;
2d9772ef
TI		 1032
1033 if (!card)
1034 return 0;
1da177e4 1035
2d9772ef
TI		 1036 chip = card->private_data;
1037 hda = container_of(chip, struct hda_intel, chip);
a52ff34e 1038 bus = azx_bus(chip);
342e8449 1039 if (chip->disabled || hda->init_failed || !chip->running)
c5c21523
TI		 1040 return 0;
1041
a52ff34e
TI		 1042 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1043 snd_hdac_display_power(bus, true);
1044 if (hda->need_i915_power)
1045 snd_hdac_i915_set_bclk(bus);
a07187c9 1046 }
a52ff34e 1047
68e7fffc
TI		 1048 if (chip->msi)
1049 if (pci_enable_msi(pci) < 0)
1050 chip->msi = 0;
1051 if (azx_acquire_irq(chip, 1) < 0)
30b35399 1052 return -EIO;
cb53c626 1053 azx_init_pci(chip);
d804ad92 1054
0a673521 1055 hda_intel_init_chip(chip, true);
d804ad92 1056
a52ff34e
TI		 1057 /* power down again for link-controlled chips */
1058 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1059 !hda->need_i915_power)
1060 snd_hdac_display_power(bus, false);
1061
421a1252 1062 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
785d8c4b
LY		 1063
1064 trace_azx_resume(chip);
1da177e4
LT		 1065 return 0;
1066}
b8dfc462
ML		 1067#endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1068
3e6db33a
XZ		 1069#ifdef CONFIG_PM_SLEEP
1070/* put codec down to D3 at hibernation for Intel SKL+;
1071 * otherwise BIOS may still access the codec and screw up the driver
1072 */
3e6db33a
XZ		 1073static int azx_freeze_noirq(struct device *dev)
1074{
a4b4793f
TI		 1075 struct snd_card *card = dev_get_drvdata(dev);
1076 struct azx *chip = card->private_data;
3e6db33a
XZ		 1077 struct pci_dev *pci = to_pci_dev(dev);
1078
a4b4793f 1079 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1080 pci_set_power_state(pci, PCI_D3hot);
1081
1082 return 0;
1083}
1084
1085static int azx_thaw_noirq(struct device *dev)
1086{
a4b4793f
TI		 1087 struct snd_card *card = dev_get_drvdata(dev);
1088 struct azx *chip = card->private_data;
3e6db33a
XZ		 1089 struct pci_dev *pci = to_pci_dev(dev);
1090
a4b4793f 1091 if (chip->driver_type == AZX_DRIVER_SKL)
3e6db33a
XZ		 1092 pci_set_power_state(pci, PCI_D0);
1093
1094 return 0;
1095}
1096#endif /* CONFIG_PM_SLEEP */
1097
641d334b 1098#ifdef CONFIG_PM
b8dfc462
ML		 1099static int azx_runtime_suspend(struct device *dev)
1100{
1101 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1102 struct azx *chip;
1103 struct hda_intel *hda;
b8dfc462 1104
2d9772ef
TI		 1105 if (!card)
1106 return 0;
1107
1108 chip = card->private_data;
1109 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1110 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1111 return 0;
1112
364aa716 1113 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1114 return 0;
1115
7d4f606c
WX		 1116 /* enable controller wake up event */
1117 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1118 STATESTS_INT_MASK);
1119
b8dfc462 1120 azx_stop_chip(chip);
873ce8ad 1121 azx_enter_link_reset(chip);
b8dfc462 1122 azx_clear_irq_pending(chip);
dba9b7b6 1123 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
795614dd 1124 && hda->need_i915_power)
98d8fc6c 1125 snd_hdac_display_power(azx_bus(chip), false);
e4d9e513 1126
785d8c4b 1127 trace_azx_runtime_suspend(chip);
b8dfc462
ML		 1128 return 0;
1129}
1130
1131static int azx_runtime_resume(struct device *dev)
1132{
1133 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1134 struct azx *chip;
1135 struct hda_intel *hda;
98d8fc6c 1136 struct hdac_bus *bus;
7d4f606c
WX		 1137 struct hda_codec *codec;
1138 int status;
b8dfc462 1139
2d9772ef
TI		 1140 if (!card)
1141 return 0;
1142
1143 chip = card->private_data;
1144 hda = container_of(chip, struct hda_intel, chip);
a52ff34e 1145 bus = azx_bus(chip);
1618e84a 1146 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1147 return 0;
1148
364aa716 1149 if (!azx_has_pm_runtime(chip))
246efa4a
DA		 1150 return 0;
1151
033ea349 1152 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
a52ff34e
TI		 1153 snd_hdac_display_power(bus, true);
1154 if (hda->need_i915_power)
bb03ed21 1155 snd_hdac_i915_set_bclk(bus);
a07187c9 1156 }
7d4f606c
WX		 1157
1158 /* Read STATESTS before controller reset */
1159 status = azx_readw(chip, STATESTS);
1160
b8dfc462 1161 azx_init_pci(chip);
0a673521 1162 hda_intel_init_chip(chip, true);
7d4f606c 1163
a41d1224
TI		 1164 if (status) {
1165 list_for_each_codec(codec, &chip->bus)
7d4f606c 1166 if (status & (1 << codec->addr))
2f35c630
TI		 1167 schedule_delayed_work(&codec->jackpoll_work,
1168 codec->jackpoll_interval);
7d4f606c
WX		 1169 }
1170
1171 /* disable controller Wake Up event*/
1172 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1173 ~STATESTS_INT_MASK);
1174
a52ff34e
TI		 1175 /* power down again for link-controlled chips */
1176 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1177 !hda->need_i915_power)
1178 snd_hdac_display_power(bus, false);
1179
785d8c4b 1180 trace_azx_runtime_resume(chip);
b8dfc462
ML		 1181 return 0;
1182}
6eb827d2
TI		 1183
1184static int azx_runtime_idle(struct device *dev)
1185{
1186 struct snd_card *card = dev_get_drvdata(dev);
2d9772ef
TI		 1187 struct azx *chip;
1188 struct hda_intel *hda;
1189
1190 if (!card)
1191 return 0;
6eb827d2 1192
2d9772ef
TI		 1193 chip = card->private_data;
1194 hda = container_of(chip, struct hda_intel, chip);
1618e84a 1195 if (chip->disabled || hda->init_failed)
246efa4a
DA		 1196 return 0;
1197
55ed9cd1 1198 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
342e8449 1199 azx_bus(chip)->codec_powered || !chip->running)
6eb827d2
TI		 1200 return -EBUSY;
1201
1202 return 0;
1203}
1204
b8dfc462
ML		 1205static const struct dev_pm_ops azx_pm = {
1206 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3e6db33a
XZ		 1207#ifdef CONFIG_PM_SLEEP
1208 .freeze_noirq = azx_freeze_noirq,
1209 .thaw_noirq = azx_thaw_noirq,
1210#endif
6eb827d2 1211 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
b8dfc462
ML		 1212};
1213
68cb2b55
TI		 1214#define AZX_PM_OPS &azx_pm
1215#else
68cb2b55 1216#define AZX_PM_OPS NULL
b8dfc462 1217#endif /* CONFIG_PM */
1da177e4
LT		 1218
1219
48c8b0eb 1220static int azx_probe_continue(struct azx *chip);
a82d51ed 1221
8393ec4a 1222#ifdef SUPPORT_VGA_SWITCHEROO
e23e7a14 1223static struct pci_dev *get_bound_vga(struct pci_dev *pci);
a82d51ed 1224
a82d51ed
TI		 1225static void azx_vs_set_state(struct pci_dev *pci,
1226 enum vga_switcheroo_state state)
1227{
1228 struct snd_card *card = pci_get_drvdata(pci);
1229 struct azx *chip = card->private_data;
9a34af4a 1230 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1231 bool disabled;
1232
9a34af4a
TI		 1233 wait_for_completion(&hda->probe_wait);
1234 if (hda->init_failed)
a82d51ed
TI		 1235 return;
1236
1237 disabled = (state == VGA_SWITCHEROO_OFF);
1238 if (chip->disabled == disabled)
1239 return;
1240
a41d1224 1241 if (!hda->probe_continued) {
a82d51ed
TI		 1242 chip->disabled = disabled;
1243 if (!disabled) {
4e76a883
TI		 1244 dev_info(chip->card->dev,
1245 "Start delayed initialization\n");
5c90680e 1246 if (azx_probe_continue(chip) < 0) {
4e76a883 1247 dev_err(chip->card->dev, "initialization error\n");
9a34af4a 1248 hda->init_failed = true;
a82d51ed
TI		 1249 }
1250 }
1251 } else {
2b760d88 1252 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
4e76a883 1253 disabled ? "Disabling" : "Enabling");
a82d51ed 1254 if (disabled) {
8928756d
DR		 1255 pm_runtime_put_sync_suspend(card->dev);
1256 azx_suspend(card->dev);
2b760d88 1257 /* when we get suspended by vga_switcheroo we end up in D3cold,
246efa4a
DA		 1258 * however we have no ACPI handle, so pci/acpi can't put us there,
1259 * put ourselves there */
1260 pci->current_state = PCI_D3cold;
a82d51ed 1261 chip->disabled = true;
a41d1224 1262 if (snd_hda_lock_devices(&chip->bus))
4e76a883
TI		 1263 dev_warn(chip->card->dev,
1264 "Cannot lock devices!\n");
a82d51ed 1265 } else {
a41d1224 1266 snd_hda_unlock_devices(&chip->bus);
8928756d 1267 pm_runtime_get_noresume(card->dev);
a82d51ed 1268 chip->disabled = false;
8928756d 1269 azx_resume(card->dev);
a82d51ed
TI		 1270 }
1271 }
1272}
1273
1274static bool azx_vs_can_switch(struct pci_dev *pci)
1275{
1276 struct snd_card *card = pci_get_drvdata(pci);
1277 struct azx *chip = card->private_data;
9a34af4a 1278 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed 1279
9a34af4a
TI		 1280 wait_for_completion(&hda->probe_wait);
1281 if (hda->init_failed)
a82d51ed 1282 return false;
a41d1224 1283 if (chip->disabled || !hda->probe_continued)
a82d51ed 1284 return true;
a41d1224 1285 if (snd_hda_lock_devices(&chip->bus))
a82d51ed 1286 return false;
a41d1224 1287 snd_hda_unlock_devices(&chip->bus);
a82d51ed
TI		 1288 return true;
1289}
1290
e23e7a14 1291static void init_vga_switcheroo(struct azx *chip)
a82d51ed 1292{
9a34af4a 1293 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a82d51ed
TI		 1294 struct pci_dev *p = get_bound_vga(chip->pci);
1295 if (p) {
4e76a883 1296 dev_info(chip->card->dev,
2b760d88 1297 "Handle vga_switcheroo audio client\n");
9a34af4a 1298 hda->use_vga_switcheroo = 1;
a82d51ed
TI		 1299 pci_dev_put(p);
1300 }
1301}
1302
1303static const struct vga_switcheroo_client_ops azx_vs_ops = {
1304 .set_gpu_state = azx_vs_set_state,
1305 .can_switch = azx_vs_can_switch,
1306};
1307
e23e7a14 1308static int register_vga_switcheroo(struct azx *chip)
a82d51ed 1309{
9a34af4a 1310 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
128960a9
TI		 1311 int err;
1312
9a34af4a 1313 if (!hda->use_vga_switcheroo)
a82d51ed
TI		 1314 return 0;
1315 /* FIXME: currently only handling DIS controller
1316 * is there any machine with two switchable HDMI audio controllers?
1317 */
128960a9 1318 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
21b45676 1319 VGA_SWITCHEROO_DIS);
128960a9
TI		 1320 if (err < 0)
1321 return err;
9a34af4a 1322 hda->vga_switcheroo_registered = 1;
246efa4a
DA		 1323
1324 /* register as an optimus hdmi audio power domain */
8928756d 1325 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
9a34af4a 1326 &hda->hdmi_pm_domain);
128960a9 1327 return 0;
a82d51ed
TI		 1328}
1329#else
1330#define init_vga_switcheroo(chip) /* NOP */
1331#define register_vga_switcheroo(chip) 0
8393ec4a 1332#define check_hdmi_disabled(pci) false
a82d51ed
TI		 1333#endif /* SUPPORT_VGA_SWITCHER */
1334
1da177e4
LT		 1335/*
1336 * destructor
1337 */
a98f90fd 1338static int azx_free(struct azx *chip)
1da177e4 1339{
c67e2228 1340 struct pci_dev *pci = chip->pci;
a07187c9 1341 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
a41d1224 1342 struct hdac_bus *bus = azx_bus(chip);
4ce107b9 1343
364aa716 1344 if (azx_has_pm_runtime(chip) && chip->running)
c67e2228
WX		 1345 pm_runtime_get_noresume(&pci->dev);
1346
65fcd41d
TI		 1347 azx_del_card_list(chip);
1348
9a34af4a
TI		 1349 hda->init_failed = 1; /* to be sure */
1350 complete_all(&hda->probe_wait);
f4c482a4 1351
9a34af4a 1352 if (use_vga_switcheroo(hda)) {
a41d1224
TI		 1353 if (chip->disabled && hda->probe_continued)
1354 snd_hda_unlock_devices(&chip->bus);
ab58d8cc 1355 if (hda->vga_switcheroo_registered) {
128960a9 1356 vga_switcheroo_unregister_client(chip->pci);
ab58d8cc
PW		 1357 vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1358 }
a82d51ed
TI		 1359 }
1360
a41d1224 1361 if (bus->chip_init) {
9ad593f6 1362 azx_clear_irq_pending(chip);
7833c3f8 1363 azx_stop_all_streams(chip);
cb53c626 1364 azx_stop_chip(chip);
1da177e4
LT		 1365 }
1366
a41d1224
TI		 1367 if (bus->irq >= 0)
1368 free_irq(bus->irq, (void*)chip);
68e7fffc 1369 if (chip->msi)
30b35399 1370 pci_disable_msi(chip->pci);
a41d1224 1371 iounmap(bus->remap_addr);
1da177e4 1372
67908994 1373 azx_free_stream_pages(chip);
a41d1224
TI		 1374 azx_free_streams(chip);
1375 snd_hdac_bus_exit(bus);
1376
a82d51ed
TI		 1377 if (chip->region_requested)
1378 pci_release_regions(chip->pci);
a41d1224 1379
1da177e4 1380 pci_disable_device(chip->pci);
4918cdab 1381#ifdef CONFIG_SND_HDA_PATCH_LOADER
f0acd28c 1382 release_firmware(chip->fw);
4918cdab 1383#endif
98d8fc6c 1384
99a2008d 1385 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
795614dd 1386 if (hda->need_i915_power)
98d8fc6c 1387 snd_hdac_display_power(bus, false);
99a2008d 1388 }
fc18282c 1389 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
fcc88d91 1390 snd_hdac_i915_exit(bus);
a07187c9 1391 kfree(hda);
1da177e4
LT		 1392
1393 return 0;
1394}
1395
a41d1224
TI		 1396static int azx_dev_disconnect(struct snd_device *device)
1397{
1398 struct azx *chip = device->device_data;
1399
1400 chip->bus.shutdown = 1;
1401 return 0;
1402}
1403
a98f90fd 1404static int azx_dev_free(struct snd_device *device)
1da177e4
LT		 1405{
1406 return azx_free(device->device_data);
1407}
1408
8393ec4a 1409#ifdef SUPPORT_VGA_SWITCHEROO
9121947d 1410/*
2b760d88 1411 * Check of disabled HDMI controller by vga_switcheroo
9121947d 1412 */
e23e7a14 1413static struct pci_dev *get_bound_vga(struct pci_dev *pci)
9121947d
TI		 1414{
1415 struct pci_dev *p;
1416
1417 /* check only discrete GPU */
1418 switch (pci->vendor) {
1419 case PCI_VENDOR_ID_ATI:
1420 case PCI_VENDOR_ID_AMD:
1421 case PCI_VENDOR_ID_NVIDIA:
1422 if (pci->devfn == 1) {
1423 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1424 pci->bus->number, 0);
1425 if (p) {
1426 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1427 return p;
1428 pci_dev_put(p);
1429 }
1430 }
1431 break;
1432 }
1433 return NULL;
1434}
1435
e23e7a14 1436static bool check_hdmi_disabled(struct pci_dev *pci)
9121947d
TI		 1437{
1438 bool vga_inactive = false;
1439 struct pci_dev *p = get_bound_vga(pci);
1440
1441 if (p) {
12b78a7f 1442 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
9121947d
TI		 1443 vga_inactive = true;
1444 pci_dev_put(p);
1445 }
1446 return vga_inactive;
1447}
8393ec4a 1448#endif /* SUPPORT_VGA_SWITCHEROO */
9121947d 1449
3372a153
TI		 1450/*
1451 * white/black-listing for position_fix
1452 */
e23e7a14 1453static struct snd_pci_quirk position_fix_list[] = {
d2e1c973
TI		 1454 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1455 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2f703e7a 1456 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
d2e1c973 1457 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
dd37f8e8 1458 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
9f75c1b1 1459 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
e96d3127 1460 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
b01de4fb 1461 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
61bb42c3 1462 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
9ec8ddad 1463 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
45d4ebf1 1464 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
8815cd03 1465 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
b90c0764 1466 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
0e0280dc 1467 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3372a153
TI		 1468 {}
1469};
1470
e23e7a14 1471static int check_position_fix(struct azx *chip, int fix)
3372a153
TI		 1472{
1473 const struct snd_pci_quirk *q;
1474
c673ba1c 1475 switch (fix) {
1dac6695 1476 case POS_FIX_AUTO:
c673ba1c
TI		 1477 case POS_FIX_LPIB:
1478 case POS_FIX_POSBUF:
4cb36310 1479 case POS_FIX_VIACOMBO:
a6f2fd55 1480 case POS_FIX_COMBO:
f87e7f25 1481 case POS_FIX_SKL:
c673ba1c
TI		 1482 return fix;
1483 }
1484
c673ba1c
TI		 1485 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1486 if (q) {
4e76a883
TI		 1487 dev_info(chip->card->dev,
1488 "position_fix set to %d for device %04x:%04x\n",
1489 q->value, q->subvendor, q->subdevice);
c673ba1c 1490 return q->value;
3372a153 1491 }
bdd9ef24
DH		 1492
1493 /* Check VIA/ATI HD Audio Controller exist */
26f05717 1494 if (chip->driver_type == AZX_DRIVER_VIA) {
4e76a883 1495 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
bdd9ef24 1496 return POS_FIX_VIACOMBO;
9477c58e
TI		 1497 }
1498 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
4e76a883 1499 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
50e3bbf9 1500 return POS_FIX_LPIB;
bdd9ef24 1501 }
a4b4793f 1502 if (chip->driver_type == AZX_DRIVER_SKL) {
f87e7f25
TI		 1503 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1504 return POS_FIX_SKL;
1505 }
c673ba1c 1506 return POS_FIX_AUTO;
3372a153
TI		 1507}
1508
b6050ef6
TI		 1509static void assign_position_fix(struct azx *chip, int fix)
1510{
1511 static azx_get_pos_callback_t callbacks[] = {
1512 [POS_FIX_AUTO] = NULL,
1513 [POS_FIX_LPIB] = azx_get_pos_lpib,
1514 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1515 [POS_FIX_VIACOMBO] = azx_via_get_position,
1516 [POS_FIX_COMBO] = azx_get_pos_lpib,
f87e7f25 1517 [POS_FIX_SKL] = azx_get_pos_skl,
b6050ef6
TI		 1518 };
1519
1520 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1521
1522 /* combo mode uses LPIB only for playback */
1523 if (fix == POS_FIX_COMBO)
1524 chip->get_position[1] = NULL;
1525
f87e7f25 1526 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
b6050ef6
TI		 1527 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1528 chip->get_delay[0] = chip->get_delay[1] =
1529 azx_get_delay_from_lpib;
1530 }
1531
1532}
1533
669ba27a
TI		 1534/*
1535 * black-lists for probe_mask
1536 */
e23e7a14 1537static struct snd_pci_quirk probe_mask_list[] = {
669ba27a
TI		 1538 /* Thinkpad often breaks the controller communication when accessing
1539 * to the non-working (or non-existing) modem codec slot.
1540 */
1541 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1542 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1543 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
0edb9454
TI		 1544 /* broken BIOS */
1545 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
ef1681d8
TI		 1546 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1547 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
20db7cb0 1548 /* forced codec slots */
93574844 1549 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
20db7cb0 1550 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
f3af9051
JK		 1551 /* WinFast VP200 H (Teradici) user reported broken communication */
1552 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
669ba27a
TI		 1553 {}
1554};
1555
f1eaaeec
TI		 1556#define AZX_FORCE_CODEC_MASK 0x100
1557
e23e7a14 1558static void check_probe_mask(struct azx *chip, int dev)
669ba27a
TI		 1559{
1560 const struct snd_pci_quirk *q;
1561
f1eaaeec
TI		 1562 chip->codec_probe_mask = probe_mask[dev];
1563 if (chip->codec_probe_mask == -1) {
669ba27a
TI		 1564 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1565 if (q) {
4e76a883
TI		 1566 dev_info(chip->card->dev,
1567 "probe_mask set to 0x%x for device %04x:%04x\n",
1568 q->value, q->subvendor, q->subdevice);
f1eaaeec 1569 chip->codec_probe_mask = q->value;
669ba27a
TI		 1570 }
1571 }
f1eaaeec
TI		 1572
1573 /* check forced option */
1574 if (chip->codec_probe_mask != -1 &&
1575 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
a41d1224 1576 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
4e76a883 1577 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
a41d1224 1578 (int)azx_bus(chip)->codec_mask);
f1eaaeec 1579 }
669ba27a
TI		 1580}
1581
4d8e22e0 1582/*
71623855 1583 * white/black-list for enable_msi
4d8e22e0 1584 */
e23e7a14 1585static struct snd_pci_quirk msi_black_list[] = {
693e0cb0
DH		 1586 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1587 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1588 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1589 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
9dc8398b 1590 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
0a27fcfa 1591 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
ecd21626 1592 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
83f72151 1593 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
4193d13b 1594 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3815595e 1595 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
4d8e22e0
TI		 1596 {}
1597};
1598
e23e7a14 1599static void check_msi(struct azx *chip)
4d8e22e0
TI		 1600{
1601 const struct snd_pci_quirk *q;
1602
71623855
TI		 1603 if (enable_msi >= 0) {
1604 chip->msi = !!enable_msi;
4d8e22e0 1605 return;
71623855
TI		 1606 }
1607 chip->msi = 1; /* enable MSI as default */
1608 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
4d8e22e0 1609 if (q) {
4e76a883
TI		 1610 dev_info(chip->card->dev,
1611 "msi for device %04x:%04x set to %d\n",
1612 q->subvendor, q->subdevice, q->value);
4d8e22e0 1613 chip->msi = q->value;
80c43ed7
TI		 1614 return;
1615 }
1616
1617 /* NVidia chipsets seem to cause troubles with MSI */
9477c58e 1618 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
4e76a883 1619 dev_info(chip->card->dev, "Disabling MSI\n");
80c43ed7 1620 chip->msi = 0;
4d8e22e0
TI		 1621 }
1622}
1623
a1585d76 1624/* check the snoop mode availability */
e23e7a14 1625static void azx_check_snoop_available(struct azx *chip)
a1585d76 1626{
7c732015 1627 int snoop = hda_snoop;
a1585d76 1628
7c732015
TI		 1629 if (snoop >= 0) {
1630 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1631 snoop ? "snoop" : "non-snoop");
1632 chip->snoop = snoop;
1633 return;
1634 }
1635
1636 snoop = true;
37e661ee
TI		 1637 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1638 chip->driver_type == AZX_DRIVER_VIA) {
a1585d76
TI		 1639 /* force to non-snoop mode for a new VIA controller
1640 * when BIOS is set
1641 */
7c732015
TI		 1642 u8 val;
1643 pci_read_config_byte(chip->pci, 0x42, &val);
1644 if (!(val & 0x80) && chip->pci->revision == 0x30)
1645 snoop = false;
a1585d76
TI		 1646 }
1647
37e661ee
TI		 1648 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1649 snoop = false;
1650
7c732015
TI		 1651 chip->snoop = snoop;
1652 if (!snoop)
1653 dev_info(chip->card->dev, "Force to non-snoop mode\n");
a1585d76 1654}
669ba27a 1655
99a2008d
WX		 1656static void azx_probe_work(struct work_struct *work)
1657{
9a34af4a
TI		 1658 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1659 azx_probe_continue(&hda->chip);
99a2008d 1660}
99a2008d 1661
4f0189be
TI		 1662static int default_bdl_pos_adj(struct azx *chip)
1663{
2cf721db
TI		 1664 /* some exceptions: Atoms seem problematic with value 1 */
1665 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1666 switch (chip->pci->device) {
1667 case 0x0f04: /* Baytrail */
1668 case 0x2284: /* Braswell */
1669 return 32;
1670 }
1671 }
1672
4f0189be
TI		 1673 switch (chip->driver_type) {
1674 case AZX_DRIVER_ICH:
1675 case AZX_DRIVER_PCH:
1676 return 1;
1677 default:
1678 return 32;
1679 }
1680}
1681
1da177e4
LT		 1682/*
1683 * constructor
1684 */
a43ff5ba
TI		 1685static const struct hdac_io_ops pci_hda_io_ops;
1686static const struct hda_controller_ops pci_hda_ops;
1687
e23e7a14
BP		 1688static int azx_create(struct snd_card *card, struct pci_dev *pci,
1689 int dev, unsigned int driver_caps,
1690 struct azx **rchip)
1da177e4 1691{
a98f90fd 1692 static struct snd_device_ops ops = {
a41d1224 1693 .dev_disconnect = azx_dev_disconnect,
1da177e4
LT		 1694 .dev_free = azx_dev_free,
1695 };
a07187c9 1696 struct hda_intel *hda;
a82d51ed
TI		 1697 struct azx *chip;
1698 int err;
1da177e4
LT		 1699
1700 *rchip = NULL;
bcd72003 1701
927fc866
PM		 1702 err = pci_enable_device(pci);
1703 if (err < 0)
1da177e4
LT		 1704 return err;
1705
a07187c9
ML		 1706 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1707 if (!hda) {
1da177e4
LT		 1708 pci_disable_device(pci);
1709 return -ENOMEM;
1710 }
1711
a07187c9 1712 chip = &hda->chip;
62932df8 1713 mutex_init(&chip->open_mutex);
1da177e4
LT		 1714 chip->card = card;
1715 chip->pci = pci;
a43ff5ba 1716 chip->ops = &pci_hda_ops;
9477c58e
TI		 1717 chip->driver_caps = driver_caps;
1718 chip->driver_type = driver_caps & 0xff;
4d8e22e0 1719 check_msi(chip);
555e219f 1720 chip->dev_index = dev;
749ee287 1721 chip->jackpoll_ms = jackpoll_ms;
01b65bfb 1722 INIT_LIST_HEAD(&chip->pcm_list);
9a34af4a
TI		 1723 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1724 INIT_LIST_HEAD(&hda->list);
a82d51ed 1725 init_vga_switcheroo(chip);
9a34af4a 1726 init_completion(&hda->probe_wait);
1da177e4 1727
b6050ef6 1728 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
a6f2fd55 1729
5aba4f8e 1730 check_probe_mask(chip, dev);
3372a153 1731
41438f13
TI		 1732 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1733 chip->fallback_to_single_cmd = 1;
1734 else /* explicitly set to single_cmd or not */
1735 chip->single_cmd = single_cmd;
1736
a1585d76 1737 azx_check_snoop_available(chip);
c74db86b 1738
4f0189be
TI		 1739 if (bdl_pos_adj[dev] < 0)
1740 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1741 else
1742 chip->bdl_pos_adj = bdl_pos_adj[dev];
5c0d7bc1 1743
9ae118db
TI		 1744 /* Workaround for a communication error on CFL (bko#199007) */
1745 if (IS_CFL(pci))
1746 chip->polling_mode = 1;
1747
a41d1224
TI		 1748 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1749 if (err < 0) {
1750 kfree(hda);
1751 pci_disable_device(pci);
1752 return err;
1753 }
1754
7d9a1808
TI		 1755 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1756 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1757 chip->bus.needs_damn_long_delay = 1;
1758 }
1759
a82d51ed
TI		 1760 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1761 if (err < 0) {
4e76a883 1762 dev_err(card->dev, "Error creating device [card]!\n");
a82d51ed
TI		 1763 azx_free(chip);
1764 return err;
1765 }
1766
99a2008d 1767 /* continue probing in work context as may trigger request module */
9a34af4a 1768 INIT_WORK(&hda->probe_work, azx_probe_work);
99a2008d 1769
a82d51ed 1770 *rchip = chip;
99a2008d 1771
a82d51ed
TI		 1772 return 0;
1773}
1774
48c8b0eb 1775static int azx_first_init(struct azx *chip)
a82d51ed
TI		 1776{
1777 int dev = chip->dev_index;
1778 struct pci_dev *pci = chip->pci;
1779 struct snd_card *card = chip->card;
a41d1224 1780 struct hdac_bus *bus = azx_bus(chip);
67908994 1781 int err;
a82d51ed 1782 unsigned short gcap;
413cbf46 1783 unsigned int dma_bits = 64;
a82d51ed 1784
07e4ca50
TI		 1785#if BITS_PER_LONG != 64
1786 /* Fix up base address on ULI M5461 */
1787 if (chip->driver_type == AZX_DRIVER_ULI) {
1788 u16 tmp3;
1789 pci_read_config_word(pci, 0x40, &tmp3);
1790 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1791 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1792 }
1793#endif
1794
927fc866 1795 err = pci_request_regions(pci, "ICH HD audio");
a82d51ed 1796 if (err < 0)
1da177e4 1797 return err;
a82d51ed 1798 chip->region_requested = 1;
1da177e4 1799
a41d1224
TI		 1800 bus->addr = pci_resource_start(pci, 0);
1801 bus->remap_addr = pci_ioremap_bar(pci, 0);
1802 if (bus->remap_addr == NULL) {
4e76a883 1803 dev_err(card->dev, "ioremap error\n");
a82d51ed 1804 return -ENXIO;
1da177e4
LT		 1805 }
1806
a4b4793f 1807 if (chip->driver_type == AZX_DRIVER_SKL)
50279d9b
GS		 1808 snd_hdac_bus_parse_capabilities(bus);
1809
1810 /*
1811 * Some Intel CPUs has always running timer (ART) feature and
1812 * controller may have Global time sync reporting capability, so
1813 * check both of these before declaring synchronized time reporting
1814 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1815 */
1816 chip->gts_present = false;
1817
1818#ifdef CONFIG_X86
1819 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1820 chip->gts_present = true;
1821#endif
1822
db79afa1
BH		 1823 if (chip->msi) {
1824 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1825 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1826 pci->no_64bit_msi = true;
1827 }
68e7fffc
TI		 1828 if (pci_enable_msi(pci) < 0)
1829 chip->msi = 0;
db79afa1 1830 }
7376d013 1831
a82d51ed
TI		 1832 if (azx_acquire_irq(chip, 0) < 0)
1833 return -EBUSY;
1da177e4
LT		 1834
1835 pci_set_master(pci);
a41d1224 1836 synchronize_irq(bus->irq);
1da177e4 1837
bcd72003 1838 gcap = azx_readw(chip, GCAP);
4e76a883 1839 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
bcd72003 1840
413cbf46
TI		 1841 /* AMD devices support 40 or 48bit DMA, take the safe one */
1842 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1843 dma_bits = 40;
1844
dc4c2e6b 1845 /* disable SB600 64bit support for safety */
9477c58e 1846 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
dc4c2e6b 1847 struct pci_dev *p_smbus;
413cbf46 1848 dma_bits = 40;
dc4c2e6b
AB		 1849 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1850 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1851 NULL);
1852 if (p_smbus) {
1853 if (p_smbus->revision < 0x30)
fb1d8ac2 1854 gcap &= ~AZX_GCAP_64OK;
dc4c2e6b
AB		 1855 pci_dev_put(p_smbus);
1856 }
1857 }
09240cf4 1858
3ab7511e
AB		 1859 /* NVidia hardware normally only supports up to 40 bits of DMA */
1860 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1861 dma_bits = 40;
1862
9477c58e
TI		 1863 /* disable 64bit DMA address on some devices */
1864 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4e76a883 1865 dev_dbg(card->dev, "Disabling 64bit DMA\n");
fb1d8ac2 1866 gcap &= ~AZX_GCAP_64OK;
9477c58e 1867 }
396087ea 1868
2ae66c26 1869 /* disable buffer size rounding to 128-byte multiples if supported */
7bfe059e
TI		 1870 if (align_buffer_size >= 0)
1871 chip->align_buffer_size = !!align_buffer_size;
1872 else {
103884a3 1873 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
7bfe059e 1874 chip->align_buffer_size = 0;
7bfe059e
TI		 1875 else
1876 chip->align_buffer_size = 1;
1877 }
2ae66c26 1878
cf7aaca8 1879 /* allow 64bit DMA address if supported by H/W */
413cbf46
TI		 1880 if (!(gcap & AZX_GCAP_64OK))
1881 dma_bits = 32;
412b979c
QL		 1882 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1883 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
413cbf46 1884 } else {
412b979c
QL		 1885 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1886 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
09240cf4 1887 }
cf7aaca8 1888
8b6ed8e7
TI		 1889 /* read number of streams from GCAP register instead of using
1890 * hardcoded value
1891 */
1892 chip->capture_streams = (gcap >> 8) & 0x0f;
1893 chip->playback_streams = (gcap >> 12) & 0x0f;
1894 if (!chip->playback_streams && !chip->capture_streams) {
bcd72003
TD		 1895 /* gcap didn't give any info, switching to old method */
1896
1897 switch (chip->driver_type) {
1898 case AZX_DRIVER_ULI:
1899 chip->playback_streams = ULI_NUM_PLAYBACK;
1900 chip->capture_streams = ULI_NUM_CAPTURE;
bcd72003
TD		 1901 break;
1902 case AZX_DRIVER_ATIHDMI:
1815b34a 1903 case AZX_DRIVER_ATIHDMI_NS:
bcd72003
TD		 1904 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1905 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
bcd72003 1906 break;
c4da29ca 1907 case AZX_DRIVER_GENERIC:
bcd72003
TD		 1908 default:
1909 chip->playback_streams = ICH6_NUM_PLAYBACK;
1910 chip->capture_streams = ICH6_NUM_CAPTURE;
bcd72003
TD		 1911 break;
1912 }
07e4ca50 1913 }
8b6ed8e7
TI		 1914 chip->capture_index_offset = 0;
1915 chip->playback_index_offset = chip->capture_streams;
07e4ca50 1916 chip->num_streams = chip->playback_streams + chip->capture_streams;
07e4ca50 1917
df56c3db
JK		 1918 /* sanity check for the SDxCTL.STRM field overflow */
1919 if (chip->num_streams > 15 &&
1920 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1921 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1922 "forcing separate stream tags", chip->num_streams);
1923 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1924 }
1925
a41d1224
TI		 1926 /* initialize streams */
1927 err = azx_init_streams(chip);
81740861 1928 if (err < 0)
a82d51ed 1929 return err;
1da177e4 1930
a41d1224
TI		 1931 err = azx_alloc_stream_pages(chip);
1932 if (err < 0)
1933 return err;
1da177e4
LT		 1934
1935 /* initialize chip */
cb53c626 1936 azx_init_pci(chip);
e4d9e513 1937
bb03ed21
TI		 1938 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1939 snd_hdac_i915_set_bclk(bus);
e4d9e513 1940
0a673521 1941 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1da177e4
LT		 1942
1943 /* codec detection */
a41d1224 1944 if (!azx_bus(chip)->codec_mask) {
4e76a883 1945 dev_err(card->dev, "no codecs found!\n");
a82d51ed 1946 return -ENODEV;
1da177e4
LT		 1947 }
1948
07e4ca50 1949 strcpy(card->driver, "HDA-Intel");
18cb7109
TI		 1950 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1951 sizeof(card->shortname));
1952 snprintf(card->longname, sizeof(card->longname),
1953 "%s at 0x%lx irq %i",
a41d1224 1954 card->shortname, bus->addr, bus->irq);
07e4ca50 1955
1da177e4 1956 return 0;
1da177e4
LT		 1957}
1958
97c6a3d1 1959#ifdef CONFIG_SND_HDA_PATCH_LOADER
5cb543db
TI		 1960/* callback from request_firmware_nowait() */
1961static void azx_firmware_cb(const struct firmware *fw, void *context)
1962{
1963 struct snd_card *card = context;
1964 struct azx *chip = card->private_data;
1965 struct pci_dev *pci = chip->pci;
1966
1967 if (!fw) {
4e76a883 1968 dev_err(card->dev, "Cannot load firmware, aborting\n");
5cb543db
TI		 1969 goto error;
1970 }
1971
1972 chip->fw = fw;
1973 if (!chip->disabled) {
1974 /* continue probing */
1975 if (azx_probe_continue(chip))
1976 goto error;
1977 }
1978 return; /* OK */
1979
1980 error:
1981 snd_card_free(card);
1982 pci_set_drvdata(pci, NULL);
1983}
97c6a3d1 1984#endif
5cb543db 1985
40830813
DR		 1986/*
1987 * HDA controller ops.
1988 */
1989
1990/* PCI register access. */
db291e36 1991static void pci_azx_writel(u32 value, u32 __iomem *addr)
40830813
DR		 1992{
1993 writel(value, addr);
1994}
1995
db291e36 1996static u32 pci_azx_readl(u32 __iomem *addr)
40830813
DR		 1997{
1998 return readl(addr);
1999}
2000
db291e36 2001static void pci_azx_writew(u16 value, u16 __iomem *addr)
40830813
DR		 2002{
2003 writew(value, addr);
2004}
2005
db291e36 2006static u16 pci_azx_readw(u16 __iomem *addr)
40830813
DR		 2007{
2008 return readw(addr);
2009}
2010
db291e36 2011static void pci_azx_writeb(u8 value, u8 __iomem *addr)
40830813
DR		 2012{
2013 writeb(value, addr);
2014}
2015
db291e36 2016static u8 pci_azx_readb(u8 __iomem *addr)
40830813
DR		 2017{
2018 return readb(addr);
2019}
2020
f46ea609
DR		 2021static int disable_msi_reset_irq(struct azx *chip)
2022{
a41d1224 2023 struct hdac_bus *bus = azx_bus(chip);
f46ea609
DR		 2024 int err;
2025
a41d1224
TI		 2026 free_irq(bus->irq, chip);
2027 bus->irq = -1;
f46ea609
DR		 2028 pci_disable_msi(chip->pci);
2029 chip->msi = 0;
2030 err = azx_acquire_irq(chip, 1);
2031 if (err < 0)
2032 return err;
2033
2034 return 0;
2035}
2036
b419b35b 2037/* DMA page allocation helpers. */
a43ff5ba 2038static int dma_alloc_pages(struct hdac_bus *bus,
b419b35b
DR		 2039 int type,
2040 size_t size,
2041 struct snd_dma_buffer *buf)
2042{
a41d1224 2043 struct azx *chip = bus_to_azx(bus);
b419b35b
DR		 2044 int err;
2045
2046 err = snd_dma_alloc_pages(type,
a43ff5ba 2047 bus->dev,
b419b35b
DR		 2048 size, buf);
2049 if (err < 0)
2050 return err;
2051 mark_pages_wc(chip, buf, true);
2052 return 0;
2053}
2054
a43ff5ba 2055static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
b419b35b 2056{
a41d1224 2057 struct azx *chip = bus_to_azx(bus);
a43ff5ba 2058
b419b35b
DR		 2059 mark_pages_wc(chip, buf, false);
2060 snd_dma_free_pages(buf);
2061}
2062
2063static int substream_alloc_pages(struct azx *chip,
2064 struct snd_pcm_substream *substream,
2065 size_t size)
2066{
2067 struct azx_dev *azx_dev = get_azx_dev(substream);
2068 int ret;
2069
2070 mark_runtime_wc(chip, azx_dev, substream, false);
b419b35b
DR		 2071 ret = snd_pcm_lib_malloc_pages(substream, size);
2072 if (ret < 0)
2073 return ret;
2074 mark_runtime_wc(chip, azx_dev, substream, true);
2075 return 0;
2076}
2077
2078static int substream_free_pages(struct azx *chip,
2079 struct snd_pcm_substream *substream)
2080{
2081 struct azx_dev *azx_dev = get_azx_dev(substream);
2082 mark_runtime_wc(chip, azx_dev, substream, false);
2083 return snd_pcm_lib_free_pages(substream);
2084}
2085
8769b278
DR		 2086static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2087 struct vm_area_struct *area)
2088{
2089#ifdef CONFIG_X86
2090 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2091 struct azx *chip = apcm->chip;
3b70bdba 2092 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
8769b278
DR		 2093 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2094#endif
2095}
2096
a43ff5ba 2097static const struct hdac_io_ops pci_hda_io_ops = {
778bde6f
DR		 2098 .reg_writel = pci_azx_writel,
2099 .reg_readl = pci_azx_readl,
2100 .reg_writew = pci_azx_writew,
2101 .reg_readw = pci_azx_readw,
2102 .reg_writeb = pci_azx_writeb,
2103 .reg_readb = pci_azx_readb,
b419b35b
DR		 2104 .dma_alloc_pages = dma_alloc_pages,
2105 .dma_free_pages = dma_free_pages,
a43ff5ba
TI		 2106};
2107
2108static const struct hda_controller_ops pci_hda_ops = {
2109 .disable_msi_reset_irq = disable_msi_reset_irq,
b419b35b
DR		 2110 .substream_alloc_pages = substream_alloc_pages,
2111 .substream_free_pages = substream_free_pages,
8769b278 2112 .pcm_mmap_prepare = pcm_mmap_prepare,
7ca954a8 2113 .position_check = azx_position_check,
17eccb27 2114 .link_power = azx_intel_link_power,
40830813
DR		 2115};
2116
e23e7a14
BP		 2117static int azx_probe(struct pci_dev *pci,
2118 const struct pci_device_id *pci_id)
1da177e4 2119{
5aba4f8e 2120 static int dev;
a98f90fd 2121 struct snd_card *card;
9a34af4a 2122 struct hda_intel *hda;
a98f90fd 2123 struct azx *chip;
aad730d0 2124 bool schedule_probe;
927fc866 2125 int err;
1da177e4 2126
5aba4f8e
TI		 2127 if (dev >= SNDRV_CARDS)
2128 return -ENODEV;
2129 if (!enable[dev]) {
2130 dev++;
2131 return -ENOENT;
2132 }
2133
60c5772b
TI		 2134 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2135 0, &card);
e58de7ba 2136 if (err < 0) {
4e76a883 2137 dev_err(&pci->dev, "Error creating card!\n");
e58de7ba 2138 return err;
1da177e4
LT		 2139 }
2140
a43ff5ba 2141 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
41dda0fd
WF		 2142 if (err < 0)
2143 goto out_free;
421a1252 2144 card->private_data = chip;
9a34af4a 2145 hda = container_of(chip, struct hda_intel, chip);
f4c482a4
TI		 2146
2147 pci_set_drvdata(pci, card);
2148
2149 err = register_vga_switcheroo(chip);
2150 if (err < 0) {
2b760d88 2151 dev_err(card->dev, "Error registering vga_switcheroo client\n");
f4c482a4
TI		 2152 goto out_free;
2153 }
2154
2155 if (check_hdmi_disabled(pci)) {
4e76a883
TI		 2156 dev_info(card->dev, "VGA controller is disabled\n");
2157 dev_info(card->dev, "Delaying initialization\n");
f4c482a4
TI		 2158 chip->disabled = true;
2159 }
2160
aad730d0 2161 schedule_probe = !chip->disabled;
1da177e4 2162
4918cdab
TI		 2163#ifdef CONFIG_SND_HDA_PATCH_LOADER
2164 if (patch[dev] && *patch[dev]) {
4e76a883
TI		 2165 dev_info(card->dev, "Applying patch firmware '%s'\n",
2166 patch[dev]);
5cb543db
TI		 2167 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2168 &pci->dev, GFP_KERNEL, card,
2169 azx_firmware_cb);
4918cdab
TI		 2170 if (err < 0)
2171 goto out_free;
aad730d0 2172 schedule_probe = false; /* continued in azx_firmware_cb() */
4918cdab
TI		 2173 }
2174#endif /* CONFIG_SND_HDA_PATCH_LOADER */
2175
aad730d0 2176#ifndef CONFIG_SND_HDA_I915
6ee8eeb4
TI		 2177 if (CONTROLLER_IN_GPU(pci))
2178 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
99a2008d 2179#endif
99a2008d 2180
aad730d0 2181 if (schedule_probe)
9a34af4a 2182 schedule_work(&hda->probe_work);
a82d51ed 2183
a82d51ed 2184 dev++;
88d071fc 2185 if (chip->disabled)
9a34af4a 2186 complete_all(&hda->probe_wait);
a82d51ed
TI		 2187 return 0;
2188
2189out_free:
2190 snd_card_free(card);
2191 return err;
2192}
2193
e62a42ae
DR		 2194/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2195static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2196 [AZX_DRIVER_NVIDIA] = 8,
2197 [AZX_DRIVER_TERA] = 1,
2198};
2199
48c8b0eb 2200static int azx_probe_continue(struct azx *chip)
a82d51ed 2201{
9a34af4a 2202 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
98d8fc6c 2203 struct hdac_bus *bus = azx_bus(chip);
c67e2228 2204 struct pci_dev *pci = chip->pci;
a82d51ed
TI		 2205 int dev = chip->dev_index;
2206 int err;
2207
a41d1224 2208 hda->probe_continued = 1;
795614dd 2209
fcc88d91 2210 /* bind with i915 if needed */
dba9b7b6 2211 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
98d8fc6c 2212 err = snd_hdac_i915_init(bus);
535115b5
TI		 2213 if (err < 0) {
2214 /* if the controller is bound only with HDMI/DP
2215 * (for HSW and BDW), we need to abort the probe;
2216 * for other chips, still continue probing as other
2217 * codecs can be on the same link.
2218 */
bed2e98e
TI		 2219 if (CONTROLLER_IN_GPU(pci)) {
2220 dev_err(chip->card->dev,
2221 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
535115b5 2222 goto out_free;
fcc88d91
TI		 2223 } else {
2224 /* don't bother any longer */
dba9b7b6
TI		 2225 chip->driver_caps &=
2226 ~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL);
fcc88d91 2227 }
535115b5 2228 }
fcc88d91
TI		 2229 }
2230
2231 /* Request display power well for the HDA controller or codec. For
2232 * Haswell/Broadwell, both the display HDA controller and codec need
2233 * this power. For other platforms, like Baytrail/Braswell, only the
2234 * display codec needs the power and it can be released after probe.
2235 */
2236 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2237 /* HSW/BDW controllers need this power */
2238 if (CONTROLLER_IN_GPU(pci))
2239 hda->need_i915_power = 1;
795614dd 2240
98d8fc6c 2241 err = snd_hdac_display_power(bus, true);
74b0c2d7
TI		 2242 if (err < 0) {
2243 dev_err(chip->card->dev,
2244 "Cannot turn on display power on i915\n");
795614dd 2245 goto i915_power_fail;
74b0c2d7 2246 }
99a2008d
WX		 2247 }
2248
5c90680e
TI		 2249 err = azx_first_init(chip);
2250 if (err < 0)
2251 goto out_free;
2252
2dca0bba
JK		 2253#ifdef CONFIG_SND_HDA_INPUT_BEEP
2254 chip->beep_mode = beep_mode[dev];
2255#endif
2256
1da177e4 2257 /* create codec instances */
96d2bd6e 2258 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
41dda0fd
WF		 2259 if (err < 0)
2260 goto out_free;
96d2bd6e 2261
4ea6fbc8 2262#ifdef CONFIG_SND_HDA_PATCH_LOADER
4918cdab 2263 if (chip->fw) {
a41d1224 2264 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
4918cdab 2265 chip->fw->data);
4ea6fbc8
TI		 2266 if (err < 0)
2267 goto out_free;
e39ae856 2268#ifndef CONFIG_PM
4918cdab
TI		 2269 release_firmware(chip->fw); /* no longer needed */
2270 chip->fw = NULL;
e39ae856 2271#endif
4ea6fbc8
TI		 2272 }
2273#endif
10e77dda 2274 if ((probe_only[dev] & 1) == 0) {
a1e21c90
TI		 2275 err = azx_codec_configure(chip);
2276 if (err < 0)
2277 goto out_free;
2278 }
1da177e4 2279
a82d51ed 2280 err = snd_card_register(chip->card);
41dda0fd
WF		 2281 if (err < 0)
2282 goto out_free;
1da177e4 2283
cb53c626 2284 chip->running = 1;
65fcd41d 2285 azx_add_card_list(chip);
a41d1224 2286 snd_hda_set_power_save(&chip->bus, power_save * 1000);
364aa716 2287 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
30ff5957 2288 pm_runtime_put_autosuspend(&pci->dev);
1da177e4 2289
41dda0fd 2290out_free:
dba9b7b6 2291 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
795614dd 2292 && !hda->need_i915_power)
98d8fc6c 2293 snd_hdac_display_power(bus, false);
795614dd
ML		 2294
2295i915_power_fail:
88d071fc 2296 if (err < 0)
9a34af4a
TI		 2297 hda->init_failed = 1;
2298 complete_all(&hda->probe_wait);
41dda0fd 2299 return err;
1da177e4
LT		 2300}
2301
e23e7a14 2302static void azx_remove(struct pci_dev *pci)
1da177e4 2303{
9121947d 2304 struct snd_card *card = pci_get_drvdata(pci);
991f86d7
TI		 2305 struct azx *chip;
2306 struct hda_intel *hda;
2307
2308 if (card) {
0b8c8219 2309 /* cancel the pending probing work */
991f86d7
TI		 2310 chip = card->private_data;
2311 hda = container_of(chip, struct hda_intel, chip);
ab949d51
TI		 2312 /* FIXME: below is an ugly workaround.
2313 * Both device_release_driver() and driver_probe_device()
2314 * take *both* the device's and its parent's lock before
2315 * calling the remove() and probe() callbacks. The codec
2316 * probe takes the locks of both the codec itself and its
2317 * parent, i.e. the PCI controller dev. Meanwhile, when
2318 * the PCI controller is unbound, it takes its lock, too
2319 * ==> ouch, a deadlock!
2320 * As a workaround, we unlock temporarily here the controller
2321 * device during cancel_work_sync() call.
2322 */
2323 device_unlock(&pci->dev);
0b8c8219 2324 cancel_work_sync(&hda->probe_work);
ab949d51 2325 device_lock(&pci->dev);
b8dfc462 2326
9121947d 2327 snd_card_free(card);
991f86d7 2328 }
1da177e4
LT		 2329}
2330
b2a0bafa
TI		 2331static void azx_shutdown(struct pci_dev *pci)
2332{
2333 struct snd_card *card = pci_get_drvdata(pci);
2334 struct azx *chip;
2335
2336 if (!card)
2337 return;
2338 chip = card->private_data;
2339 if (chip && chip->running)
2340 azx_stop_chip(chip);
2341}
2342
1da177e4 2343/* PCI IDs */
6f51f6cf 2344static const struct pci_device_id azx_ids[] = {
d2f2fcd2 2345 /* CPT */
9477c58e 2346 { PCI_DEVICE(0x8086, 0x1c20),
d7dab4db 2347 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
cea310e8 2348 /* PBG */
9477c58e 2349 { PCI_DEVICE(0x8086, 0x1d20),
d7dab4db 2350 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
d2edeb7c 2351 /* Panther Point */
9477c58e 2352 { PCI_DEVICE(0x8086, 0x1e20),
de5d0ad5 2353 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
8bc039a1
SH		 2354 /* Lynx Point */
2355 { PCI_DEVICE(0x8086, 0x8c20),
2ea3c6a2 2356 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
77f07800
TI		 2357 /* 9 Series */
2358 { PCI_DEVICE(0x8086, 0x8ca0),
2359 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
884b088f
JR		 2360 /* Wellsburg */
2361 { PCI_DEVICE(0x8086, 0x8d20),
2362 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2363 { PCI_DEVICE(0x8086, 0x8d21),
2364 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
5cf92c8b
AY		 2365 /* Lewisburg */
2366 { PCI_DEVICE(0x8086, 0xa1f0),
e7480b34 2367 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
5cf92c8b 2368 { PCI_DEVICE(0x8086, 0xa270),
e7480b34 2369 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
144dad99
JR		 2370 /* Lynx Point-LP */
2371 { PCI_DEVICE(0x8086, 0x9c20),
2ea3c6a2 2372 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
144dad99
JR		 2373 /* Lynx Point-LP */
2374 { PCI_DEVICE(0x8086, 0x9c21),
2ea3c6a2 2375 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4eeca499
JR		 2376 /* Wildcat Point-LP */
2377 { PCI_DEVICE(0x8086, 0x9ca0),
2378 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
c8b00fd2
JR		 2379 /* Sunrise Point */
2380 { PCI_DEVICE(0x8086, 0xa170),
a4b4793f 2381 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
b4565913
DR		 2382 /* Sunrise Point-LP */
2383 { PCI_DEVICE(0x8086, 0x9d70),
a4b4793f 2384 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2385 /* Kabylake */
2386 { PCI_DEVICE(0x8086, 0xa171),
a4b4793f 2387 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
35639a0e
VK		 2388 /* Kabylake-LP */
2389 { PCI_DEVICE(0x8086, 0x9d71),
a4b4793f 2390 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
6858107e
VK		 2391 /* Kabylake-H */
2392 { PCI_DEVICE(0x8086, 0xa2f0),
a4b4793f 2393 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
e79b0006
MD		 2394 /* Coffelake */
2395 { PCI_DEVICE(0x8086, 0xa348),
a4b4793f 2396 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
c87693da
LH		 2397 /* Broxton-P(Apollolake) */
2398 { PCI_DEVICE(0x8086, 0x5a98),
a4b4793f 2399 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
9859a971
LH		 2400 /* Broxton-T */
2401 { PCI_DEVICE(0x8086, 0x1a98),
a4b4793f 2402 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
44b46d73
VK		 2403 /* Gemini-Lake */
2404 { PCI_DEVICE(0x8086, 0x3198),
a4b4793f 2405 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
e926f2c8 2406 /* Haswell */
4a7c516b 2407 { PCI_DEVICE(0x8086, 0x0a0c),
fab1285a 2408 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
e926f2c8 2409 { PCI_DEVICE(0x8086, 0x0c0c),
fab1285a 2410 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
d279fae8 2411 { PCI_DEVICE(0x8086, 0x0d0c),
fab1285a 2412 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
862d7618
ML		 2413 /* Broadwell */
2414 { PCI_DEVICE(0x8086, 0x160c),
54a0405d 2415 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
99df18b3
PLB		 2416 /* 5 Series/3400 */
2417 { PCI_DEVICE(0x8086, 0x3b56),
2c1350fd 2418 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
f748abcc 2419 /* Poulsbo */
9477c58e 2420 { PCI_DEVICE(0x8086, 0x811b),
6603249d 2421 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
f748abcc 2422 /* Oaktrail */
09904b95 2423 { PCI_DEVICE(0x8086, 0x080a),
6603249d 2424 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
e44007e0
CCE		 2425 /* BayTrail */
2426 { PCI_DEVICE(0x8086, 0x0f04),
40cc2392 2427 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
f31b2ffc
LY		 2428 /* Braswell */
2429 { PCI_DEVICE(0x8086, 0x2284),
2d846c74 2430 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
b42b4afb 2431 /* ICH6 */
8b0bd226 2432 { PCI_DEVICE(0x8086, 0x2668),
b42b4afb
TI		 2433 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2434 /* ICH7 */
8b0bd226 2435 { PCI_DEVICE(0x8086, 0x27d8),
b42b4afb
TI		 2436 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2437 /* ESB2 */
8b0bd226 2438 { PCI_DEVICE(0x8086, 0x269a),
b42b4afb
TI		 2439 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2440 /* ICH8 */
8b0bd226 2441 { PCI_DEVICE(0x8086, 0x284b),
b42b4afb
TI		 2442 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2443 /* ICH9 */
8b0bd226 2444 { PCI_DEVICE(0x8086, 0x293e),
b42b4afb
TI		 2445 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2446 /* ICH9 */
8b0bd226 2447 { PCI_DEVICE(0x8086, 0x293f),
b42b4afb
TI		 2448 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2449 /* ICH10 */
8b0bd226 2450 { PCI_DEVICE(0x8086, 0x3a3e),
b42b4afb
TI		 2451 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2452 /* ICH10 */
8b0bd226 2453 { PCI_DEVICE(0x8086, 0x3a6e),
b42b4afb 2454 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
b6864535
TI		 2455 /* Generic Intel */
2456 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2457 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2458 .class_mask = 0xffffff,
103884a3 2459 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
9477c58e
TI		 2460 /* ATI SB 450/600/700/800/900 */
2461 { PCI_DEVICE(0x1002, 0x437b),
2462 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2463 { PCI_DEVICE(0x1002, 0x4383),
2464 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2465 /* AMD Hudson */
2466 { PCI_DEVICE(0x1022, 0x780d),
2467 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
4ba5cb82
VM		 2468 /* AMD Raven */
2469 { PCI_DEVICE(0x1022, 0x15e3),
2470 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
87218e9c 2471 /* ATI HDMI */
fd48331f
MSB		 2472 { PCI_DEVICE(0x1002, 0x0002),
2473 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
650474fb
AD		 2474 { PCI_DEVICE(0x1002, 0x1308),
2475 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2476 { PCI_DEVICE(0x1002, 0x157a),
2477 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
d716fb03
AB		 2478 { PCI_DEVICE(0x1002, 0x15b3),
2479 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2480 { PCI_DEVICE(0x1002, 0x793b),
2481 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2482 { PCI_DEVICE(0x1002, 0x7919),
2483 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2484 { PCI_DEVICE(0x1002, 0x960f),
2485 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2486 { PCI_DEVICE(0x1002, 0x970f),
2487 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
650474fb
AD		 2488 { PCI_DEVICE(0x1002, 0x9840),
2489 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
9477c58e
TI		 2490 { PCI_DEVICE(0x1002, 0xaa00),
2491 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2492 { PCI_DEVICE(0x1002, 0xaa08),
2493 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2494 { PCI_DEVICE(0x1002, 0xaa10),
2495 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2496 { PCI_DEVICE(0x1002, 0xaa18),
2497 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2498 { PCI_DEVICE(0x1002, 0xaa20),
2499 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2500 { PCI_DEVICE(0x1002, 0xaa28),
2501 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2502 { PCI_DEVICE(0x1002, 0xaa30),
2503 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2504 { PCI_DEVICE(0x1002, 0xaa38),
2505 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2506 { PCI_DEVICE(0x1002, 0xaa40),
2507 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2508 { PCI_DEVICE(0x1002, 0xaa48),
2509 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
bbaa0d66
CL		 2510 { PCI_DEVICE(0x1002, 0xaa50),
2511 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512 { PCI_DEVICE(0x1002, 0xaa58),
2513 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2514 { PCI_DEVICE(0x1002, 0xaa60),
2515 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2516 { PCI_DEVICE(0x1002, 0xaa68),
2517 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2518 { PCI_DEVICE(0x1002, 0xaa80),
2519 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2520 { PCI_DEVICE(0x1002, 0xaa88),
2521 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2522 { PCI_DEVICE(0x1002, 0xaa90),
2523 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2524 { PCI_DEVICE(0x1002, 0xaa98),
2525 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
1815b34a 2526 { PCI_DEVICE(0x1002, 0x9902),
37e661ee 2527 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2528 { PCI_DEVICE(0x1002, 0xaaa0),
37e661ee 2529 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2530 { PCI_DEVICE(0x1002, 0xaaa8),
37e661ee 2531 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
1815b34a 2532 { PCI_DEVICE(0x1002, 0xaab0),
37e661ee 2533 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2534 { PCI_DEVICE(0x1002, 0xaac0),
2535 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
0fa372b6
TI		 2536 { PCI_DEVICE(0x1002, 0xaac8),
2537 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
5022813d
MSB		 2538 { PCI_DEVICE(0x1002, 0xaad8),
2539 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2540 { PCI_DEVICE(0x1002, 0xaae8),
2541 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
8eb22214
MSB		 2542 { PCI_DEVICE(0x1002, 0xaae0),
2543 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2544 { PCI_DEVICE(0x1002, 0xaaf0),
2545 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
87218e9c 2546 /* VIA VT8251/VT8237A */
26f05717 2547 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
754fdff8
AL		 2548 /* VIA GFX VT7122/VX900 */
2549 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2550 /* VIA GFX VT6122/VX11 */
2551 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
87218e9c
TI		 2552 /* SIS966 */
2553 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2554 /* ULI M5461 */
2555 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2556 /* NVIDIA MCP */
0c2fd1bf
TI		 2557 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2558 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2559 .class_mask = 0xffffff,
9477c58e 2560 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
f269002e 2561 /* Teradici */
9477c58e
TI		 2562 { PCI_DEVICE(0x6549, 0x1200),
2563 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
f0b3da98
LD		 2564 { PCI_DEVICE(0x6549, 0x2200),
2565 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4e01f54b 2566 /* Creative X-Fi (CA0110-IBG) */
f2a8ecaf
TI		 2567 /* CTHDA chips */
2568 { PCI_DEVICE(0x1102, 0x0010),
2569 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2570 { PCI_DEVICE(0x1102, 0x0012),
2571 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
8eeaa2f9 2572#if !IS_ENABLED(CONFIG_SND_CTXFI)
313f6e2d
TI		 2573 /* the following entry conflicts with snd-ctxfi driver,
2574 * as ctxfi driver mutates from HD-audio to native mode with
2575 * a special command sequence.
2576 */
4e01f54b
TI		 2577 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2578 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2579 .class_mask = 0xffffff,
9477c58e 2580 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2581 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d
TI		 2582#else
2583 /* this entry seems still valid -- i.e. without emu20kx chip */
9477c58e
TI		 2584 { PCI_DEVICE(0x1102, 0x0009),
2585 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
ef85f299 2586 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
313f6e2d 2587#endif
c563f473
TI		 2588 /* CM8888 */
2589 { PCI_DEVICE(0x13f6, 0x5011),
2590 .driver_data = AZX_DRIVER_CMEDIA |
37e661ee 2591 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
e35d4b11
OS		 2592 /* Vortex86MX */
2593 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
0f0714c5
BB		 2594 /* VMware HDAudio */
2595 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
9176b672 2596 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
c4da29ca
YL		 2597 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2598 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2599 .class_mask = 0xffffff,
9477c58e 2600 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
9176b672
AB		 2601 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2602 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2603 .class_mask = 0xffffff,
9477c58e 2604 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
1da177e4
LT		 2605 { 0, }
2606};
2607MODULE_DEVICE_TABLE(pci, azx_ids);
2608
2609/* pci_driver definition */
e9f66d9b 2610static struct pci_driver azx_driver = {
3733e424 2611 .name = KBUILD_MODNAME,
1da177e4
LT		 2612 .id_table = azx_ids,
2613 .probe = azx_probe,
e23e7a14 2614 .remove = azx_remove,
b2a0bafa 2615 .shutdown = azx_shutdown,
68cb2b55
TI		 2616 .driver = {
2617 .pm = AZX_PM_OPS,
2618 },
1da177e4
LT		 2619};
2620
e9f66d9b 2621module_pci_driver(azx_driver);
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