[mirror_ubuntu-bionic-kernel.git] / sound / pci / hda / hda_tegra.c

/*
 *
 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 */

#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mutex.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <linux/time.h>

#include <sound/core.h>
#include <sound/initval.h>

#include "hda_codec.h"
#include "hda_controller.h"

/* Defines for Nvidia Tegra HDA support */
#define HDA_BAR0           0x8000

#define HDA_CFG_CMD        0x1004
#define HDA_CFG_BAR0       0x1010

#define HDA_ENABLE_IO_SPACE       (1 << 0)
#define HDA_ENABLE_MEM_SPACE      (1 << 1)
#define HDA_ENABLE_BUS_MASTER     (1 << 2)
#define HDA_ENABLE_SERR           (1 << 8)
#define HDA_DISABLE_INTR          (1 << 10)
#define HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
#define HDA_BAR0_FINAL_PROGRAM    (1 << 14)

/* IPFS */
#define HDA_IPFS_CONFIG           0x180
#define HDA_IPFS_EN_FPCI          0x1

#define HDA_IPFS_FPCI_BAR0        0x80
#define HDA_FPCI_BAR0_START       0x40

#define HDA_IPFS_INTR_MASK        0x188
#define HDA_IPFS_EN_INTR          (1 << 16)

/* max number of SDs */
#define NUM_CAPTURE_SD 1
#define NUM_PLAYBACK_SD 1

struct hda_tegra {
	struct azx chip;
	struct device *dev;
	struct clk *hda_clk;
	struct clk *hda2codec_2x_clk;
	struct clk *hda2hdmi_clk;
	void __iomem *regs;
};

#ifdef CONFIG_PM
static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
module_param(power_save, bint, 0644);
MODULE_PARM_DESC(power_save,
		 "Automatic power-saving timeout (in seconds, 0 = disable).");
#else
#define power_save	0
#endif

/*
 * DMA page allocation ops.
 */
static int dma_alloc_pages(struct azx *chip, int type, size_t size,
			   struct snd_dma_buffer *buf)
{
	return snd_dma_alloc_pages(type, chip->card->dev, size, buf);
}

static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
{
	snd_dma_free_pages(buf);
}

static int substream_alloc_pages(struct azx *chip,
				 struct snd_pcm_substream *substream,
				 size_t size)
{
	struct azx_dev *azx_dev = get_azx_dev(substream);

	azx_dev->bufsize = 0;
	azx_dev->period_bytes = 0;
	azx_dev->format_val = 0;
	return snd_pcm_lib_malloc_pages(substream, size);
}

static int substream_free_pages(struct azx *chip,
				struct snd_pcm_substream *substream)
{
	return snd_pcm_lib_free_pages(substream);
}

/*
 * Register access ops. Tegra HDA register access is DWORD only.
 */
static void hda_tegra_writel(u32 value, u32 *addr)
{
	writel(value, addr);
}

static u32 hda_tegra_readl(u32 *addr)
{
	return readl(addr);
}

static void hda_tegra_writew(u16 value, u16 *addr)
{
	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
	u32 v;

	v = readl(dword_addr);
	v &= ~(0xffff << shift);
	v |= value << shift;
	writel(v, dword_addr);
}

static u16 hda_tegra_readw(u16 *addr)
{
	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
	u32 v;

	v = readl(dword_addr);
	return (v >> shift) & 0xffff;
}

static void hda_tegra_writeb(u8 value, u8 *addr)
{
	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
	u32 v;

	v = readl(dword_addr);
	v &= ~(0xff << shift);
	v |= value << shift;
	writel(v, dword_addr);
}

static u8 hda_tegra_readb(u8 *addr)
{
	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
	u32 v;

	v = readl(dword_addr);
	return (v >> shift) & 0xff;
}

static const struct hda_controller_ops hda_tegra_ops = {
	.reg_writel = hda_tegra_writel,
	.reg_readl = hda_tegra_readl,
	.reg_writew = hda_tegra_writew,
	.reg_readw = hda_tegra_readw,
	.reg_writeb = hda_tegra_writeb,
	.reg_readb = hda_tegra_readb,
	.dma_alloc_pages = dma_alloc_pages,
	.dma_free_pages = dma_free_pages,
	.substream_alloc_pages = substream_alloc_pages,
	.substream_free_pages = substream_free_pages,
};

static void hda_tegra_init(struct hda_tegra *hda)
{
	u32 v;

	/* Enable PCI access */
	v = readl(hda->regs + HDA_IPFS_CONFIG);
	v |= HDA_IPFS_EN_FPCI;
	writel(v, hda->regs + HDA_IPFS_CONFIG);

	/* Enable MEM/IO space and bus master */
	v = readl(hda->regs + HDA_CFG_CMD);
	v &= ~HDA_DISABLE_INTR;
	v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
		HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
	writel(v, hda->regs + HDA_CFG_CMD);

	writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
	writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
	writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);

	v = readl(hda->regs + HDA_IPFS_INTR_MASK);
	v |= HDA_IPFS_EN_INTR;
	writel(v, hda->regs + HDA_IPFS_INTR_MASK);
}

static int hda_tegra_enable_clocks(struct hda_tegra *data)
{
	int rc;

	rc = clk_prepare_enable(data->hda_clk);
	if (rc)
		return rc;
	rc = clk_prepare_enable(data->hda2codec_2x_clk);
	if (rc)
		goto disable_hda;
	rc = clk_prepare_enable(data->hda2hdmi_clk);
	if (rc)
		goto disable_codec_2x;

	return 0;

disable_codec_2x:
	clk_disable_unprepare(data->hda2codec_2x_clk);
disable_hda:
	clk_disable_unprepare(data->hda_clk);
	return rc;
}

#ifdef CONFIG_PM_SLEEP
static void hda_tegra_disable_clocks(struct hda_tegra *data)
{
	clk_disable_unprepare(data->hda2hdmi_clk);
	clk_disable_unprepare(data->hda2codec_2x_clk);
	clk_disable_unprepare(data->hda_clk);
}

/*
 * power management
 */
static int hda_tegra_suspend(struct device *dev)
{
	struct snd_card *card = dev_get_drvdata(dev);
	struct azx *chip = card->private_data;
	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);

	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);

	azx_stop_chip(chip);
	azx_enter_link_reset(chip);
	hda_tegra_disable_clocks(hda);

	return 0;
}

static int hda_tegra_resume(struct device *dev)
{
	struct snd_card *card = dev_get_drvdata(dev);
	struct azx *chip = card->private_data;
	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);

	hda_tegra_enable_clocks(hda);

	hda_tegra_init(hda);

	azx_init_chip(chip, 1);

	snd_power_change_state(card, SNDRV_CTL_POWER_D0);

	return 0;
}
#endif /* CONFIG_PM_SLEEP */

static const struct dev_pm_ops hda_tegra_pm = {
	SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
};

/*
 * destructor
 */
static int hda_tegra_dev_free(struct snd_device *device)
{
	int i;
	struct azx *chip = device->device_data;

	azx_notifier_unregister(chip);

	if (chip->initialized) {
		for (i = 0; i < chip->num_streams; i++)
			azx_stream_stop(chip, &chip->azx_dev[i]);
		azx_stop_chip(chip);
	}

	azx_free_stream_pages(chip);

	return 0;
}

static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
{
	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
	struct device *dev = hda->dev;
	struct resource *res;
	int err;

	hda->hda_clk = devm_clk_get(dev, "hda");
	if (IS_ERR(hda->hda_clk))
		return PTR_ERR(hda->hda_clk);
	hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
	if (IS_ERR(hda->hda2codec_2x_clk))
		return PTR_ERR(hda->hda2codec_2x_clk);
	hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
	if (IS_ERR(hda->hda2hdmi_clk))
		return PTR_ERR(hda->hda2hdmi_clk);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	hda->regs = devm_ioremap_resource(dev, res);
	if (IS_ERR(hda->regs))
		return PTR_ERR(hda->regs);

	chip->remap_addr = hda->regs + HDA_BAR0;
	chip->addr = res->start + HDA_BAR0;

	err = hda_tegra_enable_clocks(hda);
	if (err)
		return err;

	hda_tegra_init(hda);

	return 0;
}

/*
 * The codecs were powered up in snd_hda_codec_new().
 * Now all initialization done, so turn them down if possible
 */
static void power_down_all_codecs(struct azx *chip)
{
	struct hda_codec *codec;
	list_for_each_entry(codec, &chip->bus->codec_list, list)
		snd_hda_power_down(codec);
}

static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
{
	struct snd_card *card = chip->card;
	int err;
	unsigned short gcap;
	int irq_id = platform_get_irq(pdev, 0);

	err = hda_tegra_init_chip(chip, pdev);
	if (err)
		return err;

	err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
			     IRQF_SHARED, KBUILD_MODNAME, chip);
	if (err) {
		dev_err(chip->card->dev,
			"unable to request IRQ %d, disabling device\n",
			irq_id);
		return err;
	}
	chip->irq = irq_id;

	synchronize_irq(chip->irq);

	gcap = azx_readw(chip, GCAP);
	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);

	/* read number of streams from GCAP register instead of using
	 * hardcoded value
	 */
	chip->capture_streams = (gcap >> 8) & 0x0f;
	chip->playback_streams = (gcap >> 12) & 0x0f;
	if (!chip->playback_streams && !chip->capture_streams) {
		/* gcap didn't give any info, switching to old method */
		chip->playback_streams = NUM_PLAYBACK_SD;
		chip->capture_streams = NUM_CAPTURE_SD;
	}
	chip->capture_index_offset = 0;
	chip->playback_index_offset = chip->capture_streams;
	chip->num_streams = chip->playback_streams + chip->capture_streams;
	chip->azx_dev = devm_kcalloc(card->dev, chip->num_streams,
				     sizeof(*chip->azx_dev), GFP_KERNEL);
	if (!chip->azx_dev)
		return -ENOMEM;

	err = azx_alloc_stream_pages(chip);
	if (err < 0)
		return err;

	/* initialize streams */
	azx_init_stream(chip);

	/* initialize chip */
	azx_init_chip(chip, 1);

	/* codec detection */
	if (!chip->codec_mask) {
		dev_err(card->dev, "no codecs found!\n");
		return -ENODEV;
	}

	strcpy(card->driver, "tegra-hda");
	strcpy(card->shortname, "tegra-hda");
	snprintf(card->longname, sizeof(card->longname),
		 "%s at 0x%lx irq %i",
		 card->shortname, chip->addr, chip->irq);

	return 0;
}

/*
 * constructor
 */
static int hda_tegra_create(struct snd_card *card,
			    unsigned int driver_caps,
			    const struct hda_controller_ops *hda_ops,
			    struct hda_tegra *hda)
{
	static struct snd_device_ops ops = {
		.dev_free = hda_tegra_dev_free,
	};
	struct azx *chip;
	int err;

	chip = &hda->chip;

	spin_lock_init(&chip->reg_lock);
	mutex_init(&chip->open_mutex);
	chip->card = card;
	chip->ops = hda_ops;
	chip->irq = -1;
	chip->driver_caps = driver_caps;
	chip->driver_type = driver_caps & 0xff;
	chip->dev_index = 0;
	INIT_LIST_HEAD(&chip->pcm_list);

	chip->codec_probe_mask = -1;

	chip->single_cmd = false;
	chip->snoop = true;

	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
	if (err < 0) {
		dev_err(card->dev, "Error creating device\n");
		return err;
	}

	return 0;
}

static const struct of_device_id hda_tegra_match[] = {
	{ .compatible = "nvidia,tegra30-hda" },
	{},
};
MODULE_DEVICE_TABLE(of, hda_tegra_match);

static int hda_tegra_probe(struct platform_device *pdev)
{
	struct snd_card *card;
	struct azx *chip;
	struct hda_tegra *hda;
	int err;
	const unsigned int driver_flags = AZX_DCAPS_RIRB_DELAY;

	hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
	if (!hda)
		return -ENOMEM;
	hda->dev = &pdev->dev;
	chip = &hda->chip;

	err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
			   THIS_MODULE, 0, &card);
	if (err < 0) {
		dev_err(&pdev->dev, "Error creating card!\n");
		return err;
	}

	err = hda_tegra_create(card, driver_flags, &hda_tegra_ops, hda);
	if (err < 0)
		goto out_free;
	card->private_data = chip;

	dev_set_drvdata(&pdev->dev, card);

	err = hda_tegra_first_init(chip, pdev);
	if (err < 0)
		goto out_free;

	/* create codec instances */
	err = azx_bus_create(chip, NULL);
	if (err < 0)
		goto out_free;

	err = azx_probe_codecs(chip, 0);
	if (err < 0)
		goto out_free;

	err = azx_codec_configure(chip);
	if (err < 0)
		goto out_free;

	/* create PCM streams */
	err = snd_hda_build_pcms(chip->bus);
	if (err < 0)
		goto out_free;

	/* create mixer controls */
	err = snd_hda_build_controls(chip->bus);
	if (err < 0)
		goto out_free;

	err = snd_card_register(chip->card);
	if (err < 0)
		goto out_free;

	chip->running = 1;
	power_down_all_codecs(chip);
	azx_notifier_register(chip);
	snd_hda_set_power_save(chip->bus, power_save * 1000);

	return 0;

out_free:
	snd_card_free(card);
	return err;
}

static int hda_tegra_remove(struct platform_device *pdev)
{
	return snd_card_free(dev_get_drvdata(&pdev->dev));
}

static struct platform_driver tegra_platform_hda = {
	.driver = {
		.name = "tegra-hda",
		.pm = &hda_tegra_pm,
		.of_match_table = hda_tegra_match,
	},
	.probe = hda_tegra_probe,
	.remove = hda_tegra_remove,
};
module_platform_driver(tegra_platform_hda);

MODULE_DESCRIPTION("Tegra HDA bus driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
3c320f3f DR	1	/*
	2	*
	3	* Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*
	17	*/
	18
	19	#include <linux/clk.h>
	20	#include <linux/clocksource.h>
	21	#include <linux/completion.h>
	22	#include <linux/delay.h>
	23	#include <linux/dma-mapping.h>
	24	#include <linux/init.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/io.h>
	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
	29	#include <linux/moduleparam.h>
	30	#include <linux/mutex.h>
	31	#include <linux/of_device.h>
3c320f3f DR	32	#include <linux/slab.h>
	33	#include <linux/time.h>
	34
	35	#include <sound/core.h>
	36	#include <sound/initval.h>
	37
	38	#include "hda_codec.h"
	39	#include "hda_controller.h"
3c320f3f DR	40
	41	/* Defines for Nvidia Tegra HDA support */
	42	#define HDA_BAR0 0x8000
	43
	44	#define HDA_CFG_CMD 0x1004
	45	#define HDA_CFG_BAR0 0x1010
	46
	47	#define HDA_ENABLE_IO_SPACE (1 << 0)
	48	#define HDA_ENABLE_MEM_SPACE (1 << 1)
	49	#define HDA_ENABLE_BUS_MASTER (1 << 2)
	50	#define HDA_ENABLE_SERR (1 << 8)
	51	#define HDA_DISABLE_INTR (1 << 10)
	52	#define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
	53	#define HDA_BAR0_FINAL_PROGRAM (1 << 14)
	54
	55	/* IPFS */
	56	#define HDA_IPFS_CONFIG 0x180
	57	#define HDA_IPFS_EN_FPCI 0x1
	58
	59	#define HDA_IPFS_FPCI_BAR0 0x80
	60	#define HDA_FPCI_BAR0_START 0x40
	61
	62	#define HDA_IPFS_INTR_MASK 0x188
	63	#define HDA_IPFS_EN_INTR (1 << 16)
	64
	65	/* max number of SDs */
	66	#define NUM_CAPTURE_SD 1
	67	#define NUM_PLAYBACK_SD 1
	68
	69	struct hda_tegra {
	70	struct azx chip;
	71	struct device *dev;
	72	struct clk *hda_clk;
	73	struct clk *hda2codec_2x_clk;
	74	struct clk *hda2hdmi_clk;
	75	void __iomem *regs;
	76	};
	77
16c23952	78	#ifdef CONFIG_PM
3c320f3f DR	79	static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
	80	module_param(power_save, bint, 0644);
	81	MODULE_PARM_DESC(power_save,
	82	"Automatic power-saving timeout (in seconds, 0 = disable).");
16c23952	83	#else
bb573928	84	#define power_save 0
16c23952	85	#endif
3c320f3f DR	86
	87	/*
	88	* DMA page allocation ops.
	89	*/
	90	static int dma_alloc_pages(struct azx *chip, int type, size_t size,
	91	struct snd_dma_buffer *buf)
	92	{
	93	return snd_dma_alloc_pages(type, chip->card->dev, size, buf);
	94	}
	95
	96	static void dma_free_pages(struct azx chip, struct snd_dma_buffer buf)
	97	{
	98	snd_dma_free_pages(buf);
	99	}
	100
	101	static int substream_alloc_pages(struct azx *chip,
	102	struct snd_pcm_substream *substream,
	103	size_t size)
	104	{
	105	struct azx_dev *azx_dev = get_azx_dev(substream);
	106
	107	azx_dev->bufsize = 0;
	108	azx_dev->period_bytes = 0;
	109	azx_dev->format_val = 0;
	110	return snd_pcm_lib_malloc_pages(substream, size);
	111	}
	112
	113	static int substream_free_pages(struct azx *chip,
	114	struct snd_pcm_substream *substream)
	115	{
	116	return snd_pcm_lib_free_pages(substream);
	117	}
	118
	119	/*
	120	* Register access ops. Tegra HDA register access is DWORD only.
	121	*/
	122	static void hda_tegra_writel(u32 value, u32 *addr)
	123	{
	124	writel(value, addr);
	125	}
	126
	127	static u32 hda_tegra_readl(u32 *addr)
	128	{
	129	return readl(addr);
	130	}
	131
	132	static void hda_tegra_writew(u16 value, u16 *addr)
	133	{
	134	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	135	void dword_addr = (void )((unsigned long)(addr) & ~0x3);
	136	u32 v;
	137
	138	v = readl(dword_addr);
	139	v &= ~(0xffff << shift);
	140	v \|= value << shift;
	141	writel(v, dword_addr);
	142	}
	143
	144	static u16 hda_tegra_readw(u16 *addr)
	145	{
	146	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	147	void dword_addr = (void )((unsigned long)(addr) & ~0x3);
	148	u32 v;
	149
150	v = readl(dword_addr);
151	return (v >> shift) & 0xffff;
152	}
153
154	static void hda_tegra_writeb(u8 value, u8 *addr)
155	{
156	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
157	void dword_addr = (void )((unsigned long)(addr) & ~0x3);
158	u32 v;
159
160	v = readl(dword_addr);
161	v &= ~(0xff << shift);
162	v \|= value << shift;
163	writel(v, dword_addr);
164	}
165
166	static u8 hda_tegra_readb(u8 *addr)
167	{
168	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
169	void dword_addr = (void )((unsigned long)(addr) & ~0x3);
170	u32 v;
171
172	v = readl(dword_addr);
173	return (v >> shift) & 0xff;
174	}
175
176	static const struct hda_controller_ops hda_tegra_ops = {
177	.reg_writel = hda_tegra_writel,
178	.reg_readl = hda_tegra_readl,
179	.reg_writew = hda_tegra_writew,
180	.reg_readw = hda_tegra_readw,
181	.reg_writeb = hda_tegra_writeb,
182	.reg_readb = hda_tegra_readb,
183	.dma_alloc_pages = dma_alloc_pages,
184	.dma_free_pages = dma_free_pages,
185	.substream_alloc_pages = substream_alloc_pages,
186	.substream_free_pages = substream_free_pages,
187	};
188
189	static void hda_tegra_init(struct hda_tegra *hda)
190	{
191	u32 v;
192
193	/* Enable PCI access */
194	v = readl(hda->regs + HDA_IPFS_CONFIG);
195	v \|= HDA_IPFS_EN_FPCI;
196	writel(v, hda->regs + HDA_IPFS_CONFIG);
197
198	/* Enable MEM/IO space and bus master */
199	v = readl(hda->regs + HDA_CFG_CMD);
200	v &= ~HDA_DISABLE_INTR;
201	v \|= HDA_ENABLE_MEM_SPACE \| HDA_ENABLE_IO_SPACE \|
202	HDA_ENABLE_BUS_MASTER \| HDA_ENABLE_SERR;
203	writel(v, hda->regs + HDA_CFG_CMD);
204
205	writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
206	writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
207	writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
208
209	v = readl(hda->regs + HDA_IPFS_INTR_MASK);
210	v \|= HDA_IPFS_EN_INTR;
211	writel(v, hda->regs + HDA_IPFS_INTR_MASK);
212	}
213
214	static int hda_tegra_enable_clocks(struct hda_tegra *data)
215	{
216	int rc;
217
218	rc = clk_prepare_enable(data->hda_clk);
219	if (rc)
220	return rc;
221	rc = clk_prepare_enable(data->hda2codec_2x_clk);
222	if (rc)
223	goto disable_hda;
224	rc = clk_prepare_enable(data->hda2hdmi_clk);
225	if (rc)
226	goto disable_codec_2x;
227
228	return 0;
229
230	disable_codec_2x:
231	clk_disable_unprepare(data->hda2codec_2x_clk);
232	disable_hda:
233	clk_disable_unprepare(data->hda_clk);
234	return rc;
235	}
236
525549d7	237	#ifdef CONFIG_PM_SLEEP
3c320f3f DR	238	static void hda_tegra_disable_clocks(struct hda_tegra *data)
	239	{
	240	clk_disable_unprepare(data->hda2hdmi_clk);
	241	clk_disable_unprepare(data->hda2codec_2x_clk);
	242	clk_disable_unprepare(data->hda_clk);
	243	}
	244
3c320f3f DR	245	/*
	246	* power management
	247	*/
	248	static int hda_tegra_suspend(struct device *dev)
	249	{
	250	struct snd_card *card = dev_get_drvdata(dev);
	251	struct azx *chip = card->private_data;
3c320f3f DR	252	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
	253
	254	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3c320f3f DR	255
	256	azx_stop_chip(chip);
	257	azx_enter_link_reset(chip);
	258	hda_tegra_disable_clocks(hda);
	259
	260	return 0;
	261	}
	262
	263	static int hda_tegra_resume(struct device *dev)
	264	{
	265	struct snd_card *card = dev_get_drvdata(dev);
	266	struct azx *chip = card->private_data;
	267	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
3c320f3f DR	268
	269	hda_tegra_enable_clocks(hda);
	270
3c320f3f DR	271	hda_tegra_init(hda);
	272
	273	azx_init_chip(chip, 1);
	274
3c320f3f DR	275	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
	276
	277	return 0;
	278	}
	279	#endif /* CONFIG_PM_SLEEP */
	280
	281	static const struct dev_pm_ops hda_tegra_pm = {
	282	SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
	283	};
	284
3c320f3f DR	285	/*
	286	* destructor
	287	*/
	288	static int hda_tegra_dev_free(struct snd_device *device)
	289	{
	290	int i;
	291	struct azx *chip = device->device_data;
	292
703c759f	293	azx_notifier_unregister(chip);
3c320f3f DR	294
	295	if (chip->initialized) {
	296	for (i = 0; i < chip->num_streams; i++)
	297	azx_stream_stop(chip, &chip->azx_dev[i]);
	298	azx_stop_chip(chip);
	299	}
	300
	301	azx_free_stream_pages(chip);
	302
	303	return 0;
	304	}
	305
	306	static int hda_tegra_init_chip(struct azx chip, struct platform_device pdev)
	307	{
	308	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
	309	struct device *dev = hda->dev;
	310	struct resource *res;
	311	int err;
	312
	313	hda->hda_clk = devm_clk_get(dev, "hda");
	314	if (IS_ERR(hda->hda_clk))
	315	return PTR_ERR(hda->hda_clk);
	316	hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
	317	if (IS_ERR(hda->hda2codec_2x_clk))
	318	return PTR_ERR(hda->hda2codec_2x_clk);
	319	hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
	320	if (IS_ERR(hda->hda2hdmi_clk))
	321	return PTR_ERR(hda->hda2hdmi_clk);
	322
	323	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	324	hda->regs = devm_ioremap_resource(dev, res);
93ceaa30 EB	325	if (IS_ERR(hda->regs))
93ceaa30 EB	326	return PTR_ERR(hda->regs);
3c320f3f DR	327
	328	chip->remap_addr = hda->regs + HDA_BAR0;
	329	chip->addr = res->start + HDA_BAR0;
	330
	331	err = hda_tegra_enable_clocks(hda);
	332	if (err)
	333	return err;
	334
	335	hda_tegra_init(hda);
	336
	337	return 0;
	338	}
	339
	340	/*
	341	* The codecs were powered up in snd_hda_codec_new().
	342	* Now all initialization done, so turn them down if possible
	343	*/
	344	static void power_down_all_codecs(struct azx *chip)
	345	{
	346	struct hda_codec *codec;
	347	list_for_each_entry(codec, &chip->bus->codec_list, list)
	348	snd_hda_power_down(codec);
	349	}
	350
	351	static int hda_tegra_first_init(struct azx chip, struct platform_device pdev)
	352	{
	353	struct snd_card *card = chip->card;
	354	int err;
	355	unsigned short gcap;
	356	int irq_id = platform_get_irq(pdev, 0);
	357
	358	err = hda_tegra_init_chip(chip, pdev);
	359	if (err)
	360	return err;
	361
	362	err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
	363	IRQF_SHARED, KBUILD_MODNAME, chip);
	364	if (err) {
	365	dev_err(chip->card->dev,
	366	"unable to request IRQ %d, disabling device\n",
	367	irq_id);
	368	return err;
	369	}
	370	chip->irq = irq_id;
	371
	372	synchronize_irq(chip->irq);
	373
	374	gcap = azx_readw(chip, GCAP);
	375	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
	376
	377	/* read number of streams from GCAP register instead of using
	378	* hardcoded value
	379	*/
	380	chip->capture_streams = (gcap >> 8) & 0x0f;
	381	chip->playback_streams = (gcap >> 12) & 0x0f;
	382	if (!chip->playback_streams && !chip->capture_streams) {
	383	/* gcap didn't give any info, switching to old method */
	384	chip->playback_streams = NUM_PLAYBACK_SD;
	385	chip->capture_streams = NUM_CAPTURE_SD;
	386	}
	387	chip->capture_index_offset = 0;
	388	chip->playback_index_offset = chip->capture_streams;
	389	chip->num_streams = chip->playback_streams + chip->capture_streams;
	390	chip->azx_dev = devm_kcalloc(card->dev, chip->num_streams,
391	sizeof(*chip->azx_dev), GFP_KERNEL);
392	if (!chip->azx_dev)
393	return -ENOMEM;
394
395	err = azx_alloc_stream_pages(chip);
396	if (err < 0)
397	return err;
398
399	/* initialize streams */
400	azx_init_stream(chip);
401
402	/* initialize chip */
403	azx_init_chip(chip, 1);
404
405	/* codec detection */
406	if (!chip->codec_mask) {
407	dev_err(card->dev, "no codecs found!\n");
408	return -ENODEV;
409	}
410
411	strcpy(card->driver, "tegra-hda");
412	strcpy(card->shortname, "tegra-hda");
413	snprintf(card->longname, sizeof(card->longname),
414	"%s at 0x%lx irq %i",
415	card->shortname, chip->addr, chip->irq);
416
417	return 0;
418	}
419
420	/*
421	* constructor
422	*/
423	static int hda_tegra_create(struct snd_card *card,
424	unsigned int driver_caps,
425	const struct hda_controller_ops *hda_ops,
426	struct hda_tegra *hda)
427	{
428	static struct snd_device_ops ops = {
429	.dev_free = hda_tegra_dev_free,
430	};
431	struct azx *chip;
432	int err;
433
434	chip = &hda->chip;
435
436	spin_lock_init(&chip->reg_lock);
437	mutex_init(&chip->open_mutex);
438	chip->card = card;
439	chip->ops = hda_ops;
440	chip->irq = -1;
441	chip->driver_caps = driver_caps;
442	chip->driver_type = driver_caps & 0xff;
443	chip->dev_index = 0;
444	INIT_LIST_HEAD(&chip->pcm_list);
3c320f3f	445
3c320f3f DR	446	chip->codec_probe_mask = -1;
	447
	448	chip->single_cmd = false;
	449	chip->snoop = true;
	450
	451	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
	452	if (err < 0) {
	453	dev_err(card->dev, "Error creating device\n");
	454	return err;
	455	}
	456
	457	return 0;
	458	}
	459
	460	static const struct of_device_id hda_tegra_match[] = {
	461	{ .compatible = "nvidia,tegra30-hda" },
	462	{},
	463	};
f73387cb	464	MODULE_DEVICE_TABLE(of, hda_tegra_match);
3c320f3f DR	465
	466	static int hda_tegra_probe(struct platform_device *pdev)
	467	{
	468	struct snd_card *card;
	469	struct azx *chip;
	470	struct hda_tegra *hda;
	471	int err;
	472	const unsigned int driver_flags = AZX_DCAPS_RIRB_DELAY;
	473
	474	hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
	475	if (!hda)
	476	return -ENOMEM;
	477	hda->dev = &pdev->dev;
	478	chip = &hda->chip;
	479
	480	err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
	481	THIS_MODULE, 0, &card);
	482	if (err < 0) {
	483	dev_err(&pdev->dev, "Error creating card!\n");
	484	return err;
	485	}
	486
	487	err = hda_tegra_create(card, driver_flags, &hda_tegra_ops, hda);
	488	if (err < 0)
	489	goto out_free;
	490	card->private_data = chip;
	491
	492	dev_set_drvdata(&pdev->dev, card);
	493
	494	err = hda_tegra_first_init(chip, pdev);
	495	if (err < 0)
	496	goto out_free;
	497
	498	/* create codec instances */
bb573928	499	err = azx_bus_create(chip, NULL);
96d2bd6e TI	500	if (err < 0)
	501	goto out_free;
	502
	503	err = azx_probe_codecs(chip, 0);
3c320f3f DR	504	if (err < 0)
	505	goto out_free;
	506
	507	err = azx_codec_configure(chip);
	508	if (err < 0)
	509	goto out_free;
	510
	511	/* create PCM streams */
	512	err = snd_hda_build_pcms(chip->bus);
	513	if (err < 0)
	514	goto out_free;
	515
	516	/* create mixer controls */
b8f28d53	517	err = snd_hda_build_controls(chip->bus);
3c320f3f DR	518	if (err < 0)
	519	goto out_free;
	520
	521	err = snd_card_register(chip->card);
	522	if (err < 0)
	523	goto out_free;
	524
	525	chip->running = 1;
	526	power_down_all_codecs(chip);
703c759f	527	azx_notifier_register(chip);
bb573928	528	snd_hda_set_power_save(chip->bus, power_save * 1000);
3c320f3f DR	529
	530	return 0;
	531
	532	out_free:
	533	snd_card_free(card);
	534	return err;
	535	}
	536
	537	static int hda_tegra_remove(struct platform_device *pdev)
	538	{
	539	return snd_card_free(dev_get_drvdata(&pdev->dev));
	540	}
	541
	542	static struct platform_driver tegra_platform_hda = {
	543	.driver = {
	544	.name = "tegra-hda",
	545	.pm = &hda_tegra_pm,
	546	.of_match_table = hda_tegra_match,
	547	},
	548	.probe = hda_tegra_probe,
	549	.remove = hda_tegra_remove,
	550	};
	551	module_platform_driver(tegra_platform_hda);
	552
	553	MODULE_DESCRIPTION("Tegra HDA bus driver");
	554	MODULE_LICENSE("GPL v2");