[mirror_ubuntu-bionic-kernel.git] / sound / pci / hda / hda_tegra.c

/*
 *
 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 */

#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/mutex.h>
#include <linux/of_device.h>
#include <linux/reboot.h>
#include <linux/slab.h>
#include <linux/time.h>

#include <sound/core.h>
#include <sound/initval.h>

#include "hda_codec.h"
#include "hda_controller.h"
#include "hda_priv.h"

/* Defines for Nvidia Tegra HDA support */
#define HDA_BAR0           0x8000

#define HDA_CFG_CMD        0x1004
#define HDA_CFG_BAR0       0x1010

#define HDA_ENABLE_IO_SPACE       (1 << 0)
#define HDA_ENABLE_MEM_SPACE      (1 << 1)
#define HDA_ENABLE_BUS_MASTER     (1 << 2)
#define HDA_ENABLE_SERR           (1 << 8)
#define HDA_DISABLE_INTR          (1 << 10)
#define HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
#define HDA_BAR0_FINAL_PROGRAM    (1 << 14)

/* IPFS */
#define HDA_IPFS_CONFIG           0x180
#define HDA_IPFS_EN_FPCI          0x1

#define HDA_IPFS_FPCI_BAR0        0x80
#define HDA_FPCI_BAR0_START       0x40

#define HDA_IPFS_INTR_MASK        0x188
#define HDA_IPFS_EN_INTR          (1 << 16)

/* max number of SDs */
#define NUM_CAPTURE_SD 1
#define NUM_PLAYBACK_SD 1

struct hda_tegra {
	struct azx chip;
	struct device *dev;
	struct clk *hda_clk;
	struct clk *hda2codec_2x_clk;
	struct clk *hda2hdmi_clk;
	void __iomem *regs;
};

#ifdef CONFIG_PM
static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
module_param(power_save, bint, 0644);
MODULE_PARM_DESC(power_save,
		 "Automatic power-saving timeout (in seconds, 0 = disable).");
#else
static int power_save = 0;
#endif

/*
 * DMA page allocation ops.
 */
static int dma_alloc_pages(struct azx *chip, int type, size_t size,
			   struct snd_dma_buffer *buf)
{
	return snd_dma_alloc_pages(type, chip->card->dev, size, buf);
}

static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
{
	snd_dma_free_pages(buf);
}

static int substream_alloc_pages(struct azx *chip,
				 struct snd_pcm_substream *substream,
				 size_t size)
{
	struct azx_dev *azx_dev = get_azx_dev(substream);

	azx_dev->bufsize = 0;
	azx_dev->period_bytes = 0;
	azx_dev->format_val = 0;
	return snd_pcm_lib_malloc_pages(substream, size);
}

static int substream_free_pages(struct azx *chip,
				struct snd_pcm_substream *substream)
{
	return snd_pcm_lib_free_pages(substream);
}

/*
 * Register access ops. Tegra HDA register access is DWORD only.
 */
static void hda_tegra_writel(u32 value, u32 *addr)
{
	writel(value, addr);
}

static u32 hda_tegra_readl(u32 *addr)
{
	return readl(addr);
}

static void hda_tegra_writew(u16 value, u16 *addr)
{
	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
	u32 v;

	v = readl(dword_addr);
	v &= ~(0xffff << shift);
	v |= value << shift;
	writel(v, dword_addr);
}

static u16 hda_tegra_readw(u16 *addr)
{
	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
	u32 v;

	v = readl(dword_addr);
	return (v >> shift) & 0xffff;
}

static void hda_tegra_writeb(u8 value, u8 *addr)
{
	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
	u32 v;

	v = readl(dword_addr);
	v &= ~(0xff << shift);
	v |= value << shift;
	writel(v, dword_addr);
}

static u8 hda_tegra_readb(u8 *addr)
{
	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
	u32 v;

	v = readl(dword_addr);
	return (v >> shift) & 0xff;
}

static const struct hda_controller_ops hda_tegra_ops = {
	.reg_writel = hda_tegra_writel,
	.reg_readl = hda_tegra_readl,
	.reg_writew = hda_tegra_writew,
	.reg_readw = hda_tegra_readw,
	.reg_writeb = hda_tegra_writeb,
	.reg_readb = hda_tegra_readb,
	.dma_alloc_pages = dma_alloc_pages,
	.dma_free_pages = dma_free_pages,
	.substream_alloc_pages = substream_alloc_pages,
	.substream_free_pages = substream_free_pages,
};

static void hda_tegra_init(struct hda_tegra *hda)
{
	u32 v;

	/* Enable PCI access */
	v = readl(hda->regs + HDA_IPFS_CONFIG);
	v |= HDA_IPFS_EN_FPCI;
	writel(v, hda->regs + HDA_IPFS_CONFIG);

	/* Enable MEM/IO space and bus master */
	v = readl(hda->regs + HDA_CFG_CMD);
	v &= ~HDA_DISABLE_INTR;
	v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
		HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
	writel(v, hda->regs + HDA_CFG_CMD);

	writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
	writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
	writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);

	v = readl(hda->regs + HDA_IPFS_INTR_MASK);
	v |= HDA_IPFS_EN_INTR;
	writel(v, hda->regs + HDA_IPFS_INTR_MASK);
}

static int hda_tegra_enable_clocks(struct hda_tegra *data)
{
	int rc;

	rc = clk_prepare_enable(data->hda_clk);
	if (rc)
		return rc;
	rc = clk_prepare_enable(data->hda2codec_2x_clk);
	if (rc)
		goto disable_hda;
	rc = clk_prepare_enable(data->hda2hdmi_clk);
	if (rc)
		goto disable_codec_2x;

	return 0;

disable_codec_2x:
	clk_disable_unprepare(data->hda2codec_2x_clk);
disable_hda:
	clk_disable_unprepare(data->hda_clk);
	return rc;
}

#ifdef CONFIG_PM_SLEEP
static void hda_tegra_disable_clocks(struct hda_tegra *data)
{
	clk_disable_unprepare(data->hda2hdmi_clk);
	clk_disable_unprepare(data->hda2codec_2x_clk);
	clk_disable_unprepare(data->hda_clk);
}

/*
 * power management
 */
static int hda_tegra_suspend(struct device *dev)
{
	struct snd_card *card = dev_get_drvdata(dev);
	struct azx *chip = card->private_data;
	struct azx_pcm *p;
	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);

	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
	list_for_each_entry(p, &chip->pcm_list, list)
		snd_pcm_suspend_all(p->pcm);
	if (chip->initialized)
		snd_hda_suspend(chip->bus);

	azx_stop_chip(chip);
	azx_enter_link_reset(chip);
	hda_tegra_disable_clocks(hda);

	return 0;
}

static int hda_tegra_resume(struct device *dev)
{
	struct snd_card *card = dev_get_drvdata(dev);
	struct azx *chip = card->private_data;
	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
	int status;

	hda_tegra_enable_clocks(hda);

	/* Read STATESTS before controller reset */
	status = azx_readw(chip, STATESTS);

	hda_tegra_init(hda);

	azx_init_chip(chip, 1);

	snd_hda_resume(chip->bus);
	snd_power_change_state(card, SNDRV_CTL_POWER_D0);

	return 0;
}
#endif /* CONFIG_PM_SLEEP */

static const struct dev_pm_ops hda_tegra_pm = {
	SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
};

/*
 * reboot notifier for hang-up problem at power-down
 */
static int hda_tegra_halt(struct notifier_block *nb, unsigned long event,
			  void *buf)
{
	struct azx *chip = container_of(nb, struct azx, reboot_notifier);
	snd_hda_bus_reboot_notify(chip->bus);
	azx_stop_chip(chip);
	return NOTIFY_OK;
}

static void hda_tegra_notifier_register(struct azx *chip)
{
	chip->reboot_notifier.notifier_call = hda_tegra_halt;
	register_reboot_notifier(&chip->reboot_notifier);
}

static void hda_tegra_notifier_unregister(struct azx *chip)
{
	if (chip->reboot_notifier.notifier_call)
		unregister_reboot_notifier(&chip->reboot_notifier);
}

/*
 * destructor
 */
static int hda_tegra_dev_free(struct snd_device *device)
{
	int i;
	struct azx *chip = device->device_data;

	hda_tegra_notifier_unregister(chip);

	if (chip->initialized) {
		for (i = 0; i < chip->num_streams; i++)
			azx_stream_stop(chip, &chip->azx_dev[i]);
		azx_stop_chip(chip);
	}

	azx_free_stream_pages(chip);

	return 0;
}

static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
{
	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
	struct device *dev = hda->dev;
	struct resource *res;
	int err;

	hda->hda_clk = devm_clk_get(dev, "hda");
	if (IS_ERR(hda->hda_clk))
		return PTR_ERR(hda->hda_clk);
	hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
	if (IS_ERR(hda->hda2codec_2x_clk))
		return PTR_ERR(hda->hda2codec_2x_clk);
	hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
	if (IS_ERR(hda->hda2hdmi_clk))
		return PTR_ERR(hda->hda2hdmi_clk);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	hda->regs = devm_ioremap_resource(dev, res);
	if (IS_ERR(chip->remap_addr))
		return PTR_ERR(chip->remap_addr);

	chip->remap_addr = hda->regs + HDA_BAR0;
	chip->addr = res->start + HDA_BAR0;

	err = hda_tegra_enable_clocks(hda);
	if (err)
		return err;

	hda_tegra_init(hda);

	return 0;
}

/*
 * The codecs were powered up in snd_hda_codec_new().
 * Now all initialization done, so turn them down if possible
 */
static void power_down_all_codecs(struct azx *chip)
{
	struct hda_codec *codec;
	list_for_each_entry(codec, &chip->bus->codec_list, list)
		snd_hda_power_down(codec);
}

static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
{
	struct snd_card *card = chip->card;
	int err;
	unsigned short gcap;
	int irq_id = platform_get_irq(pdev, 0);

	err = hda_tegra_init_chip(chip, pdev);
	if (err)
		return err;

	err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
			     IRQF_SHARED, KBUILD_MODNAME, chip);
	if (err) {
		dev_err(chip->card->dev,
			"unable to request IRQ %d, disabling device\n",
			irq_id);
		return err;
	}
	chip->irq = irq_id;

	synchronize_irq(chip->irq);

	gcap = azx_readw(chip, GCAP);
	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);

	/* read number of streams from GCAP register instead of using
	 * hardcoded value
	 */
	chip->capture_streams = (gcap >> 8) & 0x0f;
	chip->playback_streams = (gcap >> 12) & 0x0f;
	if (!chip->playback_streams && !chip->capture_streams) {
		/* gcap didn't give any info, switching to old method */
		chip->playback_streams = NUM_PLAYBACK_SD;
		chip->capture_streams = NUM_CAPTURE_SD;
	}
	chip->capture_index_offset = 0;
	chip->playback_index_offset = chip->capture_streams;
	chip->num_streams = chip->playback_streams + chip->capture_streams;
	chip->azx_dev = devm_kcalloc(card->dev, chip->num_streams,
				     sizeof(*chip->azx_dev), GFP_KERNEL);
	if (!chip->azx_dev)
		return -ENOMEM;

	err = azx_alloc_stream_pages(chip);
	if (err < 0)
		return err;

	/* initialize streams */
	azx_init_stream(chip);

	/* initialize chip */
	azx_init_chip(chip, 1);

	/* codec detection */
	if (!chip->codec_mask) {
		dev_err(card->dev, "no codecs found!\n");
		return -ENODEV;
	}

	strcpy(card->driver, "tegra-hda");
	strcpy(card->shortname, "tegra-hda");
	snprintf(card->longname, sizeof(card->longname),
		 "%s at 0x%lx irq %i",
		 card->shortname, chip->addr, chip->irq);

	return 0;
}

/*
 * constructor
 */
static int hda_tegra_create(struct snd_card *card,
			    unsigned int driver_caps,
			    const struct hda_controller_ops *hda_ops,
			    struct hda_tegra *hda)
{
	static struct snd_device_ops ops = {
		.dev_free = hda_tegra_dev_free,
	};
	struct azx *chip;
	int err;

	chip = &hda->chip;

	spin_lock_init(&chip->reg_lock);
	mutex_init(&chip->open_mutex);
	chip->card = card;
	chip->ops = hda_ops;
	chip->irq = -1;
	chip->driver_caps = driver_caps;
	chip->driver_type = driver_caps & 0xff;
	chip->dev_index = 0;
	INIT_LIST_HEAD(&chip->pcm_list);
	INIT_LIST_HEAD(&chip->list);

	chip->position_fix[0] = POS_FIX_AUTO;
	chip->position_fix[1] = POS_FIX_AUTO;
	chip->codec_probe_mask = -1;

	chip->single_cmd = false;
	chip->snoop = true;

	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
	if (err < 0) {
		dev_err(card->dev, "Error creating device\n");
		return err;
	}

	return 0;
}

static const struct of_device_id hda_tegra_match[] = {
	{ .compatible = "nvidia,tegra30-hda" },
	{},
};
MODULE_DEVICE_TABLE(of, hda_tegra_match);

static int hda_tegra_probe(struct platform_device *pdev)
{
	struct snd_card *card;
	struct azx *chip;
	struct hda_tegra *hda;
	int err;
	const unsigned int driver_flags = AZX_DCAPS_RIRB_DELAY;

	hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
	if (!hda)
		return -ENOMEM;
	hda->dev = &pdev->dev;
	chip = &hda->chip;

	err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
			   THIS_MODULE, 0, &card);
	if (err < 0) {
		dev_err(&pdev->dev, "Error creating card!\n");
		return err;
	}

	err = hda_tegra_create(card, driver_flags, &hda_tegra_ops, hda);
	if (err < 0)
		goto out_free;
	card->private_data = chip;

	dev_set_drvdata(&pdev->dev, card);

	err = hda_tegra_first_init(chip, pdev);
	if (err < 0)
		goto out_free;

	/* create codec instances */
	err = azx_codec_create(chip, NULL, 0, &power_save);
	if (err < 0)
		goto out_free;

	err = azx_codec_configure(chip);
	if (err < 0)
		goto out_free;

	/* create PCM streams */
	err = snd_hda_build_pcms(chip->bus);
	if (err < 0)
		goto out_free;

	/* create mixer controls */
	err = azx_mixer_create(chip);
	if (err < 0)
		goto out_free;

	err = snd_card_register(chip->card);
	if (err < 0)
		goto out_free;

	chip->running = 1;
	power_down_all_codecs(chip);
	hda_tegra_notifier_register(chip);

	return 0;

out_free:
	snd_card_free(card);
	return err;
}

static int hda_tegra_remove(struct platform_device *pdev)
{
	return snd_card_free(dev_get_drvdata(&pdev->dev));
}

static struct platform_driver tegra_platform_hda = {
	.driver = {
		.name = "tegra-hda",
		.pm = &hda_tegra_pm,
		.of_match_table = hda_tegra_match,
	},
	.probe = hda_tegra_probe,
	.remove = hda_tegra_remove,
};
module_platform_driver(tegra_platform_hda);

MODULE_DESCRIPTION("Tegra HDA bus driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
3c320f3f DR	1	/*
	2	*
	3	* Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*
	17	*/
	18
	19	#include <linux/clk.h>
	20	#include <linux/clocksource.h>
	21	#include <linux/completion.h>
	22	#include <linux/delay.h>
	23	#include <linux/dma-mapping.h>
	24	#include <linux/init.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/io.h>
	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
	29	#include <linux/moduleparam.h>
	30	#include <linux/mutex.h>
	31	#include <linux/of_device.h>
	32	#include <linux/reboot.h>
	33	#include <linux/slab.h>
	34	#include <linux/time.h>
	35
	36	#include <sound/core.h>
	37	#include <sound/initval.h>
	38
	39	#include "hda_codec.h"
	40	#include "hda_controller.h"
	41	#include "hda_priv.h"
	42
	43	/* Defines for Nvidia Tegra HDA support */
	44	#define HDA_BAR0 0x8000
	45
	46	#define HDA_CFG_CMD 0x1004
	47	#define HDA_CFG_BAR0 0x1010
	48
	49	#define HDA_ENABLE_IO_SPACE (1 << 0)
	50	#define HDA_ENABLE_MEM_SPACE (1 << 1)
	51	#define HDA_ENABLE_BUS_MASTER (1 << 2)
	52	#define HDA_ENABLE_SERR (1 << 8)
	53	#define HDA_DISABLE_INTR (1 << 10)
	54	#define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
	55	#define HDA_BAR0_FINAL_PROGRAM (1 << 14)
	56
	57	/* IPFS */
	58	#define HDA_IPFS_CONFIG 0x180
	59	#define HDA_IPFS_EN_FPCI 0x1
	60
	61	#define HDA_IPFS_FPCI_BAR0 0x80
	62	#define HDA_FPCI_BAR0_START 0x40
	63
	64	#define HDA_IPFS_INTR_MASK 0x188
65	#define HDA_IPFS_EN_INTR (1 << 16)
66
67	/* max number of SDs */
68	#define NUM_CAPTURE_SD 1
69	#define NUM_PLAYBACK_SD 1
70
71	struct hda_tegra {
72	struct azx chip;
73	struct device *dev;
74	struct clk *hda_clk;
75	struct clk *hda2codec_2x_clk;
76	struct clk *hda2hdmi_clk;
77	void __iomem *regs;
78	};
79
16c23952	80	#ifdef CONFIG_PM
3c320f3f DR	81	static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
	82	module_param(power_save, bint, 0644);
	83	MODULE_PARM_DESC(power_save,
	84	"Automatic power-saving timeout (in seconds, 0 = disable).");
16c23952 AB	85	#else
	86	static int power_save = 0;
	87	#endif
3c320f3f DR	88
	89	/*
	90	* DMA page allocation ops.
	91	*/
	92	static int dma_alloc_pages(struct azx *chip, int type, size_t size,
	93	struct snd_dma_buffer *buf)
	94	{
	95	return snd_dma_alloc_pages(type, chip->card->dev, size, buf);
	96	}
	97
	98	static void dma_free_pages(struct azx chip, struct snd_dma_buffer buf)
	99	{
	100	snd_dma_free_pages(buf);
	101	}
	102
	103	static int substream_alloc_pages(struct azx *chip,
	104	struct snd_pcm_substream *substream,
	105	size_t size)
	106	{
	107	struct azx_dev *azx_dev = get_azx_dev(substream);
	108
	109	azx_dev->bufsize = 0;
	110	azx_dev->period_bytes = 0;
	111	azx_dev->format_val = 0;
	112	return snd_pcm_lib_malloc_pages(substream, size);
	113	}
	114
	115	static int substream_free_pages(struct azx *chip,
	116	struct snd_pcm_substream *substream)
	117	{
	118	return snd_pcm_lib_free_pages(substream);
	119	}
	120
	121	/*
	122	* Register access ops. Tegra HDA register access is DWORD only.
	123	*/
	124	static void hda_tegra_writel(u32 value, u32 *addr)
	125	{
	126	writel(value, addr);
	127	}
	128
	129	static u32 hda_tegra_readl(u32 *addr)
	130	{
	131	return readl(addr);
	132	}
	133
	134	static void hda_tegra_writew(u16 value, u16 *addr)
	135	{
	136	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	137	void dword_addr = (void )((unsigned long)(addr) & ~0x3);
	138	u32 v;
	139
	140	v = readl(dword_addr);
	141	v &= ~(0xffff << shift);
	142	v \|= value << shift;
	143	writel(v, dword_addr);
	144	}
	145
	146	static u16 hda_tegra_readw(u16 *addr)
	147	{
	148	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
	149	void dword_addr = (void )((unsigned long)(addr) & ~0x3);
	150	u32 v;
	151
152	v = readl(dword_addr);
153	return (v >> shift) & 0xffff;
154	}
155
156	static void hda_tegra_writeb(u8 value, u8 *addr)
157	{
158	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
159	void dword_addr = (void )((unsigned long)(addr) & ~0x3);
160	u32 v;
161
162	v = readl(dword_addr);
163	v &= ~(0xff << shift);
164	v \|= value << shift;
165	writel(v, dword_addr);
166	}
167
168	static u8 hda_tegra_readb(u8 *addr)
169	{
170	unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
171	void dword_addr = (void )((unsigned long)(addr) & ~0x3);
172	u32 v;
173
174	v = readl(dword_addr);
175	return (v >> shift) & 0xff;
176	}
177
178	static const struct hda_controller_ops hda_tegra_ops = {
179	.reg_writel = hda_tegra_writel,
180	.reg_readl = hda_tegra_readl,
181	.reg_writew = hda_tegra_writew,
182	.reg_readw = hda_tegra_readw,
183	.reg_writeb = hda_tegra_writeb,
184	.reg_readb = hda_tegra_readb,
185	.dma_alloc_pages = dma_alloc_pages,
186	.dma_free_pages = dma_free_pages,
187	.substream_alloc_pages = substream_alloc_pages,
188	.substream_free_pages = substream_free_pages,
189	};
190
191	static void hda_tegra_init(struct hda_tegra *hda)
192	{
193	u32 v;
194
195	/* Enable PCI access */
196	v = readl(hda->regs + HDA_IPFS_CONFIG);
197	v \|= HDA_IPFS_EN_FPCI;
198	writel(v, hda->regs + HDA_IPFS_CONFIG);
199
200	/* Enable MEM/IO space and bus master */
201	v = readl(hda->regs + HDA_CFG_CMD);
202	v &= ~HDA_DISABLE_INTR;
203	v \|= HDA_ENABLE_MEM_SPACE \| HDA_ENABLE_IO_SPACE \|
204	HDA_ENABLE_BUS_MASTER \| HDA_ENABLE_SERR;
205	writel(v, hda->regs + HDA_CFG_CMD);
206
207	writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
208	writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
209	writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
210
211	v = readl(hda->regs + HDA_IPFS_INTR_MASK);
212	v \|= HDA_IPFS_EN_INTR;
213	writel(v, hda->regs + HDA_IPFS_INTR_MASK);
214	}
215
216	static int hda_tegra_enable_clocks(struct hda_tegra *data)
217	{
218	int rc;
219
220	rc = clk_prepare_enable(data->hda_clk);
221	if (rc)
222	return rc;
223	rc = clk_prepare_enable(data->hda2codec_2x_clk);
224	if (rc)
225	goto disable_hda;
226	rc = clk_prepare_enable(data->hda2hdmi_clk);
227	if (rc)
228	goto disable_codec_2x;
229
230	return 0;
231
232	disable_codec_2x:
233	clk_disable_unprepare(data->hda2codec_2x_clk);
234	disable_hda:
235	clk_disable_unprepare(data->hda_clk);
236	return rc;
237	}
238
525549d7	239	#ifdef CONFIG_PM_SLEEP
3c320f3f DR	240	static void hda_tegra_disable_clocks(struct hda_tegra *data)
	241	{
	242	clk_disable_unprepare(data->hda2hdmi_clk);
	243	clk_disable_unprepare(data->hda2codec_2x_clk);
	244	clk_disable_unprepare(data->hda_clk);
	245	}
	246
3c320f3f DR	247	/*
	248	* power management
	249	*/
	250	static int hda_tegra_suspend(struct device *dev)
	251	{
	252	struct snd_card *card = dev_get_drvdata(dev);
	253	struct azx *chip = card->private_data;
	254	struct azx_pcm *p;
	255	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
	256
	257	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
	258	list_for_each_entry(p, &chip->pcm_list, list)
	259	snd_pcm_suspend_all(p->pcm);
	260	if (chip->initialized)
	261	snd_hda_suspend(chip->bus);
	262
	263	azx_stop_chip(chip);
	264	azx_enter_link_reset(chip);
	265	hda_tegra_disable_clocks(hda);
	266
	267	return 0;
	268	}
	269
	270	static int hda_tegra_resume(struct device *dev)
	271	{
	272	struct snd_card *card = dev_get_drvdata(dev);
	273	struct azx *chip = card->private_data;
	274	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
	275	int status;
	276
	277	hda_tegra_enable_clocks(hda);
	278
	279	/* Read STATESTS before controller reset */
	280	status = azx_readw(chip, STATESTS);
	281
	282	hda_tegra_init(hda);
	283
	284	azx_init_chip(chip, 1);
	285
	286	snd_hda_resume(chip->bus);
	287	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
	288
	289	return 0;
	290	}
	291	#endif /* CONFIG_PM_SLEEP */
	292
	293	static const struct dev_pm_ops hda_tegra_pm = {
	294	SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
	295	};
	296
	297	/*
	298	* reboot notifier for hang-up problem at power-down
	299	*/
	300	static int hda_tegra_halt(struct notifier_block *nb, unsigned long event,
	301	void *buf)
	302	{
	303	struct azx *chip = container_of(nb, struct azx, reboot_notifier);
	304	snd_hda_bus_reboot_notify(chip->bus);
	305	azx_stop_chip(chip);
	306	return NOTIFY_OK;
	307	}
	308
	309	static void hda_tegra_notifier_register(struct azx *chip)
	310	{
311	chip->reboot_notifier.notifier_call = hda_tegra_halt;
312	register_reboot_notifier(&chip->reboot_notifier);
313	}
314
315	static void hda_tegra_notifier_unregister(struct azx *chip)
316	{
317	if (chip->reboot_notifier.notifier_call)
318	unregister_reboot_notifier(&chip->reboot_notifier);
319	}
320
321	/*
322	* destructor
323	*/
324	static int hda_tegra_dev_free(struct snd_device *device)
325	{
326	int i;
327	struct azx *chip = device->device_data;
328
329	hda_tegra_notifier_unregister(chip);
330
331	if (chip->initialized) {
332	for (i = 0; i < chip->num_streams; i++)
333	azx_stream_stop(chip, &chip->azx_dev[i]);
334	azx_stop_chip(chip);
335	}
336
337	azx_free_stream_pages(chip);
338
339	return 0;
340	}
341
342	static int hda_tegra_init_chip(struct azx chip, struct platform_device pdev)
343	{
344	struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
345	struct device *dev = hda->dev;
346	struct resource *res;
347	int err;
348
349	hda->hda_clk = devm_clk_get(dev, "hda");
350	if (IS_ERR(hda->hda_clk))
351	return PTR_ERR(hda->hda_clk);
352	hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
353	if (IS_ERR(hda->hda2codec_2x_clk))
354	return PTR_ERR(hda->hda2codec_2x_clk);
355	hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
356	if (IS_ERR(hda->hda2hdmi_clk))
357	return PTR_ERR(hda->hda2hdmi_clk);
358
359	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
360	hda->regs = devm_ioremap_resource(dev, res);
361	if (IS_ERR(chip->remap_addr))
362	return PTR_ERR(chip->remap_addr);
363
364	chip->remap_addr = hda->regs + HDA_BAR0;
365	chip->addr = res->start + HDA_BAR0;
366
367	err = hda_tegra_enable_clocks(hda);
368	if (err)
369	return err;
370
371	hda_tegra_init(hda);
372
373	return 0;
374	}
375
376	/*
377	* The codecs were powered up in snd_hda_codec_new().
378	* Now all initialization done, so turn them down if possible
379	*/
380	static void power_down_all_codecs(struct azx *chip)
381	{
382	struct hda_codec *codec;
383	list_for_each_entry(codec, &chip->bus->codec_list, list)
384	snd_hda_power_down(codec);
385	}
386
387	static int hda_tegra_first_init(struct azx chip, struct platform_device pdev)
388	{
389	struct snd_card *card = chip->card;
390	int err;
391	unsigned short gcap;
392	int irq_id = platform_get_irq(pdev, 0);
393
394	err = hda_tegra_init_chip(chip, pdev);
395	if (err)
396	return err;
397
398	err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
399	IRQF_SHARED, KBUILD_MODNAME, chip);
400	if (err) {
401	dev_err(chip->card->dev,
402	"unable to request IRQ %d, disabling device\n",
403	irq_id);
404	return err;
405	}
406	chip->irq = irq_id;
407
408	synchronize_irq(chip->irq);
409
410	gcap = azx_readw(chip, GCAP);
411	dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
412
413	/* read number of streams from GCAP register instead of using
414	* hardcoded value
415	*/
416	chip->capture_streams = (gcap >> 8) & 0x0f;
417	chip->playback_streams = (gcap >> 12) & 0x0f;
418	if (!chip->playback_streams && !chip->capture_streams) {
419	/* gcap didn't give any info, switching to old method */
420	chip->playback_streams = NUM_PLAYBACK_SD;
421	chip->capture_streams = NUM_CAPTURE_SD;
422	}
423	chip->capture_index_offset = 0;
424	chip->playback_index_offset = chip->capture_streams;
425	chip->num_streams = chip->playback_streams + chip->capture_streams;
426	chip->azx_dev = devm_kcalloc(card->dev, chip->num_streams,
427	sizeof(*chip->azx_dev), GFP_KERNEL);
428	if (!chip->azx_dev)
429	return -ENOMEM;
430
431	err = azx_alloc_stream_pages(chip);
432	if (err < 0)
433	return err;
434
435	/* initialize streams */
436	azx_init_stream(chip);
437
438	/* initialize chip */
439	azx_init_chip(chip, 1);
440
441	/* codec detection */
442	if (!chip->codec_mask) {
443	dev_err(card->dev, "no codecs found!\n");
444	return -ENODEV;
445	}
446
447	strcpy(card->driver, "tegra-hda");
448	strcpy(card->shortname, "tegra-hda");
449	snprintf(card->longname, sizeof(card->longname),
450	"%s at 0x%lx irq %i",
451	card->shortname, chip->addr, chip->irq);
452
453	return 0;
454	}
455
456	/*
457	* constructor
458	*/
459	static int hda_tegra_create(struct snd_card *card,
460	unsigned int driver_caps,
461	const struct hda_controller_ops *hda_ops,
462	struct hda_tegra *hda)
463	{
464	static struct snd_device_ops ops = {
465	.dev_free = hda_tegra_dev_free,
466	};
467	struct azx *chip;
468	int err;
469
470	chip = &hda->chip;
471
472	spin_lock_init(&chip->reg_lock);
473	mutex_init(&chip->open_mutex);
474	chip->card = card;
475	chip->ops = hda_ops;
476	chip->irq = -1;
477	chip->driver_caps = driver_caps;
478	chip->driver_type = driver_caps & 0xff;
479	chip->dev_index = 0;
480	INIT_LIST_HEAD(&chip->pcm_list);
481	INIT_LIST_HEAD(&chip->list);
482
483	chip->position_fix[0] = POS_FIX_AUTO;
484	chip->position_fix[1] = POS_FIX_AUTO;
485	chip->codec_probe_mask = -1;
486
487	chip->single_cmd = false;
488	chip->snoop = true;
489
490	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
491	if (err < 0) {
492	dev_err(card->dev, "Error creating device\n");
493	return err;
494	}
495
496	return 0;
497	}
498
499	static const struct of_device_id hda_tegra_match[] = {
500	{ .compatible = "nvidia,tegra30-hda" },
501	{},
502	};
f73387cb	503	MODULE_DEVICE_TABLE(of, hda_tegra_match);
3c320f3f DR	504
	505	static int hda_tegra_probe(struct platform_device *pdev)
	506	{
	507	struct snd_card *card;
	508	struct azx *chip;
	509	struct hda_tegra *hda;
	510	int err;
	511	const unsigned int driver_flags = AZX_DCAPS_RIRB_DELAY;
	512
	513	hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
	514	if (!hda)
	515	return -ENOMEM;
	516	hda->dev = &pdev->dev;
	517	chip = &hda->chip;
	518
	519	err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
	520	THIS_MODULE, 0, &card);
	521	if (err < 0) {
	522	dev_err(&pdev->dev, "Error creating card!\n");
	523	return err;
	524	}
	525
	526	err = hda_tegra_create(card, driver_flags, &hda_tegra_ops, hda);
	527	if (err < 0)
	528	goto out_free;
	529	card->private_data = chip;
	530
	531	dev_set_drvdata(&pdev->dev, card);
	532
	533	err = hda_tegra_first_init(chip, pdev);
	534	if (err < 0)
	535	goto out_free;
	536
	537	/* create codec instances */
	538	err = azx_codec_create(chip, NULL, 0, &power_save);
	539	if (err < 0)
	540	goto out_free;
	541
	542	err = azx_codec_configure(chip);
	543	if (err < 0)
	544	goto out_free;
	545
	546	/* create PCM streams */
	547	err = snd_hda_build_pcms(chip->bus);
	548	if (err < 0)
	549	goto out_free;
	550
	551	/* create mixer controls */
	552	err = azx_mixer_create(chip);
	553	if (err < 0)
	554	goto out_free;
	555
	556	err = snd_card_register(chip->card);
	557	if (err < 0)
	558	goto out_free;
	559
	560	chip->running = 1;
	561	power_down_all_codecs(chip);
	562	hda_tegra_notifier_register(chip);
	563
	564	return 0;
	565
	566	out_free:
	567	snd_card_free(card);
568	return err;
569	}
570
571	static int hda_tegra_remove(struct platform_device *pdev)
572	{
573	return snd_card_free(dev_get_drvdata(&pdev->dev));
574	}
575
576	static struct platform_driver tegra_platform_hda = {
577	.driver = {
578	.name = "tegra-hda",
579	.pm = &hda_tegra_pm,
580	.of_match_table = hda_tegra_match,
581	},
582	.probe = hda_tegra_probe,
583	.remove = hda_tegra_remove,
584	};
585	module_platform_driver(tegra_platform_hda);
586
587	MODULE_DESCRIPTION("Tegra HDA bus driver");
588	MODULE_LICENSE("GPL v2");