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ALSA: hda/realtek - Fix the problem of the front MIC on the Lenovo M715
[mirror_ubuntu-bionic-kernel.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
95c6e9cb
IM		 31#include <sound/core.h>
32#include "hda_codec.h"
33#include "hda_local.h"
128bc4ba 34#include "hda_auto_parser.h"
5aaca44d 35#include "hda_jack.h"
95c6e9cb 36
bcd109c0
IM		 37#include "ca0132_regs.h"
38
ef6b2ead
IM		 39/* Enable this to see controls for tuning purpose. */
40/*#define ENABLE_TUNING_CONTROLS*/
41
42#define FLOAT_ZERO 0x00000000
43#define FLOAT_ONE 0x3f800000
44#define FLOAT_TWO 0x40000000
45#define FLOAT_MINUS_5 0xc0a00000
46
ef6b2ead
IM		 47#define UNSOL_TAG_DSP 0x16
48
4aa3bb0c
IM		 49#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
50#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
51
52#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
53#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
54#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
55
56#define MASTERCONTROL 0x80
ef6b2ead
IM		 57#define MASTERCONTROL_ALLOC_DMA_CHAN 10
58#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 59
95c6e9cb
IM		 60#define WIDGET_CHIP_CTRL 0x15
61#define WIDGET_DSP_CTRL 0x16
62
4aa3bb0c
IM		 63#define MEM_CONNID_MICIN1 3
64#define MEM_CONNID_MICIN2 5
65#define MEM_CONNID_MICOUT1 12
66#define MEM_CONNID_MICOUT2 14
67#define MEM_CONNID_WUH 10
68#define MEM_CONNID_DSP 16
69#define MEM_CONNID_DMIC 100
70
71#define SCP_SET 0
72#define SCP_GET 1
73
01ef7dbf
IM		 74#define EFX_FILE "ctefx.bin"
75
24f3cede 76#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 77MODULE_FIRMWARE(EFX_FILE);
7a527ede 78#endif
01ef7dbf 79
ef6b2ead
IM		 80static char *dirstr[2] = { "Playback", "Capture" };
81
82enum {
83 SPEAKER_OUT,
84 HEADPHONE_OUT
85};
86
87enum {
88 DIGITAL_MIC,
89 LINE_MIC_IN
90};
91
92enum {
93#define VNODE_START_NID 0x80
94 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
95 VNID_MIC,
96 VNID_HP_SEL,
97 VNID_AMIC1_SEL,
98 VNID_HP_ASEL,
99 VNID_AMIC1_ASEL,
100 VNODE_END_NID,
101#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
102
103#define EFFECT_START_NID 0x90
104#define OUT_EFFECT_START_NID EFFECT_START_NID
105 SURROUND = OUT_EFFECT_START_NID,
106 CRYSTALIZER,
107 DIALOG_PLUS,
108 SMART_VOLUME,
109 X_BASS,
110 EQUALIZER,
111 OUT_EFFECT_END_NID,
112#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
113
114#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
115 ECHO_CANCELLATION = IN_EFFECT_START_NID,
116 VOICE_FOCUS,
117 MIC_SVM,
118 NOISE_REDUCTION,
119 IN_EFFECT_END_NID,
120#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
121
122 VOICEFX = IN_EFFECT_END_NID,
123 PLAY_ENHANCEMENT,
124 CRYSTAL_VOICE,
125 EFFECT_END_NID
126#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
127};
128
129/* Effects values size*/
130#define EFFECT_VALS_MAX_COUNT 12
131
e8412ca4
DR		 132/* Latency introduced by DSP blocks in milliseconds. */
133#define DSP_CAPTURE_INIT_LATENCY 0
134#define DSP_CRYSTAL_VOICE_LATENCY 124
135#define DSP_PLAYBACK_INIT_LATENCY 13
136#define DSP_PLAY_ENHANCEMENT_LATENCY 30
137#define DSP_SPEAKER_OUT_LATENCY 7
138
ef6b2ead 139struct ct_effect {
975cc02a 140 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 141 hda_nid_t nid;
142 int mid; /*effect module ID*/
143 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
144 int direct; /* 0:output; 1:input*/
145 int params; /* number of default non-on/off params */
146 /*effect default values, 1st is on/off. */
147 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
148};
149
150#define EFX_DIR_OUT 0
151#define EFX_DIR_IN 1
152
153static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
154 { .name = "Surround",
155 .nid = SURROUND,
156 .mid = 0x96,
157 .reqs = {0, 1},
158 .direct = EFX_DIR_OUT,
159 .params = 1,
160 .def_vals = {0x3F800000, 0x3F2B851F}
161 },
162 { .name = "Crystalizer",
163 .nid = CRYSTALIZER,
164 .mid = 0x96,
165 .reqs = {7, 8},
166 .direct = EFX_DIR_OUT,
167 .params = 1,
168 .def_vals = {0x3F800000, 0x3F266666}
169 },
170 { .name = "Dialog Plus",
171 .nid = DIALOG_PLUS,
172 .mid = 0x96,
173 .reqs = {2, 3},
174 .direct = EFX_DIR_OUT,
175 .params = 1,
176 .def_vals = {0x00000000, 0x3F000000}
177 },
178 { .name = "Smart Volume",
179 .nid = SMART_VOLUME,
180 .mid = 0x96,
181 .reqs = {4, 5, 6},
182 .direct = EFX_DIR_OUT,
183 .params = 2,
184 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
185 },
186 { .name = "X-Bass",
187 .nid = X_BASS,
188 .mid = 0x96,
189 .reqs = {24, 23, 25},
190 .direct = EFX_DIR_OUT,
191 .params = 2,
192 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
193 },
194 { .name = "Equalizer",
195 .nid = EQUALIZER,
196 .mid = 0x96,
197 .reqs = {9, 10, 11, 12, 13, 14,
198 15, 16, 17, 18, 19, 20},
199 .direct = EFX_DIR_OUT,
200 .params = 11,
201 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
202 0x00000000, 0x00000000, 0x00000000, 0x00000000,
203 0x00000000, 0x00000000, 0x00000000, 0x00000000}
204 },
205 { .name = "Echo Cancellation",
206 .nid = ECHO_CANCELLATION,
207 .mid = 0x95,
208 .reqs = {0, 1, 2, 3},
209 .direct = EFX_DIR_IN,
210 .params = 3,
211 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
212 },
213 { .name = "Voice Focus",
214 .nid = VOICE_FOCUS,
215 .mid = 0x95,
216 .reqs = {6, 7, 8, 9},
217 .direct = EFX_DIR_IN,
218 .params = 3,
219 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
220 },
221 { .name = "Mic SVM",
222 .nid = MIC_SVM,
223 .mid = 0x95,
224 .reqs = {44, 45},
225 .direct = EFX_DIR_IN,
226 .params = 1,
227 .def_vals = {0x00000000, 0x3F3D70A4}
228 },
229 { .name = "Noise Reduction",
230 .nid = NOISE_REDUCTION,
231 .mid = 0x95,
232 .reqs = {4, 5},
233 .direct = EFX_DIR_IN,
234 .params = 1,
235 .def_vals = {0x3F800000, 0x3F000000}
236 },
237 { .name = "VoiceFX",
238 .nid = VOICEFX,
239 .mid = 0x95,
240 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
241 .direct = EFX_DIR_IN,
242 .params = 8,
243 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
244 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
245 0x00000000}
246 }
247};
248
249/* Tuning controls */
250#ifdef ENABLE_TUNING_CONTROLS
251
252enum {
253#define TUNING_CTL_START_NID 0xC0
254 WEDGE_ANGLE = TUNING_CTL_START_NID,
255 SVM_LEVEL,
256 EQUALIZER_BAND_0,
257 EQUALIZER_BAND_1,
258 EQUALIZER_BAND_2,
259 EQUALIZER_BAND_3,
260 EQUALIZER_BAND_4,
261 EQUALIZER_BAND_5,
262 EQUALIZER_BAND_6,
263 EQUALIZER_BAND_7,
264 EQUALIZER_BAND_8,
265 EQUALIZER_BAND_9,
266 TUNING_CTL_END_NID
267#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
268};
269
270struct ct_tuning_ctl {
975cc02a 271 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 272 hda_nid_t parent_nid;
273 hda_nid_t nid;
274 int mid; /*effect module ID*/
275 int req; /*effect module request*/
276 int direct; /* 0:output; 1:input*/
277 unsigned int def_val;/*effect default values*/
278};
279
280static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
281 { .name = "Wedge Angle",
282 .parent_nid = VOICE_FOCUS,
283 .nid = WEDGE_ANGLE,
284 .mid = 0x95,
285 .req = 8,
286 .direct = EFX_DIR_IN,
287 .def_val = 0x41F00000
288 },
289 { .name = "SVM Level",
290 .parent_nid = MIC_SVM,
291 .nid = SVM_LEVEL,
292 .mid = 0x95,
293 .req = 45,
294 .direct = EFX_DIR_IN,
295 .def_val = 0x3F3D70A4
296 },
297 { .name = "EQ Band0",
298 .parent_nid = EQUALIZER,
299 .nid = EQUALIZER_BAND_0,
300 .mid = 0x96,
301 .req = 11,
302 .direct = EFX_DIR_OUT,
303 .def_val = 0x00000000
304 },
305 { .name = "EQ Band1",
306 .parent_nid = EQUALIZER,
307 .nid = EQUALIZER_BAND_1,
308 .mid = 0x96,
309 .req = 12,
310 .direct = EFX_DIR_OUT,
311 .def_val = 0x00000000
312 },
313 { .name = "EQ Band2",
314 .parent_nid = EQUALIZER,
315 .nid = EQUALIZER_BAND_2,
316 .mid = 0x96,
317 .req = 13,
318 .direct = EFX_DIR_OUT,
319 .def_val = 0x00000000
320 },
321 { .name = "EQ Band3",
322 .parent_nid = EQUALIZER,
323 .nid = EQUALIZER_BAND_3,
324 .mid = 0x96,
325 .req = 14,
326 .direct = EFX_DIR_OUT,
327 .def_val = 0x00000000
328 },
329 { .name = "EQ Band4",
330 .parent_nid = EQUALIZER,
331 .nid = EQUALIZER_BAND_4,
332 .mid = 0x96,
333 .req = 15,
334 .direct = EFX_DIR_OUT,
335 .def_val = 0x00000000
336 },
337 { .name = "EQ Band5",
338 .parent_nid = EQUALIZER,
339 .nid = EQUALIZER_BAND_5,
340 .mid = 0x96,
341 .req = 16,
342 .direct = EFX_DIR_OUT,
343 .def_val = 0x00000000
344 },
345 { .name = "EQ Band6",
346 .parent_nid = EQUALIZER,
347 .nid = EQUALIZER_BAND_6,
348 .mid = 0x96,
349 .req = 17,
350 .direct = EFX_DIR_OUT,
351 .def_val = 0x00000000
352 },
353 { .name = "EQ Band7",
354 .parent_nid = EQUALIZER,
355 .nid = EQUALIZER_BAND_7,
356 .mid = 0x96,
357 .req = 18,
358 .direct = EFX_DIR_OUT,
359 .def_val = 0x00000000
360 },
361 { .name = "EQ Band8",
362 .parent_nid = EQUALIZER,
363 .nid = EQUALIZER_BAND_8,
364 .mid = 0x96,
365 .req = 19,
366 .direct = EFX_DIR_OUT,
367 .def_val = 0x00000000
368 },
369 { .name = "EQ Band9",
370 .parent_nid = EQUALIZER,
371 .nid = EQUALIZER_BAND_9,
372 .mid = 0x96,
373 .req = 20,
374 .direct = EFX_DIR_OUT,
375 .def_val = 0x00000000
376 }
377};
378#endif
379
380/* Voice FX Presets */
381#define VOICEFX_MAX_PARAM_COUNT 9
382
383struct ct_voicefx {
384 char *name;
385 hda_nid_t nid;
386 int mid;
387 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
388};
389
390struct ct_voicefx_preset {
391 char *name; /*preset name*/
392 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
393};
394
ccd7bd3d 395static struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 396 .name = "VoiceFX Capture Switch",
397 .nid = VOICEFX,
398 .mid = 0x95,
399 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
400};
401
ccd7bd3d 402static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 403 { .name = "Neutral",
404 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
405 0x44FA0000, 0x3F800000, 0x3F800000,
406 0x3F800000, 0x00000000, 0x00000000 }
407 },
408 { .name = "Female2Male",
409 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
410 0x44FA0000, 0x3F19999A, 0x3F866666,
411 0x3F800000, 0x00000000, 0x00000000 }
412 },
413 { .name = "Male2Female",
414 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
415 0x450AC000, 0x4017AE14, 0x3F6B851F,
416 0x3F800000, 0x00000000, 0x00000000 }
417 },
418 { .name = "ScrappyKid",
419 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
420 0x44FA0000, 0x40400000, 0x3F28F5C3,
421 0x3F800000, 0x00000000, 0x00000000 }
422 },
423 { .name = "Elderly",
424 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
425 0x44E10000, 0x3FB33333, 0x3FB9999A,
426 0x3F800000, 0x3E3A2E43, 0x00000000 }
427 },
428 { .name = "Orc",
429 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
430 0x45098000, 0x3F266666, 0x3FC00000,
431 0x3F800000, 0x00000000, 0x00000000 }
432 },
433 { .name = "Elf",
434 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
435 0x45193000, 0x3F8E147B, 0x3F75C28F,
436 0x3F800000, 0x00000000, 0x00000000 }
437 },
438 { .name = "Dwarf",
439 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
440 0x45007000, 0x3F451EB8, 0x3F7851EC,
441 0x3F800000, 0x00000000, 0x00000000 }
442 },
443 { .name = "AlienBrute",
444 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
445 0x451F6000, 0x3F266666, 0x3FA7D945,
446 0x3F800000, 0x3CF5C28F, 0x00000000 }
447 },
448 { .name = "Robot",
449 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
450 0x44FA0000, 0x3FB2718B, 0x3F800000,
451 0xBC07010E, 0x00000000, 0x00000000 }
452 },
453 { .name = "Marine",
454 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
455 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
456 0x3F0A3D71, 0x00000000, 0x00000000 }
457 },
458 { .name = "Emo",
459 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
460 0x44FA0000, 0x3F800000, 0x3F800000,
461 0x3E4CCCCD, 0x00000000, 0x00000000 }
462 },
463 { .name = "DeepVoice",
464 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
465 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
466 0x3F800000, 0x00000000, 0x00000000 }
467 },
468 { .name = "Munchkin",
469 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
470 0x44FA0000, 0x3F800000, 0x3F1A043C,
471 0x3F800000, 0x00000000, 0x00000000 }
472 }
473};
474
95c6e9cb
IM		 475enum hda_cmd_vendor_io {
476 /* for DspIO node */
477 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
478 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
479
480 VENDOR_DSPIO_STATUS = 0xF01,
481 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
482 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
483 VENDOR_DSPIO_DSP_INIT = 0x703,
484 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
485 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
486
487 /* for ChipIO node */
488 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
489 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
490 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
491 VENDOR_CHIPIO_DATA_LOW = 0x300,
492 VENDOR_CHIPIO_DATA_HIGH = 0x400,
493
494 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
495 VENDOR_CHIPIO_STATUS = 0xF01,
496 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
497 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
498
4aa3bb0c
IM		 499 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
500 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
501
95c6e9cb 502 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 503 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 504
505 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
506 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
507 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
508 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
509 VENDOR_CHIPIO_FLAG_SET = 0x70F,
510 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 511 VENDOR_CHIPIO_PARAM_SET = 0x710,
512 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 513
514 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
515 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
516 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
517 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
518
4aa3bb0c
IM		 519 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
520 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
521 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
522 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
523
524 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
525 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
526 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
527 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
528 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
529 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
530
531 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 532};
533
534/*
535 * Control flag IDs
536 */
537enum control_flag_id {
538 /* Connection manager stream setup is bypassed/enabled */
539 CONTROL_FLAG_C_MGR = 0,
540 /* DSP DMA is bypassed/enabled */
541 CONTROL_FLAG_DMA = 1,
542 /* 8051 'idle' mode is disabled/enabled */
543 CONTROL_FLAG_IDLE_ENABLE = 2,
544 /* Tracker for the SPDIF-in path is bypassed/enabled */
545 CONTROL_FLAG_TRACKER = 3,
546 /* DigitalOut to Spdif2Out connection is disabled/enabled */
547 CONTROL_FLAG_SPDIF2OUT = 4,
548 /* Digital Microphone is disabled/enabled */
549 CONTROL_FLAG_DMIC = 5,
550 /* ADC_B rate is 48 kHz/96 kHz */
551 CONTROL_FLAG_ADC_B_96KHZ = 6,
552 /* ADC_C rate is 48 kHz/96 kHz */
553 CONTROL_FLAG_ADC_C_96KHZ = 7,
554 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
555 CONTROL_FLAG_DAC_96KHZ = 8,
556 /* DSP rate is 48 kHz/96 kHz */
557 CONTROL_FLAG_DSP_96KHZ = 9,
558 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
559 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
560 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
561 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
562 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
563 CONTROL_FLAG_DECODE_LOOP = 12,
564 /* De-emphasis filter on DAC-1 disabled/enabled */
565 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
566 /* De-emphasis filter on DAC-2 disabled/enabled */
567 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
568 /* De-emphasis filter on DAC-3 disabled/enabled */
569 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
570 /* High-pass filter on ADC_B disabled/enabled */
571 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
572 /* High-pass filter on ADC_C disabled/enabled */
573 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
574 /* Common mode on Port_A disabled/enabled */
575 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
576 /* Common mode on Port_D disabled/enabled */
577 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
578 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
579 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
580 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 581 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 582 /* ASI rate is 48kHz/96kHz */
583 CONTROL_FLAG_ASI_96KHZ = 22,
584 /* DAC power settings able to control attached ports no/yes */
585 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
586 /* Clock Stop OK reporting is disabled/enabled */
587 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
588 /* Number of control flags */
589 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
590};
591
592/*
593 * Control parameter IDs
594 */
4aa3bb0c 595enum control_param_id {
ef6b2ead
IM		 596 /* 0: None, 1: Mic1In*/
597 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 598 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
599 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 600 /* Port A output stage gain setting to use when 16 Ohm output
601 * impedance is selected*/
602 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
603 /* Port D output stage gain setting to use when 16 Ohm output
604 * impedance is selected*/
605 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb
IM		 606
607 /* Stream Control */
608
609 /* Select stream with the given ID */
610 CONTROL_PARAM_STREAM_ID = 24,
611 /* Source connection point for the selected stream */
612 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
613 /* Destination connection point for the selected stream */
614 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
615 /* Number of audio channels in the selected stream */
616 CONTROL_PARAM_STREAMS_CHANNELS = 27,
617 /*Enable control for the selected stream */
618 CONTROL_PARAM_STREAM_CONTROL = 28,
619
620 /* Connection Point Control */
621
622 /* Select connection point with the given ID */
623 CONTROL_PARAM_CONN_POINT_ID = 29,
624 /* Connection point sample rate */
625 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
626
627 /* Node Control */
628
629 /* Select HDA node with the given ID */
630 CONTROL_PARAM_NODE_ID = 31
631};
632
633/*
634 * Dsp Io Status codes
635 */
636enum hda_vendor_status_dspio {
637 /* Success */
638 VENDOR_STATUS_DSPIO_OK = 0x00,
639 /* Busy, unable to accept new command, the host must retry */
640 VENDOR_STATUS_DSPIO_BUSY = 0x01,
641 /* SCP command queue is full */
642 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
643 /* SCP response queue is empty */
644 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
645};
646
647/*
648 * Chip Io Status codes
649 */
650enum hda_vendor_status_chipio {
651 /* Success */
652 VENDOR_STATUS_CHIPIO_OK = 0x00,
653 /* Busy, unable to accept new command, the host must retry */
654 VENDOR_STATUS_CHIPIO_BUSY = 0x01
655};
656
657/*
658 * CA0132 sample rate
659 */
660enum ca0132_sample_rate {
661 SR_6_000 = 0x00,
662 SR_8_000 = 0x01,
663 SR_9_600 = 0x02,
664 SR_11_025 = 0x03,
665 SR_16_000 = 0x04,
666 SR_22_050 = 0x05,
667 SR_24_000 = 0x06,
668 SR_32_000 = 0x07,
669 SR_44_100 = 0x08,
670 SR_48_000 = 0x09,
671 SR_88_200 = 0x0A,
672 SR_96_000 = 0x0B,
673 SR_144_000 = 0x0C,
674 SR_176_400 = 0x0D,
675 SR_192_000 = 0x0E,
676 SR_384_000 = 0x0F,
677
678 SR_COUNT = 0x10,
679
680 SR_RATE_UNKNOWN = 0x1F
681};
682
01ef7dbf
IM		 683enum dsp_download_state {
684 DSP_DOWNLOAD_FAILED = -1,
685 DSP_DOWNLOAD_INIT = 0,
686 DSP_DOWNLOADING = 1,
687 DSP_DOWNLOADED = 2
688};
689
01ef7dbf
IM		 690/* retrieve parameters from hda format */
691#define get_hdafmt_chs(fmt) (fmt & 0xf)
692#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
693#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
694#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
695
696/*
697 * CA0132 specific
698 */
699
700struct ca0132_spec {
a7e76271
IM		 701 struct snd_kcontrol_new *mixers[5];
702 unsigned int num_mixers;
5aaca44d
IM		 703 const struct hda_verb *base_init_verbs;
704 const struct hda_verb *base_exit_verbs;
d5c016b5
GM		 705 const struct hda_verb *chip_init_verbs;
706 struct hda_verb *spec_init_verbs;
01ef7dbf 707 struct auto_pin_cfg autocfg;
5aaca44d
IM		 708
709 /* Nodes configurations */
01ef7dbf
IM		 710 struct hda_multi_out multiout;
711 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
712 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 713 unsigned int num_outputs;
01ef7dbf
IM		 714 hda_nid_t input_pins[AUTO_PIN_LAST];
715 hda_nid_t adcs[AUTO_PIN_LAST];
716 hda_nid_t dig_out;
717 hda_nid_t dig_in;
718 unsigned int num_inputs;
a7e76271
IM		 719 hda_nid_t shared_mic_nid;
720 hda_nid_t shared_out_nid;
d5c016b5
GM		 721 hda_nid_t unsol_tag_hp;
722 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 723
724 /* chip access */
725 struct mutex chipio_mutex; /* chip access mutex */
726 u32 curr_chip_addx;
727
728 /* DSP download related */
729 enum dsp_download_state dsp_state;
730 unsigned int dsp_stream_id;
731 unsigned int wait_scp;
732 unsigned int wait_scp_header;
733 unsigned int wait_num_data;
734 unsigned int scp_resp_header;
735 unsigned int scp_resp_data[4];
736 unsigned int scp_resp_count;
5aaca44d
IM		 737
738 /* mixer and effects related */
739 unsigned char dmic_ctl;
740 int cur_out_type;
741 int cur_mic_type;
742 long vnode_lvol[VNODES_COUNT];
743 long vnode_rvol[VNODES_COUNT];
744 long vnode_lswitch[VNODES_COUNT];
745 long vnode_rswitch[VNODES_COUNT];
746 long effects_switch[EFFECTS_COUNT];
747 long voicefx_val;
748 long cur_mic_boost;
44f0c978 749
993884f6
CCC		 750 struct hda_codec *codec;
751 struct delayed_work unsol_hp_work;
d5c016b5 752 int quirk;
993884f6 753
44f0c978
IM		 754#ifdef ENABLE_TUNING_CONTROLS
755 long cur_ctl_vals[TUNING_CTLS_COUNT];
756#endif
01ef7dbf
IM		 757};
758
d5c016b5
GM		 759/*
760 * CA0132 quirks table
761 */
762enum {
763 QUIRK_NONE,
764 QUIRK_ALIENWARE,
765};
766
fe14f39e
TI		 767static const struct hda_pintbl alienware_pincfgs[] = {
768 { 0x0b, 0x90170110 }, /* Builtin Speaker */
769 { 0x0c, 0x411111f0 }, /* N/A */
770 { 0x0d, 0x411111f0 }, /* N/A */
771 { 0x0e, 0x411111f0 }, /* N/A */
772 { 0x0f, 0x0321101f }, /* HP */
773 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
774 { 0x11, 0x03a11021 }, /* Mic */
775 { 0x12, 0xd5a30140 }, /* Builtin Mic */
776 { 0x13, 0x411111f0 }, /* N/A */
777 { 0x18, 0x411111f0 }, /* N/A */
778 {}
779};
780
d5c016b5 781static const struct snd_pci_quirk ca0132_quirks[] = {
5328e1ea
GM		 782 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
783 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 784 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
d5c016b5
GM		 785 {}
786};
787
01ef7dbf
IM		 788/*
789 * CA0132 codec access
790 */
399ae725 791static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 792 unsigned int verb, unsigned int parm, unsigned int *res)
793{
794 unsigned int response;
795 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
796 *res = response;
797
798 return ((response == -1) ? -1 : 0);
799}
800
801static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
802 unsigned short converter_format, unsigned int *res)
803{
804 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
805 converter_format & 0xffff, res);
806}
807
808static int codec_set_converter_stream_channel(struct hda_codec *codec,
809 hda_nid_t nid, unsigned char stream,
810 unsigned char channel, unsigned int *res)
811{
812 unsigned char converter_stream_channel = 0;
813
814 converter_stream_channel = (stream << 4) | (channel & 0x0f);
815 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
816 converter_stream_channel, res);
817}
818
819/* Chip access helper function */
820static int chipio_send(struct hda_codec *codec,
821 unsigned int reg,
822 unsigned int data)
823{
824 unsigned int res;
6d67530e 825 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 826
827 /* send bits of data specified by reg */
828 do {
829 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
830 reg, data);
831 if (res == VENDOR_STATUS_CHIPIO_OK)
832 return 0;
6d67530e
IM		 833 msleep(20);
834 } while (time_before(jiffies, timeout));
835
01ef7dbf
IM		 836 return -EIO;
837}
838
839/*
840 * Write chip address through the vendor widget -- NOT protected by the Mutex!
841 */
842static int chipio_write_address(struct hda_codec *codec,
843 unsigned int chip_addx)
844{
4861af80 845 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 846 int res;
847
4861af80
IM		 848 if (spec->curr_chip_addx == chip_addx)
849 return 0;
850
01ef7dbf
IM		 851 /* send low 16 bits of the address */
852 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
853 chip_addx & 0xffff);
854
855 if (res != -EIO) {
856 /* send high 16 bits of the address */
857 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
858 chip_addx >> 16);
859 }
860
d1600401 861 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 862
4861af80 863 return res;
01ef7dbf
IM		 864}
865
866/*
867 * Write data through the vendor widget -- NOT protected by the Mutex!
868 */
01ef7dbf
IM		 869static int chipio_write_data(struct hda_codec *codec, unsigned int data)
870{
5aaca44d 871 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 872 int res;
873
874 /* send low 16 bits of the data */
875 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
876
877 if (res != -EIO) {
878 /* send high 16 bits of the data */
879 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
880 data >> 16);
881 }
882
5aaca44d
IM		 883 /*If no error encountered, automatically increment the address
884 as per chip behaviour*/
885 spec->curr_chip_addx = (res != -EIO) ?
d1600401 886 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 887 return res;
888}
889
d5c21b88
IM		 890/*
891 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
892 */
01ef7dbf
IM		 893static int chipio_write_data_multiple(struct hda_codec *codec,
894 const u32 *data,
895 unsigned int count)
896{
897 int status = 0;
898
899 if (data == NULL) {
4e76a883 900 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 901 return -EINVAL;
902 }
903
904 while ((count-- != 0) && (status == 0))
905 status = chipio_write_data(codec, *data++);
906
907 return status;
908}
909
910
911/*
912 * Read data through the vendor widget -- NOT protected by the Mutex!
913 */
914static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
915{
5aaca44d 916 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 917 int res;
918
919 /* post read */
920 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
921
922 if (res != -EIO) {
923 /* read status */
924 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
925 }
926
927 if (res != -EIO) {
928 /* read data */
929 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
930 VENDOR_CHIPIO_HIC_READ_DATA,
931 0);
932 }
933
5aaca44d
IM		 934 /*If no error encountered, automatically increment the address
935 as per chip behaviour*/
936 spec->curr_chip_addx = (res != -EIO) ?
d1600401 937 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 938 return res;
939}
940
941/*
942 * Write given value to the given address through the chip I/O widget.
943 * protected by the Mutex
944 */
945static int chipio_write(struct hda_codec *codec,
946 unsigned int chip_addx, const unsigned int data)
947{
948 struct ca0132_spec *spec = codec->spec;
949 int err;
950
951 mutex_lock(&spec->chipio_mutex);
952
953 /* write the address, and if successful proceed to write data */
954 err = chipio_write_address(codec, chip_addx);
955 if (err < 0)
956 goto exit;
957
958 err = chipio_write_data(codec, data);
959 if (err < 0)
960 goto exit;
961
962exit:
963 mutex_unlock(&spec->chipio_mutex);
964 return err;
965}
966
d5c21b88
IM		 967/*
968 * Write multiple values to the given address through the chip I/O widget.
969 * protected by the Mutex
970 */
01ef7dbf
IM		 971static int chipio_write_multiple(struct hda_codec *codec,
972 u32 chip_addx,
973 const u32 *data,
974 unsigned int count)
975{
976 struct ca0132_spec *spec = codec->spec;
977 int status;
978
979 mutex_lock(&spec->chipio_mutex);
4861af80 980 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 981 if (status < 0)
982 goto error;
983
984 status = chipio_write_data_multiple(codec, data, count);
985error:
986 mutex_unlock(&spec->chipio_mutex);
987
988 return status;
989}
990
991/*
992 * Read the given address through the chip I/O widget
993 * protected by the Mutex
994 */
995static int chipio_read(struct hda_codec *codec,
996 unsigned int chip_addx, unsigned int *data)
997{
998 struct ca0132_spec *spec = codec->spec;
999 int err;
1000
1001 mutex_lock(&spec->chipio_mutex);
1002
1003 /* write the address, and if successful proceed to write data */
1004 err = chipio_write_address(codec, chip_addx);
1005 if (err < 0)
1006 goto exit;
1007
1008 err = chipio_read_data(codec, data);
1009 if (err < 0)
1010 goto exit;
1011
1012exit:
1013 mutex_unlock(&spec->chipio_mutex);
1014 return err;
1015}
1016
d5c21b88
IM		 1017/*
1018 * Set chip control flags through the chip I/O widget.
1019 */
01ef7dbf
IM		 1020static void chipio_set_control_flag(struct hda_codec *codec,
1021 enum control_flag_id flag_id,
1022 bool flag_state)
1023{
1024 unsigned int val;
1025 unsigned int flag_bit;
1026
1027 flag_bit = (flag_state ? 1 : 0);
1028 val = (flag_bit << 7) | (flag_id);
1029 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1030 VENDOR_CHIPIO_FLAG_SET, val);
1031}
1032
d5c21b88
IM		 1033/*
1034 * Set chip parameters through the chip I/O widget.
1035 */
01ef7dbf
IM		 1036static void chipio_set_control_param(struct hda_codec *codec,
1037 enum control_param_id param_id, int param_val)
1038{
1039 struct ca0132_spec *spec = codec->spec;
1040 int val;
1041
1042 if ((param_id < 32) && (param_val < 8)) {
1043 val = (param_val << 5) | (param_id);
1044 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1045 VENDOR_CHIPIO_PARAM_SET, val);
1046 } else {
1047 mutex_lock(&spec->chipio_mutex);
1048 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1049 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1050 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1051 param_id);
1052 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1053 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1054 param_val);
1055 }
1056 mutex_unlock(&spec->chipio_mutex);
1057 }
1058}
1059
d5c21b88
IM		 1060/*
1061 * Set sampling rate of the connection point.
1062 */
01ef7dbf
IM		 1063static void chipio_set_conn_rate(struct hda_codec *codec,
1064 int connid, enum ca0132_sample_rate rate)
1065{
1066 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1067 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1068 rate);
1069}
1070
d5c21b88
IM		 1071/*
1072 * Enable clocks.
1073 */
01ef7dbf
IM		 1074static void chipio_enable_clocks(struct hda_codec *codec)
1075{
1076 struct ca0132_spec *spec = codec->spec;
1077
1078 mutex_lock(&spec->chipio_mutex);
1079 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1080 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1081 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1082 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1083 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1084 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1085 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1086 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1087 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1088 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1089 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1090 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1091 mutex_unlock(&spec->chipio_mutex);
1092}
1093
1094/*
1095 * CA0132 DSP IO stuffs
1096 */
1097static int dspio_send(struct hda_codec *codec, unsigned int reg,
1098 unsigned int data)
1099{
b645d796 1100 int res;
6d67530e 1101 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1102
1103 /* send bits of data specified by reg to dsp */
1104 do {
1105 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1106 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1107 return res;
6d67530e
IM		 1108 msleep(20);
1109 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1110
1111 return -EIO;
1112}
1113
d5c21b88
IM		 1114/*
1115 * Wait for DSP to be ready for commands
1116 */
01ef7dbf
IM		 1117static void dspio_write_wait(struct hda_codec *codec)
1118{
4861af80
IM		 1119 int status;
1120 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1121
01ef7dbf 1122 do {
4861af80
IM		 1123 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1124 VENDOR_DSPIO_STATUS, 0);
1125 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1126 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1127 break;
1128 msleep(1);
1129 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1130}
1131
d5c21b88
IM		 1132/*
1133 * Write SCP data to DSP
1134 */
01ef7dbf
IM		 1135static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1136{
1137 struct ca0132_spec *spec = codec->spec;
1138 int status;
1139
1140 dspio_write_wait(codec);
1141
1142 mutex_lock(&spec->chipio_mutex);
1143 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1144 scp_data & 0xffff);
1145 if (status < 0)
1146 goto error;
1147
1148 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1149 scp_data >> 16);
1150 if (status < 0)
1151 goto error;
1152
1153 /* OK, now check if the write itself has executed*/
1154 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1155 VENDOR_DSPIO_STATUS, 0);
1156error:
1157 mutex_unlock(&spec->chipio_mutex);
1158
1159 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1160 -EIO : 0;
1161}
1162
d5c21b88
IM		 1163/*
1164 * Write multiple SCP data to DSP
1165 */
01ef7dbf
IM		 1166static int dspio_write_multiple(struct hda_codec *codec,
1167 unsigned int *buffer, unsigned int size)
1168{
1169 int status = 0;
1170 unsigned int count;
1171
a16fbb85 1172 if (buffer == NULL)
01ef7dbf
IM		 1173 return -EINVAL;
1174
1175 count = 0;
1176 while (count < size) {
1177 status = dspio_write(codec, *buffer++);
1178 if (status != 0)
1179 break;
1180 count++;
1181 }
1182
1183 return status;
1184}
1185
a73d511c
IM		 1186static int dspio_read(struct hda_codec *codec, unsigned int *data)
1187{
1188 int status;
1189
1190 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1191 if (status == -EIO)
1192 return status;
1193
1194 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1195 if (status == -EIO ||
1196 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1197 return -EIO;
1198
1199 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1200 VENDOR_DSPIO_SCP_READ_DATA, 0);
1201
1202 return 0;
1203}
1204
1205static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1206 unsigned int *buf_size, unsigned int size_count)
1207{
1208 int status = 0;
1209 unsigned int size = *buf_size;
1210 unsigned int count;
1211 unsigned int skip_count;
1212 unsigned int dummy;
1213
a16fbb85 1214 if (buffer == NULL)
a73d511c
IM		 1215 return -1;
1216
1217 count = 0;
1218 while (count < size && count < size_count) {
1219 status = dspio_read(codec, buffer++);
1220 if (status != 0)
1221 break;
1222 count++;
1223 }
1224
1225 skip_count = count;
1226 if (status == 0) {
1227 while (skip_count < size) {
1228 status = dspio_read(codec, &dummy);
1229 if (status != 0)
1230 break;
1231 skip_count++;
1232 }
1233 }
1234 *buf_size = count;
1235
1236 return status;
1237}
1238
d5c21b88
IM		 1239/*
1240 * Construct the SCP header using corresponding fields
1241 */
01ef7dbf
IM		 1242static inline unsigned int
1243make_scp_header(unsigned int target_id, unsigned int source_id,
1244 unsigned int get_flag, unsigned int req,
1245 unsigned int device_flag, unsigned int resp_flag,
1246 unsigned int error_flag, unsigned int data_size)
1247{
1248 unsigned int header = 0;
1249
1250 header = (data_size & 0x1f) << 27;
1251 header |= (error_flag & 0x01) << 26;
1252 header |= (resp_flag & 0x01) << 25;
1253 header |= (device_flag & 0x01) << 24;
1254 header |= (req & 0x7f) << 17;
1255 header |= (get_flag & 0x01) << 16;
1256 header |= (source_id & 0xff) << 8;
1257 header |= target_id & 0xff;
1258
1259 return header;
1260}
1261
d5c21b88
IM		 1262/*
1263 * Extract corresponding fields from SCP header
1264 */
01ef7dbf
IM		 1265static inline void
1266extract_scp_header(unsigned int header,
1267 unsigned int *target_id, unsigned int *source_id,
1268 unsigned int *get_flag, unsigned int *req,
1269 unsigned int *device_flag, unsigned int *resp_flag,
1270 unsigned int *error_flag, unsigned int *data_size)
1271{
1272 if (data_size)
1273 *data_size = (header >> 27) & 0x1f;
1274 if (error_flag)
1275 *error_flag = (header >> 26) & 0x01;
1276 if (resp_flag)
1277 *resp_flag = (header >> 25) & 0x01;
1278 if (device_flag)
1279 *device_flag = (header >> 24) & 0x01;
1280 if (req)
1281 *req = (header >> 17) & 0x7f;
1282 if (get_flag)
1283 *get_flag = (header >> 16) & 0x01;
1284 if (source_id)
1285 *source_id = (header >> 8) & 0xff;
1286 if (target_id)
1287 *target_id = header & 0xff;
1288}
1289
1290#define SCP_MAX_DATA_WORDS (16)
1291
1292/* Structure to contain any SCP message */
1293struct scp_msg {
1294 unsigned int hdr;
1295 unsigned int data[SCP_MAX_DATA_WORDS];
1296};
1297
a73d511c
IM		 1298static void dspio_clear_response_queue(struct hda_codec *codec)
1299{
1300 unsigned int dummy = 0;
1301 int status = -1;
1302
1303 /* clear all from the response queue */
1304 do {
1305 status = dspio_read(codec, &dummy);
1306 } while (status == 0);
1307}
1308
1309static int dspio_get_response_data(struct hda_codec *codec)
1310{
1311 struct ca0132_spec *spec = codec->spec;
1312 unsigned int data = 0;
1313 unsigned int count;
1314
1315 if (dspio_read(codec, &data) < 0)
1316 return -EIO;
1317
1318 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1319 spec->scp_resp_header = data;
1320 spec->scp_resp_count = data >> 27;
1321 count = spec->wait_num_data;
1322 dspio_read_multiple(codec, spec->scp_resp_data,
1323 &spec->scp_resp_count, count);
1324 return 0;
1325 }
1326
1327 return -EIO;
1328}
1329
d5c21b88
IM		 1330/*
1331 * Send SCP message to DSP
1332 */
01ef7dbf
IM		 1333static int dspio_send_scp_message(struct hda_codec *codec,
1334 unsigned char *send_buf,
1335 unsigned int send_buf_size,
1336 unsigned char *return_buf,
1337 unsigned int return_buf_size,
1338 unsigned int *bytes_returned)
1339{
1340 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1341 int status = -1;
1342 unsigned int scp_send_size = 0;
1343 unsigned int total_size;
1344 bool waiting_for_resp = false;
1345 unsigned int header;
1346 struct scp_msg *ret_msg;
1347 unsigned int resp_src_id, resp_target_id;
1348 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1349
1350 if (bytes_returned)
1351 *bytes_returned = 0;
1352
1353 /* get scp header from buffer */
1354 header = *((unsigned int *)send_buf);
1355 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1356 &device_flag, NULL, NULL, &data_size);
1357 scp_send_size = data_size + 1;
1358 total_size = (scp_send_size * 4);
1359
1360 if (send_buf_size < total_size)
1361 return -EINVAL;
1362
1363 if (get_flag || device_flag) {
1364 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1365 return -EINVAL;
1366
1367 spec->wait_scp_header = *((unsigned int *)send_buf);
1368
1369 /* swap source id with target id */
1370 resp_target_id = src_id;
1371 resp_src_id = target_id;
1372 spec->wait_scp_header &= 0xffff0000;
1373 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1374 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1375 spec->wait_scp = 1;
1376 waiting_for_resp = true;
1377 }
1378
1379 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1380 scp_send_size);
1381 if (status < 0) {
1382 spec->wait_scp = 0;
1383 return status;
1384 }
1385
1386 if (waiting_for_resp) {
6d67530e 1387 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1388 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1389 do {
1390 msleep(20);
6d67530e 1391 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1392 waiting_for_resp = false;
6d67530e 1393 if (!spec->wait_scp) {
01ef7dbf
IM		 1394 ret_msg = (struct scp_msg *)return_buf;
1395 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1396 memcpy(&ret_msg->data, spec->scp_resp_data,
1397 spec->wait_num_data);
1398 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1399 status = 0;
1400 } else {
1401 status = -EIO;
1402 }
1403 spec->wait_scp = 0;
1404 }
1405
1406 return status;
1407}
1408
d5c21b88
IM		 1409/**
1410 * Prepare and send the SCP message to DSP
1411 * @codec: the HDA codec
1412 * @mod_id: ID of the DSP module to send the command
1413 * @req: ID of request to send to the DSP module
1414 * @dir: SET or GET
1415 * @data: pointer to the data to send with the request, request specific
1416 * @len: length of the data, in bytes
1417 * @reply: point to the buffer to hold data returned for a reply
1418 * @reply_len: length of the reply buffer returned from GET
1419 *
1420 * Returns zero or a negative error code.
1421 */
01ef7dbf
IM		 1422static int dspio_scp(struct hda_codec *codec,
1423 int mod_id, int req, int dir, void *data, unsigned int len,
1424 void *reply, unsigned int *reply_len)
1425{
1426 int status = 0;
1427 struct scp_msg scp_send, scp_reply;
1428 unsigned int ret_bytes, send_size, ret_size;
1429 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1430 unsigned int reply_data_size;
1431
1432 memset(&scp_send, 0, sizeof(scp_send));
1433 memset(&scp_reply, 0, sizeof(scp_reply));
1434
1435 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1436 return -EINVAL;
1437
1438 if (dir == SCP_GET && reply == NULL) {
4e76a883 1439 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1440 return -EINVAL;
1441 }
1442
1443 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1444 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1445 return -EINVAL;
1446 }
1447
1448 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1449 0, 0, 0, len/sizeof(unsigned int));
1450 if (data != NULL && len > 0) {
1451 len = min((unsigned int)(sizeof(scp_send.data)), len);
1452 memcpy(scp_send.data, data, len);
1453 }
1454
1455 ret_bytes = 0;
1456 send_size = sizeof(unsigned int) + len;
1457 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1458 send_size, (unsigned char *)&scp_reply,
1459 sizeof(scp_reply), &ret_bytes);
1460
1461 if (status < 0) {
4e76a883 1462 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1463 return status;
1464 }
1465
1466 /* extract send and reply headers members */
1467 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1468 NULL, NULL, NULL, NULL, NULL);
1469 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1470 &reply_resp_flag, &reply_error_flag,
1471 &reply_data_size);
1472
1473 if (!send_get_flag)
1474 return 0;
1475
1476 if (reply_resp_flag && !reply_error_flag) {
1477 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1478 / sizeof(unsigned int);
1479
1480 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1481 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1482 return -EINVAL;
1483 } else if (ret_size != reply_data_size) {
4e76a883 1484 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1485 return -EINVAL;
46a049da
AB		 1486 } else if (!reply) {
1487 codec_dbg(codec, "NULL reply\n");
1488 return -EINVAL;
01ef7dbf
IM		 1489 } else {
1490 *reply_len = ret_size*sizeof(unsigned int);
1491 memcpy(reply, scp_reply.data, *reply_len);
1492 }
1493 } else {
4e76a883 1494 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 1495 return -EIO;
1496 }
1497
1498 return status;
1499}
1500
5aaca44d
IM		 1501/*
1502 * Set DSP parameters
1503 */
1504static int dspio_set_param(struct hda_codec *codec, int mod_id,
1505 int req, void *data, unsigned int len)
1506{
1507 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1508}
1509
1510static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1511 int req, unsigned int data)
1512{
1513 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1514}
1515
d5c21b88
IM		 1516/*
1517 * Allocate a DSP DMA channel via an SCP message
1518 */
01ef7dbf
IM		 1519static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1520{
1521 int status = 0;
1522 unsigned int size = sizeof(dma_chan);
1523
4e76a883 1524 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
01ef7dbf
IM		 1525 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1526 SCP_GET, NULL, 0, dma_chan, &size);
1527
1528 if (status < 0) {
4e76a883 1529 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1530 return status;
1531 }
1532
1533 if ((*dma_chan + 1) == 0) {
4e76a883 1534 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 1535 return -EBUSY;
1536 }
1537
4e76a883
TI		 1538 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1539 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 1540
1541 return status;
1542}
1543
d5c21b88
IM		 1544/*
1545 * Free a DSP DMA via an SCP message
1546 */
01ef7dbf
IM		 1547static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1548{
1549 int status = 0;
1550 unsigned int dummy = 0;
1551
4e76a883
TI		 1552 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1553 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf
IM		 1554
1555 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1556 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1557
1558 if (status < 0) {
4e76a883 1559 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1560 return status;
1561 }
1562
4e76a883 1563 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 1564
1565 return status;
1566}
1567
1568/*
d5c21b88 1569 * (Re)start the DSP
01ef7dbf
IM		 1570 */
1571static int dsp_set_run_state(struct hda_codec *codec)
1572{
1573 unsigned int dbg_ctrl_reg;
1574 unsigned int halt_state;
1575 int err;
1576
1577 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1578 if (err < 0)
1579 return err;
1580
1581 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1582 DSP_DBGCNTL_STATE_LOBIT;
1583
1584 if (halt_state != 0) {
1585 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1586 DSP_DBGCNTL_SS_MASK);
1587 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1588 dbg_ctrl_reg);
1589 if (err < 0)
1590 return err;
1591
1592 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1593 DSP_DBGCNTL_EXEC_MASK;
1594 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1595 dbg_ctrl_reg);
1596 if (err < 0)
1597 return err;
1598 }
1599
1600 return 0;
1601}
1602
d5c21b88
IM		 1603/*
1604 * Reset the DSP
1605 */
01ef7dbf
IM		 1606static int dsp_reset(struct hda_codec *codec)
1607{
1608 unsigned int res;
1609 int retry = 20;
1610
4e76a883 1611 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 1612 do {
1613 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1614 retry--;
1615 } while (res == -EIO && retry);
1616
1617 if (!retry) {
4e76a883 1618 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 1619 return -EIO;
1620 }
1621
1622 return 0;
1623}
1624
d5c21b88
IM		 1625/*
1626 * Convert chip address to DSP address
1627 */
01ef7dbf
IM		 1628static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1629 bool *code, bool *yram)
1630{
1631 *code = *yram = false;
1632
1633 if (UC_RANGE(chip_addx, 1)) {
1634 *code = true;
1635 return UC_OFF(chip_addx);
1636 } else if (X_RANGE_ALL(chip_addx, 1)) {
1637 return X_OFF(chip_addx);
1638 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1639 *yram = true;
1640 return Y_OFF(chip_addx);
1641 }
1642
4a8b89f9 1643 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 1644}
1645
d5c21b88
IM		 1646/*
1647 * Check if the DSP DMA is active
1648 */
01ef7dbf
IM		 1649static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1650{
1651 unsigned int dma_chnlstart_reg;
1652
1653 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1654
1655 return ((dma_chnlstart_reg & (1 <<
1656 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1657}
1658
1659static int dsp_dma_setup_common(struct hda_codec *codec,
1660 unsigned int chip_addx,
1661 unsigned int dma_chan,
1662 unsigned int port_map_mask,
1663 bool ovly)
1664{
1665 int status = 0;
1666 unsigned int chnl_prop;
1667 unsigned int dsp_addx;
1668 unsigned int active;
1669 bool code, yram;
1670
4e76a883 1671 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 1672
1673 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 1674 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 1675 return -EINVAL;
1676 }
1677
1678 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 1679 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 1680 return -EBUSY;
1681 }
1682
1683 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1684
1685 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 1686 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 1687 return -ENXIO;
1688 }
1689
1690 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1691 active = 0;
1692
4e76a883 1693 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 1694
1695 if (ovly) {
1696 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1697 &chnl_prop);
1698
1699 if (status < 0) {
4e76a883 1700 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 1701 return status;
1702 }
4e76a883 1703 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 1704 }
1705
1706 if (!code)
1707 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1708 else
1709 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1710
1711 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1712
1713 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1714 if (status < 0) {
4e76a883 1715 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 1716 return status;
1717 }
4e76a883 1718 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 1719
1720 if (ovly) {
1721 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1722 &active);
1723
1724 if (status < 0) {
4e76a883 1725 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 1726 return status;
1727 }
4e76a883 1728 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 1729 }
1730
1731 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1732 DSPDMAC_ACTIVE_AAR_MASK;
1733
1734 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1735 if (status < 0) {
4e76a883 1736 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 1737 return status;
1738 }
1739
4e76a883 1740 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 1741
1742 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1743 port_map_mask);
1744 if (status < 0) {
4e76a883 1745 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 1746 return status;
1747 }
4e76a883 1748 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 1749
1750 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1751 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1752 if (status < 0) {
4e76a883 1753 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 1754 return status;
1755 }
4e76a883 1756 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 1757
4e76a883 1758 codec_dbg(codec,
01ef7dbf
IM		 1759 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1760 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1761 chip_addx, dsp_addx, dma_chan,
1762 port_map_mask, chnl_prop, active);
1763
4e76a883 1764 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 1765
1766 return 0;
1767}
1768
d5c21b88
IM		 1769/*
1770 * Setup the DSP DMA per-transfer-specific registers
1771 */
01ef7dbf
IM		 1772static int dsp_dma_setup(struct hda_codec *codec,
1773 unsigned int chip_addx,
1774 unsigned int count,
1775 unsigned int dma_chan)
1776{
1777 int status = 0;
1778 bool code, yram;
1779 unsigned int dsp_addx;
1780 unsigned int addr_field;
1781 unsigned int incr_field;
1782 unsigned int base_cnt;
1783 unsigned int cur_cnt;
1784 unsigned int dma_cfg = 0;
1785 unsigned int adr_ofs = 0;
1786 unsigned int xfr_cnt = 0;
1787 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1788 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1789
4e76a883 1790 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 1791
1792 if (count > max_dma_count) {
4e76a883 1793 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 1794 return -EINVAL;
1795 }
1796
1797 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1798 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 1799 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 1800 return -ENXIO;
1801 }
1802
4e76a883 1803 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 1804
1805 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1806 incr_field = 0;
1807
1808 if (!code) {
1809 addr_field <<= 1;
1810 if (yram)
1811 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1812
1813 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1814 }
1815
1816 dma_cfg = addr_field + incr_field;
1817 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1818 dma_cfg);
1819 if (status < 0) {
4e76a883 1820 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 1821 return status;
1822 }
4e76a883 1823 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 1824
1825 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1826 (code ? 0 : 1));
1827
1828 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1829 adr_ofs);
1830 if (status < 0) {
4e76a883 1831 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 1832 return status;
1833 }
4e76a883 1834 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 1835
1836 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1837
1838 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1839
1840 xfr_cnt = base_cnt | cur_cnt;
1841
1842 status = chipio_write(codec,
1843 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1844 if (status < 0) {
4e76a883 1845 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 1846 return status;
1847 }
4e76a883 1848 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 1849
4e76a883 1850 codec_dbg(codec,
01ef7dbf
IM		 1851 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1852 "ADROFS=0x%x, XFRCNT=0x%x\n",
1853 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1854
4e76a883 1855 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 1856
1857 return 0;
1858}
1859
d5c21b88
IM		 1860/*
1861 * Start the DSP DMA
1862 */
01ef7dbf
IM		 1863static int dsp_dma_start(struct hda_codec *codec,
1864 unsigned int dma_chan, bool ovly)
1865{
1866 unsigned int reg = 0;
1867 int status = 0;
1868
4e76a883 1869 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 1870
1871 if (ovly) {
1872 status = chipio_read(codec,
1873 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1874
1875 if (status < 0) {
4e76a883 1876 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 1877 return status;
1878 }
4e76a883 1879 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 1880
1881 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1882 DSPDMAC_CHNLSTART_DIS_MASK);
1883 }
1884
1885 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1886 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1887 if (status < 0) {
4e76a883 1888 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 1889 return status;
1890 }
4e76a883 1891 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 1892
1893 return status;
1894}
1895
d5c21b88
IM		 1896/*
1897 * Stop the DSP DMA
1898 */
01ef7dbf
IM		 1899static int dsp_dma_stop(struct hda_codec *codec,
1900 unsigned int dma_chan, bool ovly)
1901{
1902 unsigned int reg = 0;
1903 int status = 0;
1904
4e76a883 1905 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 1906
1907 if (ovly) {
1908 status = chipio_read(codec,
1909 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1910
1911 if (status < 0) {
4e76a883 1912 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 1913 return status;
1914 }
4e76a883 1915 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 1916 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1917 DSPDMAC_CHNLSTART_DIS_MASK);
1918 }
1919
1920 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1921 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1922 if (status < 0) {
4e76a883 1923 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 1924 return status;
1925 }
4e76a883 1926 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 1927
1928 return status;
1929}
1930
d5c21b88
IM		 1931/**
1932 * Allocate router ports
1933 *
1934 * @codec: the HDA codec
1935 * @num_chans: number of channels in the stream
1936 * @ports_per_channel: number of ports per channel
1937 * @start_device: start device
1938 * @port_map: pointer to the port list to hold the allocated ports
1939 *
1940 * Returns zero or a negative error code.
1941 */
01ef7dbf
IM		 1942static int dsp_allocate_router_ports(struct hda_codec *codec,
1943 unsigned int num_chans,
1944 unsigned int ports_per_channel,
1945 unsigned int start_device,
1946 unsigned int *port_map)
1947{
1948 int status = 0;
1949 int res;
1950 u8 val;
1951
1952 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1953 if (status < 0)
1954 return status;
1955
1956 val = start_device << 6;
1957 val |= (ports_per_channel - 1) << 4;
1958 val |= num_chans - 1;
1959
1960 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1961 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1962 val);
1963
1964 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1965 VENDOR_CHIPIO_PORT_ALLOC_SET,
1966 MEM_CONNID_DSP);
1967
1968 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1969 if (status < 0)
1970 return status;
1971
1972 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1973 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1974
1975 *port_map = res;
1976
1977 return (res < 0) ? res : 0;
1978}
1979
d5c21b88
IM		 1980/*
1981 * Free router ports
1982 */
01ef7dbf
IM		 1983static int dsp_free_router_ports(struct hda_codec *codec)
1984{
1985 int status = 0;
1986
1987 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1988 if (status < 0)
1989 return status;
1990
1991 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1992 VENDOR_CHIPIO_PORT_FREE_SET,
1993 MEM_CONNID_DSP);
1994
1995 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1996
1997 return status;
1998}
1999
d5c21b88
IM		 2000/*
2001 * Allocate DSP ports for the download stream
2002 */
01ef7dbf
IM		 2003static int dsp_allocate_ports(struct hda_codec *codec,
2004 unsigned int num_chans,
2005 unsigned int rate_multi, unsigned int *port_map)
2006{
2007 int status;
2008
4e76a883 2009 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2010
2011 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2012 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2013 return -EINVAL;
2014 }
2015
2016 status = dsp_allocate_router_ports(codec, num_chans,
2017 rate_multi, 0, port_map);
2018
4e76a883 2019 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2020
2021 return status;
2022}
2023
01ef7dbf
IM		 2024static int dsp_allocate_ports_format(struct hda_codec *codec,
2025 const unsigned short fmt,
2026 unsigned int *port_map)
2027{
2028 int status;
2029 unsigned int num_chans;
2030
2031 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2032 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2033 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2034
2035 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2036 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2037 return -EINVAL;
2038 }
2039
2040 num_chans = get_hdafmt_chs(fmt) + 1;
2041
2042 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2043
2044 return status;
2045}
2046
d5c21b88
IM		 2047/*
2048 * free DSP ports
2049 */
2050static int dsp_free_ports(struct hda_codec *codec)
2051{
2052 int status;
2053
4e76a883 2054 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2055
2056 status = dsp_free_router_ports(codec);
2057 if (status < 0) {
4e76a883 2058 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2059 return status;
2060 }
4e76a883 2061 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2062
2063 return status;
2064}
2065
01ef7dbf
IM		 2066/*
2067 * HDA DMA engine stuffs for DSP code download
2068 */
2069struct dma_engine {
2070 struct hda_codec *codec;
2071 unsigned short m_converter_format;
2072 struct snd_dma_buffer *dmab;
2073 unsigned int buf_size;
2074};
2075
2076
2077enum dma_state {
2078 DMA_STATE_STOP = 0,
2079 DMA_STATE_RUN = 1
2080};
2081
6194b99d 2082static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2083 unsigned int sample_rate,
2084 unsigned short channels,
01ef7dbf
IM		 2085 unsigned short *hda_format)
2086{
2087 unsigned int format_val;
2088
b7d023e1
TI		 2089 format_val = snd_hdac_calc_stream_format(sample_rate,
2090 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2091
2092 if (hda_format)
2093 *hda_format = (unsigned short)format_val;
2094
2095 return 0;
2096}
2097
d5c21b88
IM		 2098/*
2099 * Reset DMA for DSP download
2100 */
01ef7dbf
IM		 2101static int dma_reset(struct dma_engine *dma)
2102{
2103 struct hda_codec *codec = dma->codec;
2104 struct ca0132_spec *spec = codec->spec;
2105 int status;
2106
b3667bd7 2107 if (dma->dmab->area)
01ef7dbf
IM		 2108 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2109
2110 status = snd_hda_codec_load_dsp_prepare(codec,
2111 dma->m_converter_format,
2112 dma->buf_size,
2113 dma->dmab);
2114 if (status < 0)
2115 return status;
2116 spec->dsp_stream_id = status;
2117 return 0;
2118}
2119
2120static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2121{
01ef7dbf
IM		 2122 bool cmd;
2123
01ef7dbf
IM		 2124 switch (state) {
2125 case DMA_STATE_STOP:
2126 cmd = false;
2127 break;
2128 case DMA_STATE_RUN:
2129 cmd = true;
2130 break;
2131 default:
c41999a2
DH		 2132 return 0;
2133 }
01ef7dbf
IM		 2134
2135 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2136 return 0;
95c6e9cb
IM		 2137}
2138
01ef7dbf
IM		 2139static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2140{
2141 return dma->dmab->bytes;
2142}
95c6e9cb 2143
01ef7dbf
IM		 2144static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2145{
2146 return dma->dmab->area;
2147}
95c6e9cb 2148
01ef7dbf
IM		 2149static int dma_xfer(struct dma_engine *dma,
2150 const unsigned int *data,
2151 unsigned int count)
2152{
2153 memcpy(dma->dmab->area, data, count);
2154 return 0;
2155}
95c6e9cb 2156
01ef7dbf
IM		 2157static void dma_get_converter_format(
2158 struct dma_engine *dma,
2159 unsigned short *format)
2160{
2161 if (format)
2162 *format = dma->m_converter_format;
2163}
95c6e9cb 2164
01ef7dbf 2165static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2166{
01ef7dbf 2167 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2168
01ef7dbf 2169 return spec->dsp_stream_id;
95c6e9cb
IM		 2170}
2171
01ef7dbf
IM		 2172struct dsp_image_seg {
2173 u32 magic;
2174 u32 chip_addr;
2175 u32 count;
2176 u32 data[0];
2177};
2178
2179static const u32 g_magic_value = 0x4c46584d;
2180static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2181
2182static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2183{
01ef7dbf
IM		 2184 return p->magic == g_magic_value;
2185}
95c6e9cb 2186
01ef7dbf
IM		 2187static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2188{
2189 return g_chip_addr_magic_value == p->chip_addr;
2190}
95c6e9cb 2191
01ef7dbf
IM		 2192static bool is_last(const struct dsp_image_seg *p)
2193{
2194 return p->count == 0;
2195}
95c6e9cb 2196
01ef7dbf
IM		 2197static size_t dsp_sizeof(const struct dsp_image_seg *p)
2198{
2199 return sizeof(*p) + p->count*sizeof(u32);
2200}
2201
2202static const struct dsp_image_seg *get_next_seg_ptr(
2203 const struct dsp_image_seg *p)
2204{
2205 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2206}
2207
2208/*
01ef7dbf 2209 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2210 */
8ae3124b 2211#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2212
d5c21b88
IM		 2213/*
2214 * Program a list of address/data pairs via the ChipIO widget.
2215 * The segment data is in the format of successive pairs of words.
2216 * These are repeated as indicated by the segment's count field.
2217 */
01ef7dbf
IM		 2218static int dspxfr_hci_write(struct hda_codec *codec,
2219 const struct dsp_image_seg *fls)
95c6e9cb 2220{
01ef7dbf
IM		 2221 int status;
2222 const u32 *data;
2223 unsigned int count;
95c6e9cb 2224
01ef7dbf 2225 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2226 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2227 return -EINVAL;
95c6e9cb
IM		 2228 }
2229
01ef7dbf
IM		 2230 count = fls->count;
2231 data = (u32 *)(fls->data);
2232 while (count >= 2) {
2233 status = chipio_write(codec, data[0], data[1]);
2234 if (status < 0) {
4e76a883 2235 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2236 return status;
2237 }
2238 count -= 2;
2239 data += 2;
2240 }
2241 return 0;
95c6e9cb
IM		 2242}
2243
d5c21b88
IM		 2244/**
2245 * Write a block of data into DSP code or data RAM using pre-allocated
2246 * DMA engine.
2247 *
2248 * @codec: the HDA codec
2249 * @fls: pointer to a fast load image
2250 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2251 * no relocation
2252 * @dma_engine: pointer to DMA engine to be used for DSP download
2253 * @dma_chan: The number of DMA channels used for DSP download
2254 * @port_map_mask: port mapping
2255 * @ovly: TRUE if overlay format is required
2256 *
2257 * Returns zero or a negative error code.
2258 */
01ef7dbf
IM		 2259static int dspxfr_one_seg(struct hda_codec *codec,
2260 const struct dsp_image_seg *fls,
2261 unsigned int reloc,
2262 struct dma_engine *dma_engine,
2263 unsigned int dma_chan,
2264 unsigned int port_map_mask,
2265 bool ovly)
95c6e9cb 2266{
406261ce 2267 int status = 0;
01ef7dbf
IM		 2268 bool comm_dma_setup_done = false;
2269 const unsigned int *data;
2270 unsigned int chip_addx;
2271 unsigned int words_to_write;
2272 unsigned int buffer_size_words;
2273 unsigned char *buffer_addx;
2274 unsigned short hda_format;
2275 unsigned int sample_rate_div;
2276 unsigned int sample_rate_mul;
2277 unsigned int num_chans;
2278 unsigned int hda_frame_size_words;
2279 unsigned int remainder_words;
2280 const u32 *data_remainder;
2281 u32 chip_addx_remainder;
2282 unsigned int run_size_words;
2283 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2284 unsigned long timeout;
2285 bool dma_active;
01ef7dbf
IM		 2286
2287 if (fls == NULL)
2288 return -EINVAL;
2289 if (is_hci_prog_list_seg(fls)) {
2290 hci_write = fls;
2291 fls = get_next_seg_ptr(fls);
2292 }
95c6e9cb 2293
01ef7dbf 2294 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2295 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2296 return dspxfr_hci_write(codec, hci_write);
2297 }
95c6e9cb 2298
01ef7dbf 2299 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2300 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2301 return -EINVAL;
95c6e9cb
IM		 2302 }
2303
01ef7dbf
IM		 2304 data = fls->data;
2305 chip_addx = fls->chip_addr,
2306 words_to_write = fls->count;
2307
2308 if (!words_to_write)
2309 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2310 if (reloc)
2311 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2312
2313 if (!UC_RANGE(chip_addx, words_to_write) &&
2314 !X_RANGE_ALL(chip_addx, words_to_write) &&
2315 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2316 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2317 return -EINVAL;
95c6e9cb
IM		 2318 }
2319
01ef7dbf
IM		 2320 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2321 sizeof(u32);
2322
2323 buffer_addx = dma_get_buffer_addr(dma_engine);
2324
2325 if (buffer_addx == NULL) {
4e76a883 2326 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2327 return -EINVAL;
2328 }
2329
2330 dma_get_converter_format(dma_engine, &hda_format);
2331 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2332 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2333 num_chans = get_hdafmt_chs(hda_format) + 1;
2334
2335 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2336 (num_chans * sample_rate_mul / sample_rate_div));
2337
3bc085a1 2338 if (hda_frame_size_words == 0) {
4e76a883 2339 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2340 return -EINVAL;
2341 }
2342
01ef7dbf
IM		 2343 buffer_size_words = min(buffer_size_words,
2344 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2345 65536 : 32768));
2346 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2347 codec_dbg(codec,
01ef7dbf
IM		 2348 "chpadr=0x%08x frmsz=%u nchan=%u "
2349 "rate_mul=%u div=%u bufsz=%u\n",
2350 chip_addx, hda_frame_size_words, num_chans,
2351 sample_rate_mul, sample_rate_div, buffer_size_words);
2352
3bc085a1 2353 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2354 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2355 return -EINVAL;
2356 }
2357
2358 remainder_words = words_to_write % hda_frame_size_words;
2359 data_remainder = data;
2360 chip_addx_remainder = chip_addx;
2361
2362 data += remainder_words;
2363 chip_addx += remainder_words*sizeof(u32);
2364 words_to_write -= remainder_words;
2365
2366 while (words_to_write != 0) {
2367 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2368 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2369 words_to_write, run_size_words, remainder_words);
2370 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2371 if (!comm_dma_setup_done) {
2372 status = dsp_dma_stop(codec, dma_chan, ovly);
2373 if (status < 0)
425a7880 2374 return status;
01ef7dbf
IM		 2375 status = dsp_dma_setup_common(codec, chip_addx,
2376 dma_chan, port_map_mask, ovly);
2377 if (status < 0)
2378 return status;
2379 comm_dma_setup_done = true;
2380 }
2381
2382 status = dsp_dma_setup(codec, chip_addx,
2383 run_size_words, dma_chan);
2384 if (status < 0)
2385 return status;
2386 status = dsp_dma_start(codec, dma_chan, ovly);
2387 if (status < 0)
2388 return status;
2389 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2390 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2391 return -EIO;
2392 }
2393 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2394 if (status < 0)
2395 return status;
2396 if (remainder_words != 0) {
2397 status = chipio_write_multiple(codec,
2398 chip_addx_remainder,
2399 data_remainder,
2400 remainder_words);
b3667bd7
TI		 2401 if (status < 0)
2402 return status;
01ef7dbf
IM		 2403 remainder_words = 0;
2404 }
2405 if (hci_write) {
2406 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2407 if (status < 0)
2408 return status;
01ef7dbf
IM		 2409 hci_write = NULL;
2410 }
6d67530e
IM		 2411
2412 timeout = jiffies + msecs_to_jiffies(2000);
2413 do {
2414 dma_active = dsp_is_dma_active(codec, dma_chan);
2415 if (!dma_active)
01ef7dbf 2416 break;
6d67530e
IM		 2417 msleep(20);
2418 } while (time_before(jiffies, timeout));
2419 if (dma_active)
2420 break;
2421
4e76a883 2422 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2423 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2424 status = dma_reset(dma_engine);
01ef7dbf
IM		 2425
2426 if (status < 0)
2427 return status;
2428
2429 data += run_size_words;
2430 chip_addx += run_size_words*sizeof(u32);
2431 words_to_write -= run_size_words;
2432 }
2433
2434 if (remainder_words != 0) {
2435 status = chipio_write_multiple(codec, chip_addx_remainder,
2436 data_remainder, remainder_words);
2437 }
2438
2439 return status;
95c6e9cb
IM		 2440}
2441
d5c21b88
IM		 2442/**
2443 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2444 *
2445 * @codec: the HDA codec
2446 * @fls_data: pointer to a fast load image
2447 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2448 * no relocation
e97249dd 2449 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2450 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2451 * @ovly: TRUE if overlay format is required
2452 *
2453 * Returns zero or a negative error code.
2454 */
01ef7dbf
IM		 2455static int dspxfr_image(struct hda_codec *codec,
2456 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2457 unsigned int reloc,
2458 unsigned int sample_rate,
2459 unsigned short channels,
01ef7dbf 2460 bool ovly)
95c6e9cb
IM		 2461{
2462 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2463 int status;
2464 unsigned short hda_format = 0;
2465 unsigned int response;
2466 unsigned char stream_id = 0;
2467 struct dma_engine *dma_engine;
2468 unsigned int dma_chan;
2469 unsigned int port_map_mask;
2470
2471 if (fls_data == NULL)
2472 return -EINVAL;
2473
2474 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2475 if (!dma_engine)
2476 return -ENOMEM;
95c6e9cb 2477
01ef7dbf
IM		 2478 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2479 if (!dma_engine->dmab) {
549e8292
TI		 2480 kfree(dma_engine);
2481 return -ENOMEM;
01ef7dbf 2482 }
95c6e9cb 2483
01ef7dbf 2484 dma_engine->codec = codec;
6194b99d 2485 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 2486 dma_engine->m_converter_format = hda_format;
2487 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2488 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2489
8ae3124b 2490 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2491
2492 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2493 hda_format, &response);
2494
2495 if (status < 0) {
4e76a883 2496 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 2497 goto exit;
2498 }
2499
2500 status = snd_hda_codec_load_dsp_prepare(codec,
2501 dma_engine->m_converter_format,
2502 dma_engine->buf_size,
2503 dma_engine->dmab);
2504 if (status < 0)
95c6e9cb 2505 goto exit;
01ef7dbf
IM		 2506 spec->dsp_stream_id = status;
2507
2508 if (ovly) {
2509 status = dspio_alloc_dma_chan(codec, &dma_chan);
2510 if (status < 0) {
4e76a883 2511 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 2512 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 2513 goto exit;
2514 }
2515 }
95c6e9cb 2516
01ef7dbf
IM		 2517 port_map_mask = 0;
2518 status = dsp_allocate_ports_format(codec, hda_format,
2519 &port_map_mask);
2520 if (status < 0) {
4e76a883 2521 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 2522 goto exit;
2523 }
2524
2525 stream_id = dma_get_stream_id(dma_engine);
2526 status = codec_set_converter_stream_channel(codec,
2527 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2528 if (status < 0) {
4e76a883 2529 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 2530 goto exit;
2531 }
2532
2533 while ((fls_data != NULL) && !is_last(fls_data)) {
2534 if (!is_valid(fls_data)) {
4e76a883 2535 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 2536 status = -EINVAL;
2537 goto exit;
2538 }
2539 status = dspxfr_one_seg(codec, fls_data, reloc,
2540 dma_engine, dma_chan,
2541 port_map_mask, ovly);
2542 if (status < 0)
2543 break;
2544
2545 if (is_hci_prog_list_seg(fls_data))
2546 fls_data = get_next_seg_ptr(fls_data);
2547
2548 if ((fls_data != NULL) && !is_last(fls_data))
2549 fls_data = get_next_seg_ptr(fls_data);
2550 }
2551
2552 if (port_map_mask != 0)
2553 status = dsp_free_ports(codec);
2554
2555 if (status < 0)
95c6e9cb
IM		 2556 goto exit;
2557
01ef7dbf
IM		 2558 status = codec_set_converter_stream_channel(codec,
2559 WIDGET_CHIP_CTRL, 0, 0, &response);
2560
95c6e9cb 2561exit:
01ef7dbf
IM		 2562 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2563 dspio_free_dma_chan(codec, dma_chan);
2564
b3667bd7 2565 if (dma_engine->dmab->area)
01ef7dbf
IM		 2566 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2567 kfree(dma_engine->dmab);
2568 kfree(dma_engine);
2569
2570 return status;
95c6e9cb
IM		 2571}
2572
2573/*
01ef7dbf 2574 * CA0132 DSP download stuffs.
95c6e9cb 2575 */
01ef7dbf 2576static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2577{
4e76a883 2578 codec_dbg(codec, "---- dspload_post_setup ------\n");
95c6e9cb 2579
01ef7dbf
IM		 2580 /*set DSP speaker to 2.0 configuration*/
2581 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2582 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2583
01ef7dbf
IM		 2584 /*update write pointer*/
2585 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2586}
95c6e9cb 2587
d5c21b88 2588/**
e60b2c7f 2589 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 2590 *
2591 * @codec: the HDA codec
2592 * @fls: pointer to a fast load image
2593 * @ovly: TRUE if overlay format is required
2594 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2595 * no relocation
2596 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2597 * @router_chans: number of audio router channels to be allocated (0 means use
2598 * internal defaults; max is 32)
2599 *
e60b2c7f
TI		 2600 * Download DSP from a DSP Image Fast Load structure. This structure is a
2601 * linear, non-constant sized element array of structures, each of which
2602 * contain the count of the data to be loaded, the data itself, and the
2603 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 2604 * Returns zero or a negative error code.
2605 */
01ef7dbf
IM		 2606static int dspload_image(struct hda_codec *codec,
2607 const struct dsp_image_seg *fls,
2608 bool ovly,
2609 unsigned int reloc,
2610 bool autostart,
2611 int router_chans)
2612{
2613 int status = 0;
e97249dd
IM		 2614 unsigned int sample_rate;
2615 unsigned short channels;
01ef7dbf 2616
4e76a883 2617 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 2618 if (router_chans == 0) {
2619 if (!ovly)
2620 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2621 else
2622 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2623 }
95c6e9cb 2624
e97249dd
IM		 2625 sample_rate = 48000;
2626 channels = (unsigned short)router_chans;
01ef7dbf 2627
e97249dd
IM		 2628 while (channels > 16) {
2629 sample_rate *= 2;
2630 channels /= 2;
01ef7dbf
IM		 2631 }
2632
01ef7dbf 2633 do {
4e76a883 2634 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 2635 if (!ovly)
2636 status = dsp_reset(codec);
2637
2638 if (status < 0)
2639 break;
2640
4e76a883 2641 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 2642 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2643 ovly);
01ef7dbf
IM		 2644
2645 if (status < 0)
2646 break;
2647
4e76a883 2648 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 2649 if (autostart && !ovly) {
2650 dspload_post_setup(codec);
2651 status = dsp_set_run_state(codec);
2652 }
2653
4e76a883 2654 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 2655 } while (0);
2656
2657 return status;
2658}
2659
f664417e 2660#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 2661static bool dspload_is_loaded(struct hda_codec *codec)
2662{
2663 unsigned int data = 0;
2664 int status = 0;
2665
2666 status = chipio_read(codec, 0x40004, &data);
2667 if ((status < 0) || (data != 1))
2668 return false;
2669
2670 return true;
2671}
f664417e
TI		 2672#else
2673#define dspload_is_loaded(codec) false
2674#endif
01ef7dbf
IM		 2675
2676static bool dspload_wait_loaded(struct hda_codec *codec)
2677{
6d67530e 2678 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 2679
2680 do {
01ef7dbf 2681 if (dspload_is_loaded(codec)) {
d9684bb5 2682 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 2683 return true;
2684 }
6d67530e
IM		 2685 msleep(20);
2686 } while (time_before(jiffies, timeout));
01ef7dbf 2687
d9684bb5 2688 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 2689 return false;
95c6e9cb
IM		 2690}
2691
825315bc
IM		 2692/*
2693 * PCM callbacks
2694 */
95c6e9cb
IM		 2695static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2696 struct hda_codec *codec,
2697 unsigned int stream_tag,
2698 unsigned int format,
2699 struct snd_pcm_substream *substream)
2700{
2701 struct ca0132_spec *spec = codec->spec;
825315bc 2702
28fba950 2703 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 2704
2705 return 0;
95c6e9cb
IM		 2706}
2707
2708static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2709 struct hda_codec *codec,
2710 struct snd_pcm_substream *substream)
2711{
2712 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 2713
2714 if (spec->dsp_state == DSP_DOWNLOADING)
2715 return 0;
2716
2717 /*If Playback effects are on, allow stream some time to flush
2718 *effects tail*/
2719 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2720 msleep(50);
2721
28fba950 2722 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 2723
2724 return 0;
95c6e9cb
IM		 2725}
2726
e8412ca4
DR		 2727static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2728 struct hda_codec *codec,
2729 struct snd_pcm_substream *substream)
2730{
2731 struct ca0132_spec *spec = codec->spec;
2732 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2733 struct snd_pcm_runtime *runtime = substream->runtime;
2734
2735 if (spec->dsp_state != DSP_DOWNLOADED)
2736 return 0;
2737
2738 /* Add latency if playback enhancement and either effect is enabled. */
2739 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2740 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2741 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2742 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2743 }
2744
2745 /* Applying Speaker EQ adds latency as well. */
2746 if (spec->cur_out_type == SPEAKER_OUT)
2747 latency += DSP_SPEAKER_OUT_LATENCY;
2748
2749 return (latency * runtime->rate) / 1000;
2750}
2751
95c6e9cb
IM		 2752/*
2753 * Digital out
2754 */
27ebeb0b
TI		 2755static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2756 struct hda_codec *codec,
2757 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2758{
2759 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2760 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 2761}
2762
27ebeb0b 2763static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 2764 struct hda_codec *codec,
2765 unsigned int stream_tag,
2766 unsigned int format,
2767 struct snd_pcm_substream *substream)
2768{
2769 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 2770 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2771 stream_tag, format, substream);
95c6e9cb
IM		 2772}
2773
27ebeb0b 2774static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 2775 struct hda_codec *codec,
95c6e9cb
IM		 2776 struct snd_pcm_substream *substream)
2777{
2778 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2779 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 2780}
2781
27ebeb0b
TI		 2782static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2783 struct hda_codec *codec,
2784 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2785{
2786 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2787 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 2788}
2789
825315bc
IM		 2790/*
2791 * Analog capture
2792 */
2793static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2794 struct hda_codec *codec,
2795 unsigned int stream_tag,
2796 unsigned int format,
2797 struct snd_pcm_substream *substream)
2798{
13c12dbe 2799 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 2800 stream_tag, 0, format);
825315bc
IM		 2801
2802 return 0;
2803}
2804
2805static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2806 struct hda_codec *codec,
2807 struct snd_pcm_substream *substream)
2808{
2809 struct ca0132_spec *spec = codec->spec;
2810
2811 if (spec->dsp_state == DSP_DOWNLOADING)
2812 return 0;
2813
28fba950 2814 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 2815 return 0;
2816}
2817
e8412ca4
DR		 2818static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2819 struct hda_codec *codec,
2820 struct snd_pcm_substream *substream)
2821{
2822 struct ca0132_spec *spec = codec->spec;
2823 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2824 struct snd_pcm_runtime *runtime = substream->runtime;
2825
2826 if (spec->dsp_state != DSP_DOWNLOADED)
2827 return 0;
2828
2829 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2830 latency += DSP_CRYSTAL_VOICE_LATENCY;
2831
2832 return (latency * runtime->rate) / 1000;
2833}
2834
e90f29e4
IM		 2835/*
2836 * Controls stuffs.
2837 */
2838
2839/*
2840 * Mixer controls helpers.
2841 */
2842#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2843 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2844 .name = xname, \
2845 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2846 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2847 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2848 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2849 .info = ca0132_volume_info, \
2850 .get = ca0132_volume_get, \
2851 .put = ca0132_volume_put, \
2852 .tlv = { .c = ca0132_volume_tlv }, \
2853 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2854
2855#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2856 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2857 .name = xname, \
2858 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2859 .info = snd_hda_mixer_amp_switch_info, \
2860 .get = ca0132_switch_get, \
2861 .put = ca0132_switch_put, \
2862 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2863
2864/* stereo */
2865#define CA0132_CODEC_VOL(xname, nid, dir) \
2866 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2867#define CA0132_CODEC_MUTE(xname, nid, dir) \
2868 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2869
4091fb95 2870/* The following are for tuning of products */
44f0c978
IM		 2871#ifdef ENABLE_TUNING_CONTROLS
2872
2873static unsigned int voice_focus_vals_lookup[] = {
28740x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
28750x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
28760x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
28770x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
28780x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
28790x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
28800x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
28810x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
28820x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
28830x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
28840x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
28850x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
28860x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
28870x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
28880x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
28890x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
28900x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
28910x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
28920x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
28930x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
28940x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
28950x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
28960x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
28970x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
28980x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
28990x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
29000x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2901};
2902
2903static unsigned int mic_svm_vals_lookup[] = {
29040x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
29050x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
29060x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
29070x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
29080x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
29090x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
29100x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
29110x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
29120x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
29130x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
29140x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
29150x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
29160x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
29170x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
29180x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
29190x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
29200x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2921};
2922
2923static unsigned int equalizer_vals_lookup[] = {
29240xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
29250xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
29260xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
29270xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
29280x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
29290x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
29300x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
29310x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
29320x41C00000
2933};
2934
2935static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2936 unsigned int *lookup, int idx)
2937{
2938 int i = 0;
2939
2940 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2941 if (nid == ca0132_tuning_ctls[i].nid)
2942 break;
2943
2944 snd_hda_power_up(codec);
2945 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2946 ca0132_tuning_ctls[i].req,
2947 &(lookup[idx]), sizeof(unsigned int));
2948 snd_hda_power_down(codec);
2949
2950 return 1;
2951}
2952
2953static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2954 struct snd_ctl_elem_value *ucontrol)
2955{
2956 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2957 struct ca0132_spec *spec = codec->spec;
2958 hda_nid_t nid = get_amp_nid(kcontrol);
2959 long *valp = ucontrol->value.integer.value;
2960 int idx = nid - TUNING_CTL_START_NID;
2961
2962 *valp = spec->cur_ctl_vals[idx];
2963 return 0;
2964}
2965
2966static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2967 struct snd_ctl_elem_info *uinfo)
2968{
2969 int chs = get_amp_channels(kcontrol);
2970 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2971 uinfo->count = chs == 3 ? 2 : 1;
2972 uinfo->value.integer.min = 20;
2973 uinfo->value.integer.max = 180;
2974 uinfo->value.integer.step = 1;
2975
2976 return 0;
2977}
2978
2979static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2980 struct snd_ctl_elem_value *ucontrol)
2981{
2982 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2983 struct ca0132_spec *spec = codec->spec;
2984 hda_nid_t nid = get_amp_nid(kcontrol);
2985 long *valp = ucontrol->value.integer.value;
2986 int idx;
2987
2988 idx = nid - TUNING_CTL_START_NID;
2989 /* any change? */
2990 if (spec->cur_ctl_vals[idx] == *valp)
2991 return 0;
2992
2993 spec->cur_ctl_vals[idx] = *valp;
2994
2995 idx = *valp - 20;
2996 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2997
2998 return 1;
2999}
3000
3001static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3002 struct snd_ctl_elem_info *uinfo)
3003{
3004 int chs = get_amp_channels(kcontrol);
3005 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3006 uinfo->count = chs == 3 ? 2 : 1;
3007 uinfo->value.integer.min = 0;
3008 uinfo->value.integer.max = 100;
3009 uinfo->value.integer.step = 1;
3010
3011 return 0;
3012}
3013
3014static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3015 struct snd_ctl_elem_value *ucontrol)
3016{
3017 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3018 struct ca0132_spec *spec = codec->spec;
3019 hda_nid_t nid = get_amp_nid(kcontrol);
3020 long *valp = ucontrol->value.integer.value;
3021 int idx;
3022
3023 idx = nid - TUNING_CTL_START_NID;
3024 /* any change? */
3025 if (spec->cur_ctl_vals[idx] == *valp)
3026 return 0;
3027
3028 spec->cur_ctl_vals[idx] = *valp;
3029
3030 idx = *valp;
3031 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3032
3033 return 0;
3034}
3035
3036static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3037 struct snd_ctl_elem_info *uinfo)
3038{
3039 int chs = get_amp_channels(kcontrol);
3040 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3041 uinfo->count = chs == 3 ? 2 : 1;
3042 uinfo->value.integer.min = 0;
3043 uinfo->value.integer.max = 48;
3044 uinfo->value.integer.step = 1;
3045
3046 return 0;
3047}
3048
3049static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3050 struct snd_ctl_elem_value *ucontrol)
3051{
3052 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3053 struct ca0132_spec *spec = codec->spec;
3054 hda_nid_t nid = get_amp_nid(kcontrol);
3055 long *valp = ucontrol->value.integer.value;
3056 int idx;
3057
3058 idx = nid - TUNING_CTL_START_NID;
3059 /* any change? */
3060 if (spec->cur_ctl_vals[idx] == *valp)
3061 return 0;
3062
3063 spec->cur_ctl_vals[idx] = *valp;
3064
3065 idx = *valp;
3066 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3067
3068 return 1;
3069}
3070
3071static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3072static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3073
3074static int add_tuning_control(struct hda_codec *codec,
3075 hda_nid_t pnid, hda_nid_t nid,
3076 const char *name, int dir)
3077{
975cc02a 3078 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3079 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3080 struct snd_kcontrol_new knew =
3081 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3082
3083 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3084 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3085 knew.tlv.c = 0;
3086 knew.tlv.p = 0;
3087 switch (pnid) {
3088 case VOICE_FOCUS:
3089 knew.info = voice_focus_ctl_info;
3090 knew.get = tuning_ctl_get;
3091 knew.put = voice_focus_ctl_put;
3092 knew.tlv.p = voice_focus_db_scale;
3093 break;
3094 case MIC_SVM:
3095 knew.info = mic_svm_ctl_info;
3096 knew.get = tuning_ctl_get;
3097 knew.put = mic_svm_ctl_put;
3098 break;
3099 case EQUALIZER:
3100 knew.info = equalizer_ctl_info;
3101 knew.get = tuning_ctl_get;
3102 knew.put = equalizer_ctl_put;
3103 knew.tlv.p = eq_db_scale;
3104 break;
3105 default:
3106 return 0;
3107 }
3108 knew.private_value =
3109 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3110 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3111 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3112}
3113
3114static int add_tuning_ctls(struct hda_codec *codec)
3115{
3116 int i;
3117 int err;
3118
3119 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3120 err = add_tuning_control(codec,
3121 ca0132_tuning_ctls[i].parent_nid,
3122 ca0132_tuning_ctls[i].nid,
3123 ca0132_tuning_ctls[i].name,
3124 ca0132_tuning_ctls[i].direct);
3125 if (err < 0)
3126 return err;
3127 }
3128
3129 return 0;
3130}
3131
3132static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3133{
3134 struct ca0132_spec *spec = codec->spec;
3135 int i;
3136
3137 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3138 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3139 /* SVM level defaults to 0.74. */
3140 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3141
3142 /* EQ defaults to 0dB. */
3143 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3144 spec->cur_ctl_vals[i] = 24;
3145}
3146#endif /*ENABLE_TUNING_CONTROLS*/
3147
5aaca44d
IM		 3148/*
3149 * Select the active output.
3150 * If autodetect is enabled, output will be selected based on jack detection.
3151 * If jack inserted, headphone will be selected, else built-in speakers
3152 * If autodetect is disabled, output will be selected based on selection.
3153 */
3154static int ca0132_select_out(struct hda_codec *codec)
3155{
3156 struct ca0132_spec *spec = codec->spec;
3157 unsigned int pin_ctl;
3158 int jack_present;
3159 int auto_jack;
3160 unsigned int tmp;
3161 int err;
3162
4e76a883 3163 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 3164
664c7155 3165 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3166
3167 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3168
3169 if (auto_jack)
fe14f39e 3170 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 3171 else
3172 jack_present =
3173 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3174
3175 if (jack_present)
3176 spec->cur_out_type = HEADPHONE_OUT;
3177 else
3178 spec->cur_out_type = SPEAKER_OUT;
3179
3180 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 3181 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 3182 /*speaker out config*/
3183 tmp = FLOAT_ONE;
3184 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3185 if (err < 0)
3186 goto exit;
3187 /*enable speaker EQ*/
3188 tmp = FLOAT_ONE;
3189 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3190 if (err < 0)
3191 goto exit;
3192
3193 /* Setup EAPD */
3194 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3195 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3196 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3197 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3198 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3199 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3200 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3201 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3202
3203 /* disable headphone node */
3204 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3205 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3206 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3207 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3208 /* enable speaker node */
3209 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3210 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3211 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3212 pin_ctl | PIN_OUT);
5aaca44d 3213 } else {
4e76a883 3214 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 3215 /*headphone out config*/
3216 tmp = FLOAT_ZERO;
3217 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3218 if (err < 0)
3219 goto exit;
3220 /*disable speaker EQ*/
3221 tmp = FLOAT_ZERO;
3222 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3223 if (err < 0)
3224 goto exit;
3225
3226 /* Setup EAPD */
3227 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3228 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3229 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3230 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3231 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3232 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3233 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3234 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3235
3236 /* disable speaker*/
3237 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3238 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3239 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3240 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3241 /* enable headphone*/
3242 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3243 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3244 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3245 pin_ctl | PIN_HP);
5aaca44d
IM		 3246 }
3247
3248exit:
664c7155 3249 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3250
3251 return err < 0 ? err : 0;
3252}
3253
993884f6
CCC		 3254static void ca0132_unsol_hp_delayed(struct work_struct *work)
3255{
3256 struct ca0132_spec *spec = container_of(
3257 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 3258 struct hda_jack_tbl *jack;
3259
993884f6 3260 ca0132_select_out(spec->codec);
d5c016b5 3261 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 3262 if (jack) {
3263 jack->block_report = 0;
3264 snd_hda_jack_report_sync(spec->codec);
3265 }
993884f6
CCC		 3266}
3267
5aaca44d
IM		 3268static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3269static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3270static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3271
3272/*
3273 * Select the active VIP source
3274 */
3275static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3276{
3277 struct ca0132_spec *spec = codec->spec;
3278 unsigned int tmp;
3279
e8f1bd5d 3280 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 3281 return 0;
3282
3283 /* if CrystalVoice if off, vipsource should be 0 */
3284 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3285 (val == 0)) {
3286 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3287 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3288 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3289 if (spec->cur_mic_type == DIGITAL_MIC)
3290 tmp = FLOAT_TWO;
3291 else
3292 tmp = FLOAT_ONE;
3293 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3294 tmp = FLOAT_ZERO;
3295 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3296 } else {
3297 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3298 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3299 if (spec->cur_mic_type == DIGITAL_MIC)
3300 tmp = FLOAT_TWO;
3301 else
3302 tmp = FLOAT_ONE;
3303 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3304 tmp = FLOAT_ONE;
3305 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3306 msleep(20);
3307 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3308 }
3309
3310 return 1;
3311}
3312
3313/*
3314 * Select the active microphone.
3315 * If autodetect is enabled, mic will be selected based on jack detection.
3316 * If jack inserted, ext.mic will be selected, else built-in mic
3317 * If autodetect is disabled, mic will be selected based on selection.
3318 */
3319static int ca0132_select_mic(struct hda_codec *codec)
3320{
3321 struct ca0132_spec *spec = codec->spec;
3322 int jack_present;
3323 int auto_jack;
3324
4e76a883 3325 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 3326
664c7155 3327 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3328
3329 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3330
3331 if (auto_jack)
fe14f39e 3332 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 3333 else
3334 jack_present =
3335 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3336
3337 if (jack_present)
3338 spec->cur_mic_type = LINE_MIC_IN;
3339 else
3340 spec->cur_mic_type = DIGITAL_MIC;
3341
3342 if (spec->cur_mic_type == DIGITAL_MIC) {
3343 /* enable digital Mic */
3344 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3345 ca0132_set_dmic(codec, 1);
3346 ca0132_mic_boost_set(codec, 0);
3347 /* set voice focus */
3348 ca0132_effects_set(codec, VOICE_FOCUS,
3349 spec->effects_switch
3350 [VOICE_FOCUS - EFFECT_START_NID]);
3351 } else {
3352 /* disable digital Mic */
3353 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3354 ca0132_set_dmic(codec, 0);
3355 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3356 /* disable voice focus */
3357 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3358 }
3359
664c7155 3360 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3361
3362 return 0;
3363}
3364
a7e76271
IM		 3365/*
3366 * Check if VNODE settings take effect immediately.
3367 */
3368static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3369 hda_nid_t vnid,
3370 hda_nid_t *shared_nid)
3371{
3372 struct ca0132_spec *spec = codec->spec;
3373 hda_nid_t nid;
a7e76271
IM		 3374
3375 switch (vnid) {
3376 case VNID_SPK:
3377 nid = spec->shared_out_nid;
a7e76271
IM		 3378 break;
3379 case VNID_MIC:
3380 nid = spec->shared_mic_nid;
a7e76271
IM		 3381 break;
3382 default:
9a0869f4 3383 return false;
a7e76271
IM		 3384 }
3385
9a0869f4 3386 if (shared_nid)
a7e76271
IM		 3387 *shared_nid = nid;
3388
9a0869f4 3389 return true;
a7e76271
IM		 3390}
3391
3392/*
3393* The following functions are control change helpers.
3394* They return 0 if no changed. Return 1 if changed.
3395*/
3396static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3397{
3398 struct ca0132_spec *spec = codec->spec;
3399 unsigned int tmp;
3400
3401 /* based on CrystalVoice state to enable VoiceFX. */
3402 if (enable) {
3403 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3404 FLOAT_ONE : FLOAT_ZERO;
3405 } else {
3406 tmp = FLOAT_ZERO;
3407 }
3408
3409 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3410 ca0132_voicefx.reqs[0], tmp);
3411
3412 return 1;
3413}
3414
5aaca44d
IM		 3415/*
3416 * Set the effects parameters
3417 */
3418static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3419{
3420 struct ca0132_spec *spec = codec->spec;
3421 unsigned int on;
3422 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3423 int err = 0;
3424 int idx = nid - EFFECT_START_NID;
3425
3426 if ((idx < 0) || (idx >= num_fx))
3427 return 0; /* no changed */
3428
3429 /* for out effect, qualify with PE */
3430 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3431 /* if PE if off, turn off out effects. */
3432 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3433 val = 0;
3434 }
3435
3436 /* for in effect, qualify with CrystalVoice */
3437 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3438 /* if CrystalVoice if off, turn off in effects. */
3439 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3440 val = 0;
3441
3442 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3443 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3444 val = 0;
3445 }
3446
4e76a883 3447 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 3448 nid, val);
3449
3450 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3451 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3452 ca0132_effects[idx].reqs[0], on);
3453
3454 if (err < 0)
3455 return 0; /* no changed */
3456
3457 return 1;
3458}
3459
a7e76271
IM		 3460/*
3461 * Turn on/off Playback Enhancements
3462 */
3463static int ca0132_pe_switch_set(struct hda_codec *codec)
3464{
3465 struct ca0132_spec *spec = codec->spec;
3466 hda_nid_t nid;
3467 int i, ret = 0;
3468
4e76a883 3469 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 3470 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3471
3472 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3473 nid = OUT_EFFECT_START_NID;
3474 /* PE affects all out effects */
3475 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3476 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3477
3478 return ret;
3479}
3480
5aaca44d
IM		 3481/* Check if Mic1 is streaming, if so, stop streaming */
3482static int stop_mic1(struct hda_codec *codec)
3483{
3484 struct ca0132_spec *spec = codec->spec;
3485 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3486 AC_VERB_GET_CONV, 0);
3487 if (oldval != 0)
3488 snd_hda_codec_write(codec, spec->adcs[0], 0,
3489 AC_VERB_SET_CHANNEL_STREAMID,
3490 0);
3491 return oldval;
3492}
3493
3494/* Resume Mic1 streaming if it was stopped. */
3495static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3496{
3497 struct ca0132_spec *spec = codec->spec;
3498 /* Restore the previous stream and channel */
3499 if (oldval != 0)
3500 snd_hda_codec_write(codec, spec->adcs[0], 0,
3501 AC_VERB_SET_CHANNEL_STREAMID,
3502 oldval);
3503}
3504
3505/*
a7e76271 3506 * Turn on/off CrystalVoice
5aaca44d 3507 */
a7e76271
IM		 3508static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3509{
3510 struct ca0132_spec *spec = codec->spec;
3511 hda_nid_t nid;
3512 int i, ret = 0;
3513 unsigned int oldval;
3514
4e76a883 3515 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 3516 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3517
3518 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3519 nid = IN_EFFECT_START_NID;
3520 /* CrystalVoice affects all in effects */
3521 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3522 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3523
3524 /* including VoiceFX */
3525 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3526
3527 /* set correct vipsource */
3528 oldval = stop_mic1(codec);
3529 ret |= ca0132_set_vipsource(codec, 1);
3530 resume_mic1(codec, oldval);
3531 return ret;
3532}
3533
5aaca44d
IM		 3534static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3535{
3536 struct ca0132_spec *spec = codec->spec;
3537 int ret = 0;
3538
3539 if (val) /* on */
3540 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3541 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3542 else /* off */
3543 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3544 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3545
3546 return ret;
3547}
3548
a7e76271
IM		 3549static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3550 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 3551{
a7e76271
IM		 3552 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3553 hda_nid_t nid = get_amp_nid(kcontrol);
3554 hda_nid_t shared_nid = 0;
3555 bool effective;
3556 int ret = 0;
95c6e9cb 3557 struct ca0132_spec *spec = codec->spec;
a7e76271 3558 int auto_jack;
95c6e9cb 3559
a7e76271
IM		 3560 if (nid == VNID_HP_SEL) {
3561 auto_jack =
3562 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3563 if (!auto_jack)
3564 ca0132_select_out(codec);
3565 return 1;
3566 }
95c6e9cb 3567
a7e76271
IM		 3568 if (nid == VNID_AMIC1_SEL) {
3569 auto_jack =
3570 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3571 if (!auto_jack)
3572 ca0132_select_mic(codec);
3573 return 1;
3574 }
95c6e9cb 3575
a7e76271
IM		 3576 if (nid == VNID_HP_ASEL) {
3577 ca0132_select_out(codec);
3578 return 1;
3579 }
95c6e9cb 3580
a7e76271
IM		 3581 if (nid == VNID_AMIC1_ASEL) {
3582 ca0132_select_mic(codec);
3583 return 1;
95c6e9cb 3584 }
a7e76271
IM		 3585
3586 /* if effective conditions, then update hw immediately. */
3587 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3588 if (effective) {
3589 int dir = get_amp_direction(kcontrol);
3590 int ch = get_amp_channels(kcontrol);
3591 unsigned long pval;
3592
3593 mutex_lock(&codec->control_mutex);
3594 pval = kcontrol->private_value;
3595 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3596 0, dir);
3597 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3598 kcontrol->private_value = pval;
3599 mutex_unlock(&codec->control_mutex);
95c6e9cb 3600 }
95c6e9cb 3601
a7e76271 3602 return ret;
95c6e9cb 3603}
a7e76271 3604/* End of control change helpers. */
95c6e9cb 3605
a7e76271
IM		 3606static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3607 struct snd_ctl_elem_info *uinfo)
3608{
a9291f46 3609 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 3610
3611 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3612 uinfo->count = 1;
3613 uinfo->value.enumerated.items = items;
3614 if (uinfo->value.enumerated.item >= items)
3615 uinfo->value.enumerated.item = items - 1;
3616 strcpy(uinfo->value.enumerated.name,
3617 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3618 return 0;
3619}
95c6e9cb 3620
a7e76271 3621static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3622 struct snd_ctl_elem_value *ucontrol)
3623{
3624 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3625 struct ca0132_spec *spec = codec->spec;
95c6e9cb 3626
a7e76271 3627 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 3628 return 0;
3629}
3630
a7e76271 3631static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3632 struct snd_ctl_elem_value *ucontrol)
3633{
3634 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3635 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3636 int i, err = 0;
3637 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 3638
a9291f46 3639 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 3640 return 0;
3641
4e76a883 3642 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 3643 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 3644
a7e76271
IM		 3645 /*
3646 * Idx 0 is default.
3647 * Default needs to qualify with CrystalVoice state.
3648 */
3649 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3650 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3651 ca0132_voicefx.reqs[i],
3652 ca0132_voicefx_presets[sel].vals[i]);
3653 if (err < 0)
3654 break;
3655 }
95c6e9cb 3656
a7e76271
IM		 3657 if (err >= 0) {
3658 spec->voicefx_val = sel;
3659 /* enable voice fx */
3660 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3661 }
95c6e9cb 3662
a7e76271 3663 return 1;
95c6e9cb
IM		 3664}
3665
a7e76271
IM		 3666static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3667 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3668{
3669 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3670 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3671 hda_nid_t nid = get_amp_nid(kcontrol);
3672 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3673 long *valp = ucontrol->value.integer.value;
3674
a7e76271
IM		 3675 /* vnode */
3676 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3677 if (ch & 1) {
3678 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3679 valp++;
3680 }
3681 if (ch & 2) {
3682 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3683 valp++;
3684 }
3685 return 0;
3686 }
3687
3688 /* effects, include PE and CrystalVoice */
3689 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3690 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3691 return 0;
3692 }
3693
3694 /* mic boost */
3695 if (nid == spec->input_pins[0]) {
3696 *valp = spec->cur_mic_boost;
3697 return 0;
3698 }
3699
95c6e9cb
IM		 3700 return 0;
3701}
3702
a7e76271
IM		 3703static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3704 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3705{
3706 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3707 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3708 hda_nid_t nid = get_amp_nid(kcontrol);
3709 int ch = get_amp_channels(kcontrol);
95c6e9cb 3710 long *valp = ucontrol->value.integer.value;
a7e76271 3711 int changed = 1;
95c6e9cb 3712
4e76a883 3713 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 3714 nid, *valp);
95c6e9cb
IM		 3715
3716 snd_hda_power_up(codec);
a7e76271
IM		 3717 /* vnode */
3718 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3719 if (ch & 1) {
3720 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3721 valp++;
3722 }
3723 if (ch & 2) {
3724 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3725 valp++;
3726 }
3727 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3728 goto exit;
3729 }
95c6e9cb 3730
a7e76271
IM		 3731 /* PE */
3732 if (nid == PLAY_ENHANCEMENT) {
3733 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3734 changed = ca0132_pe_switch_set(codec);
b97f6bfd 3735 goto exit;
a7e76271 3736 }
95c6e9cb 3737
a7e76271
IM		 3738 /* CrystalVoice */
3739 if (nid == CRYSTAL_VOICE) {
3740 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3741 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 3742 goto exit;
a7e76271 3743 }
95c6e9cb 3744
a7e76271
IM		 3745 /* out and in effects */
3746 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3747 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3748 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3749 changed = ca0132_effects_set(codec, nid, *valp);
3750 goto exit;
3751 }
3752
3753 /* mic boost */
3754 if (nid == spec->input_pins[0]) {
3755 spec->cur_mic_boost = *valp;
3756
3757 /* Mic boost does not apply to Digital Mic */
3758 if (spec->cur_mic_type != DIGITAL_MIC)
3759 changed = ca0132_mic_boost_set(codec, *valp);
3760 goto exit;
3761 }
95c6e9cb 3762
a7e76271 3763exit:
95c6e9cb 3764 snd_hda_power_down(codec);
a7e76271 3765 return changed;
95c6e9cb
IM		 3766}
3767
a7e76271
IM		 3768/*
3769 * Volume related
3770 */
3771static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3772 struct snd_ctl_elem_info *uinfo)
3773{
3774 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3775 struct ca0132_spec *spec = codec->spec;
3776 hda_nid_t nid = get_amp_nid(kcontrol);
3777 int ch = get_amp_channels(kcontrol);
3778 int dir = get_amp_direction(kcontrol);
3779 unsigned long pval;
3780 int err;
3781
3782 switch (nid) {
3783 case VNID_SPK:
3784 /* follow shared_out info */
3785 nid = spec->shared_out_nid;
3786 mutex_lock(&codec->control_mutex);
3787 pval = kcontrol->private_value;
3788 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3789 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3790 kcontrol->private_value = pval;
3791 mutex_unlock(&codec->control_mutex);
3792 break;
3793 case VNID_MIC:
3794 /* follow shared_mic info */
3795 nid = spec->shared_mic_nid;
3796 mutex_lock(&codec->control_mutex);
3797 pval = kcontrol->private_value;
3798 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3799 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3800 kcontrol->private_value = pval;
3801 mutex_unlock(&codec->control_mutex);
3802 break;
3803 default:
3804 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3805 }
3806 return err;
3807}
3808
3809static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3810 struct snd_ctl_elem_value *ucontrol)
3811{
3812 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3813 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3814 hda_nid_t nid = get_amp_nid(kcontrol);
3815 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3816 long *valp = ucontrol->value.integer.value;
3817
a7e76271
IM		 3818 /* store the left and right volume */
3819 if (ch & 1) {
3820 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3821 valp++;
3822 }
3823 if (ch & 2) {
3824 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3825 valp++;
3826 }
95c6e9cb
IM		 3827 return 0;
3828}
3829
a7e76271 3830static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3831 struct snd_ctl_elem_value *ucontrol)
3832{
3833 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3834 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3835 hda_nid_t nid = get_amp_nid(kcontrol);
3836 int ch = get_amp_channels(kcontrol);
95c6e9cb 3837 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 3838 hda_nid_t shared_nid = 0;
3839 bool effective;
3840 int changed = 1;
3841
3842 /* store the left and right volume */
3843 if (ch & 1) {
3844 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3845 valp++;
3846 }
3847 if (ch & 2) {
3848 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3849 valp++;
3850 }
95c6e9cb 3851
a7e76271
IM		 3852 /* if effective conditions, then update hw immediately. */
3853 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3854 if (effective) {
3855 int dir = get_amp_direction(kcontrol);
3856 unsigned long pval;
3857
3858 snd_hda_power_up(codec);
3859 mutex_lock(&codec->control_mutex);
3860 pval = kcontrol->private_value;
3861 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3862 0, dir);
3863 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3864 kcontrol->private_value = pval;
3865 mutex_unlock(&codec->control_mutex);
3866 snd_hda_power_down(codec);
3867 }
95c6e9cb 3868
a7e76271 3869 return changed;
95c6e9cb
IM		 3870}
3871
a7e76271
IM		 3872static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3873 unsigned int size, unsigned int __user *tlv)
95c6e9cb 3874{
a7e76271
IM		 3875 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3876 struct ca0132_spec *spec = codec->spec;
3877 hda_nid_t nid = get_amp_nid(kcontrol);
3878 int ch = get_amp_channels(kcontrol);
3879 int dir = get_amp_direction(kcontrol);
3880 unsigned long pval;
3881 int err;
3882
3883 switch (nid) {
3884 case VNID_SPK:
3885 /* follow shared_out tlv */
3886 nid = spec->shared_out_nid;
3887 mutex_lock(&codec->control_mutex);
3888 pval = kcontrol->private_value;
3889 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3890 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3891 kcontrol->private_value = pval;
3892 mutex_unlock(&codec->control_mutex);
3893 break;
3894 case VNID_MIC:
3895 /* follow shared_mic tlv */
3896 nid = spec->shared_mic_nid;
3897 mutex_lock(&codec->control_mutex);
3898 pval = kcontrol->private_value;
3899 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3900 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3901 kcontrol->private_value = pval;
3902 mutex_unlock(&codec->control_mutex);
3903 break;
3904 default:
3905 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3906 }
3907 return err;
95c6e9cb
IM		 3908}
3909
a7e76271
IM		 3910static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3911 const char *pfx, int dir)
95c6e9cb 3912{
975cc02a 3913 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 3914 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 3915 struct snd_kcontrol_new knew =
a7e76271
IM		 3916 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3917 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
95c6e9cb
IM		 3918 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3919}
3920
a7e76271 3921static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 3922{
3923 struct snd_kcontrol_new knew =
a7e76271
IM		 3924 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3925 VOICEFX, 1, 0, HDA_INPUT);
3926 knew.info = ca0132_voicefx_info;
3927 knew.get = ca0132_voicefx_get;
3928 knew.put = ca0132_voicefx_put;
3929 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 3930}
3931
a7e76271
IM		 3932/*
3933 * When changing Node IDs for Mixer Controls below, make sure to update
3934 * Node IDs in ca0132_config() as well.
3935 */
3936static struct snd_kcontrol_new ca0132_mixer[] = {
3937 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3938 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3939 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3940 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3941 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3942 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3943 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3944 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3945 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3946 0x12, 1, HDA_INPUT),
3947 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3948 VNID_HP_SEL, 1, HDA_OUTPUT),
3949 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3950 VNID_AMIC1_SEL, 1, HDA_INPUT),
3951 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3952 VNID_HP_ASEL, 1, HDA_OUTPUT),
3953 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3954 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3955 { } /* end */
3956};
3957
e90f29e4
IM		 3958static int ca0132_build_controls(struct hda_codec *codec)
3959{
3960 struct ca0132_spec *spec = codec->spec;
3961 int i, num_fx;
3962 int err = 0;
3963
3964 /* Add Mixer controls */
3965 for (i = 0; i < spec->num_mixers; i++) {
3966 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3967 if (err < 0)
3968 return err;
3969 }
3970
3971 /* Add in and out effects controls.
3972 * VoiceFX, PE and CrystalVoice are added separately.
3973 */
3974 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3975 for (i = 0; i < num_fx; i++) {
3976 err = add_fx_switch(codec, ca0132_effects[i].nid,
3977 ca0132_effects[i].name,
3978 ca0132_effects[i].direct);
3979 if (err < 0)
3980 return err;
3981 }
3982
3983 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3984 if (err < 0)
3985 return err;
3986
3987 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3988 if (err < 0)
3989 return err;
3990
3991 add_voicefx(codec);
3992
3993#ifdef ENABLE_TUNING_CONTROLS
3994 add_tuning_ctls(codec);
3995#endif
3996
3997 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3998 if (err < 0)
3999 return err;
4000
4001 if (spec->dig_out) {
4002 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
4003 spec->dig_out);
4004 if (err < 0)
4005 return err;
4006 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
4007 if (err < 0)
4008 return err;
4009 /* spec->multiout.share_spdif = 1; */
4010 }
4011
4012 if (spec->dig_in) {
4013 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
4014 if (err < 0)
4015 return err;
4016 }
4017 return 0;
4018}
4019
a7e76271 4020/*
e90f29e4 4021 * PCM
a7e76271 4022 */
071f1344 4023static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 4024 .substreams = 1,
4025 .channels_min = 2,
825315bc 4026 .channels_max = 6,
a7e76271 4027 .ops = {
a7e76271 4028 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 4029 .cleanup = ca0132_playback_pcm_cleanup,
4030 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 4031 },
4032};
4033
071f1344 4034static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 4035 .substreams = 1,
4036 .channels_min = 2,
4037 .channels_max = 2,
825315bc
IM		 4038 .ops = {
4039 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 4040 .cleanup = ca0132_capture_pcm_cleanup,
4041 .get_delay = ca0132_capture_pcm_delay,
825315bc 4042 },
a7e76271
IM		 4043};
4044
071f1344 4045static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 4046 .substreams = 1,
4047 .channels_min = 2,
4048 .channels_max = 2,
4049 .ops = {
4050 .open = ca0132_dig_playback_pcm_open,
4051 .close = ca0132_dig_playback_pcm_close,
4052 .prepare = ca0132_dig_playback_pcm_prepare,
4053 .cleanup = ca0132_dig_playback_pcm_cleanup
4054 },
4055};
4056
071f1344 4057static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 4058 .substreams = 1,
4059 .channels_min = 2,
4060 .channels_max = 2,
4061};
4062
4063static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 4064{
4065 struct ca0132_spec *spec = codec->spec;
bbbc7e85 4066 struct hda_pcm *info;
a7e76271 4067
bbbc7e85
TI		 4068 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
4069 if (!info)
4070 return -ENOMEM;
a7e76271
IM		 4071 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4072 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4073 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4074 spec->multiout.max_channels;
4075 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 4076 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 4077 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 4078
bbbc7e85
TI		 4079 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
4080 if (!info)
4081 return -ENOMEM;
825315bc
IM		 4082 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4083 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4084 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
825315bc 4085
bbbc7e85
TI		 4086 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
4087 if (!info)
4088 return -ENOMEM;
825315bc
IM		 4089 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4090 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4091 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 4092
a7e76271
IM		 4093 if (!spec->dig_out && !spec->dig_in)
4094 return 0;
4095
bbbc7e85
TI		 4096 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
4097 if (!info)
4098 return -ENOMEM;
a7e76271
IM		 4099 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4100 if (spec->dig_out) {
4101 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4102 ca0132_pcm_digital_playback;
4103 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4104 }
4105 if (spec->dig_in) {
4106 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4107 ca0132_pcm_digital_capture;
4108 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4109 }
95c6e9cb 4110
a7e76271 4111 return 0;
95c6e9cb
IM		 4112}
4113
441aa6a0
IM		 4114static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4115{
4116 if (pin) {
a0c041cb 4117 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 4118 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4119 snd_hda_codec_write(codec, pin, 0,
4120 AC_VERB_SET_AMP_GAIN_MUTE,
4121 AMP_OUT_UNMUTE);
4122 }
4123 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4124 snd_hda_codec_write(codec, dac, 0,
4125 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4126}
4127
4128static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4129{
4130 if (pin) {
a0c041cb 4131 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 4132 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4133 snd_hda_codec_write(codec, pin, 0,
4134 AC_VERB_SET_AMP_GAIN_MUTE,
4135 AMP_IN_UNMUTE(0));
4136 }
4137 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4138 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4139 AMP_IN_UNMUTE(0));
4140
4141 /* init to 0 dB and unmute. */
4142 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4143 HDA_AMP_VOLMASK, 0x5a);
4144 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4145 HDA_AMP_MUTE, 0);
4146 }
4147}
4148
5aaca44d
IM		 4149static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4150{
4151 unsigned int caps;
4152
4153 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4154 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4155 snd_hda_override_amp_caps(codec, nid, dir, caps);
4156}
4157
4158/*
4159 * Switch between Digital built-in mic and analog mic.
4160 */
4161static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4162{
4163 struct ca0132_spec *spec = codec->spec;
4164 unsigned int tmp;
4165 u8 val;
4166 unsigned int oldval;
4167
4e76a883 4168 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 4169
4170 oldval = stop_mic1(codec);
4171 ca0132_set_vipsource(codec, 0);
4172 if (enable) {
4173 /* set DMic input as 2-ch */
4174 tmp = FLOAT_TWO;
4175 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4176
4177 val = spec->dmic_ctl;
4178 val |= 0x80;
4179 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4180 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4181
4182 if (!(spec->dmic_ctl & 0x20))
4183 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4184 } else {
4185 /* set AMic input as mono */
4186 tmp = FLOAT_ONE;
4187 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4188
4189 val = spec->dmic_ctl;
4190 /* clear bit7 and bit5 to disable dmic */
4191 val &= 0x5f;
4192 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4193 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4194
4195 if (!(spec->dmic_ctl & 0x20))
4196 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4197 }
4198 ca0132_set_vipsource(codec, 1);
4199 resume_mic1(codec, oldval);
4200}
4201
4202/*
4203 * Initialization for Digital Mic.
4204 */
4205static void ca0132_init_dmic(struct hda_codec *codec)
4206{
4207 struct ca0132_spec *spec = codec->spec;
4208 u8 val;
4209
4210 /* Setup Digital Mic here, but don't enable.
4211 * Enable based on jack detect.
4212 */
4213
4214 /* MCLK uses MPIO1, set to enable.
4215 * Bit 2-0: MPIO select
4216 * Bit 3: set to disable
4217 * Bit 7-4: reserved
4218 */
4219 val = 0x01;
4220 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4221 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4222
4223 /* Data1 uses MPIO3. Data2 not use
4224 * Bit 2-0: Data1 MPIO select
4225 * Bit 3: set disable Data1
4226 * Bit 6-4: Data2 MPIO select
4227 * Bit 7: set disable Data2
4228 */
4229 val = 0x83;
4230 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4231 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4232
4233 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4234 * Bit 3-0: Channel mask
4235 * Bit 4: set for 48KHz, clear for 32KHz
4236 * Bit 5: mode
4237 * Bit 6: set to select Data2, clear for Data1
4238 * Bit 7: set to enable DMic, clear for AMic
4239 */
4240 val = 0x23;
4241 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4242 spec->dmic_ctl = val;
4243 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4244 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4245}
4246
4247/*
4248 * Initialization for Analog Mic 2
4249 */
4250static void ca0132_init_analog_mic2(struct hda_codec *codec)
4251{
4252 struct ca0132_spec *spec = codec->spec;
4253
4254 mutex_lock(&spec->chipio_mutex);
4255 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4256 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4257 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4258 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4259 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4260 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4261 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4262 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4263 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4264 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4265 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4266 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4267 mutex_unlock(&spec->chipio_mutex);
4268}
4269
4270static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4271{
4272 struct ca0132_spec *spec = codec->spec;
4273 int i;
5aaca44d 4274
4e76a883 4275 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 4276 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 4277
4278 for (i = 0; i < spec->multiout.num_dacs; i++)
4279 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4280
4281 for (i = 0; i < spec->num_outputs; i++)
4282 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4283
4284 for (i = 0; i < spec->num_inputs; i++) {
4285 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4286 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4287 }
4288}
4289
4290/*
4291 * Setup default parameters for DSP
4292 */
4293static void ca0132_setup_defaults(struct hda_codec *codec)
4294{
e8f1bd5d 4295 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4296 unsigned int tmp;
4297 int num_fx;
4298 int idx, i;
4299
e8f1bd5d 4300 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4301 return;
4302
4303 /* out, in effects + voicefx */
4304 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4305 for (idx = 0; idx < num_fx; idx++) {
4306 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4307 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4308 ca0132_effects[idx].reqs[i],
4309 ca0132_effects[idx].def_vals[i]);
4310 }
4311 }
4312
4313 /*remove DSP headroom*/
4314 tmp = FLOAT_ZERO;
4315 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4316
4317 /*set speaker EQ bypass attenuation*/
4318 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4319
4320 /* set AMic1 and AMic2 as mono mic */
4321 tmp = FLOAT_ONE;
4322 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4323 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4324
4325 /* set AMic1 as CrystalVoice input */
4326 tmp = FLOAT_ONE;
4327 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4328
4329 /* set WUH source */
4330 tmp = FLOAT_TWO;
4331 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4332}
4333
4334/*
4335 * Initialization of flags in chip
4336 */
4337static void ca0132_init_flags(struct hda_codec *codec)
4338{
4339 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4340 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4341 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4342 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4343 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4344 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4345}
4346
4347/*
4348 * Initialization of parameters in chip
4349 */
4350static void ca0132_init_params(struct hda_codec *codec)
4351{
4352 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4353 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4354}
95c6e9cb 4355
e90f29e4
IM		 4356static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4357{
4358 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4359 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4360 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4361 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4362 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4363 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4364
406261ce
IM		 4365 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4366 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 4367 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4368}
4369
4370static bool ca0132_download_dsp_images(struct hda_codec *codec)
4371{
4372 bool dsp_loaded = false;
4373 const struct dsp_image_seg *dsp_os_image;
15e4ba66 4374 const struct firmware *fw_entry;
e90f29e4 4375
6efdd851 4376 if (request_firmware(&fw_entry, EFX_FILE, codec->card->dev) != 0)
e90f29e4
IM		 4377 return false;
4378
15e4ba66 4379 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 4380 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 4381 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 4382 goto exit_download;
4383 }
4384
e90f29e4
IM		 4385 dsp_loaded = dspload_wait_loaded(codec);
4386
d1d28500 4387exit_download:
15e4ba66
TI		 4388 release_firmware(fw_entry);
4389
e90f29e4
IM		 4390 return dsp_loaded;
4391}
4392
4393static void ca0132_download_dsp(struct hda_codec *codec)
4394{
4395 struct ca0132_spec *spec = codec->spec;
4396
9a0869f4
TI		 4397#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4398 return; /* NOP */
4399#endif
e90f29e4 4400
e24aa0a4
TI		 4401 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
4402 return; /* don't retry failures */
4403
b714a710
DR		 4404 chipio_enable_clocks(codec);
4405 spec->dsp_state = DSP_DOWNLOADING;
4406 if (!ca0132_download_dsp_images(codec))
4407 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4408 else
4409 spec->dsp_state = DSP_DOWNLOADED;
e90f29e4
IM		 4410
4411 if (spec->dsp_state == DSP_DOWNLOADED)
4412 ca0132_set_dsp_msr(codec, true);
4413}
4414
f8fb1170
TI		 4415static void ca0132_process_dsp_response(struct hda_codec *codec,
4416 struct hda_jack_callback *callback)
e90f29e4
IM		 4417{
4418 struct ca0132_spec *spec = codec->spec;
4419
4e76a883 4420 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 4421 if (spec->wait_scp) {
4422 if (dspio_get_response_data(codec) >= 0)
4423 spec->wait_scp = 0;
4424 }
4425
4426 dspio_clear_response_queue(codec);
4427}
4428
f8fb1170 4429static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 4430{
993884f6 4431 struct ca0132_spec *spec = codec->spec;
2ebab40e 4432 struct hda_jack_tbl *tbl;
e90f29e4 4433
f8fb1170
TI		 4434 /* Delay enabling the HP amp, to let the mic-detection
4435 * state machine run.
4436 */
4437 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 4438 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 4439 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
4440 if (tbl)
4441 tbl->block_report = 1;
f8fb1170
TI		 4442}
4443
4444static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4445{
4446 ca0132_select_mic(codec);
4447}
4448
4449static void ca0132_init_unsol(struct hda_codec *codec)
4450{
d5c016b5
GM		 4451 struct ca0132_spec *spec = codec->spec;
4452 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
4453 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 4454 amic_callback);
4455 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
4456 ca0132_process_dsp_response);
e90f29e4
IM		 4457}
4458
5aaca44d
IM		 4459/*
4460 * Verbs tables.
4461 */
4462
4463/* Sends before DSP download. */
4464static struct hda_verb ca0132_base_init_verbs[] = {
4465 /*enable ct extension*/
4466 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 4467 {}
4468};
4469
4470/* Send at exit. */
4471static struct hda_verb ca0132_base_exit_verbs[] = {
4472 /*set afg to D3*/
4473 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4474 /*disable ct extension*/
4475 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4476 {}
4477};
4478
4479/* Other verbs tables. Sends after DSP download. */
4480static struct hda_verb ca0132_init_verbs0[] = {
4481 /* chip init verbs */
4482 {0x15, 0x70D, 0xF0},
4483 {0x15, 0x70E, 0xFE},
4484 {0x15, 0x707, 0x75},
4485 {0x15, 0x707, 0xD3},
4486 {0x15, 0x707, 0x09},
4487 {0x15, 0x707, 0x53},
4488 {0x15, 0x707, 0xD4},
4489 {0x15, 0x707, 0xEF},
4490 {0x15, 0x707, 0x75},
4491 {0x15, 0x707, 0xD3},
4492 {0x15, 0x707, 0x09},
4493 {0x15, 0x707, 0x02},
4494 {0x15, 0x707, 0x37},
4495 {0x15, 0x707, 0x78},
4496 {0x15, 0x53C, 0xCE},
4497 {0x15, 0x575, 0xC9},
4498 {0x15, 0x53D, 0xCE},
4499 {0x15, 0x5B7, 0xC9},
4500 {0x15, 0x70D, 0xE8},
4501 {0x15, 0x70E, 0xFE},
4502 {0x15, 0x707, 0x02},
4503 {0x15, 0x707, 0x68},
4504 {0x15, 0x707, 0x62},
4505 {0x15, 0x53A, 0xCE},
4506 {0x15, 0x546, 0xC9},
4507 {0x15, 0x53B, 0xCE},
4508 {0x15, 0x5E8, 0xC9},
4509 {0x15, 0x717, 0x0D},
4510 {0x15, 0x718, 0x20},
4511 {}
4512};
4513
95c6e9cb
IM		 4514static void ca0132_init_chip(struct hda_codec *codec)
4515{
4516 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4517 int num_fx;
4518 int i;
4519 unsigned int on;
95c6e9cb
IM		 4520
4521 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 4522
4523 spec->cur_out_type = SPEAKER_OUT;
4524 spec->cur_mic_type = DIGITAL_MIC;
4525 spec->cur_mic_boost = 0;
4526
4527 for (i = 0; i < VNODES_COUNT; i++) {
4528 spec->vnode_lvol[i] = 0x5a;
4529 spec->vnode_rvol[i] = 0x5a;
4530 spec->vnode_lswitch[i] = 0;
4531 spec->vnode_rswitch[i] = 0;
4532 }
4533
4534 /*
4535 * Default states for effects are in ca0132_effects[].
4536 */
4537 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4538 for (i = 0; i < num_fx; i++) {
4539 on = (unsigned int)ca0132_effects[i].reqs[0];
4540 spec->effects_switch[i] = on ? 1 : 0;
4541 }
4542
4543 spec->voicefx_val = 0;
4544 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4545 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4546
44f0c978
IM		 4547#ifdef ENABLE_TUNING_CONTROLS
4548 ca0132_init_tuning_defaults(codec);
4549#endif
95c6e9cb
IM		 4550}
4551
4552static void ca0132_exit_chip(struct hda_codec *codec)
4553{
4554 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 4555
4556 if (dspload_is_loaded(codec))
4557 dsp_reset(codec);
95c6e9cb
IM		 4558}
4559
4560static int ca0132_init(struct hda_codec *codec)
4561{
4562 struct ca0132_spec *spec = codec->spec;
4563 struct auto_pin_cfg *cfg = &spec->autocfg;
4564 int i;
4565
e24aa0a4
TI		 4566 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
4567 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 4568 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 4569
664c7155 4570 snd_hda_power_up_pm(codec);
5aaca44d 4571
f8fb1170
TI		 4572 ca0132_init_unsol(codec);
4573
5aaca44d
IM		 4574 ca0132_init_params(codec);
4575 ca0132_init_flags(codec);
4576 snd_hda_sequence_write(codec, spec->base_init_verbs);
01ef7dbf 4577 ca0132_download_dsp(codec);
5aaca44d
IM		 4578 ca0132_refresh_widget_caps(codec);
4579 ca0132_setup_defaults(codec);
4580 ca0132_init_analog_mic2(codec);
4581 ca0132_init_dmic(codec);
4582
4583 for (i = 0; i < spec->num_outputs; i++)
4584 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 4585
95c6e9cb
IM		 4586 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4587
4588 for (i = 0; i < spec->num_inputs; i++)
4589 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4590
4591 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4592
d5c016b5
GM		 4593 snd_hda_sequence_write(codec, spec->chip_init_verbs);
4594 snd_hda_sequence_write(codec, spec->spec_init_verbs);
5aaca44d
IM		 4595
4596 ca0132_select_out(codec);
4597 ca0132_select_mic(codec);
4598
a73d511c
IM		 4599 snd_hda_jack_report_sync(codec);
4600
664c7155 4601 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 4602
4603 return 0;
4604}
4605
95c6e9cb
IM		 4606static void ca0132_free(struct hda_codec *codec)
4607{
5aaca44d
IM		 4608 struct ca0132_spec *spec = codec->spec;
4609
993884f6 4610 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d
IM		 4611 snd_hda_power_up(codec);
4612 snd_hda_sequence_write(codec, spec->base_exit_verbs);
95c6e9cb 4613 ca0132_exit_chip(codec);
5aaca44d 4614 snd_hda_power_down(codec);
d5c016b5 4615 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 4616 kfree(codec->spec);
4617}
4618
071f1344 4619static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 4620 .build_controls = ca0132_build_controls,
4621 .build_pcms = ca0132_build_pcms,
4622 .init = ca0132_init,
4623 .free = ca0132_free,
f8fb1170 4624 .unsol_event = snd_hda_jack_unsol_event,
95c6e9cb
IM		 4625};
4626
441aa6a0
IM		 4627static void ca0132_config(struct hda_codec *codec)
4628{
4629 struct ca0132_spec *spec = codec->spec;
4630 struct auto_pin_cfg *cfg = &spec->autocfg;
4631
4632 spec->dacs[0] = 0x2;
4633 spec->dacs[1] = 0x3;
4634 spec->dacs[2] = 0x4;
4635
4636 spec->multiout.dac_nids = spec->dacs;
4637 spec->multiout.num_dacs = 3;
4638 spec->multiout.max_channels = 2;
4639
d5c016b5
GM		 4640 if (spec->quirk == QUIRK_ALIENWARE) {
4641 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
fe14f39e
TI		 4642 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
4643
4644 spec->num_outputs = 2;
4645 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 4646 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 4647 spec->shared_out_nid = 0x2;
4648 spec->unsol_tag_hp = 0x0f;
4649
4650 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4651 spec->adcs[1] = 0x8; /* analog mic2 */
4652 spec->adcs[2] = 0xa; /* what u hear */
4653
4654 spec->num_inputs = 3;
4655 spec->input_pins[0] = 0x12;
4656 spec->input_pins[1] = 0x11;
4657 spec->input_pins[2] = 0x13;
4658 spec->shared_mic_nid = 0x7;
4659 spec->unsol_tag_amic1 = 0x11;
4660 } else {
4661 spec->num_outputs = 2;
4662 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 4663 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 4664 spec->shared_out_nid = 0x2;
4665 spec->unsol_tag_hp = spec->out_pins[1];
4666
4667 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4668 spec->adcs[1] = 0x8; /* analog mic2 */
4669 spec->adcs[2] = 0xa; /* what u hear */
4670
4671 spec->num_inputs = 3;
4672 spec->input_pins[0] = 0x12;
4673 spec->input_pins[1] = 0x11;
4674 spec->input_pins[2] = 0x13;
4675 spec->shared_mic_nid = 0x7;
4676 spec->unsol_tag_amic1 = spec->input_pins[0];
4677
4678 /* SPDIF I/O */
4679 spec->dig_out = 0x05;
4680 spec->multiout.dig_out_nid = spec->dig_out;
4681 cfg->dig_out_pins[0] = 0x0c;
4682 cfg->dig_outs = 1;
4683 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4684 spec->dig_in = 0x09;
4685 cfg->dig_in_pin = 0x0e;
4686 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
d5c016b5 4687 }
441aa6a0
IM		 4688}
4689
d5c016b5
GM		 4690static int ca0132_prepare_verbs(struct hda_codec *codec)
4691{
4692/* Verbs + terminator (an empty element) */
4693#define NUM_SPEC_VERBS 4
4694 struct ca0132_spec *spec = codec->spec;
4695
4696 spec->chip_init_verbs = ca0132_init_verbs0;
4697 spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL);
4698 if (!spec->spec_init_verbs)
4699 return -ENOMEM;
4700
4701 /* HP jack autodetection */
4702 spec->spec_init_verbs[0].nid = spec->unsol_tag_hp;
4703 spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4704 spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp;
4705
4706 /* MIC1 jack autodetection */
4707 spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1;
4708 spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4709 spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1;
4710
4711 /* config EAPD */
4712 spec->spec_init_verbs[2].nid = 0x0b;
4713 spec->spec_init_verbs[2].param = 0x78D;
4714 spec->spec_init_verbs[2].verb = 0x00;
4715
4716 /* Previously commented configuration */
4717 /*
4718 spec->spec_init_verbs[3].nid = 0x0b;
4719 spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE;
4720 spec->spec_init_verbs[3].verb = 0x02;
4721
4722 spec->spec_init_verbs[4].nid = 0x10;
4723 spec->spec_init_verbs[4].param = 0x78D;
4724 spec->spec_init_verbs[4].verb = 0x02;
4725
4726 spec->spec_init_verbs[5].nid = 0x10;
4727 spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE;
4728 spec->spec_init_verbs[5].verb = 0x02;
4729 */
4730
4731 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
4732 return 0;
4733}
4734
95c6e9cb
IM		 4735static int patch_ca0132(struct hda_codec *codec)
4736{
4737 struct ca0132_spec *spec;
a73d511c 4738 int err;
d5c016b5 4739 const struct snd_pci_quirk *quirk;
95c6e9cb 4740
4e76a883 4741 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 4742
4743 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4744 if (!spec)
4745 return -ENOMEM;
4746 codec->spec = spec;
993884f6 4747 spec->codec = codec;
95c6e9cb 4748
225068ab
TI		 4749 codec->patch_ops = ca0132_patch_ops;
4750 codec->pcm_format_first = 1;
4751 codec->no_sticky_stream = 1;
4752
d5c016b5
GM		 4753 /* Detect codec quirk */
4754 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
4755 if (quirk)
4756 spec->quirk = quirk->value;
4757 else
4758 spec->quirk = QUIRK_NONE;
4759
e24aa0a4 4760 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271
IM		 4761 spec->num_mixers = 1;
4762 spec->mixers[0] = ca0132_mixer;
4763
5aaca44d
IM		 4764 spec->base_init_verbs = ca0132_base_init_verbs;
4765 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 4766
993884f6
CCC		 4767 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4768
95c6e9cb
IM		 4769 ca0132_init_chip(codec);
4770
4771 ca0132_config(codec);
4772
d5c016b5
GM		 4773 err = ca0132_prepare_verbs(codec);
4774 if (err < 0)
cc91ceaf 4775 goto error;
d5c016b5 4776
a73d511c
IM		 4777 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4778 if (err < 0)
cc91ceaf 4779 goto error;
a73d511c 4780
95c6e9cb 4781 return 0;
cc91ceaf
TI		 4782
4783 error:
4784 ca0132_free(codec);
4785 return err;
95c6e9cb
IM		 4786}
4787
4788/*
4789 * patch entries
4790 */
b9a94a9c
TI		 4791static struct hda_device_id snd_hda_id_ca0132[] = {
4792 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 4793 {} /* terminator */
4794};
b9a94a9c 4795MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 4796
4797MODULE_LICENSE("GPL");
406261ce 4798MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 4799
d8a766a1 4800static struct hda_codec_driver ca0132_driver = {
b9a94a9c 4801 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 4802};
4803
d8a766a1 4804module_hda_codec_driver(ca0132_driver);
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