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ALSA: hda/ca0132 - Add output set commands for AE-5
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
aa31704f
CM		 31#include <linux/types.h>
32#include <linux/io.h>
33#include <linux/pci.h>
95c6e9cb 34#include <sound/core.h>
be57bfff 35#include <sound/hda_codec.h>
95c6e9cb 36#include "hda_local.h"
128bc4ba 37#include "hda_auto_parser.h"
5aaca44d 38#include "hda_jack.h"
95c6e9cb 39
bcd109c0
IM		 40#include "ca0132_regs.h"
41
ef6b2ead
IM		 42/* Enable this to see controls for tuning purpose. */
43/*#define ENABLE_TUNING_CONTROLS*/
44
8e142e9e
TS		 45#ifdef ENABLE_TUNING_CONTROLS
46#include <sound/tlv.h>
47#endif
48
ef6b2ead
IM		 49#define FLOAT_ZERO 0x00000000
50#define FLOAT_ONE 0x3f800000
51#define FLOAT_TWO 0x40000000
38ba69ff 52#define FLOAT_THREE 0x40400000
7cb9d94c 53#define FLOAT_EIGHT 0x41000000
ef6b2ead
IM		 54#define FLOAT_MINUS_5 0xc0a00000
55
ef6b2ead
IM		 56#define UNSOL_TAG_DSP 0x16
57
4aa3bb0c
IM		 58#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
59#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
60
61#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
62#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
63#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
64
65#define MASTERCONTROL 0x80
ef6b2ead
IM		 66#define MASTERCONTROL_ALLOC_DMA_CHAN 10
67#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 68
95c6e9cb
IM		 69#define WIDGET_CHIP_CTRL 0x15
70#define WIDGET_DSP_CTRL 0x16
71
4aa3bb0c
IM		 72#define MEM_CONNID_MICIN1 3
73#define MEM_CONNID_MICIN2 5
74#define MEM_CONNID_MICOUT1 12
75#define MEM_CONNID_MICOUT2 14
76#define MEM_CONNID_WUH 10
77#define MEM_CONNID_DSP 16
78#define MEM_CONNID_DMIC 100
79
80#define SCP_SET 0
81#define SCP_GET 1
82
01ef7dbf 83#define EFX_FILE "ctefx.bin"
7a928186 84#define DESKTOP_EFX_FILE "ctefx-desktop.bin"
8a19bcee 85#define R3DI_EFX_FILE "ctefx-r3di.bin"
01ef7dbf 86
24f3cede 87#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 88MODULE_FIRMWARE(EFX_FILE);
7a928186 89MODULE_FIRMWARE(DESKTOP_EFX_FILE);
8a19bcee 90MODULE_FIRMWARE(R3DI_EFX_FILE);
7a527ede 91#endif
01ef7dbf 92
3a03f83b 93static const char *const dirstr[2] = { "Playback", "Capture" };
ef6b2ead 94
7cb9d94c 95#define NUM_OF_OUTPUTS 3
ef6b2ead
IM		 96enum {
97 SPEAKER_OUT,
7cb9d94c
CM		 98 HEADPHONE_OUT,
99 SURROUND_OUT
ef6b2ead
IM		 100};
101
102enum {
103 DIGITAL_MIC,
104 LINE_MIC_IN
105};
106
7cb9d94c 107/* Strings for Input Source Enum Control */
3a03f83b 108static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
7cb9d94c
CM		 109#define IN_SRC_NUM_OF_INPUTS 3
110enum {
111 REAR_MIC,
112 REAR_LINE_IN,
113 FRONT_MIC,
114};
115
ef6b2ead
IM		 116enum {
117#define VNODE_START_NID 0x80
118 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
119 VNID_MIC,
120 VNID_HP_SEL,
121 VNID_AMIC1_SEL,
122 VNID_HP_ASEL,
123 VNID_AMIC1_ASEL,
124 VNODE_END_NID,
125#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
126
127#define EFFECT_START_NID 0x90
128#define OUT_EFFECT_START_NID EFFECT_START_NID
129 SURROUND = OUT_EFFECT_START_NID,
130 CRYSTALIZER,
131 DIALOG_PLUS,
132 SMART_VOLUME,
133 X_BASS,
134 EQUALIZER,
135 OUT_EFFECT_END_NID,
136#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
137
138#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
139 ECHO_CANCELLATION = IN_EFFECT_START_NID,
140 VOICE_FOCUS,
141 MIC_SVM,
142 NOISE_REDUCTION,
143 IN_EFFECT_END_NID,
144#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
145
146 VOICEFX = IN_EFFECT_END_NID,
147 PLAY_ENHANCEMENT,
148 CRYSTAL_VOICE,
7cb9d94c
CM		 149 EFFECT_END_NID,
150 OUTPUT_SOURCE_ENUM,
47cdf76e
CM		 151 INPUT_SOURCE_ENUM,
152 XBASS_XOVER,
153 EQ_PRESET_ENUM,
154 SMART_VOLUME_ENUM,
155 MIC_BOOST_ENUM
ef6b2ead
IM		 156#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
157};
158
159/* Effects values size*/
160#define EFFECT_VALS_MAX_COUNT 12
161
47cdf76e
CM		 162/*
163 * Default values for the effect slider controls, they are in order of their
164 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
165 * X-bass.
166 */
167static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
168/* Amount of effect level sliders for ca0132_alt controls. */
169#define EFFECT_LEVEL_SLIDERS 5
170
e8412ca4
DR		 171/* Latency introduced by DSP blocks in milliseconds. */
172#define DSP_CAPTURE_INIT_LATENCY 0
173#define DSP_CRYSTAL_VOICE_LATENCY 124
174#define DSP_PLAYBACK_INIT_LATENCY 13
175#define DSP_PLAY_ENHANCEMENT_LATENCY 30
176#define DSP_SPEAKER_OUT_LATENCY 7
177
ef6b2ead 178struct ct_effect {
975cc02a 179 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 180 hda_nid_t nid;
181 int mid; /*effect module ID*/
182 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
183 int direct; /* 0:output; 1:input*/
184 int params; /* number of default non-on/off params */
185 /*effect default values, 1st is on/off. */
186 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
187};
188
189#define EFX_DIR_OUT 0
190#define EFX_DIR_IN 1
191
862154bb 192static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
ef6b2ead
IM		 193 { .name = "Surround",
194 .nid = SURROUND,
195 .mid = 0x96,
196 .reqs = {0, 1},
197 .direct = EFX_DIR_OUT,
198 .params = 1,
199 .def_vals = {0x3F800000, 0x3F2B851F}
200 },
201 { .name = "Crystalizer",
202 .nid = CRYSTALIZER,
203 .mid = 0x96,
204 .reqs = {7, 8},
205 .direct = EFX_DIR_OUT,
206 .params = 1,
207 .def_vals = {0x3F800000, 0x3F266666}
208 },
209 { .name = "Dialog Plus",
210 .nid = DIALOG_PLUS,
211 .mid = 0x96,
212 .reqs = {2, 3},
213 .direct = EFX_DIR_OUT,
214 .params = 1,
215 .def_vals = {0x00000000, 0x3F000000}
216 },
217 { .name = "Smart Volume",
218 .nid = SMART_VOLUME,
219 .mid = 0x96,
220 .reqs = {4, 5, 6},
221 .direct = EFX_DIR_OUT,
222 .params = 2,
223 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
224 },
225 { .name = "X-Bass",
226 .nid = X_BASS,
227 .mid = 0x96,
228 .reqs = {24, 23, 25},
229 .direct = EFX_DIR_OUT,
230 .params = 2,
231 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
232 },
233 { .name = "Equalizer",
234 .nid = EQUALIZER,
235 .mid = 0x96,
236 .reqs = {9, 10, 11, 12, 13, 14,
237 15, 16, 17, 18, 19, 20},
238 .direct = EFX_DIR_OUT,
239 .params = 11,
240 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
241 0x00000000, 0x00000000, 0x00000000, 0x00000000,
242 0x00000000, 0x00000000, 0x00000000, 0x00000000}
243 },
244 { .name = "Echo Cancellation",
245 .nid = ECHO_CANCELLATION,
246 .mid = 0x95,
247 .reqs = {0, 1, 2, 3},
248 .direct = EFX_DIR_IN,
249 .params = 3,
250 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
251 },
252 { .name = "Voice Focus",
253 .nid = VOICE_FOCUS,
254 .mid = 0x95,
255 .reqs = {6, 7, 8, 9},
256 .direct = EFX_DIR_IN,
257 .params = 3,
258 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
259 },
260 { .name = "Mic SVM",
261 .nid = MIC_SVM,
262 .mid = 0x95,
263 .reqs = {44, 45},
264 .direct = EFX_DIR_IN,
265 .params = 1,
266 .def_vals = {0x00000000, 0x3F3D70A4}
267 },
268 { .name = "Noise Reduction",
269 .nid = NOISE_REDUCTION,
270 .mid = 0x95,
271 .reqs = {4, 5},
272 .direct = EFX_DIR_IN,
273 .params = 1,
274 .def_vals = {0x3F800000, 0x3F000000}
275 },
276 { .name = "VoiceFX",
277 .nid = VOICEFX,
278 .mid = 0x95,
279 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
280 .direct = EFX_DIR_IN,
281 .params = 8,
282 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
283 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
284 0x00000000}
285 }
286};
287
288/* Tuning controls */
289#ifdef ENABLE_TUNING_CONTROLS
290
291enum {
292#define TUNING_CTL_START_NID 0xC0
293 WEDGE_ANGLE = TUNING_CTL_START_NID,
294 SVM_LEVEL,
295 EQUALIZER_BAND_0,
296 EQUALIZER_BAND_1,
297 EQUALIZER_BAND_2,
298 EQUALIZER_BAND_3,
299 EQUALIZER_BAND_4,
300 EQUALIZER_BAND_5,
301 EQUALIZER_BAND_6,
302 EQUALIZER_BAND_7,
303 EQUALIZER_BAND_8,
304 EQUALIZER_BAND_9,
305 TUNING_CTL_END_NID
306#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
307};
308
309struct ct_tuning_ctl {
975cc02a 310 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 311 hda_nid_t parent_nid;
312 hda_nid_t nid;
313 int mid; /*effect module ID*/
314 int req; /*effect module request*/
315 int direct; /* 0:output; 1:input*/
316 unsigned int def_val;/*effect default values*/
317};
318
862154bb 319static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
ef6b2ead
IM		 320 { .name = "Wedge Angle",
321 .parent_nid = VOICE_FOCUS,
322 .nid = WEDGE_ANGLE,
323 .mid = 0x95,
324 .req = 8,
325 .direct = EFX_DIR_IN,
326 .def_val = 0x41F00000
327 },
328 { .name = "SVM Level",
329 .parent_nid = MIC_SVM,
330 .nid = SVM_LEVEL,
331 .mid = 0x95,
332 .req = 45,
333 .direct = EFX_DIR_IN,
334 .def_val = 0x3F3D70A4
335 },
336 { .name = "EQ Band0",
337 .parent_nid = EQUALIZER,
338 .nid = EQUALIZER_BAND_0,
339 .mid = 0x96,
340 .req = 11,
341 .direct = EFX_DIR_OUT,
342 .def_val = 0x00000000
343 },
344 { .name = "EQ Band1",
345 .parent_nid = EQUALIZER,
346 .nid = EQUALIZER_BAND_1,
347 .mid = 0x96,
348 .req = 12,
349 .direct = EFX_DIR_OUT,
350 .def_val = 0x00000000
351 },
352 { .name = "EQ Band2",
353 .parent_nid = EQUALIZER,
354 .nid = EQUALIZER_BAND_2,
355 .mid = 0x96,
356 .req = 13,
357 .direct = EFX_DIR_OUT,
358 .def_val = 0x00000000
359 },
360 { .name = "EQ Band3",
361 .parent_nid = EQUALIZER,
362 .nid = EQUALIZER_BAND_3,
363 .mid = 0x96,
364 .req = 14,
365 .direct = EFX_DIR_OUT,
366 .def_val = 0x00000000
367 },
368 { .name = "EQ Band4",
369 .parent_nid = EQUALIZER,
370 .nid = EQUALIZER_BAND_4,
371 .mid = 0x96,
372 .req = 15,
373 .direct = EFX_DIR_OUT,
374 .def_val = 0x00000000
375 },
376 { .name = "EQ Band5",
377 .parent_nid = EQUALIZER,
378 .nid = EQUALIZER_BAND_5,
379 .mid = 0x96,
380 .req = 16,
381 .direct = EFX_DIR_OUT,
382 .def_val = 0x00000000
383 },
384 { .name = "EQ Band6",
385 .parent_nid = EQUALIZER,
386 .nid = EQUALIZER_BAND_6,
387 .mid = 0x96,
388 .req = 17,
389 .direct = EFX_DIR_OUT,
390 .def_val = 0x00000000
391 },
392 { .name = "EQ Band7",
393 .parent_nid = EQUALIZER,
394 .nid = EQUALIZER_BAND_7,
395 .mid = 0x96,
396 .req = 18,
397 .direct = EFX_DIR_OUT,
398 .def_val = 0x00000000
399 },
400 { .name = "EQ Band8",
401 .parent_nid = EQUALIZER,
402 .nid = EQUALIZER_BAND_8,
403 .mid = 0x96,
404 .req = 19,
405 .direct = EFX_DIR_OUT,
406 .def_val = 0x00000000
407 },
408 { .name = "EQ Band9",
409 .parent_nid = EQUALIZER,
410 .nid = EQUALIZER_BAND_9,
411 .mid = 0x96,
412 .req = 20,
413 .direct = EFX_DIR_OUT,
414 .def_val = 0x00000000
415 }
416};
417#endif
418
419/* Voice FX Presets */
420#define VOICEFX_MAX_PARAM_COUNT 9
421
422struct ct_voicefx {
423 char *name;
424 hda_nid_t nid;
425 int mid;
426 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
427};
428
429struct ct_voicefx_preset {
430 char *name; /*preset name*/
431 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
432};
433
862154bb 434static const struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 435 .name = "VoiceFX Capture Switch",
436 .nid = VOICEFX,
437 .mid = 0x95,
438 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
439};
440
862154bb 441static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 442 { .name = "Neutral",
443 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
444 0x44FA0000, 0x3F800000, 0x3F800000,
445 0x3F800000, 0x00000000, 0x00000000 }
446 },
447 { .name = "Female2Male",
448 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
449 0x44FA0000, 0x3F19999A, 0x3F866666,
450 0x3F800000, 0x00000000, 0x00000000 }
451 },
452 { .name = "Male2Female",
453 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
454 0x450AC000, 0x4017AE14, 0x3F6B851F,
455 0x3F800000, 0x00000000, 0x00000000 }
456 },
457 { .name = "ScrappyKid",
458 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
459 0x44FA0000, 0x40400000, 0x3F28F5C3,
460 0x3F800000, 0x00000000, 0x00000000 }
461 },
462 { .name = "Elderly",
463 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
464 0x44E10000, 0x3FB33333, 0x3FB9999A,
465 0x3F800000, 0x3E3A2E43, 0x00000000 }
466 },
467 { .name = "Orc",
468 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
469 0x45098000, 0x3F266666, 0x3FC00000,
470 0x3F800000, 0x00000000, 0x00000000 }
471 },
472 { .name = "Elf",
473 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
474 0x45193000, 0x3F8E147B, 0x3F75C28F,
475 0x3F800000, 0x00000000, 0x00000000 }
476 },
477 { .name = "Dwarf",
478 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
479 0x45007000, 0x3F451EB8, 0x3F7851EC,
480 0x3F800000, 0x00000000, 0x00000000 }
481 },
482 { .name = "AlienBrute",
483 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
484 0x451F6000, 0x3F266666, 0x3FA7D945,
485 0x3F800000, 0x3CF5C28F, 0x00000000 }
486 },
487 { .name = "Robot",
488 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
489 0x44FA0000, 0x3FB2718B, 0x3F800000,
490 0xBC07010E, 0x00000000, 0x00000000 }
491 },
492 { .name = "Marine",
493 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
494 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
495 0x3F0A3D71, 0x00000000, 0x00000000 }
496 },
497 { .name = "Emo",
498 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
499 0x44FA0000, 0x3F800000, 0x3F800000,
500 0x3E4CCCCD, 0x00000000, 0x00000000 }
501 },
502 { .name = "DeepVoice",
503 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
504 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
505 0x3F800000, 0x00000000, 0x00000000 }
506 },
507 { .name = "Munchkin",
508 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
509 0x44FA0000, 0x3F800000, 0x3F1A043C,
510 0x3F800000, 0x00000000, 0x00000000 }
511 }
512};
513
47cdf76e
CM		 514/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
515
516#define EQ_PRESET_MAX_PARAM_COUNT 11
517
518struct ct_eq {
519 char *name;
520 hda_nid_t nid;
521 int mid;
522 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
523};
524
525struct ct_eq_preset {
526 char *name; /*preset name*/
527 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
528};
529
862154bb 530static const struct ct_eq ca0132_alt_eq_enum = {
47cdf76e
CM		 531 .name = "FX: Equalizer Preset Switch",
532 .nid = EQ_PRESET_ENUM,
533 .mid = 0x96,
534 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
535};
536
537
862154bb 538static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
47cdf76e
CM		 539 { .name = "Flat",
540 .vals = { 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000, 0x00000000,
542 0x00000000, 0x00000000, 0x00000000,
543 0x00000000, 0x00000000 }
544 },
545 { .name = "Acoustic",
546 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
547 0x40000000, 0x00000000, 0x00000000,
548 0x00000000, 0x00000000, 0x40000000,
549 0x40000000, 0x40000000 }
550 },
551 { .name = "Classical",
552 .vals = { 0x00000000, 0x00000000, 0x40C00000,
553 0x40C00000, 0x40466666, 0x00000000,
554 0x00000000, 0x00000000, 0x00000000,
555 0x40466666, 0x40466666 }
556 },
557 { .name = "Country",
558 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
559 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
560 0x00000000, 0x00000000, 0x40000000,
561 0x40466666, 0x40800000 }
562 },
563 { .name = "Dance",
564 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
565 0x40466666, 0x40866666, 0xBF99999A,
566 0xBF99999A, 0x00000000, 0x00000000,
567 0x40800000, 0x40800000 }
568 },
569 { .name = "Jazz",
570 .vals = { 0x00000000, 0x00000000, 0x00000000,
571 0x3F8CCCCD, 0x40800000, 0x40800000,
572 0x40800000, 0x00000000, 0x3F8CCCCD,
573 0x40466666, 0x40466666 }
574 },
575 { .name = "New Age",
576 .vals = { 0x00000000, 0x00000000, 0x40000000,
577 0x40000000, 0x00000000, 0x00000000,
578 0x00000000, 0x3F8CCCCD, 0x40000000,
579 0x40000000, 0x40000000 }
580 },
581 { .name = "Pop",
582 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
583 0x40000000, 0x40000000, 0x00000000,
584 0xBF99999A, 0xBF99999A, 0x00000000,
585 0x40466666, 0x40C00000 }
586 },
587 { .name = "Rock",
588 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
589 0x3F8CCCCD, 0x40000000, 0xBF99999A,
590 0xBF99999A, 0x00000000, 0x00000000,
591 0x40800000, 0x40800000 }
592 },
593 { .name = "Vocal",
594 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
595 0xBF99999A, 0x00000000, 0x40466666,
596 0x40800000, 0x40466666, 0x00000000,
597 0x00000000, 0x3F8CCCCD }
598 }
599};
600
7cb9d94c
CM		 601/* DSP command sequences for ca0132_alt_select_out */
602#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
603struct ca0132_alt_out_set {
604 char *name; /*preset name*/
605 unsigned char commands;
606 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
607 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
608 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
609};
610
611static const struct ca0132_alt_out_set alt_out_presets[] = {
612 { .name = "Line Out",
613 .commands = 7,
614 .mids = { 0x96, 0x96, 0x96, 0x8F,
615 0x96, 0x96, 0x96 },
616 .reqs = { 0x19, 0x17, 0x18, 0x01,
617 0x1F, 0x15, 0x3A },
618 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
619 0x00000000, 0x00000000, 0x00000000,
620 0x00000000 }
621 },
622 { .name = "Headphone",
623 .commands = 7,
624 .mids = { 0x96, 0x96, 0x96, 0x8F,
625 0x96, 0x96, 0x96 },
626 .reqs = { 0x19, 0x17, 0x18, 0x01,
627 0x1F, 0x15, 0x3A },
628 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
629 0x00000000, 0x00000000, 0x00000000,
630 0x00000000 }
631 },
632 { .name = "Surround",
633 .commands = 8,
634 .mids = { 0x96, 0x8F, 0x96, 0x96,
635 0x96, 0x96, 0x96, 0x96 },
636 .reqs = { 0x18, 0x01, 0x1F, 0x15,
637 0x3A, 0x1A, 0x1B, 0x1C },
638 .vals = { 0x00000000, 0x00000000, 0x00000000,
639 0x00000000, 0x00000000, 0x00000000,
640 0x00000000, 0x00000000 }
641 }
642};
643
017310fb
CM		 644/*
645 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
646 * and I don't know what the third req is, but it's always zero. I assume it's
647 * some sort of update or set command to tell the DSP there's new volume info.
648 */
649#define DSP_VOL_OUT 0
650#define DSP_VOL_IN 1
651
652struct ct_dsp_volume_ctl {
653 hda_nid_t vnid;
654 int mid; /* module ID*/
655 unsigned int reqs[3]; /* scp req ID */
656};
657
862154bb 658static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
017310fb
CM		 659 { .vnid = VNID_SPK,
660 .mid = 0x32,
661 .reqs = {3, 4, 2}
662 },
663 { .vnid = VNID_MIC,
664 .mid = 0x37,
665 .reqs = {2, 3, 1}
666 }
667};
668
2283c85b
CM		 669/* Values for ca0113_mmio_command_set for selecting output. */
670#define AE5_CA0113_OUT_SET_COMMANDS 6
671struct ae5_ca0113_output_set {
672 unsigned int group[AE5_CA0113_OUT_SET_COMMANDS];
673 unsigned int target[AE5_CA0113_OUT_SET_COMMANDS];
674 unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS];
675};
676
677static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = {
678 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
679 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
680 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
681 },
682 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
683 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
684 .vals = { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 }
685 },
686 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
687 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
688 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }
689 }
690};
691
95c6e9cb
IM		 692enum hda_cmd_vendor_io {
693 /* for DspIO node */
694 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
695 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
696
697 VENDOR_DSPIO_STATUS = 0xF01,
698 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
699 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
700 VENDOR_DSPIO_DSP_INIT = 0x703,
701 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
702 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
703
704 /* for ChipIO node */
705 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
706 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
707 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
708 VENDOR_CHIPIO_DATA_LOW = 0x300,
709 VENDOR_CHIPIO_DATA_HIGH = 0x400,
710
bf85a91c
CM		 711 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
712 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
713
95c6e9cb
IM		 714 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
715 VENDOR_CHIPIO_STATUS = 0xF01,
716 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
717 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
718
4aa3bb0c
IM		 719 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
720 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
bf85a91c
CM		 721 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
722 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
723 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
4aa3bb0c 724
95c6e9cb 725 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 726 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 727
728 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
729 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
730 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
731 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
732 VENDOR_CHIPIO_FLAG_SET = 0x70F,
733 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 734 VENDOR_CHIPIO_PARAM_SET = 0x710,
735 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 736
737 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
738 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
739 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
740 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
741
4aa3bb0c
IM		 742 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
743 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
744 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
745 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
746
747 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
748 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
749 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
750 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
751 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
752 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
753
754 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 755};
756
757/*
758 * Control flag IDs
759 */
760enum control_flag_id {
761 /* Connection manager stream setup is bypassed/enabled */
762 CONTROL_FLAG_C_MGR = 0,
763 /* DSP DMA is bypassed/enabled */
764 CONTROL_FLAG_DMA = 1,
765 /* 8051 'idle' mode is disabled/enabled */
766 CONTROL_FLAG_IDLE_ENABLE = 2,
767 /* Tracker for the SPDIF-in path is bypassed/enabled */
768 CONTROL_FLAG_TRACKER = 3,
769 /* DigitalOut to Spdif2Out connection is disabled/enabled */
770 CONTROL_FLAG_SPDIF2OUT = 4,
771 /* Digital Microphone is disabled/enabled */
772 CONTROL_FLAG_DMIC = 5,
773 /* ADC_B rate is 48 kHz/96 kHz */
774 CONTROL_FLAG_ADC_B_96KHZ = 6,
775 /* ADC_C rate is 48 kHz/96 kHz */
776 CONTROL_FLAG_ADC_C_96KHZ = 7,
777 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
778 CONTROL_FLAG_DAC_96KHZ = 8,
779 /* DSP rate is 48 kHz/96 kHz */
780 CONTROL_FLAG_DSP_96KHZ = 9,
781 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
782 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
783 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
784 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
785 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
786 CONTROL_FLAG_DECODE_LOOP = 12,
787 /* De-emphasis filter on DAC-1 disabled/enabled */
788 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
789 /* De-emphasis filter on DAC-2 disabled/enabled */
790 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
791 /* De-emphasis filter on DAC-3 disabled/enabled */
792 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
793 /* High-pass filter on ADC_B disabled/enabled */
794 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
795 /* High-pass filter on ADC_C disabled/enabled */
796 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
797 /* Common mode on Port_A disabled/enabled */
798 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
799 /* Common mode on Port_D disabled/enabled */
800 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
801 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
802 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
803 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 804 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 805 /* ASI rate is 48kHz/96kHz */
806 CONTROL_FLAG_ASI_96KHZ = 22,
807 /* DAC power settings able to control attached ports no/yes */
808 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
809 /* Clock Stop OK reporting is disabled/enabled */
810 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
811 /* Number of control flags */
812 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
813};
814
815/*
816 * Control parameter IDs
817 */
4aa3bb0c 818enum control_param_id {
ef6b2ead
IM		 819 /* 0: None, 1: Mic1In*/
820 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 821 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
822 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 823 /* Port A output stage gain setting to use when 16 Ohm output
824 * impedance is selected*/
825 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
826 /* Port D output stage gain setting to use when 16 Ohm output
827 * impedance is selected*/
828 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb 829
bf85a91c
CM		 830 /*
831 * This control param name was found in the 8051 memory, and makes
832 * sense given the fact the AE-5 uses it and has the ASI flag set.
833 */
834 CONTROL_PARAM_ASI = 23,
835
95c6e9cb
IM		 836 /* Stream Control */
837
838 /* Select stream with the given ID */
839 CONTROL_PARAM_STREAM_ID = 24,
840 /* Source connection point for the selected stream */
841 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
842 /* Destination connection point for the selected stream */
843 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
844 /* Number of audio channels in the selected stream */
845 CONTROL_PARAM_STREAMS_CHANNELS = 27,
846 /*Enable control for the selected stream */
847 CONTROL_PARAM_STREAM_CONTROL = 28,
848
849 /* Connection Point Control */
850
851 /* Select connection point with the given ID */
852 CONTROL_PARAM_CONN_POINT_ID = 29,
853 /* Connection point sample rate */
854 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
855
856 /* Node Control */
857
858 /* Select HDA node with the given ID */
859 CONTROL_PARAM_NODE_ID = 31
860};
861
862/*
863 * Dsp Io Status codes
864 */
865enum hda_vendor_status_dspio {
866 /* Success */
867 VENDOR_STATUS_DSPIO_OK = 0x00,
868 /* Busy, unable to accept new command, the host must retry */
869 VENDOR_STATUS_DSPIO_BUSY = 0x01,
870 /* SCP command queue is full */
871 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
872 /* SCP response queue is empty */
873 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
874};
875
876/*
877 * Chip Io Status codes
878 */
879enum hda_vendor_status_chipio {
880 /* Success */
881 VENDOR_STATUS_CHIPIO_OK = 0x00,
882 /* Busy, unable to accept new command, the host must retry */
883 VENDOR_STATUS_CHIPIO_BUSY = 0x01
884};
885
886/*
887 * CA0132 sample rate
888 */
889enum ca0132_sample_rate {
890 SR_6_000 = 0x00,
891 SR_8_000 = 0x01,
892 SR_9_600 = 0x02,
893 SR_11_025 = 0x03,
894 SR_16_000 = 0x04,
895 SR_22_050 = 0x05,
896 SR_24_000 = 0x06,
897 SR_32_000 = 0x07,
898 SR_44_100 = 0x08,
899 SR_48_000 = 0x09,
900 SR_88_200 = 0x0A,
901 SR_96_000 = 0x0B,
902 SR_144_000 = 0x0C,
903 SR_176_400 = 0x0D,
904 SR_192_000 = 0x0E,
905 SR_384_000 = 0x0F,
906
907 SR_COUNT = 0x10,
908
909 SR_RATE_UNKNOWN = 0x1F
910};
911
01ef7dbf
IM		 912enum dsp_download_state {
913 DSP_DOWNLOAD_FAILED = -1,
914 DSP_DOWNLOAD_INIT = 0,
915 DSP_DOWNLOADING = 1,
916 DSP_DOWNLOADED = 2
917};
918
01ef7dbf
IM		 919/* retrieve parameters from hda format */
920#define get_hdafmt_chs(fmt) (fmt & 0xf)
921#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
922#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
923#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
924
925/*
926 * CA0132 specific
927 */
928
929struct ca0132_spec {
b0eaa072 930 const struct snd_kcontrol_new *mixers[5];
a7e76271 931 unsigned int num_mixers;
5aaca44d
IM		 932 const struct hda_verb *base_init_verbs;
933 const struct hda_verb *base_exit_verbs;
d5c016b5 934 const struct hda_verb *chip_init_verbs;
e42c7c73 935 const struct hda_verb *desktop_init_verbs;
d5c016b5 936 struct hda_verb *spec_init_verbs;
01ef7dbf 937 struct auto_pin_cfg autocfg;
5aaca44d
IM		 938
939 /* Nodes configurations */
01ef7dbf
IM		 940 struct hda_multi_out multiout;
941 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
942 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 943 unsigned int num_outputs;
01ef7dbf
IM		 944 hda_nid_t input_pins[AUTO_PIN_LAST];
945 hda_nid_t adcs[AUTO_PIN_LAST];
946 hda_nid_t dig_out;
947 hda_nid_t dig_in;
948 unsigned int num_inputs;
a7e76271
IM		 949 hda_nid_t shared_mic_nid;
950 hda_nid_t shared_out_nid;
d5c016b5 951 hda_nid_t unsol_tag_hp;
63177afc 952 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
d5c016b5 953 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 954
955 /* chip access */
956 struct mutex chipio_mutex; /* chip access mutex */
957 u32 curr_chip_addx;
958
959 /* DSP download related */
960 enum dsp_download_state dsp_state;
961 unsigned int dsp_stream_id;
962 unsigned int wait_scp;
963 unsigned int wait_scp_header;
964 unsigned int wait_num_data;
965 unsigned int scp_resp_header;
966 unsigned int scp_resp_data[4];
967 unsigned int scp_resp_count;
8a19bcee 968 bool alt_firmware_present;
38ba69ff 969 bool startup_check_entered;
e93ac30a 970 bool dsp_reload;
5aaca44d
IM		 971
972 /* mixer and effects related */
973 unsigned char dmic_ctl;
974 int cur_out_type;
975 int cur_mic_type;
976 long vnode_lvol[VNODES_COUNT];
977 long vnode_rvol[VNODES_COUNT];
978 long vnode_lswitch[VNODES_COUNT];
979 long vnode_rswitch[VNODES_COUNT];
980 long effects_switch[EFFECTS_COUNT];
981 long voicefx_val;
982 long cur_mic_boost;
7cb9d94c
CM		 983 /* ca0132_alt control related values */
984 unsigned char in_enum_val;
985 unsigned char out_enum_val;
47cdf76e
CM		 986 unsigned char mic_boost_enum_val;
987 unsigned char smart_volume_setting;
988 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
989 long xbass_xover_freq;
990 long eq_preset_val;
991 unsigned int tlv[4];
992 struct hda_vmaster_mute_hook vmaster_mute;
993
44f0c978 994
993884f6
CCC		 995 struct hda_codec *codec;
996 struct delayed_work unsol_hp_work;
d5c016b5 997 int quirk;
993884f6 998
44f0c978
IM		 999#ifdef ENABLE_TUNING_CONTROLS
1000 long cur_ctl_vals[TUNING_CTLS_COUNT];
1001#endif
aa31704f 1002 /*
08eca6b1
CM		 1003 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1004 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1005 * things.
aa31704f 1006 */
08eca6b1 1007 bool use_pci_mmio;
aa31704f 1008 void __iomem *mem_base;
009b8f97
CM		 1009
1010 /*
1011 * Whether or not to use the alt functions like alt_select_out,
1012 * alt_select_in, etc. Only used on desktop codecs for now, because of
1013 * surround sound support.
1014 */
1015 bool use_alt_functions;
47cdf76e
CM		 1016
1017 /*
1018 * Whether or not to use alt controls: volume effect sliders, EQ
1019 * presets, smart volume presets, and new control names with FX prefix.
1020 * Renames PlayEnhancement and CrystalVoice too.
1021 */
1022 bool use_alt_controls;
01ef7dbf
IM		 1023};
1024
d5c016b5
GM		 1025/*
1026 * CA0132 quirks table
1027 */
1028enum {
1029 QUIRK_NONE,
1030 QUIRK_ALIENWARE,
a57a46b9 1031 QUIRK_ALIENWARE_M17XR4,
8a19bcee
CM		 1032 QUIRK_SBZ,
1033 QUIRK_R3DI,
8f8c523c 1034 QUIRK_R3D,
f6276463 1035 QUIRK_AE5,
d5c016b5
GM		 1036};
1037
fe14f39e
TI		 1038static const struct hda_pintbl alienware_pincfgs[] = {
1039 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1040 { 0x0c, 0x411111f0 }, /* N/A */
1041 { 0x0d, 0x411111f0 }, /* N/A */
1042 { 0x0e, 0x411111f0 }, /* N/A */
1043 { 0x0f, 0x0321101f }, /* HP */
1044 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1045 { 0x11, 0x03a11021 }, /* Mic */
1046 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1047 { 0x13, 0x411111f0 }, /* N/A */
1048 { 0x18, 0x411111f0 }, /* N/A */
1049 {}
1050};
1051
63177afc
CM		 1052/* Sound Blaster Z pin configs taken from Windows Driver */
1053static const struct hda_pintbl sbz_pincfgs[] = {
1054 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1055 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1056 { 0x0d, 0x014510f0 }, /* Digital Out */
1057 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1058 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1059 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1060 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1061 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1062 { 0x13, 0x908700f0 }, /* What U Hear In*/
1063 { 0x18, 0x50d000f0 }, /* N/A */
1064 {}
1065};
1066
7f73df95
CM		 1067/* Recon3D pin configs taken from Windows Driver */
1068static const struct hda_pintbl r3d_pincfgs[] = {
1069 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1070 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1071 { 0x0d, 0x014510f0 }, /* Digital Out */
1072 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1073 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1074 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1075 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1076 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1077 { 0x13, 0x908700f0 }, /* What U Hear In*/
1078 { 0x18, 0x50d000f0 }, /* N/A */
1079 {}
1080};
1081
d06feaf0
CM		 1082/* Sound Blaster AE-5 pin configs taken from Windows Driver */
1083static const struct hda_pintbl ae5_pincfgs[] = {
1084 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1085 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1086 { 0x0d, 0x014510f0 }, /* Digital Out */
1087 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1088 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1089 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1090 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1091 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1092 { 0x13, 0x908700f0 }, /* What U Hear In*/
1093 { 0x18, 0x50d000f0 }, /* N/A */
1094 {}
1095};
1096
63177afc
CM		 1097/* Recon3D integrated pin configs taken from Windows Driver */
1098static const struct hda_pintbl r3di_pincfgs[] = {
1099 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1100 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1101 { 0x0d, 0x014510f0 }, /* Digital Out */
1102 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1103 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1104 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1105 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1106 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1107 { 0x13, 0x908700f0 }, /* What U Hear In*/
1108 { 0x18, 0x500000f0 }, /* N/A */
1109 {}
1110};
1111
d5c016b5 1112static const struct snd_pci_quirk ca0132_quirks[] = {
a57a46b9 1113 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
5328e1ea
GM		 1114 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1115 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 1116 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
8a19bcee
CM		 1117 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1118 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1119 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
dad59262 1120 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
c5a59d24 1121 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
8f8c523c 1122 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
f6276463 1123 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
d5c016b5
GM		 1124 {}
1125};
1126
01ef7dbf
IM		 1127/*
1128 * CA0132 codec access
1129 */
399ae725 1130static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 1131 unsigned int verb, unsigned int parm, unsigned int *res)
1132{
1133 unsigned int response;
1134 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1135 *res = response;
1136
1137 return ((response == -1) ? -1 : 0);
1138}
1139
1140static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1141 unsigned short converter_format, unsigned int *res)
1142{
1143 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1144 converter_format & 0xffff, res);
1145}
1146
1147static int codec_set_converter_stream_channel(struct hda_codec *codec,
1148 hda_nid_t nid, unsigned char stream,
1149 unsigned char channel, unsigned int *res)
1150{
1151 unsigned char converter_stream_channel = 0;
1152
1153 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1154 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1155 converter_stream_channel, res);
1156}
1157
1158/* Chip access helper function */
1159static int chipio_send(struct hda_codec *codec,
1160 unsigned int reg,
1161 unsigned int data)
1162{
1163 unsigned int res;
6d67530e 1164 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1165
1166 /* send bits of data specified by reg */
1167 do {
1168 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1169 reg, data);
1170 if (res == VENDOR_STATUS_CHIPIO_OK)
1171 return 0;
6d67530e
IM		 1172 msleep(20);
1173 } while (time_before(jiffies, timeout));
1174
01ef7dbf
IM		 1175 return -EIO;
1176}
1177
1178/*
1179 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1180 */
1181static int chipio_write_address(struct hda_codec *codec,
1182 unsigned int chip_addx)
1183{
4861af80 1184 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1185 int res;
1186
4861af80
IM		 1187 if (spec->curr_chip_addx == chip_addx)
1188 return 0;
1189
01ef7dbf
IM		 1190 /* send low 16 bits of the address */
1191 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1192 chip_addx & 0xffff);
1193
1194 if (res != -EIO) {
1195 /* send high 16 bits of the address */
1196 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1197 chip_addx >> 16);
1198 }
1199
d1600401 1200 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 1201
4861af80 1202 return res;
01ef7dbf
IM		 1203}
1204
1205/*
1206 * Write data through the vendor widget -- NOT protected by the Mutex!
1207 */
01ef7dbf
IM		 1208static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1209{
5aaca44d 1210 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1211 int res;
1212
1213 /* send low 16 bits of the data */
1214 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1215
1216 if (res != -EIO) {
1217 /* send high 16 bits of the data */
1218 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1219 data >> 16);
1220 }
1221
5aaca44d
IM		 1222 /*If no error encountered, automatically increment the address
1223 as per chip behaviour*/
1224 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1225 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1226 return res;
1227}
1228
d5c21b88
IM		 1229/*
1230 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1231 */
01ef7dbf
IM		 1232static int chipio_write_data_multiple(struct hda_codec *codec,
1233 const u32 *data,
1234 unsigned int count)
1235{
1236 int status = 0;
1237
1238 if (data == NULL) {
4e76a883 1239 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 1240 return -EINVAL;
1241 }
1242
1243 while ((count-- != 0) && (status == 0))
1244 status = chipio_write_data(codec, *data++);
1245
1246 return status;
1247}
1248
1249
1250/*
1251 * Read data through the vendor widget -- NOT protected by the Mutex!
1252 */
1253static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1254{
5aaca44d 1255 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1256 int res;
1257
1258 /* post read */
1259 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1260
1261 if (res != -EIO) {
1262 /* read status */
1263 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1264 }
1265
1266 if (res != -EIO) {
1267 /* read data */
1268 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1269 VENDOR_CHIPIO_HIC_READ_DATA,
1270 0);
1271 }
1272
5aaca44d
IM		 1273 /*If no error encountered, automatically increment the address
1274 as per chip behaviour*/
1275 spec->curr_chip_addx = (res != -EIO) ?
d1600401 1276 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 1277 return res;
1278}
1279
1280/*
1281 * Write given value to the given address through the chip I/O widget.
1282 * protected by the Mutex
1283 */
1284static int chipio_write(struct hda_codec *codec,
1285 unsigned int chip_addx, const unsigned int data)
1286{
1287 struct ca0132_spec *spec = codec->spec;
1288 int err;
1289
1290 mutex_lock(&spec->chipio_mutex);
1291
1292 /* write the address, and if successful proceed to write data */
1293 err = chipio_write_address(codec, chip_addx);
1294 if (err < 0)
1295 goto exit;
1296
1297 err = chipio_write_data(codec, data);
1298 if (err < 0)
1299 goto exit;
1300
1301exit:
1302 mutex_unlock(&spec->chipio_mutex);
1303 return err;
1304}
1305
38ba69ff
CM		 1306/*
1307 * Write given value to the given address through the chip I/O widget.
1308 * not protected by the Mutex
1309 */
1310static int chipio_write_no_mutex(struct hda_codec *codec,
1311 unsigned int chip_addx, const unsigned int data)
1312{
1313 int err;
1314
1315
1316 /* write the address, and if successful proceed to write data */
1317 err = chipio_write_address(codec, chip_addx);
1318 if (err < 0)
1319 goto exit;
1320
1321 err = chipio_write_data(codec, data);
1322 if (err < 0)
1323 goto exit;
1324
1325exit:
1326 return err;
1327}
1328
d5c21b88
IM		 1329/*
1330 * Write multiple values to the given address through the chip I/O widget.
1331 * protected by the Mutex
1332 */
01ef7dbf
IM		 1333static int chipio_write_multiple(struct hda_codec *codec,
1334 u32 chip_addx,
1335 const u32 *data,
1336 unsigned int count)
1337{
1338 struct ca0132_spec *spec = codec->spec;
1339 int status;
1340
1341 mutex_lock(&spec->chipio_mutex);
4861af80 1342 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 1343 if (status < 0)
1344 goto error;
1345
1346 status = chipio_write_data_multiple(codec, data, count);
1347error:
1348 mutex_unlock(&spec->chipio_mutex);
1349
1350 return status;
1351}
1352
1353/*
1354 * Read the given address through the chip I/O widget
1355 * protected by the Mutex
1356 */
1357static int chipio_read(struct hda_codec *codec,
1358 unsigned int chip_addx, unsigned int *data)
1359{
1360 struct ca0132_spec *spec = codec->spec;
1361 int err;
1362
1363 mutex_lock(&spec->chipio_mutex);
1364
1365 /* write the address, and if successful proceed to write data */
1366 err = chipio_write_address(codec, chip_addx);
1367 if (err < 0)
1368 goto exit;
1369
1370 err = chipio_read_data(codec, data);
1371 if (err < 0)
1372 goto exit;
1373
1374exit:
1375 mutex_unlock(&spec->chipio_mutex);
1376 return err;
1377}
1378
d5c21b88
IM		 1379/*
1380 * Set chip control flags through the chip I/O widget.
1381 */
01ef7dbf
IM		 1382static void chipio_set_control_flag(struct hda_codec *codec,
1383 enum control_flag_id flag_id,
1384 bool flag_state)
1385{
1386 unsigned int val;
1387 unsigned int flag_bit;
1388
1389 flag_bit = (flag_state ? 1 : 0);
1390 val = (flag_bit << 7) | (flag_id);
1391 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1392 VENDOR_CHIPIO_FLAG_SET, val);
1393}
1394
d5c21b88
IM		 1395/*
1396 * Set chip parameters through the chip I/O widget.
1397 */
01ef7dbf
IM		 1398static void chipio_set_control_param(struct hda_codec *codec,
1399 enum control_param_id param_id, int param_val)
1400{
1401 struct ca0132_spec *spec = codec->spec;
1402 int val;
1403
1404 if ((param_id < 32) && (param_val < 8)) {
1405 val = (param_val << 5) | (param_id);
1406 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1407 VENDOR_CHIPIO_PARAM_SET, val);
1408 } else {
1409 mutex_lock(&spec->chipio_mutex);
1410 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1411 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1412 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1413 param_id);
1414 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1415 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1416 param_val);
1417 }
1418 mutex_unlock(&spec->chipio_mutex);
1419 }
1420}
1421
009b8f97
CM		 1422/*
1423 * Set chip parameters through the chip I/O widget. NO MUTEX.
1424 */
1425static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1426 enum control_param_id param_id, int param_val)
1427{
1428 int val;
1429
1430 if ((param_id < 32) && (param_val < 8)) {
1431 val = (param_val << 5) | (param_id);
1432 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1433 VENDOR_CHIPIO_PARAM_SET, val);
1434 } else {
1435 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1436 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1437 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1438 param_id);
1439 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1440 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1441 param_val);
1442 }
1443 }
1444}
38ba69ff
CM		 1445/*
1446 * Connect stream to a source point, and then connect
1447 * that source point to a destination point.
1448 */
1449static void chipio_set_stream_source_dest(struct hda_codec *codec,
1450 int streamid, int source_point, int dest_point)
1451{
1452 chipio_set_control_param_no_mutex(codec,
1453 CONTROL_PARAM_STREAM_ID, streamid);
1454 chipio_set_control_param_no_mutex(codec,
1455 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1456 chipio_set_control_param_no_mutex(codec,
1457 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1458}
1459
1460/*
1461 * Set number of channels in the selected stream.
1462 */
1463static void chipio_set_stream_channels(struct hda_codec *codec,
1464 int streamid, unsigned int channels)
1465{
1466 chipio_set_control_param_no_mutex(codec,
1467 CONTROL_PARAM_STREAM_ID, streamid);
1468 chipio_set_control_param_no_mutex(codec,
1469 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1470}
009b8f97
CM		 1471
1472/*
1473 * Enable/Disable audio stream.
1474 */
1475static void chipio_set_stream_control(struct hda_codec *codec,
1476 int streamid, int enable)
1477{
1478 chipio_set_control_param_no_mutex(codec,
1479 CONTROL_PARAM_STREAM_ID, streamid);
1480 chipio_set_control_param_no_mutex(codec,
1481 CONTROL_PARAM_STREAM_CONTROL, enable);
1482}
1483
38ba69ff
CM		 1484
1485/*
1486 * Set sampling rate of the connection point. NO MUTEX.
1487 */
1488static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1489 int connid, enum ca0132_sample_rate rate)
1490{
1491 chipio_set_control_param_no_mutex(codec,
1492 CONTROL_PARAM_CONN_POINT_ID, connid);
1493 chipio_set_control_param_no_mutex(codec,
1494 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1495}
1496
d5c21b88
IM		 1497/*
1498 * Set sampling rate of the connection point.
1499 */
01ef7dbf
IM		 1500static void chipio_set_conn_rate(struct hda_codec *codec,
1501 int connid, enum ca0132_sample_rate rate)
1502{
1503 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1504 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1505 rate);
1506}
1507
b9b41345
CM		 1508/*
1509 * Writes to the 8051's internal address space directly instead of indirectly,
1510 * giving access to the special function registers located at addresses
1511 * 0x80-0xFF.
1512 */
1513static void chipio_8051_write_direct(struct hda_codec *codec,
1514 unsigned int addr, unsigned int data)
1515{
1516 unsigned int verb;
1517
1518 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1519 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1520}
1521
d5c21b88
IM		 1522/*
1523 * Enable clocks.
1524 */
01ef7dbf
IM		 1525static void chipio_enable_clocks(struct hda_codec *codec)
1526{
1527 struct ca0132_spec *spec = codec->spec;
1528
1529 mutex_lock(&spec->chipio_mutex);
1530 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1531 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1532 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1533 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1534 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1535 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1536 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1537 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1538 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1539 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1540 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1541 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1542 mutex_unlock(&spec->chipio_mutex);
1543}
1544
1545/*
1546 * CA0132 DSP IO stuffs
1547 */
1548static int dspio_send(struct hda_codec *codec, unsigned int reg,
1549 unsigned int data)
1550{
b645d796 1551 int res;
6d67530e 1552 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1553
1554 /* send bits of data specified by reg to dsp */
1555 do {
1556 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1557 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1558 return res;
6d67530e
IM		 1559 msleep(20);
1560 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1561
1562 return -EIO;
1563}
1564
d5c21b88
IM		 1565/*
1566 * Wait for DSP to be ready for commands
1567 */
01ef7dbf
IM		 1568static void dspio_write_wait(struct hda_codec *codec)
1569{
4861af80
IM		 1570 int status;
1571 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1572
01ef7dbf 1573 do {
4861af80
IM		 1574 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1575 VENDOR_DSPIO_STATUS, 0);
1576 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1577 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1578 break;
1579 msleep(1);
1580 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1581}
1582
d5c21b88
IM		 1583/*
1584 * Write SCP data to DSP
1585 */
01ef7dbf
IM		 1586static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1587{
1588 struct ca0132_spec *spec = codec->spec;
1589 int status;
1590
1591 dspio_write_wait(codec);
1592
1593 mutex_lock(&spec->chipio_mutex);
1594 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1595 scp_data & 0xffff);
1596 if (status < 0)
1597 goto error;
1598
1599 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1600 scp_data >> 16);
1601 if (status < 0)
1602 goto error;
1603
1604 /* OK, now check if the write itself has executed*/
1605 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1606 VENDOR_DSPIO_STATUS, 0);
1607error:
1608 mutex_unlock(&spec->chipio_mutex);
1609
1610 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1611 -EIO : 0;
1612}
1613
d5c21b88
IM		 1614/*
1615 * Write multiple SCP data to DSP
1616 */
01ef7dbf
IM		 1617static int dspio_write_multiple(struct hda_codec *codec,
1618 unsigned int *buffer, unsigned int size)
1619{
1620 int status = 0;
1621 unsigned int count;
1622
a16fbb85 1623 if (buffer == NULL)
01ef7dbf
IM		 1624 return -EINVAL;
1625
1626 count = 0;
1627 while (count < size) {
1628 status = dspio_write(codec, *buffer++);
1629 if (status != 0)
1630 break;
1631 count++;
1632 }
1633
1634 return status;
1635}
1636
a73d511c
IM		 1637static int dspio_read(struct hda_codec *codec, unsigned int *data)
1638{
1639 int status;
1640
1641 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1642 if (status == -EIO)
1643 return status;
1644
1645 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1646 if (status == -EIO ||
1647 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1648 return -EIO;
1649
1650 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1651 VENDOR_DSPIO_SCP_READ_DATA, 0);
1652
1653 return 0;
1654}
1655
1656static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1657 unsigned int *buf_size, unsigned int size_count)
1658{
1659 int status = 0;
1660 unsigned int size = *buf_size;
1661 unsigned int count;
1662 unsigned int skip_count;
1663 unsigned int dummy;
1664
a16fbb85 1665 if (buffer == NULL)
a73d511c
IM		 1666 return -1;
1667
1668 count = 0;
1669 while (count < size && count < size_count) {
1670 status = dspio_read(codec, buffer++);
1671 if (status != 0)
1672 break;
1673 count++;
1674 }
1675
1676 skip_count = count;
1677 if (status == 0) {
1678 while (skip_count < size) {
1679 status = dspio_read(codec, &dummy);
1680 if (status != 0)
1681 break;
1682 skip_count++;
1683 }
1684 }
1685 *buf_size = count;
1686
1687 return status;
1688}
1689
d5c21b88
IM		 1690/*
1691 * Construct the SCP header using corresponding fields
1692 */
01ef7dbf
IM		 1693static inline unsigned int
1694make_scp_header(unsigned int target_id, unsigned int source_id,
1695 unsigned int get_flag, unsigned int req,
1696 unsigned int device_flag, unsigned int resp_flag,
1697 unsigned int error_flag, unsigned int data_size)
1698{
1699 unsigned int header = 0;
1700
1701 header = (data_size & 0x1f) << 27;
1702 header |= (error_flag & 0x01) << 26;
1703 header |= (resp_flag & 0x01) << 25;
1704 header |= (device_flag & 0x01) << 24;
1705 header |= (req & 0x7f) << 17;
1706 header |= (get_flag & 0x01) << 16;
1707 header |= (source_id & 0xff) << 8;
1708 header |= target_id & 0xff;
1709
1710 return header;
1711}
1712
d5c21b88
IM		 1713/*
1714 * Extract corresponding fields from SCP header
1715 */
01ef7dbf
IM		 1716static inline void
1717extract_scp_header(unsigned int header,
1718 unsigned int *target_id, unsigned int *source_id,
1719 unsigned int *get_flag, unsigned int *req,
1720 unsigned int *device_flag, unsigned int *resp_flag,
1721 unsigned int *error_flag, unsigned int *data_size)
1722{
1723 if (data_size)
1724 *data_size = (header >> 27) & 0x1f;
1725 if (error_flag)
1726 *error_flag = (header >> 26) & 0x01;
1727 if (resp_flag)
1728 *resp_flag = (header >> 25) & 0x01;
1729 if (device_flag)
1730 *device_flag = (header >> 24) & 0x01;
1731 if (req)
1732 *req = (header >> 17) & 0x7f;
1733 if (get_flag)
1734 *get_flag = (header >> 16) & 0x01;
1735 if (source_id)
1736 *source_id = (header >> 8) & 0xff;
1737 if (target_id)
1738 *target_id = header & 0xff;
1739}
1740
1741#define SCP_MAX_DATA_WORDS (16)
1742
1743/* Structure to contain any SCP message */
1744struct scp_msg {
1745 unsigned int hdr;
1746 unsigned int data[SCP_MAX_DATA_WORDS];
1747};
1748
a73d511c
IM		 1749static void dspio_clear_response_queue(struct hda_codec *codec)
1750{
1751 unsigned int dummy = 0;
1752 int status = -1;
1753
1754 /* clear all from the response queue */
1755 do {
1756 status = dspio_read(codec, &dummy);
1757 } while (status == 0);
1758}
1759
1760static int dspio_get_response_data(struct hda_codec *codec)
1761{
1762 struct ca0132_spec *spec = codec->spec;
1763 unsigned int data = 0;
1764 unsigned int count;
1765
1766 if (dspio_read(codec, &data) < 0)
1767 return -EIO;
1768
1769 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1770 spec->scp_resp_header = data;
1771 spec->scp_resp_count = data >> 27;
1772 count = spec->wait_num_data;
1773 dspio_read_multiple(codec, spec->scp_resp_data,
1774 &spec->scp_resp_count, count);
1775 return 0;
1776 }
1777
1778 return -EIO;
1779}
1780
d5c21b88
IM		 1781/*
1782 * Send SCP message to DSP
1783 */
01ef7dbf
IM		 1784static int dspio_send_scp_message(struct hda_codec *codec,
1785 unsigned char *send_buf,
1786 unsigned int send_buf_size,
1787 unsigned char *return_buf,
1788 unsigned int return_buf_size,
1789 unsigned int *bytes_returned)
1790{
1791 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1792 int status = -1;
1793 unsigned int scp_send_size = 0;
1794 unsigned int total_size;
1795 bool waiting_for_resp = false;
1796 unsigned int header;
1797 struct scp_msg *ret_msg;
1798 unsigned int resp_src_id, resp_target_id;
1799 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1800
1801 if (bytes_returned)
1802 *bytes_returned = 0;
1803
1804 /* get scp header from buffer */
1805 header = *((unsigned int *)send_buf);
1806 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1807 &device_flag, NULL, NULL, &data_size);
1808 scp_send_size = data_size + 1;
1809 total_size = (scp_send_size * 4);
1810
1811 if (send_buf_size < total_size)
1812 return -EINVAL;
1813
1814 if (get_flag || device_flag) {
1815 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1816 return -EINVAL;
1817
1818 spec->wait_scp_header = *((unsigned int *)send_buf);
1819
1820 /* swap source id with target id */
1821 resp_target_id = src_id;
1822 resp_src_id = target_id;
1823 spec->wait_scp_header &= 0xffff0000;
1824 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1825 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1826 spec->wait_scp = 1;
1827 waiting_for_resp = true;
1828 }
1829
1830 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1831 scp_send_size);
1832 if (status < 0) {
1833 spec->wait_scp = 0;
1834 return status;
1835 }
1836
1837 if (waiting_for_resp) {
6d67530e 1838 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1839 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1840 do {
1841 msleep(20);
6d67530e 1842 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1843 waiting_for_resp = false;
6d67530e 1844 if (!spec->wait_scp) {
01ef7dbf
IM		 1845 ret_msg = (struct scp_msg *)return_buf;
1846 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1847 memcpy(&ret_msg->data, spec->scp_resp_data,
1848 spec->wait_num_data);
1849 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1850 status = 0;
1851 } else {
1852 status = -EIO;
1853 }
1854 spec->wait_scp = 0;
1855 }
1856
1857 return status;
1858}
1859
d5c21b88
IM		 1860/**
1861 * Prepare and send the SCP message to DSP
1862 * @codec: the HDA codec
1863 * @mod_id: ID of the DSP module to send the command
1864 * @req: ID of request to send to the DSP module
1865 * @dir: SET or GET
1866 * @data: pointer to the data to send with the request, request specific
1867 * @len: length of the data, in bytes
1868 * @reply: point to the buffer to hold data returned for a reply
1869 * @reply_len: length of the reply buffer returned from GET
1870 *
1871 * Returns zero or a negative error code.
1872 */
01ef7dbf 1873static int dspio_scp(struct hda_codec *codec,
447fd8e9
CM		 1874 int mod_id, int src_id, int req, int dir, const void *data,
1875 unsigned int len, void *reply, unsigned int *reply_len)
01ef7dbf
IM		 1876{
1877 int status = 0;
1878 struct scp_msg scp_send, scp_reply;
1879 unsigned int ret_bytes, send_size, ret_size;
1880 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1881 unsigned int reply_data_size;
1882
1883 memset(&scp_send, 0, sizeof(scp_send));
1884 memset(&scp_reply, 0, sizeof(scp_reply));
1885
1886 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1887 return -EINVAL;
1888
1889 if (dir == SCP_GET && reply == NULL) {
4e76a883 1890 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1891 return -EINVAL;
1892 }
1893
1894 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1895 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1896 return -EINVAL;
1897 }
1898
447fd8e9 1899 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
01ef7dbf
IM		 1900 0, 0, 0, len/sizeof(unsigned int));
1901 if (data != NULL && len > 0) {
1902 len = min((unsigned int)(sizeof(scp_send.data)), len);
1903 memcpy(scp_send.data, data, len);
1904 }
1905
1906 ret_bytes = 0;
1907 send_size = sizeof(unsigned int) + len;
1908 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1909 send_size, (unsigned char *)&scp_reply,
1910 sizeof(scp_reply), &ret_bytes);
1911
1912 if (status < 0) {
4e76a883 1913 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1914 return status;
1915 }
1916
1917 /* extract send and reply headers members */
1918 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1919 NULL, NULL, NULL, NULL, NULL);
1920 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1921 &reply_resp_flag, &reply_error_flag,
1922 &reply_data_size);
1923
1924 if (!send_get_flag)
1925 return 0;
1926
1927 if (reply_resp_flag && !reply_error_flag) {
1928 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1929 / sizeof(unsigned int);
1930
1931 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1932 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1933 return -EINVAL;
1934 } else if (ret_size != reply_data_size) {
4e76a883 1935 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1936 return -EINVAL;
46a049da
AB		 1937 } else if (!reply) {
1938 codec_dbg(codec, "NULL reply\n");
1939 return -EINVAL;
01ef7dbf
IM		 1940 } else {
1941 *reply_len = ret_size*sizeof(unsigned int);
1942 memcpy(reply, scp_reply.data, *reply_len);
1943 }
1944 } else {
4e76a883 1945 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 1946 return -EIO;
1947 }
1948
1949 return status;
1950}
1951
5aaca44d
IM		 1952/*
1953 * Set DSP parameters
1954 */
1955static int dspio_set_param(struct hda_codec *codec, int mod_id,
447fd8e9 1956 int src_id, int req, const void *data, unsigned int len)
5aaca44d 1957{
447fd8e9
CM		 1958 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
1959 NULL);
5aaca44d
IM		 1960}
1961
1962static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
447fd8e9 1963 int req, const unsigned int data)
5aaca44d 1964{
447fd8e9
CM		 1965 return dspio_set_param(codec, mod_id, 0x20, req, &data,
1966 sizeof(unsigned int));
1967}
1968
1969static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
1970 int req, const unsigned int data)
1971{
1972 return dspio_set_param(codec, mod_id, 0x00, req, &data,
1973 sizeof(unsigned int));
5aaca44d
IM		 1974}
1975
d5c21b88
IM		 1976/*
1977 * Allocate a DSP DMA channel via an SCP message
1978 */
01ef7dbf
IM		 1979static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1980{
1981 int status = 0;
1982 unsigned int size = sizeof(dma_chan);
1983
4e76a883 1984 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
447fd8e9
CM		 1985 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1986 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
1987 dma_chan, &size);
01ef7dbf
IM		 1988
1989 if (status < 0) {
4e76a883 1990 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1991 return status;
1992 }
1993
1994 if ((*dma_chan + 1) == 0) {
4e76a883 1995 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 1996 return -EBUSY;
1997 }
1998
4e76a883
TI		 1999 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2000 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 2001
2002 return status;
2003}
2004
d5c21b88
IM		 2005/*
2006 * Free a DSP DMA via an SCP message
2007 */
01ef7dbf
IM		 2008static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2009{
2010 int status = 0;
2011 unsigned int dummy = 0;
2012
4e76a883
TI		 2013 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2014 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf 2015
447fd8e9
CM		 2016 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2017 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2018 sizeof(dma_chan), NULL, &dummy);
01ef7dbf
IM		 2019
2020 if (status < 0) {
4e76a883 2021 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 2022 return status;
2023 }
2024
4e76a883 2025 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 2026
2027 return status;
2028}
2029
2030/*
d5c21b88 2031 * (Re)start the DSP
01ef7dbf
IM		 2032 */
2033static int dsp_set_run_state(struct hda_codec *codec)
2034{
2035 unsigned int dbg_ctrl_reg;
2036 unsigned int halt_state;
2037 int err;
2038
2039 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2040 if (err < 0)
2041 return err;
2042
2043 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2044 DSP_DBGCNTL_STATE_LOBIT;
2045
2046 if (halt_state != 0) {
2047 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2048 DSP_DBGCNTL_SS_MASK);
2049 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2050 dbg_ctrl_reg);
2051 if (err < 0)
2052 return err;
2053
2054 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2055 DSP_DBGCNTL_EXEC_MASK;
2056 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2057 dbg_ctrl_reg);
2058 if (err < 0)
2059 return err;
2060 }
2061
2062 return 0;
2063}
2064
d5c21b88
IM		 2065/*
2066 * Reset the DSP
2067 */
01ef7dbf
IM		 2068static int dsp_reset(struct hda_codec *codec)
2069{
2070 unsigned int res;
2071 int retry = 20;
2072
4e76a883 2073 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 2074 do {
2075 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2076 retry--;
2077 } while (res == -EIO && retry);
2078
2079 if (!retry) {
4e76a883 2080 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 2081 return -EIO;
2082 }
2083
2084 return 0;
2085}
2086
d5c21b88
IM		 2087/*
2088 * Convert chip address to DSP address
2089 */
01ef7dbf
IM		 2090static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2091 bool *code, bool *yram)
2092{
2093 *code = *yram = false;
2094
2095 if (UC_RANGE(chip_addx, 1)) {
2096 *code = true;
2097 return UC_OFF(chip_addx);
2098 } else if (X_RANGE_ALL(chip_addx, 1)) {
2099 return X_OFF(chip_addx);
2100 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2101 *yram = true;
2102 return Y_OFF(chip_addx);
2103 }
2104
4a8b89f9 2105 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 2106}
2107
d5c21b88
IM		 2108/*
2109 * Check if the DSP DMA is active
2110 */
01ef7dbf
IM		 2111static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2112{
2113 unsigned int dma_chnlstart_reg;
2114
2115 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2116
2117 return ((dma_chnlstart_reg & (1 <<
2118 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2119}
2120
2121static int dsp_dma_setup_common(struct hda_codec *codec,
2122 unsigned int chip_addx,
2123 unsigned int dma_chan,
2124 unsigned int port_map_mask,
2125 bool ovly)
2126{
2127 int status = 0;
2128 unsigned int chnl_prop;
2129 unsigned int dsp_addx;
2130 unsigned int active;
2131 bool code, yram;
2132
4e76a883 2133 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 2134
2135 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 2136 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 2137 return -EINVAL;
2138 }
2139
2140 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2141 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 2142 return -EBUSY;
2143 }
2144
2145 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2146
2147 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2148 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2149 return -ENXIO;
2150 }
2151
2152 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2153 active = 0;
2154
4e76a883 2155 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 2156
2157 if (ovly) {
2158 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2159 &chnl_prop);
2160
2161 if (status < 0) {
4e76a883 2162 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 2163 return status;
2164 }
4e76a883 2165 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 2166 }
2167
2168 if (!code)
2169 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2170 else
2171 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2172
2173 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2174
2175 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2176 if (status < 0) {
4e76a883 2177 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 2178 return status;
2179 }
4e76a883 2180 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 2181
2182 if (ovly) {
2183 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2184 &active);
2185
2186 if (status < 0) {
4e76a883 2187 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 2188 return status;
2189 }
4e76a883 2190 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 2191 }
2192
2193 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2194 DSPDMAC_ACTIVE_AAR_MASK;
2195
2196 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2197 if (status < 0) {
4e76a883 2198 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 2199 return status;
2200 }
2201
4e76a883 2202 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 2203
2204 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2205 port_map_mask);
2206 if (status < 0) {
4e76a883 2207 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 2208 return status;
2209 }
4e76a883 2210 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 2211
2212 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2213 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2214 if (status < 0) {
4e76a883 2215 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 2216 return status;
2217 }
4e76a883 2218 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 2219
4e76a883 2220 codec_dbg(codec,
01ef7dbf
IM		 2221 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2222 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2223 chip_addx, dsp_addx, dma_chan,
2224 port_map_mask, chnl_prop, active);
2225
4e76a883 2226 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 2227
2228 return 0;
2229}
2230
d5c21b88
IM		 2231/*
2232 * Setup the DSP DMA per-transfer-specific registers
2233 */
01ef7dbf
IM		 2234static int dsp_dma_setup(struct hda_codec *codec,
2235 unsigned int chip_addx,
2236 unsigned int count,
2237 unsigned int dma_chan)
2238{
2239 int status = 0;
2240 bool code, yram;
2241 unsigned int dsp_addx;
2242 unsigned int addr_field;
2243 unsigned int incr_field;
2244 unsigned int base_cnt;
2245 unsigned int cur_cnt;
2246 unsigned int dma_cfg = 0;
2247 unsigned int adr_ofs = 0;
2248 unsigned int xfr_cnt = 0;
2249 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2250 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2251
4e76a883 2252 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 2253
2254 if (count > max_dma_count) {
4e76a883 2255 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 2256 return -EINVAL;
2257 }
2258
2259 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2260 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 2261 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 2262 return -ENXIO;
2263 }
2264
4e76a883 2265 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 2266
2267 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2268 incr_field = 0;
2269
2270 if (!code) {
2271 addr_field <<= 1;
2272 if (yram)
2273 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2274
2275 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2276 }
2277
2278 dma_cfg = addr_field + incr_field;
2279 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2280 dma_cfg);
2281 if (status < 0) {
4e76a883 2282 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 2283 return status;
2284 }
4e76a883 2285 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 2286
2287 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2288 (code ? 0 : 1));
2289
2290 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2291 adr_ofs);
2292 if (status < 0) {
4e76a883 2293 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 2294 return status;
2295 }
4e76a883 2296 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 2297
2298 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2299
2300 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2301
2302 xfr_cnt = base_cnt | cur_cnt;
2303
2304 status = chipio_write(codec,
2305 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2306 if (status < 0) {
4e76a883 2307 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 2308 return status;
2309 }
4e76a883 2310 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 2311
4e76a883 2312 codec_dbg(codec,
01ef7dbf
IM		 2313 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2314 "ADROFS=0x%x, XFRCNT=0x%x\n",
2315 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2316
4e76a883 2317 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 2318
2319 return 0;
2320}
2321
d5c21b88
IM		 2322/*
2323 * Start the DSP DMA
2324 */
01ef7dbf
IM		 2325static int dsp_dma_start(struct hda_codec *codec,
2326 unsigned int dma_chan, bool ovly)
2327{
2328 unsigned int reg = 0;
2329 int status = 0;
2330
4e76a883 2331 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 2332
2333 if (ovly) {
2334 status = chipio_read(codec,
2335 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2336
2337 if (status < 0) {
4e76a883 2338 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2339 return status;
2340 }
4e76a883 2341 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 2342
2343 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2344 DSPDMAC_CHNLSTART_DIS_MASK);
2345 }
2346
2347 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2348 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2349 if (status < 0) {
4e76a883 2350 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2351 return status;
2352 }
4e76a883 2353 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 2354
2355 return status;
2356}
2357
d5c21b88
IM		 2358/*
2359 * Stop the DSP DMA
2360 */
01ef7dbf
IM		 2361static int dsp_dma_stop(struct hda_codec *codec,
2362 unsigned int dma_chan, bool ovly)
2363{
2364 unsigned int reg = 0;
2365 int status = 0;
2366
4e76a883 2367 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 2368
2369 if (ovly) {
2370 status = chipio_read(codec,
2371 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2372
2373 if (status < 0) {
4e76a883 2374 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 2375 return status;
2376 }
4e76a883 2377 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 2378 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2379 DSPDMAC_CHNLSTART_DIS_MASK);
2380 }
2381
2382 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2383 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2384 if (status < 0) {
4e76a883 2385 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 2386 return status;
2387 }
4e76a883 2388 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 2389
2390 return status;
2391}
2392
d5c21b88
IM		 2393/**
2394 * Allocate router ports
2395 *
2396 * @codec: the HDA codec
2397 * @num_chans: number of channels in the stream
2398 * @ports_per_channel: number of ports per channel
2399 * @start_device: start device
2400 * @port_map: pointer to the port list to hold the allocated ports
2401 *
2402 * Returns zero or a negative error code.
2403 */
01ef7dbf
IM		 2404static int dsp_allocate_router_ports(struct hda_codec *codec,
2405 unsigned int num_chans,
2406 unsigned int ports_per_channel,
2407 unsigned int start_device,
2408 unsigned int *port_map)
2409{
2410 int status = 0;
2411 int res;
2412 u8 val;
2413
2414 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2415 if (status < 0)
2416 return status;
2417
2418 val = start_device << 6;
2419 val |= (ports_per_channel - 1) << 4;
2420 val |= num_chans - 1;
2421
2422 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2423 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2424 val);
2425
2426 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2427 VENDOR_CHIPIO_PORT_ALLOC_SET,
2428 MEM_CONNID_DSP);
2429
2430 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2431 if (status < 0)
2432 return status;
2433
2434 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2435 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2436
2437 *port_map = res;
2438
2439 return (res < 0) ? res : 0;
2440}
2441
d5c21b88
IM		 2442/*
2443 * Free router ports
2444 */
01ef7dbf
IM		 2445static int dsp_free_router_ports(struct hda_codec *codec)
2446{
2447 int status = 0;
2448
2449 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2450 if (status < 0)
2451 return status;
2452
2453 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2454 VENDOR_CHIPIO_PORT_FREE_SET,
2455 MEM_CONNID_DSP);
2456
2457 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2458
2459 return status;
2460}
2461
d5c21b88
IM		 2462/*
2463 * Allocate DSP ports for the download stream
2464 */
01ef7dbf
IM		 2465static int dsp_allocate_ports(struct hda_codec *codec,
2466 unsigned int num_chans,
2467 unsigned int rate_multi, unsigned int *port_map)
2468{
2469 int status;
2470
4e76a883 2471 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2472
2473 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2474 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2475 return -EINVAL;
2476 }
2477
2478 status = dsp_allocate_router_ports(codec, num_chans,
2479 rate_multi, 0, port_map);
2480
4e76a883 2481 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2482
2483 return status;
2484}
2485
01ef7dbf
IM		 2486static int dsp_allocate_ports_format(struct hda_codec *codec,
2487 const unsigned short fmt,
2488 unsigned int *port_map)
2489{
2490 int status;
2491 unsigned int num_chans;
2492
2493 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2494 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2495 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2496
2497 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2498 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2499 return -EINVAL;
2500 }
2501
2502 num_chans = get_hdafmt_chs(fmt) + 1;
2503
2504 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2505
2506 return status;
2507}
2508
d5c21b88
IM		 2509/*
2510 * free DSP ports
2511 */
2512static int dsp_free_ports(struct hda_codec *codec)
2513{
2514 int status;
2515
4e76a883 2516 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2517
2518 status = dsp_free_router_ports(codec);
2519 if (status < 0) {
4e76a883 2520 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2521 return status;
2522 }
4e76a883 2523 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2524
2525 return status;
2526}
2527
01ef7dbf
IM		 2528/*
2529 * HDA DMA engine stuffs for DSP code download
2530 */
2531struct dma_engine {
2532 struct hda_codec *codec;
2533 unsigned short m_converter_format;
2534 struct snd_dma_buffer *dmab;
2535 unsigned int buf_size;
2536};
2537
2538
2539enum dma_state {
2540 DMA_STATE_STOP = 0,
2541 DMA_STATE_RUN = 1
2542};
2543
6194b99d 2544static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2545 unsigned int sample_rate,
2546 unsigned short channels,
01ef7dbf
IM		 2547 unsigned short *hda_format)
2548{
2549 unsigned int format_val;
2550
b7d023e1
TI		 2551 format_val = snd_hdac_calc_stream_format(sample_rate,
2552 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2553
2554 if (hda_format)
2555 *hda_format = (unsigned short)format_val;
2556
2557 return 0;
2558}
2559
d5c21b88
IM		 2560/*
2561 * Reset DMA for DSP download
2562 */
01ef7dbf
IM		 2563static int dma_reset(struct dma_engine *dma)
2564{
2565 struct hda_codec *codec = dma->codec;
2566 struct ca0132_spec *spec = codec->spec;
2567 int status;
2568
b3667bd7 2569 if (dma->dmab->area)
01ef7dbf
IM		 2570 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2571
2572 status = snd_hda_codec_load_dsp_prepare(codec,
2573 dma->m_converter_format,
2574 dma->buf_size,
2575 dma->dmab);
2576 if (status < 0)
2577 return status;
2578 spec->dsp_stream_id = status;
2579 return 0;
2580}
2581
2582static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2583{
01ef7dbf
IM		 2584 bool cmd;
2585
01ef7dbf
IM		 2586 switch (state) {
2587 case DMA_STATE_STOP:
2588 cmd = false;
2589 break;
2590 case DMA_STATE_RUN:
2591 cmd = true;
2592 break;
2593 default:
c41999a2
DH		 2594 return 0;
2595 }
01ef7dbf
IM		 2596
2597 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2598 return 0;
95c6e9cb
IM		 2599}
2600
01ef7dbf
IM		 2601static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2602{
2603 return dma->dmab->bytes;
2604}
95c6e9cb 2605
01ef7dbf
IM		 2606static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2607{
2608 return dma->dmab->area;
2609}
95c6e9cb 2610
01ef7dbf
IM		 2611static int dma_xfer(struct dma_engine *dma,
2612 const unsigned int *data,
2613 unsigned int count)
2614{
2615 memcpy(dma->dmab->area, data, count);
2616 return 0;
2617}
95c6e9cb 2618
01ef7dbf
IM		 2619static void dma_get_converter_format(
2620 struct dma_engine *dma,
2621 unsigned short *format)
2622{
2623 if (format)
2624 *format = dma->m_converter_format;
2625}
95c6e9cb 2626
01ef7dbf 2627static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2628{
01ef7dbf 2629 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2630
01ef7dbf 2631 return spec->dsp_stream_id;
95c6e9cb
IM		 2632}
2633
01ef7dbf
IM		 2634struct dsp_image_seg {
2635 u32 magic;
2636 u32 chip_addr;
2637 u32 count;
2638 u32 data[0];
2639};
2640
2641static const u32 g_magic_value = 0x4c46584d;
2642static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2643
2644static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2645{
01ef7dbf
IM		 2646 return p->magic == g_magic_value;
2647}
95c6e9cb 2648
01ef7dbf
IM		 2649static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2650{
2651 return g_chip_addr_magic_value == p->chip_addr;
2652}
95c6e9cb 2653
01ef7dbf
IM		 2654static bool is_last(const struct dsp_image_seg *p)
2655{
2656 return p->count == 0;
2657}
95c6e9cb 2658
01ef7dbf
IM		 2659static size_t dsp_sizeof(const struct dsp_image_seg *p)
2660{
2661 return sizeof(*p) + p->count*sizeof(u32);
2662}
2663
2664static const struct dsp_image_seg *get_next_seg_ptr(
2665 const struct dsp_image_seg *p)
2666{
2667 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2668}
2669
2670/*
01ef7dbf 2671 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2672 */
8ae3124b 2673#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2674
d5c21b88
IM		 2675/*
2676 * Program a list of address/data pairs via the ChipIO widget.
2677 * The segment data is in the format of successive pairs of words.
2678 * These are repeated as indicated by the segment's count field.
2679 */
01ef7dbf
IM		 2680static int dspxfr_hci_write(struct hda_codec *codec,
2681 const struct dsp_image_seg *fls)
95c6e9cb 2682{
01ef7dbf
IM		 2683 int status;
2684 const u32 *data;
2685 unsigned int count;
95c6e9cb 2686
01ef7dbf 2687 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2688 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2689 return -EINVAL;
95c6e9cb
IM		 2690 }
2691
01ef7dbf
IM		 2692 count = fls->count;
2693 data = (u32 *)(fls->data);
2694 while (count >= 2) {
2695 status = chipio_write(codec, data[0], data[1]);
2696 if (status < 0) {
4e76a883 2697 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2698 return status;
2699 }
2700 count -= 2;
2701 data += 2;
2702 }
2703 return 0;
95c6e9cb
IM		 2704}
2705
d5c21b88
IM		 2706/**
2707 * Write a block of data into DSP code or data RAM using pre-allocated
2708 * DMA engine.
2709 *
2710 * @codec: the HDA codec
2711 * @fls: pointer to a fast load image
2712 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2713 * no relocation
2714 * @dma_engine: pointer to DMA engine to be used for DSP download
2715 * @dma_chan: The number of DMA channels used for DSP download
2716 * @port_map_mask: port mapping
2717 * @ovly: TRUE if overlay format is required
2718 *
2719 * Returns zero or a negative error code.
2720 */
01ef7dbf
IM		 2721static int dspxfr_one_seg(struct hda_codec *codec,
2722 const struct dsp_image_seg *fls,
2723 unsigned int reloc,
2724 struct dma_engine *dma_engine,
2725 unsigned int dma_chan,
2726 unsigned int port_map_mask,
2727 bool ovly)
95c6e9cb 2728{
406261ce 2729 int status = 0;
01ef7dbf
IM		 2730 bool comm_dma_setup_done = false;
2731 const unsigned int *data;
2732 unsigned int chip_addx;
2733 unsigned int words_to_write;
2734 unsigned int buffer_size_words;
2735 unsigned char *buffer_addx;
2736 unsigned short hda_format;
2737 unsigned int sample_rate_div;
2738 unsigned int sample_rate_mul;
2739 unsigned int num_chans;
2740 unsigned int hda_frame_size_words;
2741 unsigned int remainder_words;
2742 const u32 *data_remainder;
2743 u32 chip_addx_remainder;
2744 unsigned int run_size_words;
2745 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2746 unsigned long timeout;
2747 bool dma_active;
01ef7dbf
IM		 2748
2749 if (fls == NULL)
2750 return -EINVAL;
2751 if (is_hci_prog_list_seg(fls)) {
2752 hci_write = fls;
2753 fls = get_next_seg_ptr(fls);
2754 }
95c6e9cb 2755
01ef7dbf 2756 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2757 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2758 return dspxfr_hci_write(codec, hci_write);
2759 }
95c6e9cb 2760
01ef7dbf 2761 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2762 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2763 return -EINVAL;
95c6e9cb
IM		 2764 }
2765
01ef7dbf
IM		 2766 data = fls->data;
2767 chip_addx = fls->chip_addr,
2768 words_to_write = fls->count;
2769
2770 if (!words_to_write)
2771 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2772 if (reloc)
2773 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2774
2775 if (!UC_RANGE(chip_addx, words_to_write) &&
2776 !X_RANGE_ALL(chip_addx, words_to_write) &&
2777 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2778 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2779 return -EINVAL;
95c6e9cb
IM		 2780 }
2781
01ef7dbf
IM		 2782 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2783 sizeof(u32);
2784
2785 buffer_addx = dma_get_buffer_addr(dma_engine);
2786
2787 if (buffer_addx == NULL) {
4e76a883 2788 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2789 return -EINVAL;
2790 }
2791
2792 dma_get_converter_format(dma_engine, &hda_format);
2793 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2794 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2795 num_chans = get_hdafmt_chs(hda_format) + 1;
2796
2797 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2798 (num_chans * sample_rate_mul / sample_rate_div));
2799
3bc085a1 2800 if (hda_frame_size_words == 0) {
4e76a883 2801 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2802 return -EINVAL;
2803 }
2804
01ef7dbf
IM		 2805 buffer_size_words = min(buffer_size_words,
2806 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2807 65536 : 32768));
2808 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2809 codec_dbg(codec,
01ef7dbf
IM		 2810 "chpadr=0x%08x frmsz=%u nchan=%u "
2811 "rate_mul=%u div=%u bufsz=%u\n",
2812 chip_addx, hda_frame_size_words, num_chans,
2813 sample_rate_mul, sample_rate_div, buffer_size_words);
2814
3bc085a1 2815 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2816 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2817 return -EINVAL;
2818 }
2819
2820 remainder_words = words_to_write % hda_frame_size_words;
2821 data_remainder = data;
2822 chip_addx_remainder = chip_addx;
2823
2824 data += remainder_words;
2825 chip_addx += remainder_words*sizeof(u32);
2826 words_to_write -= remainder_words;
2827
2828 while (words_to_write != 0) {
2829 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2830 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2831 words_to_write, run_size_words, remainder_words);
2832 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2833 if (!comm_dma_setup_done) {
2834 status = dsp_dma_stop(codec, dma_chan, ovly);
2835 if (status < 0)
425a7880 2836 return status;
01ef7dbf
IM		 2837 status = dsp_dma_setup_common(codec, chip_addx,
2838 dma_chan, port_map_mask, ovly);
2839 if (status < 0)
2840 return status;
2841 comm_dma_setup_done = true;
2842 }
2843
2844 status = dsp_dma_setup(codec, chip_addx,
2845 run_size_words, dma_chan);
2846 if (status < 0)
2847 return status;
2848 status = dsp_dma_start(codec, dma_chan, ovly);
2849 if (status < 0)
2850 return status;
2851 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2852 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2853 return -EIO;
2854 }
2855 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2856 if (status < 0)
2857 return status;
2858 if (remainder_words != 0) {
2859 status = chipio_write_multiple(codec,
2860 chip_addx_remainder,
2861 data_remainder,
2862 remainder_words);
b3667bd7
TI		 2863 if (status < 0)
2864 return status;
01ef7dbf
IM		 2865 remainder_words = 0;
2866 }
2867 if (hci_write) {
2868 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2869 if (status < 0)
2870 return status;
01ef7dbf
IM		 2871 hci_write = NULL;
2872 }
6d67530e
IM		 2873
2874 timeout = jiffies + msecs_to_jiffies(2000);
2875 do {
2876 dma_active = dsp_is_dma_active(codec, dma_chan);
2877 if (!dma_active)
01ef7dbf 2878 break;
6d67530e
IM		 2879 msleep(20);
2880 } while (time_before(jiffies, timeout));
2881 if (dma_active)
2882 break;
2883
4e76a883 2884 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2885 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2886 status = dma_reset(dma_engine);
01ef7dbf
IM		 2887
2888 if (status < 0)
2889 return status;
2890
2891 data += run_size_words;
2892 chip_addx += run_size_words*sizeof(u32);
2893 words_to_write -= run_size_words;
2894 }
2895
2896 if (remainder_words != 0) {
2897 status = chipio_write_multiple(codec, chip_addx_remainder,
2898 data_remainder, remainder_words);
2899 }
2900
2901 return status;
95c6e9cb
IM		 2902}
2903
d5c21b88
IM		 2904/**
2905 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2906 *
2907 * @codec: the HDA codec
2908 * @fls_data: pointer to a fast load image
2909 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2910 * no relocation
e97249dd 2911 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2912 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2913 * @ovly: TRUE if overlay format is required
2914 *
2915 * Returns zero or a negative error code.
2916 */
01ef7dbf
IM		 2917static int dspxfr_image(struct hda_codec *codec,
2918 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2919 unsigned int reloc,
2920 unsigned int sample_rate,
2921 unsigned short channels,
01ef7dbf 2922 bool ovly)
95c6e9cb
IM		 2923{
2924 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2925 int status;
2926 unsigned short hda_format = 0;
2927 unsigned int response;
2928 unsigned char stream_id = 0;
2929 struct dma_engine *dma_engine;
2930 unsigned int dma_chan;
2931 unsigned int port_map_mask;
2932
2933 if (fls_data == NULL)
2934 return -EINVAL;
2935
2936 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2937 if (!dma_engine)
2938 return -ENOMEM;
95c6e9cb 2939
01ef7dbf
IM		 2940 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2941 if (!dma_engine->dmab) {
549e8292
TI		 2942 kfree(dma_engine);
2943 return -ENOMEM;
01ef7dbf 2944 }
95c6e9cb 2945
01ef7dbf 2946 dma_engine->codec = codec;
6194b99d 2947 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 2948 dma_engine->m_converter_format = hda_format;
2949 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2950 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2951
8ae3124b 2952 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2953
2954 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2955 hda_format, &response);
2956
2957 if (status < 0) {
4e76a883 2958 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 2959 goto exit;
2960 }
2961
2962 status = snd_hda_codec_load_dsp_prepare(codec,
2963 dma_engine->m_converter_format,
2964 dma_engine->buf_size,
2965 dma_engine->dmab);
2966 if (status < 0)
95c6e9cb 2967 goto exit;
01ef7dbf
IM		 2968 spec->dsp_stream_id = status;
2969
2970 if (ovly) {
2971 status = dspio_alloc_dma_chan(codec, &dma_chan);
2972 if (status < 0) {
4e76a883 2973 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 2974 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 2975 goto exit;
2976 }
2977 }
95c6e9cb 2978
01ef7dbf
IM		 2979 port_map_mask = 0;
2980 status = dsp_allocate_ports_format(codec, hda_format,
2981 &port_map_mask);
2982 if (status < 0) {
4e76a883 2983 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 2984 goto exit;
2985 }
2986
2987 stream_id = dma_get_stream_id(dma_engine);
2988 status = codec_set_converter_stream_channel(codec,
2989 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2990 if (status < 0) {
4e76a883 2991 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 2992 goto exit;
2993 }
2994
2995 while ((fls_data != NULL) && !is_last(fls_data)) {
2996 if (!is_valid(fls_data)) {
4e76a883 2997 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 2998 status = -EINVAL;
2999 goto exit;
3000 }
3001 status = dspxfr_one_seg(codec, fls_data, reloc,
3002 dma_engine, dma_chan,
3003 port_map_mask, ovly);
3004 if (status < 0)
3005 break;
3006
3007 if (is_hci_prog_list_seg(fls_data))
3008 fls_data = get_next_seg_ptr(fls_data);
3009
3010 if ((fls_data != NULL) && !is_last(fls_data))
3011 fls_data = get_next_seg_ptr(fls_data);
3012 }
3013
3014 if (port_map_mask != 0)
3015 status = dsp_free_ports(codec);
3016
3017 if (status < 0)
95c6e9cb
IM		 3018 goto exit;
3019
01ef7dbf
IM		 3020 status = codec_set_converter_stream_channel(codec,
3021 WIDGET_CHIP_CTRL, 0, 0, &response);
3022
95c6e9cb 3023exit:
01ef7dbf
IM		 3024 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3025 dspio_free_dma_chan(codec, dma_chan);
3026
b3667bd7 3027 if (dma_engine->dmab->area)
01ef7dbf
IM		 3028 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3029 kfree(dma_engine->dmab);
3030 kfree(dma_engine);
3031
3032 return status;
95c6e9cb
IM		 3033}
3034
3035/*
01ef7dbf 3036 * CA0132 DSP download stuffs.
95c6e9cb 3037 */
01ef7dbf 3038static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 3039{
009b8f97 3040 struct ca0132_spec *spec = codec->spec;
4e76a883 3041 codec_dbg(codec, "---- dspload_post_setup ------\n");
009b8f97
CM		 3042 if (!spec->use_alt_functions) {
3043 /*set DSP speaker to 2.0 configuration*/
3044 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3045 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 3046
009b8f97
CM		 3047 /*update write pointer*/
3048 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3049 }
01ef7dbf 3050}
95c6e9cb 3051
d5c21b88 3052/**
e60b2c7f 3053 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 3054 *
3055 * @codec: the HDA codec
3056 * @fls: pointer to a fast load image
3057 * @ovly: TRUE if overlay format is required
3058 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3059 * no relocation
3060 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3061 * @router_chans: number of audio router channels to be allocated (0 means use
3062 * internal defaults; max is 32)
3063 *
e60b2c7f
TI		 3064 * Download DSP from a DSP Image Fast Load structure. This structure is a
3065 * linear, non-constant sized element array of structures, each of which
3066 * contain the count of the data to be loaded, the data itself, and the
3067 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 3068 * Returns zero or a negative error code.
3069 */
01ef7dbf
IM		 3070static int dspload_image(struct hda_codec *codec,
3071 const struct dsp_image_seg *fls,
3072 bool ovly,
3073 unsigned int reloc,
3074 bool autostart,
3075 int router_chans)
3076{
3077 int status = 0;
e97249dd
IM		 3078 unsigned int sample_rate;
3079 unsigned short channels;
01ef7dbf 3080
4e76a883 3081 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 3082 if (router_chans == 0) {
3083 if (!ovly)
3084 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3085 else
3086 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3087 }
95c6e9cb 3088
e97249dd
IM		 3089 sample_rate = 48000;
3090 channels = (unsigned short)router_chans;
01ef7dbf 3091
e97249dd
IM		 3092 while (channels > 16) {
3093 sample_rate *= 2;
3094 channels /= 2;
01ef7dbf
IM		 3095 }
3096
01ef7dbf 3097 do {
4e76a883 3098 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 3099 if (!ovly)
3100 status = dsp_reset(codec);
3101
3102 if (status < 0)
3103 break;
3104
4e76a883 3105 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 3106 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3107 ovly);
01ef7dbf
IM		 3108
3109 if (status < 0)
3110 break;
3111
4e76a883 3112 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 3113 if (autostart && !ovly) {
3114 dspload_post_setup(codec);
3115 status = dsp_set_run_state(codec);
3116 }
3117
4e76a883 3118 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 3119 } while (0);
3120
3121 return status;
3122}
3123
f664417e 3124#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 3125static bool dspload_is_loaded(struct hda_codec *codec)
3126{
3127 unsigned int data = 0;
3128 int status = 0;
3129
3130 status = chipio_read(codec, 0x40004, &data);
3131 if ((status < 0) || (data != 1))
3132 return false;
3133
3134 return true;
3135}
f664417e
TI		 3136#else
3137#define dspload_is_loaded(codec) false
3138#endif
01ef7dbf
IM		 3139
3140static bool dspload_wait_loaded(struct hda_codec *codec)
3141{
6d67530e 3142 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 3143
3144 do {
01ef7dbf 3145 if (dspload_is_loaded(codec)) {
d9684bb5 3146 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 3147 return true;
3148 }
6d67530e
IM		 3149 msleep(20);
3150 } while (time_before(jiffies, timeout));
01ef7dbf 3151
d9684bb5 3152 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 3153 return false;
95c6e9cb
IM		 3154}
3155
e93ac30a 3156/*
b9b41345
CM		 3157 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3158 * based cards, and has a second mmio region, region2, that's used for special
3159 * commands.
e93ac30a
CM		 3160 */
3161
a62e4739
CM		 3162/*
3163 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3164 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3165 * The first eight bits are just the number of the pin. So far, I've only seen
3166 * this number go to 7.
b9b41345
CM		 3167 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3168 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3169 * then off to send that bit.
a62e4739 3170 */
b9b41345 3171static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
a62e4739
CM		 3172 bool enable)
3173{
3174 struct ca0132_spec *spec = codec->spec;
3175 unsigned short gpio_data;
3176
3177 gpio_data = gpio_pin & 0xF;
3178 gpio_data |= ((enable << 8) & 0x100);
3179
3180 writew(gpio_data, spec->mem_base + 0x320);
3181}
3182
b9b41345
CM		 3183/*
3184 * Special pci region2 commands that are only used by the AE-5. They follow
3185 * a set format, and require reads at certain points to seemingly 'clear'
3186 * the response data. My first tests didn't do these reads, and would cause
3187 * the card to get locked up until the memory was read. These commands
3188 * seem to work with three distinct values that I've taken to calling group,
3189 * target-id, and value.
3190 */
3191static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3192 unsigned int target, unsigned int value)
3193{
3194 struct ca0132_spec *spec = codec->spec;
3195 unsigned int write_val;
3196
3197 writel(0x0000007e, spec->mem_base + 0x210);
3198 readl(spec->mem_base + 0x210);
3199 writel(0x0000005a, spec->mem_base + 0x210);
3200 readl(spec->mem_base + 0x210);
3201 readl(spec->mem_base + 0x210);
3202
3203 writel(0x00800005, spec->mem_base + 0x20c);
3204 writel(group, spec->mem_base + 0x804);
3205
3206 writel(0x00800005, spec->mem_base + 0x20c);
3207 write_val = (target & 0xff);
3208 write_val |= (value << 8);
3209
3210
3211 writel(write_val, spec->mem_base + 0x204);
3212 /*
3213 * Need delay here or else it goes too fast and works inconsistently.
3214 */
3215 msleep(20);
3216
3217 readl(spec->mem_base + 0x860);
3218 readl(spec->mem_base + 0x854);
3219 readl(spec->mem_base + 0x840);
3220
3221 writel(0x00800004, spec->mem_base + 0x20c);
3222 writel(0x00000000, spec->mem_base + 0x210);
3223 readl(spec->mem_base + 0x210);
3224 readl(spec->mem_base + 0x210);
3225}
3226
3227/*
3228 * Setup GPIO for the other variants of Core3D.
3229 */
3230
e93ac30a
CM		 3231/*
3232 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3233 * the card shows as having no GPIO pins.
3234 */
3235static void ca0132_gpio_init(struct hda_codec *codec)
3236{
3237 struct ca0132_spec *spec = codec->spec;
3238
3239 switch (spec->quirk) {
3240 case QUIRK_SBZ:
03c9b6b1 3241 case QUIRK_AE5:
e93ac30a
CM		 3242 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3243 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3244 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3245 break;
3246 case QUIRK_R3DI:
3247 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3248 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3249 break;
3250 }
3251
3252}
3253
3254/* Sets the GPIO for audio output. */
3255static void ca0132_gpio_setup(struct hda_codec *codec)
3256{
3257 struct ca0132_spec *spec = codec->spec;
3258
3259 switch (spec->quirk) {
3260 case QUIRK_SBZ:
3261 snd_hda_codec_write(codec, 0x01, 0,
3262 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3263 snd_hda_codec_write(codec, 0x01, 0,
3264 AC_VERB_SET_GPIO_MASK, 0x07);
3265 snd_hda_codec_write(codec, 0x01, 0,
3266 AC_VERB_SET_GPIO_DATA, 0x04);
3267 snd_hda_codec_write(codec, 0x01, 0,
3268 AC_VERB_SET_GPIO_DATA, 0x06);
3269 break;
3270 case QUIRK_R3DI:
3271 snd_hda_codec_write(codec, 0x01, 0,
3272 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3273 snd_hda_codec_write(codec, 0x01, 0,
3274 AC_VERB_SET_GPIO_MASK, 0x1F);
3275 snd_hda_codec_write(codec, 0x01, 0,
3276 AC_VERB_SET_GPIO_DATA, 0x0C);
3277 break;
3278 }
3279}
3280
7e6ed62e
CM		 3281/*
3282 * GPIO control functions for the Recon3D integrated.
3283 */
3284
3285enum r3di_gpio_bit {
3286 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3287 R3DI_MIC_SELECT_BIT = 1,
3288 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3289 R3DI_OUT_SELECT_BIT = 2,
3290 /*
3291 * I dunno what this actually does, but it stays on until the dsp
3292 * is downloaded.
3293 */
3294 R3DI_GPIO_DSP_DOWNLOADING = 3,
3295 /*
3296 * Same as above, no clue what it does, but it comes on after the dsp
3297 * is downloaded.
3298 */
3299 R3DI_GPIO_DSP_DOWNLOADED = 4
3300};
3301
3302enum r3di_mic_select {
3303 /* Set GPIO bit 1 to 0 for rear mic */
3304 R3DI_REAR_MIC = 0,
3305 /* Set GPIO bit 1 to 1 for front microphone*/
3306 R3DI_FRONT_MIC = 1
3307};
3308
3309enum r3di_out_select {
3310 /* Set GPIO bit 2 to 0 for headphone */
3311 R3DI_HEADPHONE_OUT = 0,
3312 /* Set GPIO bit 2 to 1 for speaker */
3313 R3DI_LINE_OUT = 1
3314};
3315enum r3di_dsp_status {
3316 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3317 R3DI_DSP_DOWNLOADING = 0,
3318 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3319 R3DI_DSP_DOWNLOADED = 1
3320};
3321
7cb9d94c
CM		 3322
3323static void r3di_gpio_mic_set(struct hda_codec *codec,
3324 enum r3di_mic_select cur_mic)
3325{
3326 unsigned int cur_gpio;
3327
3328 /* Get the current GPIO Data setup */
3329 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3330
3331 switch (cur_mic) {
3332 case R3DI_REAR_MIC:
3333 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3334 break;
3335 case R3DI_FRONT_MIC:
3336 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3337 break;
3338 }
3339 snd_hda_codec_write(codec, codec->core.afg, 0,
3340 AC_VERB_SET_GPIO_DATA, cur_gpio);
3341}
3342
3343static void r3di_gpio_out_set(struct hda_codec *codec,
3344 enum r3di_out_select cur_out)
3345{
3346 unsigned int cur_gpio;
3347
3348 /* Get the current GPIO Data setup */
3349 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3350
3351 switch (cur_out) {
3352 case R3DI_HEADPHONE_OUT:
3353 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3354 break;
3355 case R3DI_LINE_OUT:
3356 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3357 break;
3358 }
3359 snd_hda_codec_write(codec, codec->core.afg, 0,
3360 AC_VERB_SET_GPIO_DATA, cur_gpio);
3361}
3362
7e6ed62e
CM		 3363static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3364 enum r3di_dsp_status dsp_status)
3365{
3366 unsigned int cur_gpio;
3367
3368 /* Get the current GPIO Data setup */
3369 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3370
3371 switch (dsp_status) {
3372 case R3DI_DSP_DOWNLOADING:
3373 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3374 snd_hda_codec_write(codec, codec->core.afg, 0,
3375 AC_VERB_SET_GPIO_DATA, cur_gpio);
3376 break;
3377 case R3DI_DSP_DOWNLOADED:
3378 /* Set DOWNLOADING bit to 0. */
3379 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3380
3381 snd_hda_codec_write(codec, codec->core.afg, 0,
3382 AC_VERB_SET_GPIO_DATA, cur_gpio);
3383
3384 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3385 break;
3386 }
3387
3388 snd_hda_codec_write(codec, codec->core.afg, 0,
3389 AC_VERB_SET_GPIO_DATA, cur_gpio);
3390}
3391
825315bc
IM		 3392/*
3393 * PCM callbacks
3394 */
95c6e9cb
IM		 3395static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3396 struct hda_codec *codec,
3397 unsigned int stream_tag,
3398 unsigned int format,
3399 struct snd_pcm_substream *substream)
3400{
3401 struct ca0132_spec *spec = codec->spec;
825315bc 3402
28fba950 3403 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 3404
3405 return 0;
95c6e9cb
IM		 3406}
3407
3408static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3409 struct hda_codec *codec,
3410 struct snd_pcm_substream *substream)
3411{
3412 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 3413
3414 if (spec->dsp_state == DSP_DOWNLOADING)
3415 return 0;
3416
3417 /*If Playback effects are on, allow stream some time to flush
3418 *effects tail*/
3419 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3420 msleep(50);
3421
28fba950 3422 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 3423
3424 return 0;
95c6e9cb
IM		 3425}
3426
e8412ca4
DR		 3427static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3428 struct hda_codec *codec,
3429 struct snd_pcm_substream *substream)
3430{
3431 struct ca0132_spec *spec = codec->spec;
3432 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3433 struct snd_pcm_runtime *runtime = substream->runtime;
3434
3435 if (spec->dsp_state != DSP_DOWNLOADED)
3436 return 0;
3437
3438 /* Add latency if playback enhancement and either effect is enabled. */
3439 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3440 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3441 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3442 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3443 }
3444
3445 /* Applying Speaker EQ adds latency as well. */
3446 if (spec->cur_out_type == SPEAKER_OUT)
3447 latency += DSP_SPEAKER_OUT_LATENCY;
3448
3449 return (latency * runtime->rate) / 1000;
3450}
3451
95c6e9cb
IM		 3452/*
3453 * Digital out
3454 */
27ebeb0b
TI		 3455static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3456 struct hda_codec *codec,
3457 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3458{
3459 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3460 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 3461}
3462
27ebeb0b 3463static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 3464 struct hda_codec *codec,
3465 unsigned int stream_tag,
3466 unsigned int format,
3467 struct snd_pcm_substream *substream)
3468{
3469 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 3470 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3471 stream_tag, format, substream);
95c6e9cb
IM		 3472}
3473
27ebeb0b 3474static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 3475 struct hda_codec *codec,
95c6e9cb
IM		 3476 struct snd_pcm_substream *substream)
3477{
3478 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3479 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 3480}
3481
27ebeb0b
TI		 3482static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3483 struct hda_codec *codec,
3484 struct snd_pcm_substream *substream)
95c6e9cb
IM		 3485{
3486 struct ca0132_spec *spec = codec->spec;
27ebeb0b 3487 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 3488}
3489
825315bc
IM		 3490/*
3491 * Analog capture
3492 */
3493static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3494 struct hda_codec *codec,
3495 unsigned int stream_tag,
3496 unsigned int format,
3497 struct snd_pcm_substream *substream)
3498{
13c12dbe 3499 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 3500 stream_tag, 0, format);
825315bc
IM		 3501
3502 return 0;
3503}
3504
3505static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3506 struct hda_codec *codec,
3507 struct snd_pcm_substream *substream)
3508{
3509 struct ca0132_spec *spec = codec->spec;
3510
3511 if (spec->dsp_state == DSP_DOWNLOADING)
3512 return 0;
3513
28fba950 3514 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 3515 return 0;
3516}
3517
e8412ca4
DR		 3518static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3519 struct hda_codec *codec,
3520 struct snd_pcm_substream *substream)
3521{
3522 struct ca0132_spec *spec = codec->spec;
3523 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3524 struct snd_pcm_runtime *runtime = substream->runtime;
3525
3526 if (spec->dsp_state != DSP_DOWNLOADED)
3527 return 0;
3528
3529 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3530 latency += DSP_CRYSTAL_VOICE_LATENCY;
3531
3532 return (latency * runtime->rate) / 1000;
3533}
3534
e90f29e4
IM		 3535/*
3536 * Controls stuffs.
3537 */
3538
3539/*
3540 * Mixer controls helpers.
3541 */
3542#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3543 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3544 .name = xname, \
3545 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3546 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3547 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3548 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3549 .info = ca0132_volume_info, \
3550 .get = ca0132_volume_get, \
3551 .put = ca0132_volume_put, \
3552 .tlv = { .c = ca0132_volume_tlv }, \
3553 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3554
017310fb
CM		 3555/*
3556 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3557 * volume put, which is used for setting the DSP volume. This was done because
3558 * the ca0132 functions were taking too much time and causing lag.
3559 */
3560#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3561 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3562 .name = xname, \
3563 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3564 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3565 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3566 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3567 .info = snd_hda_mixer_amp_volume_info, \
3568 .get = snd_hda_mixer_amp_volume_get, \
3569 .put = ca0132_alt_volume_put, \
3570 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3571 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3572
e90f29e4
IM		 3573#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3574 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3575 .name = xname, \
3576 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3577 .info = snd_hda_mixer_amp_switch_info, \
3578 .get = ca0132_switch_get, \
3579 .put = ca0132_switch_put, \
3580 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3581
3582/* stereo */
3583#define CA0132_CODEC_VOL(xname, nid, dir) \
3584 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
017310fb
CM		 3585#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3586 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
e90f29e4
IM		 3587#define CA0132_CODEC_MUTE(xname, nid, dir) \
3588 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3589
017310fb
CM		 3590/* lookup tables */
3591/*
3592 * Lookup table with decibel values for the DSP. When volume is changed in
3593 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3594 * these values have decimal points, probably because the Windows driver
3595 * actually uses floating point. We can't here, so I made a lookup table of
3596 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3597 * DAC's, and 9 is the maximum.
3598 */
3599static const unsigned int float_vol_db_lookup[] = {
36000xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
36010xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
36020xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
36030xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
36040xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
36050xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
36060xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
36070xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
36080xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
36090xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
36100xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
36110xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
36120xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
36130xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
36140xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
36150x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
36160x40C00000, 0x40E00000, 0x41000000, 0x41100000
3617};
3618
47cdf76e
CM		 3619/*
3620 * This table counts from float 0 to 1 in increments of .01, which is
3621 * useful for a few different sliders.
3622 */
3623static const unsigned int float_zero_to_one_lookup[] = {
36240x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
36250x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
36260x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
36270x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
36280x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
36290x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
36300x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
36310x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
36320x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
36330x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
36340x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
36350x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
36360x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
36370x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
36380x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
36390x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
36400x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3641};
3642
3643/*
3644 * This table counts from float 10 to 1000, which is the range of the x-bass
3645 * crossover slider in Windows.
3646 */
3647static const unsigned int float_xbass_xover_lookup[] = {
36480x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
36490x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
36500x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
36510x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
36520x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
36530x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
36540x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
36550x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
36560x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
36570x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
36580x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
36590x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
36600x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
36610x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
36620x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
36630x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
36640x44728000, 0x44750000, 0x44778000, 0x447A0000
3665};
3666
4091fb95 3667/* The following are for tuning of products */
44f0c978
IM		 3668#ifdef ENABLE_TUNING_CONTROLS
3669
3670static unsigned int voice_focus_vals_lookup[] = {
36710x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
36720x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
36730x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
36740x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
36750x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
36760x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
36770x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
36780x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
36790x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
36800x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
36810x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
36820x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
36830x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
36840x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
36850x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
36860x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
36870x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
36880x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
36890x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
36900x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
36910x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
36920x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
36930x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
36940x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
36950x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
36960x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
36970x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3698};
3699
3700static unsigned int mic_svm_vals_lookup[] = {
37010x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
37020x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
37030x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
37040x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
37050x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
37060x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
37070x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
37080x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
37090x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
37100x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
37110x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
37120x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
37130x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
37140x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
37150x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
37160x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
37170x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3718};
3719
3720static unsigned int equalizer_vals_lookup[] = {
37210xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
37220xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
37230xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
37240xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
37250x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
37260x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
37270x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
37280x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
37290x41C00000
3730};
3731
3732static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3733 unsigned int *lookup, int idx)
3734{
3735 int i = 0;
3736
3737 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3738 if (nid == ca0132_tuning_ctls[i].nid)
3739 break;
3740
3741 snd_hda_power_up(codec);
447fd8e9 3742 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
44f0c978
IM		 3743 ca0132_tuning_ctls[i].req,
3744 &(lookup[idx]), sizeof(unsigned int));
3745 snd_hda_power_down(codec);
3746
3747 return 1;
3748}
3749
3750static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3751 struct snd_ctl_elem_value *ucontrol)
3752{
3753 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3754 struct ca0132_spec *spec = codec->spec;
3755 hda_nid_t nid = get_amp_nid(kcontrol);
3756 long *valp = ucontrol->value.integer.value;
3757 int idx = nid - TUNING_CTL_START_NID;
3758
3759 *valp = spec->cur_ctl_vals[idx];
3760 return 0;
3761}
3762
3763static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3764 struct snd_ctl_elem_info *uinfo)
3765{
3766 int chs = get_amp_channels(kcontrol);
3767 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3768 uinfo->count = chs == 3 ? 2 : 1;
3769 uinfo->value.integer.min = 20;
3770 uinfo->value.integer.max = 180;
3771 uinfo->value.integer.step = 1;
3772
3773 return 0;
3774}
3775
3776static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3777 struct snd_ctl_elem_value *ucontrol)
3778{
3779 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3780 struct ca0132_spec *spec = codec->spec;
3781 hda_nid_t nid = get_amp_nid(kcontrol);
3782 long *valp = ucontrol->value.integer.value;
3783 int idx;
3784
3785 idx = nid - TUNING_CTL_START_NID;
3786 /* any change? */
3787 if (spec->cur_ctl_vals[idx] == *valp)
3788 return 0;
3789
3790 spec->cur_ctl_vals[idx] = *valp;
3791
3792 idx = *valp - 20;
3793 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3794
3795 return 1;
3796}
3797
3798static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3799 struct snd_ctl_elem_info *uinfo)
3800{
3801 int chs = get_amp_channels(kcontrol);
3802 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3803 uinfo->count = chs == 3 ? 2 : 1;
3804 uinfo->value.integer.min = 0;
3805 uinfo->value.integer.max = 100;
3806 uinfo->value.integer.step = 1;
3807
3808 return 0;
3809}
3810
3811static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3812 struct snd_ctl_elem_value *ucontrol)
3813{
3814 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3815 struct ca0132_spec *spec = codec->spec;
3816 hda_nid_t nid = get_amp_nid(kcontrol);
3817 long *valp = ucontrol->value.integer.value;
3818 int idx;
3819
3820 idx = nid - TUNING_CTL_START_NID;
3821 /* any change? */
3822 if (spec->cur_ctl_vals[idx] == *valp)
3823 return 0;
3824
3825 spec->cur_ctl_vals[idx] = *valp;
3826
3827 idx = *valp;
3828 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3829
3830 return 0;
3831}
3832
3833static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3834 struct snd_ctl_elem_info *uinfo)
3835{
3836 int chs = get_amp_channels(kcontrol);
3837 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3838 uinfo->count = chs == 3 ? 2 : 1;
3839 uinfo->value.integer.min = 0;
3840 uinfo->value.integer.max = 48;
3841 uinfo->value.integer.step = 1;
3842
3843 return 0;
3844}
3845
3846static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3847 struct snd_ctl_elem_value *ucontrol)
3848{
3849 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3850 struct ca0132_spec *spec = codec->spec;
3851 hda_nid_t nid = get_amp_nid(kcontrol);
3852 long *valp = ucontrol->value.integer.value;
3853 int idx;
3854
3855 idx = nid - TUNING_CTL_START_NID;
3856 /* any change? */
3857 if (spec->cur_ctl_vals[idx] == *valp)
3858 return 0;
3859
3860 spec->cur_ctl_vals[idx] = *valp;
3861
3862 idx = *valp;
3863 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3864
3865 return 1;
3866}
3867
8e142e9e
TS		 3868static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3869static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3870
3871static int add_tuning_control(struct hda_codec *codec,
3872 hda_nid_t pnid, hda_nid_t nid,
3873 const char *name, int dir)
3874{
975cc02a 3875 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3876 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3877 struct snd_kcontrol_new knew =
3878 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3879
3880 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3881 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3882 knew.tlv.c = 0;
3883 knew.tlv.p = 0;
3884 switch (pnid) {
3885 case VOICE_FOCUS:
3886 knew.info = voice_focus_ctl_info;
3887 knew.get = tuning_ctl_get;
3888 knew.put = voice_focus_ctl_put;
3889 knew.tlv.p = voice_focus_db_scale;
3890 break;
3891 case MIC_SVM:
3892 knew.info = mic_svm_ctl_info;
3893 knew.get = tuning_ctl_get;
3894 knew.put = mic_svm_ctl_put;
3895 break;
3896 case EQUALIZER:
3897 knew.info = equalizer_ctl_info;
3898 knew.get = tuning_ctl_get;
3899 knew.put = equalizer_ctl_put;
3900 knew.tlv.p = eq_db_scale;
3901 break;
3902 default:
3903 return 0;
3904 }
3905 knew.private_value =
3906 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3907 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3908 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3909}
3910
3911static int add_tuning_ctls(struct hda_codec *codec)
3912{
3913 int i;
3914 int err;
3915
3916 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3917 err = add_tuning_control(codec,
3918 ca0132_tuning_ctls[i].parent_nid,
3919 ca0132_tuning_ctls[i].nid,
3920 ca0132_tuning_ctls[i].name,
3921 ca0132_tuning_ctls[i].direct);
3922 if (err < 0)
3923 return err;
3924 }
3925
3926 return 0;
3927}
3928
3929static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3930{
3931 struct ca0132_spec *spec = codec->spec;
3932 int i;
3933
3934 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3935 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3936 /* SVM level defaults to 0.74. */
3937 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3938
3939 /* EQ defaults to 0dB. */
3940 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3941 spec->cur_ctl_vals[i] = 24;
3942}
3943#endif /*ENABLE_TUNING_CONTROLS*/
3944
5aaca44d
IM		 3945/*
3946 * Select the active output.
3947 * If autodetect is enabled, output will be selected based on jack detection.
3948 * If jack inserted, headphone will be selected, else built-in speakers
3949 * If autodetect is disabled, output will be selected based on selection.
3950 */
3951static int ca0132_select_out(struct hda_codec *codec)
3952{
3953 struct ca0132_spec *spec = codec->spec;
3954 unsigned int pin_ctl;
3955 int jack_present;
3956 int auto_jack;
3957 unsigned int tmp;
3958 int err;
3959
4e76a883 3960 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 3961
664c7155 3962 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3963
3964 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3965
3966 if (auto_jack)
fe14f39e 3967 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 3968 else
3969 jack_present =
3970 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3971
3972 if (jack_present)
3973 spec->cur_out_type = HEADPHONE_OUT;
3974 else
3975 spec->cur_out_type = SPEAKER_OUT;
3976
3977 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 3978 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 3979 /*speaker out config*/
3980 tmp = FLOAT_ONE;
3981 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3982 if (err < 0)
3983 goto exit;
3984 /*enable speaker EQ*/
3985 tmp = FLOAT_ONE;
3986 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3987 if (err < 0)
3988 goto exit;
3989
3990 /* Setup EAPD */
3991 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3992 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3993 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3994 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3995 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3996 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3997 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3998 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3999
4000 /* disable headphone node */
4001 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4002 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4003 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4004 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4005 /* enable speaker node */
4006 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
8a19bcee 4007 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4008 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4009 pin_ctl | PIN_OUT);
5aaca44d 4010 } else {
4e76a883 4011 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 4012 /*headphone out config*/
4013 tmp = FLOAT_ZERO;
4014 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4015 if (err < 0)
4016 goto exit;
4017 /*disable speaker EQ*/
4018 tmp = FLOAT_ZERO;
4019 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4020 if (err < 0)
4021 goto exit;
4022
4023 /* Setup EAPD */
4024 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4025 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4026 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4027 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4028 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4029 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4030 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4031 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4032
4033 /* disable speaker*/
4034 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4035 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4036 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4037 pin_ctl & ~PIN_HP);
5aaca44d
IM		 4038 /* enable headphone*/
4039 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4040 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 4041 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4042 pin_ctl | PIN_HP);
5aaca44d
IM		 4043 }
4044
4045exit:
664c7155 4046 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4047
4048 return err < 0 ? err : 0;
4049}
4050
2283c85b
CM		 4051static void ae5_mmio_select_out(struct hda_codec *codec)
4052{
4053 struct ca0132_spec *spec = codec->spec;
4054 unsigned int i;
4055
4056 for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++)
4057 ca0113_mmio_command_set(codec,
4058 ae5_ca0113_output_presets[spec->cur_out_type].group[i],
4059 ae5_ca0113_output_presets[spec->cur_out_type].target[i],
4060 ae5_ca0113_output_presets[spec->cur_out_type].vals[i]);
4061}
4062
746fc9de
CM		 4063/*
4064 * These are the commands needed to setup output on each of the different card
4065 * types.
4066 */
4067static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec)
4068{
4069 struct ca0132_spec *spec = codec->spec;
2283c85b 4070 unsigned int tmp;
746fc9de
CM		 4071
4072 switch (spec->cur_out_type) {
4073 case SPEAKER_OUT:
4074 switch (spec->quirk) {
4075 case QUIRK_SBZ:
4076 ca0113_mmio_gpio_set(codec, 7, false);
4077 ca0113_mmio_gpio_set(codec, 4, true);
4078 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b 4079 chipio_set_control_param(codec, 0x0d, 0x18);
746fc9de
CM		 4080 break;
4081 case QUIRK_R3DI:
2283c85b 4082 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4083 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4084 break;
4085 case QUIRK_R3D:
2283c85b 4086 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4087 ca0113_mmio_gpio_set(codec, 1, true);
4088 break;
2283c85b
CM		 4089 case QUIRK_AE5:
4090 ae5_mmio_select_out(codec);
4091 tmp = FLOAT_ZERO;
4092 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4093 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4094 chipio_set_control_param(codec, 0x0d, 0xa4);
4095 chipio_write(codec, 0x18b03c, 0x00000012);
4096 break;
746fc9de
CM		 4097 }
4098 break;
4099 case HEADPHONE_OUT:
4100 switch (spec->quirk) {
4101 case QUIRK_SBZ:
4102 ca0113_mmio_gpio_set(codec, 7, true);
4103 ca0113_mmio_gpio_set(codec, 4, true);
4104 ca0113_mmio_gpio_set(codec, 1, false);
2283c85b 4105 chipio_set_control_param(codec, 0x0d, 0x12);
746fc9de
CM		 4106 break;
4107 case QUIRK_R3DI:
2283c85b 4108 chipio_set_control_param(codec, 0x0d, 0x21);
746fc9de
CM		 4109 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4110 break;
4111 case QUIRK_R3D:
2283c85b 4112 chipio_set_control_param(codec, 0x0d, 0x21);
746fc9de
CM		 4113 ca0113_mmio_gpio_set(codec, 0x1, false);
4114 break;
2283c85b
CM		 4115 case QUIRK_AE5:
4116 ae5_mmio_select_out(codec);
4117 tmp = FLOAT_ONE;
4118 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4119 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4120 chipio_set_control_param(codec, 0x0d, 0xa1);
4121 chipio_write(codec, 0x18b03c, 0x00000012);
4122 break;
746fc9de
CM		 4123 }
4124 break;
4125 case SURROUND_OUT:
4126 switch (spec->quirk) {
4127 case QUIRK_SBZ:
4128 ca0113_mmio_gpio_set(codec, 7, false);
4129 ca0113_mmio_gpio_set(codec, 4, true);
4130 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b 4131 chipio_set_control_param(codec, 0x0d, 0x18);
746fc9de
CM		 4132 break;
4133 case QUIRK_R3DI:
2283c85b 4134 chipio_set_control_param(codec, 0x0d, 0x24);
746fc9de
CM		 4135 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4136 break;
4137 case QUIRK_R3D:
4138 ca0113_mmio_gpio_set(codec, 1, true);
2283c85b
CM		 4139 chipio_set_control_param(codec, 0x0d, 0x24);
4140 break;
4141 case QUIRK_AE5:
4142 ae5_mmio_select_out(codec);
4143 tmp = FLOAT_ZERO;
4144 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
4145 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
4146 chipio_set_control_param(codec, 0x0d, 0xa4);
4147 chipio_write(codec, 0x18b03c, 0x00000012);
746fc9de
CM		 4148 break;
4149 }
4150 break;
4151 }
4152}
4153
7cb9d94c
CM		 4154/*
4155 * This function behaves similarly to the ca0132_select_out funciton above,
4156 * except with a few differences. It adds the ability to select the current
4157 * output with an enumerated control "output source" if the auto detect
4158 * mute switch is set to off. If the auto detect mute switch is enabled, it
4159 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4160 * It also adds the ability to auto-detect the front headphone port. The only
4161 * way to select surround is to disable auto detect, and set Surround with the
4162 * enumerated control.
4163 */
4164static int ca0132_alt_select_out(struct hda_codec *codec)
4165{
4166 struct ca0132_spec *spec = codec->spec;
4167 unsigned int pin_ctl;
4168 int jack_present;
4169 int auto_jack;
4170 unsigned int i;
4171 unsigned int tmp;
4172 int err;
4173 /* Default Headphone is rear headphone */
4174 hda_nid_t headphone_nid = spec->out_pins[1];
4175
4176 codec_dbg(codec, "%s\n", __func__);
4177
4178 snd_hda_power_up_pm(codec);
4179
4180 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4181
4182 /*
4183 * If headphone rear or front is plugged in, set to headphone.
4184 * If neither is plugged in, set to rear line out. Only if
4185 * hp/speaker auto detect is enabled.
4186 */
4187 if (auto_jack) {
4188 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4189 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4190
4191 if (jack_present)
4192 spec->cur_out_type = HEADPHONE_OUT;
4193 else
4194 spec->cur_out_type = SPEAKER_OUT;
4195 } else
4196 spec->cur_out_type = spec->out_enum_val;
4197
4198 /* Begin DSP output switch */
4199 tmp = FLOAT_ONE;
4200 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
4201 if (err < 0)
4202 goto exit;
4203
746fc9de
CM		 4204 ca0132_alt_select_out_quirk_handler(codec);
4205
7cb9d94c
CM		 4206 switch (spec->cur_out_type) {
4207 case SPEAKER_OUT:
4208 codec_dbg(codec, "%s speaker\n", __func__);
7cb9d94c
CM		 4209
4210 /* disable headphone node */
4211 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4212 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4213 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4214 pin_ctl & ~PIN_HP);
4215 /* enable line-out node */
4216 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4217 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4218 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4219 pin_ctl | PIN_OUT);
4220 /* Enable EAPD */
4221 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4222 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4223
4224 /* If PlayEnhancement is enabled, set different source */
4225 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4226 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4227 else
4228 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4229 break;
4230 case HEADPHONE_OUT:
4231 codec_dbg(codec, "%s hp\n", __func__);
7cb9d94c
CM		 4232
4233 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4234 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4235
4236 /* disable speaker*/
4237 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4238 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4239 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4240 pin_ctl & ~PIN_HP);
4241
4242 /* enable headphone, either front or rear */
4243
4244 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4245 headphone_nid = spec->out_pins[2];
4246 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4247 headphone_nid = spec->out_pins[1];
4248
4249 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4250 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4251 snd_hda_set_pin_ctl(codec, headphone_nid,
4252 pin_ctl | PIN_HP);
4253
4254 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4255 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4256 else
4257 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4258 break;
4259 case SURROUND_OUT:
4260 codec_dbg(codec, "%s surround\n", __func__);
746fc9de 4261
7cb9d94c
CM		 4262 /* enable line out node */
4263 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4264 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4265 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4266 pin_ctl | PIN_OUT);
4267 /* Disable headphone out */
4268 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4269 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4270 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4271 pin_ctl & ~PIN_HP);
4272 /* Enable EAPD on line out */
4273 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4274 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4275 /* enable center/lfe out node */
4276 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4277 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4278 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4279 pin_ctl | PIN_OUT);
4280 /* Now set rear surround node as out. */
4281 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4282 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4283 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4284 pin_ctl | PIN_OUT);
4285
4286 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4287 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4288 else
4289 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4290 break;
4291 }
4292
2283c85b 4293 /* run through the output dsp commands for the selected output. */
7cb9d94c
CM		 4294 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4295 err = dspio_set_uint_param(codec,
4296 alt_out_presets[spec->cur_out_type].mids[i],
4297 alt_out_presets[spec->cur_out_type].reqs[i],
4298 alt_out_presets[spec->cur_out_type].vals[i]);
4299
4300 if (err < 0)
4301 goto exit;
4302 }
4303
4304exit:
4305 snd_hda_power_down_pm(codec);
4306
4307 return err < 0 ? err : 0;
4308}
4309
993884f6
CCC		 4310static void ca0132_unsol_hp_delayed(struct work_struct *work)
4311{
4312 struct ca0132_spec *spec = container_of(
4313 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 4314 struct hda_jack_tbl *jack;
4315
7cb9d94c
CM		 4316 if (spec->use_alt_functions)
4317 ca0132_alt_select_out(spec->codec);
4318 else
4319 ca0132_select_out(spec->codec);
4320
d5c016b5 4321 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 4322 if (jack) {
4323 jack->block_report = 0;
4324 snd_hda_jack_report_sync(spec->codec);
4325 }
993884f6
CCC		 4326}
4327
5aaca44d
IM		 4328static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4329static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4330static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
e0026d03
CM		 4331static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4332static int stop_mic1(struct hda_codec *codec);
4333static int ca0132_cvoice_switch_set(struct hda_codec *codec);
47cdf76e 4334static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
5aaca44d
IM		 4335
4336/*
4337 * Select the active VIP source
4338 */
4339static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4340{
4341 struct ca0132_spec *spec = codec->spec;
4342 unsigned int tmp;
4343
e8f1bd5d 4344 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4345 return 0;
4346
4347 /* if CrystalVoice if off, vipsource should be 0 */
4348 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4349 (val == 0)) {
4350 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4351 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4352 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4353 if (spec->cur_mic_type == DIGITAL_MIC)
4354 tmp = FLOAT_TWO;
4355 else
4356 tmp = FLOAT_ONE;
4357 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4358 tmp = FLOAT_ZERO;
4359 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4360 } else {
4361 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4362 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4363 if (spec->cur_mic_type == DIGITAL_MIC)
4364 tmp = FLOAT_TWO;
4365 else
4366 tmp = FLOAT_ONE;
4367 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4368 tmp = FLOAT_ONE;
4369 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4370 msleep(20);
4371 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4372 }
4373
4374 return 1;
4375}
4376
e0026d03
CM		 4377static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4378{
4379 struct ca0132_spec *spec = codec->spec;
4380 unsigned int tmp;
4381
4382 if (spec->dsp_state != DSP_DOWNLOADED)
4383 return 0;
4384
4385 codec_dbg(codec, "%s\n", __func__);
4386
4387 chipio_set_stream_control(codec, 0x03, 0);
4388 chipio_set_stream_control(codec, 0x04, 0);
4389
4390 /* if CrystalVoice is off, vipsource should be 0 */
4391 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4392 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4393 codec_dbg(codec, "%s: off.", __func__);
4394 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4395
4396 tmp = FLOAT_ZERO;
4397 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4398
4399 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4400 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4401 if (spec->quirk == QUIRK_R3DI)
4402 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4403
4404
4405 if (spec->in_enum_val == REAR_LINE_IN)
4406 tmp = FLOAT_ZERO;
4407 else {
4408 if (spec->quirk == QUIRK_SBZ)
4409 tmp = FLOAT_THREE;
4410 else
4411 tmp = FLOAT_ONE;
4412 }
4413
4414 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4415
4416 } else {
4417 codec_dbg(codec, "%s: on.", __func__);
4418 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4419 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4420 if (spec->quirk == QUIRK_R3DI)
4421 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4422
4423 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4424 tmp = FLOAT_TWO;
4425 else
4426 tmp = FLOAT_ONE;
4427 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4428
4429 tmp = FLOAT_ONE;
4430 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4431
4432 msleep(20);
4433 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4434 }
4435
4436 chipio_set_stream_control(codec, 0x03, 1);
4437 chipio_set_stream_control(codec, 0x04, 1);
4438
4439 return 1;
4440}
4441
5aaca44d
IM		 4442/*
4443 * Select the active microphone.
4444 * If autodetect is enabled, mic will be selected based on jack detection.
4445 * If jack inserted, ext.mic will be selected, else built-in mic
4446 * If autodetect is disabled, mic will be selected based on selection.
4447 */
4448static int ca0132_select_mic(struct hda_codec *codec)
4449{
4450 struct ca0132_spec *spec = codec->spec;
4451 int jack_present;
4452 int auto_jack;
4453
4e76a883 4454 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 4455
664c7155 4456 snd_hda_power_up_pm(codec);
5aaca44d
IM		 4457
4458 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4459
4460 if (auto_jack)
fe14f39e 4461 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 4462 else
4463 jack_present =
4464 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4465
4466 if (jack_present)
4467 spec->cur_mic_type = LINE_MIC_IN;
4468 else
4469 spec->cur_mic_type = DIGITAL_MIC;
4470
4471 if (spec->cur_mic_type == DIGITAL_MIC) {
4472 /* enable digital Mic */
4473 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4474 ca0132_set_dmic(codec, 1);
4475 ca0132_mic_boost_set(codec, 0);
4476 /* set voice focus */
4477 ca0132_effects_set(codec, VOICE_FOCUS,
4478 spec->effects_switch
4479 [VOICE_FOCUS - EFFECT_START_NID]);
4480 } else {
4481 /* disable digital Mic */
4482 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4483 ca0132_set_dmic(codec, 0);
4484 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4485 /* disable voice focus */
4486 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4487 }
4488
664c7155 4489 snd_hda_power_down_pm(codec);
5aaca44d
IM		 4490
4491 return 0;
4492}
4493
7cb9d94c
CM		 4494/*
4495 * Select the active input.
4496 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4497 * The front mic has no jack-detection, so the only way to switch to it
4498 * is to do it manually in alsamixer.
4499 */
4500static int ca0132_alt_select_in(struct hda_codec *codec)
4501{
4502 struct ca0132_spec *spec = codec->spec;
4503 unsigned int tmp;
4504
4505 codec_dbg(codec, "%s\n", __func__);
4506
4507 snd_hda_power_up_pm(codec);
4508
4509 chipio_set_stream_control(codec, 0x03, 0);
4510 chipio_set_stream_control(codec, 0x04, 0);
4511
4512 spec->cur_mic_type = spec->in_enum_val;
4513
4514 switch (spec->cur_mic_type) {
4515 case REAR_MIC:
4516 switch (spec->quirk) {
4517 case QUIRK_SBZ:
42aa3a16 4518 case QUIRK_R3D:
b9b41345 4519 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4520 tmp = FLOAT_THREE;
4521 break;
4522 case QUIRK_R3DI:
4523 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4524 tmp = FLOAT_ONE;
4525 break;
4526 default:
4527 tmp = FLOAT_ONE;
4528 break;
4529 }
4530
4531 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4532 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4533 if (spec->quirk == QUIRK_R3DI)
4534 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4535
4536 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4537
4538 chipio_set_stream_control(codec, 0x03, 1);
4539 chipio_set_stream_control(codec, 0x04, 1);
4540
4541 if (spec->quirk == QUIRK_SBZ) {
4542 chipio_write(codec, 0x18B098, 0x0000000C);
4543 chipio_write(codec, 0x18B09C, 0x0000000C);
4544 }
47cdf76e 4545 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4546 break;
4547 case REAR_LINE_IN:
4548 ca0132_mic_boost_set(codec, 0);
4549 switch (spec->quirk) {
4550 case QUIRK_SBZ:
42aa3a16 4551 case QUIRK_R3D:
b9b41345 4552 ca0113_mmio_gpio_set(codec, 0, false);
7cb9d94c
CM		 4553 break;
4554 case QUIRK_R3DI:
4555 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4556 break;
4557 }
4558
4559 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4560 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4561 if (spec->quirk == QUIRK_R3DI)
4562 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4563
4564 tmp = FLOAT_ZERO;
4565 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4566
4567 if (spec->quirk == QUIRK_SBZ) {
4568 chipio_write(codec, 0x18B098, 0x00000000);
4569 chipio_write(codec, 0x18B09C, 0x00000000);
4570 }
4571
4572 chipio_set_stream_control(codec, 0x03, 1);
4573 chipio_set_stream_control(codec, 0x04, 1);
4574 break;
4575 case FRONT_MIC:
4576 switch (spec->quirk) {
4577 case QUIRK_SBZ:
42aa3a16 4578 case QUIRK_R3D:
b9b41345
CM		 4579 ca0113_mmio_gpio_set(codec, 0, true);
4580 ca0113_mmio_gpio_set(codec, 5, false);
7cb9d94c
CM		 4581 tmp = FLOAT_THREE;
4582 break;
4583 case QUIRK_R3DI:
4584 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4585 tmp = FLOAT_ONE;
4586 break;
4587 default:
4588 tmp = FLOAT_ONE;
4589 break;
4590 }
4591
4592 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4593 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4594 if (spec->quirk == QUIRK_R3DI)
4595 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4596
4597 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4598
4599 chipio_set_stream_control(codec, 0x03, 1);
4600 chipio_set_stream_control(codec, 0x04, 1);
4601
4602 if (spec->quirk == QUIRK_SBZ) {
4603 chipio_write(codec, 0x18B098, 0x0000000C);
4604 chipio_write(codec, 0x18B09C, 0x000000CC);
4605 }
47cdf76e 4606 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
7cb9d94c
CM		 4607 break;
4608 }
e0026d03 4609 ca0132_cvoice_switch_set(codec);
7cb9d94c
CM		 4610
4611 snd_hda_power_down_pm(codec);
4612 return 0;
4613
4614}
4615
a7e76271
IM		 4616/*
4617 * Check if VNODE settings take effect immediately.
4618 */
4619static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4620 hda_nid_t vnid,
4621 hda_nid_t *shared_nid)
4622{
4623 struct ca0132_spec *spec = codec->spec;
4624 hda_nid_t nid;
a7e76271
IM		 4625
4626 switch (vnid) {
4627 case VNID_SPK:
4628 nid = spec->shared_out_nid;
a7e76271
IM		 4629 break;
4630 case VNID_MIC:
4631 nid = spec->shared_mic_nid;
a7e76271
IM		 4632 break;
4633 default:
9a0869f4 4634 return false;
a7e76271
IM		 4635 }
4636
9a0869f4 4637 if (shared_nid)
a7e76271
IM		 4638 *shared_nid = nid;
4639
9a0869f4 4640 return true;
a7e76271
IM		 4641}
4642
4643/*
4644* The following functions are control change helpers.
4645* They return 0 if no changed. Return 1 if changed.
4646*/
4647static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4648{
4649 struct ca0132_spec *spec = codec->spec;
4650 unsigned int tmp;
4651
4652 /* based on CrystalVoice state to enable VoiceFX. */
4653 if (enable) {
4654 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4655 FLOAT_ONE : FLOAT_ZERO;
4656 } else {
4657 tmp = FLOAT_ZERO;
4658 }
4659
4660 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4661 ca0132_voicefx.reqs[0], tmp);
4662
4663 return 1;
4664}
4665
5aaca44d
IM		 4666/*
4667 * Set the effects parameters
4668 */
4669static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4670{
4671 struct ca0132_spec *spec = codec->spec;
009b8f97 4672 unsigned int on, tmp;
5aaca44d
IM		 4673 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4674 int err = 0;
4675 int idx = nid - EFFECT_START_NID;
4676
4677 if ((idx < 0) || (idx >= num_fx))
4678 return 0; /* no changed */
4679
4680 /* for out effect, qualify with PE */
4681 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4682 /* if PE if off, turn off out effects. */
4683 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4684 val = 0;
4685 }
4686
4687 /* for in effect, qualify with CrystalVoice */
4688 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4689 /* if CrystalVoice if off, turn off in effects. */
4690 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4691 val = 0;
4692
4693 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4694 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4695 val = 0;
009b8f97
CM		 4696
4697 /* If Voice Focus on SBZ, set to two channel. */
7cb9d94c
CM		 4698 if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
4699 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4700 if (spec->effects_switch[CRYSTAL_VOICE -
4701 EFFECT_START_NID]) {
4702
4703 if (spec->effects_switch[VOICE_FOCUS -
4704 EFFECT_START_NID]) {
4705 tmp = FLOAT_TWO;
4706 val = 1;
4707 } else
4708 tmp = FLOAT_ONE;
4709
4710 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4711 }
4712 }
4713 /*
4714 * For SBZ noise reduction, there's an extra command
4715 * to module ID 0x47. No clue why.
4716 */
7cb9d94c
CM		 4717 if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
4718 && (spec->cur_mic_type != REAR_LINE_IN)) {
009b8f97
CM		 4719 if (spec->effects_switch[CRYSTAL_VOICE -
4720 EFFECT_START_NID]) {
4721 if (spec->effects_switch[NOISE_REDUCTION -
4722 EFFECT_START_NID])
4723 tmp = FLOAT_ONE;
4724 else
4725 tmp = FLOAT_ZERO;
4726 } else
4727 tmp = FLOAT_ZERO;
4728
4729 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4730 }
7cb9d94c
CM		 4731
4732 /* If rear line in disable effects. */
4733 if (spec->use_alt_functions &&
4734 spec->in_enum_val == REAR_LINE_IN)
4735 val = 0;
5aaca44d
IM		 4736 }
4737
4e76a883 4738 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 4739 nid, val);
4740
4741 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4742 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4743 ca0132_effects[idx].reqs[0], on);
4744
4745 if (err < 0)
4746 return 0; /* no changed */
4747
4748 return 1;
4749}
4750
a7e76271
IM		 4751/*
4752 * Turn on/off Playback Enhancements
4753 */
4754static int ca0132_pe_switch_set(struct hda_codec *codec)
4755{
4756 struct ca0132_spec *spec = codec->spec;
4757 hda_nid_t nid;
4758 int i, ret = 0;
4759
4e76a883 4760 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 4761 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4762
7cb9d94c
CM		 4763 if (spec->use_alt_functions)
4764 ca0132_alt_select_out(codec);
4765
a7e76271
IM		 4766 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4767 nid = OUT_EFFECT_START_NID;
4768 /* PE affects all out effects */
4769 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4770 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4771
4772 return ret;
4773}
4774
5aaca44d
IM		 4775/* Check if Mic1 is streaming, if so, stop streaming */
4776static int stop_mic1(struct hda_codec *codec)
4777{
4778 struct ca0132_spec *spec = codec->spec;
4779 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4780 AC_VERB_GET_CONV, 0);
4781 if (oldval != 0)
4782 snd_hda_codec_write(codec, spec->adcs[0], 0,
4783 AC_VERB_SET_CHANNEL_STREAMID,
4784 0);
4785 return oldval;
4786}
4787
4788/* Resume Mic1 streaming if it was stopped. */
4789static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4790{
4791 struct ca0132_spec *spec = codec->spec;
4792 /* Restore the previous stream and channel */
4793 if (oldval != 0)
4794 snd_hda_codec_write(codec, spec->adcs[0], 0,
4795 AC_VERB_SET_CHANNEL_STREAMID,
4796 oldval);
4797}
4798
4799/*
a7e76271 4800 * Turn on/off CrystalVoice
5aaca44d 4801 */
a7e76271
IM		 4802static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4803{
4804 struct ca0132_spec *spec = codec->spec;
4805 hda_nid_t nid;
4806 int i, ret = 0;
4807 unsigned int oldval;
4808
4e76a883 4809 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 4810 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4811
4812 i = IN_EFFECT_START_NID - EFFECT_START_NID;
4813 nid = IN_EFFECT_START_NID;
4814 /* CrystalVoice affects all in effects */
4815 for (; nid < IN_EFFECT_END_NID; nid++, i++)
4816 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4817
4818 /* including VoiceFX */
4819 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4820
4821 /* set correct vipsource */
4822 oldval = stop_mic1(codec);
e0026d03
CM		 4823 if (spec->use_alt_functions)
4824 ret |= ca0132_alt_set_vipsource(codec, 1);
4825 else
4826 ret |= ca0132_set_vipsource(codec, 1);
a7e76271
IM		 4827 resume_mic1(codec, oldval);
4828 return ret;
4829}
4830
5aaca44d
IM		 4831static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4832{
4833 struct ca0132_spec *spec = codec->spec;
4834 int ret = 0;
4835
4836 if (val) /* on */
4837 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4838 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4839 else /* off */
4840 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4841 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4842
4843 return ret;
4844}
4845
47cdf76e
CM		 4846static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
4847{
4848 struct ca0132_spec *spec = codec->spec;
4849 int ret = 0;
4850
4851 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4852 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
4853 return ret;
4854}
4855
a7e76271
IM		 4856static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4857 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 4858{
a7e76271
IM		 4859 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4860 hda_nid_t nid = get_amp_nid(kcontrol);
4861 hda_nid_t shared_nid = 0;
4862 bool effective;
4863 int ret = 0;
95c6e9cb 4864 struct ca0132_spec *spec = codec->spec;
a7e76271 4865 int auto_jack;
95c6e9cb 4866
a7e76271
IM		 4867 if (nid == VNID_HP_SEL) {
4868 auto_jack =
4869 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
7cb9d94c
CM		 4870 if (!auto_jack) {
4871 if (spec->use_alt_functions)
4872 ca0132_alt_select_out(codec);
4873 else
4874 ca0132_select_out(codec);
4875 }
a7e76271
IM		 4876 return 1;
4877 }
95c6e9cb 4878
a7e76271
IM		 4879 if (nid == VNID_AMIC1_SEL) {
4880 auto_jack =
4881 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4882 if (!auto_jack)
4883 ca0132_select_mic(codec);
4884 return 1;
4885 }
95c6e9cb 4886
a7e76271 4887 if (nid == VNID_HP_ASEL) {
7cb9d94c
CM		 4888 if (spec->use_alt_functions)
4889 ca0132_alt_select_out(codec);
4890 else
4891 ca0132_select_out(codec);
a7e76271
IM		 4892 return 1;
4893 }
95c6e9cb 4894
a7e76271
IM		 4895 if (nid == VNID_AMIC1_ASEL) {
4896 ca0132_select_mic(codec);
4897 return 1;
95c6e9cb 4898 }
a7e76271
IM		 4899
4900 /* if effective conditions, then update hw immediately. */
4901 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
4902 if (effective) {
4903 int dir = get_amp_direction(kcontrol);
4904 int ch = get_amp_channels(kcontrol);
4905 unsigned long pval;
4906
4907 mutex_lock(&codec->control_mutex);
4908 pval = kcontrol->private_value;
4909 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
4910 0, dir);
4911 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
4912 kcontrol->private_value = pval;
4913 mutex_unlock(&codec->control_mutex);
95c6e9cb 4914 }
95c6e9cb 4915
a7e76271 4916 return ret;
95c6e9cb 4917}
a7e76271 4918/* End of control change helpers. */
47cdf76e
CM		 4919/*
4920 * Below I've added controls to mess with the effect levels, I've only enabled
4921 * them on the Sound Blaster Z, but they would probably also work on the
4922 * Chromebook. I figured they were probably tuned specifically for it, and left
4923 * out for a reason.
4924 */
4925
4926/* Sets DSP effect level from the sliders above the controls */
4927static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4928 const unsigned int *lookup, int idx)
4929{
4930 int i = 0;
4931 unsigned int y;
4932 /*
4933 * For X_BASS, req 2 is actually crossover freq instead of
4934 * effect level
4935 */
4936 if (nid == X_BASS)
4937 y = 2;
4938 else
4939 y = 1;
4940
4941 snd_hda_power_up(codec);
4942 if (nid == XBASS_XOVER) {
4943 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4944 if (ca0132_effects[i].nid == X_BASS)
4945 break;
4946
4947 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4948 ca0132_effects[i].reqs[1],
4949 &(lookup[idx - 1]), sizeof(unsigned int));
4950 } else {
4951 /* Find the actual effect structure */
4952 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4953 if (nid == ca0132_effects[i].nid)
4954 break;
4955
4956 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4957 ca0132_effects[i].reqs[y],
4958 &(lookup[idx]), sizeof(unsigned int));
4959 }
4960
4961 snd_hda_power_down(codec);
4962
4963 return 0;
4964}
4965
4966static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
4967 struct snd_ctl_elem_value *ucontrol)
4968{
4969 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4970 struct ca0132_spec *spec = codec->spec;
4971 long *valp = ucontrol->value.integer.value;
4972
4973 *valp = spec->xbass_xover_freq;
4974 return 0;
4975}
4976
4977static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
4978 struct snd_ctl_elem_value *ucontrol)
4979{
4980 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4981 struct ca0132_spec *spec = codec->spec;
4982 hda_nid_t nid = get_amp_nid(kcontrol);
4983 long *valp = ucontrol->value.integer.value;
4984 int idx = nid - OUT_EFFECT_START_NID;
4985
4986 *valp = spec->fx_ctl_val[idx];
4987 return 0;
4988}
4989
4990/*
4991 * The X-bass crossover starts at 10hz, so the min is 1. The
4992 * frequency is set in multiples of 10.
4993 */
4994static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
4995 struct snd_ctl_elem_info *uinfo)
4996{
4997 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4998 uinfo->count = 1;
4999 uinfo->value.integer.min = 1;
5000 uinfo->value.integer.max = 100;
5001 uinfo->value.integer.step = 1;
5002
5003 return 0;
5004}
5005
5006static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5007 struct snd_ctl_elem_info *uinfo)
5008{
5009 int chs = get_amp_channels(kcontrol);
5010
5011 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5012 uinfo->count = chs == 3 ? 2 : 1;
5013 uinfo->value.integer.min = 0;
5014 uinfo->value.integer.max = 100;
5015 uinfo->value.integer.step = 1;
5016
5017 return 0;
5018}
5019
5020static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5021 struct snd_ctl_elem_value *ucontrol)
5022{
5023 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5024 struct ca0132_spec *spec = codec->spec;
5025 hda_nid_t nid = get_amp_nid(kcontrol);
5026 long *valp = ucontrol->value.integer.value;
5027 int idx;
5028
5029 /* any change? */
5030 if (spec->xbass_xover_freq == *valp)
5031 return 0;
5032
5033 spec->xbass_xover_freq = *valp;
5034
5035 idx = *valp;
5036 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5037
5038 return 0;
5039}
5040
5041static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5042 struct snd_ctl_elem_value *ucontrol)
5043{
5044 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5045 struct ca0132_spec *spec = codec->spec;
5046 hda_nid_t nid = get_amp_nid(kcontrol);
5047 long *valp = ucontrol->value.integer.value;
5048 int idx;
5049
5050 idx = nid - EFFECT_START_NID;
5051 /* any change? */
5052 if (spec->fx_ctl_val[idx] == *valp)
5053 return 0;
5054
5055 spec->fx_ctl_val[idx] = *valp;
5056
5057 idx = *valp;
5058 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5059
5060 return 0;
5061}
5062
5063
5064/*
5065 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5066 * only has off or full 30 dB, and didn't like making a volume slider that has
5067 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5068 */
5069#define MIC_BOOST_NUM_OF_STEPS 4
5070#define MIC_BOOST_ENUM_MAX_STRLEN 10
5071
5072static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5073 struct snd_ctl_elem_info *uinfo)
5074{
5075 char *sfx = "dB";
5076 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5077
5078 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5079 uinfo->count = 1;
5080 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5081 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5082 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5083 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5084 strcpy(uinfo->value.enumerated.name, namestr);
5085 return 0;
5086}
5087
5088static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5089 struct snd_ctl_elem_value *ucontrol)
5090{
5091 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5092 struct ca0132_spec *spec = codec->spec;
5093
5094 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5095 return 0;
5096}
5097
5098static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5099 struct snd_ctl_elem_value *ucontrol)
5100{
5101 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5102 struct ca0132_spec *spec = codec->spec;
5103 int sel = ucontrol->value.enumerated.item[0];
5104 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5105
5106 if (sel >= items)
5107 return 0;
5108
5109 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5110 sel);
5111
5112 spec->mic_boost_enum_val = sel;
5113
5114 if (spec->in_enum_val != REAR_LINE_IN)
5115 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5116
5117 return 1;
5118}
5119
95c6e9cb 5120
7cb9d94c
CM		 5121/*
5122 * Input Select Control for alternative ca0132 codecs. This exists because
5123 * front microphone has no auto-detect, and we need a way to set the rear
5124 * as line-in
5125 */
5126static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5127 struct snd_ctl_elem_info *uinfo)
5128{
5129 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5130 uinfo->count = 1;
5131 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5132 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5133 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5134 strcpy(uinfo->value.enumerated.name,
5135 in_src_str[uinfo->value.enumerated.item]);
5136 return 0;
5137}
5138
5139static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5140 struct snd_ctl_elem_value *ucontrol)
5141{
5142 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5143 struct ca0132_spec *spec = codec->spec;
5144
5145 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5146 return 0;
5147}
5148
5149static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5150 struct snd_ctl_elem_value *ucontrol)
5151{
5152 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5153 struct ca0132_spec *spec = codec->spec;
5154 int sel = ucontrol->value.enumerated.item[0];
5155 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5156
5157 if (sel >= items)
5158 return 0;
5159
5160 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5161 sel, in_src_str[sel]);
5162
5163 spec->in_enum_val = sel;
5164
5165 ca0132_alt_select_in(codec);
5166
5167 return 1;
5168}
5169
5170/* Sound Blaster Z Output Select Control */
5171static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5172 struct snd_ctl_elem_info *uinfo)
5173{
5174 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5175 uinfo->count = 1;
5176 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5177 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5178 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5179 strcpy(uinfo->value.enumerated.name,
5180 alt_out_presets[uinfo->value.enumerated.item].name);
5181 return 0;
5182}
5183
5184static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5185 struct snd_ctl_elem_value *ucontrol)
5186{
5187 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5188 struct ca0132_spec *spec = codec->spec;
5189
5190 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5191 return 0;
5192}
5193
5194static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5195 struct snd_ctl_elem_value *ucontrol)
5196{
5197 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5198 struct ca0132_spec *spec = codec->spec;
5199 int sel = ucontrol->value.enumerated.item[0];
5200 unsigned int items = NUM_OF_OUTPUTS;
5201 unsigned int auto_jack;
5202
5203 if (sel >= items)
5204 return 0;
5205
5206 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5207 sel, alt_out_presets[sel].name);
5208
5209 spec->out_enum_val = sel;
5210
5211 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5212
5213 if (!auto_jack)
5214 ca0132_alt_select_out(codec);
5215
5216 return 1;
5217}
5218
47cdf76e
CM		 5219/*
5220 * Smart Volume output setting control. Three different settings, Normal,
5221 * which takes the value from the smart volume slider. The two others, loud
5222 * and night, disregard the slider value and have uneditable values.
5223 */
5224#define NUM_OF_SVM_SETTINGS 3
3a03f83b 5225static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
47cdf76e
CM		 5226
5227static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5228 struct snd_ctl_elem_info *uinfo)
5229{
5230 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5231 uinfo->count = 1;
5232 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5233 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5234 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5235 strcpy(uinfo->value.enumerated.name,
5236 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5237 return 0;
5238}
5239
5240static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5241 struct snd_ctl_elem_value *ucontrol)
5242{
5243 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5244 struct ca0132_spec *spec = codec->spec;
5245
5246 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5247 return 0;
5248}
5249
5250static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5251 struct snd_ctl_elem_value *ucontrol)
5252{
5253 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5254 struct ca0132_spec *spec = codec->spec;
5255 int sel = ucontrol->value.enumerated.item[0];
5256 unsigned int items = NUM_OF_SVM_SETTINGS;
5257 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5258 unsigned int tmp;
5259
5260 if (sel >= items)
5261 return 0;
5262
5263 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5264 sel, out_svm_set_enum_str[sel]);
5265
5266 spec->smart_volume_setting = sel;
5267
5268 switch (sel) {
5269 case 0:
5270 tmp = FLOAT_ZERO;
5271 break;
5272 case 1:
5273 tmp = FLOAT_ONE;
5274 break;
5275 case 2:
5276 tmp = FLOAT_TWO;
5277 break;
5278 default:
5279 tmp = FLOAT_ZERO;
5280 break;
5281 }
5282 /* Req 2 is the Smart Volume Setting req. */
5283 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5284 ca0132_effects[idx].reqs[2], tmp);
5285 return 1;
5286}
5287
5288/* Sound Blaster Z EQ preset controls */
5289static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5290 struct snd_ctl_elem_info *uinfo)
5291{
c5f13d75 5292 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5293
5294 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5295 uinfo->count = 1;
5296 uinfo->value.enumerated.items = items;
5297 if (uinfo->value.enumerated.item >= items)
5298 uinfo->value.enumerated.item = items - 1;
5299 strcpy(uinfo->value.enumerated.name,
5300 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5301 return 0;
5302}
5303
5304static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5305 struct snd_ctl_elem_value *ucontrol)
5306{
5307 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5308 struct ca0132_spec *spec = codec->spec;
5309
5310 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5311 return 0;
5312}
5313
5314static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5315 struct snd_ctl_elem_value *ucontrol)
5316{
5317 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5318 struct ca0132_spec *spec = codec->spec;
5319 int i, err = 0;
5320 int sel = ucontrol->value.enumerated.item[0];
c5f13d75 5321 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
47cdf76e
CM		 5322
5323 if (sel >= items)
5324 return 0;
5325
5326 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5327 ca0132_alt_eq_presets[sel].name);
5328 /*
5329 * Idx 0 is default.
5330 * Default needs to qualify with CrystalVoice state.
5331 */
5332 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5333 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5334 ca0132_alt_eq_enum.reqs[i],
5335 ca0132_alt_eq_presets[sel].vals[i]);
5336 if (err < 0)
5337 break;
5338 }
5339
5340 if (err >= 0)
5341 spec->eq_preset_val = sel;
5342
5343 return 1;
5344}
5345
a7e76271
IM		 5346static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5347 struct snd_ctl_elem_info *uinfo)
5348{
a9291f46 5349 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 5350
5351 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5352 uinfo->count = 1;
5353 uinfo->value.enumerated.items = items;
5354 if (uinfo->value.enumerated.item >= items)
5355 uinfo->value.enumerated.item = items - 1;
5356 strcpy(uinfo->value.enumerated.name,
5357 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5358 return 0;
5359}
95c6e9cb 5360
a7e76271 5361static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5362 struct snd_ctl_elem_value *ucontrol)
5363{
5364 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5365 struct ca0132_spec *spec = codec->spec;
95c6e9cb 5366
a7e76271 5367 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 5368 return 0;
5369}
5370
a7e76271 5371static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5372 struct snd_ctl_elem_value *ucontrol)
5373{
5374 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5375 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5376 int i, err = 0;
5377 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 5378
a9291f46 5379 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 5380 return 0;
5381
4e76a883 5382 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 5383 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 5384
a7e76271
IM		 5385 /*
5386 * Idx 0 is default.
5387 * Default needs to qualify with CrystalVoice state.
5388 */
5389 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5390 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5391 ca0132_voicefx.reqs[i],
5392 ca0132_voicefx_presets[sel].vals[i]);
5393 if (err < 0)
5394 break;
5395 }
95c6e9cb 5396
a7e76271
IM		 5397 if (err >= 0) {
5398 spec->voicefx_val = sel;
5399 /* enable voice fx */
5400 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5401 }
95c6e9cb 5402
a7e76271 5403 return 1;
95c6e9cb
IM		 5404}
5405
a7e76271
IM		 5406static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5407 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5408{
5409 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5410 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5411 hda_nid_t nid = get_amp_nid(kcontrol);
5412 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5413 long *valp = ucontrol->value.integer.value;
5414
a7e76271
IM		 5415 /* vnode */
5416 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5417 if (ch & 1) {
5418 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5419 valp++;
5420 }
5421 if (ch & 2) {
5422 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5423 valp++;
5424 }
5425 return 0;
5426 }
5427
5428 /* effects, include PE and CrystalVoice */
5429 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5430 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5431 return 0;
5432 }
5433
5434 /* mic boost */
5435 if (nid == spec->input_pins[0]) {
5436 *valp = spec->cur_mic_boost;
5437 return 0;
5438 }
5439
95c6e9cb
IM		 5440 return 0;
5441}
5442
a7e76271
IM		 5443static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5444 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 5445{
5446 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5447 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5448 hda_nid_t nid = get_amp_nid(kcontrol);
5449 int ch = get_amp_channels(kcontrol);
95c6e9cb 5450 long *valp = ucontrol->value.integer.value;
a7e76271 5451 int changed = 1;
95c6e9cb 5452
4e76a883 5453 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 5454 nid, *valp);
95c6e9cb
IM		 5455
5456 snd_hda_power_up(codec);
a7e76271
IM		 5457 /* vnode */
5458 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5459 if (ch & 1) {
5460 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5461 valp++;
5462 }
5463 if (ch & 2) {
5464 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5465 valp++;
5466 }
5467 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5468 goto exit;
5469 }
95c6e9cb 5470
a7e76271
IM		 5471 /* PE */
5472 if (nid == PLAY_ENHANCEMENT) {
5473 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5474 changed = ca0132_pe_switch_set(codec);
b97f6bfd 5475 goto exit;
a7e76271 5476 }
95c6e9cb 5477
a7e76271
IM		 5478 /* CrystalVoice */
5479 if (nid == CRYSTAL_VOICE) {
5480 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5481 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 5482 goto exit;
a7e76271 5483 }
95c6e9cb 5484
a7e76271
IM		 5485 /* out and in effects */
5486 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5487 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5488 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5489 changed = ca0132_effects_set(codec, nid, *valp);
5490 goto exit;
5491 }
5492
5493 /* mic boost */
5494 if (nid == spec->input_pins[0]) {
5495 spec->cur_mic_boost = *valp;
7cb9d94c
CM		 5496 if (spec->use_alt_functions) {
5497 if (spec->in_enum_val != REAR_LINE_IN)
5498 changed = ca0132_mic_boost_set(codec, *valp);
5499 } else {
5500 /* Mic boost does not apply to Digital Mic */
5501 if (spec->cur_mic_type != DIGITAL_MIC)
5502 changed = ca0132_mic_boost_set(codec, *valp);
5503 }
a7e76271 5504
a7e76271
IM		 5505 goto exit;
5506 }
95c6e9cb 5507
a7e76271 5508exit:
95c6e9cb 5509 snd_hda_power_down(codec);
a7e76271 5510 return changed;
95c6e9cb
IM		 5511}
5512
a7e76271
IM		 5513/*
5514 * Volume related
5515 */
017310fb
CM		 5516/*
5517 * Sets the internal DSP decibel level to match the DAC for output, and the
5518 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5519 * all alternative codecs set DSP playback volume.
5520 */
5521static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5522{
5523 struct ca0132_spec *spec = codec->spec;
5524 unsigned int dsp_dir;
5525 unsigned int lookup_val;
5526
5527 if (nid == VNID_SPK)
5528 dsp_dir = DSP_VOL_OUT;
5529 else
5530 dsp_dir = DSP_VOL_IN;
5531
5532 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5533
5534 dspio_set_uint_param(codec,
5535 ca0132_alt_vol_ctls[dsp_dir].mid,
5536 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5537 float_vol_db_lookup[lookup_val]);
5538
5539 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5540
5541 dspio_set_uint_param(codec,
5542 ca0132_alt_vol_ctls[dsp_dir].mid,
5543 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5544 float_vol_db_lookup[lookup_val]);
5545
5546 dspio_set_uint_param(codec,
5547 ca0132_alt_vol_ctls[dsp_dir].mid,
5548 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5549}
5550
a7e76271
IM		 5551static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5552 struct snd_ctl_elem_info *uinfo)
5553{
5554 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5555 struct ca0132_spec *spec = codec->spec;
5556 hda_nid_t nid = get_amp_nid(kcontrol);
5557 int ch = get_amp_channels(kcontrol);
5558 int dir = get_amp_direction(kcontrol);
5559 unsigned long pval;
5560 int err;
5561
5562 switch (nid) {
5563 case VNID_SPK:
5564 /* follow shared_out info */
5565 nid = spec->shared_out_nid;
5566 mutex_lock(&codec->control_mutex);
5567 pval = kcontrol->private_value;
5568 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5569 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5570 kcontrol->private_value = pval;
5571 mutex_unlock(&codec->control_mutex);
5572 break;
5573 case VNID_MIC:
5574 /* follow shared_mic info */
5575 nid = spec->shared_mic_nid;
5576 mutex_lock(&codec->control_mutex);
5577 pval = kcontrol->private_value;
5578 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5579 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5580 kcontrol->private_value = pval;
5581 mutex_unlock(&codec->control_mutex);
5582 break;
5583 default:
5584 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5585 }
5586 return err;
5587}
5588
5589static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5590 struct snd_ctl_elem_value *ucontrol)
5591{
5592 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5593 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5594 hda_nid_t nid = get_amp_nid(kcontrol);
5595 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 5596 long *valp = ucontrol->value.integer.value;
5597
a7e76271
IM		 5598 /* store the left and right volume */
5599 if (ch & 1) {
5600 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5601 valp++;
5602 }
5603 if (ch & 2) {
5604 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5605 valp++;
5606 }
95c6e9cb
IM		 5607 return 0;
5608}
5609
a7e76271 5610static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 5611 struct snd_ctl_elem_value *ucontrol)
5612{
5613 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5614 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 5615 hda_nid_t nid = get_amp_nid(kcontrol);
5616 int ch = get_amp_channels(kcontrol);
95c6e9cb 5617 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 5618 hda_nid_t shared_nid = 0;
5619 bool effective;
5620 int changed = 1;
5621
5622 /* store the left and right volume */
5623 if (ch & 1) {
5624 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5625 valp++;
5626 }
5627 if (ch & 2) {
5628 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5629 valp++;
5630 }
95c6e9cb 5631
a7e76271
IM		 5632 /* if effective conditions, then update hw immediately. */
5633 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5634 if (effective) {
5635 int dir = get_amp_direction(kcontrol);
5636 unsigned long pval;
5637
5638 snd_hda_power_up(codec);
5639 mutex_lock(&codec->control_mutex);
5640 pval = kcontrol->private_value;
5641 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5642 0, dir);
5643 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5644 kcontrol->private_value = pval;
5645 mutex_unlock(&codec->control_mutex);
5646 snd_hda_power_down(codec);
5647 }
95c6e9cb 5648
a7e76271 5649 return changed;
95c6e9cb
IM		 5650}
5651
017310fb
CM		 5652/*
5653 * This function is the same as the one above, because using an if statement
5654 * inside of the above volume control for the DSP volume would cause too much
5655 * lag. This is a lot more smooth.
5656 */
5657static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5658 struct snd_ctl_elem_value *ucontrol)
5659{
5660 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5661 struct ca0132_spec *spec = codec->spec;
5662 hda_nid_t nid = get_amp_nid(kcontrol);
5663 int ch = get_amp_channels(kcontrol);
5664 long *valp = ucontrol->value.integer.value;
5665 hda_nid_t vnid = 0;
5666 int changed = 1;
5667
5668 switch (nid) {
5669 case 0x02:
5670 vnid = VNID_SPK;
5671 break;
5672 case 0x07:
5673 vnid = VNID_MIC;
5674 break;
5675 }
5676
5677 /* store the left and right volume */
5678 if (ch & 1) {
5679 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5680 valp++;
5681 }
5682 if (ch & 2) {
5683 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5684 valp++;
5685 }
5686
5687 snd_hda_power_up(codec);
5688 ca0132_alt_dsp_volume_put(codec, vnid);
5689 mutex_lock(&codec->control_mutex);
5690 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5691 mutex_unlock(&codec->control_mutex);
5692 snd_hda_power_down(codec);
5693
5694 return changed;
5695}
5696
a7e76271
IM		 5697static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5698 unsigned int size, unsigned int __user *tlv)
95c6e9cb 5699{
a7e76271
IM		 5700 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5701 struct ca0132_spec *spec = codec->spec;
5702 hda_nid_t nid = get_amp_nid(kcontrol);
5703 int ch = get_amp_channels(kcontrol);
5704 int dir = get_amp_direction(kcontrol);
5705 unsigned long pval;
5706 int err;
5707
5708 switch (nid) {
5709 case VNID_SPK:
5710 /* follow shared_out tlv */
5711 nid = spec->shared_out_nid;
5712 mutex_lock(&codec->control_mutex);
5713 pval = kcontrol->private_value;
5714 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5715 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5716 kcontrol->private_value = pval;
5717 mutex_unlock(&codec->control_mutex);
5718 break;
5719 case VNID_MIC:
5720 /* follow shared_mic tlv */
5721 nid = spec->shared_mic_nid;
5722 mutex_lock(&codec->control_mutex);
5723 pval = kcontrol->private_value;
5724 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5725 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5726 kcontrol->private_value = pval;
5727 mutex_unlock(&codec->control_mutex);
5728 break;
5729 default:
5730 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5731 }
5732 return err;
95c6e9cb
IM		 5733}
5734
47cdf76e
CM		 5735/* Add volume slider control for effect level */
5736static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
5737 const char *pfx, int dir)
5738{
47cdf76e
CM		 5739 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5740 int type = dir ? HDA_INPUT : HDA_OUTPUT;
5741 struct snd_kcontrol_new knew =
5742 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
5743
0cc1aa71 5744 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
47cdf76e 5745
bb86124c 5746 knew.tlv.c = NULL;
47cdf76e
CM		 5747
5748 switch (nid) {
5749 case XBASS_XOVER:
5750 knew.info = ca0132_alt_xbass_xover_slider_info;
5751 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
5752 knew.put = ca0132_alt_xbass_xover_slider_put;
5753 break;
5754 default:
5755 knew.info = ca0132_alt_effect_slider_info;
5756 knew.get = ca0132_alt_slider_ctl_get;
5757 knew.put = ca0132_alt_effect_slider_put;
5758 knew.private_value =
5759 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
5760 break;
5761 }
5762
5763 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5764}
5765
5766/*
5767 * Added FX: prefix for the alternative codecs, because otherwise the surround
5768 * effect would conflict with the Surround sound volume control. Also seems more
5769 * clear as to what the switches do. Left alone for others.
5770 */
a7e76271
IM		 5771static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
5772 const char *pfx, int dir)
95c6e9cb 5773{
47cdf76e 5774 struct ca0132_spec *spec = codec->spec;
975cc02a 5775 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 5776 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 5777 struct snd_kcontrol_new knew =
a7e76271 5778 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
47cdf76e
CM		 5779 /* If using alt_controls, add FX: prefix. But, don't add FX:
5780 * prefix to OutFX or InFX enable controls.
5781 */
5782 if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
0cc1aa71 5783 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
47cdf76e
CM		 5784 else
5785 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
5786
95c6e9cb
IM		 5787 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5788}
5789
a7e76271 5790static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 5791{
5792 struct snd_kcontrol_new knew =
a7e76271
IM		 5793 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
5794 VOICEFX, 1, 0, HDA_INPUT);
5795 knew.info = ca0132_voicefx_info;
5796 knew.get = ca0132_voicefx_get;
5797 knew.put = ca0132_voicefx_put;
5798 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 5799}
5800
47cdf76e
CM		 5801/* Create the EQ Preset control */
5802static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
5803{
5804 struct snd_kcontrol_new knew =
5805 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
5806 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
5807 knew.info = ca0132_alt_eq_preset_info;
5808 knew.get = ca0132_alt_eq_preset_get;
5809 knew.put = ca0132_alt_eq_preset_put;
5810 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
5811 snd_ctl_new1(&knew, codec));
5812}
5813
5814/*
5815 * Add enumerated control for the three different settings of the smart volume
5816 * output effect. Normal just uses the slider value, and loud and night are
5817 * their own things that ignore that value.
5818 */
5819static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
5820{
5821 struct snd_kcontrol_new knew =
5822 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
5823 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
5824 knew.info = ca0132_alt_svm_setting_info;
5825 knew.get = ca0132_alt_svm_setting_get;
5826 knew.put = ca0132_alt_svm_setting_put;
5827 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
5828 snd_ctl_new1(&knew, codec));
5829
5830}
5831
7cb9d94c
CM		 5832/*
5833 * Create an Output Select enumerated control for codecs with surround
5834 * out capabilities.
5835 */
5836static int ca0132_alt_add_output_enum(struct hda_codec *codec)
5837{
5838 struct snd_kcontrol_new knew =
5839 HDA_CODEC_MUTE_MONO("Output Select",
5840 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
5841 knew.info = ca0132_alt_output_select_get_info;
5842 knew.get = ca0132_alt_output_select_get;
5843 knew.put = ca0132_alt_output_select_put;
5844 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
5845 snd_ctl_new1(&knew, codec));
5846}
5847
5848/*
5849 * Create an Input Source enumerated control for the alternate ca0132 codecs
5850 * because the front microphone has no auto-detect, and Line-in has to be set
5851 * somehow.
5852 */
5853static int ca0132_alt_add_input_enum(struct hda_codec *codec)
5854{
5855 struct snd_kcontrol_new knew =
5856 HDA_CODEC_MUTE_MONO("Input Source",
5857 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
5858 knew.info = ca0132_alt_input_source_info;
5859 knew.get = ca0132_alt_input_source_get;
5860 knew.put = ca0132_alt_input_source_put;
5861 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
5862 snd_ctl_new1(&knew, codec));
5863}
5864
47cdf76e
CM		 5865/*
5866 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
5867 * more control than the original mic boost, which is either full 30dB or off.
5868 */
5869static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
5870{
5871 struct snd_kcontrol_new knew =
5872 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
5873 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
5874 knew.info = ca0132_alt_mic_boost_info;
5875 knew.get = ca0132_alt_mic_boost_get;
5876 knew.put = ca0132_alt_mic_boost_put;
5877 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
5878 snd_ctl_new1(&knew, codec));
5879
5880}
5881
5882/*
5883 * Need to create slave controls for the alternate codecs that have surround
5884 * capabilities.
5885 */
5886static const char * const ca0132_alt_slave_pfxs[] = {
5887 "Front", "Surround", "Center", "LFE", NULL,
5888};
5889
5890/*
5891 * Also need special channel map, because the default one is incorrect.
5892 * I think this has to do with the pin for rear surround being 0x11,
5893 * and the center/lfe being 0x10. Usually the pin order is the opposite.
5894 */
9c4a665e 5895static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
47cdf76e
CM		 5896 { .channels = 2,
5897 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
5898 { .channels = 4,
5899 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5900 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5901 { .channels = 6,
5902 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5903 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
5904 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5905 { }
5906};
5907
5908/* Add the correct chmap for streams with 6 channels. */
5909static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
5910{
5911 int err = 0;
5912 struct hda_pcm *pcm;
5913
5914 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
5915 struct hda_pcm_stream *hinfo =
5916 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
5917 struct snd_pcm_chmap *chmap;
5918 const struct snd_pcm_chmap_elem *elem;
5919
5920 elem = ca0132_alt_chmaps;
5921 if (hinfo->channels_max == 6) {
5922 err = snd_pcm_add_chmap_ctls(pcm->pcm,
5923 SNDRV_PCM_STREAM_PLAYBACK,
5924 elem, hinfo->channels_max, 0, &chmap);
5925 if (err < 0)
5926 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
5927 }
5928 }
5929}
5930
a7e76271
IM		 5931/*
5932 * When changing Node IDs for Mixer Controls below, make sure to update
5933 * Node IDs in ca0132_config() as well.
5934 */
b0eaa072 5935static const struct snd_kcontrol_new ca0132_mixer[] = {
a7e76271
IM		 5936 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
5937 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
5938 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5939 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5940 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
5941 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
5942 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5943 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5944 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
5945 0x12, 1, HDA_INPUT),
5946 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
5947 VNID_HP_SEL, 1, HDA_OUTPUT),
5948 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
5949 VNID_AMIC1_SEL, 1, HDA_INPUT),
5950 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5951 VNID_HP_ASEL, 1, HDA_OUTPUT),
5952 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
5953 VNID_AMIC1_ASEL, 1, HDA_INPUT),
5954 { } /* end */
5955};
5956
017310fb 5957/*
e25e3445
CM		 5958 * Desktop specific control mixer. Removes auto-detect for mic, and adds
5959 * surround controls. Also sets both the Front Playback and Capture Volume
5960 * controls to alt so they set the DSP's decibel level.
017310fb 5961 */
e25e3445 5962static const struct snd_kcontrol_new desktop_mixer[] = {
017310fb
CM		 5963 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5964 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 5965 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5966 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5967 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5968 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5969 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5970 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 5971 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
5972 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5973 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5974 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5975 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5976 VNID_HP_ASEL, 1, HDA_OUTPUT),
5977 { } /* end */
5978};
5979
5980/*
5981 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
5982 * because it doesn't set decibel levels for the DSP for capture.
5983 */
b0eaa072 5984static const struct snd_kcontrol_new r3di_mixer[] = {
017310fb
CM		 5985 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5986 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
47cdf76e
CM		 5987 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5988 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5989 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5990 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5991 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5992 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
017310fb
CM		 5993 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5994 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5995 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5996 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5997 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5998 VNID_HP_ASEL, 1, HDA_OUTPUT),
5999 { } /* end */
6000};
6001
e90f29e4
IM		 6002static int ca0132_build_controls(struct hda_codec *codec)
6003{
6004 struct ca0132_spec *spec = codec->spec;
47cdf76e 6005 int i, num_fx, num_sliders;
e90f29e4
IM		 6006 int err = 0;
6007
6008 /* Add Mixer controls */
6009 for (i = 0; i < spec->num_mixers; i++) {
6010 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6011 if (err < 0)
6012 return err;
6013 }
47cdf76e
CM		 6014 /* Setup vmaster with surround slaves for desktop ca0132 devices */
6015 if (spec->use_alt_functions) {
6016 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6017 spec->tlv);
6018 snd_hda_add_vmaster(codec, "Master Playback Volume",
6019 spec->tlv, ca0132_alt_slave_pfxs,
6020 "Playback Volume");
6021 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
6022 NULL, ca0132_alt_slave_pfxs,
6023 "Playback Switch",
6024 true, &spec->vmaster_mute.sw_kctl);
6025
6026 }
e90f29e4
IM		 6027
6028 /* Add in and out effects controls.
6029 * VoiceFX, PE and CrystalVoice are added separately.
6030 */
6031 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6032 for (i = 0; i < num_fx; i++) {
e25e3445
CM		 6033 /* SBZ and R3D break if Echo Cancellation is used. */
6034 if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D) {
47cdf76e
CM		 6035 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
6036 OUT_EFFECTS_COUNT))
6037 continue;
6038 }
6039
e90f29e4
IM		 6040 err = add_fx_switch(codec, ca0132_effects[i].nid,
6041 ca0132_effects[i].name,
6042 ca0132_effects[i].direct);
6043 if (err < 0)
6044 return err;
6045 }
47cdf76e
CM		 6046 /*
6047 * If codec has use_alt_controls set to true, add effect level sliders,
6048 * EQ presets, and Smart Volume presets. Also, change names to add FX
6049 * prefix, and change PlayEnhancement and CrystalVoice to match.
6050 */
6051 if (spec->use_alt_controls) {
6052 ca0132_alt_add_svm_enum(codec);
6053 add_ca0132_alt_eq_presets(codec);
6054 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6055 "Enable OutFX", 0);
6056 if (err < 0)
6057 return err;
e90f29e4 6058
47cdf76e
CM		 6059 err = add_fx_switch(codec, CRYSTAL_VOICE,
6060 "Enable InFX", 1);
6061 if (err < 0)
6062 return err;
e90f29e4 6063
47cdf76e
CM		 6064 num_sliders = OUT_EFFECTS_COUNT - 1;
6065 for (i = 0; i < num_sliders; i++) {
6066 err = ca0132_alt_add_effect_slider(codec,
6067 ca0132_effects[i].nid,
6068 ca0132_effects[i].name,
6069 ca0132_effects[i].direct);
6070 if (err < 0)
6071 return err;
6072 }
6073
6074 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
6075 "X-Bass Crossover", EFX_DIR_OUT);
6076
6077 if (err < 0)
6078 return err;
6079 } else {
6080 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6081 "PlayEnhancement", 0);
6082 if (err < 0)
6083 return err;
e90f29e4 6084
47cdf76e
CM		 6085 err = add_fx_switch(codec, CRYSTAL_VOICE,
6086 "CrystalVoice", 1);
6087 if (err < 0)
6088 return err;
6089 }
e90f29e4
IM		 6090 add_voicefx(codec);
6091
7cb9d94c
CM		 6092 /*
6093 * If the codec uses alt_functions, you need the enumerated controls
6094 * to select the new outputs and inputs, plus add the new mic boost
6095 * setting control.
6096 */
6097 if (spec->use_alt_functions) {
6098 ca0132_alt_add_output_enum(codec);
6099 ca0132_alt_add_input_enum(codec);
47cdf76e 6100 ca0132_alt_add_mic_boost_enum(codec);
7cb9d94c 6101 }
e90f29e4
IM		 6102#ifdef ENABLE_TUNING_CONTROLS
6103 add_tuning_ctls(codec);
6104#endif
6105
6106 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
6107 if (err < 0)
6108 return err;
6109
6110 if (spec->dig_out) {
6111 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6112 spec->dig_out);
6113 if (err < 0)
6114 return err;
6115 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
6116 if (err < 0)
6117 return err;
6118 /* spec->multiout.share_spdif = 1; */
6119 }
6120
6121 if (spec->dig_in) {
6122 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6123 if (err < 0)
6124 return err;
6125 }
47cdf76e
CM		 6126
6127 if (spec->use_alt_functions)
6128 ca0132_alt_add_chmap_ctls(codec);
6129
e90f29e4
IM		 6130 return 0;
6131}
6132
a7e76271 6133/*
e90f29e4 6134 * PCM
a7e76271 6135 */
071f1344 6136static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 6137 .substreams = 1,
6138 .channels_min = 2,
825315bc 6139 .channels_max = 6,
a7e76271 6140 .ops = {
a7e76271 6141 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 6142 .cleanup = ca0132_playback_pcm_cleanup,
6143 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 6144 },
6145};
6146
071f1344 6147static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 6148 .substreams = 1,
6149 .channels_min = 2,
6150 .channels_max = 2,
825315bc
IM		 6151 .ops = {
6152 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 6153 .cleanup = ca0132_capture_pcm_cleanup,
6154 .get_delay = ca0132_capture_pcm_delay,
825315bc 6155 },
a7e76271
IM		 6156};
6157
071f1344 6158static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 6159 .substreams = 1,
6160 .channels_min = 2,
6161 .channels_max = 2,
6162 .ops = {
6163 .open = ca0132_dig_playback_pcm_open,
6164 .close = ca0132_dig_playback_pcm_close,
6165 .prepare = ca0132_dig_playback_pcm_prepare,
6166 .cleanup = ca0132_dig_playback_pcm_cleanup
6167 },
6168};
6169
071f1344 6170static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 6171 .substreams = 1,
6172 .channels_min = 2,
6173 .channels_max = 2,
6174};
6175
6176static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 6177{
6178 struct ca0132_spec *spec = codec->spec;
bbbc7e85 6179 struct hda_pcm *info;
a7e76271 6180
bbbc7e85
TI		 6181 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6182 if (!info)
6183 return -ENOMEM;
47cdf76e
CM		 6184 if (spec->use_alt_functions) {
6185 info->own_chmap = true;
6186 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6187 = ca0132_alt_chmaps;
6188 }
a7e76271
IM		 6189 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6190 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6191 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6192 spec->multiout.max_channels;
6193 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 6194 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 6195 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 6196
009b8f97 6197 /* With the DSP enabled, desktops don't use this ADC. */
5f8ddc6e 6198 if (!spec->use_alt_functions) {
009b8f97
CM		 6199 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6200 if (!info)
6201 return -ENOMEM;
6202 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6203 ca0132_pcm_analog_capture;
6204 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6205 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6206 }
825315bc 6207
bbbc7e85
TI		 6208 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6209 if (!info)
6210 return -ENOMEM;
825315bc
IM		 6211 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6212 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6213 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 6214
a7e76271
IM		 6215 if (!spec->dig_out && !spec->dig_in)
6216 return 0;
6217
bbbc7e85
TI		 6218 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6219 if (!info)
6220 return -ENOMEM;
a7e76271
IM		 6221 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6222 if (spec->dig_out) {
6223 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6224 ca0132_pcm_digital_playback;
6225 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6226 }
6227 if (spec->dig_in) {
6228 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6229 ca0132_pcm_digital_capture;
6230 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6231 }
95c6e9cb 6232
a7e76271 6233 return 0;
95c6e9cb
IM		 6234}
6235
441aa6a0
IM		 6236static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6237{
6238 if (pin) {
a0c041cb 6239 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 6240 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6241 snd_hda_codec_write(codec, pin, 0,
6242 AC_VERB_SET_AMP_GAIN_MUTE,
6243 AMP_OUT_UNMUTE);
6244 }
6245 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6246 snd_hda_codec_write(codec, dac, 0,
6247 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6248}
6249
6250static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6251{
6252 if (pin) {
a0c041cb 6253 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 6254 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6255 snd_hda_codec_write(codec, pin, 0,
6256 AC_VERB_SET_AMP_GAIN_MUTE,
6257 AMP_IN_UNMUTE(0));
6258 }
6259 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6260 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6261 AMP_IN_UNMUTE(0));
6262
6263 /* init to 0 dB and unmute. */
6264 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6265 HDA_AMP_VOLMASK, 0x5a);
6266 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6267 HDA_AMP_MUTE, 0);
6268 }
6269}
6270
5aaca44d
IM		 6271static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6272{
6273 unsigned int caps;
6274
6275 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6276 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6277 snd_hda_override_amp_caps(codec, nid, dir, caps);
6278}
6279
6280/*
6281 * Switch between Digital built-in mic and analog mic.
6282 */
6283static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6284{
6285 struct ca0132_spec *spec = codec->spec;
6286 unsigned int tmp;
6287 u8 val;
6288 unsigned int oldval;
6289
4e76a883 6290 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 6291
6292 oldval = stop_mic1(codec);
6293 ca0132_set_vipsource(codec, 0);
6294 if (enable) {
6295 /* set DMic input as 2-ch */
6296 tmp = FLOAT_TWO;
6297 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6298
6299 val = spec->dmic_ctl;
6300 val |= 0x80;
6301 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6302 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6303
6304 if (!(spec->dmic_ctl & 0x20))
6305 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6306 } else {
6307 /* set AMic input as mono */
6308 tmp = FLOAT_ONE;
6309 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6310
6311 val = spec->dmic_ctl;
6312 /* clear bit7 and bit5 to disable dmic */
6313 val &= 0x5f;
6314 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6315 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6316
6317 if (!(spec->dmic_ctl & 0x20))
6318 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6319 }
6320 ca0132_set_vipsource(codec, 1);
6321 resume_mic1(codec, oldval);
6322}
6323
6324/*
6325 * Initialization for Digital Mic.
6326 */
6327static void ca0132_init_dmic(struct hda_codec *codec)
6328{
6329 struct ca0132_spec *spec = codec->spec;
6330 u8 val;
6331
6332 /* Setup Digital Mic here, but don't enable.
6333 * Enable based on jack detect.
6334 */
6335
6336 /* MCLK uses MPIO1, set to enable.
6337 * Bit 2-0: MPIO select
6338 * Bit 3: set to disable
6339 * Bit 7-4: reserved
6340 */
6341 val = 0x01;
6342 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6343 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6344
6345 /* Data1 uses MPIO3. Data2 not use
6346 * Bit 2-0: Data1 MPIO select
6347 * Bit 3: set disable Data1
6348 * Bit 6-4: Data2 MPIO select
6349 * Bit 7: set disable Data2
6350 */
6351 val = 0x83;
6352 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6353 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6354
6355 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6356 * Bit 3-0: Channel mask
6357 * Bit 4: set for 48KHz, clear for 32KHz
6358 * Bit 5: mode
6359 * Bit 6: set to select Data2, clear for Data1
6360 * Bit 7: set to enable DMic, clear for AMic
6361 */
a57a46b9
AB		 6362 if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6363 val = 0x33;
6364 else
6365 val = 0x23;
5aaca44d
IM		 6366 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6367 spec->dmic_ctl = val;
6368 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6369 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6370}
6371
6372/*
6373 * Initialization for Analog Mic 2
6374 */
6375static void ca0132_init_analog_mic2(struct hda_codec *codec)
6376{
6377 struct ca0132_spec *spec = codec->spec;
6378
6379 mutex_lock(&spec->chipio_mutex);
6380 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6381 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6382 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6383 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6384 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6385 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6386 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6387 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6388 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6389 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6390 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6391 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6392 mutex_unlock(&spec->chipio_mutex);
6393}
6394
6395static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6396{
6397 struct ca0132_spec *spec = codec->spec;
6398 int i;
5aaca44d 6399
4e76a883 6400 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 6401 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 6402
6403 for (i = 0; i < spec->multiout.num_dacs; i++)
6404 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6405
6406 for (i = 0; i < spec->num_outputs; i++)
6407 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6408
6409 for (i = 0; i < spec->num_inputs; i++) {
6410 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6411 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6412 }
6413}
6414
7e6ed62e 6415/*
6ef0e91e
CM		 6416 * Creates a dummy stream to bind the output to. This seems to have to be done
6417 * after changing the main outputs source and destination streams.
7e6ed62e 6418 */
6ef0e91e 6419static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
447fd8e9 6420{
6ef0e91e
CM		 6421 struct ca0132_spec *spec = codec->spec;
6422 unsigned int stream_format;
447fd8e9 6423
6ef0e91e
CM		 6424 stream_format = snd_hdac_calc_stream_format(48000, 2,
6425 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
7e6ed62e 6426
6ef0e91e
CM		 6427 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6428 0, stream_format);
7e6ed62e 6429
6ef0e91e 6430 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
7e6ed62e
CM		 6431}
6432
38ba69ff 6433/*
6ef0e91e 6434 * Initialize mic for non-chromebook ca0132 implementations.
38ba69ff 6435 */
6ef0e91e 6436static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
38ba69ff 6437{
6ef0e91e 6438 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 6439 unsigned int tmp;
6440
6441 /* Mic 1 Setup */
6442 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6443 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6ef0e91e
CM		 6444 if (spec->quirk == QUIRK_R3DI) {
6445 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6446 tmp = FLOAT_ONE;
6447 } else
6448 tmp = FLOAT_THREE;
38ba69ff
CM		 6449 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6450
6ef0e91e 6451 /* Mic 2 setup (not present on desktop cards) */
38ba69ff
CM		 6452 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6453 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6ef0e91e
CM		 6454 if (spec->quirk == QUIRK_R3DI)
6455 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
38ba69ff
CM		 6456 tmp = FLOAT_ZERO;
6457 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
38ba69ff
CM		 6458}
6459
6460/*
6461 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6462 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6463 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6464 * having an updated DAC, which changes the destination to that DAC.
6465 */
6466static void sbz_connect_streams(struct hda_codec *codec)
6467{
6468 struct ca0132_spec *spec = codec->spec;
6469
6470 mutex_lock(&spec->chipio_mutex);
6471
6472 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6473
6474 chipio_set_stream_channels(codec, 0x0C, 6);
6475 chipio_set_stream_control(codec, 0x0C, 1);
6476
6477 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6478 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6479
6480 /* Setup stream 0x14 with it's source and destination points */
6481 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6482 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6483 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6484 chipio_set_stream_channels(codec, 0x14, 2);
6485 chipio_set_stream_control(codec, 0x14, 1);
6486
6487 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6488
6489 mutex_unlock(&spec->chipio_mutex);
38ba69ff
CM		 6490}
6491
6492/*
6493 * Write data through ChipIO to setup proper stream destinations.
6494 * Not sure how it exactly works, but it seems to direct data
6495 * to different destinations. Example is f8 to c0, e0 to c0.
6496 * All I know is, if you don't set these, you get no sound.
6497 */
6498static void sbz_chipio_startup_data(struct hda_codec *codec)
6499{
6500 struct ca0132_spec *spec = codec->spec;
6501
6502 mutex_lock(&spec->chipio_mutex);
6503 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6504
6505 /* These control audio output */
6506 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6507 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6508 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6509 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6510 /* Signal to update I think */
6511 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6512
6513 chipio_set_stream_channels(codec, 0x0C, 6);
6514 chipio_set_stream_control(codec, 0x0C, 1);
6515 /* No clue what these control */
6516 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6517 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6518 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6519 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6520 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6521 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6522 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6523 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6524 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6525 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6526 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6527 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6528
6529 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6530
6531 codec_dbg(codec, "Startup Data exited, mutex released.\n");
6532 mutex_unlock(&spec->chipio_mutex);
6533}
6534
447fd8e9 6535/*
6ef0e91e
CM		 6536 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
6537 * done after the DSP is loaded.
447fd8e9 6538 */
6ef0e91e 6539static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
447fd8e9 6540{
6ef0e91e 6541 struct ca0132_spec *spec = codec->spec;
447fd8e9
CM		 6542 unsigned int tmp;
6543
6ef0e91e
CM		 6544 switch (spec->quirk) {
6545 case QUIRK_SBZ:
6546 case QUIRK_AE5:
6547 tmp = 0x00000003;
6548 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6549 tmp = 0x00000000;
6550 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6551 tmp = 0x00000001;
6552 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6553 tmp = 0x00000004;
6554 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6555 tmp = 0x00000005;
6556 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6557 tmp = 0x00000000;
6558 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6559 break;
6560 case QUIRK_R3D:
6561 case QUIRK_R3DI:
6562 tmp = 0x00000000;
6563 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6564 tmp = 0x00000001;
6565 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6566 tmp = 0x00000004;
6567 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6568 tmp = 0x00000005;
6569 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6570 tmp = 0x00000000;
6571 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6572 break;
6573 }
447fd8e9
CM		 6574}
6575
6ef0e91e 6576static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
38ba69ff 6577{
6ef0e91e 6578 struct ca0132_spec *spec = codec->spec;
38ba69ff
CM		 6579 unsigned int tmp;
6580
6581 chipio_set_stream_control(codec, 0x03, 0);
6582 chipio_set_stream_control(codec, 0x04, 0);
6583
6584 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6585 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6586
6587 tmp = FLOAT_THREE;
6588 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6589
6590 chipio_set_stream_control(codec, 0x03, 1);
6591 chipio_set_stream_control(codec, 0x04, 1);
6592
6ef0e91e
CM		 6593 switch (spec->quirk) {
6594 case QUIRK_SBZ:
6595 chipio_write(codec, 0x18b098, 0x0000000c);
6596 chipio_write(codec, 0x18b09C, 0x0000000c);
6597 break;
6598 case QUIRK_AE5:
6599 chipio_write(codec, 0x18b098, 0x0000000c);
6600 chipio_write(codec, 0x18b09c, 0x0000004c);
6601 break;
6602 }
38ba69ff
CM		 6603}
6604
415cd844
CM		 6605static void ae5_post_dsp_register_set(struct hda_codec *codec)
6606{
6607 struct ca0132_spec *spec = codec->spec;
6608
6609 chipio_8051_write_direct(codec, 0x93, 0x10);
6610 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6611 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
6612 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6613 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
6614
6615 writeb(0xff, spec->mem_base + 0x304);
6616 writeb(0xff, spec->mem_base + 0x304);
6617 writeb(0xff, spec->mem_base + 0x304);
6618 writeb(0xff, spec->mem_base + 0x304);
6619 writeb(0x00, spec->mem_base + 0x100);
6620 writeb(0xff, spec->mem_base + 0x304);
6621 writeb(0x00, spec->mem_base + 0x100);
6622 writeb(0xff, spec->mem_base + 0x304);
6623 writeb(0x00, spec->mem_base + 0x100);
6624 writeb(0xff, spec->mem_base + 0x304);
6625 writeb(0x00, spec->mem_base + 0x100);
6626 writeb(0xff, spec->mem_base + 0x304);
6627
6628 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
6629 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
6630 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
6631}
6632
6633static void ae5_post_dsp_param_setup(struct hda_codec *codec)
6634{
6635 /*
6636 * Param3 in the 8051's memory is represented by the ascii string 'mch'
6637 * which seems to be 'multichannel'. This is also mentioned in the
6638 * AE-5's registry values in Windows.
6639 */
6640 chipio_set_control_param(codec, 3, 0);
6641 /*
6642 * I believe ASI is 'audio serial interface' and that it's used to
6643 * change colors on the external LED strip connected to the AE-5.
6644 */
6645 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
6646
6647 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
6648 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
6649
6650 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6651 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
6652 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6653 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
6654 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6655 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
6656}
6657
6658static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
6659{
6660 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6661 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
6662 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6663 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
6664
6665 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6666 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
6667 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6668 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
6669
6670 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6671 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
6672 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6673 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
6674
6675 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6676 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
6677 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6678 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
6679
6680 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6681 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
6682 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6683 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
6684}
6685
6686static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
6687{
6688 struct ca0132_spec *spec = codec->spec;
6689
6690 mutex_lock(&spec->chipio_mutex);
6691
6692 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
6693
6694 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
6695
6696 chipio_set_stream_channels(codec, 0x0C, 6);
6697 chipio_set_stream_control(codec, 0x0C, 1);
6698
6699 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
6700
6701 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
6702 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
6703 chipio_set_stream_channels(codec, 0x18, 6);
6704 chipio_set_stream_control(codec, 0x18, 1);
6705
6706 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
6707
6708 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6709 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
6710 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6711 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
6712
6713 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
6714
6715 mutex_unlock(&spec->chipio_mutex);
6716}
6717
6718static void ae5_post_dsp_startup_data(struct hda_codec *codec)
6719{
6720 struct ca0132_spec *spec = codec->spec;
6721
6722 mutex_lock(&spec->chipio_mutex);
6723
6724 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
6725 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
6726 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
6727 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
6728
6729 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
6730 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
6731 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
6732 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
6733 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
6734 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
6735 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
6736 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
6737 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
6738 ca0113_mmio_gpio_set(codec, 0, true);
6739 ca0113_mmio_gpio_set(codec, 1, true);
6740 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
6741
6742 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
6743
6744 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
6745 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
6746
6747 mutex_unlock(&spec->chipio_mutex);
6748}
6749
5aaca44d
IM		 6750/*
6751 * Setup default parameters for DSP
6752 */
6753static void ca0132_setup_defaults(struct hda_codec *codec)
6754{
e8f1bd5d 6755 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 6756 unsigned int tmp;
6757 int num_fx;
6758 int idx, i;
6759
e8f1bd5d 6760 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 6761 return;
6762
6763 /* out, in effects + voicefx */
6764 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6765 for (idx = 0; idx < num_fx; idx++) {
6766 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6767 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6768 ca0132_effects[idx].reqs[i],
6769 ca0132_effects[idx].def_vals[i]);
6770 }
6771 }
6772
6773 /*remove DSP headroom*/
6774 tmp = FLOAT_ZERO;
6775 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6776
6777 /*set speaker EQ bypass attenuation*/
6778 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
6779
6780 /* set AMic1 and AMic2 as mono mic */
6781 tmp = FLOAT_ONE;
6782 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6783 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6784
6785 /* set AMic1 as CrystalVoice input */
6786 tmp = FLOAT_ONE;
6787 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
6788
6789 /* set WUH source */
6790 tmp = FLOAT_TWO;
6791 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6792}
6793
7e6ed62e 6794/*
c986f50c 6795 * Setup default parameters for Recon3D/Recon3Di DSP.
7e6ed62e
CM		 6796 */
6797
c986f50c 6798static void r3d_setup_defaults(struct hda_codec *codec)
7e6ed62e
CM		 6799{
6800 struct ca0132_spec *spec = codec->spec;
6801 unsigned int tmp;
6802 int num_fx;
6803 int idx, i;
6804
6805 if (spec->dsp_state != DSP_DOWNLOADED)
6806 return;
6807
6ef0e91e
CM		 6808 ca0132_alt_dsp_scp_startup(codec);
6809 ca0132_alt_init_analog_mics(codec);
7e6ed62e
CM		 6810
6811 /*remove DSP headroom*/
6812 tmp = FLOAT_ZERO;
6813 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6814
6815 /* set WUH source */
6816 tmp = FLOAT_TWO;
6817 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6818 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6819
6820 /* Set speaker source? */
6821 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6822
c986f50c
CM		 6823 if (spec->quirk == QUIRK_R3DI)
6824 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
7e6ed62e
CM		 6825
6826 /* Setup effect defaults */
6827 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6828 for (idx = 0; idx < num_fx; idx++) {
6829 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6830 dspio_set_uint_param(codec,
6831 ca0132_effects[idx].mid,
6832 ca0132_effects[idx].reqs[i],
6833 ca0132_effects[idx].def_vals[i]);
6834 }
6835 }
7e6ed62e
CM		 6836}
6837
38ba69ff
CM		 6838/*
6839 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
6840 * than the Chromebook setup.
6841 */
6842static void sbz_setup_defaults(struct hda_codec *codec)
6843{
6844 struct ca0132_spec *spec = codec->spec;
6ef0e91e 6845 unsigned int tmp;
38ba69ff
CM		 6846 int num_fx;
6847 int idx, i;
6848
6849 if (spec->dsp_state != DSP_DOWNLOADED)
6850 return;
6851
6ef0e91e
CM		 6852 ca0132_alt_dsp_scp_startup(codec);
6853 ca0132_alt_init_analog_mics(codec);
38ba69ff 6854 sbz_connect_streams(codec);
38ba69ff
CM		 6855 sbz_chipio_startup_data(codec);
6856
6857 chipio_set_stream_control(codec, 0x03, 1);
6858 chipio_set_stream_control(codec, 0x04, 1);
6859
6860 /*
6861 * Sets internal input loopback to off, used to have a switch to
6862 * enable input loopback, but turned out to be way too buggy.
6863 */
6864 tmp = FLOAT_ONE;
6865 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
6866 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
6867
6868 /*remove DSP headroom*/
6869 tmp = FLOAT_ZERO;
6870 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6871
6872 /* set WUH source */
6873 tmp = FLOAT_TWO;
6874 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6875 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6876
6877 /* Set speaker source? */
6878 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6879
6ef0e91e 6880 ca0132_alt_dsp_initial_mic_setup(codec);
38ba69ff
CM		 6881
6882 /* out, in effects + voicefx */
6883 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6884 for (idx = 0; idx < num_fx; idx++) {
6885 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6886 dspio_set_uint_param(codec,
6887 ca0132_effects[idx].mid,
6888 ca0132_effects[idx].reqs[i],
6889 ca0132_effects[idx].def_vals[i]);
6890 }
6891 }
6892
6ef0e91e 6893 ca0132_alt_create_dummy_stream(codec);
38ba69ff
CM		 6894}
6895
415cd844
CM		 6896/*
6897 * Setup default parameters for the Sound BlasterX AE-5 DSP.
6898 */
6899static void ae5_setup_defaults(struct hda_codec *codec)
6900{
6901 struct ca0132_spec *spec = codec->spec;
6902 unsigned int tmp;
6903 int num_fx;
6904 int idx, i;
6905
6906 if (spec->dsp_state != DSP_DOWNLOADED)
6907 return;
6908
6909 ca0132_alt_dsp_scp_startup(codec);
6910 ca0132_alt_init_analog_mics(codec);
6911 chipio_set_stream_control(codec, 0x03, 1);
6912 chipio_set_stream_control(codec, 0x04, 1);
6913
6914 /* New, unknown SCP req's */
6915 tmp = FLOAT_ZERO;
6916 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
6917 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
6918 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
6919 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
6920
6921 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
6922 ca0113_mmio_gpio_set(codec, 0, false);
6923 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
6924
6925 /* Internal loopback off */
6926 tmp = FLOAT_ONE;
6927 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
6928 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
6929
6930 /*remove DSP headroom*/
6931 tmp = FLOAT_ZERO;
6932 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6933
6934 /* set WUH source */
6935 tmp = FLOAT_TWO;
6936 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6937 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6938
6939 /* Set speaker source? */
6940 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6941
6942 ca0132_alt_dsp_initial_mic_setup(codec);
6943 ae5_post_dsp_register_set(codec);
6944 ae5_post_dsp_param_setup(codec);
6945 ae5_post_dsp_pll_setup(codec);
6946 ae5_post_dsp_stream_setup(codec);
6947 ae5_post_dsp_startup_data(codec);
6948
6949 /* out, in effects + voicefx */
6950 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6951 for (idx = 0; idx < num_fx; idx++) {
6952 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6953 dspio_set_uint_param(codec,
6954 ca0132_effects[idx].mid,
6955 ca0132_effects[idx].reqs[i],
6956 ca0132_effects[idx].def_vals[i]);
6957 }
6958 }
6959
6960 ca0132_alt_create_dummy_stream(codec);
6961}
6962
5aaca44d
IM		 6963/*
6964 * Initialization of flags in chip
6965 */
6966static void ca0132_init_flags(struct hda_codec *codec)
6967{
009b8f97
CM		 6968 struct ca0132_spec *spec = codec->spec;
6969
6970 if (spec->use_alt_functions) {
6971 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
6972 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
6973 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
6974 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
6975 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
6976 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6977 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
6978 chipio_set_control_flag(codec,
6979 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6980 chipio_set_control_flag(codec,
6981 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
6982 } else {
6983 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6984 chipio_set_control_flag(codec,
6985 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
6986 chipio_set_control_flag(codec,
6987 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
6988 chipio_set_control_flag(codec,
6989 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
6990 chipio_set_control_flag(codec,
6991 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6992 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
6993 }
5aaca44d
IM		 6994}
6995
6996/*
6997 * Initialization of parameters in chip
6998 */
6999static void ca0132_init_params(struct hda_codec *codec)
7000{
009b8f97
CM		 7001 struct ca0132_spec *spec = codec->spec;
7002
7003 if (spec->use_alt_functions) {
7004 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7005 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
7006 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
7007 chipio_set_control_param(codec, 0, 0);
7008 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
7009 }
7010
5aaca44d
IM		 7011 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
7012 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
7013}
95c6e9cb 7014
e90f29e4
IM		 7015static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
7016{
7017 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
7018 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
7019 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
7020 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
7021 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
7022 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
7023
406261ce
IM		 7024 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7025 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 7026 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
7027}
7028
7029static bool ca0132_download_dsp_images(struct hda_codec *codec)
7030{
7031 bool dsp_loaded = false;
8a19bcee 7032 struct ca0132_spec *spec = codec->spec;
e90f29e4 7033 const struct dsp_image_seg *dsp_os_image;
15e4ba66 7034 const struct firmware *fw_entry;
8a19bcee
CM		 7035 /*
7036 * Alternate firmwares for different variants. The Recon3Di apparently
7037 * can use the default firmware, but I'll leave the option in case
7038 * it needs it again.
7039 */
7040 switch (spec->quirk) {
7041 case QUIRK_SBZ:
7a928186
CM		 7042 case QUIRK_R3D:
7043 case QUIRK_AE5:
7044 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
8a19bcee 7045 codec->card->dev) != 0) {
6ef0e91e 7046 codec_dbg(codec, "Desktop firmware not found.");
8a19bcee
CM		 7047 spec->alt_firmware_present = false;
7048 } else {
7a928186 7049 codec_dbg(codec, "Desktop firmware selected.");
8a19bcee
CM		 7050 spec->alt_firmware_present = true;
7051 }
7052 break;
7053 case QUIRK_R3DI:
7054 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
7055 codec->card->dev) != 0) {
7056 codec_dbg(codec, "Recon3Di alt firmware not detected.");
7057 spec->alt_firmware_present = false;
7058 } else {
7059 codec_dbg(codec, "Recon3Di firmware selected.");
7060 spec->alt_firmware_present = true;
7061 }
7062 break;
7063 default:
7064 spec->alt_firmware_present = false;
7065 break;
7066 }
7067 /*
7068 * Use default ctefx.bin if no alt firmware is detected, or if none
7069 * exists for your particular codec.
7070 */
7071 if (!spec->alt_firmware_present) {
7072 codec_dbg(codec, "Default firmware selected.");
7073 if (request_firmware(&fw_entry, EFX_FILE,
7074 codec->card->dev) != 0)
7075 return false;
7076 }
e90f29e4 7077
15e4ba66 7078 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 7079 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 7080 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 7081 goto exit_download;
7082 }
7083
e90f29e4
IM		 7084 dsp_loaded = dspload_wait_loaded(codec);
7085
d1d28500 7086exit_download:
15e4ba66
TI		 7087 release_firmware(fw_entry);
7088
e90f29e4
IM		 7089 return dsp_loaded;
7090}
7091
7092static void ca0132_download_dsp(struct hda_codec *codec)
7093{
7094 struct ca0132_spec *spec = codec->spec;
7095
9a0869f4
TI		 7096#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
7097 return; /* NOP */
7098#endif
e90f29e4 7099
e24aa0a4
TI		 7100 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
7101 return; /* don't retry failures */
7102
b714a710 7103 chipio_enable_clocks(codec);
e93ac30a
CM		 7104 if (spec->dsp_state != DSP_DOWNLOADED) {
7105 spec->dsp_state = DSP_DOWNLOADING;
7106
7107 if (!ca0132_download_dsp_images(codec))
7108 spec->dsp_state = DSP_DOWNLOAD_FAILED;
7109 else
7110 spec->dsp_state = DSP_DOWNLOADED;
7111 }
e90f29e4 7112
009b8f97
CM		 7113 /* For codecs using alt functions, this is already done earlier */
7114 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
e90f29e4
IM		 7115 ca0132_set_dsp_msr(codec, true);
7116}
7117
f8fb1170
TI		 7118static void ca0132_process_dsp_response(struct hda_codec *codec,
7119 struct hda_jack_callback *callback)
e90f29e4
IM		 7120{
7121 struct ca0132_spec *spec = codec->spec;
7122
4e76a883 7123 codec_dbg(codec, "ca0132_process_dsp_response\n");
e90f29e4
IM		 7124 if (spec->wait_scp) {
7125 if (dspio_get_response_data(codec) >= 0)
7126 spec->wait_scp = 0;
7127 }
7128
7129 dspio_clear_response_queue(codec);
7130}
7131
f8fb1170 7132static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 7133{
993884f6 7134 struct ca0132_spec *spec = codec->spec;
2ebab40e 7135 struct hda_jack_tbl *tbl;
e90f29e4 7136
f8fb1170
TI		 7137 /* Delay enabling the HP amp, to let the mic-detection
7138 * state machine run.
7139 */
7140 cancel_delayed_work_sync(&spec->unsol_hp_work);
2f35c630 7141 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 7142 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
7143 if (tbl)
7144 tbl->block_report = 1;
f8fb1170
TI		 7145}
7146
7147static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
7148{
a1b7f016
CM		 7149 struct ca0132_spec *spec = codec->spec;
7150
7151 if (spec->use_alt_functions)
7152 ca0132_alt_select_in(codec);
7153 else
7154 ca0132_select_mic(codec);
f8fb1170
TI		 7155}
7156
7157static void ca0132_init_unsol(struct hda_codec *codec)
7158{
d5c016b5
GM		 7159 struct ca0132_spec *spec = codec->spec;
7160 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
7161 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 7162 amic_callback);
7163 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
7164 ca0132_process_dsp_response);
63177afc 7165 /* Front headphone jack detection */
009b8f97 7166 if (spec->use_alt_functions)
63177afc
CM		 7167 snd_hda_jack_detect_enable_callback(codec,
7168 spec->unsol_tag_front_hp, hp_callback);
e90f29e4
IM		 7169}
7170
5aaca44d
IM		 7171/*
7172 * Verbs tables.
7173 */
7174
7175/* Sends before DSP download. */
7176static struct hda_verb ca0132_base_init_verbs[] = {
7177 /*enable ct extension*/
7178 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 7179 {}
7180};
7181
7182/* Send at exit. */
7183static struct hda_verb ca0132_base_exit_verbs[] = {
7184 /*set afg to D3*/
7185 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
7186 /*disable ct extension*/
7187 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
7188 {}
7189};
7190
8a19bcee 7191/* Other verbs tables. Sends after DSP download. */
e93ac30a 7192
5aaca44d
IM		 7193static struct hda_verb ca0132_init_verbs0[] = {
7194 /* chip init verbs */
7195 {0x15, 0x70D, 0xF0},
7196 {0x15, 0x70E, 0xFE},
7197 {0x15, 0x707, 0x75},
7198 {0x15, 0x707, 0xD3},
7199 {0x15, 0x707, 0x09},
7200 {0x15, 0x707, 0x53},
7201 {0x15, 0x707, 0xD4},
7202 {0x15, 0x707, 0xEF},
7203 {0x15, 0x707, 0x75},
7204 {0x15, 0x707, 0xD3},
7205 {0x15, 0x707, 0x09},
7206 {0x15, 0x707, 0x02},
7207 {0x15, 0x707, 0x37},
7208 {0x15, 0x707, 0x78},
7209 {0x15, 0x53C, 0xCE},
7210 {0x15, 0x575, 0xC9},
7211 {0x15, 0x53D, 0xCE},
7212 {0x15, 0x5B7, 0xC9},
7213 {0x15, 0x70D, 0xE8},
7214 {0x15, 0x70E, 0xFE},
7215 {0x15, 0x707, 0x02},
7216 {0x15, 0x707, 0x68},
7217 {0x15, 0x707, 0x62},
7218 {0x15, 0x53A, 0xCE},
7219 {0x15, 0x546, 0xC9},
7220 {0x15, 0x53B, 0xCE},
7221 {0x15, 0x5E8, 0xC9},
e93ac30a
CM		 7222 {}
7223};
7224
e42c7c73
CM		 7225/* Extra init verbs for desktop cards. */
7226static struct hda_verb ca0132_init_verbs1[] = {
e93ac30a
CM		 7227 {0x15, 0x70D, 0x20},
7228 {0x15, 0x70E, 0x19},
7229 {0x15, 0x707, 0x00},
7230 {0x15, 0x539, 0xCE},
7231 {0x15, 0x546, 0xC9},
7232 {0x15, 0x70D, 0xB7},
7233 {0x15, 0x70E, 0x09},
7234 {0x15, 0x707, 0x10},
7235 {0x15, 0x70D, 0xAF},
7236 {0x15, 0x70E, 0x09},
7237 {0x15, 0x707, 0x01},
7238 {0x15, 0x707, 0x05},
7239 {0x15, 0x70D, 0x73},
7240 {0x15, 0x70E, 0x09},
7241 {0x15, 0x707, 0x14},
7242 {0x15, 0x6FF, 0xC4},
5aaca44d
IM		 7243 {}
7244};
7245
95c6e9cb
IM		 7246static void ca0132_init_chip(struct hda_codec *codec)
7247{
7248 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 7249 int num_fx;
7250 int i;
7251 unsigned int on;
95c6e9cb
IM		 7252
7253 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 7254
7255 spec->cur_out_type = SPEAKER_OUT;
7cb9d94c
CM		 7256 if (!spec->use_alt_functions)
7257 spec->cur_mic_type = DIGITAL_MIC;
7258 else
7259 spec->cur_mic_type = REAR_MIC;
7260
5aaca44d
IM		 7261 spec->cur_mic_boost = 0;
7262
7263 for (i = 0; i < VNODES_COUNT; i++) {
7264 spec->vnode_lvol[i] = 0x5a;
7265 spec->vnode_rvol[i] = 0x5a;
7266 spec->vnode_lswitch[i] = 0;
7267 spec->vnode_rswitch[i] = 0;
7268 }
7269
7270 /*
7271 * Default states for effects are in ca0132_effects[].
7272 */
7273 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7274 for (i = 0; i < num_fx; i++) {
7275 on = (unsigned int)ca0132_effects[i].reqs[0];
7276 spec->effects_switch[i] = on ? 1 : 0;
7277 }
47cdf76e
CM		 7278 /*
7279 * Sets defaults for the effect slider controls, only for alternative
7280 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
7281 */
7282 if (spec->use_alt_controls) {
7283 spec->xbass_xover_freq = 8;
7284 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
7285 spec->fx_ctl_val[i] = effect_slider_defaults[i];
7286 }
5aaca44d
IM		 7287
7288 spec->voicefx_val = 0;
7289 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
7290 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
7291
44f0c978
IM		 7292#ifdef ENABLE_TUNING_CONTROLS
7293 ca0132_init_tuning_defaults(codec);
7294#endif
95c6e9cb
IM		 7295}
7296
2e48b2b7
CM		 7297/*
7298 * Recon3Di exit specific commands.
7299 */
7300/* prevents popping noise on shutdown */
7301static void r3di_gpio_shutdown(struct hda_codec *codec)
7302{
7303 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
7304}
7305
7306/*
7307 * Sound Blaster Z exit specific commands.
7308 */
7309static void sbz_region2_exit(struct hda_codec *codec)
7310{
7311 struct ca0132_spec *spec = codec->spec;
7312 unsigned int i;
7313
7314 for (i = 0; i < 4; i++)
7315 writeb(0x0, spec->mem_base + 0x100);
7316 for (i = 0; i < 8; i++)
7317 writeb(0xb3, spec->mem_base + 0x304);
a62e4739 7318
b9b41345
CM		 7319 ca0113_mmio_gpio_set(codec, 0, false);
7320 ca0113_mmio_gpio_set(codec, 1, false);
7321 ca0113_mmio_gpio_set(codec, 4, true);
7322 ca0113_mmio_gpio_set(codec, 5, false);
7323 ca0113_mmio_gpio_set(codec, 7, false);
2e48b2b7
CM		 7324}
7325
7326static void sbz_set_pin_ctl_default(struct hda_codec *codec)
7327{
7328 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
7329 unsigned int i;
7330
7331 snd_hda_codec_write(codec, 0x11, 0,
7332 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
7333
7334 for (i = 0; i < 5; i++)
7335 snd_hda_codec_write(codec, pins[i], 0,
7336 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
7337}
7338
2f295f91 7339static void ca0132_clear_unsolicited(struct hda_codec *codec)
2e48b2b7
CM		 7340{
7341 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
7342 unsigned int i;
7343
7344 for (i = 0; i < 7; i++) {
7345 snd_hda_codec_write(codec, pins[i], 0,
7346 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
7347 }
7348}
7349
7350/* On shutdown, sends commands in sets of three */
7351static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
7352 int mask, int data)
7353{
7354 if (dir >= 0)
7355 snd_hda_codec_write(codec, 0x01, 0,
7356 AC_VERB_SET_GPIO_DIRECTION, dir);
7357 if (mask >= 0)
7358 snd_hda_codec_write(codec, 0x01, 0,
7359 AC_VERB_SET_GPIO_MASK, mask);
7360
7361 if (data >= 0)
7362 snd_hda_codec_write(codec, 0x01, 0,
7363 AC_VERB_SET_GPIO_DATA, data);
7364}
7365
7366static void sbz_exit_chip(struct hda_codec *codec)
7367{
009b8f97
CM		 7368 chipio_set_stream_control(codec, 0x03, 0);
7369 chipio_set_stream_control(codec, 0x04, 0);
2e48b2b7
CM		 7370
7371 /* Mess with GPIO */
7372 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7373 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7374 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7375
009b8f97
CM		 7376 chipio_set_stream_control(codec, 0x14, 0);
7377 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7378
7379 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7380 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7381
7382 chipio_write(codec, 0x18a020, 0x00000083);
7383
7384 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7385 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7386 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7387
009b8f97 7388 chipio_set_stream_control(codec, 0x0C, 0);
2e48b2b7
CM		 7389
7390 chipio_set_control_param(codec, 0x0D, 0x24);
7391
2f295f91 7392 ca0132_clear_unsolicited(codec);
2e48b2b7
CM		 7393 sbz_set_pin_ctl_default(codec);
7394
7395 snd_hda_codec_write(codec, 0x0B, 0,
7396 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7397
2e48b2b7
CM		 7398 sbz_region2_exit(codec);
7399}
7400
2f295f91
CM		 7401static void r3d_exit_chip(struct hda_codec *codec)
7402{
7403 ca0132_clear_unsolicited(codec);
7404 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7405 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7406}
7407
95c6e9cb
IM		 7408static void ca0132_exit_chip(struct hda_codec *codec)
7409{
7410 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 7411
7412 if (dspload_is_loaded(codec))
7413 dsp_reset(codec);
95c6e9cb
IM		 7414}
7415
38ba69ff
CM		 7416/*
7417 * This fixes a problem that was hard to reproduce. Very rarely, I would
7418 * boot up, and there would be no sound, but the DSP indicated it had loaded
7419 * properly. I did a few memory dumps to see if anything was different, and
7420 * there were a few areas of memory uninitialized with a1a2a3a4. This function
7421 * checks if those areas are uninitialized, and if they are, it'll attempt to
7422 * reload the card 3 times. Usually it fixes by the second.
7423 */
7424static void sbz_dsp_startup_check(struct hda_codec *codec)
7425{
7426 struct ca0132_spec *spec = codec->spec;
7427 unsigned int dsp_data_check[4];
7428 unsigned int cur_address = 0x390;
7429 unsigned int i;
7430 unsigned int failure = 0;
7431 unsigned int reload = 3;
7432
7433 if (spec->startup_check_entered)
7434 return;
7435
7436 spec->startup_check_entered = true;
7437
7438 for (i = 0; i < 4; i++) {
7439 chipio_read(codec, cur_address, &dsp_data_check[i]);
7440 cur_address += 0x4;
7441 }
7442 for (i = 0; i < 4; i++) {
7443 if (dsp_data_check[i] == 0xa1a2a3a4)
7444 failure = 1;
7445 }
7446
7447 codec_dbg(codec, "Startup Check: %d ", failure);
7448 if (failure)
7449 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7450 /*
7451 * While the failure condition is true, and we haven't reached our
7452 * three reload limit, continue trying to reload the driver and
7453 * fix the issue.
7454 */
7455 while (failure && (reload != 0)) {
7456 codec_info(codec, "Reloading... Tries left: %d", reload);
7457 sbz_exit_chip(codec);
7458 spec->dsp_state = DSP_DOWNLOAD_INIT;
7459 codec->patch_ops.init(codec);
7460 failure = 0;
7461 for (i = 0; i < 4; i++) {
7462 chipio_read(codec, cur_address, &dsp_data_check[i]);
7463 cur_address += 0x4;
7464 }
7465 for (i = 0; i < 4; i++) {
7466 if (dsp_data_check[i] == 0xa1a2a3a4)
7467 failure = 1;
7468 }
7469 reload--;
7470 }
7471
7472 if (!failure && reload < 3)
7473 codec_info(codec, "DSP fixed.");
7474
7475 if (!failure)
7476 return;
7477
7478 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7479}
7480
e93ac30a
CM		 7481/*
7482 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7483 * extra precision for decibel values. If you had the dB value in floating point
7484 * you would take the value after the decimal point, multiply by 64, and divide
7485 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7486 * implement fixed point or floating point dB volumes. For now, I'll set them
7487 * to 0 just incase a value has lingered from a boot into Windows.
7488 */
7489static void ca0132_alt_vol_setup(struct hda_codec *codec)
7490{
7491 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7492 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7493 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7494 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7495 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7496 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7497 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7498 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7499}
7500
7501/*
7502 * Extra commands that don't really fit anywhere else.
7503 */
7504static void sbz_pre_dsp_setup(struct hda_codec *codec)
7505{
7506 struct ca0132_spec *spec = codec->spec;
7507
7508 writel(0x00820680, spec->mem_base + 0x01C);
7509 writel(0x00820680, spec->mem_base + 0x01C);
7510
e93ac30a
CM		 7511 chipio_write(codec, 0x18b0a4, 0x000000c2);
7512
7513 snd_hda_codec_write(codec, 0x11, 0,
7514 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7515}
7516
e42c7c73
CM		 7517static void r3d_pre_dsp_setup(struct hda_codec *codec)
7518{
e42c7c73
CM		 7519 chipio_write(codec, 0x18b0a4, 0x000000c2);
7520
7521 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7522 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7523 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7524 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7525 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7526 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7527
7528 snd_hda_codec_write(codec, 0x11, 0,
7529 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7530}
7531
e93ac30a
CM		 7532static void r3di_pre_dsp_setup(struct hda_codec *codec)
7533{
7534 chipio_write(codec, 0x18b0a4, 0x000000c2);
7535
7536 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7537 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7538 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7539 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7540 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7541 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7542
7543 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7544 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7545 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7546 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7547 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7548 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7549 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7550 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
7551
7552 snd_hda_codec_write(codec, 0x11, 0,
7553 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
7554}
7555
e93ac30a
CM		 7556/*
7557 * These are sent before the DSP is downloaded. Not sure
7558 * what they do, or if they're necessary. Could possibly
7559 * be removed. Figure they're better to leave in.
7560 */
e42c7c73 7561static void ca0132_mmio_init(struct hda_codec *codec)
e93ac30a
CM		 7562{
7563 struct ca0132_spec *spec = codec->spec;
7564
ce715448
CM		 7565 if (spec->quirk == QUIRK_AE5)
7566 writel(0x00000001, spec->mem_base + 0x400);
7567 else
7568 writel(0x00000000, spec->mem_base + 0x400);
7569
7570 if (spec->quirk == QUIRK_AE5)
7571 writel(0x00000001, spec->mem_base + 0x408);
7572 else
7573 writel(0x00000000, spec->mem_base + 0x408);
7574
7575 if (spec->quirk == QUIRK_AE5)
7576 writel(0x00000001, spec->mem_base + 0x40c);
7577 else
7578 writel(0x00000000, spec->mem_base + 0x40C);
7579
e93ac30a 7580 writel(0x00880680, spec->mem_base + 0x01C);
ce715448
CM		 7581
7582 if (spec->quirk == QUIRK_AE5)
7583 writel(0x00000080, spec->mem_base + 0xC0C);
7584 else
7585 writel(0x00000083, spec->mem_base + 0xC0C);
7586
e93ac30a
CM		 7587 writel(0x00000030, spec->mem_base + 0xC00);
7588 writel(0x00000000, spec->mem_base + 0xC04);
ce715448
CM		 7589
7590 if (spec->quirk == QUIRK_AE5)
7591 writel(0x00000000, spec->mem_base + 0xC0C);
7592 else
7593 writel(0x00000003, spec->mem_base + 0xC0C);
7594
e93ac30a
CM		 7595 writel(0x00000003, spec->mem_base + 0xC0C);
7596 writel(0x00000003, spec->mem_base + 0xC0C);
7597 writel(0x00000003, spec->mem_base + 0xC0C);
ce715448
CM		 7598
7599 if (spec->quirk == QUIRK_AE5)
7600 writel(0x00000001, spec->mem_base + 0xC08);
7601 else
7602 writel(0x000000C1, spec->mem_base + 0xC08);
7603
e93ac30a
CM		 7604 writel(0x000000F1, spec->mem_base + 0xC08);
7605 writel(0x00000001, spec->mem_base + 0xC08);
7606 writel(0x000000C7, spec->mem_base + 0xC08);
7607 writel(0x000000C1, spec->mem_base + 0xC08);
7608 writel(0x00000080, spec->mem_base + 0xC04);
ce715448
CM		 7609
7610 if (spec->quirk == QUIRK_AE5) {
7611 writel(0x00000000, spec->mem_base + 0x42c);
7612 writel(0x00000000, spec->mem_base + 0x46c);
7613 writel(0x00000000, spec->mem_base + 0x4ac);
7614 writel(0x00000000, spec->mem_base + 0x4ec);
7615 writel(0x00000000, spec->mem_base + 0x43c);
7616 writel(0x00000000, spec->mem_base + 0x47c);
7617 writel(0x00000000, spec->mem_base + 0x4bc);
7618 writel(0x00000000, spec->mem_base + 0x4fc);
7619 writel(0x00000600, spec->mem_base + 0x100);
7620 writel(0x00000014, spec->mem_base + 0x410);
7621 writel(0x0000060f, spec->mem_base + 0x100);
7622 writel(0x0000070f, spec->mem_base + 0x100);
7623 writel(0x00000aff, spec->mem_base + 0x830);
7624 writel(0x00000000, spec->mem_base + 0x86c);
7625 writel(0x0000006b, spec->mem_base + 0x800);
7626 writel(0x00000001, spec->mem_base + 0x86c);
7627 writel(0x0000006b, spec->mem_base + 0x800);
7628 writel(0x00000057, spec->mem_base + 0x804);
7629 writel(0x00800000, spec->mem_base + 0x20c);
7630 }
e93ac30a
CM		 7631}
7632
b9b41345
CM		 7633/*
7634 * This function writes to some SFR's, does some region2 writes, and then
7635 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
7636 * what it does.
7637 */
7638static void ae5_register_set(struct hda_codec *codec)
7639{
7640 struct ca0132_spec *spec = codec->spec;
7641
7642 chipio_8051_write_direct(codec, 0x93, 0x10);
7643 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7644 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
7645 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7646 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
7647
7648 writeb(0x0f, spec->mem_base + 0x304);
7649 writeb(0x0f, spec->mem_base + 0x304);
7650 writeb(0x0f, spec->mem_base + 0x304);
7651 writeb(0x0f, spec->mem_base + 0x304);
7652 writeb(0x0e, spec->mem_base + 0x100);
7653 writeb(0x1f, spec->mem_base + 0x304);
7654 writeb(0x0c, spec->mem_base + 0x100);
7655 writeb(0x3f, spec->mem_base + 0x304);
7656 writeb(0x08, spec->mem_base + 0x100);
7657 writeb(0x7f, spec->mem_base + 0x304);
7658 writeb(0x00, spec->mem_base + 0x100);
7659 writeb(0xff, spec->mem_base + 0x304);
7660
7661 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7662
7663 chipio_8051_write_direct(codec, 0x90, 0x00);
7664 chipio_8051_write_direct(codec, 0x90, 0x10);
7665
7666 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7667
7668 chipio_write(codec, 0x18b0a4, 0x000000c2);
7669
7670 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
7671 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
7672}
7673
e93ac30a
CM		 7674/*
7675 * Extra init functions for alternative ca0132 codecs. Done
7676 * here so they don't clutter up the main ca0132_init function
7677 * anymore than they have to.
7678 */
7679static void ca0132_alt_init(struct hda_codec *codec)
7680{
7681 struct ca0132_spec *spec = codec->spec;
7682
7683 ca0132_alt_vol_setup(codec);
7684
7685 switch (spec->quirk) {
7686 case QUIRK_SBZ:
7687 codec_dbg(codec, "SBZ alt_init");
7688 ca0132_gpio_init(codec);
7689 sbz_pre_dsp_setup(codec);
7690 snd_hda_sequence_write(codec, spec->chip_init_verbs);
e42c7c73 7691 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
e93ac30a
CM		 7692 break;
7693 case QUIRK_R3DI:
7694 codec_dbg(codec, "R3DI alt_init");
7695 ca0132_gpio_init(codec);
7696 ca0132_gpio_setup(codec);
7e6ed62e 7697 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
e93ac30a
CM		 7698 r3di_pre_dsp_setup(codec);
7699 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7700 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
7701 break;
e42c7c73
CM		 7702 case QUIRK_R3D:
7703 r3d_pre_dsp_setup(codec);
7704 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7705 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7706 break;
03c9b6b1
CM		 7707 case QUIRK_AE5:
7708 ca0132_gpio_init(codec);
7709 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7710 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
7711 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7712 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
7713 chipio_write(codec, 0x18b030, 0x00000020);
7714 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7715 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7716 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
7717 break;
e93ac30a
CM		 7718 }
7719}
7720
95c6e9cb
IM		 7721static int ca0132_init(struct hda_codec *codec)
7722{
7723 struct ca0132_spec *spec = codec->spec;
7724 struct auto_pin_cfg *cfg = &spec->autocfg;
7725 int i;
e93ac30a
CM		 7726 bool dsp_loaded;
7727
7728 /*
7729 * If the DSP is already downloaded, and init has been entered again,
7730 * there's only two reasons for it. One, the codec has awaken from a
7731 * suspended state, and in that case dspload_is_loaded will return
7732 * false, and the init will be ran again. The other reason it gets
7733 * re entered is on startup for some reason it triggers a suspend and
7734 * resume state. In this case, it will check if the DSP is downloaded,
7735 * and not run the init function again. For codecs using alt_functions,
7736 * it will check if the DSP is loaded properly.
7737 */
7738 if (spec->dsp_state == DSP_DOWNLOADED) {
7739 dsp_loaded = dspload_is_loaded(codec);
7740 if (!dsp_loaded) {
7741 spec->dsp_reload = true;
7742 spec->dsp_state = DSP_DOWNLOAD_INIT;
38ba69ff
CM		 7743 } else {
7744 if (spec->quirk == QUIRK_SBZ)
7745 sbz_dsp_startup_check(codec);
e93ac30a 7746 return 0;
38ba69ff 7747 }
e93ac30a 7748 }
95c6e9cb 7749
e24aa0a4
TI		 7750 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
7751 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 7752 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 7753
e42c7c73
CM		 7754 if (spec->use_pci_mmio)
7755 ca0132_mmio_init(codec);
e93ac30a 7756
664c7155 7757 snd_hda_power_up_pm(codec);
5aaca44d 7758
b9b41345
CM		 7759 if (spec->quirk == QUIRK_AE5)
7760 ae5_register_set(codec);
7761
f8fb1170 7762 ca0132_init_unsol(codec);
5aaca44d
IM		 7763 ca0132_init_params(codec);
7764 ca0132_init_flags(codec);
7e6ed62e 7765
5aaca44d 7766 snd_hda_sequence_write(codec, spec->base_init_verbs);
e93ac30a 7767
365c7f25 7768 if (spec->use_alt_functions)
e93ac30a
CM		 7769 ca0132_alt_init(codec);
7770
01ef7dbf 7771 ca0132_download_dsp(codec);
7e6ed62e 7772
5aaca44d 7773 ca0132_refresh_widget_caps(codec);
e93ac30a 7774
7e6ed62e
CM		 7775 switch (spec->quirk) {
7776 case QUIRK_R3DI:
c986f50c
CM		 7777 case QUIRK_R3D:
7778 r3d_setup_defaults(codec);
7e6ed62e 7779 break;
126b75e0 7780 case QUIRK_SBZ:
d97420d2 7781 sbz_setup_defaults(codec);
126b75e0 7782 break;
415cd844
CM		 7783 case QUIRK_AE5:
7784 ae5_setup_defaults(codec);
7785 break;
126b75e0 7786 default:
38ba69ff
CM		 7787 ca0132_setup_defaults(codec);
7788 ca0132_init_analog_mic2(codec);
7789 ca0132_init_dmic(codec);
7e6ed62e 7790 break;
38ba69ff 7791 }
5aaca44d
IM		 7792
7793 for (i = 0; i < spec->num_outputs; i++)
7794 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 7795
95c6e9cb
IM		 7796 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
7797
7798 for (i = 0; i < spec->num_inputs; i++)
7799 init_input(codec, spec->input_pins[i], spec->adcs[i]);
7800
7801 init_input(codec, cfg->dig_in_pin, spec->dig_in);
7802
009b8f97 7803 if (!spec->use_alt_functions) {
e93ac30a
CM		 7804 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7805 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7806 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
7807 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7808 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
7809 }
7810
7cb9d94c 7811 if (spec->quirk == QUIRK_SBZ)
e93ac30a
CM		 7812 ca0132_gpio_setup(codec);
7813
d5c016b5 7814 snd_hda_sequence_write(codec, spec->spec_init_verbs);
d97420d2 7815 if (spec->use_alt_functions) {
7cb9d94c
CM		 7816 ca0132_alt_select_out(codec);
7817 ca0132_alt_select_in(codec);
d97420d2 7818 } else {
7cb9d94c
CM		 7819 ca0132_select_out(codec);
7820 ca0132_select_mic(codec);
7cb9d94c 7821 }
5aaca44d 7822
a73d511c
IM		 7823 snd_hda_jack_report_sync(codec);
7824
e93ac30a
CM		 7825 /*
7826 * Re set the PlayEnhancement switch on a resume event, because the
7827 * controls will not be reloaded.
7828 */
7829 if (spec->dsp_reload) {
7830 spec->dsp_reload = false;
7831 ca0132_pe_switch_set(codec);
7832 }
7833
664c7155 7834 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 7835
7836 return 0;
7837}
7838
95c6e9cb
IM		 7839static void ca0132_free(struct hda_codec *codec)
7840{
5aaca44d
IM		 7841 struct ca0132_spec *spec = codec->spec;
7842
993884f6 7843 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d 7844 snd_hda_power_up(codec);
2e48b2b7
CM		 7845 switch (spec->quirk) {
7846 case QUIRK_SBZ:
7847 sbz_exit_chip(codec);
7848 break;
2f295f91
CM		 7849 case QUIRK_R3D:
7850 r3d_exit_chip(codec);
7851 break;
2e48b2b7
CM		 7852 case QUIRK_R3DI:
7853 r3di_gpio_shutdown(codec);
2e48b2b7
CM		 7854 break;
7855 }
2f295f91
CM		 7856
7857 snd_hda_sequence_write(codec, spec->base_exit_verbs);
7858 ca0132_exit_chip(codec);
7859
5aaca44d 7860 snd_hda_power_down(codec);
aa31704f
CM		 7861 if (spec->mem_base)
7862 iounmap(spec->mem_base);
d5c016b5 7863 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 7864 kfree(codec->spec);
7865}
7866
2e48b2b7
CM		 7867static void ca0132_reboot_notify(struct hda_codec *codec)
7868{
7869 codec->patch_ops.free(codec);
7870}
7871
071f1344 7872static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 7873 .build_controls = ca0132_build_controls,
7874 .build_pcms = ca0132_build_pcms,
7875 .init = ca0132_init,
7876 .free = ca0132_free,
f8fb1170 7877 .unsol_event = snd_hda_jack_unsol_event,
2e48b2b7 7878 .reboot_notify = ca0132_reboot_notify,
95c6e9cb
IM		 7879};
7880
441aa6a0
IM		 7881static void ca0132_config(struct hda_codec *codec)
7882{
7883 struct ca0132_spec *spec = codec->spec;
441aa6a0
IM		 7884
7885 spec->dacs[0] = 0x2;
7886 spec->dacs[1] = 0x3;
7887 spec->dacs[2] = 0x4;
7888
7889 spec->multiout.dac_nids = spec->dacs;
7890 spec->multiout.num_dacs = 3;
441aa6a0 7891
009b8f97 7892 if (!spec->use_alt_functions)
63177afc
CM		 7893 spec->multiout.max_channels = 2;
7894 else
7895 spec->multiout.max_channels = 6;
7896
7897 switch (spec->quirk) {
7898 case QUIRK_ALIENWARE:
d06feaf0 7899 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
fe14f39e 7900 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
d06feaf0
CM		 7901 break;
7902 case QUIRK_SBZ:
7903 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
7904 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
7905 break;
7906 case QUIRK_R3D:
7907 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
7908 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
7909 break;
7910 case QUIRK_R3DI:
7911 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
7912 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7913 break;
7914 case QUIRK_AE5:
7915 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
7916 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7917 break;
7918 }
fe14f39e 7919
d06feaf0
CM		 7920 switch (spec->quirk) {
7921 case QUIRK_ALIENWARE:
fe14f39e
TI		 7922 spec->num_outputs = 2;
7923 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 7924 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 7925 spec->shared_out_nid = 0x2;
7926 spec->unsol_tag_hp = 0x0f;
7927
7928 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7929 spec->adcs[1] = 0x8; /* analog mic2 */
7930 spec->adcs[2] = 0xa; /* what u hear */
7931
7932 spec->num_inputs = 3;
7933 spec->input_pins[0] = 0x12;
7934 spec->input_pins[1] = 0x11;
7935 spec->input_pins[2] = 0x13;
7936 spec->shared_mic_nid = 0x7;
7937 spec->unsol_tag_amic1 = 0x11;
63177afc
CM		 7938 break;
7939 case QUIRK_SBZ:
7f73df95 7940 case QUIRK_R3D:
63177afc
CM		 7941 spec->num_outputs = 2;
7942 spec->out_pins[0] = 0x0B; /* Line out */
7943 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7944 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7945 spec->out_pins[3] = 0x11; /* Rear surround */
7946 spec->shared_out_nid = 0x2;
7947 spec->unsol_tag_hp = spec->out_pins[1];
7948 spec->unsol_tag_front_hp = spec->out_pins[2];
7949
7950 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7951 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7952 spec->adcs[2] = 0xa; /* what u hear */
7953
7954 spec->num_inputs = 2;
7955 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7956 spec->input_pins[1] = 0x13; /* What U Hear */
7957 spec->shared_mic_nid = 0x7;
7958 spec->unsol_tag_amic1 = spec->input_pins[0];
7959
7960 /* SPDIF I/O */
7961 spec->dig_out = 0x05;
7962 spec->multiout.dig_out_nid = spec->dig_out;
63177afc 7963 spec->dig_in = 0x09;
63177afc 7964 break;
d06feaf0
CM		 7965 case QUIRK_AE5:
7966 spec->num_outputs = 2;
7967 spec->out_pins[0] = 0x0B; /* Line out */
7968 spec->out_pins[1] = 0x11; /* Rear headphone out */
7969 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7970 spec->out_pins[3] = 0x0F; /* Rear surround */
7971 spec->shared_out_nid = 0x2;
7972 spec->unsol_tag_hp = spec->out_pins[1];
7973 spec->unsol_tag_front_hp = spec->out_pins[2];
7974
7975 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7976 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7977 spec->adcs[2] = 0xa; /* what u hear */
63177afc 7978
d06feaf0
CM		 7979 spec->num_inputs = 2;
7980 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7981 spec->input_pins[1] = 0x13; /* What U Hear */
7982 spec->shared_mic_nid = 0x7;
7983 spec->unsol_tag_amic1 = spec->input_pins[0];
7984
7985 /* SPDIF I/O */
7986 spec->dig_out = 0x05;
7987 spec->multiout.dig_out_nid = spec->dig_out;
7988 break;
7989 case QUIRK_R3DI:
63177afc
CM		 7990 spec->num_outputs = 2;
7991 spec->out_pins[0] = 0x0B; /* Line out */
7992 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7993 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7994 spec->out_pins[3] = 0x11; /* Rear surround */
7995 spec->shared_out_nid = 0x2;
7996 spec->unsol_tag_hp = spec->out_pins[1];
7997 spec->unsol_tag_front_hp = spec->out_pins[2];
7998
7999 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
8000 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
8001 spec->adcs[2] = 0x0a; /* what u hear */
8002
8003 spec->num_inputs = 2;
8004 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
8005 spec->input_pins[1] = 0x13; /* What U Hear */
8006 spec->shared_mic_nid = 0x7;
8007 spec->unsol_tag_amic1 = spec->input_pins[0];
8008
8009 /* SPDIF I/O */
8010 spec->dig_out = 0x05;
8011 spec->multiout.dig_out_nid = spec->dig_out;
63177afc
CM		 8012 break;
8013 default:
fe14f39e
TI		 8014 spec->num_outputs = 2;
8015 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 8016 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 8017 spec->shared_out_nid = 0x2;
8018 spec->unsol_tag_hp = spec->out_pins[1];
8019
8020 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
8021 spec->adcs[1] = 0x8; /* analog mic2 */
8022 spec->adcs[2] = 0xa; /* what u hear */
8023
8024 spec->num_inputs = 3;
8025 spec->input_pins[0] = 0x12;
8026 spec->input_pins[1] = 0x11;
8027 spec->input_pins[2] = 0x13;
8028 spec->shared_mic_nid = 0x7;
8029 spec->unsol_tag_amic1 = spec->input_pins[0];
8030
8031 /* SPDIF I/O */
8032 spec->dig_out = 0x05;
8033 spec->multiout.dig_out_nid = spec->dig_out;
fe14f39e 8034 spec->dig_in = 0x09;
63177afc 8035 break;
d5c016b5 8036 }
441aa6a0
IM		 8037}
8038
d5c016b5
GM		 8039static int ca0132_prepare_verbs(struct hda_codec *codec)
8040{
8041/* Verbs + terminator (an empty element) */
a3d90d67 8042#define NUM_SPEC_VERBS 2
d5c016b5
GM		 8043 struct ca0132_spec *spec = codec->spec;
8044
8045 spec->chip_init_verbs = ca0132_init_verbs0;
88268ce8
CM		 8046 /*
8047 * Since desktop cards use pci_mmio, this can be used to determine
8048 * whether or not to use these verbs instead of a separate bool.
8049 */
8050 if (spec->use_pci_mmio)
e42c7c73 8051 spec->desktop_init_verbs = ca0132_init_verbs1;
6396bb22
KC		 8052 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
8053 sizeof(struct hda_verb),
8054 GFP_KERNEL);
d5c016b5
GM		 8055 if (!spec->spec_init_verbs)
8056 return -ENOMEM;
8057
d5c016b5 8058 /* config EAPD */
a3d90d67
AB		 8059 spec->spec_init_verbs[0].nid = 0x0b;
8060 spec->spec_init_verbs[0].param = 0x78D;
8061 spec->spec_init_verbs[0].verb = 0x00;
d5c016b5
GM		 8062
8063 /* Previously commented configuration */
8064 /*
a3d90d67
AB		 8065 spec->spec_init_verbs[2].nid = 0x0b;
8066 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
8067 spec->spec_init_verbs[2].verb = 0x02;
8068
8069 spec->spec_init_verbs[3].nid = 0x10;
8070 spec->spec_init_verbs[3].param = 0x78D;
d5c016b5
GM		 8071 spec->spec_init_verbs[3].verb = 0x02;
8072
8073 spec->spec_init_verbs[4].nid = 0x10;
a3d90d67 8074 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
d5c016b5 8075 spec->spec_init_verbs[4].verb = 0x02;
d5c016b5
GM		 8076 */
8077
8078 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
8079 return 0;
8080}
8081
95c6e9cb
IM		 8082static int patch_ca0132(struct hda_codec *codec)
8083{
8084 struct ca0132_spec *spec;
a73d511c 8085 int err;
d5c016b5 8086 const struct snd_pci_quirk *quirk;
95c6e9cb 8087
4e76a883 8088 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 8089
8090 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
8091 if (!spec)
8092 return -ENOMEM;
8093 codec->spec = spec;
993884f6 8094 spec->codec = codec;
95c6e9cb 8095
225068ab
TI		 8096 codec->patch_ops = ca0132_patch_ops;
8097 codec->pcm_format_first = 1;
8098 codec->no_sticky_stream = 1;
8099
d5c016b5
GM		 8100 /* Detect codec quirk */
8101 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
8102 if (quirk)
8103 spec->quirk = quirk->value;
8104 else
8105 spec->quirk = QUIRK_NONE;
8106
e24aa0a4 8107 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271 8108 spec->num_mixers = 1;
017310fb
CM		 8109
8110 /* Set which mixers each quirk uses. */
8111 switch (spec->quirk) {
8112 case QUIRK_SBZ:
e25e3445 8113 spec->mixers[0] = desktop_mixer;
017310fb
CM		 8114 snd_hda_codec_set_name(codec, "Sound Blaster Z");
8115 break;
e25e3445
CM		 8116 case QUIRK_R3D:
8117 spec->mixers[0] = desktop_mixer;
8118 snd_hda_codec_set_name(codec, "Recon3D");
8119 break;
017310fb
CM		 8120 case QUIRK_R3DI:
8121 spec->mixers[0] = r3di_mixer;
8122 snd_hda_codec_set_name(codec, "Recon3Di");
8123 break;
88268ce8
CM		 8124 case QUIRK_AE5:
8125 spec->mixers[0] = desktop_mixer;
8126 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
8127 break;
017310fb
CM		 8128 default:
8129 spec->mixers[0] = ca0132_mixer;
8130 break;
8131 }
a7e76271 8132
08eca6b1 8133 /* Setup whether or not to use alt functions/controls/pci_mmio */
009b8f97
CM		 8134 switch (spec->quirk) {
8135 case QUIRK_SBZ:
e42c7c73 8136 case QUIRK_R3D:
88268ce8 8137 case QUIRK_AE5:
08eca6b1
CM		 8138 spec->use_alt_controls = true;
8139 spec->use_alt_functions = true;
8140 spec->use_pci_mmio = true;
8141 break;
009b8f97 8142 case QUIRK_R3DI:
47cdf76e 8143 spec->use_alt_controls = true;
009b8f97 8144 spec->use_alt_functions = true;
08eca6b1 8145 spec->use_pci_mmio = false;
009b8f97
CM		 8146 break;
8147 default:
47cdf76e 8148 spec->use_alt_controls = false;
009b8f97 8149 spec->use_alt_functions = false;
08eca6b1 8150 spec->use_pci_mmio = false;
009b8f97
CM		 8151 break;
8152 }
8153
08eca6b1
CM		 8154 if (spec->use_pci_mmio) {
8155 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
8156 if (spec->mem_base == NULL) {
8157 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
8158 spec->quirk = QUIRK_NONE;
8159 }
8160 }
8161
5aaca44d
IM		 8162 spec->base_init_verbs = ca0132_base_init_verbs;
8163 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 8164
993884f6
CCC		 8165 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
8166
95c6e9cb
IM		 8167 ca0132_init_chip(codec);
8168
8169 ca0132_config(codec);
8170
d5c016b5
GM		 8171 err = ca0132_prepare_verbs(codec);
8172 if (err < 0)
cc91ceaf 8173 goto error;
d5c016b5 8174
a73d511c
IM		 8175 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
8176 if (err < 0)
cc91ceaf 8177 goto error;
a73d511c 8178
95c6e9cb 8179 return 0;
cc91ceaf
TI		 8180
8181 error:
8182 ca0132_free(codec);
8183 return err;
95c6e9cb
IM		 8184}
8185
8186/*
8187 * patch entries
8188 */
b9a94a9c
TI		 8189static struct hda_device_id snd_hda_id_ca0132[] = {
8190 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 8191 {} /* terminator */
8192};
b9a94a9c 8193MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 8194
8195MODULE_LICENSE("GPL");
406261ce 8196MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 8197
d8a766a1 8198static struct hda_codec_driver ca0132_driver = {
b9a94a9c 8199 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 8200};
8201
d8a766a1 8202module_hda_codec_driver(ca0132_driver);
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