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ALSA: hda/ca0132 - Keep power on during processing DSP response
[mirror_ubuntu-bionic-kernel.git] / sound / pci / hda / patch_ca0132.c
CommitLineData
95c6e9cb
IM		 1/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
95c6e9cb 27#include <linux/mutex.h>
da155d5b 28#include <linux/module.h>
4aa3bb0c 29#include <linux/firmware.h>
a9291f46 30#include <linux/kernel.h>
85affca4 31#include <asm/io.h>
95c6e9cb
IM		 32#include <sound/core.h>
33#include "hda_codec.h"
34#include "hda_local.h"
128bc4ba 35#include "hda_auto_parser.h"
5aaca44d 36#include "hda_jack.h"
95c6e9cb 37
bcd109c0
IM		 38#include "ca0132_regs.h"
39
ef6b2ead
IM		 40/* Enable this to see controls for tuning purpose. */
41/*#define ENABLE_TUNING_CONTROLS*/
42
4a404cbb
TS		 43#ifdef ENABLE_TUNING_CONTROLS
44#include <sound/tlv.h>
45#endif
46
ef6b2ead
IM		 47#define FLOAT_ZERO 0x00000000
48#define FLOAT_ONE 0x3f800000
49#define FLOAT_TWO 0x40000000
50#define FLOAT_MINUS_5 0xc0a00000
51
ef6b2ead
IM		 52#define UNSOL_TAG_DSP 0x16
53
4aa3bb0c
IM		 54#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
55#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
56
57#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
58#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
59#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
60
61#define MASTERCONTROL 0x80
ef6b2ead
IM		 62#define MASTERCONTROL_ALLOC_DMA_CHAN 10
63#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
4aa3bb0c 64
95c6e9cb
IM		 65#define WIDGET_CHIP_CTRL 0x15
66#define WIDGET_DSP_CTRL 0x16
67
4aa3bb0c
IM		 68#define MEM_CONNID_MICIN1 3
69#define MEM_CONNID_MICIN2 5
70#define MEM_CONNID_MICOUT1 12
71#define MEM_CONNID_MICOUT2 14
72#define MEM_CONNID_WUH 10
73#define MEM_CONNID_DSP 16
74#define MEM_CONNID_DMIC 100
75
76#define SCP_SET 0
77#define SCP_GET 1
78
01ef7dbf
IM		 79#define EFX_FILE "ctefx.bin"
80
24f3cede 81#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf 82MODULE_FIRMWARE(EFX_FILE);
7a527ede 83#endif
01ef7dbf 84
ef6b2ead
IM		 85static char *dirstr[2] = { "Playback", "Capture" };
86
87enum {
88 SPEAKER_OUT,
89 HEADPHONE_OUT
90};
91
92enum {
93 DIGITAL_MIC,
94 LINE_MIC_IN
95};
96
97enum {
98#define VNODE_START_NID 0x80
99 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
100 VNID_MIC,
101 VNID_HP_SEL,
102 VNID_AMIC1_SEL,
103 VNID_HP_ASEL,
104 VNID_AMIC1_ASEL,
105 VNODE_END_NID,
106#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
107
108#define EFFECT_START_NID 0x90
109#define OUT_EFFECT_START_NID EFFECT_START_NID
110 SURROUND = OUT_EFFECT_START_NID,
111 CRYSTALIZER,
112 DIALOG_PLUS,
113 SMART_VOLUME,
114 X_BASS,
115 EQUALIZER,
116 OUT_EFFECT_END_NID,
117#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
118
119#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
120 ECHO_CANCELLATION = IN_EFFECT_START_NID,
121 VOICE_FOCUS,
122 MIC_SVM,
123 NOISE_REDUCTION,
124 IN_EFFECT_END_NID,
125#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
126
127 VOICEFX = IN_EFFECT_END_NID,
128 PLAY_ENHANCEMENT,
129 CRYSTAL_VOICE,
130 EFFECT_END_NID
131#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
132};
133
134/* Effects values size*/
135#define EFFECT_VALS_MAX_COUNT 12
136
e8412ca4
DR		 137/* Latency introduced by DSP blocks in milliseconds. */
138#define DSP_CAPTURE_INIT_LATENCY 0
139#define DSP_CRYSTAL_VOICE_LATENCY 124
140#define DSP_PLAYBACK_INIT_LATENCY 13
141#define DSP_PLAY_ENHANCEMENT_LATENCY 30
142#define DSP_SPEAKER_OUT_LATENCY 7
143
ef6b2ead 144struct ct_effect {
975cc02a 145 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 146 hda_nid_t nid;
147 int mid; /*effect module ID*/
148 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
149 int direct; /* 0:output; 1:input*/
150 int params; /* number of default non-on/off params */
151 /*effect default values, 1st is on/off. */
152 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
153};
154
155#define EFX_DIR_OUT 0
156#define EFX_DIR_IN 1
157
158static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
159 { .name = "Surround",
160 .nid = SURROUND,
161 .mid = 0x96,
162 .reqs = {0, 1},
163 .direct = EFX_DIR_OUT,
164 .params = 1,
165 .def_vals = {0x3F800000, 0x3F2B851F}
166 },
167 { .name = "Crystalizer",
168 .nid = CRYSTALIZER,
169 .mid = 0x96,
170 .reqs = {7, 8},
171 .direct = EFX_DIR_OUT,
172 .params = 1,
173 .def_vals = {0x3F800000, 0x3F266666}
174 },
175 { .name = "Dialog Plus",
176 .nid = DIALOG_PLUS,
177 .mid = 0x96,
178 .reqs = {2, 3},
179 .direct = EFX_DIR_OUT,
180 .params = 1,
181 .def_vals = {0x00000000, 0x3F000000}
182 },
183 { .name = "Smart Volume",
184 .nid = SMART_VOLUME,
185 .mid = 0x96,
186 .reqs = {4, 5, 6},
187 .direct = EFX_DIR_OUT,
188 .params = 2,
189 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
190 },
191 { .name = "X-Bass",
192 .nid = X_BASS,
193 .mid = 0x96,
194 .reqs = {24, 23, 25},
195 .direct = EFX_DIR_OUT,
196 .params = 2,
197 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
198 },
199 { .name = "Equalizer",
200 .nid = EQUALIZER,
201 .mid = 0x96,
202 .reqs = {9, 10, 11, 12, 13, 14,
203 15, 16, 17, 18, 19, 20},
204 .direct = EFX_DIR_OUT,
205 .params = 11,
206 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
207 0x00000000, 0x00000000, 0x00000000, 0x00000000,
208 0x00000000, 0x00000000, 0x00000000, 0x00000000}
209 },
210 { .name = "Echo Cancellation",
211 .nid = ECHO_CANCELLATION,
212 .mid = 0x95,
213 .reqs = {0, 1, 2, 3},
214 .direct = EFX_DIR_IN,
215 .params = 3,
216 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
217 },
218 { .name = "Voice Focus",
219 .nid = VOICE_FOCUS,
220 .mid = 0x95,
221 .reqs = {6, 7, 8, 9},
222 .direct = EFX_DIR_IN,
223 .params = 3,
224 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
225 },
226 { .name = "Mic SVM",
227 .nid = MIC_SVM,
228 .mid = 0x95,
229 .reqs = {44, 45},
230 .direct = EFX_DIR_IN,
231 .params = 1,
232 .def_vals = {0x00000000, 0x3F3D70A4}
233 },
234 { .name = "Noise Reduction",
235 .nid = NOISE_REDUCTION,
236 .mid = 0x95,
237 .reqs = {4, 5},
238 .direct = EFX_DIR_IN,
239 .params = 1,
240 .def_vals = {0x3F800000, 0x3F000000}
241 },
242 { .name = "VoiceFX",
243 .nid = VOICEFX,
244 .mid = 0x95,
245 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
246 .direct = EFX_DIR_IN,
247 .params = 8,
248 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
249 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
250 0x00000000}
251 }
252};
253
254/* Tuning controls */
255#ifdef ENABLE_TUNING_CONTROLS
256
257enum {
258#define TUNING_CTL_START_NID 0xC0
259 WEDGE_ANGLE = TUNING_CTL_START_NID,
260 SVM_LEVEL,
261 EQUALIZER_BAND_0,
262 EQUALIZER_BAND_1,
263 EQUALIZER_BAND_2,
264 EQUALIZER_BAND_3,
265 EQUALIZER_BAND_4,
266 EQUALIZER_BAND_5,
267 EQUALIZER_BAND_6,
268 EQUALIZER_BAND_7,
269 EQUALIZER_BAND_8,
270 EQUALIZER_BAND_9,
271 TUNING_CTL_END_NID
272#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
273};
274
275struct ct_tuning_ctl {
975cc02a 276 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
ef6b2ead
IM		 277 hda_nid_t parent_nid;
278 hda_nid_t nid;
279 int mid; /*effect module ID*/
280 int req; /*effect module request*/
281 int direct; /* 0:output; 1:input*/
282 unsigned int def_val;/*effect default values*/
283};
284
285static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
286 { .name = "Wedge Angle",
287 .parent_nid = VOICE_FOCUS,
288 .nid = WEDGE_ANGLE,
289 .mid = 0x95,
290 .req = 8,
291 .direct = EFX_DIR_IN,
292 .def_val = 0x41F00000
293 },
294 { .name = "SVM Level",
295 .parent_nid = MIC_SVM,
296 .nid = SVM_LEVEL,
297 .mid = 0x95,
298 .req = 45,
299 .direct = EFX_DIR_IN,
300 .def_val = 0x3F3D70A4
301 },
302 { .name = "EQ Band0",
303 .parent_nid = EQUALIZER,
304 .nid = EQUALIZER_BAND_0,
305 .mid = 0x96,
306 .req = 11,
307 .direct = EFX_DIR_OUT,
308 .def_val = 0x00000000
309 },
310 { .name = "EQ Band1",
311 .parent_nid = EQUALIZER,
312 .nid = EQUALIZER_BAND_1,
313 .mid = 0x96,
314 .req = 12,
315 .direct = EFX_DIR_OUT,
316 .def_val = 0x00000000
317 },
318 { .name = "EQ Band2",
319 .parent_nid = EQUALIZER,
320 .nid = EQUALIZER_BAND_2,
321 .mid = 0x96,
322 .req = 13,
323 .direct = EFX_DIR_OUT,
324 .def_val = 0x00000000
325 },
326 { .name = "EQ Band3",
327 .parent_nid = EQUALIZER,
328 .nid = EQUALIZER_BAND_3,
329 .mid = 0x96,
330 .req = 14,
331 .direct = EFX_DIR_OUT,
332 .def_val = 0x00000000
333 },
334 { .name = "EQ Band4",
335 .parent_nid = EQUALIZER,
336 .nid = EQUALIZER_BAND_4,
337 .mid = 0x96,
338 .req = 15,
339 .direct = EFX_DIR_OUT,
340 .def_val = 0x00000000
341 },
342 { .name = "EQ Band5",
343 .parent_nid = EQUALIZER,
344 .nid = EQUALIZER_BAND_5,
345 .mid = 0x96,
346 .req = 16,
347 .direct = EFX_DIR_OUT,
348 .def_val = 0x00000000
349 },
350 { .name = "EQ Band6",
351 .parent_nid = EQUALIZER,
352 .nid = EQUALIZER_BAND_6,
353 .mid = 0x96,
354 .req = 17,
355 .direct = EFX_DIR_OUT,
356 .def_val = 0x00000000
357 },
358 { .name = "EQ Band7",
359 .parent_nid = EQUALIZER,
360 .nid = EQUALIZER_BAND_7,
361 .mid = 0x96,
362 .req = 18,
363 .direct = EFX_DIR_OUT,
364 .def_val = 0x00000000
365 },
366 { .name = "EQ Band8",
367 .parent_nid = EQUALIZER,
368 .nid = EQUALIZER_BAND_8,
369 .mid = 0x96,
370 .req = 19,
371 .direct = EFX_DIR_OUT,
372 .def_val = 0x00000000
373 },
374 { .name = "EQ Band9",
375 .parent_nid = EQUALIZER,
376 .nid = EQUALIZER_BAND_9,
377 .mid = 0x96,
378 .req = 20,
379 .direct = EFX_DIR_OUT,
380 .def_val = 0x00000000
381 }
382};
383#endif
384
385/* Voice FX Presets */
386#define VOICEFX_MAX_PARAM_COUNT 9
387
388struct ct_voicefx {
389 char *name;
390 hda_nid_t nid;
391 int mid;
392 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
393};
394
395struct ct_voicefx_preset {
396 char *name; /*preset name*/
397 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
398};
399
ccd7bd3d 400static struct ct_voicefx ca0132_voicefx = {
ef6b2ead
IM		 401 .name = "VoiceFX Capture Switch",
402 .nid = VOICEFX,
403 .mid = 0x95,
404 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
405};
406
ccd7bd3d 407static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
ef6b2ead
IM		 408 { .name = "Neutral",
409 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
410 0x44FA0000, 0x3F800000, 0x3F800000,
411 0x3F800000, 0x00000000, 0x00000000 }
412 },
413 { .name = "Female2Male",
414 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
415 0x44FA0000, 0x3F19999A, 0x3F866666,
416 0x3F800000, 0x00000000, 0x00000000 }
417 },
418 { .name = "Male2Female",
419 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
420 0x450AC000, 0x4017AE14, 0x3F6B851F,
421 0x3F800000, 0x00000000, 0x00000000 }
422 },
423 { .name = "ScrappyKid",
424 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
425 0x44FA0000, 0x40400000, 0x3F28F5C3,
426 0x3F800000, 0x00000000, 0x00000000 }
427 },
428 { .name = "Elderly",
429 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
430 0x44E10000, 0x3FB33333, 0x3FB9999A,
431 0x3F800000, 0x3E3A2E43, 0x00000000 }
432 },
433 { .name = "Orc",
434 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
435 0x45098000, 0x3F266666, 0x3FC00000,
436 0x3F800000, 0x00000000, 0x00000000 }
437 },
438 { .name = "Elf",
439 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
440 0x45193000, 0x3F8E147B, 0x3F75C28F,
441 0x3F800000, 0x00000000, 0x00000000 }
442 },
443 { .name = "Dwarf",
444 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
445 0x45007000, 0x3F451EB8, 0x3F7851EC,
446 0x3F800000, 0x00000000, 0x00000000 }
447 },
448 { .name = "AlienBrute",
449 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
450 0x451F6000, 0x3F266666, 0x3FA7D945,
451 0x3F800000, 0x3CF5C28F, 0x00000000 }
452 },
453 { .name = "Robot",
454 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
455 0x44FA0000, 0x3FB2718B, 0x3F800000,
456 0xBC07010E, 0x00000000, 0x00000000 }
457 },
458 { .name = "Marine",
459 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
460 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
461 0x3F0A3D71, 0x00000000, 0x00000000 }
462 },
463 { .name = "Emo",
464 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
465 0x44FA0000, 0x3F800000, 0x3F800000,
466 0x3E4CCCCD, 0x00000000, 0x00000000 }
467 },
468 { .name = "DeepVoice",
469 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
470 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
471 0x3F800000, 0x00000000, 0x00000000 }
472 },
473 { .name = "Munchkin",
474 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
475 0x44FA0000, 0x3F800000, 0x3F1A043C,
476 0x3F800000, 0x00000000, 0x00000000 }
477 }
478};
479
95c6e9cb
IM		 480enum hda_cmd_vendor_io {
481 /* for DspIO node */
482 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
483 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
484
485 VENDOR_DSPIO_STATUS = 0xF01,
486 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
487 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
488 VENDOR_DSPIO_DSP_INIT = 0x703,
489 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
490 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
491
492 /* for ChipIO node */
493 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
494 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
495 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
496 VENDOR_CHIPIO_DATA_LOW = 0x300,
497 VENDOR_CHIPIO_DATA_HIGH = 0x400,
498
499 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
500 VENDOR_CHIPIO_STATUS = 0xF01,
501 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
502 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
503
4aa3bb0c
IM		 504 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
505 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
506
95c6e9cb 507 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
4aa3bb0c 508 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
95c6e9cb
IM		 509
510 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
511 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
512 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
513 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
514 VENDOR_CHIPIO_FLAG_SET = 0x70F,
515 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
4aa3bb0c
IM		 516 VENDOR_CHIPIO_PARAM_SET = 0x710,
517 VENDOR_CHIPIO_PARAM_GET = 0xF10,
95c6e9cb
IM		 518
519 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
520 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
521 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
522 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
523
4aa3bb0c
IM		 524 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
525 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
526 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
527 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
528
529 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
530 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
531 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
532 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
533 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
534 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
535
536 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
95c6e9cb
IM		 537};
538
539/*
540 * Control flag IDs
541 */
542enum control_flag_id {
543 /* Connection manager stream setup is bypassed/enabled */
544 CONTROL_FLAG_C_MGR = 0,
545 /* DSP DMA is bypassed/enabled */
546 CONTROL_FLAG_DMA = 1,
547 /* 8051 'idle' mode is disabled/enabled */
548 CONTROL_FLAG_IDLE_ENABLE = 2,
549 /* Tracker for the SPDIF-in path is bypassed/enabled */
550 CONTROL_FLAG_TRACKER = 3,
551 /* DigitalOut to Spdif2Out connection is disabled/enabled */
552 CONTROL_FLAG_SPDIF2OUT = 4,
553 /* Digital Microphone is disabled/enabled */
554 CONTROL_FLAG_DMIC = 5,
555 /* ADC_B rate is 48 kHz/96 kHz */
556 CONTROL_FLAG_ADC_B_96KHZ = 6,
557 /* ADC_C rate is 48 kHz/96 kHz */
558 CONTROL_FLAG_ADC_C_96KHZ = 7,
559 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
560 CONTROL_FLAG_DAC_96KHZ = 8,
561 /* DSP rate is 48 kHz/96 kHz */
562 CONTROL_FLAG_DSP_96KHZ = 9,
563 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
564 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
565 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
566 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
567 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
568 CONTROL_FLAG_DECODE_LOOP = 12,
569 /* De-emphasis filter on DAC-1 disabled/enabled */
570 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
571 /* De-emphasis filter on DAC-2 disabled/enabled */
572 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
573 /* De-emphasis filter on DAC-3 disabled/enabled */
574 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
575 /* High-pass filter on ADC_B disabled/enabled */
576 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
577 /* High-pass filter on ADC_C disabled/enabled */
578 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
579 /* Common mode on Port_A disabled/enabled */
580 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
581 /* Common mode on Port_D disabled/enabled */
582 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
583 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
584 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
585 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
4aa3bb0c 586 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
95c6e9cb
IM		 587 /* ASI rate is 48kHz/96kHz */
588 CONTROL_FLAG_ASI_96KHZ = 22,
589 /* DAC power settings able to control attached ports no/yes */
590 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
591 /* Clock Stop OK reporting is disabled/enabled */
592 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
593 /* Number of control flags */
594 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
595};
596
597/*
598 * Control parameter IDs
599 */
4aa3bb0c 600enum control_param_id {
ef6b2ead
IM		 601 /* 0: None, 1: Mic1In*/
602 CONTROL_PARAM_VIP_SOURCE = 1,
95c6e9cb
IM		 603 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
604 CONTROL_PARAM_SPDIF1_SOURCE = 2,
ef6b2ead
IM		 605 /* Port A output stage gain setting to use when 16 Ohm output
606 * impedance is selected*/
607 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
608 /* Port D output stage gain setting to use when 16 Ohm output
609 * impedance is selected*/
610 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
95c6e9cb
IM		 611
612 /* Stream Control */
613
614 /* Select stream with the given ID */
615 CONTROL_PARAM_STREAM_ID = 24,
616 /* Source connection point for the selected stream */
617 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
618 /* Destination connection point for the selected stream */
619 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
620 /* Number of audio channels in the selected stream */
621 CONTROL_PARAM_STREAMS_CHANNELS = 27,
622 /*Enable control for the selected stream */
623 CONTROL_PARAM_STREAM_CONTROL = 28,
624
625 /* Connection Point Control */
626
627 /* Select connection point with the given ID */
628 CONTROL_PARAM_CONN_POINT_ID = 29,
629 /* Connection point sample rate */
630 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
631
632 /* Node Control */
633
634 /* Select HDA node with the given ID */
635 CONTROL_PARAM_NODE_ID = 31
636};
637
638/*
639 * Dsp Io Status codes
640 */
641enum hda_vendor_status_dspio {
642 /* Success */
643 VENDOR_STATUS_DSPIO_OK = 0x00,
644 /* Busy, unable to accept new command, the host must retry */
645 VENDOR_STATUS_DSPIO_BUSY = 0x01,
646 /* SCP command queue is full */
647 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
648 /* SCP response queue is empty */
649 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
650};
651
652/*
653 * Chip Io Status codes
654 */
655enum hda_vendor_status_chipio {
656 /* Success */
657 VENDOR_STATUS_CHIPIO_OK = 0x00,
658 /* Busy, unable to accept new command, the host must retry */
659 VENDOR_STATUS_CHIPIO_BUSY = 0x01
660};
661
662/*
663 * CA0132 sample rate
664 */
665enum ca0132_sample_rate {
666 SR_6_000 = 0x00,
667 SR_8_000 = 0x01,
668 SR_9_600 = 0x02,
669 SR_11_025 = 0x03,
670 SR_16_000 = 0x04,
671 SR_22_050 = 0x05,
672 SR_24_000 = 0x06,
673 SR_32_000 = 0x07,
674 SR_44_100 = 0x08,
675 SR_48_000 = 0x09,
676 SR_88_200 = 0x0A,
677 SR_96_000 = 0x0B,
678 SR_144_000 = 0x0C,
679 SR_176_400 = 0x0D,
680 SR_192_000 = 0x0E,
681 SR_384_000 = 0x0F,
682
683 SR_COUNT = 0x10,
684
685 SR_RATE_UNKNOWN = 0x1F
686};
687
01ef7dbf
IM		 688enum dsp_download_state {
689 DSP_DOWNLOAD_FAILED = -1,
690 DSP_DOWNLOAD_INIT = 0,
691 DSP_DOWNLOADING = 1,
692 DSP_DOWNLOADED = 2
693};
694
01ef7dbf
IM		 695/* retrieve parameters from hda format */
696#define get_hdafmt_chs(fmt) (fmt & 0xf)
697#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
698#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
699#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
700
701/*
702 * CA0132 specific
703 */
704
705struct ca0132_spec {
a7e76271
IM		 706 struct snd_kcontrol_new *mixers[5];
707 unsigned int num_mixers;
5aaca44d
IM		 708 const struct hda_verb *base_init_verbs;
709 const struct hda_verb *base_exit_verbs;
d5c016b5
GM		 710 const struct hda_verb *chip_init_verbs;
711 struct hda_verb *spec_init_verbs;
01ef7dbf 712 struct auto_pin_cfg autocfg;
5aaca44d
IM		 713
714 /* Nodes configurations */
01ef7dbf
IM		 715 struct hda_multi_out multiout;
716 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
717 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
5aaca44d 718 unsigned int num_outputs;
01ef7dbf
IM		 719 hda_nid_t input_pins[AUTO_PIN_LAST];
720 hda_nid_t adcs[AUTO_PIN_LAST];
721 hda_nid_t dig_out;
722 hda_nid_t dig_in;
723 unsigned int num_inputs;
a7e76271
IM		 724 hda_nid_t shared_mic_nid;
725 hda_nid_t shared_out_nid;
d5c016b5
GM		 726 hda_nid_t unsol_tag_hp;
727 hda_nid_t unsol_tag_amic1;
01ef7dbf
IM		 728
729 /* chip access */
730 struct mutex chipio_mutex; /* chip access mutex */
731 u32 curr_chip_addx;
732
733 /* DSP download related */
734 enum dsp_download_state dsp_state;
735 unsigned int dsp_stream_id;
736 unsigned int wait_scp;
737 unsigned int wait_scp_header;
738 unsigned int wait_num_data;
739 unsigned int scp_resp_header;
740 unsigned int scp_resp_data[4];
741 unsigned int scp_resp_count;
5aaca44d
IM		 742
743 /* mixer and effects related */
744 unsigned char dmic_ctl;
745 int cur_out_type;
746 int cur_mic_type;
747 long vnode_lvol[VNODES_COUNT];
748 long vnode_rvol[VNODES_COUNT];
749 long vnode_lswitch[VNODES_COUNT];
750 long vnode_rswitch[VNODES_COUNT];
751 long effects_switch[EFFECTS_COUNT];
752 long voicefx_val;
753 long cur_mic_boost;
44f0c978 754
993884f6
CCC		 755 struct hda_codec *codec;
756 struct delayed_work unsol_hp_work;
d5c016b5 757 int quirk;
993884f6 758
44f0c978
IM		 759#ifdef ENABLE_TUNING_CONTROLS
760 long cur_ctl_vals[TUNING_CTLS_COUNT];
761#endif
01ef7dbf
IM		 762};
763
d5c016b5
GM		 764/*
765 * CA0132 quirks table
766 */
767enum {
768 QUIRK_NONE,
769 QUIRK_ALIENWARE,
770};
771
fe14f39e
TI		 772static const struct hda_pintbl alienware_pincfgs[] = {
773 { 0x0b, 0x90170110 }, /* Builtin Speaker */
774 { 0x0c, 0x411111f0 }, /* N/A */
775 { 0x0d, 0x411111f0 }, /* N/A */
776 { 0x0e, 0x411111f0 }, /* N/A */
777 { 0x0f, 0x0321101f }, /* HP */
778 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
779 { 0x11, 0x03a11021 }, /* Mic */
780 { 0x12, 0xd5a30140 }, /* Builtin Mic */
781 { 0x13, 0x411111f0 }, /* N/A */
782 { 0x18, 0x411111f0 }, /* N/A */
783 {}
784};
785
d5c016b5 786static const struct snd_pci_quirk ca0132_quirks[] = {
5328e1ea
GM		 787 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
788 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
b5337cfe 789 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
d5c016b5
GM		 790 {}
791};
792
01ef7dbf
IM		 793/*
794 * CA0132 codec access
795 */
399ae725 796static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
01ef7dbf
IM		 797 unsigned int verb, unsigned int parm, unsigned int *res)
798{
799 unsigned int response;
800 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
801 *res = response;
802
803 return ((response == -1) ? -1 : 0);
804}
805
806static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
807 unsigned short converter_format, unsigned int *res)
808{
809 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
810 converter_format & 0xffff, res);
811}
812
813static int codec_set_converter_stream_channel(struct hda_codec *codec,
814 hda_nid_t nid, unsigned char stream,
815 unsigned char channel, unsigned int *res)
816{
817 unsigned char converter_stream_channel = 0;
818
819 converter_stream_channel = (stream << 4) | (channel & 0x0f);
820 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
821 converter_stream_channel, res);
822}
823
824/* Chip access helper function */
825static int chipio_send(struct hda_codec *codec,
826 unsigned int reg,
827 unsigned int data)
828{
829 unsigned int res;
6d67530e 830 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 831
832 /* send bits of data specified by reg */
833 do {
834 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
835 reg, data);
836 if (res == VENDOR_STATUS_CHIPIO_OK)
837 return 0;
6d67530e
IM		 838 msleep(20);
839 } while (time_before(jiffies, timeout));
840
01ef7dbf
IM		 841 return -EIO;
842}
843
844/*
845 * Write chip address through the vendor widget -- NOT protected by the Mutex!
846 */
847static int chipio_write_address(struct hda_codec *codec,
848 unsigned int chip_addx)
849{
4861af80 850 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 851 int res;
852
4861af80
IM		 853 if (spec->curr_chip_addx == chip_addx)
854 return 0;
855
01ef7dbf
IM		 856 /* send low 16 bits of the address */
857 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
858 chip_addx & 0xffff);
859
860 if (res != -EIO) {
861 /* send high 16 bits of the address */
862 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
863 chip_addx >> 16);
864 }
865
d1600401 866 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
01ef7dbf 867
4861af80 868 return res;
01ef7dbf
IM		 869}
870
871/*
872 * Write data through the vendor widget -- NOT protected by the Mutex!
873 */
01ef7dbf
IM		 874static int chipio_write_data(struct hda_codec *codec, unsigned int data)
875{
5aaca44d 876 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 877 int res;
878
879 /* send low 16 bits of the data */
880 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
881
882 if (res != -EIO) {
883 /* send high 16 bits of the data */
884 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
885 data >> 16);
886 }
887
5aaca44d
IM		 888 /*If no error encountered, automatically increment the address
889 as per chip behaviour*/
890 spec->curr_chip_addx = (res != -EIO) ?
d1600401 891 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 892 return res;
893}
894
d5c21b88
IM		 895/*
896 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
897 */
01ef7dbf
IM		 898static int chipio_write_data_multiple(struct hda_codec *codec,
899 const u32 *data,
900 unsigned int count)
901{
902 int status = 0;
903
904 if (data == NULL) {
4e76a883 905 codec_dbg(codec, "chipio_write_data null ptr\n");
01ef7dbf
IM		 906 return -EINVAL;
907 }
908
909 while ((count-- != 0) && (status == 0))
910 status = chipio_write_data(codec, *data++);
911
912 return status;
913}
914
915
916/*
917 * Read data through the vendor widget -- NOT protected by the Mutex!
918 */
919static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
920{
5aaca44d 921 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 922 int res;
923
924 /* post read */
925 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
926
927 if (res != -EIO) {
928 /* read status */
929 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
930 }
931
932 if (res != -EIO) {
933 /* read data */
934 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
935 VENDOR_CHIPIO_HIC_READ_DATA,
936 0);
937 }
938
5aaca44d
IM		 939 /*If no error encountered, automatically increment the address
940 as per chip behaviour*/
941 spec->curr_chip_addx = (res != -EIO) ?
d1600401 942 (spec->curr_chip_addx + 4) : ~0U;
01ef7dbf
IM		 943 return res;
944}
945
946/*
947 * Write given value to the given address through the chip I/O widget.
948 * protected by the Mutex
949 */
950static int chipio_write(struct hda_codec *codec,
951 unsigned int chip_addx, const unsigned int data)
952{
953 struct ca0132_spec *spec = codec->spec;
954 int err;
955
956 mutex_lock(&spec->chipio_mutex);
957
958 /* write the address, and if successful proceed to write data */
959 err = chipio_write_address(codec, chip_addx);
960 if (err < 0)
961 goto exit;
962
963 err = chipio_write_data(codec, data);
964 if (err < 0)
965 goto exit;
966
967exit:
968 mutex_unlock(&spec->chipio_mutex);
969 return err;
970}
971
d5c21b88
IM		 972/*
973 * Write multiple values to the given address through the chip I/O widget.
974 * protected by the Mutex
975 */
01ef7dbf
IM		 976static int chipio_write_multiple(struct hda_codec *codec,
977 u32 chip_addx,
978 const u32 *data,
979 unsigned int count)
980{
981 struct ca0132_spec *spec = codec->spec;
982 int status;
983
984 mutex_lock(&spec->chipio_mutex);
4861af80 985 status = chipio_write_address(codec, chip_addx);
01ef7dbf
IM		 986 if (status < 0)
987 goto error;
988
989 status = chipio_write_data_multiple(codec, data, count);
990error:
991 mutex_unlock(&spec->chipio_mutex);
992
993 return status;
994}
995
996/*
997 * Read the given address through the chip I/O widget
998 * protected by the Mutex
999 */
1000static int chipio_read(struct hda_codec *codec,
1001 unsigned int chip_addx, unsigned int *data)
1002{
1003 struct ca0132_spec *spec = codec->spec;
1004 int err;
1005
1006 mutex_lock(&spec->chipio_mutex);
1007
1008 /* write the address, and if successful proceed to write data */
1009 err = chipio_write_address(codec, chip_addx);
1010 if (err < 0)
1011 goto exit;
1012
1013 err = chipio_read_data(codec, data);
1014 if (err < 0)
1015 goto exit;
1016
1017exit:
1018 mutex_unlock(&spec->chipio_mutex);
1019 return err;
1020}
1021
d5c21b88
IM		 1022/*
1023 * Set chip control flags through the chip I/O widget.
1024 */
01ef7dbf
IM		 1025static void chipio_set_control_flag(struct hda_codec *codec,
1026 enum control_flag_id flag_id,
1027 bool flag_state)
1028{
1029 unsigned int val;
1030 unsigned int flag_bit;
1031
1032 flag_bit = (flag_state ? 1 : 0);
1033 val = (flag_bit << 7) | (flag_id);
1034 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1035 VENDOR_CHIPIO_FLAG_SET, val);
1036}
1037
d5c21b88
IM		 1038/*
1039 * Set chip parameters through the chip I/O widget.
1040 */
01ef7dbf
IM		 1041static void chipio_set_control_param(struct hda_codec *codec,
1042 enum control_param_id param_id, int param_val)
1043{
1044 struct ca0132_spec *spec = codec->spec;
1045 int val;
1046
1047 if ((param_id < 32) && (param_val < 8)) {
1048 val = (param_val << 5) | (param_id);
1049 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1050 VENDOR_CHIPIO_PARAM_SET, val);
1051 } else {
1052 mutex_lock(&spec->chipio_mutex);
1053 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1054 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1055 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1056 param_id);
1057 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1058 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1059 param_val);
1060 }
1061 mutex_unlock(&spec->chipio_mutex);
1062 }
1063}
1064
d5c21b88
IM		 1065/*
1066 * Set sampling rate of the connection point.
1067 */
01ef7dbf
IM		 1068static void chipio_set_conn_rate(struct hda_codec *codec,
1069 int connid, enum ca0132_sample_rate rate)
1070{
1071 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1072 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1073 rate);
1074}
1075
d5c21b88
IM		 1076/*
1077 * Enable clocks.
1078 */
01ef7dbf
IM		 1079static void chipio_enable_clocks(struct hda_codec *codec)
1080{
1081 struct ca0132_spec *spec = codec->spec;
1082
1083 mutex_lock(&spec->chipio_mutex);
1084 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1085 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1086 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1087 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1088 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1089 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1090 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1091 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1092 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1093 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1094 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1095 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1096 mutex_unlock(&spec->chipio_mutex);
1097}
1098
1099/*
1100 * CA0132 DSP IO stuffs
1101 */
1102static int dspio_send(struct hda_codec *codec, unsigned int reg,
1103 unsigned int data)
1104{
b645d796 1105 int res;
6d67530e 1106 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf
IM		 1107
1108 /* send bits of data specified by reg to dsp */
1109 do {
1110 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1111 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1112 return res;
6d67530e
IM		 1113 msleep(20);
1114 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1115
1116 return -EIO;
1117}
1118
d5c21b88
IM		 1119/*
1120 * Wait for DSP to be ready for commands
1121 */
01ef7dbf
IM		 1122static void dspio_write_wait(struct hda_codec *codec)
1123{
4861af80
IM		 1124 int status;
1125 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1126
01ef7dbf 1127 do {
4861af80
IM		 1128 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1129 VENDOR_DSPIO_STATUS, 0);
1130 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1131 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1132 break;
1133 msleep(1);
1134 } while (time_before(jiffies, timeout));
01ef7dbf
IM		 1135}
1136
d5c21b88
IM		 1137/*
1138 * Write SCP data to DSP
1139 */
01ef7dbf
IM		 1140static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1141{
1142 struct ca0132_spec *spec = codec->spec;
1143 int status;
1144
1145 dspio_write_wait(codec);
1146
1147 mutex_lock(&spec->chipio_mutex);
1148 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1149 scp_data & 0xffff);
1150 if (status < 0)
1151 goto error;
1152
1153 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1154 scp_data >> 16);
1155 if (status < 0)
1156 goto error;
1157
1158 /* OK, now check if the write itself has executed*/
1159 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1160 VENDOR_DSPIO_STATUS, 0);
1161error:
1162 mutex_unlock(&spec->chipio_mutex);
1163
1164 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1165 -EIO : 0;
1166}
1167
d5c21b88
IM		 1168/*
1169 * Write multiple SCP data to DSP
1170 */
01ef7dbf
IM		 1171static int dspio_write_multiple(struct hda_codec *codec,
1172 unsigned int *buffer, unsigned int size)
1173{
1174 int status = 0;
1175 unsigned int count;
1176
a16fbb85 1177 if (buffer == NULL)
01ef7dbf
IM		 1178 return -EINVAL;
1179
1180 count = 0;
1181 while (count < size) {
1182 status = dspio_write(codec, *buffer++);
1183 if (status != 0)
1184 break;
1185 count++;
1186 }
1187
1188 return status;
1189}
1190
a73d511c
IM		 1191static int dspio_read(struct hda_codec *codec, unsigned int *data)
1192{
1193 int status;
1194
1195 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1196 if (status == -EIO)
1197 return status;
1198
1199 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1200 if (status == -EIO ||
1201 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1202 return -EIO;
1203
1204 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1205 VENDOR_DSPIO_SCP_READ_DATA, 0);
1206
1207 return 0;
1208}
1209
1210static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1211 unsigned int *buf_size, unsigned int size_count)
1212{
1213 int status = 0;
1214 unsigned int size = *buf_size;
1215 unsigned int count;
1216 unsigned int skip_count;
1217 unsigned int dummy;
1218
a16fbb85 1219 if (buffer == NULL)
a73d511c
IM		 1220 return -1;
1221
1222 count = 0;
1223 while (count < size && count < size_count) {
1224 status = dspio_read(codec, buffer++);
1225 if (status != 0)
1226 break;
1227 count++;
1228 }
1229
1230 skip_count = count;
1231 if (status == 0) {
1232 while (skip_count < size) {
1233 status = dspio_read(codec, &dummy);
1234 if (status != 0)
1235 break;
1236 skip_count++;
1237 }
1238 }
1239 *buf_size = count;
1240
1241 return status;
1242}
1243
d5c21b88
IM		 1244/*
1245 * Construct the SCP header using corresponding fields
1246 */
01ef7dbf
IM		 1247static inline unsigned int
1248make_scp_header(unsigned int target_id, unsigned int source_id,
1249 unsigned int get_flag, unsigned int req,
1250 unsigned int device_flag, unsigned int resp_flag,
1251 unsigned int error_flag, unsigned int data_size)
1252{
1253 unsigned int header = 0;
1254
1255 header = (data_size & 0x1f) << 27;
1256 header |= (error_flag & 0x01) << 26;
1257 header |= (resp_flag & 0x01) << 25;
1258 header |= (device_flag & 0x01) << 24;
1259 header |= (req & 0x7f) << 17;
1260 header |= (get_flag & 0x01) << 16;
1261 header |= (source_id & 0xff) << 8;
1262 header |= target_id & 0xff;
1263
1264 return header;
1265}
1266
d5c21b88
IM		 1267/*
1268 * Extract corresponding fields from SCP header
1269 */
01ef7dbf
IM		 1270static inline void
1271extract_scp_header(unsigned int header,
1272 unsigned int *target_id, unsigned int *source_id,
1273 unsigned int *get_flag, unsigned int *req,
1274 unsigned int *device_flag, unsigned int *resp_flag,
1275 unsigned int *error_flag, unsigned int *data_size)
1276{
1277 if (data_size)
1278 *data_size = (header >> 27) & 0x1f;
1279 if (error_flag)
1280 *error_flag = (header >> 26) & 0x01;
1281 if (resp_flag)
1282 *resp_flag = (header >> 25) & 0x01;
1283 if (device_flag)
1284 *device_flag = (header >> 24) & 0x01;
1285 if (req)
1286 *req = (header >> 17) & 0x7f;
1287 if (get_flag)
1288 *get_flag = (header >> 16) & 0x01;
1289 if (source_id)
1290 *source_id = (header >> 8) & 0xff;
1291 if (target_id)
1292 *target_id = header & 0xff;
1293}
1294
1295#define SCP_MAX_DATA_WORDS (16)
1296
1297/* Structure to contain any SCP message */
1298struct scp_msg {
1299 unsigned int hdr;
1300 unsigned int data[SCP_MAX_DATA_WORDS];
1301};
1302
a73d511c
IM		 1303static void dspio_clear_response_queue(struct hda_codec *codec)
1304{
1305 unsigned int dummy = 0;
1306 int status = -1;
1307
1308 /* clear all from the response queue */
1309 do {
1310 status = dspio_read(codec, &dummy);
1311 } while (status == 0);
1312}
1313
1314static int dspio_get_response_data(struct hda_codec *codec)
1315{
1316 struct ca0132_spec *spec = codec->spec;
1317 unsigned int data = 0;
1318 unsigned int count;
1319
1320 if (dspio_read(codec, &data) < 0)
1321 return -EIO;
1322
1323 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1324 spec->scp_resp_header = data;
1325 spec->scp_resp_count = data >> 27;
1326 count = spec->wait_num_data;
1327 dspio_read_multiple(codec, spec->scp_resp_data,
1328 &spec->scp_resp_count, count);
1329 return 0;
1330 }
1331
1332 return -EIO;
1333}
1334
d5c21b88
IM		 1335/*
1336 * Send SCP message to DSP
1337 */
01ef7dbf
IM		 1338static int dspio_send_scp_message(struct hda_codec *codec,
1339 unsigned char *send_buf,
1340 unsigned int send_buf_size,
1341 unsigned char *return_buf,
1342 unsigned int return_buf_size,
1343 unsigned int *bytes_returned)
1344{
1345 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 1346 int status = -1;
1347 unsigned int scp_send_size = 0;
1348 unsigned int total_size;
1349 bool waiting_for_resp = false;
1350 unsigned int header;
1351 struct scp_msg *ret_msg;
1352 unsigned int resp_src_id, resp_target_id;
1353 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1354
1355 if (bytes_returned)
1356 *bytes_returned = 0;
1357
1358 /* get scp header from buffer */
1359 header = *((unsigned int *)send_buf);
1360 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1361 &device_flag, NULL, NULL, &data_size);
1362 scp_send_size = data_size + 1;
1363 total_size = (scp_send_size * 4);
1364
1365 if (send_buf_size < total_size)
1366 return -EINVAL;
1367
1368 if (get_flag || device_flag) {
1369 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1370 return -EINVAL;
1371
1372 spec->wait_scp_header = *((unsigned int *)send_buf);
1373
1374 /* swap source id with target id */
1375 resp_target_id = src_id;
1376 resp_src_id = target_id;
1377 spec->wait_scp_header &= 0xffff0000;
1378 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1379 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1380 spec->wait_scp = 1;
1381 waiting_for_resp = true;
1382 }
1383
1384 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1385 scp_send_size);
1386 if (status < 0) {
1387 spec->wait_scp = 0;
1388 return status;
1389 }
1390
1391 if (waiting_for_resp) {
6d67530e 1392 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
01ef7dbf 1393 memset(return_buf, 0, return_buf_size);
01ef7dbf
IM		 1394 do {
1395 msleep(20);
6d67530e 1396 } while (spec->wait_scp && time_before(jiffies, timeout));
01ef7dbf 1397 waiting_for_resp = false;
6d67530e 1398 if (!spec->wait_scp) {
01ef7dbf
IM		 1399 ret_msg = (struct scp_msg *)return_buf;
1400 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1401 memcpy(&ret_msg->data, spec->scp_resp_data,
1402 spec->wait_num_data);
1403 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1404 status = 0;
1405 } else {
1406 status = -EIO;
1407 }
1408 spec->wait_scp = 0;
1409 }
1410
1411 return status;
1412}
1413
d5c21b88
IM		 1414/**
1415 * Prepare and send the SCP message to DSP
1416 * @codec: the HDA codec
1417 * @mod_id: ID of the DSP module to send the command
1418 * @req: ID of request to send to the DSP module
1419 * @dir: SET or GET
1420 * @data: pointer to the data to send with the request, request specific
1421 * @len: length of the data, in bytes
1422 * @reply: point to the buffer to hold data returned for a reply
1423 * @reply_len: length of the reply buffer returned from GET
1424 *
1425 * Returns zero or a negative error code.
1426 */
01ef7dbf
IM		 1427static int dspio_scp(struct hda_codec *codec,
1428 int mod_id, int req, int dir, void *data, unsigned int len,
1429 void *reply, unsigned int *reply_len)
1430{
1431 int status = 0;
1432 struct scp_msg scp_send, scp_reply;
1433 unsigned int ret_bytes, send_size, ret_size;
1434 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1435 unsigned int reply_data_size;
1436
1437 memset(&scp_send, 0, sizeof(scp_send));
1438 memset(&scp_reply, 0, sizeof(scp_reply));
1439
1440 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1441 return -EINVAL;
1442
1443 if (dir == SCP_GET && reply == NULL) {
4e76a883 1444 codec_dbg(codec, "dspio_scp get but has no buffer\n");
01ef7dbf
IM		 1445 return -EINVAL;
1446 }
1447
1448 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
4e76a883 1449 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
01ef7dbf
IM		 1450 return -EINVAL;
1451 }
1452
1453 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1454 0, 0, 0, len/sizeof(unsigned int));
1455 if (data != NULL && len > 0) {
1456 len = min((unsigned int)(sizeof(scp_send.data)), len);
1457 memcpy(scp_send.data, data, len);
1458 }
1459
1460 ret_bytes = 0;
1461 send_size = sizeof(unsigned int) + len;
1462 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1463 send_size, (unsigned char *)&scp_reply,
1464 sizeof(scp_reply), &ret_bytes);
1465
1466 if (status < 0) {
4e76a883 1467 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
01ef7dbf
IM		 1468 return status;
1469 }
1470
1471 /* extract send and reply headers members */
1472 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1473 NULL, NULL, NULL, NULL, NULL);
1474 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1475 &reply_resp_flag, &reply_error_flag,
1476 &reply_data_size);
1477
1478 if (!send_get_flag)
1479 return 0;
1480
1481 if (reply_resp_flag && !reply_error_flag) {
1482 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1483 / sizeof(unsigned int);
1484
1485 if (*reply_len < ret_size*sizeof(unsigned int)) {
4e76a883 1486 codec_dbg(codec, "reply too long for buf\n");
01ef7dbf
IM		 1487 return -EINVAL;
1488 } else if (ret_size != reply_data_size) {
4e76a883 1489 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
01ef7dbf 1490 return -EINVAL;
46a049da
AB		 1491 } else if (!reply) {
1492 codec_dbg(codec, "NULL reply\n");
1493 return -EINVAL;
01ef7dbf
IM		 1494 } else {
1495 *reply_len = ret_size*sizeof(unsigned int);
1496 memcpy(reply, scp_reply.data, *reply_len);
1497 }
1498 } else {
4e76a883 1499 codec_dbg(codec, "reply ill-formed or errflag set\n");
01ef7dbf
IM		 1500 return -EIO;
1501 }
1502
1503 return status;
1504}
1505
5aaca44d
IM		 1506/*
1507 * Set DSP parameters
1508 */
1509static int dspio_set_param(struct hda_codec *codec, int mod_id,
1510 int req, void *data, unsigned int len)
1511{
1512 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1513}
1514
1515static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1516 int req, unsigned int data)
1517{
1518 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1519}
1520
d5c21b88
IM		 1521/*
1522 * Allocate a DSP DMA channel via an SCP message
1523 */
01ef7dbf
IM		 1524static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1525{
1526 int status = 0;
1527 unsigned int size = sizeof(dma_chan);
1528
4e76a883 1529 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
01ef7dbf
IM		 1530 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1531 SCP_GET, NULL, 0, dma_chan, &size);
1532
1533 if (status < 0) {
4e76a883 1534 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1535 return status;
1536 }
1537
1538 if ((*dma_chan + 1) == 0) {
4e76a883 1539 codec_dbg(codec, "no free dma channels to allocate\n");
01ef7dbf
IM		 1540 return -EBUSY;
1541 }
1542
4e76a883
TI		 1543 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1544 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
01ef7dbf
IM		 1545
1546 return status;
1547}
1548
d5c21b88
IM		 1549/*
1550 * Free a DSP DMA via an SCP message
1551 */
01ef7dbf
IM		 1552static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1553{
1554 int status = 0;
1555 unsigned int dummy = 0;
1556
4e76a883
TI		 1557 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1558 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
01ef7dbf
IM		 1559
1560 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1561 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1562
1563 if (status < 0) {
4e76a883 1564 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
01ef7dbf
IM		 1565 return status;
1566 }
1567
4e76a883 1568 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
01ef7dbf
IM		 1569
1570 return status;
1571}
1572
1573/*
d5c21b88 1574 * (Re)start the DSP
01ef7dbf
IM		 1575 */
1576static int dsp_set_run_state(struct hda_codec *codec)
1577{
1578 unsigned int dbg_ctrl_reg;
1579 unsigned int halt_state;
1580 int err;
1581
1582 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1583 if (err < 0)
1584 return err;
1585
1586 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1587 DSP_DBGCNTL_STATE_LOBIT;
1588
1589 if (halt_state != 0) {
1590 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1591 DSP_DBGCNTL_SS_MASK);
1592 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1593 dbg_ctrl_reg);
1594 if (err < 0)
1595 return err;
1596
1597 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1598 DSP_DBGCNTL_EXEC_MASK;
1599 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1600 dbg_ctrl_reg);
1601 if (err < 0)
1602 return err;
1603 }
1604
1605 return 0;
1606}
1607
d5c21b88
IM		 1608/*
1609 * Reset the DSP
1610 */
01ef7dbf
IM		 1611static int dsp_reset(struct hda_codec *codec)
1612{
1613 unsigned int res;
1614 int retry = 20;
1615
4e76a883 1616 codec_dbg(codec, "dsp_reset\n");
01ef7dbf
IM		 1617 do {
1618 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1619 retry--;
1620 } while (res == -EIO && retry);
1621
1622 if (!retry) {
4e76a883 1623 codec_dbg(codec, "dsp_reset timeout\n");
01ef7dbf
IM		 1624 return -EIO;
1625 }
1626
1627 return 0;
1628}
1629
d5c21b88
IM		 1630/*
1631 * Convert chip address to DSP address
1632 */
01ef7dbf
IM		 1633static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1634 bool *code, bool *yram)
1635{
1636 *code = *yram = false;
1637
1638 if (UC_RANGE(chip_addx, 1)) {
1639 *code = true;
1640 return UC_OFF(chip_addx);
1641 } else if (X_RANGE_ALL(chip_addx, 1)) {
1642 return X_OFF(chip_addx);
1643 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1644 *yram = true;
1645 return Y_OFF(chip_addx);
1646 }
1647
4a8b89f9 1648 return INVALID_CHIP_ADDRESS;
01ef7dbf
IM		 1649}
1650
d5c21b88
IM		 1651/*
1652 * Check if the DSP DMA is active
1653 */
01ef7dbf
IM		 1654static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1655{
1656 unsigned int dma_chnlstart_reg;
1657
1658 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1659
1660 return ((dma_chnlstart_reg & (1 <<
1661 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1662}
1663
1664static int dsp_dma_setup_common(struct hda_codec *codec,
1665 unsigned int chip_addx,
1666 unsigned int dma_chan,
1667 unsigned int port_map_mask,
1668 bool ovly)
1669{
1670 int status = 0;
1671 unsigned int chnl_prop;
1672 unsigned int dsp_addx;
1673 unsigned int active;
1674 bool code, yram;
1675
4e76a883 1676 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
01ef7dbf
IM		 1677
1678 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
4e76a883 1679 codec_dbg(codec, "dma chan num invalid\n");
01ef7dbf
IM		 1680 return -EINVAL;
1681 }
1682
1683 if (dsp_is_dma_active(codec, dma_chan)) {
4e76a883 1684 codec_dbg(codec, "dma already active\n");
01ef7dbf
IM		 1685 return -EBUSY;
1686 }
1687
1688 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1689
1690 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 1691 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 1692 return -ENXIO;
1693 }
1694
1695 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1696 active = 0;
1697
4e76a883 1698 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
01ef7dbf
IM		 1699
1700 if (ovly) {
1701 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1702 &chnl_prop);
1703
1704 if (status < 0) {
4e76a883 1705 codec_dbg(codec, "read CHNLPROP Reg fail\n");
01ef7dbf
IM		 1706 return status;
1707 }
4e76a883 1708 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
01ef7dbf
IM		 1709 }
1710
1711 if (!code)
1712 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1713 else
1714 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1715
1716 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1717
1718 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1719 if (status < 0) {
4e76a883 1720 codec_dbg(codec, "write CHNLPROP Reg fail\n");
01ef7dbf
IM		 1721 return status;
1722 }
4e76a883 1723 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
01ef7dbf
IM		 1724
1725 if (ovly) {
1726 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1727 &active);
1728
1729 if (status < 0) {
4e76a883 1730 codec_dbg(codec, "read ACTIVE Reg fail\n");
01ef7dbf
IM		 1731 return status;
1732 }
4e76a883 1733 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
01ef7dbf
IM		 1734 }
1735
1736 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1737 DSPDMAC_ACTIVE_AAR_MASK;
1738
1739 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1740 if (status < 0) {
4e76a883 1741 codec_dbg(codec, "write ACTIVE Reg fail\n");
01ef7dbf
IM		 1742 return status;
1743 }
1744
4e76a883 1745 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
01ef7dbf
IM		 1746
1747 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1748 port_map_mask);
1749 if (status < 0) {
4e76a883 1750 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
01ef7dbf
IM		 1751 return status;
1752 }
4e76a883 1753 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
01ef7dbf
IM		 1754
1755 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1756 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1757 if (status < 0) {
4e76a883 1758 codec_dbg(codec, "write IRQCNT Reg fail\n");
01ef7dbf
IM		 1759 return status;
1760 }
4e76a883 1761 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
01ef7dbf 1762
4e76a883 1763 codec_dbg(codec,
01ef7dbf
IM		 1764 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1765 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1766 chip_addx, dsp_addx, dma_chan,
1767 port_map_mask, chnl_prop, active);
1768
4e76a883 1769 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
01ef7dbf
IM		 1770
1771 return 0;
1772}
1773
d5c21b88
IM		 1774/*
1775 * Setup the DSP DMA per-transfer-specific registers
1776 */
01ef7dbf
IM		 1777static int dsp_dma_setup(struct hda_codec *codec,
1778 unsigned int chip_addx,
1779 unsigned int count,
1780 unsigned int dma_chan)
1781{
1782 int status = 0;
1783 bool code, yram;
1784 unsigned int dsp_addx;
1785 unsigned int addr_field;
1786 unsigned int incr_field;
1787 unsigned int base_cnt;
1788 unsigned int cur_cnt;
1789 unsigned int dma_cfg = 0;
1790 unsigned int adr_ofs = 0;
1791 unsigned int xfr_cnt = 0;
1792 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1793 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1794
4e76a883 1795 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
01ef7dbf
IM		 1796
1797 if (count > max_dma_count) {
4e76a883 1798 codec_dbg(codec, "count too big\n");
01ef7dbf
IM		 1799 return -EINVAL;
1800 }
1801
1802 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1803 if (dsp_addx == INVALID_CHIP_ADDRESS) {
4e76a883 1804 codec_dbg(codec, "invalid chip addr\n");
01ef7dbf
IM		 1805 return -ENXIO;
1806 }
1807
4e76a883 1808 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
01ef7dbf
IM		 1809
1810 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1811 incr_field = 0;
1812
1813 if (!code) {
1814 addr_field <<= 1;
1815 if (yram)
1816 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1817
1818 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1819 }
1820
1821 dma_cfg = addr_field + incr_field;
1822 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1823 dma_cfg);
1824 if (status < 0) {
4e76a883 1825 codec_dbg(codec, "write DMACFG Reg fail\n");
01ef7dbf
IM		 1826 return status;
1827 }
4e76a883 1828 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
01ef7dbf
IM		 1829
1830 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1831 (code ? 0 : 1));
1832
1833 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1834 adr_ofs);
1835 if (status < 0) {
4e76a883 1836 codec_dbg(codec, "write DSPADROFS Reg fail\n");
01ef7dbf
IM		 1837 return status;
1838 }
4e76a883 1839 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
01ef7dbf
IM		 1840
1841 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1842
1843 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1844
1845 xfr_cnt = base_cnt | cur_cnt;
1846
1847 status = chipio_write(codec,
1848 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1849 if (status < 0) {
4e76a883 1850 codec_dbg(codec, "write XFRCNT Reg fail\n");
01ef7dbf
IM		 1851 return status;
1852 }
4e76a883 1853 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
01ef7dbf 1854
4e76a883 1855 codec_dbg(codec,
01ef7dbf
IM		 1856 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1857 "ADROFS=0x%x, XFRCNT=0x%x\n",
1858 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1859
4e76a883 1860 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
01ef7dbf
IM		 1861
1862 return 0;
1863}
1864
d5c21b88
IM		 1865/*
1866 * Start the DSP DMA
1867 */
01ef7dbf
IM		 1868static int dsp_dma_start(struct hda_codec *codec,
1869 unsigned int dma_chan, bool ovly)
1870{
1871 unsigned int reg = 0;
1872 int status = 0;
1873
4e76a883 1874 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
01ef7dbf
IM		 1875
1876 if (ovly) {
1877 status = chipio_read(codec,
1878 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1879
1880 if (status < 0) {
4e76a883 1881 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 1882 return status;
1883 }
4e76a883 1884 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
01ef7dbf
IM		 1885
1886 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1887 DSPDMAC_CHNLSTART_DIS_MASK);
1888 }
1889
1890 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1891 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1892 if (status < 0) {
4e76a883 1893 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 1894 return status;
1895 }
4e76a883 1896 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
01ef7dbf
IM		 1897
1898 return status;
1899}
1900
d5c21b88
IM		 1901/*
1902 * Stop the DSP DMA
1903 */
01ef7dbf
IM		 1904static int dsp_dma_stop(struct hda_codec *codec,
1905 unsigned int dma_chan, bool ovly)
1906{
1907 unsigned int reg = 0;
1908 int status = 0;
1909
4e76a883 1910 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
01ef7dbf
IM		 1911
1912 if (ovly) {
1913 status = chipio_read(codec,
1914 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1915
1916 if (status < 0) {
4e76a883 1917 codec_dbg(codec, "read CHNLSTART reg fail\n");
01ef7dbf
IM		 1918 return status;
1919 }
4e76a883 1920 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
01ef7dbf
IM		 1921 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1922 DSPDMAC_CHNLSTART_DIS_MASK);
1923 }
1924
1925 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1926 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1927 if (status < 0) {
4e76a883 1928 codec_dbg(codec, "write CHNLSTART reg fail\n");
01ef7dbf
IM		 1929 return status;
1930 }
4e76a883 1931 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
01ef7dbf
IM		 1932
1933 return status;
1934}
1935
d5c21b88
IM		 1936/**
1937 * Allocate router ports
1938 *
1939 * @codec: the HDA codec
1940 * @num_chans: number of channels in the stream
1941 * @ports_per_channel: number of ports per channel
1942 * @start_device: start device
1943 * @port_map: pointer to the port list to hold the allocated ports
1944 *
1945 * Returns zero or a negative error code.
1946 */
01ef7dbf
IM		 1947static int dsp_allocate_router_ports(struct hda_codec *codec,
1948 unsigned int num_chans,
1949 unsigned int ports_per_channel,
1950 unsigned int start_device,
1951 unsigned int *port_map)
1952{
1953 int status = 0;
1954 int res;
1955 u8 val;
1956
1957 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1958 if (status < 0)
1959 return status;
1960
1961 val = start_device << 6;
1962 val |= (ports_per_channel - 1) << 4;
1963 val |= num_chans - 1;
1964
1965 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1966 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1967 val);
1968
1969 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1970 VENDOR_CHIPIO_PORT_ALLOC_SET,
1971 MEM_CONNID_DSP);
1972
1973 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1974 if (status < 0)
1975 return status;
1976
1977 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1978 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1979
1980 *port_map = res;
1981
1982 return (res < 0) ? res : 0;
1983}
1984
d5c21b88
IM		 1985/*
1986 * Free router ports
1987 */
01ef7dbf
IM		 1988static int dsp_free_router_ports(struct hda_codec *codec)
1989{
1990 int status = 0;
1991
1992 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1993 if (status < 0)
1994 return status;
1995
1996 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1997 VENDOR_CHIPIO_PORT_FREE_SET,
1998 MEM_CONNID_DSP);
1999
2000 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2001
2002 return status;
2003}
2004
d5c21b88
IM		 2005/*
2006 * Allocate DSP ports for the download stream
2007 */
01ef7dbf
IM		 2008static int dsp_allocate_ports(struct hda_codec *codec,
2009 unsigned int num_chans,
2010 unsigned int rate_multi, unsigned int *port_map)
2011{
2012 int status;
2013
4e76a883 2014 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
01ef7dbf
IM		 2015
2016 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2017 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2018 return -EINVAL;
2019 }
2020
2021 status = dsp_allocate_router_ports(codec, num_chans,
2022 rate_multi, 0, port_map);
2023
4e76a883 2024 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
01ef7dbf
IM		 2025
2026 return status;
2027}
2028
01ef7dbf
IM		 2029static int dsp_allocate_ports_format(struct hda_codec *codec,
2030 const unsigned short fmt,
2031 unsigned int *port_map)
2032{
2033 int status;
2034 unsigned int num_chans;
2035
2036 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2037 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2038 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2039
2040 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
4e76a883 2041 codec_dbg(codec, "bad rate multiple\n");
01ef7dbf
IM		 2042 return -EINVAL;
2043 }
2044
2045 num_chans = get_hdafmt_chs(fmt) + 1;
2046
2047 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2048
2049 return status;
2050}
2051
d5c21b88
IM		 2052/*
2053 * free DSP ports
2054 */
2055static int dsp_free_ports(struct hda_codec *codec)
2056{
2057 int status;
2058
4e76a883 2059 codec_dbg(codec, " dsp_free_ports() -- begin\n");
d5c21b88
IM		 2060
2061 status = dsp_free_router_ports(codec);
2062 if (status < 0) {
4e76a883 2063 codec_dbg(codec, "free router ports fail\n");
d5c21b88
IM		 2064 return status;
2065 }
4e76a883 2066 codec_dbg(codec, " dsp_free_ports() -- complete\n");
d5c21b88
IM		 2067
2068 return status;
2069}
2070
01ef7dbf
IM		 2071/*
2072 * HDA DMA engine stuffs for DSP code download
2073 */
2074struct dma_engine {
2075 struct hda_codec *codec;
2076 unsigned short m_converter_format;
2077 struct snd_dma_buffer *dmab;
2078 unsigned int buf_size;
2079};
2080
2081
2082enum dma_state {
2083 DMA_STATE_STOP = 0,
2084 DMA_STATE_RUN = 1
2085};
2086
6194b99d 2087static int dma_convert_to_hda_format(struct hda_codec *codec,
e97249dd
IM		 2088 unsigned int sample_rate,
2089 unsigned short channels,
01ef7dbf
IM		 2090 unsigned short *hda_format)
2091{
2092 unsigned int format_val;
2093
b7d023e1
TI		 2094 format_val = snd_hdac_calc_stream_format(sample_rate,
2095 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
01ef7dbf
IM		 2096
2097 if (hda_format)
2098 *hda_format = (unsigned short)format_val;
2099
2100 return 0;
2101}
2102
d5c21b88
IM		 2103/*
2104 * Reset DMA for DSP download
2105 */
01ef7dbf
IM		 2106static int dma_reset(struct dma_engine *dma)
2107{
2108 struct hda_codec *codec = dma->codec;
2109 struct ca0132_spec *spec = codec->spec;
2110 int status;
2111
b3667bd7 2112 if (dma->dmab->area)
01ef7dbf
IM		 2113 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2114
2115 status = snd_hda_codec_load_dsp_prepare(codec,
2116 dma->m_converter_format,
2117 dma->buf_size,
2118 dma->dmab);
2119 if (status < 0)
2120 return status;
2121 spec->dsp_stream_id = status;
2122 return 0;
2123}
2124
2125static int dma_set_state(struct dma_engine *dma, enum dma_state state)
95c6e9cb 2126{
01ef7dbf
IM		 2127 bool cmd;
2128
01ef7dbf
IM		 2129 switch (state) {
2130 case DMA_STATE_STOP:
2131 cmd = false;
2132 break;
2133 case DMA_STATE_RUN:
2134 cmd = true;
2135 break;
2136 default:
c41999a2
DH		 2137 return 0;
2138 }
01ef7dbf
IM		 2139
2140 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2141 return 0;
95c6e9cb
IM		 2142}
2143
01ef7dbf
IM		 2144static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2145{
2146 return dma->dmab->bytes;
2147}
95c6e9cb 2148
01ef7dbf
IM		 2149static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2150{
2151 return dma->dmab->area;
2152}
95c6e9cb 2153
01ef7dbf
IM		 2154static int dma_xfer(struct dma_engine *dma,
2155 const unsigned int *data,
2156 unsigned int count)
2157{
2158 memcpy(dma->dmab->area, data, count);
2159 return 0;
2160}
95c6e9cb 2161
01ef7dbf
IM		 2162static void dma_get_converter_format(
2163 struct dma_engine *dma,
2164 unsigned short *format)
2165{
2166 if (format)
2167 *format = dma->m_converter_format;
2168}
95c6e9cb 2169
01ef7dbf 2170static unsigned int dma_get_stream_id(struct dma_engine *dma)
95c6e9cb 2171{
01ef7dbf 2172 struct ca0132_spec *spec = dma->codec->spec;
95c6e9cb 2173
01ef7dbf 2174 return spec->dsp_stream_id;
95c6e9cb
IM		 2175}
2176
01ef7dbf
IM		 2177struct dsp_image_seg {
2178 u32 magic;
2179 u32 chip_addr;
2180 u32 count;
2181 u32 data[0];
2182};
2183
2184static const u32 g_magic_value = 0x4c46584d;
2185static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2186
2187static bool is_valid(const struct dsp_image_seg *p)
95c6e9cb 2188{
01ef7dbf
IM		 2189 return p->magic == g_magic_value;
2190}
95c6e9cb 2191
01ef7dbf
IM		 2192static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2193{
2194 return g_chip_addr_magic_value == p->chip_addr;
2195}
95c6e9cb 2196
01ef7dbf
IM		 2197static bool is_last(const struct dsp_image_seg *p)
2198{
2199 return p->count == 0;
2200}
95c6e9cb 2201
01ef7dbf
IM		 2202static size_t dsp_sizeof(const struct dsp_image_seg *p)
2203{
2204 return sizeof(*p) + p->count*sizeof(u32);
2205}
2206
2207static const struct dsp_image_seg *get_next_seg_ptr(
2208 const struct dsp_image_seg *p)
2209{
2210 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
95c6e9cb
IM		 2211}
2212
2213/*
01ef7dbf 2214 * CA0132 chip DSP transfer stuffs. For DSP download.
95c6e9cb 2215 */
8ae3124b 2216#define INVALID_DMA_CHANNEL (~0U)
95c6e9cb 2217
d5c21b88
IM		 2218/*
2219 * Program a list of address/data pairs via the ChipIO widget.
2220 * The segment data is in the format of successive pairs of words.
2221 * These are repeated as indicated by the segment's count field.
2222 */
01ef7dbf
IM		 2223static int dspxfr_hci_write(struct hda_codec *codec,
2224 const struct dsp_image_seg *fls)
95c6e9cb 2225{
01ef7dbf
IM		 2226 int status;
2227 const u32 *data;
2228 unsigned int count;
95c6e9cb 2229
01ef7dbf 2230 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
4e76a883 2231 codec_dbg(codec, "hci_write invalid params\n");
01ef7dbf 2232 return -EINVAL;
95c6e9cb
IM		 2233 }
2234
01ef7dbf
IM		 2235 count = fls->count;
2236 data = (u32 *)(fls->data);
2237 while (count >= 2) {
2238 status = chipio_write(codec, data[0], data[1]);
2239 if (status < 0) {
4e76a883 2240 codec_dbg(codec, "hci_write chipio failed\n");
01ef7dbf
IM		 2241 return status;
2242 }
2243 count -= 2;
2244 data += 2;
2245 }
2246 return 0;
95c6e9cb
IM		 2247}
2248
d5c21b88
IM		 2249/**
2250 * Write a block of data into DSP code or data RAM using pre-allocated
2251 * DMA engine.
2252 *
2253 * @codec: the HDA codec
2254 * @fls: pointer to a fast load image
2255 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2256 * no relocation
2257 * @dma_engine: pointer to DMA engine to be used for DSP download
2258 * @dma_chan: The number of DMA channels used for DSP download
2259 * @port_map_mask: port mapping
2260 * @ovly: TRUE if overlay format is required
2261 *
2262 * Returns zero or a negative error code.
2263 */
01ef7dbf
IM		 2264static int dspxfr_one_seg(struct hda_codec *codec,
2265 const struct dsp_image_seg *fls,
2266 unsigned int reloc,
2267 struct dma_engine *dma_engine,
2268 unsigned int dma_chan,
2269 unsigned int port_map_mask,
2270 bool ovly)
95c6e9cb 2271{
406261ce 2272 int status = 0;
01ef7dbf
IM		 2273 bool comm_dma_setup_done = false;
2274 const unsigned int *data;
2275 unsigned int chip_addx;
2276 unsigned int words_to_write;
2277 unsigned int buffer_size_words;
2278 unsigned char *buffer_addx;
2279 unsigned short hda_format;
2280 unsigned int sample_rate_div;
2281 unsigned int sample_rate_mul;
2282 unsigned int num_chans;
2283 unsigned int hda_frame_size_words;
2284 unsigned int remainder_words;
2285 const u32 *data_remainder;
2286 u32 chip_addx_remainder;
2287 unsigned int run_size_words;
2288 const struct dsp_image_seg *hci_write = NULL;
6d67530e
IM		 2289 unsigned long timeout;
2290 bool dma_active;
01ef7dbf
IM		 2291
2292 if (fls == NULL)
2293 return -EINVAL;
2294 if (is_hci_prog_list_seg(fls)) {
2295 hci_write = fls;
2296 fls = get_next_seg_ptr(fls);
2297 }
95c6e9cb 2298
01ef7dbf 2299 if (hci_write && (!fls || is_last(fls))) {
4e76a883 2300 codec_dbg(codec, "hci_write\n");
01ef7dbf
IM		 2301 return dspxfr_hci_write(codec, hci_write);
2302 }
95c6e9cb 2303
01ef7dbf 2304 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
4e76a883 2305 codec_dbg(codec, "Invalid Params\n");
01ef7dbf 2306 return -EINVAL;
95c6e9cb
IM		 2307 }
2308
01ef7dbf
IM		 2309 data = fls->data;
2310 chip_addx = fls->chip_addr,
2311 words_to_write = fls->count;
2312
2313 if (!words_to_write)
2314 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2315 if (reloc)
2316 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2317
2318 if (!UC_RANGE(chip_addx, words_to_write) &&
2319 !X_RANGE_ALL(chip_addx, words_to_write) &&
2320 !Y_RANGE_ALL(chip_addx, words_to_write)) {
4e76a883 2321 codec_dbg(codec, "Invalid chip_addx Params\n");
01ef7dbf 2322 return -EINVAL;
95c6e9cb
IM		 2323 }
2324
01ef7dbf
IM		 2325 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2326 sizeof(u32);
2327
2328 buffer_addx = dma_get_buffer_addr(dma_engine);
2329
2330 if (buffer_addx == NULL) {
4e76a883 2331 codec_dbg(codec, "dma_engine buffer NULL\n");
01ef7dbf
IM		 2332 return -EINVAL;
2333 }
2334
2335 dma_get_converter_format(dma_engine, &hda_format);
2336 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2337 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2338 num_chans = get_hdafmt_chs(hda_format) + 1;
2339
2340 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2341 (num_chans * sample_rate_mul / sample_rate_div));
2342
3bc085a1 2343 if (hda_frame_size_words == 0) {
4e76a883 2344 codec_dbg(codec, "frmsz zero\n");
3bc085a1
XW		 2345 return -EINVAL;
2346 }
2347
01ef7dbf
IM		 2348 buffer_size_words = min(buffer_size_words,
2349 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2350 65536 : 32768));
2351 buffer_size_words -= buffer_size_words % hda_frame_size_words;
4e76a883 2352 codec_dbg(codec,
01ef7dbf
IM		 2353 "chpadr=0x%08x frmsz=%u nchan=%u "
2354 "rate_mul=%u div=%u bufsz=%u\n",
2355 chip_addx, hda_frame_size_words, num_chans,
2356 sample_rate_mul, sample_rate_div, buffer_size_words);
2357
3bc085a1 2358 if (buffer_size_words < hda_frame_size_words) {
4e76a883 2359 codec_dbg(codec, "dspxfr_one_seg:failed\n");
01ef7dbf
IM		 2360 return -EINVAL;
2361 }
2362
2363 remainder_words = words_to_write % hda_frame_size_words;
2364 data_remainder = data;
2365 chip_addx_remainder = chip_addx;
2366
2367 data += remainder_words;
2368 chip_addx += remainder_words*sizeof(u32);
2369 words_to_write -= remainder_words;
2370
2371 while (words_to_write != 0) {
2372 run_size_words = min(buffer_size_words, words_to_write);
4e76a883 2373 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
01ef7dbf
IM		 2374 words_to_write, run_size_words, remainder_words);
2375 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2376 if (!comm_dma_setup_done) {
2377 status = dsp_dma_stop(codec, dma_chan, ovly);
2378 if (status < 0)
425a7880 2379 return status;
01ef7dbf
IM		 2380 status = dsp_dma_setup_common(codec, chip_addx,
2381 dma_chan, port_map_mask, ovly);
2382 if (status < 0)
2383 return status;
2384 comm_dma_setup_done = true;
2385 }
2386
2387 status = dsp_dma_setup(codec, chip_addx,
2388 run_size_words, dma_chan);
2389 if (status < 0)
2390 return status;
2391 status = dsp_dma_start(codec, dma_chan, ovly);
2392 if (status < 0)
2393 return status;
2394 if (!dsp_is_dma_active(codec, dma_chan)) {
4e76a883 2395 codec_dbg(codec, "dspxfr:DMA did not start\n");
01ef7dbf
IM		 2396 return -EIO;
2397 }
2398 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2399 if (status < 0)
2400 return status;
2401 if (remainder_words != 0) {
2402 status = chipio_write_multiple(codec,
2403 chip_addx_remainder,
2404 data_remainder,
2405 remainder_words);
b3667bd7
TI		 2406 if (status < 0)
2407 return status;
01ef7dbf
IM		 2408 remainder_words = 0;
2409 }
2410 if (hci_write) {
2411 status = dspxfr_hci_write(codec, hci_write);
b3667bd7
TI		 2412 if (status < 0)
2413 return status;
01ef7dbf
IM		 2414 hci_write = NULL;
2415 }
6d67530e
IM		 2416
2417 timeout = jiffies + msecs_to_jiffies(2000);
2418 do {
2419 dma_active = dsp_is_dma_active(codec, dma_chan);
2420 if (!dma_active)
01ef7dbf 2421 break;
6d67530e
IM		 2422 msleep(20);
2423 } while (time_before(jiffies, timeout));
2424 if (dma_active)
2425 break;
2426
4e76a883 2427 codec_dbg(codec, "+++++ DMA complete\n");
01ef7dbf 2428 dma_set_state(dma_engine, DMA_STATE_STOP);
b3667bd7 2429 status = dma_reset(dma_engine);
01ef7dbf
IM		 2430
2431 if (status < 0)
2432 return status;
2433
2434 data += run_size_words;
2435 chip_addx += run_size_words*sizeof(u32);
2436 words_to_write -= run_size_words;
2437 }
2438
2439 if (remainder_words != 0) {
2440 status = chipio_write_multiple(codec, chip_addx_remainder,
2441 data_remainder, remainder_words);
2442 }
2443
2444 return status;
95c6e9cb
IM		 2445}
2446
d5c21b88
IM		 2447/**
2448 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2449 *
2450 * @codec: the HDA codec
2451 * @fls_data: pointer to a fast load image
2452 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2453 * no relocation
e97249dd 2454 * @sample_rate: sampling rate of the stream used for DSP download
e60b2c7f 2455 * @channels: channels of the stream used for DSP download
d5c21b88
IM		 2456 * @ovly: TRUE if overlay format is required
2457 *
2458 * Returns zero or a negative error code.
2459 */
01ef7dbf
IM		 2460static int dspxfr_image(struct hda_codec *codec,
2461 const struct dsp_image_seg *fls_data,
e97249dd
IM		 2462 unsigned int reloc,
2463 unsigned int sample_rate,
2464 unsigned short channels,
01ef7dbf 2465 bool ovly)
95c6e9cb
IM		 2466{
2467 struct ca0132_spec *spec = codec->spec;
01ef7dbf
IM		 2468 int status;
2469 unsigned short hda_format = 0;
2470 unsigned int response;
2471 unsigned char stream_id = 0;
2472 struct dma_engine *dma_engine;
2473 unsigned int dma_chan;
2474 unsigned int port_map_mask;
2475
2476 if (fls_data == NULL)
2477 return -EINVAL;
2478
2479 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
549e8292
TI		 2480 if (!dma_engine)
2481 return -ENOMEM;
95c6e9cb 2482
01ef7dbf
IM		 2483 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2484 if (!dma_engine->dmab) {
549e8292
TI		 2485 kfree(dma_engine);
2486 return -ENOMEM;
01ef7dbf 2487 }
95c6e9cb 2488
01ef7dbf 2489 dma_engine->codec = codec;
6194b99d 2490 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
01ef7dbf
IM		 2491 dma_engine->m_converter_format = hda_format;
2492 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2493 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2494
8ae3124b 2495 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
01ef7dbf
IM		 2496
2497 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2498 hda_format, &response);
2499
2500 if (status < 0) {
4e76a883 2501 codec_dbg(codec, "set converter format fail\n");
01ef7dbf
IM		 2502 goto exit;
2503 }
2504
2505 status = snd_hda_codec_load_dsp_prepare(codec,
2506 dma_engine->m_converter_format,
2507 dma_engine->buf_size,
2508 dma_engine->dmab);
2509 if (status < 0)
95c6e9cb 2510 goto exit;
01ef7dbf
IM		 2511 spec->dsp_stream_id = status;
2512
2513 if (ovly) {
2514 status = dspio_alloc_dma_chan(codec, &dma_chan);
2515 if (status < 0) {
4e76a883 2516 codec_dbg(codec, "alloc dmachan fail\n");
8ae3124b 2517 dma_chan = INVALID_DMA_CHANNEL;
01ef7dbf
IM		 2518 goto exit;
2519 }
2520 }
95c6e9cb 2521
01ef7dbf
IM		 2522 port_map_mask = 0;
2523 status = dsp_allocate_ports_format(codec, hda_format,
2524 &port_map_mask);
2525 if (status < 0) {
4e76a883 2526 codec_dbg(codec, "alloc ports fail\n");
01ef7dbf
IM		 2527 goto exit;
2528 }
2529
2530 stream_id = dma_get_stream_id(dma_engine);
2531 status = codec_set_converter_stream_channel(codec,
2532 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2533 if (status < 0) {
4e76a883 2534 codec_dbg(codec, "set stream chan fail\n");
01ef7dbf
IM		 2535 goto exit;
2536 }
2537
2538 while ((fls_data != NULL) && !is_last(fls_data)) {
2539 if (!is_valid(fls_data)) {
4e76a883 2540 codec_dbg(codec, "FLS check fail\n");
01ef7dbf
IM		 2541 status = -EINVAL;
2542 goto exit;
2543 }
2544 status = dspxfr_one_seg(codec, fls_data, reloc,
2545 dma_engine, dma_chan,
2546 port_map_mask, ovly);
2547 if (status < 0)
2548 break;
2549
2550 if (is_hci_prog_list_seg(fls_data))
2551 fls_data = get_next_seg_ptr(fls_data);
2552
2553 if ((fls_data != NULL) && !is_last(fls_data))
2554 fls_data = get_next_seg_ptr(fls_data);
2555 }
2556
2557 if (port_map_mask != 0)
2558 status = dsp_free_ports(codec);
2559
2560 if (status < 0)
95c6e9cb
IM		 2561 goto exit;
2562
01ef7dbf
IM		 2563 status = codec_set_converter_stream_channel(codec,
2564 WIDGET_CHIP_CTRL, 0, 0, &response);
2565
95c6e9cb 2566exit:
01ef7dbf
IM		 2567 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2568 dspio_free_dma_chan(codec, dma_chan);
2569
b3667bd7 2570 if (dma_engine->dmab->area)
01ef7dbf
IM		 2571 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2572 kfree(dma_engine->dmab);
2573 kfree(dma_engine);
2574
2575 return status;
95c6e9cb
IM		 2576}
2577
2578/*
01ef7dbf 2579 * CA0132 DSP download stuffs.
95c6e9cb 2580 */
01ef7dbf 2581static void dspload_post_setup(struct hda_codec *codec)
95c6e9cb 2582{
4e76a883 2583 codec_dbg(codec, "---- dspload_post_setup ------\n");
95c6e9cb 2584
01ef7dbf
IM		 2585 /*set DSP speaker to 2.0 configuration*/
2586 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2587 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
95c6e9cb 2588
01ef7dbf
IM		 2589 /*update write pointer*/
2590 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2591}
95c6e9cb 2592
d5c21b88 2593/**
e60b2c7f 2594 * dspload_image - Download DSP from a DSP Image Fast Load structure.
d5c21b88
IM		 2595 *
2596 * @codec: the HDA codec
2597 * @fls: pointer to a fast load image
2598 * @ovly: TRUE if overlay format is required
2599 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2600 * no relocation
2601 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2602 * @router_chans: number of audio router channels to be allocated (0 means use
2603 * internal defaults; max is 32)
2604 *
e60b2c7f
TI		 2605 * Download DSP from a DSP Image Fast Load structure. This structure is a
2606 * linear, non-constant sized element array of structures, each of which
2607 * contain the count of the data to be loaded, the data itself, and the
2608 * corresponding starting chip address of the starting data location.
d5c21b88
IM		 2609 * Returns zero or a negative error code.
2610 */
01ef7dbf
IM		 2611static int dspload_image(struct hda_codec *codec,
2612 const struct dsp_image_seg *fls,
2613 bool ovly,
2614 unsigned int reloc,
2615 bool autostart,
2616 int router_chans)
2617{
2618 int status = 0;
e97249dd
IM		 2619 unsigned int sample_rate;
2620 unsigned short channels;
01ef7dbf 2621
4e76a883 2622 codec_dbg(codec, "---- dspload_image begin ------\n");
01ef7dbf
IM		 2623 if (router_chans == 0) {
2624 if (!ovly)
2625 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2626 else
2627 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2628 }
95c6e9cb 2629
e97249dd
IM		 2630 sample_rate = 48000;
2631 channels = (unsigned short)router_chans;
01ef7dbf 2632
e97249dd
IM		 2633 while (channels > 16) {
2634 sample_rate *= 2;
2635 channels /= 2;
01ef7dbf
IM		 2636 }
2637
01ef7dbf 2638 do {
4e76a883 2639 codec_dbg(codec, "Ready to program DMA\n");
01ef7dbf
IM		 2640 if (!ovly)
2641 status = dsp_reset(codec);
2642
2643 if (status < 0)
2644 break;
2645
4e76a883 2646 codec_dbg(codec, "dsp_reset() complete\n");
e97249dd
IM		 2647 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2648 ovly);
01ef7dbf
IM		 2649
2650 if (status < 0)
2651 break;
2652
4e76a883 2653 codec_dbg(codec, "dspxfr_image() complete\n");
01ef7dbf
IM		 2654 if (autostart && !ovly) {
2655 dspload_post_setup(codec);
2656 status = dsp_set_run_state(codec);
2657 }
2658
4e76a883 2659 codec_dbg(codec, "LOAD FINISHED\n");
01ef7dbf
IM		 2660 } while (0);
2661
2662 return status;
2663}
2664
f664417e 2665#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
01ef7dbf
IM		 2666static bool dspload_is_loaded(struct hda_codec *codec)
2667{
2668 unsigned int data = 0;
2669 int status = 0;
2670
2671 status = chipio_read(codec, 0x40004, &data);
2672 if ((status < 0) || (data != 1))
2673 return false;
2674
2675 return true;
2676}
f664417e
TI		 2677#else
2678#define dspload_is_loaded(codec) false
2679#endif
01ef7dbf
IM		 2680
2681static bool dspload_wait_loaded(struct hda_codec *codec)
2682{
6d67530e 2683 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
01ef7dbf
IM		 2684
2685 do {
01ef7dbf 2686 if (dspload_is_loaded(codec)) {
d9684bb5 2687 codec_info(codec, "ca0132 DSP downloaded and running\n");
01ef7dbf
IM		 2688 return true;
2689 }
6d67530e
IM		 2690 msleep(20);
2691 } while (time_before(jiffies, timeout));
01ef7dbf 2692
d9684bb5 2693 codec_err(codec, "ca0132 failed to download DSP\n");
01ef7dbf 2694 return false;
95c6e9cb
IM		 2695}
2696
825315bc
IM		 2697/*
2698 * PCM callbacks
2699 */
95c6e9cb
IM		 2700static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2701 struct hda_codec *codec,
2702 unsigned int stream_tag,
2703 unsigned int format,
2704 struct snd_pcm_substream *substream)
2705{
2706 struct ca0132_spec *spec = codec->spec;
825315bc 2707
28fba950 2708 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
825315bc
IM		 2709
2710 return 0;
95c6e9cb
IM		 2711}
2712
2713static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2714 struct hda_codec *codec,
2715 struct snd_pcm_substream *substream)
2716{
2717 struct ca0132_spec *spec = codec->spec;
825315bc
IM		 2718
2719 if (spec->dsp_state == DSP_DOWNLOADING)
2720 return 0;
2721
2722 /*If Playback effects are on, allow stream some time to flush
2723 *effects tail*/
2724 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2725 msleep(50);
2726
28fba950 2727 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
825315bc
IM		 2728
2729 return 0;
95c6e9cb
IM		 2730}
2731
e8412ca4
DR		 2732static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2733 struct hda_codec *codec,
2734 struct snd_pcm_substream *substream)
2735{
2736 struct ca0132_spec *spec = codec->spec;
2737 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2738 struct snd_pcm_runtime *runtime = substream->runtime;
2739
2740 if (spec->dsp_state != DSP_DOWNLOADED)
2741 return 0;
2742
2743 /* Add latency if playback enhancement and either effect is enabled. */
2744 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2745 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2746 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2747 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2748 }
2749
2750 /* Applying Speaker EQ adds latency as well. */
2751 if (spec->cur_out_type == SPEAKER_OUT)
2752 latency += DSP_SPEAKER_OUT_LATENCY;
2753
2754 return (latency * runtime->rate) / 1000;
2755}
2756
95c6e9cb
IM		 2757/*
2758 * Digital out
2759 */
27ebeb0b
TI		 2760static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2761 struct hda_codec *codec,
2762 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2763{
2764 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2765 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
95c6e9cb
IM		 2766}
2767
27ebeb0b 2768static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
95c6e9cb
IM		 2769 struct hda_codec *codec,
2770 unsigned int stream_tag,
2771 unsigned int format,
2772 struct snd_pcm_substream *substream)
2773{
2774 struct ca0132_spec *spec = codec->spec;
27ebeb0b
TI		 2775 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2776 stream_tag, format, substream);
95c6e9cb
IM		 2777}
2778
27ebeb0b 2779static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
95c6e9cb 2780 struct hda_codec *codec,
95c6e9cb
IM		 2781 struct snd_pcm_substream *substream)
2782{
2783 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2784 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
95c6e9cb
IM		 2785}
2786
27ebeb0b
TI		 2787static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2788 struct hda_codec *codec,
2789 struct snd_pcm_substream *substream)
95c6e9cb
IM		 2790{
2791 struct ca0132_spec *spec = codec->spec;
27ebeb0b 2792 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
95c6e9cb
IM		 2793}
2794
825315bc
IM		 2795/*
2796 * Analog capture
2797 */
2798static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2799 struct hda_codec *codec,
2800 unsigned int stream_tag,
2801 unsigned int format,
2802 struct snd_pcm_substream *substream)
2803{
13c12dbe 2804 snd_hda_codec_setup_stream(codec, hinfo->nid,
28fba950 2805 stream_tag, 0, format);
825315bc
IM		 2806
2807 return 0;
2808}
2809
2810static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2811 struct hda_codec *codec,
2812 struct snd_pcm_substream *substream)
2813{
2814 struct ca0132_spec *spec = codec->spec;
2815
2816 if (spec->dsp_state == DSP_DOWNLOADING)
2817 return 0;
2818
28fba950 2819 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
825315bc
IM		 2820 return 0;
2821}
2822
e8412ca4
DR		 2823static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2824 struct hda_codec *codec,
2825 struct snd_pcm_substream *substream)
2826{
2827 struct ca0132_spec *spec = codec->spec;
2828 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2829 struct snd_pcm_runtime *runtime = substream->runtime;
2830
2831 if (spec->dsp_state != DSP_DOWNLOADED)
2832 return 0;
2833
2834 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2835 latency += DSP_CRYSTAL_VOICE_LATENCY;
2836
2837 return (latency * runtime->rate) / 1000;
2838}
2839
e90f29e4
IM		 2840/*
2841 * Controls stuffs.
2842 */
2843
2844/*
2845 * Mixer controls helpers.
2846 */
2847#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2848 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2849 .name = xname, \
2850 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2851 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2852 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2853 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2854 .info = ca0132_volume_info, \
2855 .get = ca0132_volume_get, \
2856 .put = ca0132_volume_put, \
2857 .tlv = { .c = ca0132_volume_tlv }, \
2858 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2859
2860#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2861 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2862 .name = xname, \
2863 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2864 .info = snd_hda_mixer_amp_switch_info, \
2865 .get = ca0132_switch_get, \
2866 .put = ca0132_switch_put, \
2867 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2868
2869/* stereo */
2870#define CA0132_CODEC_VOL(xname, nid, dir) \
2871 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2872#define CA0132_CODEC_MUTE(xname, nid, dir) \
2873 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2874
4091fb95 2875/* The following are for tuning of products */
44f0c978
IM		 2876#ifdef ENABLE_TUNING_CONTROLS
2877
2878static unsigned int voice_focus_vals_lookup[] = {
28790x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
28800x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
28810x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
28820x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
28830x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
28840x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
28850x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
28860x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
28870x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
28880x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
28890x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
28900x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
28910x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
28920x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
28930x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
28940x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
28950x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
28960x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
28970x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
28980x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
28990x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
29000x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
29010x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
29020x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
29030x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
29040x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
29050x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2906};
2907
2908static unsigned int mic_svm_vals_lookup[] = {
29090x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
29100x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
29110x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
29120x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
29130x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
29140x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
29150x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
29160x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
29170x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
29180x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
29190x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
29200x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
29210x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
29220x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
29230x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
29240x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
29250x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2926};
2927
2928static unsigned int equalizer_vals_lookup[] = {
29290xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
29300xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
29310xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
29320xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
29330x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
29340x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
29350x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
29360x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
29370x41C00000
2938};
2939
2940static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2941 unsigned int *lookup, int idx)
2942{
2943 int i = 0;
2944
2945 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2946 if (nid == ca0132_tuning_ctls[i].nid)
2947 break;
2948
2949 snd_hda_power_up(codec);
2950 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2951 ca0132_tuning_ctls[i].req,
2952 &(lookup[idx]), sizeof(unsigned int));
2953 snd_hda_power_down(codec);
2954
2955 return 1;
2956}
2957
2958static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2959 struct snd_ctl_elem_value *ucontrol)
2960{
2961 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2962 struct ca0132_spec *spec = codec->spec;
2963 hda_nid_t nid = get_amp_nid(kcontrol);
2964 long *valp = ucontrol->value.integer.value;
2965 int idx = nid - TUNING_CTL_START_NID;
2966
2967 *valp = spec->cur_ctl_vals[idx];
2968 return 0;
2969}
2970
2971static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2972 struct snd_ctl_elem_info *uinfo)
2973{
2974 int chs = get_amp_channels(kcontrol);
2975 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2976 uinfo->count = chs == 3 ? 2 : 1;
2977 uinfo->value.integer.min = 20;
2978 uinfo->value.integer.max = 180;
2979 uinfo->value.integer.step = 1;
2980
2981 return 0;
2982}
2983
2984static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2985 struct snd_ctl_elem_value *ucontrol)
2986{
2987 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2988 struct ca0132_spec *spec = codec->spec;
2989 hda_nid_t nid = get_amp_nid(kcontrol);
2990 long *valp = ucontrol->value.integer.value;
2991 int idx;
2992
2993 idx = nid - TUNING_CTL_START_NID;
2994 /* any change? */
2995 if (spec->cur_ctl_vals[idx] == *valp)
2996 return 0;
2997
2998 spec->cur_ctl_vals[idx] = *valp;
2999
3000 idx = *valp - 20;
3001 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3002
3003 return 1;
3004}
3005
3006static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3007 struct snd_ctl_elem_info *uinfo)
3008{
3009 int chs = get_amp_channels(kcontrol);
3010 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3011 uinfo->count = chs == 3 ? 2 : 1;
3012 uinfo->value.integer.min = 0;
3013 uinfo->value.integer.max = 100;
3014 uinfo->value.integer.step = 1;
3015
3016 return 0;
3017}
3018
3019static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3020 struct snd_ctl_elem_value *ucontrol)
3021{
3022 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3023 struct ca0132_spec *spec = codec->spec;
3024 hda_nid_t nid = get_amp_nid(kcontrol);
3025 long *valp = ucontrol->value.integer.value;
3026 int idx;
3027
3028 idx = nid - TUNING_CTL_START_NID;
3029 /* any change? */
3030 if (spec->cur_ctl_vals[idx] == *valp)
3031 return 0;
3032
3033 spec->cur_ctl_vals[idx] = *valp;
3034
3035 idx = *valp;
3036 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3037
3038 return 0;
3039}
3040
3041static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3042 struct snd_ctl_elem_info *uinfo)
3043{
3044 int chs = get_amp_channels(kcontrol);
3045 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3046 uinfo->count = chs == 3 ? 2 : 1;
3047 uinfo->value.integer.min = 0;
3048 uinfo->value.integer.max = 48;
3049 uinfo->value.integer.step = 1;
3050
3051 return 0;
3052}
3053
3054static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3055 struct snd_ctl_elem_value *ucontrol)
3056{
3057 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3058 struct ca0132_spec *spec = codec->spec;
3059 hda_nid_t nid = get_amp_nid(kcontrol);
3060 long *valp = ucontrol->value.integer.value;
3061 int idx;
3062
3063 idx = nid - TUNING_CTL_START_NID;
3064 /* any change? */
3065 if (spec->cur_ctl_vals[idx] == *valp)
3066 return 0;
3067
3068 spec->cur_ctl_vals[idx] = *valp;
3069
3070 idx = *valp;
3071 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3072
3073 return 1;
3074}
3075
4a404cbb
TS		 3076static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3077static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
44f0c978
IM		 3078
3079static int add_tuning_control(struct hda_codec *codec,
3080 hda_nid_t pnid, hda_nid_t nid,
3081 const char *name, int dir)
3082{
975cc02a 3083 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
44f0c978
IM		 3084 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3085 struct snd_kcontrol_new knew =
3086 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3087
3088 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3089 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3090 knew.tlv.c = 0;
3091 knew.tlv.p = 0;
3092 switch (pnid) {
3093 case VOICE_FOCUS:
3094 knew.info = voice_focus_ctl_info;
3095 knew.get = tuning_ctl_get;
3096 knew.put = voice_focus_ctl_put;
3097 knew.tlv.p = voice_focus_db_scale;
3098 break;
3099 case MIC_SVM:
3100 knew.info = mic_svm_ctl_info;
3101 knew.get = tuning_ctl_get;
3102 knew.put = mic_svm_ctl_put;
3103 break;
3104 case EQUALIZER:
3105 knew.info = equalizer_ctl_info;
3106 knew.get = tuning_ctl_get;
3107 knew.put = equalizer_ctl_put;
3108 knew.tlv.p = eq_db_scale;
3109 break;
3110 default:
3111 return 0;
3112 }
3113 knew.private_value =
3114 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3115 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3116 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3117}
3118
3119static int add_tuning_ctls(struct hda_codec *codec)
3120{
3121 int i;
3122 int err;
3123
3124 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3125 err = add_tuning_control(codec,
3126 ca0132_tuning_ctls[i].parent_nid,
3127 ca0132_tuning_ctls[i].nid,
3128 ca0132_tuning_ctls[i].name,
3129 ca0132_tuning_ctls[i].direct);
3130 if (err < 0)
3131 return err;
3132 }
3133
3134 return 0;
3135}
3136
3137static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3138{
3139 struct ca0132_spec *spec = codec->spec;
3140 int i;
3141
3142 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3143 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3144 /* SVM level defaults to 0.74. */
3145 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3146
3147 /* EQ defaults to 0dB. */
3148 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3149 spec->cur_ctl_vals[i] = 24;
3150}
3151#endif /*ENABLE_TUNING_CONTROLS*/
3152
5aaca44d
IM		 3153/*
3154 * Select the active output.
3155 * If autodetect is enabled, output will be selected based on jack detection.
3156 * If jack inserted, headphone will be selected, else built-in speakers
3157 * If autodetect is disabled, output will be selected based on selection.
3158 */
3159static int ca0132_select_out(struct hda_codec *codec)
3160{
3161 struct ca0132_spec *spec = codec->spec;
3162 unsigned int pin_ctl;
3163 int jack_present;
3164 int auto_jack;
3165 unsigned int tmp;
3166 int err;
3167
4e76a883 3168 codec_dbg(codec, "ca0132_select_out\n");
5aaca44d 3169
664c7155 3170 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3171
3172 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3173
3174 if (auto_jack)
fe14f39e 3175 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
5aaca44d
IM		 3176 else
3177 jack_present =
3178 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3179
3180 if (jack_present)
3181 spec->cur_out_type = HEADPHONE_OUT;
3182 else
3183 spec->cur_out_type = SPEAKER_OUT;
3184
3185 if (spec->cur_out_type == SPEAKER_OUT) {
4e76a883 3186 codec_dbg(codec, "ca0132_select_out speaker\n");
5aaca44d
IM		 3187 /*speaker out config*/
3188 tmp = FLOAT_ONE;
3189 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3190 if (err < 0)
3191 goto exit;
3192 /*enable speaker EQ*/
3193 tmp = FLOAT_ONE;
3194 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3195 if (err < 0)
3196 goto exit;
3197
3198 /* Setup EAPD */
3199 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3200 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3201 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3202 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3203 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3204 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3205 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3206 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3207
3208 /* disable headphone node */
3209 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3210 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3211 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3212 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3213 /* enable speaker node */
3214 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3215 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3216 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3217 pin_ctl | PIN_OUT);
5aaca44d 3218 } else {
4e76a883 3219 codec_dbg(codec, "ca0132_select_out hp\n");
5aaca44d
IM		 3220 /*headphone out config*/
3221 tmp = FLOAT_ZERO;
3222 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3223 if (err < 0)
3224 goto exit;
3225 /*disable speaker EQ*/
3226 tmp = FLOAT_ZERO;
3227 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3228 if (err < 0)
3229 goto exit;
3230
3231 /* Setup EAPD */
3232 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3233 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3234 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3235 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3236 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3237 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3238 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3239 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3240
3241 /* disable speaker*/
3242 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3243 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3244 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3245 pin_ctl & ~PIN_HP);
5aaca44d
IM		 3246 /* enable headphone*/
3247 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3248 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
a0c041cb
TI		 3249 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3250 pin_ctl | PIN_HP);
5aaca44d
IM		 3251 }
3252
3253exit:
664c7155 3254 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3255
3256 return err < 0 ? err : 0;
3257}
3258
993884f6
CCC		 3259static void ca0132_unsol_hp_delayed(struct work_struct *work)
3260{
3261 struct ca0132_spec *spec = container_of(
3262 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
f8fb1170
TI		 3263 struct hda_jack_tbl *jack;
3264
993884f6 3265 ca0132_select_out(spec->codec);
d5c016b5 3266 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
f8fb1170
TI		 3267 if (jack) {
3268 jack->block_report = 0;
3269 snd_hda_jack_report_sync(spec->codec);
3270 }
993884f6
CCC		 3271}
3272
5aaca44d
IM		 3273static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3274static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3275static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3276
3277/*
3278 * Select the active VIP source
3279 */
3280static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3281{
3282 struct ca0132_spec *spec = codec->spec;
3283 unsigned int tmp;
3284
e8f1bd5d 3285 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 3286 return 0;
3287
3288 /* if CrystalVoice if off, vipsource should be 0 */
3289 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3290 (val == 0)) {
3291 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3292 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3293 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3294 if (spec->cur_mic_type == DIGITAL_MIC)
3295 tmp = FLOAT_TWO;
3296 else
3297 tmp = FLOAT_ONE;
3298 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3299 tmp = FLOAT_ZERO;
3300 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3301 } else {
3302 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3303 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3304 if (spec->cur_mic_type == DIGITAL_MIC)
3305 tmp = FLOAT_TWO;
3306 else
3307 tmp = FLOAT_ONE;
3308 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3309 tmp = FLOAT_ONE;
3310 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3311 msleep(20);
3312 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3313 }
3314
3315 return 1;
3316}
3317
3318/*
3319 * Select the active microphone.
3320 * If autodetect is enabled, mic will be selected based on jack detection.
3321 * If jack inserted, ext.mic will be selected, else built-in mic
3322 * If autodetect is disabled, mic will be selected based on selection.
3323 */
3324static int ca0132_select_mic(struct hda_codec *codec)
3325{
3326 struct ca0132_spec *spec = codec->spec;
3327 int jack_present;
3328 int auto_jack;
3329
4e76a883 3330 codec_dbg(codec, "ca0132_select_mic\n");
5aaca44d 3331
664c7155 3332 snd_hda_power_up_pm(codec);
5aaca44d
IM		 3333
3334 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3335
3336 if (auto_jack)
fe14f39e 3337 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5aaca44d
IM		 3338 else
3339 jack_present =
3340 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3341
3342 if (jack_present)
3343 spec->cur_mic_type = LINE_MIC_IN;
3344 else
3345 spec->cur_mic_type = DIGITAL_MIC;
3346
3347 if (spec->cur_mic_type == DIGITAL_MIC) {
3348 /* enable digital Mic */
3349 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3350 ca0132_set_dmic(codec, 1);
3351 ca0132_mic_boost_set(codec, 0);
3352 /* set voice focus */
3353 ca0132_effects_set(codec, VOICE_FOCUS,
3354 spec->effects_switch
3355 [VOICE_FOCUS - EFFECT_START_NID]);
3356 } else {
3357 /* disable digital Mic */
3358 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3359 ca0132_set_dmic(codec, 0);
3360 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3361 /* disable voice focus */
3362 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3363 }
3364
664c7155 3365 snd_hda_power_down_pm(codec);
5aaca44d
IM		 3366
3367 return 0;
3368}
3369
a7e76271
IM		 3370/*
3371 * Check if VNODE settings take effect immediately.
3372 */
3373static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3374 hda_nid_t vnid,
3375 hda_nid_t *shared_nid)
3376{
3377 struct ca0132_spec *spec = codec->spec;
3378 hda_nid_t nid;
a7e76271
IM		 3379
3380 switch (vnid) {
3381 case VNID_SPK:
3382 nid = spec->shared_out_nid;
a7e76271
IM		 3383 break;
3384 case VNID_MIC:
3385 nid = spec->shared_mic_nid;
a7e76271
IM		 3386 break;
3387 default:
9a0869f4 3388 return false;
a7e76271
IM		 3389 }
3390
9a0869f4 3391 if (shared_nid)
a7e76271
IM		 3392 *shared_nid = nid;
3393
9a0869f4 3394 return true;
a7e76271
IM		 3395}
3396
3397/*
3398* The following functions are control change helpers.
3399* They return 0 if no changed. Return 1 if changed.
3400*/
3401static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3402{
3403 struct ca0132_spec *spec = codec->spec;
3404 unsigned int tmp;
3405
3406 /* based on CrystalVoice state to enable VoiceFX. */
3407 if (enable) {
3408 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3409 FLOAT_ONE : FLOAT_ZERO;
3410 } else {
3411 tmp = FLOAT_ZERO;
3412 }
3413
3414 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3415 ca0132_voicefx.reqs[0], tmp);
3416
3417 return 1;
3418}
3419
5aaca44d
IM		 3420/*
3421 * Set the effects parameters
3422 */
3423static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3424{
3425 struct ca0132_spec *spec = codec->spec;
3426 unsigned int on;
3427 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3428 int err = 0;
3429 int idx = nid - EFFECT_START_NID;
3430
3431 if ((idx < 0) || (idx >= num_fx))
3432 return 0; /* no changed */
3433
3434 /* for out effect, qualify with PE */
3435 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3436 /* if PE if off, turn off out effects. */
3437 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3438 val = 0;
3439 }
3440
3441 /* for in effect, qualify with CrystalVoice */
3442 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3443 /* if CrystalVoice if off, turn off in effects. */
3444 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3445 val = 0;
3446
3447 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3448 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3449 val = 0;
3450 }
3451
4e76a883 3452 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5aaca44d
IM		 3453 nid, val);
3454
3455 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3456 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3457 ca0132_effects[idx].reqs[0], on);
3458
3459 if (err < 0)
3460 return 0; /* no changed */
3461
3462 return 1;
3463}
3464
a7e76271
IM		 3465/*
3466 * Turn on/off Playback Enhancements
3467 */
3468static int ca0132_pe_switch_set(struct hda_codec *codec)
3469{
3470 struct ca0132_spec *spec = codec->spec;
3471 hda_nid_t nid;
3472 int i, ret = 0;
3473
4e76a883 3474 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
a7e76271
IM		 3475 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3476
3477 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3478 nid = OUT_EFFECT_START_NID;
3479 /* PE affects all out effects */
3480 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3481 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3482
3483 return ret;
3484}
3485
5aaca44d
IM		 3486/* Check if Mic1 is streaming, if so, stop streaming */
3487static int stop_mic1(struct hda_codec *codec)
3488{
3489 struct ca0132_spec *spec = codec->spec;
3490 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3491 AC_VERB_GET_CONV, 0);
3492 if (oldval != 0)
3493 snd_hda_codec_write(codec, spec->adcs[0], 0,
3494 AC_VERB_SET_CHANNEL_STREAMID,
3495 0);
3496 return oldval;
3497}
3498
3499/* Resume Mic1 streaming if it was stopped. */
3500static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3501{
3502 struct ca0132_spec *spec = codec->spec;
3503 /* Restore the previous stream and channel */
3504 if (oldval != 0)
3505 snd_hda_codec_write(codec, spec->adcs[0], 0,
3506 AC_VERB_SET_CHANNEL_STREAMID,
3507 oldval);
3508}
3509
3510/*
a7e76271 3511 * Turn on/off CrystalVoice
5aaca44d 3512 */
a7e76271
IM		 3513static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3514{
3515 struct ca0132_spec *spec = codec->spec;
3516 hda_nid_t nid;
3517 int i, ret = 0;
3518 unsigned int oldval;
3519
4e76a883 3520 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
a7e76271
IM		 3521 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3522
3523 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3524 nid = IN_EFFECT_START_NID;
3525 /* CrystalVoice affects all in effects */
3526 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3527 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3528
3529 /* including VoiceFX */
3530 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3531
3532 /* set correct vipsource */
3533 oldval = stop_mic1(codec);
3534 ret |= ca0132_set_vipsource(codec, 1);
3535 resume_mic1(codec, oldval);
3536 return ret;
3537}
3538
5aaca44d
IM		 3539static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3540{
3541 struct ca0132_spec *spec = codec->spec;
3542 int ret = 0;
3543
3544 if (val) /* on */
3545 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3546 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3547 else /* off */
3548 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3549 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3550
3551 return ret;
3552}
3553
a7e76271
IM		 3554static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3555 struct snd_ctl_elem_value *ucontrol)
95c6e9cb 3556{
a7e76271
IM		 3557 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3558 hda_nid_t nid = get_amp_nid(kcontrol);
3559 hda_nid_t shared_nid = 0;
3560 bool effective;
3561 int ret = 0;
95c6e9cb 3562 struct ca0132_spec *spec = codec->spec;
a7e76271 3563 int auto_jack;
95c6e9cb 3564
a7e76271
IM		 3565 if (nid == VNID_HP_SEL) {
3566 auto_jack =
3567 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3568 if (!auto_jack)
3569 ca0132_select_out(codec);
3570 return 1;
3571 }
95c6e9cb 3572
a7e76271
IM		 3573 if (nid == VNID_AMIC1_SEL) {
3574 auto_jack =
3575 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3576 if (!auto_jack)
3577 ca0132_select_mic(codec);
3578 return 1;
3579 }
95c6e9cb 3580
a7e76271
IM		 3581 if (nid == VNID_HP_ASEL) {
3582 ca0132_select_out(codec);
3583 return 1;
3584 }
95c6e9cb 3585
a7e76271
IM		 3586 if (nid == VNID_AMIC1_ASEL) {
3587 ca0132_select_mic(codec);
3588 return 1;
95c6e9cb 3589 }
a7e76271
IM		 3590
3591 /* if effective conditions, then update hw immediately. */
3592 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3593 if (effective) {
3594 int dir = get_amp_direction(kcontrol);
3595 int ch = get_amp_channels(kcontrol);
3596 unsigned long pval;
3597
3598 mutex_lock(&codec->control_mutex);
3599 pval = kcontrol->private_value;
3600 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3601 0, dir);
3602 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3603 kcontrol->private_value = pval;
3604 mutex_unlock(&codec->control_mutex);
95c6e9cb 3605 }
95c6e9cb 3606
a7e76271 3607 return ret;
95c6e9cb 3608}
a7e76271 3609/* End of control change helpers. */
95c6e9cb 3610
a7e76271
IM		 3611static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3612 struct snd_ctl_elem_info *uinfo)
3613{
a9291f46 3614 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
a7e76271
IM		 3615
3616 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3617 uinfo->count = 1;
3618 uinfo->value.enumerated.items = items;
3619 if (uinfo->value.enumerated.item >= items)
3620 uinfo->value.enumerated.item = items - 1;
3621 strcpy(uinfo->value.enumerated.name,
3622 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3623 return 0;
3624}
95c6e9cb 3625
a7e76271 3626static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3627 struct snd_ctl_elem_value *ucontrol)
3628{
3629 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3630 struct ca0132_spec *spec = codec->spec;
95c6e9cb 3631
a7e76271 3632 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
95c6e9cb
IM		 3633 return 0;
3634}
3635
a7e76271 3636static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3637 struct snd_ctl_elem_value *ucontrol)
3638{
3639 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3640 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3641 int i, err = 0;
3642 int sel = ucontrol->value.enumerated.item[0];
95c6e9cb 3643
a9291f46 3644 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
95c6e9cb
IM		 3645 return 0;
3646
4e76a883 3647 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
a7e76271 3648 sel, ca0132_voicefx_presets[sel].name);
95c6e9cb 3649
a7e76271
IM		 3650 /*
3651 * Idx 0 is default.
3652 * Default needs to qualify with CrystalVoice state.
3653 */
3654 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3655 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3656 ca0132_voicefx.reqs[i],
3657 ca0132_voicefx_presets[sel].vals[i]);
3658 if (err < 0)
3659 break;
3660 }
95c6e9cb 3661
a7e76271
IM		 3662 if (err >= 0) {
3663 spec->voicefx_val = sel;
3664 /* enable voice fx */
3665 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3666 }
95c6e9cb 3667
a7e76271 3668 return 1;
95c6e9cb
IM		 3669}
3670
a7e76271
IM		 3671static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3672 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3673{
3674 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3675 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3676 hda_nid_t nid = get_amp_nid(kcontrol);
3677 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3678 long *valp = ucontrol->value.integer.value;
3679
a7e76271
IM		 3680 /* vnode */
3681 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3682 if (ch & 1) {
3683 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3684 valp++;
3685 }
3686 if (ch & 2) {
3687 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3688 valp++;
3689 }
3690 return 0;
3691 }
3692
3693 /* effects, include PE and CrystalVoice */
3694 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3695 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3696 return 0;
3697 }
3698
3699 /* mic boost */
3700 if (nid == spec->input_pins[0]) {
3701 *valp = spec->cur_mic_boost;
3702 return 0;
3703 }
3704
95c6e9cb
IM		 3705 return 0;
3706}
3707
a7e76271
IM		 3708static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3709 struct snd_ctl_elem_value *ucontrol)
95c6e9cb
IM		 3710{
3711 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3712 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3713 hda_nid_t nid = get_amp_nid(kcontrol);
3714 int ch = get_amp_channels(kcontrol);
95c6e9cb 3715 long *valp = ucontrol->value.integer.value;
a7e76271 3716 int changed = 1;
95c6e9cb 3717
4e76a883 3718 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
a7e76271 3719 nid, *valp);
95c6e9cb
IM		 3720
3721 snd_hda_power_up(codec);
a7e76271
IM		 3722 /* vnode */
3723 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3724 if (ch & 1) {
3725 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3726 valp++;
3727 }
3728 if (ch & 2) {
3729 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3730 valp++;
3731 }
3732 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3733 goto exit;
3734 }
95c6e9cb 3735
a7e76271
IM		 3736 /* PE */
3737 if (nid == PLAY_ENHANCEMENT) {
3738 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3739 changed = ca0132_pe_switch_set(codec);
b97f6bfd 3740 goto exit;
a7e76271 3741 }
95c6e9cb 3742
a7e76271
IM		 3743 /* CrystalVoice */
3744 if (nid == CRYSTAL_VOICE) {
3745 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3746 changed = ca0132_cvoice_switch_set(codec);
b97f6bfd 3747 goto exit;
a7e76271 3748 }
95c6e9cb 3749
a7e76271
IM		 3750 /* out and in effects */
3751 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3752 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3753 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3754 changed = ca0132_effects_set(codec, nid, *valp);
3755 goto exit;
3756 }
3757
3758 /* mic boost */
3759 if (nid == spec->input_pins[0]) {
3760 spec->cur_mic_boost = *valp;
3761
3762 /* Mic boost does not apply to Digital Mic */
3763 if (spec->cur_mic_type != DIGITAL_MIC)
3764 changed = ca0132_mic_boost_set(codec, *valp);
3765 goto exit;
3766 }
95c6e9cb 3767
a7e76271 3768exit:
95c6e9cb 3769 snd_hda_power_down(codec);
a7e76271 3770 return changed;
95c6e9cb
IM		 3771}
3772
a7e76271
IM		 3773/*
3774 * Volume related
3775 */
3776static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3777 struct snd_ctl_elem_info *uinfo)
3778{
3779 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3780 struct ca0132_spec *spec = codec->spec;
3781 hda_nid_t nid = get_amp_nid(kcontrol);
3782 int ch = get_amp_channels(kcontrol);
3783 int dir = get_amp_direction(kcontrol);
3784 unsigned long pval;
3785 int err;
3786
3787 switch (nid) {
3788 case VNID_SPK:
3789 /* follow shared_out info */
3790 nid = spec->shared_out_nid;
3791 mutex_lock(&codec->control_mutex);
3792 pval = kcontrol->private_value;
3793 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3794 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3795 kcontrol->private_value = pval;
3796 mutex_unlock(&codec->control_mutex);
3797 break;
3798 case VNID_MIC:
3799 /* follow shared_mic info */
3800 nid = spec->shared_mic_nid;
3801 mutex_lock(&codec->control_mutex);
3802 pval = kcontrol->private_value;
3803 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3804 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3805 kcontrol->private_value = pval;
3806 mutex_unlock(&codec->control_mutex);
3807 break;
3808 default:
3809 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3810 }
3811 return err;
3812}
3813
3814static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3815 struct snd_ctl_elem_value *ucontrol)
3816{
3817 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3818 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3819 hda_nid_t nid = get_amp_nid(kcontrol);
3820 int ch = get_amp_channels(kcontrol);
95c6e9cb
IM		 3821 long *valp = ucontrol->value.integer.value;
3822
a7e76271
IM		 3823 /* store the left and right volume */
3824 if (ch & 1) {
3825 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3826 valp++;
3827 }
3828 if (ch & 2) {
3829 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3830 valp++;
3831 }
95c6e9cb
IM		 3832 return 0;
3833}
3834
a7e76271 3835static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
95c6e9cb
IM		 3836 struct snd_ctl_elem_value *ucontrol)
3837{
3838 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3839 struct ca0132_spec *spec = codec->spec;
a7e76271
IM		 3840 hda_nid_t nid = get_amp_nid(kcontrol);
3841 int ch = get_amp_channels(kcontrol);
95c6e9cb 3842 long *valp = ucontrol->value.integer.value;
a7e76271
IM		 3843 hda_nid_t shared_nid = 0;
3844 bool effective;
3845 int changed = 1;
3846
3847 /* store the left and right volume */
3848 if (ch & 1) {
3849 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3850 valp++;
3851 }
3852 if (ch & 2) {
3853 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3854 valp++;
3855 }
95c6e9cb 3856
a7e76271
IM		 3857 /* if effective conditions, then update hw immediately. */
3858 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3859 if (effective) {
3860 int dir = get_amp_direction(kcontrol);
3861 unsigned long pval;
3862
3863 snd_hda_power_up(codec);
3864 mutex_lock(&codec->control_mutex);
3865 pval = kcontrol->private_value;
3866 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3867 0, dir);
3868 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3869 kcontrol->private_value = pval;
3870 mutex_unlock(&codec->control_mutex);
3871 snd_hda_power_down(codec);
3872 }
95c6e9cb 3873
a7e76271 3874 return changed;
95c6e9cb
IM		 3875}
3876
a7e76271
IM		 3877static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3878 unsigned int size, unsigned int __user *tlv)
95c6e9cb 3879{
a7e76271
IM		 3880 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3881 struct ca0132_spec *spec = codec->spec;
3882 hda_nid_t nid = get_amp_nid(kcontrol);
3883 int ch = get_amp_channels(kcontrol);
3884 int dir = get_amp_direction(kcontrol);
3885 unsigned long pval;
3886 int err;
3887
3888 switch (nid) {
3889 case VNID_SPK:
3890 /* follow shared_out tlv */
3891 nid = spec->shared_out_nid;
3892 mutex_lock(&codec->control_mutex);
3893 pval = kcontrol->private_value;
3894 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3895 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3896 kcontrol->private_value = pval;
3897 mutex_unlock(&codec->control_mutex);
3898 break;
3899 case VNID_MIC:
3900 /* follow shared_mic tlv */
3901 nid = spec->shared_mic_nid;
3902 mutex_lock(&codec->control_mutex);
3903 pval = kcontrol->private_value;
3904 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3905 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3906 kcontrol->private_value = pval;
3907 mutex_unlock(&codec->control_mutex);
3908 break;
3909 default:
3910 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3911 }
3912 return err;
95c6e9cb
IM		 3913}
3914
a7e76271
IM		 3915static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3916 const char *pfx, int dir)
95c6e9cb 3917{
975cc02a 3918 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
a7e76271 3919 int type = dir ? HDA_INPUT : HDA_OUTPUT;
95c6e9cb 3920 struct snd_kcontrol_new knew =
a7e76271
IM		 3921 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3922 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
95c6e9cb
IM		 3923 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3924}
3925
a7e76271 3926static int add_voicefx(struct hda_codec *codec)
95c6e9cb
IM		 3927{
3928 struct snd_kcontrol_new knew =
a7e76271
IM		 3929 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3930 VOICEFX, 1, 0, HDA_INPUT);
3931 knew.info = ca0132_voicefx_info;
3932 knew.get = ca0132_voicefx_get;
3933 knew.put = ca0132_voicefx_put;
3934 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
95c6e9cb
IM		 3935}
3936
a7e76271
IM		 3937/*
3938 * When changing Node IDs for Mixer Controls below, make sure to update
3939 * Node IDs in ca0132_config() as well.
3940 */
3941static struct snd_kcontrol_new ca0132_mixer[] = {
3942 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3943 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3944 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3945 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3946 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3947 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3948 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3949 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3950 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3951 0x12, 1, HDA_INPUT),
3952 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3953 VNID_HP_SEL, 1, HDA_OUTPUT),
3954 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3955 VNID_AMIC1_SEL, 1, HDA_INPUT),
3956 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3957 VNID_HP_ASEL, 1, HDA_OUTPUT),
3958 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3959 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3960 { } /* end */
3961};
3962
e90f29e4
IM		 3963static int ca0132_build_controls(struct hda_codec *codec)
3964{
3965 struct ca0132_spec *spec = codec->spec;
3966 int i, num_fx;
3967 int err = 0;
3968
3969 /* Add Mixer controls */
3970 for (i = 0; i < spec->num_mixers; i++) {
3971 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3972 if (err < 0)
3973 return err;
3974 }
3975
3976 /* Add in and out effects controls.
3977 * VoiceFX, PE and CrystalVoice are added separately.
3978 */
3979 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3980 for (i = 0; i < num_fx; i++) {
3981 err = add_fx_switch(codec, ca0132_effects[i].nid,
3982 ca0132_effects[i].name,
3983 ca0132_effects[i].direct);
3984 if (err < 0)
3985 return err;
3986 }
3987
3988 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3989 if (err < 0)
3990 return err;
3991
3992 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3993 if (err < 0)
3994 return err;
3995
3996 add_voicefx(codec);
3997
3998#ifdef ENABLE_TUNING_CONTROLS
3999 add_tuning_ctls(codec);
4000#endif
4001
4002 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
4003 if (err < 0)
4004 return err;
4005
4006 if (spec->dig_out) {
4007 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
4008 spec->dig_out);
4009 if (err < 0)
4010 return err;
4011 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
4012 if (err < 0)
4013 return err;
4014 /* spec->multiout.share_spdif = 1; */
4015 }
4016
4017 if (spec->dig_in) {
4018 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
4019 if (err < 0)
4020 return err;
4021 }
4022 return 0;
4023}
4024
a7e76271 4025/*
e90f29e4 4026 * PCM
a7e76271 4027 */
071f1344 4028static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
a7e76271
IM		 4029 .substreams = 1,
4030 .channels_min = 2,
825315bc 4031 .channels_max = 6,
a7e76271 4032 .ops = {
a7e76271 4033 .prepare = ca0132_playback_pcm_prepare,
e8412ca4
DR		 4034 .cleanup = ca0132_playback_pcm_cleanup,
4035 .get_delay = ca0132_playback_pcm_delay,
a7e76271
IM		 4036 },
4037};
4038
071f1344 4039static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
a7e76271
IM		 4040 .substreams = 1,
4041 .channels_min = 2,
4042 .channels_max = 2,
825315bc
IM		 4043 .ops = {
4044 .prepare = ca0132_capture_pcm_prepare,
e8412ca4
DR		 4045 .cleanup = ca0132_capture_pcm_cleanup,
4046 .get_delay = ca0132_capture_pcm_delay,
825315bc 4047 },
a7e76271
IM		 4048};
4049
071f1344 4050static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
a7e76271
IM		 4051 .substreams = 1,
4052 .channels_min = 2,
4053 .channels_max = 2,
4054 .ops = {
4055 .open = ca0132_dig_playback_pcm_open,
4056 .close = ca0132_dig_playback_pcm_close,
4057 .prepare = ca0132_dig_playback_pcm_prepare,
4058 .cleanup = ca0132_dig_playback_pcm_cleanup
4059 },
4060};
4061
071f1344 4062static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
a7e76271
IM		 4063 .substreams = 1,
4064 .channels_min = 2,
4065 .channels_max = 2,
4066};
4067
4068static int ca0132_build_pcms(struct hda_codec *codec)
95c6e9cb
IM		 4069{
4070 struct ca0132_spec *spec = codec->spec;
bbbc7e85 4071 struct hda_pcm *info;
a7e76271 4072
bbbc7e85
TI		 4073 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
4074 if (!info)
4075 return -ENOMEM;
a7e76271
IM		 4076 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4077 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4078 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4079 spec->multiout.max_channels;
4080 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
825315bc 4081 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
a7e76271 4082 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
a7e76271 4083
bbbc7e85
TI		 4084 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
4085 if (!info)
4086 return -ENOMEM;
825315bc
IM		 4087 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4088 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4089 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
825315bc 4090
bbbc7e85
TI		 4091 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
4092 if (!info)
4093 return -ENOMEM;
825315bc
IM		 4094 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4095 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4096 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
825315bc 4097
a7e76271
IM		 4098 if (!spec->dig_out && !spec->dig_in)
4099 return 0;
4100
bbbc7e85
TI		 4101 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
4102 if (!info)
4103 return -ENOMEM;
a7e76271
IM		 4104 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4105 if (spec->dig_out) {
4106 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4107 ca0132_pcm_digital_playback;
4108 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4109 }
4110 if (spec->dig_in) {
4111 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4112 ca0132_pcm_digital_capture;
4113 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4114 }
95c6e9cb 4115
a7e76271 4116 return 0;
95c6e9cb
IM		 4117}
4118
441aa6a0
IM		 4119static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4120{
4121 if (pin) {
a0c041cb 4122 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
441aa6a0
IM		 4123 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4124 snd_hda_codec_write(codec, pin, 0,
4125 AC_VERB_SET_AMP_GAIN_MUTE,
4126 AMP_OUT_UNMUTE);
4127 }
4128 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4129 snd_hda_codec_write(codec, dac, 0,
4130 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4131}
4132
4133static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4134{
4135 if (pin) {
a0c041cb 4136 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
441aa6a0
IM		 4137 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4138 snd_hda_codec_write(codec, pin, 0,
4139 AC_VERB_SET_AMP_GAIN_MUTE,
4140 AMP_IN_UNMUTE(0));
4141 }
4142 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4143 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4144 AMP_IN_UNMUTE(0));
4145
4146 /* init to 0 dB and unmute. */
4147 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4148 HDA_AMP_VOLMASK, 0x5a);
4149 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4150 HDA_AMP_MUTE, 0);
4151 }
4152}
4153
5aaca44d
IM		 4154static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4155{
4156 unsigned int caps;
4157
4158 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4159 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4160 snd_hda_override_amp_caps(codec, nid, dir, caps);
4161}
4162
4163/*
4164 * Switch between Digital built-in mic and analog mic.
4165 */
4166static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4167{
4168 struct ca0132_spec *spec = codec->spec;
4169 unsigned int tmp;
4170 u8 val;
4171 unsigned int oldval;
4172
4e76a883 4173 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
5aaca44d
IM		 4174
4175 oldval = stop_mic1(codec);
4176 ca0132_set_vipsource(codec, 0);
4177 if (enable) {
4178 /* set DMic input as 2-ch */
4179 tmp = FLOAT_TWO;
4180 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4181
4182 val = spec->dmic_ctl;
4183 val |= 0x80;
4184 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4185 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4186
4187 if (!(spec->dmic_ctl & 0x20))
4188 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4189 } else {
4190 /* set AMic input as mono */
4191 tmp = FLOAT_ONE;
4192 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4193
4194 val = spec->dmic_ctl;
4195 /* clear bit7 and bit5 to disable dmic */
4196 val &= 0x5f;
4197 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4198 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4199
4200 if (!(spec->dmic_ctl & 0x20))
4201 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4202 }
4203 ca0132_set_vipsource(codec, 1);
4204 resume_mic1(codec, oldval);
4205}
4206
4207/*
4208 * Initialization for Digital Mic.
4209 */
4210static void ca0132_init_dmic(struct hda_codec *codec)
4211{
4212 struct ca0132_spec *spec = codec->spec;
4213 u8 val;
4214
4215 /* Setup Digital Mic here, but don't enable.
4216 * Enable based on jack detect.
4217 */
4218
4219 /* MCLK uses MPIO1, set to enable.
4220 * Bit 2-0: MPIO select
4221 * Bit 3: set to disable
4222 * Bit 7-4: reserved
4223 */
4224 val = 0x01;
4225 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4226 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4227
4228 /* Data1 uses MPIO3. Data2 not use
4229 * Bit 2-0: Data1 MPIO select
4230 * Bit 3: set disable Data1
4231 * Bit 6-4: Data2 MPIO select
4232 * Bit 7: set disable Data2
4233 */
4234 val = 0x83;
4235 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4236 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4237
4238 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4239 * Bit 3-0: Channel mask
4240 * Bit 4: set for 48KHz, clear for 32KHz
4241 * Bit 5: mode
4242 * Bit 6: set to select Data2, clear for Data1
4243 * Bit 7: set to enable DMic, clear for AMic
4244 */
4245 val = 0x23;
4246 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4247 spec->dmic_ctl = val;
4248 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4249 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4250}
4251
4252/*
4253 * Initialization for Analog Mic 2
4254 */
4255static void ca0132_init_analog_mic2(struct hda_codec *codec)
4256{
4257 struct ca0132_spec *spec = codec->spec;
4258
4259 mutex_lock(&spec->chipio_mutex);
4260 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4261 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4262 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4263 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4264 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4265 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4266 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4267 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4268 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4269 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4270 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4271 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4272 mutex_unlock(&spec->chipio_mutex);
4273}
4274
4275static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4276{
4277 struct ca0132_spec *spec = codec->spec;
4278 int i;
5aaca44d 4279
4e76a883 4280 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7639a06c 4281 snd_hda_codec_update_widgets(codec);
5aaca44d
IM		 4282
4283 for (i = 0; i < spec->multiout.num_dacs; i++)
4284 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4285
4286 for (i = 0; i < spec->num_outputs; i++)
4287 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4288
4289 for (i = 0; i < spec->num_inputs; i++) {
4290 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4291 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4292 }
4293}
4294
4295/*
4296 * Setup default parameters for DSP
4297 */
4298static void ca0132_setup_defaults(struct hda_codec *codec)
4299{
e8f1bd5d 4300 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4301 unsigned int tmp;
4302 int num_fx;
4303 int idx, i;
4304
e8f1bd5d 4305 if (spec->dsp_state != DSP_DOWNLOADED)
5aaca44d
IM		 4306 return;
4307
4308 /* out, in effects + voicefx */
4309 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4310 for (idx = 0; idx < num_fx; idx++) {
4311 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4312 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4313 ca0132_effects[idx].reqs[i],
4314 ca0132_effects[idx].def_vals[i]);
4315 }
4316 }
4317
4318 /*remove DSP headroom*/
4319 tmp = FLOAT_ZERO;
4320 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4321
4322 /*set speaker EQ bypass attenuation*/
4323 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4324
4325 /* set AMic1 and AMic2 as mono mic */
4326 tmp = FLOAT_ONE;
4327 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4328 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4329
4330 /* set AMic1 as CrystalVoice input */
4331 tmp = FLOAT_ONE;
4332 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4333
4334 /* set WUH source */
4335 tmp = FLOAT_TWO;
4336 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4337}
4338
4339/*
4340 * Initialization of flags in chip
4341 */
4342static void ca0132_init_flags(struct hda_codec *codec)
4343{
4344 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4345 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4346 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4347 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4348 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4349 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4350}
4351
4352/*
4353 * Initialization of parameters in chip
4354 */
4355static void ca0132_init_params(struct hda_codec *codec)
4356{
4357 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4358 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4359}
95c6e9cb 4360
e90f29e4
IM		 4361static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4362{
4363 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4364 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4365 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4366 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4367 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4368 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4369
406261ce
IM		 4370 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4371 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
e90f29e4
IM		 4372 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4373}
4374
4375static bool ca0132_download_dsp_images(struct hda_codec *codec)
4376{
4377 bool dsp_loaded = false;
4378 const struct dsp_image_seg *dsp_os_image;
15e4ba66 4379 const struct firmware *fw_entry;
e90f29e4 4380
6efdd851 4381 if (request_firmware(&fw_entry, EFX_FILE, codec->card->dev) != 0)
e90f29e4
IM		 4382 return false;
4383
15e4ba66 4384 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
d1d28500 4385 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
d9684bb5 4386 codec_err(codec, "ca0132 DSP load image failed\n");
d1d28500
DR		 4387 goto exit_download;
4388 }
4389
e90f29e4
IM		 4390 dsp_loaded = dspload_wait_loaded(codec);
4391
d1d28500 4392exit_download:
15e4ba66
TI		 4393 release_firmware(fw_entry);
4394
e90f29e4
IM		 4395 return dsp_loaded;
4396}
4397
4398static void ca0132_download_dsp(struct hda_codec *codec)
4399{
4400 struct ca0132_spec *spec = codec->spec;
4401
9a0869f4
TI		 4402#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4403 return; /* NOP */
4404#endif
e90f29e4 4405
e24aa0a4
TI		 4406 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
4407 return; /* don't retry failures */
4408
b714a710
DR		 4409 chipio_enable_clocks(codec);
4410 spec->dsp_state = DSP_DOWNLOADING;
4411 if (!ca0132_download_dsp_images(codec))
4412 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4413 else
4414 spec->dsp_state = DSP_DOWNLOADED;
e90f29e4
IM		 4415
4416 if (spec->dsp_state == DSP_DOWNLOADED)
4417 ca0132_set_dsp_msr(codec, true);
4418}
4419
f8fb1170
TI		 4420static void ca0132_process_dsp_response(struct hda_codec *codec,
4421 struct hda_jack_callback *callback)
e90f29e4
IM		 4422{
4423 struct ca0132_spec *spec = codec->spec;
4424
4e76a883 4425 codec_dbg(codec, "ca0132_process_dsp_response\n");
5b0e6f0f 4426 snd_hda_power_up_pm(codec);
e90f29e4
IM		 4427 if (spec->wait_scp) {
4428 if (dspio_get_response_data(codec) >= 0)
4429 spec->wait_scp = 0;
4430 }
4431
4432 dspio_clear_response_queue(codec);
5b0e6f0f 4433 snd_hda_power_down_pm(codec);
e90f29e4
IM		 4434}
4435
f8fb1170 4436static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
e90f29e4 4437{
993884f6 4438 struct ca0132_spec *spec = codec->spec;
2ebab40e 4439 struct hda_jack_tbl *tbl;
e90f29e4 4440
f8fb1170
TI		 4441 /* Delay enabling the HP amp, to let the mic-detection
4442 * state machine run.
4443 */
c36493f9 4444 cancel_delayed_work(&spec->unsol_hp_work);
2f35c630 4445 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
2ebab40e
TI		 4446 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
4447 if (tbl)
4448 tbl->block_report = 1;
f8fb1170
TI		 4449}
4450
4451static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4452{
4453 ca0132_select_mic(codec);
4454}
4455
4456static void ca0132_init_unsol(struct hda_codec *codec)
4457{
d5c016b5
GM		 4458 struct ca0132_spec *spec = codec->spec;
4459 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
4460 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
f8fb1170
TI		 4461 amic_callback);
4462 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
4463 ca0132_process_dsp_response);
e90f29e4
IM		 4464}
4465
5aaca44d
IM		 4466/*
4467 * Verbs tables.
4468 */
4469
4470/* Sends before DSP download. */
4471static struct hda_verb ca0132_base_init_verbs[] = {
4472 /*enable ct extension*/
4473 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
5aaca44d
IM		 4474 {}
4475};
4476
4477/* Send at exit. */
4478static struct hda_verb ca0132_base_exit_verbs[] = {
4479 /*set afg to D3*/
4480 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4481 /*disable ct extension*/
4482 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4483 {}
4484};
4485
4486/* Other verbs tables. Sends after DSP download. */
4487static struct hda_verb ca0132_init_verbs0[] = {
4488 /* chip init verbs */
4489 {0x15, 0x70D, 0xF0},
4490 {0x15, 0x70E, 0xFE},
4491 {0x15, 0x707, 0x75},
4492 {0x15, 0x707, 0xD3},
4493 {0x15, 0x707, 0x09},
4494 {0x15, 0x707, 0x53},
4495 {0x15, 0x707, 0xD4},
4496 {0x15, 0x707, 0xEF},
4497 {0x15, 0x707, 0x75},
4498 {0x15, 0x707, 0xD3},
4499 {0x15, 0x707, 0x09},
4500 {0x15, 0x707, 0x02},
4501 {0x15, 0x707, 0x37},
4502 {0x15, 0x707, 0x78},
4503 {0x15, 0x53C, 0xCE},
4504 {0x15, 0x575, 0xC9},
4505 {0x15, 0x53D, 0xCE},
4506 {0x15, 0x5B7, 0xC9},
4507 {0x15, 0x70D, 0xE8},
4508 {0x15, 0x70E, 0xFE},
4509 {0x15, 0x707, 0x02},
4510 {0x15, 0x707, 0x68},
4511 {0x15, 0x707, 0x62},
4512 {0x15, 0x53A, 0xCE},
4513 {0x15, 0x546, 0xC9},
4514 {0x15, 0x53B, 0xCE},
4515 {0x15, 0x5E8, 0xC9},
4516 {0x15, 0x717, 0x0D},
4517 {0x15, 0x718, 0x20},
4518 {}
4519};
4520
95c6e9cb
IM		 4521static void ca0132_init_chip(struct hda_codec *codec)
4522{
4523 struct ca0132_spec *spec = codec->spec;
5aaca44d
IM		 4524 int num_fx;
4525 int i;
4526 unsigned int on;
95c6e9cb
IM		 4527
4528 mutex_init(&spec->chipio_mutex);
5aaca44d
IM		 4529
4530 spec->cur_out_type = SPEAKER_OUT;
4531 spec->cur_mic_type = DIGITAL_MIC;
4532 spec->cur_mic_boost = 0;
4533
4534 for (i = 0; i < VNODES_COUNT; i++) {
4535 spec->vnode_lvol[i] = 0x5a;
4536 spec->vnode_rvol[i] = 0x5a;
4537 spec->vnode_lswitch[i] = 0;
4538 spec->vnode_rswitch[i] = 0;
4539 }
4540
4541 /*
4542 * Default states for effects are in ca0132_effects[].
4543 */
4544 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4545 for (i = 0; i < num_fx; i++) {
4546 on = (unsigned int)ca0132_effects[i].reqs[0];
4547 spec->effects_switch[i] = on ? 1 : 0;
4548 }
4549
4550 spec->voicefx_val = 0;
4551 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4552 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4553
44f0c978
IM		 4554#ifdef ENABLE_TUNING_CONTROLS
4555 ca0132_init_tuning_defaults(codec);
4556#endif
95c6e9cb
IM		 4557}
4558
4559static void ca0132_exit_chip(struct hda_codec *codec)
4560{
4561 /* put any chip cleanup stuffs here. */
5aaca44d
IM		 4562
4563 if (dspload_is_loaded(codec))
4564 dsp_reset(codec);
95c6e9cb
IM		 4565}
4566
4567static int ca0132_init(struct hda_codec *codec)
4568{
4569 struct ca0132_spec *spec = codec->spec;
4570 struct auto_pin_cfg *cfg = &spec->autocfg;
4571 int i;
4572
e24aa0a4
TI		 4573 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
4574 spec->dsp_state = DSP_DOWNLOAD_INIT;
4a8b89f9 4575 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
5aaca44d 4576
664c7155 4577 snd_hda_power_up_pm(codec);
5aaca44d 4578
f8fb1170
TI		 4579 ca0132_init_unsol(codec);
4580
5aaca44d
IM		 4581 ca0132_init_params(codec);
4582 ca0132_init_flags(codec);
4583 snd_hda_sequence_write(codec, spec->base_init_verbs);
01ef7dbf 4584 ca0132_download_dsp(codec);
5aaca44d
IM		 4585 ca0132_refresh_widget_caps(codec);
4586 ca0132_setup_defaults(codec);
4587 ca0132_init_analog_mic2(codec);
4588 ca0132_init_dmic(codec);
4589
4590 for (i = 0; i < spec->num_outputs; i++)
4591 init_output(codec, spec->out_pins[i], spec->dacs[0]);
01ef7dbf 4592
95c6e9cb
IM		 4593 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4594
4595 for (i = 0; i < spec->num_inputs; i++)
4596 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4597
4598 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4599
d5c016b5
GM		 4600 snd_hda_sequence_write(codec, spec->chip_init_verbs);
4601 snd_hda_sequence_write(codec, spec->spec_init_verbs);
5aaca44d
IM		 4602
4603 ca0132_select_out(codec);
4604 ca0132_select_mic(codec);
4605
a73d511c
IM		 4606 snd_hda_jack_report_sync(codec);
4607
664c7155 4608 snd_hda_power_down_pm(codec);
95c6e9cb
IM		 4609
4610 return 0;
4611}
4612
95c6e9cb
IM		 4613static void ca0132_free(struct hda_codec *codec)
4614{
5aaca44d
IM		 4615 struct ca0132_spec *spec = codec->spec;
4616
993884f6 4617 cancel_delayed_work_sync(&spec->unsol_hp_work);
5aaca44d
IM		 4618 snd_hda_power_up(codec);
4619 snd_hda_sequence_write(codec, spec->base_exit_verbs);
95c6e9cb 4620 ca0132_exit_chip(codec);
5aaca44d 4621 snd_hda_power_down(codec);
d5c016b5 4622 kfree(spec->spec_init_verbs);
95c6e9cb
IM		 4623 kfree(codec->spec);
4624}
4625
071f1344 4626static const struct hda_codec_ops ca0132_patch_ops = {
95c6e9cb
IM		 4627 .build_controls = ca0132_build_controls,
4628 .build_pcms = ca0132_build_pcms,
4629 .init = ca0132_init,
4630 .free = ca0132_free,
f8fb1170 4631 .unsol_event = snd_hda_jack_unsol_event,
95c6e9cb
IM		 4632};
4633
441aa6a0
IM		 4634static void ca0132_config(struct hda_codec *codec)
4635{
4636 struct ca0132_spec *spec = codec->spec;
4637 struct auto_pin_cfg *cfg = &spec->autocfg;
4638
4639 spec->dacs[0] = 0x2;
4640 spec->dacs[1] = 0x3;
4641 spec->dacs[2] = 0x4;
4642
4643 spec->multiout.dac_nids = spec->dacs;
4644 spec->multiout.num_dacs = 3;
4645 spec->multiout.max_channels = 2;
4646
d5c016b5
GM		 4647 if (spec->quirk == QUIRK_ALIENWARE) {
4648 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
fe14f39e
TI		 4649 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
4650
4651 spec->num_outputs = 2;
4652 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 4653 spec->out_pins[1] = 0x0f;
fe14f39e
TI		 4654 spec->shared_out_nid = 0x2;
4655 spec->unsol_tag_hp = 0x0f;
4656
4657 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4658 spec->adcs[1] = 0x8; /* analog mic2 */
4659 spec->adcs[2] = 0xa; /* what u hear */
4660
4661 spec->num_inputs = 3;
4662 spec->input_pins[0] = 0x12;
4663 spec->input_pins[1] = 0x11;
4664 spec->input_pins[2] = 0x13;
4665 spec->shared_mic_nid = 0x7;
4666 spec->unsol_tag_amic1 = 0x11;
4667 } else {
4668 spec->num_outputs = 2;
4669 spec->out_pins[0] = 0x0b; /* speaker out */
d5c016b5 4670 spec->out_pins[1] = 0x10; /* headphone out */
fe14f39e
TI		 4671 spec->shared_out_nid = 0x2;
4672 spec->unsol_tag_hp = spec->out_pins[1];
4673
4674 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4675 spec->adcs[1] = 0x8; /* analog mic2 */
4676 spec->adcs[2] = 0xa; /* what u hear */
4677
4678 spec->num_inputs = 3;
4679 spec->input_pins[0] = 0x12;
4680 spec->input_pins[1] = 0x11;
4681 spec->input_pins[2] = 0x13;
4682 spec->shared_mic_nid = 0x7;
4683 spec->unsol_tag_amic1 = spec->input_pins[0];
4684
4685 /* SPDIF I/O */
4686 spec->dig_out = 0x05;
4687 spec->multiout.dig_out_nid = spec->dig_out;
4688 cfg->dig_out_pins[0] = 0x0c;
4689 cfg->dig_outs = 1;
4690 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4691 spec->dig_in = 0x09;
4692 cfg->dig_in_pin = 0x0e;
4693 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
d5c016b5 4694 }
441aa6a0
IM		 4695}
4696
d5c016b5
GM		 4697static int ca0132_prepare_verbs(struct hda_codec *codec)
4698{
4699/* Verbs + terminator (an empty element) */
4700#define NUM_SPEC_VERBS 4
4701 struct ca0132_spec *spec = codec->spec;
4702
4703 spec->chip_init_verbs = ca0132_init_verbs0;
4704 spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL);
4705 if (!spec->spec_init_verbs)
4706 return -ENOMEM;
4707
4708 /* HP jack autodetection */
4709 spec->spec_init_verbs[0].nid = spec->unsol_tag_hp;
4710 spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4711 spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp;
4712
4713 /* MIC1 jack autodetection */
4714 spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1;
4715 spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4716 spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1;
4717
4718 /* config EAPD */
4719 spec->spec_init_verbs[2].nid = 0x0b;
4720 spec->spec_init_verbs[2].param = 0x78D;
4721 spec->spec_init_verbs[2].verb = 0x00;
4722
4723 /* Previously commented configuration */
4724 /*
4725 spec->spec_init_verbs[3].nid = 0x0b;
4726 spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE;
4727 spec->spec_init_verbs[3].verb = 0x02;
4728
4729 spec->spec_init_verbs[4].nid = 0x10;
4730 spec->spec_init_verbs[4].param = 0x78D;
4731 spec->spec_init_verbs[4].verb = 0x02;
4732
4733 spec->spec_init_verbs[5].nid = 0x10;
4734 spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE;
4735 spec->spec_init_verbs[5].verb = 0x02;
4736 */
4737
4738 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
4739 return 0;
4740}
4741
95c6e9cb
IM		 4742static int patch_ca0132(struct hda_codec *codec)
4743{
4744 struct ca0132_spec *spec;
a73d511c 4745 int err;
d5c016b5 4746 const struct snd_pci_quirk *quirk;
95c6e9cb 4747
4e76a883 4748 codec_dbg(codec, "patch_ca0132\n");
95c6e9cb
IM		 4749
4750 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4751 if (!spec)
4752 return -ENOMEM;
4753 codec->spec = spec;
993884f6 4754 spec->codec = codec;
95c6e9cb 4755
225068ab
TI		 4756 codec->patch_ops = ca0132_patch_ops;
4757 codec->pcm_format_first = 1;
4758 codec->no_sticky_stream = 1;
4759
d5c016b5
GM		 4760 /* Detect codec quirk */
4761 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
4762 if (quirk)
4763 spec->quirk = quirk->value;
4764 else
4765 spec->quirk = QUIRK_NONE;
4766
e24aa0a4 4767 spec->dsp_state = DSP_DOWNLOAD_INIT;
a7e76271
IM		 4768 spec->num_mixers = 1;
4769 spec->mixers[0] = ca0132_mixer;
4770
5aaca44d
IM		 4771 spec->base_init_verbs = ca0132_base_init_verbs;
4772 spec->base_exit_verbs = ca0132_base_exit_verbs;
5aaca44d 4773
993884f6
CCC		 4774 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4775
95c6e9cb
IM		 4776 ca0132_init_chip(codec);
4777
4778 ca0132_config(codec);
4779
d5c016b5
GM		 4780 err = ca0132_prepare_verbs(codec);
4781 if (err < 0)
cc91ceaf 4782 goto error;
d5c016b5 4783
a73d511c
IM		 4784 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4785 if (err < 0)
cc91ceaf 4786 goto error;
a73d511c 4787
95c6e9cb 4788 return 0;
cc91ceaf
TI		 4789
4790 error:
4791 ca0132_free(codec);
4792 return err;
95c6e9cb
IM		 4793}
4794
4795/*
4796 * patch entries
4797 */
b9a94a9c
TI		 4798static struct hda_device_id snd_hda_id_ca0132[] = {
4799 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
95c6e9cb
IM		 4800 {} /* terminator */
4801};
b9a94a9c 4802MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
95c6e9cb
IM		 4803
4804MODULE_LICENSE("GPL");
406261ce 4805MODULE_DESCRIPTION("Creative Sound Core3D codec");
95c6e9cb 4806
d8a766a1 4807static struct hda_codec_driver ca0132_driver = {
b9a94a9c 4808 .id = snd_hda_id_ca0132,
95c6e9cb
IM		 4809};
4810
d8a766a1 4811module_hda_codec_driver(ca0132_driver);
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