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Merge branch 'fixes' of git://git.alsa-project.org/alsa-kernel into for-next
[mirror_ubuntu-zesty-kernel.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
84eb01be
TI		 37#include "hda_codec.h"
38#include "hda_local.h"
1835a0f9 39#include "hda_jack.h"
84eb01be 40
0ebaa24c
TI		 41static bool static_hdmi_pcm;
42module_param(static_hdmi_pcm, bool, 0644);
43MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
44
84eb01be
TI		 45/*
46 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
384a48d7 47 * could support N independent pipes, each of them can be connected to one or
84eb01be
TI		 48 * more ports (DVI, HDMI or DisplayPort).
49 *
50 * The HDA correspondence of pipes/ports are converter/pin nodes.
51 */
a4567cb3
TI		 52#define MAX_HDMI_CVTS 8
53#define MAX_HDMI_PINS 8
079d88cc 54
384a48d7
SW		 55struct hdmi_spec_per_cvt {
56 hda_nid_t cvt_nid;
57 int assigned;
58 unsigned int channels_min;
59 unsigned int channels_max;
60 u32 rates;
61 u64 formats;
62 unsigned int maxbps;
63};
079d88cc 64
384a48d7
SW		 65struct hdmi_spec_per_pin {
66 hda_nid_t pin_nid;
67 int num_mux_nids;
68 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
744626da
WF		 69
70 struct hda_codec *codec;
384a48d7 71 struct hdmi_eld sink_eld;
744626da 72 struct delayed_work work;
c6e8453e 73 int repoll_count;
384a48d7 74};
079d88cc 75
384a48d7
SW		 76struct hdmi_spec {
77 int num_cvts;
78 struct hdmi_spec_per_cvt cvts[MAX_HDMI_CVTS];
079d88cc 79
384a48d7
SW		 80 int num_pins;
81 struct hdmi_spec_per_pin pins[MAX_HDMI_PINS];
82 struct hda_pcm pcm_rec[MAX_HDMI_PINS];
079d88cc
WF		 83
84 /*
384a48d7 85 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 86 */
87 struct hda_multi_out multiout;
d0b1252d 88 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 89};
90
91
92struct hdmi_audio_infoframe {
93 u8 type; /* 0x84 */
94 u8 ver; /* 0x01 */
95 u8 len; /* 0x0a */
96
53d7d69d
WF		 97 u8 checksum;
98
079d88cc
WF		 99 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
100 u8 SS01_SF24;
101 u8 CXT04;
102 u8 CA;
103 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 104};
105
106struct dp_audio_infoframe {
107 u8 type; /* 0x84 */
108 u8 len; /* 0x1b */
109 u8 ver; /* 0x11 << 2 */
110
111 u8 CC02_CT47; /* match with HDMI infoframe from this on */
112 u8 SS01_SF24;
113 u8 CXT04;
114 u8 CA;
115 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 116};
117
2b203dbb
TI		 118union audio_infoframe {
119 struct hdmi_audio_infoframe hdmi;
120 struct dp_audio_infoframe dp;
121 u8 bytes[0];
122};
123
079d88cc
WF		 124/*
125 * CEA speaker placement:
126 *
127 * FLH FCH FRH
128 * FLW FL FLC FC FRC FR FRW
129 *
130 * LFE
131 * TC
132 *
133 * RL RLC RC RRC RR
134 *
135 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
136 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
137 */
138enum cea_speaker_placement {
139 FL = (1 << 0), /* Front Left */
140 FC = (1 << 1), /* Front Center */
141 FR = (1 << 2), /* Front Right */
142 FLC = (1 << 3), /* Front Left Center */
143 FRC = (1 << 4), /* Front Right Center */
144 RL = (1 << 5), /* Rear Left */
145 RC = (1 << 6), /* Rear Center */
146 RR = (1 << 7), /* Rear Right */
147 RLC = (1 << 8), /* Rear Left Center */
148 RRC = (1 << 9), /* Rear Right Center */
149 LFE = (1 << 10), /* Low Frequency Effect */
150 FLW = (1 << 11), /* Front Left Wide */
151 FRW = (1 << 12), /* Front Right Wide */
152 FLH = (1 << 13), /* Front Left High */
153 FCH = (1 << 14), /* Front Center High */
154 FRH = (1 << 15), /* Front Right High */
155 TC = (1 << 16), /* Top Center */
156};
157
158/*
159 * ELD SA bits in the CEA Speaker Allocation data block
160 */
161static int eld_speaker_allocation_bits[] = {
162 [0] = FL | FR,
163 [1] = LFE,
164 [2] = FC,
165 [3] = RL | RR,
166 [4] = RC,
167 [5] = FLC | FRC,
168 [6] = RLC | RRC,
169 /* the following are not defined in ELD yet */
170 [7] = FLW | FRW,
171 [8] = FLH | FRH,
172 [9] = TC,
173 [10] = FCH,
174};
175
176struct cea_channel_speaker_allocation {
177 int ca_index;
178 int speakers[8];
179
180 /* derived values, just for convenience */
181 int channels;
182 int spk_mask;
183};
184
185/*
186 * ALSA sequence is:
187 *
188 * surround40 surround41 surround50 surround51 surround71
189 * ch0 front left = = = =
190 * ch1 front right = = = =
191 * ch2 rear left = = = =
192 * ch3 rear right = = = =
193 * ch4 LFE center center center
194 * ch5 LFE LFE
195 * ch6 side left
196 * ch7 side right
197 *
198 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
199 */
200static int hdmi_channel_mapping[0x32][8] = {
201 /* stereo */
202 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
203 /* 2.1 */
204 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
205 /* Dolby Surround */
206 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
207 /* surround40 */
208 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
209 /* 4ch */
210 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
211 /* surround41 */
9396d317 212 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 213 /* surround50 */
214 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
215 /* surround51 */
216 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
217 /* 7.1 */
218 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
219};
220
221/*
222 * This is an ordered list!
223 *
224 * The preceding ones have better chances to be selected by
53d7d69d 225 * hdmi_channel_allocation().
079d88cc
WF		 226 */
227static struct cea_channel_speaker_allocation channel_allocations[] = {
228/* channel: 7 6 5 4 3 2 1 0 */
229{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
230 /* 2.1 */
231{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
232 /* Dolby Surround */
233{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
234 /* surround40 */
235{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
236 /* surround41 */
237{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
238 /* surround50 */
239{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
240 /* surround51 */
241{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
242 /* 6.1 */
243{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
244 /* surround71 */
245{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
246
247{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
248{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
249{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
250{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
251{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
252{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
253{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
254{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
255{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
256{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
257{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
258{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
259{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
260{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
261{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
262{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
263{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
264{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
265{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
266{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
267{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
268{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
269{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
270{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
271{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
272{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
273{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
274{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
275{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
276{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
277{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
278{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
279{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
280{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
281{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
282{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
283{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
284{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
285{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
286{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
287{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
288};
289
290
291/*
292 * HDMI routines
293 */
294
384a48d7 295static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 296{
384a48d7 297 int pin_idx;
079d88cc 298
384a48d7
SW		 299 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
300 if (spec->pins[pin_idx].pin_nid == pin_nid)
301 return pin_idx;
079d88cc 302
384a48d7
SW		 303 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
304 return -EINVAL;
305}
306
307static int hinfo_to_pin_index(struct hdmi_spec *spec,
308 struct hda_pcm_stream *hinfo)
309{
310 int pin_idx;
311
312 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
313 if (&spec->pcm_rec[pin_idx].stream[0] == hinfo)
314 return pin_idx;
315
316 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
317 return -EINVAL;
318}
319
320static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
321{
322 int cvt_idx;
323
324 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
325 if (spec->cvts[cvt_idx].cvt_nid == cvt_nid)
326 return cvt_idx;
327
328 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 329 return -EINVAL;
330}
331
14bc52b8
PLB		 332static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
333 struct snd_ctl_elem_info *uinfo)
334{
335 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
336 struct hdmi_spec *spec;
337 int pin_idx;
338
339 spec = codec->spec;
340 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
341
342 pin_idx = kcontrol->private_value;
343 uinfo->count = spec->pins[pin_idx].sink_eld.eld_size;
344
345 return 0;
346}
347
348static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
349 struct snd_ctl_elem_value *ucontrol)
350{
351 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
352 struct hdmi_spec *spec;
353 int pin_idx;
354
355 spec = codec->spec;
356 pin_idx = kcontrol->private_value;
357
358 memcpy(ucontrol->value.bytes.data,
359 spec->pins[pin_idx].sink_eld.eld_buffer, ELD_MAX_SIZE);
360
361 return 0;
362}
363
364static struct snd_kcontrol_new eld_bytes_ctl = {
365 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
366 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
367 .name = "ELD",
368 .info = hdmi_eld_ctl_info,
369 .get = hdmi_eld_ctl_get,
370};
371
372static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
373 int device)
374{
375 struct snd_kcontrol *kctl;
376 struct hdmi_spec *spec = codec->spec;
377 int err;
378
379 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
380 if (!kctl)
381 return -ENOMEM;
382 kctl->private_value = pin_idx;
383 kctl->id.device = device;
384
385 err = snd_hda_ctl_add(codec, spec->pins[pin_idx].pin_nid, kctl);
386 if (err < 0)
387 return err;
388
389 return 0;
390}
391
079d88cc
WF		 392#ifdef BE_PARANOID
393static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
394 int *packet_index, int *byte_index)
395{
396 int val;
397
398 val = snd_hda_codec_read(codec, pin_nid, 0,
399 AC_VERB_GET_HDMI_DIP_INDEX, 0);
400
401 *packet_index = val >> 5;
402 *byte_index = val & 0x1f;
403}
404#endif
405
406static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
407 int packet_index, int byte_index)
408{
409 int val;
410
411 val = (packet_index << 5) | (byte_index & 0x1f);
412
413 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
414}
415
416static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
417 unsigned char val)
418{
419 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
420}
421
384a48d7 422static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 423{
424 /* Unmute */
425 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
426 snd_hda_codec_write(codec, pin_nid, 0,
427 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
384a48d7 428 /* Disable pin out until stream is active*/
079d88cc 429 snd_hda_codec_write(codec, pin_nid, 0,
384a48d7 430 AC_VERB_SET_PIN_WIDGET_CONTROL, 0);
079d88cc
WF		 431}
432
384a48d7 433static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 434{
384a48d7 435 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 436 AC_VERB_GET_CVT_CHAN_COUNT, 0);
437}
438
439static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 440 hda_nid_t cvt_nid, int chs)
079d88cc 441{
384a48d7
SW		 442 if (chs != hdmi_get_channel_count(codec, cvt_nid))
443 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 444 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
445}
446
447
448/*
449 * Channel mapping routines
450 */
451
452/*
453 * Compute derived values in channel_allocations[].
454 */
455static void init_channel_allocations(void)
456{
457 int i, j;
458 struct cea_channel_speaker_allocation *p;
459
460 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
461 p = channel_allocations + i;
462 p->channels = 0;
463 p->spk_mask = 0;
464 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
465 if (p->speakers[j]) {
466 p->channels++;
467 p->spk_mask |= p->speakers[j];
468 }
469 }
470}
471
472/*
473 * The transformation takes two steps:
474 *
475 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
476 * spk_mask => (channel_allocations[]) => ai->CA
477 *
478 * TODO: it could select the wrong CA from multiple candidates.
479*/
384a48d7 480static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 481{
079d88cc 482 int i;
53d7d69d 483 int ca = 0;
079d88cc 484 int spk_mask = 0;
079d88cc
WF		 485 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
486
487 /*
488 * CA defaults to 0 for basic stereo audio
489 */
490 if (channels <= 2)
491 return 0;
492
079d88cc
WF		 493 /*
494 * expand ELD's speaker allocation mask
495 *
496 * ELD tells the speaker mask in a compact(paired) form,
497 * expand ELD's notions to match the ones used by Audio InfoFrame.
498 */
499 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
500 if (eld->spk_alloc & (1 << i))
501 spk_mask |= eld_speaker_allocation_bits[i];
502 }
503
504 /* search for the first working match in the CA table */
505 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
506 if (channels == channel_allocations[i].channels &&
507 (spk_mask & channel_allocations[i].spk_mask) ==
508 channel_allocations[i].spk_mask) {
53d7d69d 509 ca = channel_allocations[i].ca_index;
079d88cc
WF		 510 break;
511 }
512 }
513
514 snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
2abbf439 515 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 516 ca, channels, buf);
079d88cc 517
53d7d69d 518 return ca;
079d88cc
WF		 519}
520
521static void hdmi_debug_channel_mapping(struct hda_codec *codec,
522 hda_nid_t pin_nid)
523{
524#ifdef CONFIG_SND_DEBUG_VERBOSE
525 int i;
526 int slot;
527
528 for (i = 0; i < 8; i++) {
529 slot = snd_hda_codec_read(codec, pin_nid, 0,
530 AC_VERB_GET_HDMI_CHAN_SLOT, i);
531 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
532 slot >> 4, slot & 0xf);
533 }
534#endif
535}
536
537
538static void hdmi_setup_channel_mapping(struct hda_codec *codec,
539 hda_nid_t pin_nid,
53d7d69d 540 int ca)
079d88cc
WF		 541{
542 int i;
079d88cc
WF		 543 int err;
544
545 if (hdmi_channel_mapping[ca][1] == 0) {
546 for (i = 0; i < channel_allocations[ca].channels; i++)
547 hdmi_channel_mapping[ca][i] = i | (i << 4);
548 for (; i < 8; i++)
549 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
550 }
551
552 for (i = 0; i < 8; i++) {
553 err = snd_hda_codec_write(codec, pin_nid, 0,
554 AC_VERB_SET_HDMI_CHAN_SLOT,
555 hdmi_channel_mapping[ca][i]);
556 if (err) {
2abbf439
WF		 557 snd_printdd(KERN_NOTICE
558 "HDMI: channel mapping failed\n");
079d88cc
WF		 559 break;
560 }
561 }
562
563 hdmi_debug_channel_mapping(codec, pin_nid);
564}
565
566
567/*
568 * Audio InfoFrame routines
569 */
570
571/*
572 * Enable Audio InfoFrame Transmission
573 */
574static void hdmi_start_infoframe_trans(struct hda_codec *codec,
575 hda_nid_t pin_nid)
576{
577 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
578 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
579 AC_DIPXMIT_BEST);
580}
581
582/*
583 * Disable Audio InfoFrame Transmission
584 */
585static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
586 hda_nid_t pin_nid)
587{
588 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
589 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
590 AC_DIPXMIT_DISABLE);
591}
592
593static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
594{
595#ifdef CONFIG_SND_DEBUG_VERBOSE
596 int i;
597 int size;
598
599 size = snd_hdmi_get_eld_size(codec, pin_nid);
600 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
601
602 for (i = 0; i < 8; i++) {
603 size = snd_hda_codec_read(codec, pin_nid, 0,
604 AC_VERB_GET_HDMI_DIP_SIZE, i);
605 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
606 }
607#endif
608}
609
610static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
611{
612#ifdef BE_PARANOID
613 int i, j;
614 int size;
615 int pi, bi;
616 for (i = 0; i < 8; i++) {
617 size = snd_hda_codec_read(codec, pin_nid, 0,
618 AC_VERB_GET_HDMI_DIP_SIZE, i);
619 if (size == 0)
620 continue;
621
622 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
623 for (j = 1; j < 1000; j++) {
624 hdmi_write_dip_byte(codec, pin_nid, 0x0);
625 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
626 if (pi != i)
627 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
628 bi, pi, i);
629 if (bi == 0) /* byte index wrapped around */
630 break;
631 }
632 snd_printd(KERN_INFO
633 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
634 i, size, j);
635 }
636#endif
637}
638
53d7d69d 639static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 640{
53d7d69d 641 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 642 u8 sum = 0;
643 int i;
644
53d7d69d 645 hdmi_ai->checksum = 0;
079d88cc 646
53d7d69d 647 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 648 sum += bytes[i];
649
53d7d69d 650 hdmi_ai->checksum = -sum;
079d88cc
WF		 651}
652
653static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
654 hda_nid_t pin_nid,
53d7d69d 655 u8 *dip, int size)
079d88cc 656{
079d88cc
WF		 657 int i;
658
659 hdmi_debug_dip_size(codec, pin_nid);
660 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
661
079d88cc 662 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 663 for (i = 0; i < size; i++)
664 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 665}
666
667static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 668 u8 *dip, int size)
079d88cc 669{
079d88cc
WF		 670 u8 val;
671 int i;
672
673 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
674 != AC_DIPXMIT_BEST)
675 return false;
676
677 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 678 for (i = 0; i < size; i++) {
079d88cc
WF		 679 val = snd_hda_codec_read(codec, pin_nid, 0,
680 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 681 if (val != dip[i])
079d88cc
WF		 682 return false;
683 }
684
685 return true;
686}
687
384a48d7 688static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
079d88cc
WF		 689 struct snd_pcm_substream *substream)
690{
691 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 692 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
693 hda_nid_t pin_nid = per_pin->pin_nid;
53d7d69d 694 int channels = substream->runtime->channels;
384a48d7 695 struct hdmi_eld *eld;
53d7d69d 696 int ca;
2b203dbb 697 union audio_infoframe ai;
079d88cc 698
384a48d7
SW		 699 eld = &spec->pins[pin_idx].sink_eld;
700 if (!eld->monitor_present)
701 return;
079d88cc 702
384a48d7
SW		 703 ca = hdmi_channel_allocation(eld, channels);
704
705 memset(&ai, 0, sizeof(ai));
706 if (eld->conn_type == 0) { /* HDMI */
707 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
708
709 hdmi_ai->type = 0x84;
710 hdmi_ai->ver = 0x01;
711 hdmi_ai->len = 0x0a;
712 hdmi_ai->CC02_CT47 = channels - 1;
713 hdmi_ai->CA = ca;
714 hdmi_checksum_audio_infoframe(hdmi_ai);
715 } else if (eld->conn_type == 1) { /* DisplayPort */
716 struct dp_audio_infoframe *dp_ai = &ai.dp;
717
718 dp_ai->type = 0x84;
719 dp_ai->len = 0x1b;
720 dp_ai->ver = 0x11 << 2;
721 dp_ai->CC02_CT47 = channels - 1;
722 dp_ai->CA = ca;
723 } else {
724 snd_printd("HDMI: unknown connection type at pin %d\n",
725 pin_nid);
726 return;
727 }
53d7d69d 728
384a48d7
SW		 729 /*
730 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
731 * sizeof(*dp_ai) to avoid partial match/update problems when
732 * the user switches between HDMI/DP monitors.
733 */
734 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
735 sizeof(ai))) {
736 snd_printdd("hdmi_setup_audio_infoframe: "
737 "pin=%d channels=%d\n",
738 pin_nid,
739 channels);
740 hdmi_setup_channel_mapping(codec, pin_nid, ca);
741 hdmi_stop_infoframe_trans(codec, pin_nid);
742 hdmi_fill_audio_infoframe(codec, pin_nid,
743 ai.bytes, sizeof(ai));
744 hdmi_start_infoframe_trans(codec, pin_nid);
079d88cc
WF		 745 }
746}
747
748
749/*
750 * Unsolicited events
751 */
752
c6e8453e 753static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 754
079d88cc
WF		 755static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
756{
757 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 758 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
759 int pin_nid;
384a48d7 760 int pin_idx;
3a93897e
TI		 761 struct hda_jack_tbl *jack;
762
763 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
764 if (!jack)
765 return;
766 pin_nid = jack->nid;
767 jack->jack_dirty = 1;
079d88cc 768
fae3d88a 769 _snd_printd(SND_PR_VERBOSE,
384a48d7 770 "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
fae3d88a
FW		 771 codec->addr, pin_nid,
772 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 773
384a48d7
SW		 774 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
775 if (pin_idx < 0)
079d88cc
WF		 776 return;
777
c6e8453e 778 hdmi_present_sense(&spec->pins[pin_idx], 1);
01a61e12 779 snd_hda_jack_report_sync(codec);
079d88cc
WF		 780}
781
782static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
783{
784 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
785 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
786 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
787 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
788
789 printk(KERN_INFO
e9ea8e8f 790 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 791 codec->addr,
079d88cc
WF		 792 tag,
793 subtag,
794 cp_state,
795 cp_ready);
796
797 /* TODO */
798 if (cp_state)
799 ;
800 if (cp_ready)
801 ;
802}
803
804
805static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
806{
079d88cc
WF		 807 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
808 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
809
3a93897e 810 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 811 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
812 return;
813 }
814
815 if (subtag == 0)
816 hdmi_intrinsic_event(codec, res);
817 else
818 hdmi_non_intrinsic_event(codec, res);
819}
820
821/*
822 * Callbacks
823 */
824
92f10b3f
TI		 825/* HBR should be Non-PCM, 8 channels */
826#define is_hbr_format(format) \
827 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
828
384a48d7
SW		 829static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
830 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 831{
ea87d1c4
AH		 832 int pinctl;
833 int new_pinctl = 0;
ea87d1c4 834
384a48d7
SW		 835 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
836 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 837 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
838
839 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 840 if (is_hbr_format(format))
ea87d1c4
AH		 841 new_pinctl |= AC_PINCTL_EPT_HBR;
842 else
843 new_pinctl |= AC_PINCTL_EPT_NATIVE;
844
845 snd_printdd("hdmi_setup_stream: "
846 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 847 pin_nid,
ea87d1c4
AH		 848 pinctl == new_pinctl ? "" : "new-",
849 new_pinctl);
850
851 if (pinctl != new_pinctl)
384a48d7 852 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 853 AC_VERB_SET_PIN_WIDGET_CONTROL,
854 new_pinctl);
ea87d1c4 855
384a48d7 856 }
92f10b3f 857 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 858 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
859 return -EINVAL;
860 }
079d88cc 861
384a48d7 862 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 863 return 0;
079d88cc
WF		 864}
865
bbbe3390
TI		 866/*
867 * HDA PCM callbacks
868 */
869static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
870 struct hda_codec *codec,
871 struct snd_pcm_substream *substream)
872{
873 struct hdmi_spec *spec = codec->spec;
639cef0e 874 struct snd_pcm_runtime *runtime = substream->runtime;
384a48d7
SW		 875 int pin_idx, cvt_idx, mux_idx = 0;
876 struct hdmi_spec_per_pin *per_pin;
877 struct hdmi_eld *eld;
878 struct hdmi_spec_per_cvt *per_cvt = NULL;
bbbe3390 879
384a48d7
SW		 880 /* Validate hinfo */
881 pin_idx = hinfo_to_pin_index(spec, hinfo);
882 if (snd_BUG_ON(pin_idx < 0))
bbbe3390 883 return -EINVAL;
384a48d7
SW		 884 per_pin = &spec->pins[pin_idx];
885 eld = &per_pin->sink_eld;
886
887 /* Dynamically assign converter to stream */
888 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
889 per_cvt = &spec->cvts[cvt_idx];
bbbe3390 890
384a48d7
SW		 891 /* Must not already be assigned */
892 if (per_cvt->assigned)
893 continue;
894 /* Must be in pin's mux's list of converters */
895 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
896 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
897 break;
898 /* Not in mux list */
899 if (mux_idx == per_pin->num_mux_nids)
900 continue;
901 break;
902 }
903 /* No free converters */
904 if (cvt_idx == spec->num_cvts)
905 return -ENODEV;
906
907 /* Claim converter */
908 per_cvt->assigned = 1;
909 hinfo->nid = per_cvt->cvt_nid;
910
911 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
912 AC_VERB_SET_CONNECT_SEL,
913 mux_idx);
384a48d7 914 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 915
2def8172 916 /* Initially set the converter's capabilities */
384a48d7
SW		 917 hinfo->channels_min = per_cvt->channels_min;
918 hinfo->channels_max = per_cvt->channels_max;
919 hinfo->rates = per_cvt->rates;
920 hinfo->formats = per_cvt->formats;
921 hinfo->maxbps = per_cvt->maxbps;
2def8172 922
384a48d7 923 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 924 if (!static_hdmi_pcm && eld->eld_valid) {
2def8172 925 snd_hdmi_eld_update_pcm_info(eld, hinfo);
bbbe3390
TI		 926 if (hinfo->channels_min > hinfo->channels_max ||
927 !hinfo->rates || !hinfo->formats)
928 return -ENODEV;
bbbe3390 929 }
2def8172
SW		 930
931 /* Store the updated parameters */
639cef0e
TI		 932 runtime->hw.channels_min = hinfo->channels_min;
933 runtime->hw.channels_max = hinfo->channels_max;
934 runtime->hw.formats = hinfo->formats;
935 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 936
937 snd_pcm_hw_constraint_step(substream->runtime, 0,
938 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 939 return 0;
940}
941
079d88cc
WF		 942/*
943 * HDA/HDMI auto parsing
944 */
384a48d7 945static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 946{
947 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 948 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
949 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 950
951 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
952 snd_printk(KERN_WARNING
953 "HDMI: pin %d wcaps %#x "
954 "does not support connection list\n",
955 pin_nid, get_wcaps(codec, pin_nid));
956 return -EINVAL;
957 }
958
384a48d7
SW		 959 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
960 per_pin->mux_nids,
961 HDA_MAX_CONNECTIONS);
079d88cc
WF		 962
963 return 0;
964}
965
c6e8453e 966static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 967{
744626da
WF		 968 struct hda_codec *codec = per_pin->codec;
969 struct hdmi_eld *eld = &per_pin->sink_eld;
970 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 971 /*
972 * Always execute a GetPinSense verb here, even when called from
973 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
974 * response's PD bit is not the real PD value, but indicates that
975 * the real PD value changed. An older version of the HD-audio
976 * specification worked this way. Hence, we just ignore the data in
977 * the unsolicited response to avoid custom WARs.
978 */
079d88cc 979 int present = snd_hda_pin_sense(codec, pin_nid);
b95d68b8 980 bool eld_valid = false;
079d88cc 981
b95d68b8 982 memset(eld, 0, offsetof(struct hdmi_eld, eld_buffer));
5d44f927 983
079d88cc 984 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
5d44f927 985 if (eld->monitor_present)
b95d68b8 986 eld_valid = !!(present & AC_PINSENSE_ELDV);
079d88cc 987
fae3d88a 988 _snd_printd(SND_PR_VERBOSE,
384a48d7 989 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
b95d68b8 990 codec->addr, pin_nid, eld->monitor_present, eld_valid);
5d44f927 991
744626da 992 if (eld_valid) {
5d44f927
SW		 993 if (!snd_hdmi_get_eld(eld, codec, pin_nid))
994 snd_hdmi_show_eld(eld);
c6e8453e 995 else if (repoll) {
744626da
WF		 996 queue_delayed_work(codec->bus->workq,
997 &per_pin->work,
998 msecs_to_jiffies(300));
999 }
1000 }
079d88cc
WF		 1001}
1002
744626da
WF		 1003static void hdmi_repoll_eld(struct work_struct *work)
1004{
1005 struct hdmi_spec_per_pin *per_pin =
1006 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1007
c6e8453e
WF		 1008 if (per_pin->repoll_count++ > 6)
1009 per_pin->repoll_count = 0;
1010
1011 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1012}
1013
079d88cc
WF		 1014static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1015{
1016 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1017 unsigned int caps, config;
1018 int pin_idx;
1019 struct hdmi_spec_per_pin *per_pin;
07acecc1 1020 int err;
079d88cc 1021
384a48d7
SW		 1022 caps = snd_hda_param_read(codec, pin_nid, AC_PAR_PIN_CAP);
1023 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1024 return 0;
1025
1026 config = snd_hda_codec_read(codec, pin_nid, 0,
1027 AC_VERB_GET_CONFIG_DEFAULT, 0);
1028 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1029 return 0;
1030
1031 if (snd_BUG_ON(spec->num_pins >= MAX_HDMI_PINS))
3eaead57 1032 return -E2BIG;
384a48d7
SW		 1033
1034 pin_idx = spec->num_pins;
1035 per_pin = &spec->pins[pin_idx];
384a48d7
SW		 1036
1037 per_pin->pin_nid = pin_nid;
079d88cc 1038
384a48d7
SW		 1039 err = hdmi_read_pin_conn(codec, pin_idx);
1040 if (err < 0)
1041 return err;
079d88cc 1042
079d88cc
WF		 1043 spec->num_pins++;
1044
384a48d7 1045 return 0;
079d88cc
WF		 1046}
1047
384a48d7 1048static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1049{
1050 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1051 int cvt_idx;
1052 struct hdmi_spec_per_cvt *per_cvt;
1053 unsigned int chans;
1054 int err;
079d88cc 1055
116dcde6
DH		 1056 if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
1057 return -E2BIG;
1058
384a48d7
SW		 1059 chans = get_wcaps(codec, cvt_nid);
1060 chans = get_wcaps_channels(chans);
1061
1062 cvt_idx = spec->num_cvts;
1063 per_cvt = &spec->cvts[cvt_idx];
1064
1065 per_cvt->cvt_nid = cvt_nid;
1066 per_cvt->channels_min = 2;
1067 if (chans <= 16)
1068 per_cvt->channels_max = chans;
1069
1070 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1071 &per_cvt->rates,
1072 &per_cvt->formats,
1073 &per_cvt->maxbps);
1074 if (err < 0)
1075 return err;
1076
079d88cc
WF		 1077 spec->num_cvts++;
1078
1079 return 0;
1080}
1081
1082static int hdmi_parse_codec(struct hda_codec *codec)
1083{
1084 hda_nid_t nid;
1085 int i, nodes;
1086
1087 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1088 if (!nid || nodes < 0) {
1089 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1090 return -EINVAL;
1091 }
1092
1093 for (i = 0; i < nodes; i++, nid++) {
1094 unsigned int caps;
1095 unsigned int type;
1096
1097 caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP);
1098 type = get_wcaps_type(caps);
1099
1100 if (!(caps & AC_WCAP_DIGITAL))
1101 continue;
1102
1103 switch (type) {
1104 case AC_WID_AUD_OUT:
384a48d7 1105 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1106 break;
1107 case AC_WID_PIN:
3eaead57 1108 hdmi_add_pin(codec, nid);
079d88cc
WF		 1109 break;
1110 }
1111 }
1112
1113 /*
1114 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1115 * can be lost and presence sense verb will become inaccurate if the
1116 * HDA link is powered off at hot plug or hw initialization time.
1117 */
83012a7c 1118#ifdef CONFIG_PM
079d88cc
WF		 1119 if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
1120 AC_PWRST_EPSS))
1121 codec->bus->power_keep_link_on = 1;
1122#endif
1123
1124 return 0;
1125}
1126
84eb01be
TI		 1127/*
1128 */
a4567cb3
TI		 1129static char *get_hdmi_pcm_name(int idx)
1130{
1131 static char names[MAX_HDMI_PINS][8];
1132 sprintf(&names[idx][0], "HDMI %d", idx);
1133 return &names[idx][0];
1134}
84eb01be
TI		 1135
1136/*
1137 * HDMI callbacks
1138 */
1139
1140static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1141 struct hda_codec *codec,
1142 unsigned int stream_tag,
1143 unsigned int format,
1144 struct snd_pcm_substream *substream)
1145{
384a48d7
SW		 1146 hda_nid_t cvt_nid = hinfo->nid;
1147 struct hdmi_spec *spec = codec->spec;
1148 int pin_idx = hinfo_to_pin_index(spec, hinfo);
1149 hda_nid_t pin_nid = spec->pins[pin_idx].pin_nid;
9e76e6d0 1150 int pinctl;
384a48d7
SW		 1151
1152 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
84eb01be 1153
384a48d7 1154 hdmi_setup_audio_infoframe(codec, pin_idx, substream);
84eb01be 1155
9e76e6d0
DR		 1156 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1157 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1158 snd_hda_codec_write(codec, pin_nid, 0,
1159 AC_VERB_SET_PIN_WIDGET_CONTROL, pinctl | PIN_OUT);
1160
384a48d7 1161 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1162}
1163
8dfaa573
TI		 1164static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1165 struct hda_codec *codec,
1166 struct snd_pcm_substream *substream)
1167{
1168 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1169 return 0;
1170}
1171
f2ad24fa
TI		 1172static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1173 struct hda_codec *codec,
1174 struct snd_pcm_substream *substream)
384a48d7
SW		 1175{
1176 struct hdmi_spec *spec = codec->spec;
1177 int cvt_idx, pin_idx;
1178 struct hdmi_spec_per_cvt *per_cvt;
1179 struct hdmi_spec_per_pin *per_pin;
1180 int pinctl;
1181
384a48d7
SW		 1182 if (hinfo->nid) {
1183 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1184 if (snd_BUG_ON(cvt_idx < 0))
1185 return -EINVAL;
1186 per_cvt = &spec->cvts[cvt_idx];
1187
1188 snd_BUG_ON(!per_cvt->assigned);
1189 per_cvt->assigned = 0;
1190 hinfo->nid = 0;
1191
1192 pin_idx = hinfo_to_pin_index(spec, hinfo);
1193 if (snd_BUG_ON(pin_idx < 0))
1194 return -EINVAL;
1195 per_pin = &spec->pins[pin_idx];
1196
1197 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1198 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1199 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1200 AC_VERB_SET_PIN_WIDGET_CONTROL,
1201 pinctl & ~PIN_OUT);
1202 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1203 }
384a48d7
SW		 1204 return 0;
1205}
1206
1207static const struct hda_pcm_ops generic_ops = {
1208 .open = hdmi_pcm_open,
f2ad24fa 1209 .close = hdmi_pcm_close,
384a48d7 1210 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1211 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1212};
1213
1214static int generic_hdmi_build_pcms(struct hda_codec *codec)
1215{
1216 struct hdmi_spec *spec = codec->spec;
384a48d7 1217 int pin_idx;
84eb01be 1218
384a48d7
SW		 1219 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1220 struct hda_pcm *info;
84eb01be
TI		 1221 struct hda_pcm_stream *pstr;
1222
384a48d7 1223 info = &spec->pcm_rec[pin_idx];
a4567cb3 1224 info->name = get_hdmi_pcm_name(pin_idx);
84eb01be 1225 info->pcm_type = HDA_PCM_TYPE_HDMI;
384a48d7 1226
84eb01be 1227 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1228 pstr->substreams = 1;
1229 pstr->ops = generic_ops;
1230 /* other pstr fields are set in open */
84eb01be
TI		 1231 }
1232
384a48d7
SW		 1233 codec->num_pcms = spec->num_pins;
1234 codec->pcm_info = spec->pcm_rec;
1235
84eb01be
TI		 1236 return 0;
1237}
1238
0b6c49b5
DH		 1239static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1240{
31ef2257 1241 char hdmi_str[32] = "HDMI/DP";
0b6c49b5
DH		 1242 struct hdmi_spec *spec = codec->spec;
1243 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1244 int pcmdev = spec->pcm_rec[pin_idx].device;
1245
31ef2257
TI		 1246 if (pcmdev > 0)
1247 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
0b6c49b5 1248
31ef2257 1249 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1250}
1251
84eb01be
TI		 1252static int generic_hdmi_build_controls(struct hda_codec *codec)
1253{
1254 struct hdmi_spec *spec = codec->spec;
1255 int err;
384a48d7 1256 int pin_idx;
84eb01be 1257
384a48d7
SW		 1258 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1259 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
0b6c49b5
DH		 1260
1261 err = generic_hdmi_build_jack(codec, pin_idx);
1262 if (err < 0)
1263 return err;
1264
384a48d7
SW		 1265 err = snd_hda_create_spdif_out_ctls(codec,
1266 per_pin->pin_nid,
1267 per_pin->mux_nids[0]);
84eb01be
TI		 1268 if (err < 0)
1269 return err;
384a48d7 1270 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1271
1272 /* add control for ELD Bytes */
1273 err = hdmi_create_eld_ctl(codec,
1274 pin_idx,
1275 spec->pcm_rec[pin_idx].device);
1276
1277 if (err < 0)
1278 return err;
31ef2257 1279
82b1d73f 1280 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 1281 }
1282
1283 return 0;
1284}
1285
8b8d654b 1286static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 1287{
1288 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1289 int pin_idx;
1290
1291 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1292 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
384a48d7 1293 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1294
744626da
WF		 1295 per_pin->codec = codec;
1296 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
384a48d7 1297 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be 1298 }
8b8d654b
TI		 1299 return 0;
1300}
1301
1302static int generic_hdmi_init(struct hda_codec *codec)
1303{
1304 struct hdmi_spec *spec = codec->spec;
1305 int pin_idx;
1306
1307 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1308 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1309 hda_nid_t pin_nid = per_pin->pin_nid;
1310
1311 hdmi_init_pin(codec, pin_nid);
1312 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
1313 }
84eb01be
TI		 1314 return 0;
1315}
1316
1317static void generic_hdmi_free(struct hda_codec *codec)
1318{
1319 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1320 int pin_idx;
1321
1322 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1323 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1324 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1325
744626da 1326 cancel_delayed_work(&per_pin->work);
384a48d7
SW		 1327 snd_hda_eld_proc_free(codec, eld);
1328 }
84eb01be 1329
744626da 1330 flush_workqueue(codec->bus->workq);
84eb01be
TI		 1331 kfree(spec);
1332}
1333
fb79e1e0 1334static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1335 .init = generic_hdmi_init,
1336 .free = generic_hdmi_free,
1337 .build_pcms = generic_hdmi_build_pcms,
1338 .build_controls = generic_hdmi_build_controls,
1339 .unsol_event = hdmi_unsol_event,
1340};
1341
1342static int patch_generic_hdmi(struct hda_codec *codec)
1343{
1344 struct hdmi_spec *spec;
84eb01be
TI		 1345
1346 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1347 if (spec == NULL)
1348 return -ENOMEM;
1349
1350 codec->spec = spec;
1351 if (hdmi_parse_codec(codec) < 0) {
1352 codec->spec = NULL;
1353 kfree(spec);
1354 return -EINVAL;
1355 }
1356 codec->patch_ops = generic_hdmi_patch_ops;
8b8d654b 1357 generic_hdmi_init_per_pins(codec);
84eb01be 1358
84eb01be
TI		 1359 init_channel_allocations();
1360
1361 return 0;
1362}
1363
3aaf8980
SW		 1364/*
1365 * Shared non-generic implementations
1366 */
1367
1368static int simple_playback_build_pcms(struct hda_codec *codec)
1369{
1370 struct hdmi_spec *spec = codec->spec;
1371 struct hda_pcm *info = spec->pcm_rec;
8ceb332d
TI		 1372 unsigned int chans;
1373 struct hda_pcm_stream *pstr;
3aaf8980 1374
8ceb332d 1375 codec->num_pcms = 1;
3aaf8980
SW		 1376 codec->pcm_info = info;
1377
8ceb332d
TI		 1378 chans = get_wcaps(codec, spec->cvts[0].cvt_nid);
1379 chans = get_wcaps_channels(chans);
3aaf8980 1380
8ceb332d
TI		 1381 info->name = get_hdmi_pcm_name(0);
1382 info->pcm_type = HDA_PCM_TYPE_HDMI;
1383 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1384 *pstr = spec->pcm_playback;
1385 pstr->nid = spec->cvts[0].cvt_nid;
1386 if (pstr->channels_max <= 2 && chans && chans <= 16)
1387 pstr->channels_max = chans;
3aaf8980
SW		 1388
1389 return 0;
1390}
1391
4b6ace9e
TI		 1392/* unsolicited event for jack sensing */
1393static void simple_hdmi_unsol_event(struct hda_codec *codec,
1394 unsigned int res)
1395{
9dd8cf12 1396 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 1397 snd_hda_jack_report_sync(codec);
1398}
1399
1400/* generic_hdmi_build_jack can be used for simple_hdmi, too,
1401 * as long as spec->pins[] is set correctly
1402 */
1403#define simple_hdmi_build_jack generic_hdmi_build_jack
1404
3aaf8980
SW		 1405static int simple_playback_build_controls(struct hda_codec *codec)
1406{
1407 struct hdmi_spec *spec = codec->spec;
1408 int err;
3aaf8980 1409
8ceb332d
TI		 1410 err = snd_hda_create_spdif_out_ctls(codec,
1411 spec->cvts[0].cvt_nid,
1412 spec->cvts[0].cvt_nid);
1413 if (err < 0)
1414 return err;
1415 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 1416}
1417
4f0110ce
TI		 1418static int simple_playback_init(struct hda_codec *codec)
1419{
1420 struct hdmi_spec *spec = codec->spec;
8ceb332d
TI		 1421 hda_nid_t pin = spec->pins[0].pin_nid;
1422
1423 snd_hda_codec_write(codec, pin, 0,
1424 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
1425 /* some codecs require to unmute the pin */
1426 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
1427 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
1428 AMP_OUT_UNMUTE);
1429 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 1430 return 0;
1431}
1432
3aaf8980
SW		 1433static void simple_playback_free(struct hda_codec *codec)
1434{
1435 struct hdmi_spec *spec = codec->spec;
1436
1437 kfree(spec);
1438}
1439
84eb01be
TI		 1440/*
1441 * Nvidia specific implementations
1442 */
1443
1444#define Nv_VERB_SET_Channel_Allocation 0xF79
1445#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1446#define Nv_VERB_SET_Audio_Protection_On 0xF98
1447#define Nv_VERB_SET_Audio_Protection_Off 0xF99
1448
1449#define nvhdmi_master_con_nid_7x 0x04
1450#define nvhdmi_master_pin_nid_7x 0x05
1451
fb79e1e0 1452static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 1453 /*front, rear, clfe, rear_surr */
1454 0x6, 0x8, 0xa, 0xc,
1455};
1456
ceaa86ba
TI		 1457static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
1458 /* set audio protect on */
1459 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1460 /* enable digital output on pin widget */
1461 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1462 {} /* terminator */
1463};
1464
1465static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 1466 /* set audio protect on */
1467 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1468 /* enable digital output on pin widget */
1469 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1470 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1471 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1472 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1473 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1474 {} /* terminator */
1475};
1476
1477#ifdef LIMITED_RATE_FMT_SUPPORT
1478/* support only the safe format and rate */
1479#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1480#define SUPPORTED_MAXBPS 16
1481#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1482#else
1483/* support all rates and formats */
1484#define SUPPORTED_RATES \
1485 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1486 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1487 SNDRV_PCM_RATE_192000)
1488#define SUPPORTED_MAXBPS 24
1489#define SUPPORTED_FORMATS \
1490 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1491#endif
1492
ceaa86ba
TI		 1493static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
1494{
1495 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
1496 return 0;
1497}
1498
1499static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 1500{
ceaa86ba 1501 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 1502 return 0;
1503}
1504
393004b2
ND		 1505static unsigned int channels_2_6_8[] = {
1506 2, 6, 8
1507};
1508
1509static unsigned int channels_2_8[] = {
1510 2, 8
1511};
1512
1513static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
1514 .count = ARRAY_SIZE(channels_2_6_8),
1515 .list = channels_2_6_8,
1516 .mask = 0,
1517};
1518
1519static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
1520 .count = ARRAY_SIZE(channels_2_8),
1521 .list = channels_2_8,
1522 .mask = 0,
1523};
1524
84eb01be
TI		 1525static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
1526 struct hda_codec *codec,
1527 struct snd_pcm_substream *substream)
1528{
1529 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 1530 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
1531
1532 switch (codec->preset->id) {
1533 case 0x10de0002:
1534 case 0x10de0003:
1535 case 0x10de0005:
1536 case 0x10de0006:
1537 hw_constraints_channels = &hw_constraints_2_8_channels;
1538 break;
1539 case 0x10de0007:
1540 hw_constraints_channels = &hw_constraints_2_6_8_channels;
1541 break;
1542 default:
1543 break;
1544 }
1545
1546 if (hw_constraints_channels != NULL) {
1547 snd_pcm_hw_constraint_list(substream->runtime, 0,
1548 SNDRV_PCM_HW_PARAM_CHANNELS,
1549 hw_constraints_channels);
ad09fc9d
TI		 1550 } else {
1551 snd_pcm_hw_constraint_step(substream->runtime, 0,
1552 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 1553 }
1554
84eb01be
TI		 1555 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
1556}
1557
1558static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
1559 struct hda_codec *codec,
1560 struct snd_pcm_substream *substream)
1561{
1562 struct hdmi_spec *spec = codec->spec;
1563 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1564}
1565
1566static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1567 struct hda_codec *codec,
1568 unsigned int stream_tag,
1569 unsigned int format,
1570 struct snd_pcm_substream *substream)
1571{
1572 struct hdmi_spec *spec = codec->spec;
1573 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
1574 stream_tag, format, substream);
1575}
1576
d0b1252d
TI		 1577static const struct hda_pcm_stream simple_pcm_playback = {
1578 .substreams = 1,
1579 .channels_min = 2,
1580 .channels_max = 2,
1581 .ops = {
1582 .open = simple_playback_pcm_open,
1583 .close = simple_playback_pcm_close,
1584 .prepare = simple_playback_pcm_prepare
1585 },
1586};
1587
1588static const struct hda_codec_ops simple_hdmi_patch_ops = {
1589 .build_controls = simple_playback_build_controls,
1590 .build_pcms = simple_playback_build_pcms,
1591 .init = simple_playback_init,
1592 .free = simple_playback_free,
250e41ac 1593 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 1594};
1595
1596static int patch_simple_hdmi(struct hda_codec *codec,
1597 hda_nid_t cvt_nid, hda_nid_t pin_nid)
1598{
1599 struct hdmi_spec *spec;
1600
1601 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1602 if (!spec)
1603 return -ENOMEM;
1604
1605 codec->spec = spec;
1606
1607 spec->multiout.num_dacs = 0; /* no analog */
1608 spec->multiout.max_channels = 2;
1609 spec->multiout.dig_out_nid = cvt_nid;
1610 spec->num_cvts = 1;
1611 spec->num_pins = 1;
1612 spec->cvts[0].cvt_nid = cvt_nid;
21cd683d 1613 spec->pins[0].pin_nid = pin_nid;
d0b1252d
TI		 1614 spec->pcm_playback = simple_pcm_playback;
1615
1616 codec->patch_ops = simple_hdmi_patch_ops;
1617
1618 return 0;
1619}
1620
1f348522
AP		 1621static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
1622 int channels)
1623{
1624 unsigned int chanmask;
1625 int chan = channels ? (channels - 1) : 1;
1626
1627 switch (channels) {
1628 default:
1629 case 0:
1630 case 2:
1631 chanmask = 0x00;
1632 break;
1633 case 4:
1634 chanmask = 0x08;
1635 break;
1636 case 6:
1637 chanmask = 0x0b;
1638 break;
1639 case 8:
1640 chanmask = 0x13;
1641 break;
1642 }
1643
1644 /* Set the audio infoframe channel allocation and checksum fields. The
1645 * channel count is computed implicitly by the hardware. */
1646 snd_hda_codec_write(codec, 0x1, 0,
1647 Nv_VERB_SET_Channel_Allocation, chanmask);
1648
1649 snd_hda_codec_write(codec, 0x1, 0,
1650 Nv_VERB_SET_Info_Frame_Checksum,
1651 (0x71 - chan - chanmask));
1652}
1653
84eb01be
TI		 1654static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
1655 struct hda_codec *codec,
1656 struct snd_pcm_substream *substream)
1657{
1658 struct hdmi_spec *spec = codec->spec;
1659 int i;
1660
1661 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
1662 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
1663 for (i = 0; i < 4; i++) {
1664 /* set the stream id */
1665 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1666 AC_VERB_SET_CHANNEL_STREAMID, 0);
1667 /* set the stream format */
1668 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1669 AC_VERB_SET_STREAM_FORMAT, 0);
1670 }
1671
1f348522
AP		 1672 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
1673 * streams are disabled. */
1674 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
1675
84eb01be
TI		 1676 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1677}
1678
1679static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
1680 struct hda_codec *codec,
1681 unsigned int stream_tag,
1682 unsigned int format,
1683 struct snd_pcm_substream *substream)
1684{
1685 int chs;
112daa7a 1686 unsigned int dataDCC2, channel_id;
84eb01be 1687 int i;
7c935976 1688 struct hdmi_spec *spec = codec->spec;
e3245cdd 1689 struct hda_spdif_out *spdif;
84eb01be
TI		 1690
1691 mutex_lock(&codec->spdif_mutex);
e3245cdd 1692 spdif = snd_hda_spdif_out_of_nid(codec, spec->cvts[0].cvt_nid);
84eb01be
TI		 1693
1694 chs = substream->runtime->channels;
84eb01be 1695
84eb01be
TI		 1696 dataDCC2 = 0x2;
1697
84eb01be 1698 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 1699 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 1700 snd_hda_codec_write(codec,
1701 nvhdmi_master_con_nid_7x,
1702 0,
1703 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1704 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 1705
1706 /* set the stream id */
1707 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1708 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
1709
1710 /* set the stream format */
1711 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1712 AC_VERB_SET_STREAM_FORMAT, format);
1713
1714 /* turn on again (if needed) */
1715 /* enable and set the channel status audio/data flag */
7c935976 1716 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 1717 snd_hda_codec_write(codec,
1718 nvhdmi_master_con_nid_7x,
1719 0,
1720 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1721 spdif->ctls & 0xff);
84eb01be
TI		 1722 snd_hda_codec_write(codec,
1723 nvhdmi_master_con_nid_7x,
1724 0,
1725 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1726 }
1727
1728 for (i = 0; i < 4; i++) {
1729 if (chs == 2)
1730 channel_id = 0;
1731 else
1732 channel_id = i * 2;
1733
1734 /* turn off SPDIF once;
1735 *otherwise the IEC958 bits won't be updated
1736 */
1737 if (codec->spdif_status_reset &&
7c935976 1738 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 1739 snd_hda_codec_write(codec,
1740 nvhdmi_con_nids_7x[i],
1741 0,
1742 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1743 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 1744 /* set the stream id */
1745 snd_hda_codec_write(codec,
1746 nvhdmi_con_nids_7x[i],
1747 0,
1748 AC_VERB_SET_CHANNEL_STREAMID,
1749 (stream_tag << 4) | channel_id);
1750 /* set the stream format */
1751 snd_hda_codec_write(codec,
1752 nvhdmi_con_nids_7x[i],
1753 0,
1754 AC_VERB_SET_STREAM_FORMAT,
1755 format);
1756 /* turn on again (if needed) */
1757 /* enable and set the channel status audio/data flag */
1758 if (codec->spdif_status_reset &&
7c935976 1759 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 1760 snd_hda_codec_write(codec,
1761 nvhdmi_con_nids_7x[i],
1762 0,
1763 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1764 spdif->ctls & 0xff);
84eb01be
TI		 1765 snd_hda_codec_write(codec,
1766 nvhdmi_con_nids_7x[i],
1767 0,
1768 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1769 }
1770 }
1771
1f348522 1772 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 1773
1774 mutex_unlock(&codec->spdif_mutex);
1775 return 0;
1776}
1777
fb79e1e0 1778static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 1779 .substreams = 1,
1780 .channels_min = 2,
1781 .channels_max = 8,
1782 .nid = nvhdmi_master_con_nid_7x,
1783 .rates = SUPPORTED_RATES,
1784 .maxbps = SUPPORTED_MAXBPS,
1785 .formats = SUPPORTED_FORMATS,
1786 .ops = {
1787 .open = simple_playback_pcm_open,
1788 .close = nvhdmi_8ch_7x_pcm_close,
1789 .prepare = nvhdmi_8ch_7x_pcm_prepare
1790 },
1791};
1792
84eb01be
TI		 1793static int patch_nvhdmi_2ch(struct hda_codec *codec)
1794{
1795 struct hdmi_spec *spec;
d0b1252d
TI		 1796 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
1797 nvhdmi_master_pin_nid_7x);
1798 if (err < 0)
1799 return err;
84eb01be 1800
ceaa86ba 1801 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 1802 /* override the PCM rates, etc, as the codec doesn't give full list */
1803 spec = codec->spec;
1804 spec->pcm_playback.rates = SUPPORTED_RATES;
1805 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
1806 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 1807 return 0;
1808}
1809
1810static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
1811{
1812 struct hdmi_spec *spec;
1813 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 1814 if (err < 0)
1815 return err;
1816 spec = codec->spec;
1817 spec->multiout.max_channels = 8;
d0b1252d 1818 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 1819 codec->patch_ops.init = nvhdmi_7x_init_8ch;
1f348522
AP		 1820
1821 /* Initialize the audio infoframe channel mask and checksum to something
1822 * valid */
1823 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
1824
84eb01be
TI		 1825 return 0;
1826}
1827
1828/*
1829 * ATI-specific implementations
1830 *
1831 * FIXME: we may omit the whole this and use the generic code once after
1832 * it's confirmed to work.
1833 */
1834
1835#define ATIHDMI_CVT_NID 0x02 /* audio converter */
1836#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
1837
1838static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1839 struct hda_codec *codec,
1840 unsigned int stream_tag,
1841 unsigned int format,
1842 struct snd_pcm_substream *substream)
1843{
1844 struct hdmi_spec *spec = codec->spec;
1845 int chans = substream->runtime->channels;
1846 int i, err;
1847
1848 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
1849 substream);
1850 if (err < 0)
1851 return err;
384a48d7
SW		 1852 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
1853 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 1854 /* FIXME: XXX */
1855 for (i = 0; i < chans; i++) {
384a48d7 1856 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
84eb01be
TI		 1857 AC_VERB_SET_HDMI_CHAN_SLOT,
1858 (i << 4) | i);
1859 }
1860 return 0;
1861}
1862
84eb01be
TI		 1863static int patch_atihdmi(struct hda_codec *codec)
1864{
1865 struct hdmi_spec *spec;
d0b1252d
TI		 1866 int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
1867 if (err < 0)
1868 return err;
1869 spec = codec->spec;
1870 spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
84eb01be
TI		 1871 return 0;
1872}
1873
3de5ff88
AL		 1874/* VIA HDMI Implementation */
1875#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
1876#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
1877
3de5ff88
AL		 1878static int patch_via_hdmi(struct hda_codec *codec)
1879{
250e41ac 1880 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 1881}
84eb01be
TI		 1882
1883/*
1884 * patch entries
1885 */
fb79e1e0 1886static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 1887{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
1888{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
1889{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 1890{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 1891{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
1892{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
1893{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
1894{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1895{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1896{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1897{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1898{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 1899{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
1900{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
1901{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
1902{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
1903{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
1904{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
1905{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
1906{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
1907{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
1908{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
1909{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 1910/* 17 is known to be absent */
5d44f927
SW		 1911{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
1912{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
1913{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
1914{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
1915{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
1916{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
1917{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
1918{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
1919{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
1920{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
7ae48b56 1921{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 1922{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
1923{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 1924{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
1925{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
1926{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
1927{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 1928{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1929{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
1930{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
1931{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
1932{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1933{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 1934{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 1935{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 1936{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 1937{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
1938{} /* terminator */
1939};
1940
1941MODULE_ALIAS("snd-hda-codec-id:1002793c");
1942MODULE_ALIAS("snd-hda-codec-id:10027919");
1943MODULE_ALIAS("snd-hda-codec-id:1002791a");
1944MODULE_ALIAS("snd-hda-codec-id:1002aa01");
1945MODULE_ALIAS("snd-hda-codec-id:10951390");
1946MODULE_ALIAS("snd-hda-codec-id:10951392");
1947MODULE_ALIAS("snd-hda-codec-id:10de0002");
1948MODULE_ALIAS("snd-hda-codec-id:10de0003");
1949MODULE_ALIAS("snd-hda-codec-id:10de0005");
1950MODULE_ALIAS("snd-hda-codec-id:10de0006");
1951MODULE_ALIAS("snd-hda-codec-id:10de0007");
1952MODULE_ALIAS("snd-hda-codec-id:10de000a");
1953MODULE_ALIAS("snd-hda-codec-id:10de000b");
1954MODULE_ALIAS("snd-hda-codec-id:10de000c");
1955MODULE_ALIAS("snd-hda-codec-id:10de000d");
1956MODULE_ALIAS("snd-hda-codec-id:10de0010");
1957MODULE_ALIAS("snd-hda-codec-id:10de0011");
1958MODULE_ALIAS("snd-hda-codec-id:10de0012");
1959MODULE_ALIAS("snd-hda-codec-id:10de0013");
1960MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 1961MODULE_ALIAS("snd-hda-codec-id:10de0015");
1962MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 1963MODULE_ALIAS("snd-hda-codec-id:10de0018");
1964MODULE_ALIAS("snd-hda-codec-id:10de0019");
1965MODULE_ALIAS("snd-hda-codec-id:10de001a");
1966MODULE_ALIAS("snd-hda-codec-id:10de001b");
1967MODULE_ALIAS("snd-hda-codec-id:10de001c");
1968MODULE_ALIAS("snd-hda-codec-id:10de0040");
1969MODULE_ALIAS("snd-hda-codec-id:10de0041");
1970MODULE_ALIAS("snd-hda-codec-id:10de0042");
1971MODULE_ALIAS("snd-hda-codec-id:10de0043");
1972MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 1973MODULE_ALIAS("snd-hda-codec-id:10de0051");
84eb01be
TI		 1974MODULE_ALIAS("snd-hda-codec-id:10de0067");
1975MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 1976MODULE_ALIAS("snd-hda-codec-id:11069f80");
1977MODULE_ALIAS("snd-hda-codec-id:11069f81");
1978MODULE_ALIAS("snd-hda-codec-id:11069f84");
1979MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 1980MODULE_ALIAS("snd-hda-codec-id:17e80047");
1981MODULE_ALIAS("snd-hda-codec-id:80860054");
1982MODULE_ALIAS("snd-hda-codec-id:80862801");
1983MODULE_ALIAS("snd-hda-codec-id:80862802");
1984MODULE_ALIAS("snd-hda-codec-id:80862803");
1985MODULE_ALIAS("snd-hda-codec-id:80862804");
1986MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 1987MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 1988MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 1989MODULE_ALIAS("snd-hda-codec-id:80862880");
84eb01be
TI		 1990MODULE_ALIAS("snd-hda-codec-id:808629fb");
1991
1992MODULE_LICENSE("GPL");
1993MODULE_DESCRIPTION("HDMI HD-audio codec");
1994MODULE_ALIAS("snd-hda-codec-intelhdmi");
1995MODULE_ALIAS("snd-hda-codec-nvhdmi");
1996MODULE_ALIAS("snd-hda-codec-atihdmi");
1997
1998static struct hda_codec_preset_list intel_list = {
1999 .preset = snd_hda_preset_hdmi,
2000 .owner = THIS_MODULE,
2001};
2002
2003static int __init patch_hdmi_init(void)
2004{
2005 return snd_hda_add_codec_preset(&intel_list);
2006}
2007
2008static void __exit patch_hdmi_exit(void)
2009{
2010 snd_hda_delete_codec_preset(&intel_list);
2011}
2012
2013module_init(patch_hdmi_init)
2014module_exit(patch_hdmi_exit)
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