]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - sound/pci/hda/patch_hdmi.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: HDA: Fix Oops caused by dereference NULL pointer
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
433968da 37#include <sound/asoundef.h>
d45e6889 38#include <sound/tlv.h>
84eb01be
TI		 39#include "hda_codec.h"
40#include "hda_local.h"
1835a0f9 41#include "hda_jack.h"
84eb01be 42
0ebaa24c
TI		 43static bool static_hdmi_pcm;
44module_param(static_hdmi_pcm, bool, 0644);
45MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
46
384a48d7
SW		 47struct hdmi_spec_per_cvt {
48 hda_nid_t cvt_nid;
49 int assigned;
50 unsigned int channels_min;
51 unsigned int channels_max;
52 u32 rates;
53 u64 formats;
54 unsigned int maxbps;
55};
079d88cc 56
4eea3091
TI		 57/* max. connections to a widget */
58#define HDA_MAX_CONNECTIONS 32
59
384a48d7
SW		 60struct hdmi_spec_per_pin {
61 hda_nid_t pin_nid;
62 int num_mux_nids;
63 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
744626da
WF		 64
65 struct hda_codec *codec;
384a48d7 66 struct hdmi_eld sink_eld;
744626da 67 struct delayed_work work;
92c69e79 68 struct snd_kcontrol *eld_ctl;
c6e8453e 69 int repoll_count;
1a6003b5 70 bool non_pcm;
d45e6889
TI		 71 bool chmap_set; /* channel-map override by ALSA API? */
72 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 73 char pcm_name[8]; /* filled in build_pcm callbacks */
384a48d7 74};
079d88cc 75
384a48d7
SW		 76struct hdmi_spec {
77 int num_cvts;
bce0d2a8
TI		 78 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
79 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 80
384a48d7 81 int num_pins;
bce0d2a8
TI		 82 struct snd_array pins; /* struct hdmi_spec_per_pin */
83 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 84 unsigned int channels_max; /* max over all cvts */
079d88cc 85
4bd038f9 86 struct hdmi_eld temp_eld;
079d88cc 87 /*
384a48d7 88 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 89 */
90 struct hda_multi_out multiout;
d0b1252d 91 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 92};
93
94
95struct hdmi_audio_infoframe {
96 u8 type; /* 0x84 */
97 u8 ver; /* 0x01 */
98 u8 len; /* 0x0a */
99
53d7d69d
WF		 100 u8 checksum;
101
079d88cc
WF		 102 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
103 u8 SS01_SF24;
104 u8 CXT04;
105 u8 CA;
106 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 107};
108
109struct dp_audio_infoframe {
110 u8 type; /* 0x84 */
111 u8 len; /* 0x1b */
112 u8 ver; /* 0x11 << 2 */
113
114 u8 CC02_CT47; /* match with HDMI infoframe from this on */
115 u8 SS01_SF24;
116 u8 CXT04;
117 u8 CA;
118 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 119};
120
2b203dbb
TI		 121union audio_infoframe {
122 struct hdmi_audio_infoframe hdmi;
123 struct dp_audio_infoframe dp;
124 u8 bytes[0];
125};
126
079d88cc
WF		 127/*
128 * CEA speaker placement:
129 *
130 * FLH FCH FRH
131 * FLW FL FLC FC FRC FR FRW
132 *
133 * LFE
134 * TC
135 *
136 * RL RLC RC RRC RR
137 *
138 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
139 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
140 */
141enum cea_speaker_placement {
142 FL = (1 << 0), /* Front Left */
143 FC = (1 << 1), /* Front Center */
144 FR = (1 << 2), /* Front Right */
145 FLC = (1 << 3), /* Front Left Center */
146 FRC = (1 << 4), /* Front Right Center */
147 RL = (1 << 5), /* Rear Left */
148 RC = (1 << 6), /* Rear Center */
149 RR = (1 << 7), /* Rear Right */
150 RLC = (1 << 8), /* Rear Left Center */
151 RRC = (1 << 9), /* Rear Right Center */
152 LFE = (1 << 10), /* Low Frequency Effect */
153 FLW = (1 << 11), /* Front Left Wide */
154 FRW = (1 << 12), /* Front Right Wide */
155 FLH = (1 << 13), /* Front Left High */
156 FCH = (1 << 14), /* Front Center High */
157 FRH = (1 << 15), /* Front Right High */
158 TC = (1 << 16), /* Top Center */
159};
160
161/*
162 * ELD SA bits in the CEA Speaker Allocation data block
163 */
164static int eld_speaker_allocation_bits[] = {
165 [0] = FL | FR,
166 [1] = LFE,
167 [2] = FC,
168 [3] = RL | RR,
169 [4] = RC,
170 [5] = FLC | FRC,
171 [6] = RLC | RRC,
172 /* the following are not defined in ELD yet */
173 [7] = FLW | FRW,
174 [8] = FLH | FRH,
175 [9] = TC,
176 [10] = FCH,
177};
178
179struct cea_channel_speaker_allocation {
180 int ca_index;
181 int speakers[8];
182
183 /* derived values, just for convenience */
184 int channels;
185 int spk_mask;
186};
187
188/*
189 * ALSA sequence is:
190 *
191 * surround40 surround41 surround50 surround51 surround71
192 * ch0 front left = = = =
193 * ch1 front right = = = =
194 * ch2 rear left = = = =
195 * ch3 rear right = = = =
196 * ch4 LFE center center center
197 * ch5 LFE LFE
198 * ch6 side left
199 * ch7 side right
200 *
201 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
202 */
203static int hdmi_channel_mapping[0x32][8] = {
204 /* stereo */
205 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
206 /* 2.1 */
207 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
208 /* Dolby Surround */
209 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
210 /* surround40 */
211 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
212 /* 4ch */
213 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
214 /* surround41 */
9396d317 215 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 216 /* surround50 */
217 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
218 /* surround51 */
219 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
220 /* 7.1 */
221 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
222};
223
224/*
225 * This is an ordered list!
226 *
227 * The preceding ones have better chances to be selected by
53d7d69d 228 * hdmi_channel_allocation().
079d88cc
WF		 229 */
230static struct cea_channel_speaker_allocation channel_allocations[] = {
231/* channel: 7 6 5 4 3 2 1 0 */
232{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
233 /* 2.1 */
234{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
235 /* Dolby Surround */
236{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
237 /* surround40 */
238{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
239 /* surround41 */
240{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
241 /* surround50 */
242{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
243 /* surround51 */
244{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
245 /* 6.1 */
246{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
247 /* surround71 */
248{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
249
250{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
251{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
252{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
253{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
254{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
255{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
256{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
257{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
258{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
259{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
260{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
261{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
262{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
263{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
264{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
265{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
266{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
267{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
268{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
269{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
270{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
271{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
272{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
273{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
274{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
275{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
276{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
277{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
278{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
279{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
280{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
281{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
282{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
283{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
284{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
285{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
286{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
287{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
288{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
289{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
290{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
291};
292
293
294/*
295 * HDMI routines
296 */
297
bce0d2a8
TI		 298#define get_pin(spec, idx) \
299 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
300#define get_cvt(spec, idx) \
301 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
302#define get_pcm_rec(spec, idx) \
303 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
304
384a48d7 305static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 306{
384a48d7 307 int pin_idx;
079d88cc 308
384a48d7 309 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 310 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 311 return pin_idx;
079d88cc 312
384a48d7
SW		 313 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
314 return -EINVAL;
315}
316
317static int hinfo_to_pin_index(struct hdmi_spec *spec,
318 struct hda_pcm_stream *hinfo)
319{
320 int pin_idx;
321
322 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 323 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 324 return pin_idx;
325
326 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
327 return -EINVAL;
328}
329
330static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
331{
332 int cvt_idx;
333
334 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 335 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 336 return cvt_idx;
337
338 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 339 return -EINVAL;
340}
341
14bc52b8
PLB		 342static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
343 struct snd_ctl_elem_info *uinfo)
344{
345 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 346 struct hdmi_spec *spec = codec->spec;
347 struct hdmi_eld *eld;
14bc52b8
PLB		 348 int pin_idx;
349
14bc52b8
PLB		 350 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
351
352 pin_idx = kcontrol->private_value;
bce0d2a8 353 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 354
4bd038f9 355 mutex_lock(&eld->lock);
68e03de9 356 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
4bd038f9 357 mutex_unlock(&eld->lock);
14bc52b8
PLB		 358
359 return 0;
360}
361
362static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
363 struct snd_ctl_elem_value *ucontrol)
364{
365 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 366 struct hdmi_spec *spec = codec->spec;
367 struct hdmi_eld *eld;
14bc52b8
PLB		 368 int pin_idx;
369
14bc52b8 370 pin_idx = kcontrol->private_value;
bce0d2a8 371 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 372
4bd038f9 373 mutex_lock(&eld->lock);
68e03de9 374 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
4bd038f9 375 mutex_unlock(&eld->lock);
68e03de9
DH		 376 snd_BUG();
377 return -EINVAL;
378 }
379
380 memset(ucontrol->value.bytes.data, 0,
381 ARRAY_SIZE(ucontrol->value.bytes.data));
382 if (eld->eld_valid)
383 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
384 eld->eld_size);
4bd038f9 385 mutex_unlock(&eld->lock);
14bc52b8
PLB		 386
387 return 0;
388}
389
390static struct snd_kcontrol_new eld_bytes_ctl = {
391 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
392 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
393 .name = "ELD",
394 .info = hdmi_eld_ctl_info,
395 .get = hdmi_eld_ctl_get,
396};
397
398static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
399 int device)
400{
401 struct snd_kcontrol *kctl;
402 struct hdmi_spec *spec = codec->spec;
403 int err;
404
405 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
406 if (!kctl)
407 return -ENOMEM;
408 kctl->private_value = pin_idx;
409 kctl->id.device = device;
410
bce0d2a8 411 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 412 if (err < 0)
413 return err;
414
bce0d2a8 415 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 416 return 0;
417}
418
079d88cc
WF		 419#ifdef BE_PARANOID
420static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
421 int *packet_index, int *byte_index)
422{
423 int val;
424
425 val = snd_hda_codec_read(codec, pin_nid, 0,
426 AC_VERB_GET_HDMI_DIP_INDEX, 0);
427
428 *packet_index = val >> 5;
429 *byte_index = val & 0x1f;
430}
431#endif
432
433static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
434 int packet_index, int byte_index)
435{
436 int val;
437
438 val = (packet_index << 5) | (byte_index & 0x1f);
439
440 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
441}
442
443static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
444 unsigned char val)
445{
446 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
447}
448
384a48d7 449static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 450{
451 /* Unmute */
452 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
453 snd_hda_codec_write(codec, pin_nid, 0,
454 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 455 /* Enable pin out: some machines with GM965 gets broken output when
456 * the pin is disabled or changed while using with HDMI
457 */
079d88cc 458 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 459 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 460}
461
384a48d7 462static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 463{
384a48d7 464 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 465 AC_VERB_GET_CVT_CHAN_COUNT, 0);
466}
467
468static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 469 hda_nid_t cvt_nid, int chs)
079d88cc 470{
384a48d7
SW		 471 if (chs != hdmi_get_channel_count(codec, cvt_nid))
472 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 473 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
474}
475
476
477/*
478 * Channel mapping routines
479 */
480
481/*
482 * Compute derived values in channel_allocations[].
483 */
484static void init_channel_allocations(void)
485{
486 int i, j;
487 struct cea_channel_speaker_allocation *p;
488
489 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
490 p = channel_allocations + i;
491 p->channels = 0;
492 p->spk_mask = 0;
493 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
494 if (p->speakers[j]) {
495 p->channels++;
496 p->spk_mask |= p->speakers[j];
497 }
498 }
499}
500
72357c78
WX		 501static int get_channel_allocation_order(int ca)
502{
503 int i;
504
505 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
506 if (channel_allocations[i].ca_index == ca)
507 break;
508 }
509 return i;
510}
511
079d88cc
WF		 512/*
513 * The transformation takes two steps:
514 *
515 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
516 * spk_mask => (channel_allocations[]) => ai->CA
517 *
518 * TODO: it could select the wrong CA from multiple candidates.
519*/
384a48d7 520static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 521{
079d88cc 522 int i;
53d7d69d 523 int ca = 0;
079d88cc 524 int spk_mask = 0;
079d88cc
WF		 525 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
526
527 /*
528 * CA defaults to 0 for basic stereo audio
529 */
530 if (channels <= 2)
531 return 0;
532
079d88cc
WF		 533 /*
534 * expand ELD's speaker allocation mask
535 *
536 * ELD tells the speaker mask in a compact(paired) form,
537 * expand ELD's notions to match the ones used by Audio InfoFrame.
538 */
539 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 540 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 541 spk_mask |= eld_speaker_allocation_bits[i];
542 }
543
544 /* search for the first working match in the CA table */
545 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
546 if (channels == channel_allocations[i].channels &&
547 (spk_mask & channel_allocations[i].spk_mask) ==
548 channel_allocations[i].spk_mask) {
53d7d69d 549 ca = channel_allocations[i].ca_index;
079d88cc
WF		 550 break;
551 }
552 }
553
1613d6b4 554 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 555 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 556 ca, channels, buf);
079d88cc 557
53d7d69d 558 return ca;
079d88cc
WF		 559}
560
561static void hdmi_debug_channel_mapping(struct hda_codec *codec,
562 hda_nid_t pin_nid)
563{
564#ifdef CONFIG_SND_DEBUG_VERBOSE
565 int i;
566 int slot;
567
568 for (i = 0; i < 8; i++) {
569 slot = snd_hda_codec_read(codec, pin_nid, 0,
570 AC_VERB_GET_HDMI_CHAN_SLOT, i);
571 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
572 slot >> 4, slot & 0xf);
573 }
574#endif
575}
576
577
d45e6889 578static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 579 hda_nid_t pin_nid,
433968da 580 bool non_pcm,
53d7d69d 581 int ca)
079d88cc
WF		 582{
583 int i;
079d88cc 584 int err;
72357c78 585 int order;
433968da 586 int non_pcm_mapping[8];
079d88cc 587
72357c78 588 order = get_channel_allocation_order(ca);
433968da 589
079d88cc 590 if (hdmi_channel_mapping[ca][1] == 0) {
72357c78 591 for (i = 0; i < channel_allocations[order].channels; i++)
079d88cc
WF		 592 hdmi_channel_mapping[ca][i] = i | (i << 4);
593 for (; i < 8; i++)
594 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
595 }
596
433968da
WX		 597 if (non_pcm) {
598 for (i = 0; i < channel_allocations[order].channels; i++)
599 non_pcm_mapping[i] = i | (i << 4);
600 for (; i < 8; i++)
601 non_pcm_mapping[i] = 0xf | (i << 4);
602 }
603
079d88cc
WF		 604 for (i = 0; i < 8; i++) {
605 err = snd_hda_codec_write(codec, pin_nid, 0,
606 AC_VERB_SET_HDMI_CHAN_SLOT,
433968da 607 non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]);
079d88cc 608 if (err) {
2abbf439
WF		 609 snd_printdd(KERN_NOTICE
610 "HDMI: channel mapping failed\n");
079d88cc
WF		 611 break;
612 }
613 }
614
615 hdmi_debug_channel_mapping(codec, pin_nid);
616}
617
d45e6889
TI		 618struct channel_map_table {
619 unsigned char map; /* ALSA API channel map position */
620 unsigned char cea_slot; /* CEA slot value */
621 int spk_mask; /* speaker position bit mask */
622};
623
624static struct channel_map_table map_tables[] = {
625 { SNDRV_CHMAP_FL, 0x00, FL },
626 { SNDRV_CHMAP_FR, 0x01, FR },
627 { SNDRV_CHMAP_RL, 0x04, RL },
628 { SNDRV_CHMAP_RR, 0x05, RR },
629 { SNDRV_CHMAP_LFE, 0x02, LFE },
630 { SNDRV_CHMAP_FC, 0x03, FC },
631 { SNDRV_CHMAP_RLC, 0x06, RLC },
632 { SNDRV_CHMAP_RRC, 0x07, RRC },
633 {} /* terminator */
634};
635
636/* from ALSA API channel position to speaker bit mask */
637static int to_spk_mask(unsigned char c)
638{
639 struct channel_map_table *t = map_tables;
640 for (; t->map; t++) {
641 if (t->map == c)
642 return t->spk_mask;
643 }
644 return 0;
645}
646
647/* from ALSA API channel position to CEA slot */
648static int to_cea_slot(unsigned char c)
649{
650 struct channel_map_table *t = map_tables;
651 for (; t->map; t++) {
652 if (t->map == c)
653 return t->cea_slot;
654 }
655 return 0x0f;
656}
657
658/* from CEA slot to ALSA API channel position */
659static int from_cea_slot(unsigned char c)
660{
661 struct channel_map_table *t = map_tables;
662 for (; t->map; t++) {
663 if (t->cea_slot == c)
664 return t->map;
665 }
666 return 0;
667}
668
669/* from speaker bit mask to ALSA API channel position */
670static int spk_to_chmap(int spk)
671{
672 struct channel_map_table *t = map_tables;
673 for (; t->map; t++) {
674 if (t->spk_mask == spk)
675 return t->map;
676 }
677 return 0;
678}
679
680/* get the CA index corresponding to the given ALSA API channel map */
681static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
682{
683 int i, spks = 0, spk_mask = 0;
684
685 for (i = 0; i < chs; i++) {
686 int mask = to_spk_mask(map[i]);
687 if (mask) {
688 spk_mask |= mask;
689 spks++;
690 }
691 }
692
693 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
694 if ((chs == channel_allocations[i].channels ||
695 spks == channel_allocations[i].channels) &&
696 (spk_mask & channel_allocations[i].spk_mask) ==
697 channel_allocations[i].spk_mask)
698 return channel_allocations[i].ca_index;
699 }
700 return -1;
701}
702
703/* set up the channel slots for the given ALSA API channel map */
704static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
705 hda_nid_t pin_nid,
706 int chs, unsigned char *map)
707{
708 int i;
709 for (i = 0; i < 8; i++) {
710 int val, err;
711 if (i < chs)
712 val = to_cea_slot(map[i]);
713 else
714 val = 0xf;
715 val |= (i << 4);
716 err = snd_hda_codec_write(codec, pin_nid, 0,
717 AC_VERB_SET_HDMI_CHAN_SLOT, val);
718 if (err)
719 return -EINVAL;
720 }
721 return 0;
722}
723
724/* store ALSA API channel map from the current default map */
725static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
726{
727 int i;
728 for (i = 0; i < 8; i++) {
729 if (i < channel_allocations[ca].channels)
730 map[i] = from_cea_slot((hdmi_channel_mapping[ca][i] >> 4) & 0x0f);
731 else
732 map[i] = 0;
733 }
734}
735
736static void hdmi_setup_channel_mapping(struct hda_codec *codec,
737 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 738 int channels, unsigned char *map,
739 bool chmap_set)
d45e6889 740{
20608731 741 if (!non_pcm && chmap_set) {
d45e6889
TI		 742 hdmi_manual_setup_channel_mapping(codec, pin_nid,
743 channels, map);
744 } else {
745 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
746 hdmi_setup_fake_chmap(map, ca);
747 }
748}
079d88cc
WF		 749
750/*
751 * Audio InfoFrame routines
752 */
753
754/*
755 * Enable Audio InfoFrame Transmission
756 */
757static void hdmi_start_infoframe_trans(struct hda_codec *codec,
758 hda_nid_t pin_nid)
759{
760 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
761 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
762 AC_DIPXMIT_BEST);
763}
764
765/*
766 * Disable Audio InfoFrame Transmission
767 */
768static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
769 hda_nid_t pin_nid)
770{
771 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
772 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
773 AC_DIPXMIT_DISABLE);
774}
775
776static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
777{
778#ifdef CONFIG_SND_DEBUG_VERBOSE
779 int i;
780 int size;
781
782 size = snd_hdmi_get_eld_size(codec, pin_nid);
783 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
784
785 for (i = 0; i < 8; i++) {
786 size = snd_hda_codec_read(codec, pin_nid, 0,
787 AC_VERB_GET_HDMI_DIP_SIZE, i);
788 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
789 }
790#endif
791}
792
793static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
794{
795#ifdef BE_PARANOID
796 int i, j;
797 int size;
798 int pi, bi;
799 for (i = 0; i < 8; i++) {
800 size = snd_hda_codec_read(codec, pin_nid, 0,
801 AC_VERB_GET_HDMI_DIP_SIZE, i);
802 if (size == 0)
803 continue;
804
805 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
806 for (j = 1; j < 1000; j++) {
807 hdmi_write_dip_byte(codec, pin_nid, 0x0);
808 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
809 if (pi != i)
810 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
811 bi, pi, i);
812 if (bi == 0) /* byte index wrapped around */
813 break;
814 }
815 snd_printd(KERN_INFO
816 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
817 i, size, j);
818 }
819#endif
820}
821
53d7d69d 822static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 823{
53d7d69d 824 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 825 u8 sum = 0;
826 int i;
827
53d7d69d 828 hdmi_ai->checksum = 0;
079d88cc 829
53d7d69d 830 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 831 sum += bytes[i];
832
53d7d69d 833 hdmi_ai->checksum = -sum;
079d88cc
WF		 834}
835
836static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
837 hda_nid_t pin_nid,
53d7d69d 838 u8 *dip, int size)
079d88cc 839{
079d88cc
WF		 840 int i;
841
842 hdmi_debug_dip_size(codec, pin_nid);
843 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
844
079d88cc 845 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 846 for (i = 0; i < size; i++)
847 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 848}
849
850static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 851 u8 *dip, int size)
079d88cc 852{
079d88cc
WF		 853 u8 val;
854 int i;
855
856 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
857 != AC_DIPXMIT_BEST)
858 return false;
859
860 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 861 for (i = 0; i < size; i++) {
079d88cc
WF		 862 val = snd_hda_codec_read(codec, pin_nid, 0,
863 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 864 if (val != dip[i])
079d88cc
WF		 865 return false;
866 }
867
868 return true;
869}
870
384a48d7 871static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
1a6003b5
TI		 872 bool non_pcm,
873 struct snd_pcm_substream *substream)
079d88cc
WF		 874{
875 struct hdmi_spec *spec = codec->spec;
bce0d2a8 876 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 877 hda_nid_t pin_nid = per_pin->pin_nid;
53d7d69d 878 int channels = substream->runtime->channels;
384a48d7 879 struct hdmi_eld *eld;
53d7d69d 880 int ca;
2b203dbb 881 union audio_infoframe ai;
079d88cc 882
bce0d2a8 883 eld = &per_pin->sink_eld;
384a48d7
SW		 884 if (!eld->monitor_present)
885 return;
079d88cc 886
d45e6889
TI		 887 if (!non_pcm && per_pin->chmap_set)
888 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
889 else
890 ca = hdmi_channel_allocation(eld, channels);
891 if (ca < 0)
892 ca = 0;
384a48d7
SW		 893
894 memset(&ai, 0, sizeof(ai));
1613d6b4 895 if (eld->info.conn_type == 0) { /* HDMI */
384a48d7
SW		 896 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
897
898 hdmi_ai->type = 0x84;
899 hdmi_ai->ver = 0x01;
900 hdmi_ai->len = 0x0a;
901 hdmi_ai->CC02_CT47 = channels - 1;
902 hdmi_ai->CA = ca;
903 hdmi_checksum_audio_infoframe(hdmi_ai);
1613d6b4 904 } else if (eld->info.conn_type == 1) { /* DisplayPort */
384a48d7
SW		 905 struct dp_audio_infoframe *dp_ai = &ai.dp;
906
907 dp_ai->type = 0x84;
908 dp_ai->len = 0x1b;
909 dp_ai->ver = 0x11 << 2;
910 dp_ai->CC02_CT47 = channels - 1;
911 dp_ai->CA = ca;
912 } else {
913 snd_printd("HDMI: unknown connection type at pin %d\n",
914 pin_nid);
915 return;
916 }
53d7d69d 917
384a48d7
SW		 918 /*
919 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
920 * sizeof(*dp_ai) to avoid partial match/update problems when
921 * the user switches between HDMI/DP monitors.
922 */
923 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
924 sizeof(ai))) {
925 snd_printdd("hdmi_setup_audio_infoframe: "
926 "pin=%d channels=%d\n",
927 pin_nid,
928 channels);
d45e6889 929 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
20608731
AH		 930 channels, per_pin->chmap,
931 per_pin->chmap_set);
384a48d7
SW		 932 hdmi_stop_infoframe_trans(codec, pin_nid);
933 hdmi_fill_audio_infoframe(codec, pin_nid,
934 ai.bytes, sizeof(ai));
935 hdmi_start_infoframe_trans(codec, pin_nid);
2d7e887c
WX		 936 } else {
937 /* For non-pcm audio switch, setup new channel mapping
938 * accordingly */
1a6003b5 939 if (per_pin->non_pcm != non_pcm)
d45e6889 940 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
20608731
AH		 941 channels, per_pin->chmap,
942 per_pin->chmap_set);
079d88cc 943 }
433968da 944
1a6003b5 945 per_pin->non_pcm = non_pcm;
079d88cc
WF		 946}
947
948
949/*
950 * Unsolicited events
951 */
952
c6e8453e 953static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 954
079d88cc
WF		 955static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
956{
957 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 958 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
959 int pin_nid;
384a48d7 960 int pin_idx;
3a93897e
TI		 961 struct hda_jack_tbl *jack;
962
963 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
964 if (!jack)
965 return;
966 pin_nid = jack->nid;
967 jack->jack_dirty = 1;
079d88cc 968
fae3d88a 969 _snd_printd(SND_PR_VERBOSE,
384a48d7 970 "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
fae3d88a
FW		 971 codec->addr, pin_nid,
972 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 973
384a48d7
SW		 974 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
975 if (pin_idx < 0)
079d88cc
WF		 976 return;
977
bce0d2a8 978 hdmi_present_sense(get_pin(spec, pin_idx), 1);
01a61e12 979 snd_hda_jack_report_sync(codec);
079d88cc
WF		 980}
981
982static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
983{
984 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
985 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
986 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
987 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
988
989 printk(KERN_INFO
e9ea8e8f 990 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 991 codec->addr,
079d88cc
WF		 992 tag,
993 subtag,
994 cp_state,
995 cp_ready);
996
997 /* TODO */
998 if (cp_state)
999 ;
1000 if (cp_ready)
1001 ;
1002}
1003
1004
1005static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1006{
079d88cc
WF		 1007 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1008 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1009
3a93897e 1010 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 1011 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
1012 return;
1013 }
1014
1015 if (subtag == 0)
1016 hdmi_intrinsic_event(codec, res);
1017 else
1018 hdmi_non_intrinsic_event(codec, res);
1019}
1020
83f26ad2
DH		 1021static void haswell_verify_pin_D0(struct hda_codec *codec, hda_nid_t nid)
1022{
1023 int pwr, lamp, ramp;
1024
1025 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1026 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1027 if (pwr != AC_PWRST_D0) {
1028 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1029 AC_PWRST_D0);
1030 msleep(40);
1031 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1032 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1033 snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1034 }
1035
1036 lamp = snd_hda_codec_read(codec, nid, 0,
1037 AC_VERB_GET_AMP_GAIN_MUTE,
1038 AC_AMP_GET_LEFT | AC_AMP_GET_OUTPUT);
1039 ramp = snd_hda_codec_read(codec, nid, 0,
1040 AC_VERB_GET_AMP_GAIN_MUTE,
1041 AC_AMP_GET_RIGHT | AC_AMP_GET_OUTPUT);
1042 if (lamp != ramp) {
1043 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_AMP_GAIN_MUTE,
1044 AC_AMP_SET_RIGHT | AC_AMP_SET_OUTPUT | lamp);
1045
1046 lamp = snd_hda_codec_read(codec, nid, 0,
1047 AC_VERB_GET_AMP_GAIN_MUTE,
1048 AC_AMP_GET_LEFT | AC_AMP_GET_OUTPUT);
1049 ramp = snd_hda_codec_read(codec, nid, 0,
1050 AC_VERB_GET_AMP_GAIN_MUTE,
1051 AC_AMP_GET_RIGHT | AC_AMP_GET_OUTPUT);
1052 snd_printd("Haswell HDMI audio: Mute after set on pin 0x%x: [0x%x 0x%x]\n", nid, lamp, ramp);
1053 }
1054}
1055
079d88cc
WF		 1056/*
1057 * Callbacks
1058 */
1059
92f10b3f
TI		 1060/* HBR should be Non-PCM, 8 channels */
1061#define is_hbr_format(format) \
1062 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1063
384a48d7
SW		 1064static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1065 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 1066{
ea87d1c4
AH		 1067 int pinctl;
1068 int new_pinctl = 0;
ea87d1c4 1069
83f26ad2
DH		 1070 if (codec->vendor_id == 0x80862807)
1071 haswell_verify_pin_D0(codec, pin_nid);
1072
384a48d7
SW		 1073 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1074 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1075 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1076
1077 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 1078 if (is_hbr_format(format))
ea87d1c4
AH		 1079 new_pinctl |= AC_PINCTL_EPT_HBR;
1080 else
1081 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1082
1083 snd_printdd("hdmi_setup_stream: "
1084 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1085 pin_nid,
ea87d1c4
AH		 1086 pinctl == new_pinctl ? "" : "new-",
1087 new_pinctl);
1088
1089 if (pinctl != new_pinctl)
384a48d7 1090 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1091 AC_VERB_SET_PIN_WIDGET_CONTROL,
1092 new_pinctl);
ea87d1c4 1093
384a48d7 1094 }
92f10b3f 1095 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 1096 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
1097 return -EINVAL;
1098 }
079d88cc 1099
384a48d7 1100 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1101 return 0;
079d88cc
WF		 1102}
1103
bbbe3390
TI		 1104/*
1105 * HDA PCM callbacks
1106 */
1107static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1108 struct hda_codec *codec,
1109 struct snd_pcm_substream *substream)
1110{
1111 struct hdmi_spec *spec = codec->spec;
639cef0e 1112 struct snd_pcm_runtime *runtime = substream->runtime;
384a48d7
SW		 1113 int pin_idx, cvt_idx, mux_idx = 0;
1114 struct hdmi_spec_per_pin *per_pin;
1115 struct hdmi_eld *eld;
1116 struct hdmi_spec_per_cvt *per_cvt = NULL;
bbbe3390 1117
384a48d7
SW		 1118 /* Validate hinfo */
1119 pin_idx = hinfo_to_pin_index(spec, hinfo);
1120 if (snd_BUG_ON(pin_idx < 0))
bbbe3390 1121 return -EINVAL;
bce0d2a8 1122 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1123 eld = &per_pin->sink_eld;
1124
1125 /* Dynamically assign converter to stream */
1126 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1127 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1128
384a48d7
SW		 1129 /* Must not already be assigned */
1130 if (per_cvt->assigned)
1131 continue;
1132 /* Must be in pin's mux's list of converters */
1133 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1134 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1135 break;
1136 /* Not in mux list */
1137 if (mux_idx == per_pin->num_mux_nids)
1138 continue;
1139 break;
1140 }
1141 /* No free converters */
1142 if (cvt_idx == spec->num_cvts)
1143 return -ENODEV;
1144
1145 /* Claim converter */
1146 per_cvt->assigned = 1;
1147 hinfo->nid = per_cvt->cvt_nid;
1148
1149 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1150 AC_VERB_SET_CONNECT_SEL,
1151 mux_idx);
384a48d7 1152 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1153
2def8172 1154 /* Initially set the converter's capabilities */
384a48d7
SW		 1155 hinfo->channels_min = per_cvt->channels_min;
1156 hinfo->channels_max = per_cvt->channels_max;
1157 hinfo->rates = per_cvt->rates;
1158 hinfo->formats = per_cvt->formats;
1159 hinfo->maxbps = per_cvt->maxbps;
2def8172 1160
384a48d7 1161 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1162 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1163 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1164 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1165 !hinfo->rates || !hinfo->formats) {
1166 per_cvt->assigned = 0;
1167 hinfo->nid = 0;
1168 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1169 return -ENODEV;
2ad779b7 1170 }
bbbe3390 1171 }
2def8172
SW		 1172
1173 /* Store the updated parameters */
639cef0e
TI		 1174 runtime->hw.channels_min = hinfo->channels_min;
1175 runtime->hw.channels_max = hinfo->channels_max;
1176 runtime->hw.formats = hinfo->formats;
1177 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1178
1179 snd_pcm_hw_constraint_step(substream->runtime, 0,
1180 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1181 return 0;
1182}
1183
079d88cc
WF		 1184/*
1185 * HDA/HDMI auto parsing
1186 */
384a48d7 1187static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1188{
1189 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1190 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1191 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1192
1193 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1194 snd_printk(KERN_WARNING
1195 "HDMI: pin %d wcaps %#x "
1196 "does not support connection list\n",
1197 pin_nid, get_wcaps(codec, pin_nid));
1198 return -EINVAL;
1199 }
1200
384a48d7
SW		 1201 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1202 per_pin->mux_nids,
1203 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1204
1205 return 0;
1206}
1207
c6e8453e 1208static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1209{
744626da 1210 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1211 struct hdmi_spec *spec = codec->spec;
1212 struct hdmi_eld *eld = &spec->temp_eld;
1213 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1214 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1215 /*
1216 * Always execute a GetPinSense verb here, even when called from
1217 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1218 * response's PD bit is not the real PD value, but indicates that
1219 * the real PD value changed. An older version of the HD-audio
1220 * specification worked this way. Hence, we just ignore the data in
1221 * the unsolicited response to avoid custom WARs.
1222 */
079d88cc 1223 int present = snd_hda_pin_sense(codec, pin_nid);
4bd038f9
DH		 1224 bool update_eld = false;
1225 bool eld_changed = false;
079d88cc 1226
4bd038f9
DH		 1227 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1228 if (pin_eld->monitor_present)
1229 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1230 else
1231 eld->eld_valid = false;
079d88cc 1232
fae3d88a 1233 _snd_printd(SND_PR_VERBOSE,
384a48d7 1234 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1235 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1236
4bd038f9 1237 if (eld->eld_valid) {
1613d6b4
DH		 1238 if (snd_hdmi_get_eld(codec, pin_nid, eld->eld_buffer,
1239 &eld->eld_size) < 0)
4bd038f9 1240 eld->eld_valid = false;
1613d6b4
DH		 1241 else {
1242 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1243 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1244 eld->eld_size) < 0)
4bd038f9 1245 eld->eld_valid = false;
1613d6b4
DH		 1246 }
1247
4bd038f9 1248 if (eld->eld_valid) {
1613d6b4 1249 snd_hdmi_show_eld(&eld->info);
4bd038f9 1250 update_eld = true;
1613d6b4 1251 }
c6e8453e 1252 else if (repoll) {
744626da
WF		 1253 queue_delayed_work(codec->bus->workq,
1254 &per_pin->work,
1255 msecs_to_jiffies(300));
4bd038f9 1256 return;
744626da
WF		 1257 }
1258 }
4bd038f9
DH		 1259
1260 mutex_lock(&pin_eld->lock);
92c69e79 1261 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1262 update_eld = true;
92c69e79
DH		 1263 eld_changed = true;
1264 }
4bd038f9
DH		 1265 if (update_eld) {
1266 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1267 eld_changed = pin_eld->eld_size != eld->eld_size ||
1268 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1269 eld->eld_size) != 0;
1270 if (eld_changed)
1271 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1272 eld->eld_size);
1273 pin_eld->eld_size = eld->eld_size;
1274 pin_eld->info = eld->info;
1275 }
1276 mutex_unlock(&pin_eld->lock);
92c69e79
DH		 1277
1278 if (eld_changed)
1279 snd_ctl_notify(codec->bus->card,
1280 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1281 &per_pin->eld_ctl->id);
079d88cc
WF		 1282}
1283
744626da
WF		 1284static void hdmi_repoll_eld(struct work_struct *work)
1285{
1286 struct hdmi_spec_per_pin *per_pin =
1287 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1288
c6e8453e
WF		 1289 if (per_pin->repoll_count++ > 6)
1290 per_pin->repoll_count = 0;
1291
1292 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1293}
1294
c88d4e84
TI		 1295static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1296 hda_nid_t nid);
1297
079d88cc
WF		 1298static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1299{
1300 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1301 unsigned int caps, config;
1302 int pin_idx;
1303 struct hdmi_spec_per_pin *per_pin;
07acecc1 1304 int err;
079d88cc 1305
efc2f8de 1306 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1307 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1308 return 0;
1309
efc2f8de 1310 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1311 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1312 return 0;
1313
c88d4e84
TI		 1314 if (codec->vendor_id == 0x80862807)
1315 intel_haswell_fixup_connect_list(codec, pin_nid);
1316
384a48d7 1317 pin_idx = spec->num_pins;
bce0d2a8
TI		 1318 per_pin = snd_array_new(&spec->pins);
1319 if (!per_pin)
1320 return -ENOMEM;
384a48d7
SW		 1321
1322 per_pin->pin_nid = pin_nid;
1a6003b5 1323 per_pin->non_pcm = false;
079d88cc 1324
384a48d7
SW		 1325 err = hdmi_read_pin_conn(codec, pin_idx);
1326 if (err < 0)
1327 return err;
079d88cc 1328
079d88cc
WF		 1329 spec->num_pins++;
1330
384a48d7 1331 return 0;
079d88cc
WF		 1332}
1333
384a48d7 1334static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1335{
1336 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1337 struct hdmi_spec_per_cvt *per_cvt;
1338 unsigned int chans;
1339 int err;
079d88cc 1340
384a48d7
SW		 1341 chans = get_wcaps(codec, cvt_nid);
1342 chans = get_wcaps_channels(chans);
1343
bce0d2a8
TI		 1344 per_cvt = snd_array_new(&spec->cvts);
1345 if (!per_cvt)
1346 return -ENOMEM;
384a48d7
SW		 1347
1348 per_cvt->cvt_nid = cvt_nid;
1349 per_cvt->channels_min = 2;
d45e6889 1350 if (chans <= 16) {
384a48d7 1351 per_cvt->channels_max = chans;
d45e6889
TI		 1352 if (chans > spec->channels_max)
1353 spec->channels_max = chans;
1354 }
384a48d7
SW		 1355
1356 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1357 &per_cvt->rates,
1358 &per_cvt->formats,
1359 &per_cvt->maxbps);
1360 if (err < 0)
1361 return err;
1362
bce0d2a8
TI		 1363 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1364 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1365 spec->num_cvts++;
079d88cc
WF		 1366
1367 return 0;
1368}
1369
1370static int hdmi_parse_codec(struct hda_codec *codec)
1371{
1372 hda_nid_t nid;
1373 int i, nodes;
1374
1375 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1376 if (!nid || nodes < 0) {
1377 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1378 return -EINVAL;
1379 }
1380
1381 for (i = 0; i < nodes; i++, nid++) {
1382 unsigned int caps;
1383 unsigned int type;
1384
efc2f8de 1385 caps = get_wcaps(codec, nid);
079d88cc
WF		 1386 type = get_wcaps_type(caps);
1387
1388 if (!(caps & AC_WCAP_DIGITAL))
1389 continue;
1390
1391 switch (type) {
1392 case AC_WID_AUD_OUT:
384a48d7 1393 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1394 break;
1395 case AC_WID_PIN:
3eaead57 1396 hdmi_add_pin(codec, nid);
079d88cc
WF		 1397 break;
1398 }
1399 }
1400
c9adeefd
DH		 1401#ifdef CONFIG_PM
1402 /* We're seeing some problems with unsolicited hot plug events on
1403 * PantherPoint after S3, if this is not enabled */
1404 if (codec->vendor_id == 0x80862806)
1405 codec->bus->power_keep_link_on = 1;
079d88cc
WF		 1406 /*
1407 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1408 * can be lost and presence sense verb will become inaccurate if the
1409 * HDA link is powered off at hot plug or hw initialization time.
1410 */
c9adeefd 1411 else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
079d88cc
WF		 1412 AC_PWRST_EPSS))
1413 codec->bus->power_keep_link_on = 1;
1414#endif
1415
1416 return 0;
1417}
1418
84eb01be
TI		 1419/*
1420 */
1a6003b5
TI		 1421static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1422{
1423 struct hda_spdif_out *spdif;
1424 bool non_pcm;
1425
1426 mutex_lock(&codec->spdif_mutex);
1427 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1428 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1429 mutex_unlock(&codec->spdif_mutex);
1430 return non_pcm;
1431}
1432
1433
84eb01be
TI		 1434/*
1435 * HDMI callbacks
1436 */
1437
1438static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1439 struct hda_codec *codec,
1440 unsigned int stream_tag,
1441 unsigned int format,
1442 struct snd_pcm_substream *substream)
1443{
384a48d7
SW		 1444 hda_nid_t cvt_nid = hinfo->nid;
1445 struct hdmi_spec *spec = codec->spec;
1446 int pin_idx = hinfo_to_pin_index(spec, hinfo);
bce0d2a8 1447 hda_nid_t pin_nid = get_pin(spec, pin_idx)->pin_nid;
1a6003b5
TI		 1448 bool non_pcm;
1449
1450 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
384a48d7
SW		 1451
1452 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
84eb01be 1453
1a6003b5 1454 hdmi_setup_audio_infoframe(codec, pin_idx, non_pcm, substream);
84eb01be 1455
384a48d7 1456 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1457}
1458
8dfaa573
TI		 1459static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1460 struct hda_codec *codec,
1461 struct snd_pcm_substream *substream)
1462{
1463 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1464 return 0;
1465}
1466
f2ad24fa
TI		 1467static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1468 struct hda_codec *codec,
1469 struct snd_pcm_substream *substream)
384a48d7
SW		 1470{
1471 struct hdmi_spec *spec = codec->spec;
1472 int cvt_idx, pin_idx;
1473 struct hdmi_spec_per_cvt *per_cvt;
1474 struct hdmi_spec_per_pin *per_pin;
384a48d7 1475
384a48d7
SW		 1476 if (hinfo->nid) {
1477 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1478 if (snd_BUG_ON(cvt_idx < 0))
1479 return -EINVAL;
bce0d2a8 1480 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1481
1482 snd_BUG_ON(!per_cvt->assigned);
1483 per_cvt->assigned = 0;
1484 hinfo->nid = 0;
1485
1486 pin_idx = hinfo_to_pin_index(spec, hinfo);
1487 if (snd_BUG_ON(pin_idx < 0))
1488 return -EINVAL;
bce0d2a8 1489 per_pin = get_pin(spec, pin_idx);
384a48d7 1490
384a48d7 1491 snd_hda_spdif_ctls_unassign(codec, pin_idx);
d45e6889
TI		 1492 per_pin->chmap_set = false;
1493 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
384a48d7 1494 }
d45e6889 1495
384a48d7
SW		 1496 return 0;
1497}
1498
1499static const struct hda_pcm_ops generic_ops = {
1500 .open = hdmi_pcm_open,
f2ad24fa 1501 .close = hdmi_pcm_close,
384a48d7 1502 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1503 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1504};
1505
d45e6889
TI		 1506/*
1507 * ALSA API channel-map control callbacks
1508 */
1509static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1510 struct snd_ctl_elem_info *uinfo)
1511{
1512 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1513 struct hda_codec *codec = info->private_data;
1514 struct hdmi_spec *spec = codec->spec;
1515 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1516 uinfo->count = spec->channels_max;
1517 uinfo->value.integer.min = 0;
1518 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1519 return 0;
1520}
1521
1522static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1523 unsigned int size, unsigned int __user *tlv)
1524{
1525 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1526 struct hda_codec *codec = info->private_data;
1527 struct hdmi_spec *spec = codec->spec;
1528 const unsigned int valid_mask =
1529 FL | FR | RL | RR | LFE | FC | RLC | RRC;
1530 unsigned int __user *dst;
1531 int chs, count = 0;
1532
1533 if (size < 8)
1534 return -ENOMEM;
1535 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1536 return -EFAULT;
1537 size -= 8;
1538 dst = tlv + 2;
498dab3a 1539 for (chs = 2; chs <= spec->channels_max; chs++) {
d45e6889
TI		 1540 int i, c;
1541 struct cea_channel_speaker_allocation *cap;
1542 cap = channel_allocations;
1543 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1544 int chs_bytes = chs * 4;
1545 if (cap->channels != chs)
1546 continue;
1547 if (cap->spk_mask & ~valid_mask)
1548 continue;
1549 if (size < 8)
1550 return -ENOMEM;
1551 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
1552 put_user(chs_bytes, dst + 1))
1553 return -EFAULT;
1554 dst += 2;
1555 size -= 8;
1556 count += 8;
1557 if (size < chs_bytes)
1558 return -ENOMEM;
1559 size -= chs_bytes;
1560 count += chs_bytes;
1561 for (c = 7; c >= 0; c--) {
1562 int spk = cap->speakers[c];
1563 if (!spk)
1564 continue;
1565 if (put_user(spk_to_chmap(spk), dst))
1566 return -EFAULT;
1567 dst++;
1568 }
1569 }
1570 }
1571 if (put_user(count, tlv + 1))
1572 return -EFAULT;
1573 return 0;
1574}
1575
1576static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1577 struct snd_ctl_elem_value *ucontrol)
1578{
1579 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1580 struct hda_codec *codec = info->private_data;
1581 struct hdmi_spec *spec = codec->spec;
1582 int pin_idx = kcontrol->private_value;
bce0d2a8 1583 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1584 int i;
1585
1586 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1587 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1588 return 0;
1589}
1590
1591static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1592 struct snd_ctl_elem_value *ucontrol)
1593{
1594 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1595 struct hda_codec *codec = info->private_data;
1596 struct hdmi_spec *spec = codec->spec;
1597 int pin_idx = kcontrol->private_value;
bce0d2a8 1598 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1599 unsigned int ctl_idx;
1600 struct snd_pcm_substream *substream;
1601 unsigned char chmap[8];
1602 int i, ca, prepared = 0;
1603
1604 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1605 substream = snd_pcm_chmap_substream(info, ctl_idx);
1606 if (!substream || !substream->runtime)
6f54c361 1607 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1608 switch (substream->runtime->status->state) {
1609 case SNDRV_PCM_STATE_OPEN:
1610 case SNDRV_PCM_STATE_SETUP:
1611 break;
1612 case SNDRV_PCM_STATE_PREPARED:
1613 prepared = 1;
1614 break;
1615 default:
1616 return -EBUSY;
1617 }
1618 memset(chmap, 0, sizeof(chmap));
1619 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1620 chmap[i] = ucontrol->value.integer.value[i];
1621 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1622 return 0;
1623 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1624 if (ca < 0)
1625 return -EINVAL;
1626 per_pin->chmap_set = true;
1627 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1628 if (prepared)
1629 hdmi_setup_audio_infoframe(codec, pin_idx, per_pin->non_pcm,
1630 substream);
1631
1632 return 0;
1633}
1634
84eb01be
TI		 1635static int generic_hdmi_build_pcms(struct hda_codec *codec)
1636{
1637 struct hdmi_spec *spec = codec->spec;
384a48d7 1638 int pin_idx;
84eb01be 1639
384a48d7
SW		 1640 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1641 struct hda_pcm *info;
84eb01be 1642 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 1643 struct hdmi_spec_per_pin *per_pin;
1644
1645 per_pin = get_pin(spec, pin_idx);
1646 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
1647 info = snd_array_new(&spec->pcm_rec);
1648 if (!info)
1649 return -ENOMEM;
1650 info->name = per_pin->pcm_name;
84eb01be 1651 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1652 info->own_chmap = true;
384a48d7 1653
84eb01be 1654 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1655 pstr->substreams = 1;
1656 pstr->ops = generic_ops;
1657 /* other pstr fields are set in open */
84eb01be
TI		 1658 }
1659
384a48d7 1660 codec->num_pcms = spec->num_pins;
bce0d2a8 1661 codec->pcm_info = spec->pcm_rec.list;
384a48d7 1662
84eb01be
TI		 1663 return 0;
1664}
1665
0b6c49b5
DH		 1666static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1667{
31ef2257 1668 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 1669 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 1670 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1671 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 1672
31ef2257
TI		 1673 if (pcmdev > 0)
1674 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 1675 if (!is_jack_detectable(codec, per_pin->pin_nid))
1676 strncat(hdmi_str, " Phantom",
1677 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 1678
31ef2257 1679 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1680}
1681
84eb01be
TI		 1682static int generic_hdmi_build_controls(struct hda_codec *codec)
1683{
1684 struct hdmi_spec *spec = codec->spec;
1685 int err;
384a48d7 1686 int pin_idx;
84eb01be 1687
384a48d7 1688 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1689 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 1690
1691 err = generic_hdmi_build_jack(codec, pin_idx);
1692 if (err < 0)
1693 return err;
1694
dcda5806
TI		 1695 err = snd_hda_create_dig_out_ctls(codec,
1696 per_pin->pin_nid,
1697 per_pin->mux_nids[0],
1698 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 1699 if (err < 0)
1700 return err;
384a48d7 1701 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1702
1703 /* add control for ELD Bytes */
bce0d2a8
TI		 1704 err = hdmi_create_eld_ctl(codec, pin_idx,
1705 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 1706
1707 if (err < 0)
1708 return err;
31ef2257 1709
82b1d73f 1710 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 1711 }
1712
d45e6889
TI		 1713 /* add channel maps */
1714 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1715 struct snd_pcm_chmap *chmap;
1716 struct snd_kcontrol *kctl;
1717 int i;
1718 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
1719 SNDRV_PCM_STREAM_PLAYBACK,
1720 NULL, 0, pin_idx, &chmap);
1721 if (err < 0)
1722 return err;
1723 /* override handlers */
1724 chmap->private_data = codec;
1725 kctl = chmap->kctl;
1726 for (i = 0; i < kctl->count; i++)
1727 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
1728 kctl->info = hdmi_chmap_ctl_info;
1729 kctl->get = hdmi_chmap_ctl_get;
1730 kctl->put = hdmi_chmap_ctl_put;
1731 kctl->tlv.c = hdmi_chmap_ctl_tlv;
1732 }
1733
84eb01be
TI		 1734 return 0;
1735}
1736
8b8d654b 1737static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 1738{
1739 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1740 int pin_idx;
1741
1742 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1743 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1744 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1745
744626da 1746 per_pin->codec = codec;
4bd038f9 1747 mutex_init(&eld->lock);
744626da 1748 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
384a48d7 1749 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be 1750 }
8b8d654b
TI		 1751 return 0;
1752}
1753
1754static int generic_hdmi_init(struct hda_codec *codec)
1755{
1756 struct hdmi_spec *spec = codec->spec;
1757 int pin_idx;
1758
1759 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1760 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 1761 hda_nid_t pin_nid = per_pin->pin_nid;
1762
1763 hdmi_init_pin(codec, pin_nid);
1764 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
1765 }
84eb01be
TI		 1766 return 0;
1767}
1768
bce0d2a8
TI		 1769static void hdmi_array_init(struct hdmi_spec *spec, int nums)
1770{
1771 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
1772 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
1773 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
1774}
1775
1776static void hdmi_array_free(struct hdmi_spec *spec)
1777{
1778 snd_array_free(&spec->pins);
1779 snd_array_free(&spec->cvts);
1780 snd_array_free(&spec->pcm_rec);
1781}
1782
84eb01be
TI		 1783static void generic_hdmi_free(struct hda_codec *codec)
1784{
1785 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1786 int pin_idx;
1787
1788 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1789 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1790 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1791
744626da 1792 cancel_delayed_work(&per_pin->work);
384a48d7
SW		 1793 snd_hda_eld_proc_free(codec, eld);
1794 }
84eb01be 1795
744626da 1796 flush_workqueue(codec->bus->workq);
bce0d2a8 1797 hdmi_array_free(spec);
84eb01be
TI		 1798 kfree(spec);
1799}
1800
fb79e1e0 1801static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1802 .init = generic_hdmi_init,
1803 .free = generic_hdmi_free,
1804 .build_pcms = generic_hdmi_build_pcms,
1805 .build_controls = generic_hdmi_build_controls,
1806 .unsol_event = hdmi_unsol_event,
1807};
1808
6ffe168f 1809
c88d4e84
TI		 1810static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1811 hda_nid_t nid)
1812{
1813 struct hdmi_spec *spec = codec->spec;
1814 hda_nid_t conns[4];
1815 int nconns;
6ffe168f 1816
c88d4e84
TI		 1817 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
1818 if (nconns == spec->num_cvts &&
1819 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 1820 return;
1821
c88d4e84
TI		 1822 /* override pins connection list */
1823 snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
bce0d2a8 1824 nconns = max(spec->num_cvts, 4);
c88d4e84 1825 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 1826}
1827
1611a9c9
ML		 1828#define INTEL_VENDOR_NID 0x08
1829#define INTEL_GET_VENDOR_VERB 0xf81
1830#define INTEL_SET_VENDOR_VERB 0x781
1831#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
1832#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
1833
1834static void intel_haswell_enable_all_pins(struct hda_codec *codec,
1835 const struct hda_fixup *fix, int action)
1836{
1837 unsigned int vendor_param;
1838
1839 if (action != HDA_FIXUP_ACT_PRE_PROBE)
1840 return;
1841 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1842 INTEL_GET_VENDOR_VERB, 0);
1843 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
1844 return;
1845
1846 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
1847 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1848 INTEL_SET_VENDOR_VERB, vendor_param);
1849 if (vendor_param == -1)
1850 return;
1851
1852 snd_hda_codec_update_widgets(codec);
1853 return;
1854}
1855
c88d4e84
TI		 1856static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
1857{
1858 unsigned int vendor_param;
1859
1860 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1861 INTEL_GET_VENDOR_VERB, 0);
1862 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
1863 return;
1864
1865 /* enable DP1.2 mode */
1866 vendor_param |= INTEL_EN_DP12;
1867 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
1868 INTEL_SET_VENDOR_VERB, vendor_param);
1869}
1870
1871
1611a9c9
ML		 1872
1873/* available models for fixup */
1874enum {
1875 INTEL_HASWELL,
1876};
1877
1878static const struct hda_model_fixup hdmi_models[] = {
1879 {.id = INTEL_HASWELL, .name = "Haswell"},
1880 {}
1881};
1882
1883static const struct snd_pci_quirk hdmi_fixup_tbl[] = {
1884 SND_PCI_QUIRK(0x8086, 0x2010, "Haswell", INTEL_HASWELL),
1885 {} /* terminator */
1886};
1887
1888static const struct hda_fixup hdmi_fixups[] = {
1889 [INTEL_HASWELL] = {
1890 .type = HDA_FIXUP_FUNC,
1891 .v.func = intel_haswell_enable_all_pins,
1892 },
1893};
1894
6ffe168f 1895
84eb01be
TI		 1896static int patch_generic_hdmi(struct hda_codec *codec)
1897{
1898 struct hdmi_spec *spec;
84eb01be
TI		 1899
1900 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1901 if (spec == NULL)
1902 return -ENOMEM;
1903
1904 codec->spec = spec;
bce0d2a8 1905 hdmi_array_init(spec, 4);
6ffe168f 1906
1611a9c9
ML		 1907 snd_hda_pick_fixup(codec, hdmi_models, hdmi_fixup_tbl, hdmi_fixups);
1908 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE);
1909
6ffe168f 1910 if (codec->vendor_id == 0x80862807)
c88d4e84 1911 intel_haswell_fixup_enable_dp12(codec);
6ffe168f 1912
84eb01be
TI		 1913 if (hdmi_parse_codec(codec) < 0) {
1914 codec->spec = NULL;
1915 kfree(spec);
1916 return -EINVAL;
1917 }
1918 codec->patch_ops = generic_hdmi_patch_ops;
8b8d654b 1919 generic_hdmi_init_per_pins(codec);
84eb01be 1920
84eb01be
TI		 1921 init_channel_allocations();
1922
1923 return 0;
1924}
1925
3aaf8980
SW		 1926/*
1927 * Shared non-generic implementations
1928 */
1929
1930static int simple_playback_build_pcms(struct hda_codec *codec)
1931{
1932 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1933 struct hda_pcm *info;
8ceb332d
TI		 1934 unsigned int chans;
1935 struct hda_pcm_stream *pstr;
bce0d2a8 1936 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 1937
bce0d2a8
TI		 1938 per_cvt = get_cvt(spec, 0);
1939 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 1940 chans = get_wcaps_channels(chans);
3aaf8980 1941
bce0d2a8
TI		 1942 info = snd_array_new(&spec->pcm_rec);
1943 if (!info)
1944 return -ENOMEM;
1945 info->name = get_pin(spec, 0)->pcm_name;
1946 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 1947 info->pcm_type = HDA_PCM_TYPE_HDMI;
1948 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1949 *pstr = spec->pcm_playback;
bce0d2a8 1950 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 1951 if (pstr->channels_max <= 2 && chans && chans <= 16)
1952 pstr->channels_max = chans;
3aaf8980 1953
bce0d2a8
TI		 1954 codec->num_pcms = 1;
1955 codec->pcm_info = info;
1956
3aaf8980
SW		 1957 return 0;
1958}
1959
4b6ace9e
TI		 1960/* unsolicited event for jack sensing */
1961static void simple_hdmi_unsol_event(struct hda_codec *codec,
1962 unsigned int res)
1963{
9dd8cf12 1964 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 1965 snd_hda_jack_report_sync(codec);
1966}
1967
1968/* generic_hdmi_build_jack can be used for simple_hdmi, too,
1969 * as long as spec->pins[] is set correctly
1970 */
1971#define simple_hdmi_build_jack generic_hdmi_build_jack
1972
3aaf8980
SW		 1973static int simple_playback_build_controls(struct hda_codec *codec)
1974{
1975 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1976 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 1977 int err;
3aaf8980 1978
bce0d2a8
TI		 1979 per_cvt = get_cvt(spec, 0);
1980 err = snd_hda_create_spdif_out_ctls(codec, per_cvt->cvt_nid,
1981 per_cvt->cvt_nid);
8ceb332d
TI		 1982 if (err < 0)
1983 return err;
1984 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 1985}
1986
4f0110ce
TI		 1987static int simple_playback_init(struct hda_codec *codec)
1988{
1989 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 1990 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
1991 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 1992
1993 snd_hda_codec_write(codec, pin, 0,
1994 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
1995 /* some codecs require to unmute the pin */
1996 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
1997 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
1998 AMP_OUT_UNMUTE);
1999 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2000 return 0;
2001}
2002
3aaf8980
SW		 2003static void simple_playback_free(struct hda_codec *codec)
2004{
2005 struct hdmi_spec *spec = codec->spec;
2006
bce0d2a8 2007 hdmi_array_free(spec);
3aaf8980
SW		 2008 kfree(spec);
2009}
2010
84eb01be
TI		 2011/*
2012 * Nvidia specific implementations
2013 */
2014
2015#define Nv_VERB_SET_Channel_Allocation 0xF79
2016#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2017#define Nv_VERB_SET_Audio_Protection_On 0xF98
2018#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2019
2020#define nvhdmi_master_con_nid_7x 0x04
2021#define nvhdmi_master_pin_nid_7x 0x05
2022
fb79e1e0 2023static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2024 /*front, rear, clfe, rear_surr */
2025 0x6, 0x8, 0xa, 0xc,
2026};
2027
ceaa86ba
TI		 2028static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2029 /* set audio protect on */
2030 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2031 /* enable digital output on pin widget */
2032 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2033 {} /* terminator */
2034};
2035
2036static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2037 /* set audio protect on */
2038 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2039 /* enable digital output on pin widget */
2040 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2041 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2042 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2043 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2044 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2045 {} /* terminator */
2046};
2047
2048#ifdef LIMITED_RATE_FMT_SUPPORT
2049/* support only the safe format and rate */
2050#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2051#define SUPPORTED_MAXBPS 16
2052#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2053#else
2054/* support all rates and formats */
2055#define SUPPORTED_RATES \
2056 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2057 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2058 SNDRV_PCM_RATE_192000)
2059#define SUPPORTED_MAXBPS 24
2060#define SUPPORTED_FORMATS \
2061 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2062#endif
2063
ceaa86ba
TI		 2064static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2065{
2066 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2067 return 0;
2068}
2069
2070static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2071{
ceaa86ba 2072 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2073 return 0;
2074}
2075
393004b2
ND		 2076static unsigned int channels_2_6_8[] = {
2077 2, 6, 8
2078};
2079
2080static unsigned int channels_2_8[] = {
2081 2, 8
2082};
2083
2084static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2085 .count = ARRAY_SIZE(channels_2_6_8),
2086 .list = channels_2_6_8,
2087 .mask = 0,
2088};
2089
2090static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2091 .count = ARRAY_SIZE(channels_2_8),
2092 .list = channels_2_8,
2093 .mask = 0,
2094};
2095
84eb01be
TI		 2096static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2097 struct hda_codec *codec,
2098 struct snd_pcm_substream *substream)
2099{
2100 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2101 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2102
2103 switch (codec->preset->id) {
2104 case 0x10de0002:
2105 case 0x10de0003:
2106 case 0x10de0005:
2107 case 0x10de0006:
2108 hw_constraints_channels = &hw_constraints_2_8_channels;
2109 break;
2110 case 0x10de0007:
2111 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2112 break;
2113 default:
2114 break;
2115 }
2116
2117 if (hw_constraints_channels != NULL) {
2118 snd_pcm_hw_constraint_list(substream->runtime, 0,
2119 SNDRV_PCM_HW_PARAM_CHANNELS,
2120 hw_constraints_channels);
ad09fc9d
TI		 2121 } else {
2122 snd_pcm_hw_constraint_step(substream->runtime, 0,
2123 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2124 }
2125
84eb01be
TI		 2126 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2127}
2128
2129static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2130 struct hda_codec *codec,
2131 struct snd_pcm_substream *substream)
2132{
2133 struct hdmi_spec *spec = codec->spec;
2134 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2135}
2136
2137static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2138 struct hda_codec *codec,
2139 unsigned int stream_tag,
2140 unsigned int format,
2141 struct snd_pcm_substream *substream)
2142{
2143 struct hdmi_spec *spec = codec->spec;
2144 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2145 stream_tag, format, substream);
2146}
2147
d0b1252d
TI		 2148static const struct hda_pcm_stream simple_pcm_playback = {
2149 .substreams = 1,
2150 .channels_min = 2,
2151 .channels_max = 2,
2152 .ops = {
2153 .open = simple_playback_pcm_open,
2154 .close = simple_playback_pcm_close,
2155 .prepare = simple_playback_pcm_prepare
2156 },
2157};
2158
2159static const struct hda_codec_ops simple_hdmi_patch_ops = {
2160 .build_controls = simple_playback_build_controls,
2161 .build_pcms = simple_playback_build_pcms,
2162 .init = simple_playback_init,
2163 .free = simple_playback_free,
250e41ac 2164 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2165};
2166
2167static int patch_simple_hdmi(struct hda_codec *codec,
2168 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2169{
2170 struct hdmi_spec *spec;
bce0d2a8
TI		 2171 struct hdmi_spec_per_cvt *per_cvt;
2172 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2173
2174 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2175 if (!spec)
2176 return -ENOMEM;
2177
2178 codec->spec = spec;
bce0d2a8 2179 hdmi_array_init(spec, 1);
d0b1252d
TI		 2180
2181 spec->multiout.num_dacs = 0; /* no analog */
2182 spec->multiout.max_channels = 2;
2183 spec->multiout.dig_out_nid = cvt_nid;
2184 spec->num_cvts = 1;
2185 spec->num_pins = 1;
bce0d2a8
TI		 2186 per_pin = snd_array_new(&spec->pins);
2187 per_cvt = snd_array_new(&spec->cvts);
2188 if (!per_pin || !per_cvt) {
2189 simple_playback_free(codec);
2190 return -ENOMEM;
2191 }
2192 per_cvt->cvt_nid = cvt_nid;
2193 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2194 spec->pcm_playback = simple_pcm_playback;
2195
2196 codec->patch_ops = simple_hdmi_patch_ops;
2197
2198 return 0;
2199}
2200
1f348522
AP		 2201static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2202 int channels)
2203{
2204 unsigned int chanmask;
2205 int chan = channels ? (channels - 1) : 1;
2206
2207 switch (channels) {
2208 default:
2209 case 0:
2210 case 2:
2211 chanmask = 0x00;
2212 break;
2213 case 4:
2214 chanmask = 0x08;
2215 break;
2216 case 6:
2217 chanmask = 0x0b;
2218 break;
2219 case 8:
2220 chanmask = 0x13;
2221 break;
2222 }
2223
2224 /* Set the audio infoframe channel allocation and checksum fields. The
2225 * channel count is computed implicitly by the hardware. */
2226 snd_hda_codec_write(codec, 0x1, 0,
2227 Nv_VERB_SET_Channel_Allocation, chanmask);
2228
2229 snd_hda_codec_write(codec, 0x1, 0,
2230 Nv_VERB_SET_Info_Frame_Checksum,
2231 (0x71 - chan - chanmask));
2232}
2233
84eb01be
TI		 2234static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2235 struct hda_codec *codec,
2236 struct snd_pcm_substream *substream)
2237{
2238 struct hdmi_spec *spec = codec->spec;
2239 int i;
2240
2241 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2242 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2243 for (i = 0; i < 4; i++) {
2244 /* set the stream id */
2245 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2246 AC_VERB_SET_CHANNEL_STREAMID, 0);
2247 /* set the stream format */
2248 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2249 AC_VERB_SET_STREAM_FORMAT, 0);
2250 }
2251
1f348522
AP		 2252 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2253 * streams are disabled. */
2254 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2255
84eb01be
TI		 2256 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2257}
2258
2259static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2260 struct hda_codec *codec,
2261 unsigned int stream_tag,
2262 unsigned int format,
2263 struct snd_pcm_substream *substream)
2264{
2265 int chs;
112daa7a 2266 unsigned int dataDCC2, channel_id;
84eb01be 2267 int i;
7c935976 2268 struct hdmi_spec *spec = codec->spec;
e3245cdd 2269 struct hda_spdif_out *spdif;
bce0d2a8 2270 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2271
2272 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2273 per_cvt = get_cvt(spec, 0);
2274 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2275
2276 chs = substream->runtime->channels;
84eb01be 2277
84eb01be
TI		 2278 dataDCC2 = 0x2;
2279
84eb01be 2280 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2281 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2282 snd_hda_codec_write(codec,
2283 nvhdmi_master_con_nid_7x,
2284 0,
2285 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2286 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2287
2288 /* set the stream id */
2289 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2290 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2291
2292 /* set the stream format */
2293 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2294 AC_VERB_SET_STREAM_FORMAT, format);
2295
2296 /* turn on again (if needed) */
2297 /* enable and set the channel status audio/data flag */
7c935976 2298 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2299 snd_hda_codec_write(codec,
2300 nvhdmi_master_con_nid_7x,
2301 0,
2302 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2303 spdif->ctls & 0xff);
84eb01be
TI		 2304 snd_hda_codec_write(codec,
2305 nvhdmi_master_con_nid_7x,
2306 0,
2307 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2308 }
2309
2310 for (i = 0; i < 4; i++) {
2311 if (chs == 2)
2312 channel_id = 0;
2313 else
2314 channel_id = i * 2;
2315
2316 /* turn off SPDIF once;
2317 *otherwise the IEC958 bits won't be updated
2318 */
2319 if (codec->spdif_status_reset &&
7c935976 2320 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2321 snd_hda_codec_write(codec,
2322 nvhdmi_con_nids_7x[i],
2323 0,
2324 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2325 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2326 /* set the stream id */
2327 snd_hda_codec_write(codec,
2328 nvhdmi_con_nids_7x[i],
2329 0,
2330 AC_VERB_SET_CHANNEL_STREAMID,
2331 (stream_tag << 4) | channel_id);
2332 /* set the stream format */
2333 snd_hda_codec_write(codec,
2334 nvhdmi_con_nids_7x[i],
2335 0,
2336 AC_VERB_SET_STREAM_FORMAT,
2337 format);
2338 /* turn on again (if needed) */
2339 /* enable and set the channel status audio/data flag */
2340 if (codec->spdif_status_reset &&
7c935976 2341 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2342 snd_hda_codec_write(codec,
2343 nvhdmi_con_nids_7x[i],
2344 0,
2345 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2346 spdif->ctls & 0xff);
84eb01be
TI		 2347 snd_hda_codec_write(codec,
2348 nvhdmi_con_nids_7x[i],
2349 0,
2350 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2351 }
2352 }
2353
1f348522 2354 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2355
2356 mutex_unlock(&codec->spdif_mutex);
2357 return 0;
2358}
2359
fb79e1e0 2360static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2361 .substreams = 1,
2362 .channels_min = 2,
2363 .channels_max = 8,
2364 .nid = nvhdmi_master_con_nid_7x,
2365 .rates = SUPPORTED_RATES,
2366 .maxbps = SUPPORTED_MAXBPS,
2367 .formats = SUPPORTED_FORMATS,
2368 .ops = {
2369 .open = simple_playback_pcm_open,
2370 .close = nvhdmi_8ch_7x_pcm_close,
2371 .prepare = nvhdmi_8ch_7x_pcm_prepare
2372 },
2373};
2374
84eb01be
TI		 2375static int patch_nvhdmi_2ch(struct hda_codec *codec)
2376{
2377 struct hdmi_spec *spec;
d0b1252d
TI		 2378 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2379 nvhdmi_master_pin_nid_7x);
2380 if (err < 0)
2381 return err;
84eb01be 2382
ceaa86ba 2383 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2384 /* override the PCM rates, etc, as the codec doesn't give full list */
2385 spec = codec->spec;
2386 spec->pcm_playback.rates = SUPPORTED_RATES;
2387 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2388 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2389 return 0;
2390}
2391
53775b0d
TI		 2392static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2393{
2394 struct hdmi_spec *spec = codec->spec;
2395 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2396 if (!err) {
2397 struct hda_pcm *info = get_pcm_rec(spec, 0);
2398 info->own_chmap = true;
2399 }
53775b0d
TI		 2400 return err;
2401}
2402
2403static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2404{
2405 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2406 struct hda_pcm *info;
53775b0d
TI		 2407 struct snd_pcm_chmap *chmap;
2408 int err;
2409
2410 err = simple_playback_build_controls(codec);
2411 if (err < 0)
2412 return err;
2413
2414 /* add channel maps */
bce0d2a8
TI		 2415 info = get_pcm_rec(spec, 0);
2416 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2417 SNDRV_PCM_STREAM_PLAYBACK,
2418 snd_pcm_alt_chmaps, 8, 0, &chmap);
2419 if (err < 0)
2420 return err;
2421 switch (codec->preset->id) {
2422 case 0x10de0002:
2423 case 0x10de0003:
2424 case 0x10de0005:
2425 case 0x10de0006:
2426 chmap->channel_mask = (1U << 2) | (1U << 8);
2427 break;
2428 case 0x10de0007:
2429 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2430 }
2431 return 0;
2432}
2433
84eb01be
TI		 2434static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2435{
2436 struct hdmi_spec *spec;
2437 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2438 if (err < 0)
2439 return err;
2440 spec = codec->spec;
2441 spec->multiout.max_channels = 8;
d0b1252d 2442 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2443 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2444 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2445 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2446
2447 /* Initialize the audio infoframe channel mask and checksum to something
2448 * valid */
2449 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2450
84eb01be
TI		 2451 return 0;
2452}
2453
2454/*
2455 * ATI-specific implementations
2456 *
2457 * FIXME: we may omit the whole this and use the generic code once after
2458 * it's confirmed to work.
2459 */
2460
2461#define ATIHDMI_CVT_NID 0x02 /* audio converter */
2462#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
2463
2464static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2465 struct hda_codec *codec,
2466 unsigned int stream_tag,
2467 unsigned int format,
2468 struct snd_pcm_substream *substream)
2469{
2470 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2471 struct hdmi_spec_per_cvt *per_cvt = get_cvt(spec, 0);
84eb01be
TI		 2472 int chans = substream->runtime->channels;
2473 int i, err;
2474
2475 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
2476 substream);
2477 if (err < 0)
2478 return err;
bce0d2a8 2479 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
384a48d7 2480 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 2481 /* FIXME: XXX */
2482 for (i = 0; i < chans; i++) {
bce0d2a8 2483 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
84eb01be
TI		 2484 AC_VERB_SET_HDMI_CHAN_SLOT,
2485 (i << 4) | i);
2486 }
2487 return 0;
2488}
2489
84eb01be
TI		 2490static int patch_atihdmi(struct hda_codec *codec)
2491{
2492 struct hdmi_spec *spec;
d0b1252d
TI		 2493 int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
2494 if (err < 0)
2495 return err;
2496 spec = codec->spec;
2497 spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
84eb01be
TI		 2498 return 0;
2499}
2500
3de5ff88
AL		 2501/* VIA HDMI Implementation */
2502#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
2503#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
2504
3de5ff88
AL		 2505static int patch_via_hdmi(struct hda_codec *codec)
2506{
250e41ac 2507 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 2508}
84eb01be
TI		 2509
2510/*
2511 * patch entries
2512 */
fb79e1e0 2513static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 2514{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
2515{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
2516{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 2517{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2518{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
2519{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
2520{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
2521{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2522{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2523{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2524{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2525{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 2526{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
2527{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
2528{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
2529{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
2530{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
2531{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
2532{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
2533{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
2534{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
2535{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
2536{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 2537/* 17 is known to be absent */
5d44f927
SW		 2538{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
2539{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
2540{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
2541{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
2542{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
2543{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
2544{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
2545{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
2546{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
2547{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
7ae48b56 2548{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2549{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
2550{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 2551{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2552{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2553{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
2554{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2555{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2556{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
2557{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
2558{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
2559{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2560{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 2561{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 2562{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 2563{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2564{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
2565{} /* terminator */
2566};
2567
2568MODULE_ALIAS("snd-hda-codec-id:1002793c");
2569MODULE_ALIAS("snd-hda-codec-id:10027919");
2570MODULE_ALIAS("snd-hda-codec-id:1002791a");
2571MODULE_ALIAS("snd-hda-codec-id:1002aa01");
2572MODULE_ALIAS("snd-hda-codec-id:10951390");
2573MODULE_ALIAS("snd-hda-codec-id:10951392");
2574MODULE_ALIAS("snd-hda-codec-id:10de0002");
2575MODULE_ALIAS("snd-hda-codec-id:10de0003");
2576MODULE_ALIAS("snd-hda-codec-id:10de0005");
2577MODULE_ALIAS("snd-hda-codec-id:10de0006");
2578MODULE_ALIAS("snd-hda-codec-id:10de0007");
2579MODULE_ALIAS("snd-hda-codec-id:10de000a");
2580MODULE_ALIAS("snd-hda-codec-id:10de000b");
2581MODULE_ALIAS("snd-hda-codec-id:10de000c");
2582MODULE_ALIAS("snd-hda-codec-id:10de000d");
2583MODULE_ALIAS("snd-hda-codec-id:10de0010");
2584MODULE_ALIAS("snd-hda-codec-id:10de0011");
2585MODULE_ALIAS("snd-hda-codec-id:10de0012");
2586MODULE_ALIAS("snd-hda-codec-id:10de0013");
2587MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 2588MODULE_ALIAS("snd-hda-codec-id:10de0015");
2589MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 2590MODULE_ALIAS("snd-hda-codec-id:10de0018");
2591MODULE_ALIAS("snd-hda-codec-id:10de0019");
2592MODULE_ALIAS("snd-hda-codec-id:10de001a");
2593MODULE_ALIAS("snd-hda-codec-id:10de001b");
2594MODULE_ALIAS("snd-hda-codec-id:10de001c");
2595MODULE_ALIAS("snd-hda-codec-id:10de0040");
2596MODULE_ALIAS("snd-hda-codec-id:10de0041");
2597MODULE_ALIAS("snd-hda-codec-id:10de0042");
2598MODULE_ALIAS("snd-hda-codec-id:10de0043");
2599MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 2600MODULE_ALIAS("snd-hda-codec-id:10de0051");
84eb01be
TI		 2601MODULE_ALIAS("snd-hda-codec-id:10de0067");
2602MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 2603MODULE_ALIAS("snd-hda-codec-id:11069f80");
2604MODULE_ALIAS("snd-hda-codec-id:11069f81");
2605MODULE_ALIAS("snd-hda-codec-id:11069f84");
2606MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 2607MODULE_ALIAS("snd-hda-codec-id:17e80047");
2608MODULE_ALIAS("snd-hda-codec-id:80860054");
2609MODULE_ALIAS("snd-hda-codec-id:80862801");
2610MODULE_ALIAS("snd-hda-codec-id:80862802");
2611MODULE_ALIAS("snd-hda-codec-id:80862803");
2612MODULE_ALIAS("snd-hda-codec-id:80862804");
2613MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 2614MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 2615MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 2616MODULE_ALIAS("snd-hda-codec-id:80862880");
84eb01be
TI		 2617MODULE_ALIAS("snd-hda-codec-id:808629fb");
2618
2619MODULE_LICENSE("GPL");
2620MODULE_DESCRIPTION("HDMI HD-audio codec");
2621MODULE_ALIAS("snd-hda-codec-intelhdmi");
2622MODULE_ALIAS("snd-hda-codec-nvhdmi");
2623MODULE_ALIAS("snd-hda-codec-atihdmi");
2624
2625static struct hda_codec_preset_list intel_list = {
2626 .preset = snd_hda_preset_hdmi,
2627 .owner = THIS_MODULE,
2628};
2629
2630static int __init patch_hdmi_init(void)
2631{
2632 return snd_hda_add_codec_preset(&intel_list);
2633}
2634
2635static void __exit patch_hdmi_exit(void)
2636{
2637 snd_hda_delete_codec_preset(&intel_list);
2638}
2639
2640module_init(patch_hdmi_init)
2641module_exit(patch_hdmi_exit)
Ubuntu Artful kernel mirror