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ALSA: hda - Don't add channel suffix for headphone pin labels
[mirror_ubuntu-zesty-kernel.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
84eb01be
TI		 37#include "hda_codec.h"
38#include "hda_local.h"
1835a0f9 39#include "hda_jack.h"
84eb01be 40
0ebaa24c
TI		 41static bool static_hdmi_pcm;
42module_param(static_hdmi_pcm, bool, 0644);
43MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
44
84eb01be
TI		 45/*
46 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
384a48d7 47 * could support N independent pipes, each of them can be connected to one or
84eb01be
TI		 48 * more ports (DVI, HDMI or DisplayPort).
49 *
50 * The HDA correspondence of pipes/ports are converter/pin nodes.
51 */
73926656
SW		 52#define MAX_HDMI_CVTS 4
53#define MAX_HDMI_PINS 4
079d88cc 54
384a48d7
SW		 55struct hdmi_spec_per_cvt {
56 hda_nid_t cvt_nid;
57 int assigned;
58 unsigned int channels_min;
59 unsigned int channels_max;
60 u32 rates;
61 u64 formats;
62 unsigned int maxbps;
63};
079d88cc 64
384a48d7
SW		 65struct hdmi_spec_per_pin {
66 hda_nid_t pin_nid;
67 int num_mux_nids;
68 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
744626da
WF		 69
70 struct hda_codec *codec;
384a48d7 71 struct hdmi_eld sink_eld;
744626da 72 struct delayed_work work;
384a48d7 73};
079d88cc 74
384a48d7
SW		 75struct hdmi_spec {
76 int num_cvts;
77 struct hdmi_spec_per_cvt cvts[MAX_HDMI_CVTS];
079d88cc 78
384a48d7
SW		 79 int num_pins;
80 struct hdmi_spec_per_pin pins[MAX_HDMI_PINS];
81 struct hda_pcm pcm_rec[MAX_HDMI_PINS];
079d88cc
WF		 82
83 /*
384a48d7 84 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 85 */
86 struct hda_multi_out multiout;
fb79e1e0 87 const struct hda_pcm_stream *pcm_playback;
079d88cc
WF		 88};
89
90
91struct hdmi_audio_infoframe {
92 u8 type; /* 0x84 */
93 u8 ver; /* 0x01 */
94 u8 len; /* 0x0a */
95
53d7d69d
WF		 96 u8 checksum;
97
079d88cc
WF		 98 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
99 u8 SS01_SF24;
100 u8 CXT04;
101 u8 CA;
102 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 103};
104
105struct dp_audio_infoframe {
106 u8 type; /* 0x84 */
107 u8 len; /* 0x1b */
108 u8 ver; /* 0x11 << 2 */
109
110 u8 CC02_CT47; /* match with HDMI infoframe from this on */
111 u8 SS01_SF24;
112 u8 CXT04;
113 u8 CA;
114 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 115};
116
2b203dbb
TI		 117union audio_infoframe {
118 struct hdmi_audio_infoframe hdmi;
119 struct dp_audio_infoframe dp;
120 u8 bytes[0];
121};
122
079d88cc
WF		 123/*
124 * CEA speaker placement:
125 *
126 * FLH FCH FRH
127 * FLW FL FLC FC FRC FR FRW
128 *
129 * LFE
130 * TC
131 *
132 * RL RLC RC RRC RR
133 *
134 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
135 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
136 */
137enum cea_speaker_placement {
138 FL = (1 << 0), /* Front Left */
139 FC = (1 << 1), /* Front Center */
140 FR = (1 << 2), /* Front Right */
141 FLC = (1 << 3), /* Front Left Center */
142 FRC = (1 << 4), /* Front Right Center */
143 RL = (1 << 5), /* Rear Left */
144 RC = (1 << 6), /* Rear Center */
145 RR = (1 << 7), /* Rear Right */
146 RLC = (1 << 8), /* Rear Left Center */
147 RRC = (1 << 9), /* Rear Right Center */
148 LFE = (1 << 10), /* Low Frequency Effect */
149 FLW = (1 << 11), /* Front Left Wide */
150 FRW = (1 << 12), /* Front Right Wide */
151 FLH = (1 << 13), /* Front Left High */
152 FCH = (1 << 14), /* Front Center High */
153 FRH = (1 << 15), /* Front Right High */
154 TC = (1 << 16), /* Top Center */
155};
156
157/*
158 * ELD SA bits in the CEA Speaker Allocation data block
159 */
160static int eld_speaker_allocation_bits[] = {
161 [0] = FL | FR,
162 [1] = LFE,
163 [2] = FC,
164 [3] = RL | RR,
165 [4] = RC,
166 [5] = FLC | FRC,
167 [6] = RLC | RRC,
168 /* the following are not defined in ELD yet */
169 [7] = FLW | FRW,
170 [8] = FLH | FRH,
171 [9] = TC,
172 [10] = FCH,
173};
174
175struct cea_channel_speaker_allocation {
176 int ca_index;
177 int speakers[8];
178
179 /* derived values, just for convenience */
180 int channels;
181 int spk_mask;
182};
183
184/*
185 * ALSA sequence is:
186 *
187 * surround40 surround41 surround50 surround51 surround71
188 * ch0 front left = = = =
189 * ch1 front right = = = =
190 * ch2 rear left = = = =
191 * ch3 rear right = = = =
192 * ch4 LFE center center center
193 * ch5 LFE LFE
194 * ch6 side left
195 * ch7 side right
196 *
197 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
198 */
199static int hdmi_channel_mapping[0x32][8] = {
200 /* stereo */
201 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
202 /* 2.1 */
203 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
204 /* Dolby Surround */
205 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
206 /* surround40 */
207 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
208 /* 4ch */
209 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
210 /* surround41 */
9396d317 211 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 212 /* surround50 */
213 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
214 /* surround51 */
215 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
216 /* 7.1 */
217 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
218};
219
220/*
221 * This is an ordered list!
222 *
223 * The preceding ones have better chances to be selected by
53d7d69d 224 * hdmi_channel_allocation().
079d88cc
WF		 225 */
226static struct cea_channel_speaker_allocation channel_allocations[] = {
227/* channel: 7 6 5 4 3 2 1 0 */
228{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
229 /* 2.1 */
230{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
231 /* Dolby Surround */
232{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
233 /* surround40 */
234{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
235 /* surround41 */
236{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
237 /* surround50 */
238{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
239 /* surround51 */
240{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
241 /* 6.1 */
242{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
243 /* surround71 */
244{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
245
246{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
247{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
248{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
249{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
250{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
251{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
252{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
253{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
254{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
255{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
256{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
257{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
258{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
259{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
260{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
261{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
262{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
263{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
264{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
265{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
266{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
267{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
268{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
269{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
270{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
271{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
272{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
273{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
274{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
275{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
276{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
277{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
278{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
279{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
280{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
281{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
282{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
283{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
284{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
285{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
286{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
287};
288
289
290/*
291 * HDMI routines
292 */
293
384a48d7 294static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 295{
384a48d7 296 int pin_idx;
079d88cc 297
384a48d7
SW		 298 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
299 if (spec->pins[pin_idx].pin_nid == pin_nid)
300 return pin_idx;
079d88cc 301
384a48d7
SW		 302 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
303 return -EINVAL;
304}
305
306static int hinfo_to_pin_index(struct hdmi_spec *spec,
307 struct hda_pcm_stream *hinfo)
308{
309 int pin_idx;
310
311 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
312 if (&spec->pcm_rec[pin_idx].stream[0] == hinfo)
313 return pin_idx;
314
315 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
316 return -EINVAL;
317}
318
319static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
320{
321 int cvt_idx;
322
323 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
324 if (spec->cvts[cvt_idx].cvt_nid == cvt_nid)
325 return cvt_idx;
326
327 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 328 return -EINVAL;
329}
330
14bc52b8
PLB		 331static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
332 struct snd_ctl_elem_info *uinfo)
333{
334 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
335 struct hdmi_spec *spec;
336 int pin_idx;
337
338 spec = codec->spec;
339 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
340
341 pin_idx = kcontrol->private_value;
342 uinfo->count = spec->pins[pin_idx].sink_eld.eld_size;
343
344 return 0;
345}
346
347static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
348 struct snd_ctl_elem_value *ucontrol)
349{
350 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
351 struct hdmi_spec *spec;
352 int pin_idx;
353
354 spec = codec->spec;
355 pin_idx = kcontrol->private_value;
356
357 memcpy(ucontrol->value.bytes.data,
358 spec->pins[pin_idx].sink_eld.eld_buffer, ELD_MAX_SIZE);
359
360 return 0;
361}
362
363static struct snd_kcontrol_new eld_bytes_ctl = {
364 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
365 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
366 .name = "ELD",
367 .info = hdmi_eld_ctl_info,
368 .get = hdmi_eld_ctl_get,
369};
370
371static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
372 int device)
373{
374 struct snd_kcontrol *kctl;
375 struct hdmi_spec *spec = codec->spec;
376 int err;
377
378 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
379 if (!kctl)
380 return -ENOMEM;
381 kctl->private_value = pin_idx;
382 kctl->id.device = device;
383
384 err = snd_hda_ctl_add(codec, spec->pins[pin_idx].pin_nid, kctl);
385 if (err < 0)
386 return err;
387
388 return 0;
389}
390
079d88cc
WF		 391#ifdef BE_PARANOID
392static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
393 int *packet_index, int *byte_index)
394{
395 int val;
396
397 val = snd_hda_codec_read(codec, pin_nid, 0,
398 AC_VERB_GET_HDMI_DIP_INDEX, 0);
399
400 *packet_index = val >> 5;
401 *byte_index = val & 0x1f;
402}
403#endif
404
405static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
406 int packet_index, int byte_index)
407{
408 int val;
409
410 val = (packet_index << 5) | (byte_index & 0x1f);
411
412 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
413}
414
415static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
416 unsigned char val)
417{
418 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
419}
420
384a48d7 421static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 422{
423 /* Unmute */
424 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
425 snd_hda_codec_write(codec, pin_nid, 0,
426 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
384a48d7 427 /* Disable pin out until stream is active*/
079d88cc 428 snd_hda_codec_write(codec, pin_nid, 0,
384a48d7 429 AC_VERB_SET_PIN_WIDGET_CONTROL, 0);
079d88cc
WF		 430}
431
384a48d7 432static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 433{
384a48d7 434 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 435 AC_VERB_GET_CVT_CHAN_COUNT, 0);
436}
437
438static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 439 hda_nid_t cvt_nid, int chs)
079d88cc 440{
384a48d7
SW		 441 if (chs != hdmi_get_channel_count(codec, cvt_nid))
442 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 443 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
444}
445
446
447/*
448 * Channel mapping routines
449 */
450
451/*
452 * Compute derived values in channel_allocations[].
453 */
454static void init_channel_allocations(void)
455{
456 int i, j;
457 struct cea_channel_speaker_allocation *p;
458
459 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
460 p = channel_allocations + i;
461 p->channels = 0;
462 p->spk_mask = 0;
463 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
464 if (p->speakers[j]) {
465 p->channels++;
466 p->spk_mask |= p->speakers[j];
467 }
468 }
469}
470
471/*
472 * The transformation takes two steps:
473 *
474 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
475 * spk_mask => (channel_allocations[]) => ai->CA
476 *
477 * TODO: it could select the wrong CA from multiple candidates.
478*/
384a48d7 479static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 480{
079d88cc 481 int i;
53d7d69d 482 int ca = 0;
079d88cc 483 int spk_mask = 0;
079d88cc
WF		 484 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
485
486 /*
487 * CA defaults to 0 for basic stereo audio
488 */
489 if (channels <= 2)
490 return 0;
491
079d88cc
WF		 492 /*
493 * expand ELD's speaker allocation mask
494 *
495 * ELD tells the speaker mask in a compact(paired) form,
496 * expand ELD's notions to match the ones used by Audio InfoFrame.
497 */
498 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
499 if (eld->spk_alloc & (1 << i))
500 spk_mask |= eld_speaker_allocation_bits[i];
501 }
502
503 /* search for the first working match in the CA table */
504 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
505 if (channels == channel_allocations[i].channels &&
506 (spk_mask & channel_allocations[i].spk_mask) ==
507 channel_allocations[i].spk_mask) {
53d7d69d 508 ca = channel_allocations[i].ca_index;
079d88cc
WF		 509 break;
510 }
511 }
512
513 snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
2abbf439 514 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 515 ca, channels, buf);
079d88cc 516
53d7d69d 517 return ca;
079d88cc
WF		 518}
519
520static void hdmi_debug_channel_mapping(struct hda_codec *codec,
521 hda_nid_t pin_nid)
522{
523#ifdef CONFIG_SND_DEBUG_VERBOSE
524 int i;
525 int slot;
526
527 for (i = 0; i < 8; i++) {
528 slot = snd_hda_codec_read(codec, pin_nid, 0,
529 AC_VERB_GET_HDMI_CHAN_SLOT, i);
530 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
531 slot >> 4, slot & 0xf);
532 }
533#endif
534}
535
536
537static void hdmi_setup_channel_mapping(struct hda_codec *codec,
538 hda_nid_t pin_nid,
53d7d69d 539 int ca)
079d88cc
WF		 540{
541 int i;
079d88cc
WF		 542 int err;
543
544 if (hdmi_channel_mapping[ca][1] == 0) {
545 for (i = 0; i < channel_allocations[ca].channels; i++)
546 hdmi_channel_mapping[ca][i] = i | (i << 4);
547 for (; i < 8; i++)
548 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
549 }
550
551 for (i = 0; i < 8; i++) {
552 err = snd_hda_codec_write(codec, pin_nid, 0,
553 AC_VERB_SET_HDMI_CHAN_SLOT,
554 hdmi_channel_mapping[ca][i]);
555 if (err) {
2abbf439
WF		 556 snd_printdd(KERN_NOTICE
557 "HDMI: channel mapping failed\n");
079d88cc
WF		 558 break;
559 }
560 }
561
562 hdmi_debug_channel_mapping(codec, pin_nid);
563}
564
565
566/*
567 * Audio InfoFrame routines
568 */
569
570/*
571 * Enable Audio InfoFrame Transmission
572 */
573static void hdmi_start_infoframe_trans(struct hda_codec *codec,
574 hda_nid_t pin_nid)
575{
576 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
577 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
578 AC_DIPXMIT_BEST);
579}
580
581/*
582 * Disable Audio InfoFrame Transmission
583 */
584static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
585 hda_nid_t pin_nid)
586{
587 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
588 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
589 AC_DIPXMIT_DISABLE);
590}
591
592static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
593{
594#ifdef CONFIG_SND_DEBUG_VERBOSE
595 int i;
596 int size;
597
598 size = snd_hdmi_get_eld_size(codec, pin_nid);
599 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
600
601 for (i = 0; i < 8; i++) {
602 size = snd_hda_codec_read(codec, pin_nid, 0,
603 AC_VERB_GET_HDMI_DIP_SIZE, i);
604 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
605 }
606#endif
607}
608
609static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
610{
611#ifdef BE_PARANOID
612 int i, j;
613 int size;
614 int pi, bi;
615 for (i = 0; i < 8; i++) {
616 size = snd_hda_codec_read(codec, pin_nid, 0,
617 AC_VERB_GET_HDMI_DIP_SIZE, i);
618 if (size == 0)
619 continue;
620
621 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
622 for (j = 1; j < 1000; j++) {
623 hdmi_write_dip_byte(codec, pin_nid, 0x0);
624 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
625 if (pi != i)
626 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
627 bi, pi, i);
628 if (bi == 0) /* byte index wrapped around */
629 break;
630 }
631 snd_printd(KERN_INFO
632 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
633 i, size, j);
634 }
635#endif
636}
637
53d7d69d 638static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 639{
53d7d69d 640 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 641 u8 sum = 0;
642 int i;
643
53d7d69d 644 hdmi_ai->checksum = 0;
079d88cc 645
53d7d69d 646 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 647 sum += bytes[i];
648
53d7d69d 649 hdmi_ai->checksum = -sum;
079d88cc
WF		 650}
651
652static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
653 hda_nid_t pin_nid,
53d7d69d 654 u8 *dip, int size)
079d88cc 655{
079d88cc
WF		 656 int i;
657
658 hdmi_debug_dip_size(codec, pin_nid);
659 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
660
079d88cc 661 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 662 for (i = 0; i < size; i++)
663 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 664}
665
666static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 667 u8 *dip, int size)
079d88cc 668{
079d88cc
WF		 669 u8 val;
670 int i;
671
672 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
673 != AC_DIPXMIT_BEST)
674 return false;
675
676 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 677 for (i = 0; i < size; i++) {
079d88cc
WF		 678 val = snd_hda_codec_read(codec, pin_nid, 0,
679 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 680 if (val != dip[i])
079d88cc
WF		 681 return false;
682 }
683
684 return true;
685}
686
384a48d7 687static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
079d88cc
WF		 688 struct snd_pcm_substream *substream)
689{
690 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 691 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
692 hda_nid_t pin_nid = per_pin->pin_nid;
53d7d69d 693 int channels = substream->runtime->channels;
384a48d7 694 struct hdmi_eld *eld;
53d7d69d 695 int ca;
2b203dbb 696 union audio_infoframe ai;
079d88cc 697
384a48d7
SW		 698 eld = &spec->pins[pin_idx].sink_eld;
699 if (!eld->monitor_present)
700 return;
079d88cc 701
384a48d7
SW		 702 ca = hdmi_channel_allocation(eld, channels);
703
704 memset(&ai, 0, sizeof(ai));
705 if (eld->conn_type == 0) { /* HDMI */
706 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
707
708 hdmi_ai->type = 0x84;
709 hdmi_ai->ver = 0x01;
710 hdmi_ai->len = 0x0a;
711 hdmi_ai->CC02_CT47 = channels - 1;
712 hdmi_ai->CA = ca;
713 hdmi_checksum_audio_infoframe(hdmi_ai);
714 } else if (eld->conn_type == 1) { /* DisplayPort */
715 struct dp_audio_infoframe *dp_ai = &ai.dp;
716
717 dp_ai->type = 0x84;
718 dp_ai->len = 0x1b;
719 dp_ai->ver = 0x11 << 2;
720 dp_ai->CC02_CT47 = channels - 1;
721 dp_ai->CA = ca;
722 } else {
723 snd_printd("HDMI: unknown connection type at pin %d\n",
724 pin_nid);
725 return;
726 }
53d7d69d 727
384a48d7
SW		 728 /*
729 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
730 * sizeof(*dp_ai) to avoid partial match/update problems when
731 * the user switches between HDMI/DP monitors.
732 */
733 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
734 sizeof(ai))) {
735 snd_printdd("hdmi_setup_audio_infoframe: "
736 "pin=%d channels=%d\n",
737 pin_nid,
738 channels);
739 hdmi_setup_channel_mapping(codec, pin_nid, ca);
740 hdmi_stop_infoframe_trans(codec, pin_nid);
741 hdmi_fill_audio_infoframe(codec, pin_nid,
742 ai.bytes, sizeof(ai));
743 hdmi_start_infoframe_trans(codec, pin_nid);
079d88cc
WF		 744 }
745}
746
747
748/*
749 * Unsolicited events
750 */
751
744626da 752static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, bool retry);
38faddb1 753
079d88cc
WF		 754static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
755{
756 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 757 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
758 int pin_nid;
5d44f927 759 int pd = !!(res & AC_UNSOL_RES_PD);
079d88cc 760 int eldv = !!(res & AC_UNSOL_RES_ELDV);
384a48d7 761 int pin_idx;
3a93897e
TI		 762 struct hda_jack_tbl *jack;
763
764 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
765 if (!jack)
766 return;
767 pin_nid = jack->nid;
768 jack->jack_dirty = 1;
079d88cc
WF		 769
770 printk(KERN_INFO
384a48d7
SW		 771 "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
772 codec->addr, pin_nid, pd, eldv);
079d88cc 773
384a48d7
SW		 774 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
775 if (pin_idx < 0)
079d88cc
WF		 776 return;
777
744626da 778 hdmi_present_sense(&spec->pins[pin_idx], true);
01a61e12 779 snd_hda_jack_report_sync(codec);
079d88cc
WF		 780}
781
782static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
783{
784 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
785 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
786 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
787 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
788
789 printk(KERN_INFO
384a48d7
SW		 790 "HDMI CP event: CODEC=%d PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
791 codec->addr,
079d88cc
WF		 792 tag,
793 subtag,
794 cp_state,
795 cp_ready);
796
797 /* TODO */
798 if (cp_state)
799 ;
800 if (cp_ready)
801 ;
802}
803
804
805static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
806{
807 struct hdmi_spec *spec = codec->spec;
808 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
809 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
810
3a93897e 811 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 812 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
813 return;
814 }
815
816 if (subtag == 0)
817 hdmi_intrinsic_event(codec, res);
818 else
819 hdmi_non_intrinsic_event(codec, res);
820}
821
822/*
823 * Callbacks
824 */
825
92f10b3f
TI		 826/* HBR should be Non-PCM, 8 channels */
827#define is_hbr_format(format) \
828 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
829
384a48d7
SW		 830static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
831 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 832{
ea87d1c4
AH		 833 int pinctl;
834 int new_pinctl = 0;
ea87d1c4 835
384a48d7
SW		 836 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
837 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 838 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
839
840 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 841 if (is_hbr_format(format))
ea87d1c4
AH		 842 new_pinctl |= AC_PINCTL_EPT_HBR;
843 else
844 new_pinctl |= AC_PINCTL_EPT_NATIVE;
845
846 snd_printdd("hdmi_setup_stream: "
847 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 848 pin_nid,
ea87d1c4
AH		 849 pinctl == new_pinctl ? "" : "new-",
850 new_pinctl);
851
852 if (pinctl != new_pinctl)
384a48d7 853 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 854 AC_VERB_SET_PIN_WIDGET_CONTROL,
855 new_pinctl);
ea87d1c4 856
384a48d7 857 }
92f10b3f 858 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 859 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
860 return -EINVAL;
861 }
079d88cc 862
384a48d7 863 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 864 return 0;
079d88cc
WF		 865}
866
bbbe3390
TI		 867/*
868 * HDA PCM callbacks
869 */
870static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
871 struct hda_codec *codec,
872 struct snd_pcm_substream *substream)
873{
874 struct hdmi_spec *spec = codec->spec;
639cef0e 875 struct snd_pcm_runtime *runtime = substream->runtime;
384a48d7
SW		 876 int pin_idx, cvt_idx, mux_idx = 0;
877 struct hdmi_spec_per_pin *per_pin;
878 struct hdmi_eld *eld;
879 struct hdmi_spec_per_cvt *per_cvt = NULL;
880 int pinctl;
bbbe3390 881
384a48d7
SW		 882 /* Validate hinfo */
883 pin_idx = hinfo_to_pin_index(spec, hinfo);
884 if (snd_BUG_ON(pin_idx < 0))
bbbe3390 885 return -EINVAL;
384a48d7
SW		 886 per_pin = &spec->pins[pin_idx];
887 eld = &per_pin->sink_eld;
888
889 /* Dynamically assign converter to stream */
890 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
891 per_cvt = &spec->cvts[cvt_idx];
bbbe3390 892
384a48d7
SW		 893 /* Must not already be assigned */
894 if (per_cvt->assigned)
895 continue;
896 /* Must be in pin's mux's list of converters */
897 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
898 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
899 break;
900 /* Not in mux list */
901 if (mux_idx == per_pin->num_mux_nids)
902 continue;
903 break;
904 }
905 /* No free converters */
906 if (cvt_idx == spec->num_cvts)
907 return -ENODEV;
908
909 /* Claim converter */
910 per_cvt->assigned = 1;
911 hinfo->nid = per_cvt->cvt_nid;
912
913 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
914 AC_VERB_SET_CONNECT_SEL,
915 mux_idx);
916 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
917 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
918 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
919 AC_VERB_SET_PIN_WIDGET_CONTROL,
920 pinctl | PIN_OUT);
921 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 922
2def8172 923 /* Initially set the converter's capabilities */
384a48d7
SW		 924 hinfo->channels_min = per_cvt->channels_min;
925 hinfo->channels_max = per_cvt->channels_max;
926 hinfo->rates = per_cvt->rates;
927 hinfo->formats = per_cvt->formats;
928 hinfo->maxbps = per_cvt->maxbps;
2def8172 929
384a48d7 930 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 931 if (!static_hdmi_pcm && eld->eld_valid) {
2def8172 932 snd_hdmi_eld_update_pcm_info(eld, hinfo);
bbbe3390
TI		 933 if (hinfo->channels_min > hinfo->channels_max ||
934 !hinfo->rates || !hinfo->formats)
935 return -ENODEV;
bbbe3390 936 }
2def8172
SW		 937
938 /* Store the updated parameters */
639cef0e
TI		 939 runtime->hw.channels_min = hinfo->channels_min;
940 runtime->hw.channels_max = hinfo->channels_max;
941 runtime->hw.formats = hinfo->formats;
942 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 943
944 snd_pcm_hw_constraint_step(substream->runtime, 0,
945 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 946 return 0;
947}
948
079d88cc
WF		 949/*
950 * HDA/HDMI auto parsing
951 */
384a48d7 952static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 953{
954 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 955 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
956 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 957
958 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
959 snd_printk(KERN_WARNING
960 "HDMI: pin %d wcaps %#x "
961 "does not support connection list\n",
962 pin_nid, get_wcaps(codec, pin_nid));
963 return -EINVAL;
964 }
965
384a48d7
SW		 966 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
967 per_pin->mux_nids,
968 HDA_MAX_CONNECTIONS);
079d88cc
WF		 969
970 return 0;
971}
972
744626da 973static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, bool retry)
079d88cc 974{
744626da
WF		 975 struct hda_codec *codec = per_pin->codec;
976 struct hdmi_eld *eld = &per_pin->sink_eld;
977 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 978 /*
979 * Always execute a GetPinSense verb here, even when called from
980 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
981 * response's PD bit is not the real PD value, but indicates that
982 * the real PD value changed. An older version of the HD-audio
983 * specification worked this way. Hence, we just ignore the data in
984 * the unsolicited response to avoid custom WARs.
985 */
079d88cc 986 int present = snd_hda_pin_sense(codec, pin_nid);
b95d68b8 987 bool eld_valid = false;
079d88cc 988
b95d68b8 989 memset(eld, 0, offsetof(struct hdmi_eld, eld_buffer));
5d44f927 990
079d88cc 991 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
5d44f927 992 if (eld->monitor_present)
b95d68b8 993 eld_valid = !!(present & AC_PINSENSE_ELDV);
079d88cc 994
5d44f927 995 printk(KERN_INFO
384a48d7 996 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
b95d68b8 997 codec->addr, pin_nid, eld->monitor_present, eld_valid);
5d44f927 998
744626da 999 if (eld_valid) {
5d44f927
SW		 1000 if (!snd_hdmi_get_eld(eld, codec, pin_nid))
1001 snd_hdmi_show_eld(eld);
744626da
WF		 1002 else if (retry) {
1003 queue_delayed_work(codec->bus->workq,
1004 &per_pin->work,
1005 msecs_to_jiffies(300));
1006 }
1007 }
5d44f927
SW		 1008
1009 snd_hda_input_jack_report(codec, pin_nid);
079d88cc
WF		 1010}
1011
744626da
WF		 1012static void hdmi_repoll_eld(struct work_struct *work)
1013{
1014 struct hdmi_spec_per_pin *per_pin =
1015 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1016
1017 hdmi_present_sense(per_pin, false);
1018}
1019
079d88cc
WF		 1020static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1021{
1022 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1023 unsigned int caps, config;
1024 int pin_idx;
1025 struct hdmi_spec_per_pin *per_pin;
07acecc1 1026 int err;
079d88cc 1027
384a48d7
SW		 1028 caps = snd_hda_param_read(codec, pin_nid, AC_PAR_PIN_CAP);
1029 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1030 return 0;
1031
1032 config = snd_hda_codec_read(codec, pin_nid, 0,
1033 AC_VERB_GET_CONFIG_DEFAULT, 0);
1034 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1035 return 0;
1036
1037 if (snd_BUG_ON(spec->num_pins >= MAX_HDMI_PINS))
3eaead57 1038 return -E2BIG;
384a48d7
SW		 1039
1040 pin_idx = spec->num_pins;
1041 per_pin = &spec->pins[pin_idx];
384a48d7
SW		 1042
1043 per_pin->pin_nid = pin_nid;
079d88cc 1044
384a48d7
SW		 1045 err = hdmi_read_pin_conn(codec, pin_idx);
1046 if (err < 0)
1047 return err;
079d88cc 1048
079d88cc
WF		 1049 spec->num_pins++;
1050
384a48d7 1051 return 0;
079d88cc
WF		 1052}
1053
384a48d7 1054static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1055{
1056 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1057 int cvt_idx;
1058 struct hdmi_spec_per_cvt *per_cvt;
1059 unsigned int chans;
1060 int err;
079d88cc 1061
116dcde6
DH		 1062 if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
1063 return -E2BIG;
1064
384a48d7
SW		 1065 chans = get_wcaps(codec, cvt_nid);
1066 chans = get_wcaps_channels(chans);
1067
1068 cvt_idx = spec->num_cvts;
1069 per_cvt = &spec->cvts[cvt_idx];
1070
1071 per_cvt->cvt_nid = cvt_nid;
1072 per_cvt->channels_min = 2;
1073 if (chans <= 16)
1074 per_cvt->channels_max = chans;
1075
1076 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1077 &per_cvt->rates,
1078 &per_cvt->formats,
1079 &per_cvt->maxbps);
1080 if (err < 0)
1081 return err;
1082
079d88cc
WF		 1083 spec->num_cvts++;
1084
1085 return 0;
1086}
1087
1088static int hdmi_parse_codec(struct hda_codec *codec)
1089{
1090 hda_nid_t nid;
1091 int i, nodes;
1092
1093 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1094 if (!nid || nodes < 0) {
1095 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1096 return -EINVAL;
1097 }
1098
1099 for (i = 0; i < nodes; i++, nid++) {
1100 unsigned int caps;
1101 unsigned int type;
1102
1103 caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP);
1104 type = get_wcaps_type(caps);
1105
1106 if (!(caps & AC_WCAP_DIGITAL))
1107 continue;
1108
1109 switch (type) {
1110 case AC_WID_AUD_OUT:
384a48d7 1111 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1112 break;
1113 case AC_WID_PIN:
3eaead57 1114 hdmi_add_pin(codec, nid);
079d88cc
WF		 1115 break;
1116 }
1117 }
1118
1119 /*
1120 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1121 * can be lost and presence sense verb will become inaccurate if the
1122 * HDA link is powered off at hot plug or hw initialization time.
1123 */
1124#ifdef CONFIG_SND_HDA_POWER_SAVE
1125 if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
1126 AC_PWRST_EPSS))
1127 codec->bus->power_keep_link_on = 1;
1128#endif
1129
1130 return 0;
1131}
1132
84eb01be
TI		 1133/*
1134 */
384a48d7 1135static char *generic_hdmi_pcm_names[MAX_HDMI_PINS] = {
84eb01be
TI		 1136 "HDMI 0",
1137 "HDMI 1",
1138 "HDMI 2",
73926656 1139 "HDMI 3",
84eb01be
TI		 1140};
1141
1142/*
1143 * HDMI callbacks
1144 */
1145
1146static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1147 struct hda_codec *codec,
1148 unsigned int stream_tag,
1149 unsigned int format,
1150 struct snd_pcm_substream *substream)
1151{
384a48d7
SW		 1152 hda_nid_t cvt_nid = hinfo->nid;
1153 struct hdmi_spec *spec = codec->spec;
1154 int pin_idx = hinfo_to_pin_index(spec, hinfo);
1155 hda_nid_t pin_nid = spec->pins[pin_idx].pin_nid;
1156
1157 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
84eb01be 1158
384a48d7 1159 hdmi_setup_audio_infoframe(codec, pin_idx, substream);
84eb01be 1160
384a48d7 1161 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1162}
1163
384a48d7
SW		 1164static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1165 struct hda_codec *codec,
1166 struct snd_pcm_substream *substream)
1167{
1168 struct hdmi_spec *spec = codec->spec;
1169 int cvt_idx, pin_idx;
1170 struct hdmi_spec_per_cvt *per_cvt;
1171 struct hdmi_spec_per_pin *per_pin;
1172 int pinctl;
1173
1174 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1175
1176 if (hinfo->nid) {
1177 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1178 if (snd_BUG_ON(cvt_idx < 0))
1179 return -EINVAL;
1180 per_cvt = &spec->cvts[cvt_idx];
1181
1182 snd_BUG_ON(!per_cvt->assigned);
1183 per_cvt->assigned = 0;
1184 hinfo->nid = 0;
1185
1186 pin_idx = hinfo_to_pin_index(spec, hinfo);
1187 if (snd_BUG_ON(pin_idx < 0))
1188 return -EINVAL;
1189 per_pin = &spec->pins[pin_idx];
1190
1191 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1192 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1193 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1194 AC_VERB_SET_PIN_WIDGET_CONTROL,
1195 pinctl & ~PIN_OUT);
1196 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1197 }
1198
1199 return 0;
1200}
1201
1202static const struct hda_pcm_ops generic_ops = {
1203 .open = hdmi_pcm_open,
1204 .prepare = generic_hdmi_playback_pcm_prepare,
1205 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1206};
1207
1208static int generic_hdmi_build_pcms(struct hda_codec *codec)
1209{
1210 struct hdmi_spec *spec = codec->spec;
384a48d7 1211 int pin_idx;
84eb01be 1212
384a48d7
SW		 1213 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1214 struct hda_pcm *info;
84eb01be
TI		 1215 struct hda_pcm_stream *pstr;
1216
384a48d7
SW		 1217 info = &spec->pcm_rec[pin_idx];
1218 info->name = generic_hdmi_pcm_names[pin_idx];
84eb01be 1219 info->pcm_type = HDA_PCM_TYPE_HDMI;
384a48d7 1220
84eb01be 1221 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1222 pstr->substreams = 1;
1223 pstr->ops = generic_ops;
1224 /* other pstr fields are set in open */
84eb01be
TI		 1225 }
1226
384a48d7
SW		 1227 codec->num_pcms = spec->num_pins;
1228 codec->pcm_info = spec->pcm_rec;
1229
84eb01be
TI		 1230 return 0;
1231}
1232
0b6c49b5
DH		 1233static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1234{
1235 int err;
1236 char hdmi_str[32];
1237 struct hdmi_spec *spec = codec->spec;
1238 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1239 int pcmdev = spec->pcm_rec[pin_idx].device;
1240
1241 snprintf(hdmi_str, sizeof(hdmi_str), "HDMI/DP,pcm=%d", pcmdev);
1242
1243 err = snd_hda_input_jack_add(codec, per_pin->pin_nid,
1244 SND_JACK_VIDEOOUT, pcmdev > 0 ? hdmi_str : NULL);
1245 if (err < 0)
1246 return err;
1247
744626da 1248 hdmi_present_sense(per_pin, false);
0b6c49b5
DH		 1249 return 0;
1250}
1251
84eb01be
TI		 1252static int generic_hdmi_build_controls(struct hda_codec *codec)
1253{
1254 struct hdmi_spec *spec = codec->spec;
1255 int err;
384a48d7 1256 int pin_idx;
84eb01be 1257
384a48d7
SW		 1258 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1259 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
0b6c49b5
DH		 1260
1261 err = generic_hdmi_build_jack(codec, pin_idx);
1262 if (err < 0)
1263 return err;
1264
384a48d7
SW		 1265 err = snd_hda_create_spdif_out_ctls(codec,
1266 per_pin->pin_nid,
1267 per_pin->mux_nids[0]);
84eb01be
TI		 1268 if (err < 0)
1269 return err;
384a48d7 1270 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1271
1272 /* add control for ELD Bytes */
1273 err = hdmi_create_eld_ctl(codec,
1274 pin_idx,
1275 spec->pcm_rec[pin_idx].device);
1276
1277 if (err < 0)
1278 return err;
01a61e12
TI		 1279 err = snd_hda_jack_add_kctl(codec, per_pin->pin_nid,
1280 "HDMI", pin_idx);
1281 if (err < 0)
1282 return err;
84eb01be
TI		 1283 }
1284
1285 return 0;
1286}
1287
1288static int generic_hdmi_init(struct hda_codec *codec)
1289{
1290 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1291 int pin_idx;
1292
1293 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1294 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1295 hda_nid_t pin_nid = per_pin->pin_nid;
1296 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1297
384a48d7 1298 hdmi_init_pin(codec, pin_nid);
1835a0f9 1299 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
384a48d7 1300
744626da
WF		 1301 per_pin->codec = codec;
1302 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
384a48d7 1303 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be 1304 }
01a61e12 1305 snd_hda_jack_report_sync(codec);
84eb01be
TI		 1306 return 0;
1307}
1308
1309static void generic_hdmi_free(struct hda_codec *codec)
1310{
1311 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1312 int pin_idx;
1313
1314 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1315 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1316 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1317
744626da 1318 cancel_delayed_work(&per_pin->work);
384a48d7
SW		 1319 snd_hda_eld_proc_free(codec, eld);
1320 }
84eb01be 1321
744626da 1322 flush_workqueue(codec->bus->workq);
84eb01be
TI		 1323 kfree(spec);
1324}
1325
fb79e1e0 1326static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1327 .init = generic_hdmi_init,
1328 .free = generic_hdmi_free,
1329 .build_pcms = generic_hdmi_build_pcms,
1330 .build_controls = generic_hdmi_build_controls,
1331 .unsol_event = hdmi_unsol_event,
1332};
1333
1334static int patch_generic_hdmi(struct hda_codec *codec)
1335{
1336 struct hdmi_spec *spec;
84eb01be
TI		 1337
1338 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1339 if (spec == NULL)
1340 return -ENOMEM;
1341
1342 codec->spec = spec;
1343 if (hdmi_parse_codec(codec) < 0) {
1344 codec->spec = NULL;
1345 kfree(spec);
1346 return -EINVAL;
1347 }
1348 codec->patch_ops = generic_hdmi_patch_ops;
1349
84eb01be
TI		 1350 init_channel_allocations();
1351
1352 return 0;
1353}
1354
3aaf8980
SW		 1355/*
1356 * Shared non-generic implementations
1357 */
1358
1359static int simple_playback_build_pcms(struct hda_codec *codec)
1360{
1361 struct hdmi_spec *spec = codec->spec;
1362 struct hda_pcm *info = spec->pcm_rec;
1363 int i;
1364
1365 codec->num_pcms = spec->num_cvts;
1366 codec->pcm_info = info;
1367
1368 for (i = 0; i < codec->num_pcms; i++, info++) {
1369 unsigned int chans;
1370 struct hda_pcm_stream *pstr;
1371
384a48d7 1372 chans = get_wcaps(codec, spec->cvts[i].cvt_nid);
3aaf8980
SW		 1373 chans = get_wcaps_channels(chans);
1374
1375 info->name = generic_hdmi_pcm_names[i];
1376 info->pcm_type = HDA_PCM_TYPE_HDMI;
1377 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1378 snd_BUG_ON(!spec->pcm_playback);
1379 *pstr = *spec->pcm_playback;
384a48d7 1380 pstr->nid = spec->cvts[i].cvt_nid;
3aaf8980
SW		 1381 if (pstr->channels_max <= 2 && chans && chans <= 16)
1382 pstr->channels_max = chans;
1383 }
1384
1385 return 0;
1386}
1387
1388static int simple_playback_build_controls(struct hda_codec *codec)
1389{
1390 struct hdmi_spec *spec = codec->spec;
1391 int err;
1392 int i;
1393
1394 for (i = 0; i < codec->num_pcms; i++) {
1395 err = snd_hda_create_spdif_out_ctls(codec,
384a48d7
SW		 1396 spec->cvts[i].cvt_nid,
1397 spec->cvts[i].cvt_nid);
3aaf8980
SW		 1398 if (err < 0)
1399 return err;
1400 }
1401
1402 return 0;
1403}
1404
1405static void simple_playback_free(struct hda_codec *codec)
1406{
1407 struct hdmi_spec *spec = codec->spec;
1408
1409 kfree(spec);
1410}
1411
84eb01be
TI		 1412/*
1413 * Nvidia specific implementations
1414 */
1415
1416#define Nv_VERB_SET_Channel_Allocation 0xF79
1417#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1418#define Nv_VERB_SET_Audio_Protection_On 0xF98
1419#define Nv_VERB_SET_Audio_Protection_Off 0xF99
1420
1421#define nvhdmi_master_con_nid_7x 0x04
1422#define nvhdmi_master_pin_nid_7x 0x05
1423
fb79e1e0 1424static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 1425 /*front, rear, clfe, rear_surr */
1426 0x6, 0x8, 0xa, 0xc,
1427};
1428
fb79e1e0 1429static const struct hda_verb nvhdmi_basic_init_7x[] = {
84eb01be
TI		 1430 /* set audio protect on */
1431 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1432 /* enable digital output on pin widget */
1433 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1434 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1435 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1436 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1437 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1438 {} /* terminator */
1439};
1440
1441#ifdef LIMITED_RATE_FMT_SUPPORT
1442/* support only the safe format and rate */
1443#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1444#define SUPPORTED_MAXBPS 16
1445#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1446#else
1447/* support all rates and formats */
1448#define SUPPORTED_RATES \
1449 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1450 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1451 SNDRV_PCM_RATE_192000)
1452#define SUPPORTED_MAXBPS 24
1453#define SUPPORTED_FORMATS \
1454 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1455#endif
1456
1457static int nvhdmi_7x_init(struct hda_codec *codec)
1458{
1459 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x);
1460 return 0;
1461}
1462
393004b2
ND		 1463static unsigned int channels_2_6_8[] = {
1464 2, 6, 8
1465};
1466
1467static unsigned int channels_2_8[] = {
1468 2, 8
1469};
1470
1471static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
1472 .count = ARRAY_SIZE(channels_2_6_8),
1473 .list = channels_2_6_8,
1474 .mask = 0,
1475};
1476
1477static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
1478 .count = ARRAY_SIZE(channels_2_8),
1479 .list = channels_2_8,
1480 .mask = 0,
1481};
1482
84eb01be
TI		 1483static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
1484 struct hda_codec *codec,
1485 struct snd_pcm_substream *substream)
1486{
1487 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 1488 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
1489
1490 switch (codec->preset->id) {
1491 case 0x10de0002:
1492 case 0x10de0003:
1493 case 0x10de0005:
1494 case 0x10de0006:
1495 hw_constraints_channels = &hw_constraints_2_8_channels;
1496 break;
1497 case 0x10de0007:
1498 hw_constraints_channels = &hw_constraints_2_6_8_channels;
1499 break;
1500 default:
1501 break;
1502 }
1503
1504 if (hw_constraints_channels != NULL) {
1505 snd_pcm_hw_constraint_list(substream->runtime, 0,
1506 SNDRV_PCM_HW_PARAM_CHANNELS,
1507 hw_constraints_channels);
ad09fc9d
TI		 1508 } else {
1509 snd_pcm_hw_constraint_step(substream->runtime, 0,
1510 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 1511 }
1512
84eb01be
TI		 1513 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
1514}
1515
1516static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
1517 struct hda_codec *codec,
1518 struct snd_pcm_substream *substream)
1519{
1520 struct hdmi_spec *spec = codec->spec;
1521 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1522}
1523
1524static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1525 struct hda_codec *codec,
1526 unsigned int stream_tag,
1527 unsigned int format,
1528 struct snd_pcm_substream *substream)
1529{
1530 struct hdmi_spec *spec = codec->spec;
1531 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
1532 stream_tag, format, substream);
1533}
1534
1f348522
AP		 1535static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
1536 int channels)
1537{
1538 unsigned int chanmask;
1539 int chan = channels ? (channels - 1) : 1;
1540
1541 switch (channels) {
1542 default:
1543 case 0:
1544 case 2:
1545 chanmask = 0x00;
1546 break;
1547 case 4:
1548 chanmask = 0x08;
1549 break;
1550 case 6:
1551 chanmask = 0x0b;
1552 break;
1553 case 8:
1554 chanmask = 0x13;
1555 break;
1556 }
1557
1558 /* Set the audio infoframe channel allocation and checksum fields. The
1559 * channel count is computed implicitly by the hardware. */
1560 snd_hda_codec_write(codec, 0x1, 0,
1561 Nv_VERB_SET_Channel_Allocation, chanmask);
1562
1563 snd_hda_codec_write(codec, 0x1, 0,
1564 Nv_VERB_SET_Info_Frame_Checksum,
1565 (0x71 - chan - chanmask));
1566}
1567
84eb01be
TI		 1568static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
1569 struct hda_codec *codec,
1570 struct snd_pcm_substream *substream)
1571{
1572 struct hdmi_spec *spec = codec->spec;
1573 int i;
1574
1575 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
1576 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
1577 for (i = 0; i < 4; i++) {
1578 /* set the stream id */
1579 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1580 AC_VERB_SET_CHANNEL_STREAMID, 0);
1581 /* set the stream format */
1582 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1583 AC_VERB_SET_STREAM_FORMAT, 0);
1584 }
1585
1f348522
AP		 1586 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
1587 * streams are disabled. */
1588 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
1589
84eb01be
TI		 1590 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1591}
1592
1593static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
1594 struct hda_codec *codec,
1595 unsigned int stream_tag,
1596 unsigned int format,
1597 struct snd_pcm_substream *substream)
1598{
1599 int chs;
112daa7a 1600 unsigned int dataDCC2, channel_id;
84eb01be 1601 int i;
7c935976
SW		 1602 struct hdmi_spec *spec = codec->spec;
1603 struct hda_spdif_out *spdif =
384a48d7 1604 snd_hda_spdif_out_of_nid(codec, spec->cvts[0].cvt_nid);
84eb01be
TI		 1605
1606 mutex_lock(&codec->spdif_mutex);
1607
1608 chs = substream->runtime->channels;
84eb01be 1609
84eb01be
TI		 1610 dataDCC2 = 0x2;
1611
84eb01be 1612 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 1613 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 1614 snd_hda_codec_write(codec,
1615 nvhdmi_master_con_nid_7x,
1616 0,
1617 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1618 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 1619
1620 /* set the stream id */
1621 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1622 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
1623
1624 /* set the stream format */
1625 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1626 AC_VERB_SET_STREAM_FORMAT, format);
1627
1628 /* turn on again (if needed) */
1629 /* enable and set the channel status audio/data flag */
7c935976 1630 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 1631 snd_hda_codec_write(codec,
1632 nvhdmi_master_con_nid_7x,
1633 0,
1634 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1635 spdif->ctls & 0xff);
84eb01be
TI		 1636 snd_hda_codec_write(codec,
1637 nvhdmi_master_con_nid_7x,
1638 0,
1639 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1640 }
1641
1642 for (i = 0; i < 4; i++) {
1643 if (chs == 2)
1644 channel_id = 0;
1645 else
1646 channel_id = i * 2;
1647
1648 /* turn off SPDIF once;
1649 *otherwise the IEC958 bits won't be updated
1650 */
1651 if (codec->spdif_status_reset &&
7c935976 1652 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 1653 snd_hda_codec_write(codec,
1654 nvhdmi_con_nids_7x[i],
1655 0,
1656 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1657 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 1658 /* set the stream id */
1659 snd_hda_codec_write(codec,
1660 nvhdmi_con_nids_7x[i],
1661 0,
1662 AC_VERB_SET_CHANNEL_STREAMID,
1663 (stream_tag << 4) | channel_id);
1664 /* set the stream format */
1665 snd_hda_codec_write(codec,
1666 nvhdmi_con_nids_7x[i],
1667 0,
1668 AC_VERB_SET_STREAM_FORMAT,
1669 format);
1670 /* turn on again (if needed) */
1671 /* enable and set the channel status audio/data flag */
1672 if (codec->spdif_status_reset &&
7c935976 1673 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 1674 snd_hda_codec_write(codec,
1675 nvhdmi_con_nids_7x[i],
1676 0,
1677 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1678 spdif->ctls & 0xff);
84eb01be
TI		 1679 snd_hda_codec_write(codec,
1680 nvhdmi_con_nids_7x[i],
1681 0,
1682 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1683 }
1684 }
1685
1f348522 1686 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 1687
1688 mutex_unlock(&codec->spdif_mutex);
1689 return 0;
1690}
1691
fb79e1e0 1692static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 1693 .substreams = 1,
1694 .channels_min = 2,
1695 .channels_max = 8,
1696 .nid = nvhdmi_master_con_nid_7x,
1697 .rates = SUPPORTED_RATES,
1698 .maxbps = SUPPORTED_MAXBPS,
1699 .formats = SUPPORTED_FORMATS,
1700 .ops = {
1701 .open = simple_playback_pcm_open,
1702 .close = nvhdmi_8ch_7x_pcm_close,
1703 .prepare = nvhdmi_8ch_7x_pcm_prepare
1704 },
1705};
1706
fb79e1e0 1707static const struct hda_pcm_stream nvhdmi_pcm_playback_2ch = {
84eb01be
TI		 1708 .substreams = 1,
1709 .channels_min = 2,
1710 .channels_max = 2,
1711 .nid = nvhdmi_master_con_nid_7x,
1712 .rates = SUPPORTED_RATES,
1713 .maxbps = SUPPORTED_MAXBPS,
1714 .formats = SUPPORTED_FORMATS,
1715 .ops = {
1716 .open = simple_playback_pcm_open,
1717 .close = simple_playback_pcm_close,
1718 .prepare = simple_playback_pcm_prepare
1719 },
1720};
1721
fb79e1e0 1722static const struct hda_codec_ops nvhdmi_patch_ops_8ch_7x = {
3aaf8980
SW		 1723 .build_controls = simple_playback_build_controls,
1724 .build_pcms = simple_playback_build_pcms,
84eb01be 1725 .init = nvhdmi_7x_init,
3aaf8980 1726 .free = simple_playback_free,
84eb01be
TI		 1727};
1728
fb79e1e0 1729static const struct hda_codec_ops nvhdmi_patch_ops_2ch = {
3aaf8980
SW		 1730 .build_controls = simple_playback_build_controls,
1731 .build_pcms = simple_playback_build_pcms,
84eb01be 1732 .init = nvhdmi_7x_init,
3aaf8980 1733 .free = simple_playback_free,
84eb01be
TI		 1734};
1735
84eb01be
TI		 1736static int patch_nvhdmi_2ch(struct hda_codec *codec)
1737{
1738 struct hdmi_spec *spec;
1739
1740 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1741 if (spec == NULL)
1742 return -ENOMEM;
1743
1744 codec->spec = spec;
1745
1746 spec->multiout.num_dacs = 0; /* no analog */
1747 spec->multiout.max_channels = 2;
1748 spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x;
84eb01be 1749 spec->num_cvts = 1;
384a48d7 1750 spec->cvts[0].cvt_nid = nvhdmi_master_con_nid_7x;
84eb01be
TI		 1751 spec->pcm_playback = &nvhdmi_pcm_playback_2ch;
1752
1753 codec->patch_ops = nvhdmi_patch_ops_2ch;
1754
1755 return 0;
1756}
1757
1758static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
1759{
1760 struct hdmi_spec *spec;
1761 int err = patch_nvhdmi_2ch(codec);
1762
1763 if (err < 0)
1764 return err;
1765 spec = codec->spec;
1766 spec->multiout.max_channels = 8;
1767 spec->pcm_playback = &nvhdmi_pcm_playback_8ch_7x;
1768 codec->patch_ops = nvhdmi_patch_ops_8ch_7x;
1f348522
AP		 1769
1770 /* Initialize the audio infoframe channel mask and checksum to something
1771 * valid */
1772 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
1773
84eb01be
TI		 1774 return 0;
1775}
1776
1777/*
1778 * ATI-specific implementations
1779 *
1780 * FIXME: we may omit the whole this and use the generic code once after
1781 * it's confirmed to work.
1782 */
1783
1784#define ATIHDMI_CVT_NID 0x02 /* audio converter */
1785#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
1786
1787static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1788 struct hda_codec *codec,
1789 unsigned int stream_tag,
1790 unsigned int format,
1791 struct snd_pcm_substream *substream)
1792{
1793 struct hdmi_spec *spec = codec->spec;
1794 int chans = substream->runtime->channels;
1795 int i, err;
1796
1797 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
1798 substream);
1799 if (err < 0)
1800 return err;
384a48d7
SW		 1801 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
1802 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 1803 /* FIXME: XXX */
1804 for (i = 0; i < chans; i++) {
384a48d7 1805 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
84eb01be
TI		 1806 AC_VERB_SET_HDMI_CHAN_SLOT,
1807 (i << 4) | i);
1808 }
1809 return 0;
1810}
1811
fb79e1e0 1812static const struct hda_pcm_stream atihdmi_pcm_digital_playback = {
84eb01be
TI		 1813 .substreams = 1,
1814 .channels_min = 2,
1815 .channels_max = 2,
1816 .nid = ATIHDMI_CVT_NID,
1817 .ops = {
1818 .open = simple_playback_pcm_open,
1819 .close = simple_playback_pcm_close,
1820 .prepare = atihdmi_playback_pcm_prepare
1821 },
1822};
1823
fb79e1e0 1824static const struct hda_verb atihdmi_basic_init[] = {
84eb01be
TI		 1825 /* enable digital output on pin widget */
1826 { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT },
1827 {} /* terminator */
1828};
1829
1830static int atihdmi_init(struct hda_codec *codec)
1831{
1832 struct hdmi_spec *spec = codec->spec;
1833
1834 snd_hda_sequence_write(codec, atihdmi_basic_init);
1835 /* SI codec requires to unmute the pin */
384a48d7
SW		 1836 if (get_wcaps(codec, spec->pins[0].pin_nid) & AC_WCAP_OUT_AMP)
1837 snd_hda_codec_write(codec, spec->pins[0].pin_nid, 0,
84eb01be
TI		 1838 AC_VERB_SET_AMP_GAIN_MUTE,
1839 AMP_OUT_UNMUTE);
1840 return 0;
1841}
1842
fb79e1e0 1843static const struct hda_codec_ops atihdmi_patch_ops = {
3aaf8980
SW		 1844 .build_controls = simple_playback_build_controls,
1845 .build_pcms = simple_playback_build_pcms,
84eb01be 1846 .init = atihdmi_init,
3aaf8980 1847 .free = simple_playback_free,
84eb01be
TI		 1848};
1849
1850
1851static int patch_atihdmi(struct hda_codec *codec)
1852{
1853 struct hdmi_spec *spec;
1854
1855 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1856 if (spec == NULL)
1857 return -ENOMEM;
1858
1859 codec->spec = spec;
1860
1861 spec->multiout.num_dacs = 0; /* no analog */
1862 spec->multiout.max_channels = 2;
1863 spec->multiout.dig_out_nid = ATIHDMI_CVT_NID;
1864 spec->num_cvts = 1;
384a48d7
SW		 1865 spec->cvts[0].cvt_nid = ATIHDMI_CVT_NID;
1866 spec->pins[0].pin_nid = ATIHDMI_PIN_NID;
84eb01be
TI		 1867 spec->pcm_playback = &atihdmi_pcm_digital_playback;
1868
1869 codec->patch_ops = atihdmi_patch_ops;
1870
1871 return 0;
1872}
1873
1874
1875/*
1876 * patch entries
1877 */
fb79e1e0 1878static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 1879{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
1880{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
1881{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 1882{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 1883{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
1884{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
1885{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
1886{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1887{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1888{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1889{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1890{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 1891{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
1892{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
1893{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
1894{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
1895{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
1896{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
1897{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
1898{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
1899{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
1900{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
1901{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 1902/* 17 is known to be absent */
5d44f927
SW		 1903{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
1904{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
1905{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
1906{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
1907{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
1908{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
1909{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
1910{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
1911{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
1912{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 1913{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
1914{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
1915{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1916{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
1917{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
1918{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
1919{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1920{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 1921{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 1922{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
1923{} /* terminator */
1924};
1925
1926MODULE_ALIAS("snd-hda-codec-id:1002793c");
1927MODULE_ALIAS("snd-hda-codec-id:10027919");
1928MODULE_ALIAS("snd-hda-codec-id:1002791a");
1929MODULE_ALIAS("snd-hda-codec-id:1002aa01");
1930MODULE_ALIAS("snd-hda-codec-id:10951390");
1931MODULE_ALIAS("snd-hda-codec-id:10951392");
1932MODULE_ALIAS("snd-hda-codec-id:10de0002");
1933MODULE_ALIAS("snd-hda-codec-id:10de0003");
1934MODULE_ALIAS("snd-hda-codec-id:10de0005");
1935MODULE_ALIAS("snd-hda-codec-id:10de0006");
1936MODULE_ALIAS("snd-hda-codec-id:10de0007");
1937MODULE_ALIAS("snd-hda-codec-id:10de000a");
1938MODULE_ALIAS("snd-hda-codec-id:10de000b");
1939MODULE_ALIAS("snd-hda-codec-id:10de000c");
1940MODULE_ALIAS("snd-hda-codec-id:10de000d");
1941MODULE_ALIAS("snd-hda-codec-id:10de0010");
1942MODULE_ALIAS("snd-hda-codec-id:10de0011");
1943MODULE_ALIAS("snd-hda-codec-id:10de0012");
1944MODULE_ALIAS("snd-hda-codec-id:10de0013");
1945MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 1946MODULE_ALIAS("snd-hda-codec-id:10de0015");
1947MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 1948MODULE_ALIAS("snd-hda-codec-id:10de0018");
1949MODULE_ALIAS("snd-hda-codec-id:10de0019");
1950MODULE_ALIAS("snd-hda-codec-id:10de001a");
1951MODULE_ALIAS("snd-hda-codec-id:10de001b");
1952MODULE_ALIAS("snd-hda-codec-id:10de001c");
1953MODULE_ALIAS("snd-hda-codec-id:10de0040");
1954MODULE_ALIAS("snd-hda-codec-id:10de0041");
1955MODULE_ALIAS("snd-hda-codec-id:10de0042");
1956MODULE_ALIAS("snd-hda-codec-id:10de0043");
1957MODULE_ALIAS("snd-hda-codec-id:10de0044");
1958MODULE_ALIAS("snd-hda-codec-id:10de0067");
1959MODULE_ALIAS("snd-hda-codec-id:10de8001");
1960MODULE_ALIAS("snd-hda-codec-id:17e80047");
1961MODULE_ALIAS("snd-hda-codec-id:80860054");
1962MODULE_ALIAS("snd-hda-codec-id:80862801");
1963MODULE_ALIAS("snd-hda-codec-id:80862802");
1964MODULE_ALIAS("snd-hda-codec-id:80862803");
1965MODULE_ALIAS("snd-hda-codec-id:80862804");
1966MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 1967MODULE_ALIAS("snd-hda-codec-id:80862806");
84eb01be
TI		 1968MODULE_ALIAS("snd-hda-codec-id:808629fb");
1969
1970MODULE_LICENSE("GPL");
1971MODULE_DESCRIPTION("HDMI HD-audio codec");
1972MODULE_ALIAS("snd-hda-codec-intelhdmi");
1973MODULE_ALIAS("snd-hda-codec-nvhdmi");
1974MODULE_ALIAS("snd-hda-codec-atihdmi");
1975
1976static struct hda_codec_preset_list intel_list = {
1977 .preset = snd_hda_preset_hdmi,
1978 .owner = THIS_MODULE,
1979};
1980
1981static int __init patch_hdmi_init(void)
1982{
1983 return snd_hda_add_codec_preset(&intel_list);
1984}
1985
1986static void __exit patch_hdmi_exit(void)
1987{
1988 snd_hda_delete_codec_preset(&intel_list);
1989}
1990
1991module_init(patch_hdmi_init)
1992module_exit(patch_hdmi_exit)
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