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ALSA: hda - Don't refer ELD when unplugged
[mirror_ubuntu-zesty-kernel.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
34#include <sound/core.h>
35#include "hda_codec.h"
36#include "hda_local.h"
37
38/*
39 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
40 * could support two independent pipes, each of them can be connected to one or
41 * more ports (DVI, HDMI or DisplayPort).
42 *
43 * The HDA correspondence of pipes/ports are converter/pin nodes.
44 */
45#define MAX_HDMI_CVTS 3
46#define MAX_HDMI_PINS 3
079d88cc
WF		 47
48struct hdmi_spec {
49 int num_cvts;
50 int num_pins;
51 hda_nid_t cvt[MAX_HDMI_CVTS+1]; /* audio sources */
52 hda_nid_t pin[MAX_HDMI_PINS+1]; /* audio sinks */
53
54 /*
55 * source connection for each pin
56 */
57 hda_nid_t pin_cvt[MAX_HDMI_PINS+1];
58
59 /*
60 * HDMI sink attached to each pin
61 */
62 struct hdmi_eld sink_eld[MAX_HDMI_PINS];
63
64 /*
65 * export one pcm per pipe
66 */
67 struct hda_pcm pcm_rec[MAX_HDMI_CVTS];
bbbe3390 68 struct hda_pcm_stream codec_pcm_pars[MAX_HDMI_CVTS];
079d88cc
WF		 69
70 /*
84eb01be 71 * ati/nvhdmi specific
079d88cc
WF		 72 */
73 struct hda_multi_out multiout;
84eb01be 74 struct hda_pcm_stream *pcm_playback;
38faddb1
TI		 75
76 /* misc flags */
77 /* PD bit indicates only the update, not the current state */
78 unsigned int old_pin_detect:1;
079d88cc
WF		 79};
80
81
82struct hdmi_audio_infoframe {
83 u8 type; /* 0x84 */
84 u8 ver; /* 0x01 */
85 u8 len; /* 0x0a */
86
53d7d69d
WF		 87 u8 checksum;
88
079d88cc
WF		 89 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
90 u8 SS01_SF24;
91 u8 CXT04;
92 u8 CA;
93 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 94};
95
96struct dp_audio_infoframe {
97 u8 type; /* 0x84 */
98 u8 len; /* 0x1b */
99 u8 ver; /* 0x11 << 2 */
100
101 u8 CC02_CT47; /* match with HDMI infoframe from this on */
102 u8 SS01_SF24;
103 u8 CXT04;
104 u8 CA;
105 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 106};
107
108/*
109 * CEA speaker placement:
110 *
111 * FLH FCH FRH
112 * FLW FL FLC FC FRC FR FRW
113 *
114 * LFE
115 * TC
116 *
117 * RL RLC RC RRC RR
118 *
119 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
120 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
121 */
122enum cea_speaker_placement {
123 FL = (1 << 0), /* Front Left */
124 FC = (1 << 1), /* Front Center */
125 FR = (1 << 2), /* Front Right */
126 FLC = (1 << 3), /* Front Left Center */
127 FRC = (1 << 4), /* Front Right Center */
128 RL = (1 << 5), /* Rear Left */
129 RC = (1 << 6), /* Rear Center */
130 RR = (1 << 7), /* Rear Right */
131 RLC = (1 << 8), /* Rear Left Center */
132 RRC = (1 << 9), /* Rear Right Center */
133 LFE = (1 << 10), /* Low Frequency Effect */
134 FLW = (1 << 11), /* Front Left Wide */
135 FRW = (1 << 12), /* Front Right Wide */
136 FLH = (1 << 13), /* Front Left High */
137 FCH = (1 << 14), /* Front Center High */
138 FRH = (1 << 15), /* Front Right High */
139 TC = (1 << 16), /* Top Center */
140};
141
142/*
143 * ELD SA bits in the CEA Speaker Allocation data block
144 */
145static int eld_speaker_allocation_bits[] = {
146 [0] = FL | FR,
147 [1] = LFE,
148 [2] = FC,
149 [3] = RL | RR,
150 [4] = RC,
151 [5] = FLC | FRC,
152 [6] = RLC | RRC,
153 /* the following are not defined in ELD yet */
154 [7] = FLW | FRW,
155 [8] = FLH | FRH,
156 [9] = TC,
157 [10] = FCH,
158};
159
160struct cea_channel_speaker_allocation {
161 int ca_index;
162 int speakers[8];
163
164 /* derived values, just for convenience */
165 int channels;
166 int spk_mask;
167};
168
169/*
170 * ALSA sequence is:
171 *
172 * surround40 surround41 surround50 surround51 surround71
173 * ch0 front left = = = =
174 * ch1 front right = = = =
175 * ch2 rear left = = = =
176 * ch3 rear right = = = =
177 * ch4 LFE center center center
178 * ch5 LFE LFE
179 * ch6 side left
180 * ch7 side right
181 *
182 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
183 */
184static int hdmi_channel_mapping[0x32][8] = {
185 /* stereo */
186 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
187 /* 2.1 */
188 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
189 /* Dolby Surround */
190 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
191 /* surround40 */
192 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
193 /* 4ch */
194 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
195 /* surround41 */
9396d317 196 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 197 /* surround50 */
198 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
199 /* surround51 */
200 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
201 /* 7.1 */
202 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
203};
204
205/*
206 * This is an ordered list!
207 *
208 * The preceding ones have better chances to be selected by
53d7d69d 209 * hdmi_channel_allocation().
079d88cc
WF		 210 */
211static struct cea_channel_speaker_allocation channel_allocations[] = {
212/* channel: 7 6 5 4 3 2 1 0 */
213{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
214 /* 2.1 */
215{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
216 /* Dolby Surround */
217{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
218 /* surround40 */
219{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
220 /* surround41 */
221{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
222 /* surround50 */
223{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
224 /* surround51 */
225{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
226 /* 6.1 */
227{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
228 /* surround71 */
229{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
230
231{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
232{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
233{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
234{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
235{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
236{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
237{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
238{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
239{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
240{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
241{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
242{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
243{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
244{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
245{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
246{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
247{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
248{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
249{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
250{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
251{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
252{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
253{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
254{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
255{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
256{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
257{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
258{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
259{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
260{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
261{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
262{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
263{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
264{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
265{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
266{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
267{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
268{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
269{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
270{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
271{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
272};
273
274
275/*
276 * HDMI routines
277 */
278
279static int hda_node_index(hda_nid_t *nids, hda_nid_t nid)
280{
281 int i;
282
283 for (i = 0; nids[i]; i++)
284 if (nids[i] == nid)
285 return i;
286
287 snd_printk(KERN_WARNING "HDMI: nid %d not registered\n", nid);
288 return -EINVAL;
289}
290
291static void hdmi_get_show_eld(struct hda_codec *codec, hda_nid_t pin_nid,
292 struct hdmi_eld *eld)
293{
294 if (!snd_hdmi_get_eld(eld, codec, pin_nid))
295 snd_hdmi_show_eld(eld);
296}
297
298#ifdef BE_PARANOID
299static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
300 int *packet_index, int *byte_index)
301{
302 int val;
303
304 val = snd_hda_codec_read(codec, pin_nid, 0,
305 AC_VERB_GET_HDMI_DIP_INDEX, 0);
306
307 *packet_index = val >> 5;
308 *byte_index = val & 0x1f;
309}
310#endif
311
312static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
313 int packet_index, int byte_index)
314{
315 int val;
316
317 val = (packet_index << 5) | (byte_index & 0x1f);
318
319 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
320}
321
322static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
323 unsigned char val)
324{
325 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
326}
327
328static void hdmi_enable_output(struct hda_codec *codec, hda_nid_t pin_nid)
329{
330 /* Unmute */
331 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
332 snd_hda_codec_write(codec, pin_nid, 0,
333 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
334 /* Enable pin out */
335 snd_hda_codec_write(codec, pin_nid, 0,
336 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
337}
338
339static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t nid)
340{
341 return 1 + snd_hda_codec_read(codec, nid, 0,
342 AC_VERB_GET_CVT_CHAN_COUNT, 0);
343}
344
345static void hdmi_set_channel_count(struct hda_codec *codec,
346 hda_nid_t nid, int chs)
347{
348 if (chs != hdmi_get_channel_count(codec, nid))
349 snd_hda_codec_write(codec, nid, 0,
350 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
351}
352
353
354/*
355 * Channel mapping routines
356 */
357
358/*
359 * Compute derived values in channel_allocations[].
360 */
361static void init_channel_allocations(void)
362{
363 int i, j;
364 struct cea_channel_speaker_allocation *p;
365
366 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
367 p = channel_allocations + i;
368 p->channels = 0;
369 p->spk_mask = 0;
370 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
371 if (p->speakers[j]) {
372 p->channels++;
373 p->spk_mask |= p->speakers[j];
374 }
375 }
376}
377
378/*
379 * The transformation takes two steps:
380 *
381 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
382 * spk_mask => (channel_allocations[]) => ai->CA
383 *
384 * TODO: it could select the wrong CA from multiple candidates.
385*/
53d7d69d
WF		 386static int hdmi_channel_allocation(struct hda_codec *codec, hda_nid_t nid,
387 int channels)
079d88cc
WF		 388{
389 struct hdmi_spec *spec = codec->spec;
390 struct hdmi_eld *eld;
391 int i;
53d7d69d 392 int ca = 0;
079d88cc 393 int spk_mask = 0;
079d88cc
WF		 394 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
395
396 /*
397 * CA defaults to 0 for basic stereo audio
398 */
399 if (channels <= 2)
400 return 0;
401
402 i = hda_node_index(spec->pin_cvt, nid);
403 if (i < 0)
404 return 0;
405 eld = &spec->sink_eld[i];
406
407 /*
408 * HDMI sink's ELD info cannot always be retrieved for now, e.g.
409 * in console or for audio devices. Assume the highest speakers
410 * configuration, to _not_ prohibit multi-channel audio playback.
411 */
412 if (!eld->spk_alloc)
413 eld->spk_alloc = 0xffff;
414
415 /*
416 * expand ELD's speaker allocation mask
417 *
418 * ELD tells the speaker mask in a compact(paired) form,
419 * expand ELD's notions to match the ones used by Audio InfoFrame.
420 */
421 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
422 if (eld->spk_alloc & (1 << i))
423 spk_mask |= eld_speaker_allocation_bits[i];
424 }
425
426 /* search for the first working match in the CA table */
427 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
428 if (channels == channel_allocations[i].channels &&
429 (spk_mask & channel_allocations[i].spk_mask) ==
430 channel_allocations[i].spk_mask) {
53d7d69d 431 ca = channel_allocations[i].ca_index;
079d88cc
WF		 432 break;
433 }
434 }
435
436 snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
2abbf439 437 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 438 ca, channels, buf);
079d88cc 439
53d7d69d 440 return ca;
079d88cc
WF		 441}
442
443static void hdmi_debug_channel_mapping(struct hda_codec *codec,
444 hda_nid_t pin_nid)
445{
446#ifdef CONFIG_SND_DEBUG_VERBOSE
447 int i;
448 int slot;
449
450 for (i = 0; i < 8; i++) {
451 slot = snd_hda_codec_read(codec, pin_nid, 0,
452 AC_VERB_GET_HDMI_CHAN_SLOT, i);
453 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
454 slot >> 4, slot & 0xf);
455 }
456#endif
457}
458
459
460static void hdmi_setup_channel_mapping(struct hda_codec *codec,
461 hda_nid_t pin_nid,
53d7d69d 462 int ca)
079d88cc
WF		 463{
464 int i;
079d88cc
WF		 465 int err;
466
467 if (hdmi_channel_mapping[ca][1] == 0) {
468 for (i = 0; i < channel_allocations[ca].channels; i++)
469 hdmi_channel_mapping[ca][i] = i | (i << 4);
470 for (; i < 8; i++)
471 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
472 }
473
474 for (i = 0; i < 8; i++) {
475 err = snd_hda_codec_write(codec, pin_nid, 0,
476 AC_VERB_SET_HDMI_CHAN_SLOT,
477 hdmi_channel_mapping[ca][i]);
478 if (err) {
2abbf439
WF		 479 snd_printdd(KERN_NOTICE
480 "HDMI: channel mapping failed\n");
079d88cc
WF		 481 break;
482 }
483 }
484
485 hdmi_debug_channel_mapping(codec, pin_nid);
486}
487
488
489/*
490 * Audio InfoFrame routines
491 */
492
493/*
494 * Enable Audio InfoFrame Transmission
495 */
496static void hdmi_start_infoframe_trans(struct hda_codec *codec,
497 hda_nid_t pin_nid)
498{
499 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
500 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
501 AC_DIPXMIT_BEST);
502}
503
504/*
505 * Disable Audio InfoFrame Transmission
506 */
507static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
508 hda_nid_t pin_nid)
509{
510 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
511 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
512 AC_DIPXMIT_DISABLE);
513}
514
515static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
516{
517#ifdef CONFIG_SND_DEBUG_VERBOSE
518 int i;
519 int size;
520
521 size = snd_hdmi_get_eld_size(codec, pin_nid);
522 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
523
524 for (i = 0; i < 8; i++) {
525 size = snd_hda_codec_read(codec, pin_nid, 0,
526 AC_VERB_GET_HDMI_DIP_SIZE, i);
527 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
528 }
529#endif
530}
531
532static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
533{
534#ifdef BE_PARANOID
535 int i, j;
536 int size;
537 int pi, bi;
538 for (i = 0; i < 8; i++) {
539 size = snd_hda_codec_read(codec, pin_nid, 0,
540 AC_VERB_GET_HDMI_DIP_SIZE, i);
541 if (size == 0)
542 continue;
543
544 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
545 for (j = 1; j < 1000; j++) {
546 hdmi_write_dip_byte(codec, pin_nid, 0x0);
547 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
548 if (pi != i)
549 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
550 bi, pi, i);
551 if (bi == 0) /* byte index wrapped around */
552 break;
553 }
554 snd_printd(KERN_INFO
555 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
556 i, size, j);
557 }
558#endif
559}
560
53d7d69d 561static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 562{
53d7d69d 563 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 564 u8 sum = 0;
565 int i;
566
53d7d69d 567 hdmi_ai->checksum = 0;
079d88cc 568
53d7d69d 569 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 570 sum += bytes[i];
571
53d7d69d 572 hdmi_ai->checksum = -sum;
079d88cc
WF		 573}
574
575static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
576 hda_nid_t pin_nid,
53d7d69d 577 u8 *dip, int size)
079d88cc 578{
079d88cc
WF		 579 int i;
580
581 hdmi_debug_dip_size(codec, pin_nid);
582 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
583
079d88cc 584 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 585 for (i = 0; i < size; i++)
586 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 587}
588
589static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 590 u8 *dip, int size)
079d88cc 591{
079d88cc
WF		 592 u8 val;
593 int i;
594
595 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
596 != AC_DIPXMIT_BEST)
597 return false;
598
599 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 600 for (i = 0; i < size; i++) {
079d88cc
WF		 601 val = snd_hda_codec_read(codec, pin_nid, 0,
602 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 603 if (val != dip[i])
079d88cc
WF		 604 return false;
605 }
606
607 return true;
608}
609
610static void hdmi_setup_audio_infoframe(struct hda_codec *codec, hda_nid_t nid,
611 struct snd_pcm_substream *substream)
612{
613 struct hdmi_spec *spec = codec->spec;
614 hda_nid_t pin_nid;
53d7d69d
WF		 615 int channels = substream->runtime->channels;
616 int ca;
079d88cc 617 int i;
53d7d69d
WF		 618 u8 ai[max(sizeof(struct hdmi_audio_infoframe),
619 sizeof(struct dp_audio_infoframe))];
079d88cc 620
53d7d69d 621 ca = hdmi_channel_allocation(codec, nid, channels);
079d88cc
WF		 622
623 for (i = 0; i < spec->num_pins; i++) {
624 if (spec->pin_cvt[i] != nid)
625 continue;
626 if (!spec->sink_eld[i].monitor_present)
627 continue;
628
629 pin_nid = spec->pin[i];
53d7d69d
WF		 630
631 memset(ai, 0, sizeof(ai));
632 if (spec->sink_eld[i].conn_type == 0) { /* HDMI */
633 struct hdmi_audio_infoframe *hdmi_ai;
634
635 hdmi_ai = (struct hdmi_audio_infoframe *)ai;
636 hdmi_ai->type = 0x84;
637 hdmi_ai->ver = 0x01;
638 hdmi_ai->len = 0x0a;
639 hdmi_ai->CC02_CT47 = channels - 1;
640 hdmi_checksum_audio_infoframe(hdmi_ai);
641 } else if (spec->sink_eld[i].conn_type == 1) { /* DisplayPort */
642 struct dp_audio_infoframe *dp_ai;
643
644 dp_ai = (struct dp_audio_infoframe *)ai;
645 dp_ai->type = 0x84;
646 dp_ai->len = 0x1b;
647 dp_ai->ver = 0x11 << 2;
648 dp_ai->CC02_CT47 = channels - 1;
649 } else {
650 snd_printd("HDMI: unknown connection type at pin %d\n",
651 pin_nid);
652 continue;
653 }
654
655 /*
656 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
657 * sizeof(*dp_ai) to avoid partial match/update problems when
658 * the user switches between HDMI/DP monitors.
659 */
660 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai, sizeof(ai))) {
2abbf439
WF		 661 snd_printdd("hdmi_setup_audio_infoframe: "
662 "cvt=%d pin=%d channels=%d\n",
663 nid, pin_nid,
53d7d69d
WF		 664 channels);
665 hdmi_setup_channel_mapping(codec, pin_nid, ca);
079d88cc 666 hdmi_stop_infoframe_trans(codec, pin_nid);
53d7d69d
WF		 667 hdmi_fill_audio_infoframe(codec, pin_nid,
668 ai, sizeof(ai));
079d88cc
WF		 669 hdmi_start_infoframe_trans(codec, pin_nid);
670 }
671 }
672}
673
674
675/*
676 * Unsolicited events
677 */
678
38faddb1
TI		 679static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
680 struct hdmi_eld *eld);
681
079d88cc
WF		 682static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
683{
684 struct hdmi_spec *spec = codec->spec;
685 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
686 int pind = !!(res & AC_UNSOL_RES_PD);
687 int eldv = !!(res & AC_UNSOL_RES_ELDV);
688 int index;
689
690 printk(KERN_INFO
691 "HDMI hot plug event: Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
692 tag, pind, eldv);
693
694 index = hda_node_index(spec->pin, tag);
695 if (index < 0)
696 return;
697
38faddb1
TI		 698 if (spec->old_pin_detect) {
699 if (pind)
700 hdmi_present_sense(codec, tag, &spec->sink_eld[index]);
701 pind = spec->sink_eld[index].monitor_present;
702 }
703
079d88cc
WF		 704 spec->sink_eld[index].monitor_present = pind;
705 spec->sink_eld[index].eld_valid = eldv;
706
707 if (pind && eldv) {
708 hdmi_get_show_eld(codec, spec->pin[index],
709 &spec->sink_eld[index]);
710 /* TODO: do real things about ELD */
711 }
712}
713
714static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
715{
716 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
717 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
718 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
719 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
720
721 printk(KERN_INFO
722 "HDMI CP event: PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
723 tag,
724 subtag,
725 cp_state,
726 cp_ready);
727
728 /* TODO */
729 if (cp_state)
730 ;
731 if (cp_ready)
732 ;
733}
734
735
736static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
737{
738 struct hdmi_spec *spec = codec->spec;
739 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
740 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
741
742 if (hda_node_index(spec->pin, tag) < 0) {
743 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
744 return;
745 }
746
747 if (subtag == 0)
748 hdmi_intrinsic_event(codec, res);
749 else
750 hdmi_non_intrinsic_event(codec, res);
751}
752
753/*
754 * Callbacks
755 */
756
92f10b3f
TI		 757/* HBR should be Non-PCM, 8 channels */
758#define is_hbr_format(format) \
759 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
760
ea87d1c4 761static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t nid,
079d88cc
WF		 762 u32 stream_tag, int format)
763{
ea87d1c4 764 struct hdmi_spec *spec = codec->spec;
ea87d1c4
AH		 765 int pinctl;
766 int new_pinctl = 0;
767 int i;
768
769 for (i = 0; i < spec->num_pins; i++) {
770 if (spec->pin_cvt[i] != nid)
771 continue;
772 if (!(snd_hda_query_pin_caps(codec, spec->pin[i]) & AC_PINCAP_HBR))
773 continue;
774
775 pinctl = snd_hda_codec_read(codec, spec->pin[i], 0,
776 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
777
778 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 779 if (is_hbr_format(format))
ea87d1c4
AH		 780 new_pinctl |= AC_PINCTL_EPT_HBR;
781 else
782 new_pinctl |= AC_PINCTL_EPT_NATIVE;
783
784 snd_printdd("hdmi_setup_stream: "
785 "NID=0x%x, %spinctl=0x%x\n",
786 spec->pin[i],
787 pinctl == new_pinctl ? "" : "new-",
788 new_pinctl);
789
790 if (pinctl != new_pinctl)
791 snd_hda_codec_write(codec, spec->pin[i], 0,
792 AC_VERB_SET_PIN_WIDGET_CONTROL,
793 new_pinctl);
794 }
795
92f10b3f 796 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 797 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
798 return -EINVAL;
799 }
079d88cc 800
4f347607 801 snd_hda_codec_setup_stream(codec, nid, stream_tag, 0, format);
ea87d1c4 802 return 0;
079d88cc
WF		 803}
804
bbbe3390
TI		 805/*
806 * HDA PCM callbacks
807 */
808static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
809 struct hda_codec *codec,
810 struct snd_pcm_substream *substream)
811{
812 struct hdmi_spec *spec = codec->spec;
813 struct hdmi_eld *eld;
814 struct hda_pcm_stream *codec_pars;
815 unsigned int idx;
816
817 for (idx = 0; idx < spec->num_cvts; idx++)
818 if (hinfo->nid == spec->cvt[idx])
819 break;
820 if (snd_BUG_ON(idx >= spec->num_cvts) ||
821 snd_BUG_ON(idx >= spec->num_pins))
822 return -EINVAL;
823
824 /* save the PCM info the codec provides */
825 codec_pars = &spec->codec_pcm_pars[idx];
826 if (!codec_pars->rates)
827 *codec_pars = *hinfo;
828
829 eld = &spec->sink_eld[idx];
6661702f 830 if (eld->eld_valid && eld->sad_count > 0) {
bbbe3390
TI		 831 hdmi_eld_update_pcm_info(eld, hinfo, codec_pars);
832 if (hinfo->channels_min > hinfo->channels_max ||
833 !hinfo->rates || !hinfo->formats)
834 return -ENODEV;
835 } else {
836 /* fallback to the codec default */
bbbe3390
TI		 837 hinfo->channels_max = codec_pars->channels_max;
838 hinfo->rates = codec_pars->rates;
839 hinfo->formats = codec_pars->formats;
840 hinfo->maxbps = codec_pars->maxbps;
841 }
842 return 0;
843}
844
079d88cc
WF		 845/*
846 * HDA/HDMI auto parsing
847 */
079d88cc
WF		 848static int hdmi_read_pin_conn(struct hda_codec *codec, hda_nid_t pin_nid)
849{
850 struct hdmi_spec *spec = codec->spec;
851 hda_nid_t conn_list[HDA_MAX_CONNECTIONS];
852 int conn_len, curr;
853 int index;
854
855 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
856 snd_printk(KERN_WARNING
857 "HDMI: pin %d wcaps %#x "
858 "does not support connection list\n",
859 pin_nid, get_wcaps(codec, pin_nid));
860 return -EINVAL;
861 }
862
863 conn_len = snd_hda_get_connections(codec, pin_nid, conn_list,
864 HDA_MAX_CONNECTIONS);
865 if (conn_len > 1)
866 curr = snd_hda_codec_read(codec, pin_nid, 0,
867 AC_VERB_GET_CONNECT_SEL, 0);
868 else
869 curr = 0;
870
871 index = hda_node_index(spec->pin, pin_nid);
872 if (index < 0)
873 return -EINVAL;
874
875 spec->pin_cvt[index] = conn_list[curr];
876
877 return 0;
878}
879
880static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
881 struct hdmi_eld *eld)
882{
883 int present = snd_hda_pin_sense(codec, pin_nid);
884
885 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
886 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
887
888 if (present & AC_PINSENSE_ELDV)
889 hdmi_get_show_eld(codec, pin_nid, eld);
890}
891
892static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
893{
894 struct hdmi_spec *spec = codec->spec;
895
896 if (spec->num_pins >= MAX_HDMI_PINS) {
897 snd_printk(KERN_WARNING
898 "HDMI: no space for pin %d\n", pin_nid);
3eaead57 899 return -E2BIG;
079d88cc
WF		 900 }
901
902 hdmi_present_sense(codec, pin_nid, &spec->sink_eld[spec->num_pins]);
903
904 spec->pin[spec->num_pins] = pin_nid;
905 spec->num_pins++;
906
079d88cc
WF		 907 return hdmi_read_pin_conn(codec, pin_nid);
908}
909
910static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t nid)
911{
116dcde6 912 int i, found_pin = 0;
079d88cc
WF		 913 struct hdmi_spec *spec = codec->spec;
914
116dcde6
DH		 915 for (i = 0; i < spec->num_pins; i++)
916 if (nid == spec->pin_cvt[i]) {
917 found_pin = 1;
918 break;
919 }
920
921 if (!found_pin) {
922 snd_printdd("HDMI: Skipping node %d (no connection)\n", nid);
923 return -EINVAL;
079d88cc
WF		 924 }
925
116dcde6
DH		 926 if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
927 return -E2BIG;
928
079d88cc
WF		 929 spec->cvt[spec->num_cvts] = nid;
930 spec->num_cvts++;
931
932 return 0;
933}
934
935static int hdmi_parse_codec(struct hda_codec *codec)
936{
937 hda_nid_t nid;
938 int i, nodes;
116dcde6
DH		 939 int num_tmp_cvts = 0;
940 hda_nid_t tmp_cvt[MAX_HDMI_CVTS];
079d88cc
WF		 941
942 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
943 if (!nid || nodes < 0) {
944 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
945 return -EINVAL;
946 }
947
948 for (i = 0; i < nodes; i++, nid++) {
949 unsigned int caps;
950 unsigned int type;
116dcde6 951 unsigned int config;
079d88cc
WF		 952
953 caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP);
954 type = get_wcaps_type(caps);
955
956 if (!(caps & AC_WCAP_DIGITAL))
957 continue;
958
959 switch (type) {
960 case AC_WID_AUD_OUT:
116dcde6
DH		 961 if (num_tmp_cvts >= MAX_HDMI_CVTS) {
962 snd_printk(KERN_WARNING
963 "HDMI: no space for converter %d\n", nid);
964 continue;
965 }
966 tmp_cvt[num_tmp_cvts] = nid;
967 num_tmp_cvts++;
079d88cc
WF		 968 break;
969 case AC_WID_PIN:
970 caps = snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP);
971 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
972 continue;
116dcde6
DH		 973
974 config = snd_hda_codec_read(codec, nid, 0,
975 AC_VERB_GET_CONFIG_DEFAULT, 0);
976 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
977 continue;
978
3eaead57 979 hdmi_add_pin(codec, nid);
079d88cc
WF		 980 break;
981 }
982 }
983
116dcde6
DH		 984 for (i = 0; i < num_tmp_cvts; i++)
985 hdmi_add_cvt(codec, tmp_cvt[i]);
986
079d88cc
WF		 987 /*
988 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
989 * can be lost and presence sense verb will become inaccurate if the
990 * HDA link is powered off at hot plug or hw initialization time.
991 */
992#ifdef CONFIG_SND_HDA_POWER_SAVE
993 if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
994 AC_PWRST_EPSS))
995 codec->bus->power_keep_link_on = 1;
996#endif
997
998 return 0;
999}
1000
84eb01be
TI		 1001/*
1002 */
1003static char *generic_hdmi_pcm_names[MAX_HDMI_CVTS] = {
1004 "HDMI 0",
1005 "HDMI 1",
1006 "HDMI 2",
1007};
1008
1009/*
1010 * HDMI callbacks
1011 */
1012
1013static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1014 struct hda_codec *codec,
1015 unsigned int stream_tag,
1016 unsigned int format,
1017 struct snd_pcm_substream *substream)
1018{
1019 hdmi_set_channel_count(codec, hinfo->nid,
1020 substream->runtime->channels);
1021
1022 hdmi_setup_audio_infoframe(codec, hinfo->nid, substream);
1023
1024 return hdmi_setup_stream(codec, hinfo->nid, stream_tag, format);
1025}
1026
1027static struct hda_pcm_stream generic_hdmi_pcm_playback = {
1028 .substreams = 1,
1029 .channels_min = 2,
1030 .ops = {
1031 .open = hdmi_pcm_open,
1032 .prepare = generic_hdmi_playback_pcm_prepare,
1033 },
1034};
1035
1036static int generic_hdmi_build_pcms(struct hda_codec *codec)
1037{
1038 struct hdmi_spec *spec = codec->spec;
1039 struct hda_pcm *info = spec->pcm_rec;
1040 int i;
1041
1042 codec->num_pcms = spec->num_cvts;
1043 codec->pcm_info = info;
1044
1045 for (i = 0; i < codec->num_pcms; i++, info++) {
1046 unsigned int chans;
1047 struct hda_pcm_stream *pstr;
1048
1049 chans = get_wcaps(codec, spec->cvt[i]);
1050 chans = get_wcaps_channels(chans);
1051
1052 info->name = generic_hdmi_pcm_names[i];
1053 info->pcm_type = HDA_PCM_TYPE_HDMI;
1054 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1055 if (spec->pcm_playback)
1056 *pstr = *spec->pcm_playback;
1057 else
1058 *pstr = generic_hdmi_pcm_playback;
1059 pstr->nid = spec->cvt[i];
1060 if (pstr->channels_max <= 2 && chans && chans <= 16)
1061 pstr->channels_max = chans;
1062 }
1063
1064 return 0;
1065}
1066
1067static int generic_hdmi_build_controls(struct hda_codec *codec)
1068{
1069 struct hdmi_spec *spec = codec->spec;
1070 int err;
1071 int i;
1072
1073 for (i = 0; i < codec->num_pcms; i++) {
1074 err = snd_hda_create_spdif_out_ctls(codec, spec->cvt[i]);
1075 if (err < 0)
1076 return err;
1077 }
1078
1079 return 0;
1080}
1081
1082static int generic_hdmi_init(struct hda_codec *codec)
1083{
1084 struct hdmi_spec *spec = codec->spec;
1085 int i;
1086
1087 for (i = 0; spec->pin[i]; i++) {
1088 hdmi_enable_output(codec, spec->pin[i]);
1089 snd_hda_codec_write(codec, spec->pin[i], 0,
1090 AC_VERB_SET_UNSOLICITED_ENABLE,
1091 AC_USRSP_EN | spec->pin[i]);
1092 }
1093 return 0;
1094}
1095
1096static void generic_hdmi_free(struct hda_codec *codec)
1097{
1098 struct hdmi_spec *spec = codec->spec;
1099 int i;
1100
1101 for (i = 0; i < spec->num_pins; i++)
1102 snd_hda_eld_proc_free(codec, &spec->sink_eld[i]);
1103
1104 kfree(spec);
1105}
1106
1107static struct hda_codec_ops generic_hdmi_patch_ops = {
1108 .init = generic_hdmi_init,
1109 .free = generic_hdmi_free,
1110 .build_pcms = generic_hdmi_build_pcms,
1111 .build_controls = generic_hdmi_build_controls,
1112 .unsol_event = hdmi_unsol_event,
1113};
1114
1115static int patch_generic_hdmi(struct hda_codec *codec)
1116{
1117 struct hdmi_spec *spec;
1118 int i;
1119
1120 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1121 if (spec == NULL)
1122 return -ENOMEM;
1123
1124 codec->spec = spec;
1125 if (hdmi_parse_codec(codec) < 0) {
1126 codec->spec = NULL;
1127 kfree(spec);
1128 return -EINVAL;
1129 }
1130 codec->patch_ops = generic_hdmi_patch_ops;
1131
1132 for (i = 0; i < spec->num_pins; i++)
1133 snd_hda_eld_proc_new(codec, &spec->sink_eld[i], i);
1134
1135 init_channel_allocations();
1136
1137 return 0;
1138}
1139
1140/*
1141 * Nvidia specific implementations
1142 */
1143
1144#define Nv_VERB_SET_Channel_Allocation 0xF79
1145#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1146#define Nv_VERB_SET_Audio_Protection_On 0xF98
1147#define Nv_VERB_SET_Audio_Protection_Off 0xF99
1148
1149#define nvhdmi_master_con_nid_7x 0x04
1150#define nvhdmi_master_pin_nid_7x 0x05
1151
1152static hda_nid_t nvhdmi_con_nids_7x[4] = {
1153 /*front, rear, clfe, rear_surr */
1154 0x6, 0x8, 0xa, 0xc,
1155};
1156
1157static struct hda_verb nvhdmi_basic_init_7x[] = {
1158 /* set audio protect on */
1159 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1160 /* enable digital output on pin widget */
1161 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1162 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1163 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1164 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1165 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1166 {} /* terminator */
1167};
1168
1169#ifdef LIMITED_RATE_FMT_SUPPORT
1170/* support only the safe format and rate */
1171#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1172#define SUPPORTED_MAXBPS 16
1173#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1174#else
1175/* support all rates and formats */
1176#define SUPPORTED_RATES \
1177 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1178 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1179 SNDRV_PCM_RATE_192000)
1180#define SUPPORTED_MAXBPS 24
1181#define SUPPORTED_FORMATS \
1182 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1183#endif
1184
1185static int nvhdmi_7x_init(struct hda_codec *codec)
1186{
1187 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x);
1188 return 0;
1189}
1190
1191static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
1192 struct hda_codec *codec,
1193 struct snd_pcm_substream *substream)
1194{
1195 struct hdmi_spec *spec = codec->spec;
1196 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
1197}
1198
1199static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
1200 struct hda_codec *codec,
1201 struct snd_pcm_substream *substream)
1202{
1203 struct hdmi_spec *spec = codec->spec;
1204 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1205}
1206
1207static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1208 struct hda_codec *codec,
1209 unsigned int stream_tag,
1210 unsigned int format,
1211 struct snd_pcm_substream *substream)
1212{
1213 struct hdmi_spec *spec = codec->spec;
1214 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
1215 stream_tag, format, substream);
1216}
1217
1218static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
1219 struct hda_codec *codec,
1220 struct snd_pcm_substream *substream)
1221{
1222 struct hdmi_spec *spec = codec->spec;
1223 int i;
1224
1225 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
1226 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
1227 for (i = 0; i < 4; i++) {
1228 /* set the stream id */
1229 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1230 AC_VERB_SET_CHANNEL_STREAMID, 0);
1231 /* set the stream format */
1232 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1233 AC_VERB_SET_STREAM_FORMAT, 0);
1234 }
1235
1236 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1237}
1238
1239static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
1240 struct hda_codec *codec,
1241 unsigned int stream_tag,
1242 unsigned int format,
1243 struct snd_pcm_substream *substream)
1244{
1245 int chs;
1246 unsigned int dataDCC1, dataDCC2, chan, chanmask, channel_id;
1247 int i;
1248
1249 mutex_lock(&codec->spdif_mutex);
1250
1251 chs = substream->runtime->channels;
1252 chan = chs ? (chs - 1) : 1;
1253
1254 switch (chs) {
1255 default:
1256 case 0:
1257 case 2:
1258 chanmask = 0x00;
1259 break;
1260 case 4:
1261 chanmask = 0x08;
1262 break;
1263 case 6:
1264 chanmask = 0x0b;
1265 break;
1266 case 8:
1267 chanmask = 0x13;
1268 break;
1269 }
1270 dataDCC1 = AC_DIG1_ENABLE | AC_DIG1_COPYRIGHT;
1271 dataDCC2 = 0x2;
1272
1273 /* set the Audio InforFrame Channel Allocation */
1274 snd_hda_codec_write(codec, 0x1, 0,
1275 Nv_VERB_SET_Channel_Allocation, chanmask);
1276
1277 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
1278 if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE))
1279 snd_hda_codec_write(codec,
1280 nvhdmi_master_con_nid_7x,
1281 0,
1282 AC_VERB_SET_DIGI_CONVERT_1,
1283 codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff);
1284
1285 /* set the stream id */
1286 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1287 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
1288
1289 /* set the stream format */
1290 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1291 AC_VERB_SET_STREAM_FORMAT, format);
1292
1293 /* turn on again (if needed) */
1294 /* enable and set the channel status audio/data flag */
1295 if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE)) {
1296 snd_hda_codec_write(codec,
1297 nvhdmi_master_con_nid_7x,
1298 0,
1299 AC_VERB_SET_DIGI_CONVERT_1,
1300 codec->spdif_ctls & 0xff);
1301 snd_hda_codec_write(codec,
1302 nvhdmi_master_con_nid_7x,
1303 0,
1304 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1305 }
1306
1307 for (i = 0; i < 4; i++) {
1308 if (chs == 2)
1309 channel_id = 0;
1310 else
1311 channel_id = i * 2;
1312
1313 /* turn off SPDIF once;
1314 *otherwise the IEC958 bits won't be updated
1315 */
1316 if (codec->spdif_status_reset &&
1317 (codec->spdif_ctls & AC_DIG1_ENABLE))
1318 snd_hda_codec_write(codec,
1319 nvhdmi_con_nids_7x[i],
1320 0,
1321 AC_VERB_SET_DIGI_CONVERT_1,
1322 codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff);
1323 /* set the stream id */
1324 snd_hda_codec_write(codec,
1325 nvhdmi_con_nids_7x[i],
1326 0,
1327 AC_VERB_SET_CHANNEL_STREAMID,
1328 (stream_tag << 4) | channel_id);
1329 /* set the stream format */
1330 snd_hda_codec_write(codec,
1331 nvhdmi_con_nids_7x[i],
1332 0,
1333 AC_VERB_SET_STREAM_FORMAT,
1334 format);
1335 /* turn on again (if needed) */
1336 /* enable and set the channel status audio/data flag */
1337 if (codec->spdif_status_reset &&
1338 (codec->spdif_ctls & AC_DIG1_ENABLE)) {
1339 snd_hda_codec_write(codec,
1340 nvhdmi_con_nids_7x[i],
1341 0,
1342 AC_VERB_SET_DIGI_CONVERT_1,
1343 codec->spdif_ctls & 0xff);
1344 snd_hda_codec_write(codec,
1345 nvhdmi_con_nids_7x[i],
1346 0,
1347 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1348 }
1349 }
1350
1351 /* set the Audio Info Frame Checksum */
1352 snd_hda_codec_write(codec, 0x1, 0,
1353 Nv_VERB_SET_Info_Frame_Checksum,
1354 (0x71 - chan - chanmask));
1355
1356 mutex_unlock(&codec->spdif_mutex);
1357 return 0;
1358}
1359
1360static struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
1361 .substreams = 1,
1362 .channels_min = 2,
1363 .channels_max = 8,
1364 .nid = nvhdmi_master_con_nid_7x,
1365 .rates = SUPPORTED_RATES,
1366 .maxbps = SUPPORTED_MAXBPS,
1367 .formats = SUPPORTED_FORMATS,
1368 .ops = {
1369 .open = simple_playback_pcm_open,
1370 .close = nvhdmi_8ch_7x_pcm_close,
1371 .prepare = nvhdmi_8ch_7x_pcm_prepare
1372 },
1373};
1374
1375static struct hda_pcm_stream nvhdmi_pcm_playback_2ch = {
1376 .substreams = 1,
1377 .channels_min = 2,
1378 .channels_max = 2,
1379 .nid = nvhdmi_master_con_nid_7x,
1380 .rates = SUPPORTED_RATES,
1381 .maxbps = SUPPORTED_MAXBPS,
1382 .formats = SUPPORTED_FORMATS,
1383 .ops = {
1384 .open = simple_playback_pcm_open,
1385 .close = simple_playback_pcm_close,
1386 .prepare = simple_playback_pcm_prepare
1387 },
1388};
1389
1390static struct hda_codec_ops nvhdmi_patch_ops_8ch_7x = {
1391 .build_controls = generic_hdmi_build_controls,
1392 .build_pcms = generic_hdmi_build_pcms,
1393 .init = nvhdmi_7x_init,
1394 .free = generic_hdmi_free,
1395};
1396
1397static struct hda_codec_ops nvhdmi_patch_ops_2ch = {
1398 .build_controls = generic_hdmi_build_controls,
1399 .build_pcms = generic_hdmi_build_pcms,
1400 .init = nvhdmi_7x_init,
1401 .free = generic_hdmi_free,
1402};
1403
1404static int patch_nvhdmi_8ch_89(struct hda_codec *codec)
1405{
1406 struct hdmi_spec *spec;
1407 int err = patch_generic_hdmi(codec);
1408
1409 if (err < 0)
1410 return err;
1411 spec = codec->spec;
1412 spec->old_pin_detect = 1;
1413 return 0;
1414}
1415
1416static int patch_nvhdmi_2ch(struct hda_codec *codec)
1417{
1418 struct hdmi_spec *spec;
1419
1420 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1421 if (spec == NULL)
1422 return -ENOMEM;
1423
1424 codec->spec = spec;
1425
1426 spec->multiout.num_dacs = 0; /* no analog */
1427 spec->multiout.max_channels = 2;
1428 spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x;
1429 spec->old_pin_detect = 1;
1430 spec->num_cvts = 1;
1431 spec->cvt[0] = nvhdmi_master_con_nid_7x;
1432 spec->pcm_playback = &nvhdmi_pcm_playback_2ch;
1433
1434 codec->patch_ops = nvhdmi_patch_ops_2ch;
1435
1436 return 0;
1437}
1438
1439static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
1440{
1441 struct hdmi_spec *spec;
1442 int err = patch_nvhdmi_2ch(codec);
1443
1444 if (err < 0)
1445 return err;
1446 spec = codec->spec;
1447 spec->multiout.max_channels = 8;
1448 spec->pcm_playback = &nvhdmi_pcm_playback_8ch_7x;
1449 codec->patch_ops = nvhdmi_patch_ops_8ch_7x;
1450 return 0;
1451}
1452
1453/*
1454 * ATI-specific implementations
1455 *
1456 * FIXME: we may omit the whole this and use the generic code once after
1457 * it's confirmed to work.
1458 */
1459
1460#define ATIHDMI_CVT_NID 0x02 /* audio converter */
1461#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
1462
1463static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1464 struct hda_codec *codec,
1465 unsigned int stream_tag,
1466 unsigned int format,
1467 struct snd_pcm_substream *substream)
1468{
1469 struct hdmi_spec *spec = codec->spec;
1470 int chans = substream->runtime->channels;
1471 int i, err;
1472
1473 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
1474 substream);
1475 if (err < 0)
1476 return err;
1477 snd_hda_codec_write(codec, spec->cvt[0], 0, AC_VERB_SET_CVT_CHAN_COUNT,
1478 chans - 1);
1479 /* FIXME: XXX */
1480 for (i = 0; i < chans; i++) {
1481 snd_hda_codec_write(codec, spec->cvt[0], 0,
1482 AC_VERB_SET_HDMI_CHAN_SLOT,
1483 (i << 4) | i);
1484 }
1485 return 0;
1486}
1487
1488static struct hda_pcm_stream atihdmi_pcm_digital_playback = {
1489 .substreams = 1,
1490 .channels_min = 2,
1491 .channels_max = 2,
1492 .nid = ATIHDMI_CVT_NID,
1493 .ops = {
1494 .open = simple_playback_pcm_open,
1495 .close = simple_playback_pcm_close,
1496 .prepare = atihdmi_playback_pcm_prepare
1497 },
1498};
1499
1500static struct hda_verb atihdmi_basic_init[] = {
1501 /* enable digital output on pin widget */
1502 { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT },
1503 {} /* terminator */
1504};
1505
1506static int atihdmi_init(struct hda_codec *codec)
1507{
1508 struct hdmi_spec *spec = codec->spec;
1509
1510 snd_hda_sequence_write(codec, atihdmi_basic_init);
1511 /* SI codec requires to unmute the pin */
1512 if (get_wcaps(codec, spec->pin[0]) & AC_WCAP_OUT_AMP)
1513 snd_hda_codec_write(codec, spec->pin[0], 0,
1514 AC_VERB_SET_AMP_GAIN_MUTE,
1515 AMP_OUT_UNMUTE);
1516 return 0;
1517}
1518
1519static struct hda_codec_ops atihdmi_patch_ops = {
1520 .build_controls = generic_hdmi_build_controls,
1521 .build_pcms = generic_hdmi_build_pcms,
1522 .init = atihdmi_init,
1523 .free = generic_hdmi_free,
1524};
1525
1526
1527static int patch_atihdmi(struct hda_codec *codec)
1528{
1529 struct hdmi_spec *spec;
1530
1531 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1532 if (spec == NULL)
1533 return -ENOMEM;
1534
1535 codec->spec = spec;
1536
1537 spec->multiout.num_dacs = 0; /* no analog */
1538 spec->multiout.max_channels = 2;
1539 spec->multiout.dig_out_nid = ATIHDMI_CVT_NID;
1540 spec->num_cvts = 1;
1541 spec->cvt[0] = ATIHDMI_CVT_NID;
1542 spec->pin[0] = ATIHDMI_PIN_NID;
1543 spec->pcm_playback = &atihdmi_pcm_digital_playback;
1544
1545 codec->patch_ops = atihdmi_patch_ops;
1546
1547 return 0;
1548}
1549
1550
1551/*
1552 * patch entries
1553 */
1554static struct hda_codec_preset snd_hda_preset_hdmi[] = {
1555{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
1556{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
1557{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 1558{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 1559{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
1560{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
1561{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
1562{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1563{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1564{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1565{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1566{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
1567{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1568{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1569{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi_8ch_89 },
1570{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1571{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1572{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1573{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1574{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1575{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1576{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1577{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1578{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1579{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1580{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1581{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1582{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1583{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1584{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1585{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1586{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
1587{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
1588{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1589{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
1590{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
1591{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
1592{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1593{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
1594{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
1595{} /* terminator */
1596};
1597
1598MODULE_ALIAS("snd-hda-codec-id:1002793c");
1599MODULE_ALIAS("snd-hda-codec-id:10027919");
1600MODULE_ALIAS("snd-hda-codec-id:1002791a");
1601MODULE_ALIAS("snd-hda-codec-id:1002aa01");
1602MODULE_ALIAS("snd-hda-codec-id:10951390");
1603MODULE_ALIAS("snd-hda-codec-id:10951392");
1604MODULE_ALIAS("snd-hda-codec-id:10de0002");
1605MODULE_ALIAS("snd-hda-codec-id:10de0003");
1606MODULE_ALIAS("snd-hda-codec-id:10de0005");
1607MODULE_ALIAS("snd-hda-codec-id:10de0006");
1608MODULE_ALIAS("snd-hda-codec-id:10de0007");
1609MODULE_ALIAS("snd-hda-codec-id:10de000a");
1610MODULE_ALIAS("snd-hda-codec-id:10de000b");
1611MODULE_ALIAS("snd-hda-codec-id:10de000c");
1612MODULE_ALIAS("snd-hda-codec-id:10de000d");
1613MODULE_ALIAS("snd-hda-codec-id:10de0010");
1614MODULE_ALIAS("snd-hda-codec-id:10de0011");
1615MODULE_ALIAS("snd-hda-codec-id:10de0012");
1616MODULE_ALIAS("snd-hda-codec-id:10de0013");
1617MODULE_ALIAS("snd-hda-codec-id:10de0014");
1618MODULE_ALIAS("snd-hda-codec-id:10de0018");
1619MODULE_ALIAS("snd-hda-codec-id:10de0019");
1620MODULE_ALIAS("snd-hda-codec-id:10de001a");
1621MODULE_ALIAS("snd-hda-codec-id:10de001b");
1622MODULE_ALIAS("snd-hda-codec-id:10de001c");
1623MODULE_ALIAS("snd-hda-codec-id:10de0040");
1624MODULE_ALIAS("snd-hda-codec-id:10de0041");
1625MODULE_ALIAS("snd-hda-codec-id:10de0042");
1626MODULE_ALIAS("snd-hda-codec-id:10de0043");
1627MODULE_ALIAS("snd-hda-codec-id:10de0044");
1628MODULE_ALIAS("snd-hda-codec-id:10de0067");
1629MODULE_ALIAS("snd-hda-codec-id:10de8001");
1630MODULE_ALIAS("snd-hda-codec-id:17e80047");
1631MODULE_ALIAS("snd-hda-codec-id:80860054");
1632MODULE_ALIAS("snd-hda-codec-id:80862801");
1633MODULE_ALIAS("snd-hda-codec-id:80862802");
1634MODULE_ALIAS("snd-hda-codec-id:80862803");
1635MODULE_ALIAS("snd-hda-codec-id:80862804");
1636MODULE_ALIAS("snd-hda-codec-id:80862805");
1637MODULE_ALIAS("snd-hda-codec-id:808629fb");
1638
1639MODULE_LICENSE("GPL");
1640MODULE_DESCRIPTION("HDMI HD-audio codec");
1641MODULE_ALIAS("snd-hda-codec-intelhdmi");
1642MODULE_ALIAS("snd-hda-codec-nvhdmi");
1643MODULE_ALIAS("snd-hda-codec-atihdmi");
1644
1645static struct hda_codec_preset_list intel_list = {
1646 .preset = snd_hda_preset_hdmi,
1647 .owner = THIS_MODULE,
1648};
1649
1650static int __init patch_hdmi_init(void)
1651{
1652 return snd_hda_add_codec_preset(&intel_list);
1653}
1654
1655static void __exit patch_hdmi_exit(void)
1656{
1657 snd_hda_delete_codec_preset(&intel_list);
1658}
1659
1660module_init(patch_hdmi_init)
1661module_exit(patch_hdmi_exit)
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