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ALSA: hda - hdmi: Fix incorrect default channel mapping for unusual CAs
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
433968da 37#include <sound/asoundef.h>
d45e6889 38#include <sound/tlv.h>
84eb01be
TI		 39#include "hda_codec.h"
40#include "hda_local.h"
1835a0f9 41#include "hda_jack.h"
84eb01be 42
0ebaa24c
TI		 43static bool static_hdmi_pcm;
44module_param(static_hdmi_pcm, bool, 0644);
45MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
46
fb87fa3a
ML		 47#define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
48
384a48d7
SW		 49struct hdmi_spec_per_cvt {
50 hda_nid_t cvt_nid;
51 int assigned;
52 unsigned int channels_min;
53 unsigned int channels_max;
54 u32 rates;
55 u64 formats;
56 unsigned int maxbps;
57};
079d88cc 58
4eea3091
TI		 59/* max. connections to a widget */
60#define HDA_MAX_CONNECTIONS 32
61
384a48d7
SW		 62struct hdmi_spec_per_pin {
63 hda_nid_t pin_nid;
64 int num_mux_nids;
65 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
744626da
WF		 66
67 struct hda_codec *codec;
384a48d7 68 struct hdmi_eld sink_eld;
744626da 69 struct delayed_work work;
92c69e79 70 struct snd_kcontrol *eld_ctl;
c6e8453e 71 int repoll_count;
b054087d
TI		 72 bool setup; /* the stream has been set up by prepare callback */
73 int channels; /* current number of channels */
1a6003b5 74 bool non_pcm;
d45e6889
TI		 75 bool chmap_set; /* channel-map override by ALSA API? */
76 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 77 char pcm_name[8]; /* filled in build_pcm callbacks */
384a48d7 78};
079d88cc 79
384a48d7
SW		 80struct hdmi_spec {
81 int num_cvts;
bce0d2a8
TI		 82 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
83 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 84
384a48d7 85 int num_pins;
bce0d2a8
TI		 86 struct snd_array pins; /* struct hdmi_spec_per_pin */
87 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 88 unsigned int channels_max; /* max over all cvts */
079d88cc 89
4bd038f9 90 struct hdmi_eld temp_eld;
079d88cc 91 /*
384a48d7 92 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 93 */
94 struct hda_multi_out multiout;
d0b1252d 95 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 96};
97
98
99struct hdmi_audio_infoframe {
100 u8 type; /* 0x84 */
101 u8 ver; /* 0x01 */
102 u8 len; /* 0x0a */
103
53d7d69d
WF		 104 u8 checksum;
105
079d88cc
WF		 106 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
107 u8 SS01_SF24;
108 u8 CXT04;
109 u8 CA;
110 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 111};
112
113struct dp_audio_infoframe {
114 u8 type; /* 0x84 */
115 u8 len; /* 0x1b */
116 u8 ver; /* 0x11 << 2 */
117
118 u8 CC02_CT47; /* match with HDMI infoframe from this on */
119 u8 SS01_SF24;
120 u8 CXT04;
121 u8 CA;
122 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 123};
124
2b203dbb
TI		 125union audio_infoframe {
126 struct hdmi_audio_infoframe hdmi;
127 struct dp_audio_infoframe dp;
128 u8 bytes[0];
129};
130
079d88cc
WF		 131/*
132 * CEA speaker placement:
133 *
134 * FLH FCH FRH
135 * FLW FL FLC FC FRC FR FRW
136 *
137 * LFE
138 * TC
139 *
140 * RL RLC RC RRC RR
141 *
142 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
143 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
144 */
145enum cea_speaker_placement {
146 FL = (1 << 0), /* Front Left */
147 FC = (1 << 1), /* Front Center */
148 FR = (1 << 2), /* Front Right */
149 FLC = (1 << 3), /* Front Left Center */
150 FRC = (1 << 4), /* Front Right Center */
151 RL = (1 << 5), /* Rear Left */
152 RC = (1 << 6), /* Rear Center */
153 RR = (1 << 7), /* Rear Right */
154 RLC = (1 << 8), /* Rear Left Center */
155 RRC = (1 << 9), /* Rear Right Center */
156 LFE = (1 << 10), /* Low Frequency Effect */
157 FLW = (1 << 11), /* Front Left Wide */
158 FRW = (1 << 12), /* Front Right Wide */
159 FLH = (1 << 13), /* Front Left High */
160 FCH = (1 << 14), /* Front Center High */
161 FRH = (1 << 15), /* Front Right High */
162 TC = (1 << 16), /* Top Center */
163};
164
165/*
166 * ELD SA bits in the CEA Speaker Allocation data block
167 */
168static int eld_speaker_allocation_bits[] = {
169 [0] = FL | FR,
170 [1] = LFE,
171 [2] = FC,
172 [3] = RL | RR,
173 [4] = RC,
174 [5] = FLC | FRC,
175 [6] = RLC | RRC,
176 /* the following are not defined in ELD yet */
177 [7] = FLW | FRW,
178 [8] = FLH | FRH,
179 [9] = TC,
180 [10] = FCH,
181};
182
183struct cea_channel_speaker_allocation {
184 int ca_index;
185 int speakers[8];
186
187 /* derived values, just for convenience */
188 int channels;
189 int spk_mask;
190};
191
192/*
193 * ALSA sequence is:
194 *
195 * surround40 surround41 surround50 surround51 surround71
196 * ch0 front left = = = =
197 * ch1 front right = = = =
198 * ch2 rear left = = = =
199 * ch3 rear right = = = =
200 * ch4 LFE center center center
201 * ch5 LFE LFE
202 * ch6 side left
203 * ch7 side right
204 *
205 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
206 */
207static int hdmi_channel_mapping[0x32][8] = {
208 /* stereo */
209 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
210 /* 2.1 */
211 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
212 /* Dolby Surround */
213 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
214 /* surround40 */
215 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
216 /* 4ch */
217 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
218 /* surround41 */
9396d317 219 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 220 /* surround50 */
221 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
222 /* surround51 */
223 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
224 /* 7.1 */
225 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
226};
227
228/*
229 * This is an ordered list!
230 *
231 * The preceding ones have better chances to be selected by
53d7d69d 232 * hdmi_channel_allocation().
079d88cc
WF		 233 */
234static struct cea_channel_speaker_allocation channel_allocations[] = {
235/* channel: 7 6 5 4 3 2 1 0 */
236{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
237 /* 2.1 */
238{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
239 /* Dolby Surround */
240{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
241 /* surround40 */
242{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
243 /* surround41 */
244{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
245 /* surround50 */
246{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
247 /* surround51 */
248{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
249 /* 6.1 */
250{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
251 /* surround71 */
252{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
253
254{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
255{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
256{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
257{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
258{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
259{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
260{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
261{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
262{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
263{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
264{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
265{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
266{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
267{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
268{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
269{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
270{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
271{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
272{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
273{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
274{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
275{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
276{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
277{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
278{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
279{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
280{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
281{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
282{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
283{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
284{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
285{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
286{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
287{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
288{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
289{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
290{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
291{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
292{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
293{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
294{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
295};
296
297
298/*
299 * HDMI routines
300 */
301
bce0d2a8
TI		 302#define get_pin(spec, idx) \
303 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
304#define get_cvt(spec, idx) \
305 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
306#define get_pcm_rec(spec, idx) \
307 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
308
384a48d7 309static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 310{
384a48d7 311 int pin_idx;
079d88cc 312
384a48d7 313 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 314 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 315 return pin_idx;
079d88cc 316
384a48d7
SW		 317 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
318 return -EINVAL;
319}
320
321static int hinfo_to_pin_index(struct hdmi_spec *spec,
322 struct hda_pcm_stream *hinfo)
323{
324 int pin_idx;
325
326 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 327 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 328 return pin_idx;
329
330 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
331 return -EINVAL;
332}
333
334static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
335{
336 int cvt_idx;
337
338 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 339 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 340 return cvt_idx;
341
342 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 343 return -EINVAL;
344}
345
14bc52b8
PLB		 346static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
347 struct snd_ctl_elem_info *uinfo)
348{
349 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 350 struct hdmi_spec *spec = codec->spec;
351 struct hdmi_eld *eld;
14bc52b8
PLB		 352 int pin_idx;
353
14bc52b8
PLB		 354 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
355
356 pin_idx = kcontrol->private_value;
bce0d2a8 357 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 358
4bd038f9 359 mutex_lock(&eld->lock);
68e03de9 360 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
4bd038f9 361 mutex_unlock(&eld->lock);
14bc52b8
PLB		 362
363 return 0;
364}
365
366static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
367 struct snd_ctl_elem_value *ucontrol)
368{
369 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 370 struct hdmi_spec *spec = codec->spec;
371 struct hdmi_eld *eld;
14bc52b8
PLB		 372 int pin_idx;
373
14bc52b8 374 pin_idx = kcontrol->private_value;
bce0d2a8 375 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 376
4bd038f9 377 mutex_lock(&eld->lock);
68e03de9 378 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
4bd038f9 379 mutex_unlock(&eld->lock);
68e03de9
DH		 380 snd_BUG();
381 return -EINVAL;
382 }
383
384 memset(ucontrol->value.bytes.data, 0,
385 ARRAY_SIZE(ucontrol->value.bytes.data));
386 if (eld->eld_valid)
387 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
388 eld->eld_size);
4bd038f9 389 mutex_unlock(&eld->lock);
14bc52b8
PLB		 390
391 return 0;
392}
393
394static struct snd_kcontrol_new eld_bytes_ctl = {
395 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
396 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
397 .name = "ELD",
398 .info = hdmi_eld_ctl_info,
399 .get = hdmi_eld_ctl_get,
400};
401
402static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
403 int device)
404{
405 struct snd_kcontrol *kctl;
406 struct hdmi_spec *spec = codec->spec;
407 int err;
408
409 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
410 if (!kctl)
411 return -ENOMEM;
412 kctl->private_value = pin_idx;
413 kctl->id.device = device;
414
bce0d2a8 415 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 416 if (err < 0)
417 return err;
418
bce0d2a8 419 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 420 return 0;
421}
422
079d88cc
WF		 423#ifdef BE_PARANOID
424static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
425 int *packet_index, int *byte_index)
426{
427 int val;
428
429 val = snd_hda_codec_read(codec, pin_nid, 0,
430 AC_VERB_GET_HDMI_DIP_INDEX, 0);
431
432 *packet_index = val >> 5;
433 *byte_index = val & 0x1f;
434}
435#endif
436
437static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
438 int packet_index, int byte_index)
439{
440 int val;
441
442 val = (packet_index << 5) | (byte_index & 0x1f);
443
444 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
445}
446
447static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
448 unsigned char val)
449{
450 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
451}
452
384a48d7 453static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 454{
455 /* Unmute */
456 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
457 snd_hda_codec_write(codec, pin_nid, 0,
458 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 459 /* Enable pin out: some machines with GM965 gets broken output when
460 * the pin is disabled or changed while using with HDMI
461 */
079d88cc 462 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 463 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 464}
465
384a48d7 466static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 467{
384a48d7 468 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 469 AC_VERB_GET_CVT_CHAN_COUNT, 0);
470}
471
472static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 473 hda_nid_t cvt_nid, int chs)
079d88cc 474{
384a48d7
SW		 475 if (chs != hdmi_get_channel_count(codec, cvt_nid))
476 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 477 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
478}
479
480
481/*
482 * Channel mapping routines
483 */
484
485/*
486 * Compute derived values in channel_allocations[].
487 */
488static void init_channel_allocations(void)
489{
490 int i, j;
491 struct cea_channel_speaker_allocation *p;
492
493 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
494 p = channel_allocations + i;
495 p->channels = 0;
496 p->spk_mask = 0;
497 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
498 if (p->speakers[j]) {
499 p->channels++;
500 p->spk_mask |= p->speakers[j];
501 }
502 }
503}
504
72357c78
WX		 505static int get_channel_allocation_order(int ca)
506{
507 int i;
508
509 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
510 if (channel_allocations[i].ca_index == ca)
511 break;
512 }
513 return i;
514}
515
079d88cc
WF		 516/*
517 * The transformation takes two steps:
518 *
519 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
520 * spk_mask => (channel_allocations[]) => ai->CA
521 *
522 * TODO: it could select the wrong CA from multiple candidates.
523*/
384a48d7 524static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 525{
079d88cc 526 int i;
53d7d69d 527 int ca = 0;
079d88cc 528 int spk_mask = 0;
079d88cc
WF		 529 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
530
531 /*
532 * CA defaults to 0 for basic stereo audio
533 */
534 if (channels <= 2)
535 return 0;
536
079d88cc
WF		 537 /*
538 * expand ELD's speaker allocation mask
539 *
540 * ELD tells the speaker mask in a compact(paired) form,
541 * expand ELD's notions to match the ones used by Audio InfoFrame.
542 */
543 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 544 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 545 spk_mask |= eld_speaker_allocation_bits[i];
546 }
547
548 /* search for the first working match in the CA table */
549 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
550 if (channels == channel_allocations[i].channels &&
551 (spk_mask & channel_allocations[i].spk_mask) ==
552 channel_allocations[i].spk_mask) {
53d7d69d 553 ca = channel_allocations[i].ca_index;
079d88cc
WF		 554 break;
555 }
556 }
557
18e39186
AH		 558 if (!ca) {
559 /* if there was no match, select the regular ALSA channel
560 * allocation with the matching number of channels */
561 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
562 if (channels == channel_allocations[i].channels) {
563 ca = channel_allocations[i].ca_index;
564 break;
565 }
566 }
567 }
568
1613d6b4 569 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 570 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 571 ca, channels, buf);
079d88cc 572
53d7d69d 573 return ca;
079d88cc
WF		 574}
575
576static void hdmi_debug_channel_mapping(struct hda_codec *codec,
577 hda_nid_t pin_nid)
578{
579#ifdef CONFIG_SND_DEBUG_VERBOSE
580 int i;
581 int slot;
582
583 for (i = 0; i < 8; i++) {
584 slot = snd_hda_codec_read(codec, pin_nid, 0,
585 AC_VERB_GET_HDMI_CHAN_SLOT, i);
586 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
587 slot >> 4, slot & 0xf);
588 }
589#endif
590}
591
592
d45e6889 593static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 594 hda_nid_t pin_nid,
433968da 595 bool non_pcm,
53d7d69d 596 int ca)
079d88cc 597{
90f28002 598 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 599 int i;
079d88cc 600 int err;
72357c78 601 int order;
433968da 602 int non_pcm_mapping[8];
079d88cc 603
72357c78 604 order = get_channel_allocation_order(ca);
90f28002 605 ch_alloc = &channel_allocations[order];
433968da 606
079d88cc 607 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 608 int hdmi_slot = 0;
609 /* fill actual channel mappings in ALSA channel (i) order */
610 for (i = 0; i < ch_alloc->channels; i++) {
611 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
612 hdmi_slot++; /* skip zero slots */
613
614 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
615 }
616 /* fill the rest of the slots with ALSA channel 0xf */
617 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
618 if (!ch_alloc->speakers[7 - hdmi_slot])
619 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 620 }
621
433968da 622 if (non_pcm) {
90f28002 623 for (i = 0; i < ch_alloc->channels; i++)
433968da
WX		 624 non_pcm_mapping[i] = i | (i << 4);
625 for (; i < 8; i++)
626 non_pcm_mapping[i] = 0xf | (i << 4);
627 }
628
079d88cc
WF		 629 for (i = 0; i < 8; i++) {
630 err = snd_hda_codec_write(codec, pin_nid, 0,
631 AC_VERB_SET_HDMI_CHAN_SLOT,
433968da 632 non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]);
079d88cc 633 if (err) {
2abbf439
WF		 634 snd_printdd(KERN_NOTICE
635 "HDMI: channel mapping failed\n");
079d88cc
WF		 636 break;
637 }
638 }
639
640 hdmi_debug_channel_mapping(codec, pin_nid);
641}
642
d45e6889
TI		 643struct channel_map_table {
644 unsigned char map; /* ALSA API channel map position */
645 unsigned char cea_slot; /* CEA slot value */
646 int spk_mask; /* speaker position bit mask */
647};
648
649static struct channel_map_table map_tables[] = {
650 { SNDRV_CHMAP_FL, 0x00, FL },
651 { SNDRV_CHMAP_FR, 0x01, FR },
652 { SNDRV_CHMAP_RL, 0x04, RL },
653 { SNDRV_CHMAP_RR, 0x05, RR },
654 { SNDRV_CHMAP_LFE, 0x02, LFE },
655 { SNDRV_CHMAP_FC, 0x03, FC },
656 { SNDRV_CHMAP_RLC, 0x06, RLC },
657 { SNDRV_CHMAP_RRC, 0x07, RRC },
658 {} /* terminator */
659};
660
661/* from ALSA API channel position to speaker bit mask */
662static int to_spk_mask(unsigned char c)
663{
664 struct channel_map_table *t = map_tables;
665 for (; t->map; t++) {
666 if (t->map == c)
667 return t->spk_mask;
668 }
669 return 0;
670}
671
672/* from ALSA API channel position to CEA slot */
673static int to_cea_slot(unsigned char c)
674{
675 struct channel_map_table *t = map_tables;
676 for (; t->map; t++) {
677 if (t->map == c)
678 return t->cea_slot;
679 }
680 return 0x0f;
681}
682
683/* from CEA slot to ALSA API channel position */
684static int from_cea_slot(unsigned char c)
685{
686 struct channel_map_table *t = map_tables;
687 for (; t->map; t++) {
688 if (t->cea_slot == c)
689 return t->map;
690 }
691 return 0;
692}
693
694/* from speaker bit mask to ALSA API channel position */
695static int spk_to_chmap(int spk)
696{
697 struct channel_map_table *t = map_tables;
698 for (; t->map; t++) {
699 if (t->spk_mask == spk)
700 return t->map;
701 }
702 return 0;
703}
704
705/* get the CA index corresponding to the given ALSA API channel map */
706static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
707{
708 int i, spks = 0, spk_mask = 0;
709
710 for (i = 0; i < chs; i++) {
711 int mask = to_spk_mask(map[i]);
712 if (mask) {
713 spk_mask |= mask;
714 spks++;
715 }
716 }
717
718 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
719 if ((chs == channel_allocations[i].channels ||
720 spks == channel_allocations[i].channels) &&
721 (spk_mask & channel_allocations[i].spk_mask) ==
722 channel_allocations[i].spk_mask)
723 return channel_allocations[i].ca_index;
724 }
725 return -1;
726}
727
728/* set up the channel slots for the given ALSA API channel map */
729static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
730 hda_nid_t pin_nid,
731 int chs, unsigned char *map)
732{
733 int i;
734 for (i = 0; i < 8; i++) {
735 int val, err;
736 if (i < chs)
737 val = to_cea_slot(map[i]);
738 else
739 val = 0xf;
740 val |= (i << 4);
741 err = snd_hda_codec_write(codec, pin_nid, 0,
742 AC_VERB_SET_HDMI_CHAN_SLOT, val);
743 if (err)
744 return -EINVAL;
745 }
746 return 0;
747}
748
749/* store ALSA API channel map from the current default map */
750static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
751{
752 int i;
56cac413 753 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 754 for (i = 0; i < 8; i++) {
56cac413
AH		 755 if (i < channel_allocations[ordered_ca].channels)
756 map[i] = from_cea_slot(hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 757 else
758 map[i] = 0;
759 }
760}
761
762static void hdmi_setup_channel_mapping(struct hda_codec *codec,
763 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 764 int channels, unsigned char *map,
765 bool chmap_set)
d45e6889 766{
20608731 767 if (!non_pcm && chmap_set) {
d45e6889
TI		 768 hdmi_manual_setup_channel_mapping(codec, pin_nid,
769 channels, map);
770 } else {
771 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
772 hdmi_setup_fake_chmap(map, ca);
773 }
774}
079d88cc
WF		 775
776/*
777 * Audio InfoFrame routines
778 */
779
780/*
781 * Enable Audio InfoFrame Transmission
782 */
783static void hdmi_start_infoframe_trans(struct hda_codec *codec,
784 hda_nid_t pin_nid)
785{
786 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
787 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
788 AC_DIPXMIT_BEST);
789}
790
791/*
792 * Disable Audio InfoFrame Transmission
793 */
794static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
795 hda_nid_t pin_nid)
796{
797 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
798 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
799 AC_DIPXMIT_DISABLE);
800}
801
802static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
803{
804#ifdef CONFIG_SND_DEBUG_VERBOSE
805 int i;
806 int size;
807
808 size = snd_hdmi_get_eld_size(codec, pin_nid);
809 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
810
811 for (i = 0; i < 8; i++) {
812 size = snd_hda_codec_read(codec, pin_nid, 0,
813 AC_VERB_GET_HDMI_DIP_SIZE, i);
814 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
815 }
816#endif
817}
818
819static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
820{
821#ifdef BE_PARANOID
822 int i, j;
823 int size;
824 int pi, bi;
825 for (i = 0; i < 8; i++) {
826 size = snd_hda_codec_read(codec, pin_nid, 0,
827 AC_VERB_GET_HDMI_DIP_SIZE, i);
828 if (size == 0)
829 continue;
830
831 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
832 for (j = 1; j < 1000; j++) {
833 hdmi_write_dip_byte(codec, pin_nid, 0x0);
834 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
835 if (pi != i)
836 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
837 bi, pi, i);
838 if (bi == 0) /* byte index wrapped around */
839 break;
840 }
841 snd_printd(KERN_INFO
842 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
843 i, size, j);
844 }
845#endif
846}
847
53d7d69d 848static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 849{
53d7d69d 850 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 851 u8 sum = 0;
852 int i;
853
53d7d69d 854 hdmi_ai->checksum = 0;
079d88cc 855
53d7d69d 856 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 857 sum += bytes[i];
858
53d7d69d 859 hdmi_ai->checksum = -sum;
079d88cc
WF		 860}
861
862static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
863 hda_nid_t pin_nid,
53d7d69d 864 u8 *dip, int size)
079d88cc 865{
079d88cc
WF		 866 int i;
867
868 hdmi_debug_dip_size(codec, pin_nid);
869 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
870
079d88cc 871 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 872 for (i = 0; i < size; i++)
873 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 874}
875
876static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 877 u8 *dip, int size)
079d88cc 878{
079d88cc
WF		 879 u8 val;
880 int i;
881
882 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
883 != AC_DIPXMIT_BEST)
884 return false;
885
886 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 887 for (i = 0; i < size; i++) {
079d88cc
WF		 888 val = snd_hda_codec_read(codec, pin_nid, 0,
889 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 890 if (val != dip[i])
079d88cc
WF		 891 return false;
892 }
893
894 return true;
895}
896
b054087d
TI		 897static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
898 struct hdmi_spec_per_pin *per_pin,
899 bool non_pcm)
079d88cc 900{
384a48d7 901 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 902 int channels = per_pin->channels;
384a48d7 903 struct hdmi_eld *eld;
53d7d69d 904 int ca;
2b203dbb 905 union audio_infoframe ai;
079d88cc 906
b054087d
TI		 907 if (!channels)
908 return;
909
58f7d28d
ML		 910 if (is_haswell(codec))
911 snd_hda_codec_write(codec, pin_nid, 0,
912 AC_VERB_SET_AMP_GAIN_MUTE,
913 AMP_OUT_UNMUTE);
914
bce0d2a8 915 eld = &per_pin->sink_eld;
384a48d7
SW		 916 if (!eld->monitor_present)
917 return;
079d88cc 918
d45e6889
TI		 919 if (!non_pcm && per_pin->chmap_set)
920 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
921 else
922 ca = hdmi_channel_allocation(eld, channels);
923 if (ca < 0)
924 ca = 0;
384a48d7
SW		 925
926 memset(&ai, 0, sizeof(ai));
1613d6b4 927 if (eld->info.conn_type == 0) { /* HDMI */
384a48d7
SW		 928 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
929
930 hdmi_ai->type = 0x84;
931 hdmi_ai->ver = 0x01;
932 hdmi_ai->len = 0x0a;
933 hdmi_ai->CC02_CT47 = channels - 1;
934 hdmi_ai->CA = ca;
935 hdmi_checksum_audio_infoframe(hdmi_ai);
1613d6b4 936 } else if (eld->info.conn_type == 1) { /* DisplayPort */
384a48d7
SW		 937 struct dp_audio_infoframe *dp_ai = &ai.dp;
938
939 dp_ai->type = 0x84;
940 dp_ai->len = 0x1b;
941 dp_ai->ver = 0x11 << 2;
942 dp_ai->CC02_CT47 = channels - 1;
943 dp_ai->CA = ca;
944 } else {
945 snd_printd("HDMI: unknown connection type at pin %d\n",
946 pin_nid);
947 return;
948 }
53d7d69d 949
384a48d7
SW		 950 /*
951 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
952 * sizeof(*dp_ai) to avoid partial match/update problems when
953 * the user switches between HDMI/DP monitors.
954 */
955 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
956 sizeof(ai))) {
957 snd_printdd("hdmi_setup_audio_infoframe: "
958 "pin=%d channels=%d\n",
959 pin_nid,
960 channels);
d45e6889 961 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
20608731
AH		 962 channels, per_pin->chmap,
963 per_pin->chmap_set);
384a48d7
SW		 964 hdmi_stop_infoframe_trans(codec, pin_nid);
965 hdmi_fill_audio_infoframe(codec, pin_nid,
966 ai.bytes, sizeof(ai));
967 hdmi_start_infoframe_trans(codec, pin_nid);
2d7e887c
WX		 968 } else {
969 /* For non-pcm audio switch, setup new channel mapping
970 * accordingly */
1a6003b5 971 if (per_pin->non_pcm != non_pcm)
d45e6889 972 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
20608731
AH		 973 channels, per_pin->chmap,
974 per_pin->chmap_set);
079d88cc 975 }
433968da 976
1a6003b5 977 per_pin->non_pcm = non_pcm;
079d88cc
WF		 978}
979
980
981/*
982 * Unsolicited events
983 */
984
c6e8453e 985static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 986
079d88cc
WF		 987static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
988{
989 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 990 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
991 int pin_nid;
384a48d7 992 int pin_idx;
3a93897e 993 struct hda_jack_tbl *jack;
2e59e5ab 994 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 995
996 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
997 if (!jack)
998 return;
999 pin_nid = jack->nid;
1000 jack->jack_dirty = 1;
079d88cc 1001
fae3d88a 1002 _snd_printd(SND_PR_VERBOSE,
2e59e5ab
ML		 1003 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1004 codec->addr, pin_nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1005 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1006
384a48d7
SW		 1007 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
1008 if (pin_idx < 0)
079d88cc
WF		 1009 return;
1010
bce0d2a8 1011 hdmi_present_sense(get_pin(spec, pin_idx), 1);
01a61e12 1012 snd_hda_jack_report_sync(codec);
079d88cc
WF		 1013}
1014
1015static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1016{
1017 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1018 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1019 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1020 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1021
1022 printk(KERN_INFO
e9ea8e8f 1023 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1024 codec->addr,
079d88cc
WF		 1025 tag,
1026 subtag,
1027 cp_state,
1028 cp_ready);
1029
1030 /* TODO */
1031 if (cp_state)
1032 ;
1033 if (cp_ready)
1034 ;
1035}
1036
1037
1038static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1039{
079d88cc
WF		 1040 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1041 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1042
3a93897e 1043 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 1044 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
1045 return;
1046 }
1047
1048 if (subtag == 0)
1049 hdmi_intrinsic_event(codec, res);
1050 else
1051 hdmi_non_intrinsic_event(codec, res);
1052}
1053
58f7d28d 1054static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1055 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1056{
58f7d28d 1057 int pwr;
83f26ad2 1058
53b434f0
WX		 1059 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1060 * thus pins could only choose converter 0 for use. Make sure the
1061 * converters are in correct power state */
fd678cac 1062 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1063 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1064
fd678cac 1065 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1066 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1067 AC_PWRST_D0);
1068 msleep(40);
1069 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1070 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1071 snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1072 }
83f26ad2
DH		 1073}
1074
079d88cc
WF		 1075/*
1076 * Callbacks
1077 */
1078
92f10b3f
TI		 1079/* HBR should be Non-PCM, 8 channels */
1080#define is_hbr_format(format) \
1081 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1082
384a48d7
SW		 1083static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1084 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 1085{
ea87d1c4
AH		 1086 int pinctl;
1087 int new_pinctl = 0;
ea87d1c4 1088
fb87fa3a 1089 if (is_haswell(codec))
58f7d28d 1090 haswell_verify_D0(codec, cvt_nid, pin_nid);
83f26ad2 1091
384a48d7
SW		 1092 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1093 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1094 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1095
1096 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 1097 if (is_hbr_format(format))
ea87d1c4
AH		 1098 new_pinctl |= AC_PINCTL_EPT_HBR;
1099 else
1100 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1101
1102 snd_printdd("hdmi_setup_stream: "
1103 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1104 pin_nid,
ea87d1c4
AH		 1105 pinctl == new_pinctl ? "" : "new-",
1106 new_pinctl);
1107
1108 if (pinctl != new_pinctl)
384a48d7 1109 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1110 AC_VERB_SET_PIN_WIDGET_CONTROL,
1111 new_pinctl);
ea87d1c4 1112
384a48d7 1113 }
92f10b3f 1114 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 1115 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
1116 return -EINVAL;
1117 }
079d88cc 1118
384a48d7 1119 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1120 return 0;
079d88cc
WF		 1121}
1122
7ef166b8
WX		 1123static int hdmi_choose_cvt(struct hda_codec *codec,
1124 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1125{
1126 struct hdmi_spec *spec = codec->spec;
384a48d7 1127 struct hdmi_spec_per_pin *per_pin;
384a48d7 1128 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1129 int cvt_idx, mux_idx = 0;
bbbe3390 1130
bce0d2a8 1131 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1132
1133 /* Dynamically assign converter to stream */
1134 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1135 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1136
384a48d7
SW		 1137 /* Must not already be assigned */
1138 if (per_cvt->assigned)
1139 continue;
1140 /* Must be in pin's mux's list of converters */
1141 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1142 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1143 break;
1144 /* Not in mux list */
1145 if (mux_idx == per_pin->num_mux_nids)
1146 continue;
1147 break;
1148 }
7ef166b8 1149
384a48d7
SW		 1150 /* No free converters */
1151 if (cvt_idx == spec->num_cvts)
1152 return -ENODEV;
1153
7ef166b8
WX		 1154 if (cvt_id)
1155 *cvt_id = cvt_idx;
1156 if (mux_id)
1157 *mux_id = mux_idx;
1158
1159 return 0;
1160}
1161
1162static void haswell_config_cvts(struct hda_codec *codec,
f82d7d16 1163 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1164{
1165 struct hdmi_spec *spec = codec->spec;
f82d7d16
ML		 1166 hda_nid_t nid, end_nid;
1167 int cvt_idx, curr;
1168 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1169
f82d7d16
ML		 1170 /* configure all pins, including "no physical connection" ones */
1171 end_nid = codec->start_nid + codec->num_nodes;
1172 for (nid = codec->start_nid; nid < end_nid; nid++) {
1173 unsigned int wid_caps = get_wcaps(codec, nid);
1174 unsigned int wid_type = get_wcaps_type(wid_caps);
1175
1176 if (wid_type != AC_WID_PIN)
1177 continue;
7ef166b8 1178
f82d7d16 1179 if (nid == pin_nid)
7ef166b8
WX		 1180 continue;
1181
f82d7d16 1182 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1183 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1184 if (curr != mux_idx)
1185 continue;
7ef166b8 1186
f82d7d16
ML		 1187 /* choose an unassigned converter. The conveters in the
1188 * connection list are in the same order as in the codec.
1189 */
1190 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1191 per_cvt = get_cvt(spec, cvt_idx);
1192 if (!per_cvt->assigned) {
1193 snd_printdd("choose cvt %d for pin nid %d\n",
1194 cvt_idx, nid);
1195 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1196 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1197 cvt_idx);
1198 break;
1199 }
7ef166b8
WX		 1200 }
1201 }
1202}
1203
1204/*
1205 * HDA PCM callbacks
1206 */
1207static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1208 struct hda_codec *codec,
1209 struct snd_pcm_substream *substream)
1210{
1211 struct hdmi_spec *spec = codec->spec;
1212 struct snd_pcm_runtime *runtime = substream->runtime;
1213 int pin_idx, cvt_idx, mux_idx = 0;
1214 struct hdmi_spec_per_pin *per_pin;
1215 struct hdmi_eld *eld;
1216 struct hdmi_spec_per_cvt *per_cvt = NULL;
1217 int err;
1218
1219 /* Validate hinfo */
1220 pin_idx = hinfo_to_pin_index(spec, hinfo);
1221 if (snd_BUG_ON(pin_idx < 0))
1222 return -EINVAL;
1223 per_pin = get_pin(spec, pin_idx);
1224 eld = &per_pin->sink_eld;
1225
1226 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1227 if (err < 0)
1228 return err;
1229
1230 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1231 /* Claim converter */
1232 per_cvt->assigned = 1;
1233 hinfo->nid = per_cvt->cvt_nid;
1234
bddee96b 1235 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1236 AC_VERB_SET_CONNECT_SEL,
1237 mux_idx);
7ef166b8
WX		 1238
1239 /* configure unused pins to choose other converters */
fb87fa3a 1240 if (is_haswell(codec))
f82d7d16 1241 haswell_config_cvts(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1242
384a48d7 1243 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1244
2def8172 1245 /* Initially set the converter's capabilities */
384a48d7
SW		 1246 hinfo->channels_min = per_cvt->channels_min;
1247 hinfo->channels_max = per_cvt->channels_max;
1248 hinfo->rates = per_cvt->rates;
1249 hinfo->formats = per_cvt->formats;
1250 hinfo->maxbps = per_cvt->maxbps;
2def8172 1251
384a48d7 1252 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1253 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1254 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1255 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1256 !hinfo->rates || !hinfo->formats) {
1257 per_cvt->assigned = 0;
1258 hinfo->nid = 0;
1259 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1260 return -ENODEV;
2ad779b7 1261 }
bbbe3390 1262 }
2def8172
SW		 1263
1264 /* Store the updated parameters */
639cef0e
TI		 1265 runtime->hw.channels_min = hinfo->channels_min;
1266 runtime->hw.channels_max = hinfo->channels_max;
1267 runtime->hw.formats = hinfo->formats;
1268 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1269
1270 snd_pcm_hw_constraint_step(substream->runtime, 0,
1271 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1272 return 0;
1273}
1274
079d88cc
WF		 1275/*
1276 * HDA/HDMI auto parsing
1277 */
384a48d7 1278static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1279{
1280 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1281 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1282 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1283
1284 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1285 snd_printk(KERN_WARNING
1286 "HDMI: pin %d wcaps %#x "
1287 "does not support connection list\n",
1288 pin_nid, get_wcaps(codec, pin_nid));
1289 return -EINVAL;
1290 }
1291
384a48d7
SW		 1292 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1293 per_pin->mux_nids,
1294 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1295
1296 return 0;
1297}
1298
c6e8453e 1299static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1300{
744626da 1301 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1302 struct hdmi_spec *spec = codec->spec;
1303 struct hdmi_eld *eld = &spec->temp_eld;
1304 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1305 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1306 /*
1307 * Always execute a GetPinSense verb here, even when called from
1308 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1309 * response's PD bit is not the real PD value, but indicates that
1310 * the real PD value changed. An older version of the HD-audio
1311 * specification worked this way. Hence, we just ignore the data in
1312 * the unsolicited response to avoid custom WARs.
1313 */
079d88cc 1314 int present = snd_hda_pin_sense(codec, pin_nid);
4bd038f9
DH		 1315 bool update_eld = false;
1316 bool eld_changed = false;
079d88cc 1317
4bd038f9
DH		 1318 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1319 if (pin_eld->monitor_present)
1320 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1321 else
1322 eld->eld_valid = false;
079d88cc 1323
fae3d88a 1324 _snd_printd(SND_PR_VERBOSE,
384a48d7 1325 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1326 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1327
4bd038f9 1328 if (eld->eld_valid) {
1613d6b4
DH		 1329 if (snd_hdmi_get_eld(codec, pin_nid, eld->eld_buffer,
1330 &eld->eld_size) < 0)
4bd038f9 1331 eld->eld_valid = false;
1613d6b4
DH		 1332 else {
1333 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1334 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1335 eld->eld_size) < 0)
4bd038f9 1336 eld->eld_valid = false;
1613d6b4
DH		 1337 }
1338
4bd038f9 1339 if (eld->eld_valid) {
1613d6b4 1340 snd_hdmi_show_eld(&eld->info);
4bd038f9 1341 update_eld = true;
1613d6b4 1342 }
c6e8453e 1343 else if (repoll) {
744626da
WF		 1344 queue_delayed_work(codec->bus->workq,
1345 &per_pin->work,
1346 msecs_to_jiffies(300));
4bd038f9 1347 return;
744626da
WF		 1348 }
1349 }
4bd038f9
DH		 1350
1351 mutex_lock(&pin_eld->lock);
92c69e79 1352 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1353 update_eld = true;
92c69e79
DH		 1354 eld_changed = true;
1355 }
4bd038f9 1356 if (update_eld) {
b054087d 1357 bool old_eld_valid = pin_eld->eld_valid;
4bd038f9 1358 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1359 eld_changed = pin_eld->eld_size != eld->eld_size ||
1360 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1361 eld->eld_size) != 0;
1362 if (eld_changed)
1363 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1364 eld->eld_size);
1365 pin_eld->eld_size = eld->eld_size;
1366 pin_eld->info = eld->info;
b054087d
TI		 1367
1368 /* Haswell-specific workaround: re-setup when the transcoder is
1369 * changed during the stream playback
1370 */
fb87fa3a 1371 if (is_haswell(codec) &&
58f7d28d 1372 eld->eld_valid && !old_eld_valid && per_pin->setup)
b054087d
TI		 1373 hdmi_setup_audio_infoframe(codec, per_pin,
1374 per_pin->non_pcm);
4bd038f9
DH		 1375 }
1376 mutex_unlock(&pin_eld->lock);
92c69e79
DH		 1377
1378 if (eld_changed)
1379 snd_ctl_notify(codec->bus->card,
1380 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1381 &per_pin->eld_ctl->id);
079d88cc
WF		 1382}
1383
744626da
WF		 1384static void hdmi_repoll_eld(struct work_struct *work)
1385{
1386 struct hdmi_spec_per_pin *per_pin =
1387 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1388
c6e8453e
WF		 1389 if (per_pin->repoll_count++ > 6)
1390 per_pin->repoll_count = 0;
1391
1392 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1393}
1394
c88d4e84
TI		 1395static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1396 hda_nid_t nid);
1397
079d88cc
WF		 1398static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1399{
1400 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1401 unsigned int caps, config;
1402 int pin_idx;
1403 struct hdmi_spec_per_pin *per_pin;
07acecc1 1404 int err;
079d88cc 1405
efc2f8de 1406 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1407 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1408 return 0;
1409
efc2f8de 1410 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1411 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1412 return 0;
1413
fb87fa3a 1414 if (is_haswell(codec))
c88d4e84
TI		 1415 intel_haswell_fixup_connect_list(codec, pin_nid);
1416
384a48d7 1417 pin_idx = spec->num_pins;
bce0d2a8
TI		 1418 per_pin = snd_array_new(&spec->pins);
1419 if (!per_pin)
1420 return -ENOMEM;
384a48d7
SW		 1421
1422 per_pin->pin_nid = pin_nid;
1a6003b5 1423 per_pin->non_pcm = false;
079d88cc 1424
384a48d7
SW		 1425 err = hdmi_read_pin_conn(codec, pin_idx);
1426 if (err < 0)
1427 return err;
079d88cc 1428
079d88cc
WF		 1429 spec->num_pins++;
1430
384a48d7 1431 return 0;
079d88cc
WF		 1432}
1433
384a48d7 1434static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1435{
1436 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1437 struct hdmi_spec_per_cvt *per_cvt;
1438 unsigned int chans;
1439 int err;
079d88cc 1440
384a48d7
SW		 1441 chans = get_wcaps(codec, cvt_nid);
1442 chans = get_wcaps_channels(chans);
1443
bce0d2a8
TI		 1444 per_cvt = snd_array_new(&spec->cvts);
1445 if (!per_cvt)
1446 return -ENOMEM;
384a48d7
SW		 1447
1448 per_cvt->cvt_nid = cvt_nid;
1449 per_cvt->channels_min = 2;
d45e6889 1450 if (chans <= 16) {
384a48d7 1451 per_cvt->channels_max = chans;
d45e6889
TI		 1452 if (chans > spec->channels_max)
1453 spec->channels_max = chans;
1454 }
384a48d7
SW		 1455
1456 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1457 &per_cvt->rates,
1458 &per_cvt->formats,
1459 &per_cvt->maxbps);
1460 if (err < 0)
1461 return err;
1462
bce0d2a8
TI		 1463 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1464 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1465 spec->num_cvts++;
079d88cc
WF		 1466
1467 return 0;
1468}
1469
1470static int hdmi_parse_codec(struct hda_codec *codec)
1471{
1472 hda_nid_t nid;
1473 int i, nodes;
1474
1475 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1476 if (!nid || nodes < 0) {
1477 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1478 return -EINVAL;
1479 }
1480
1481 for (i = 0; i < nodes; i++, nid++) {
1482 unsigned int caps;
1483 unsigned int type;
1484
efc2f8de 1485 caps = get_wcaps(codec, nid);
079d88cc
WF		 1486 type = get_wcaps_type(caps);
1487
1488 if (!(caps & AC_WCAP_DIGITAL))
1489 continue;
1490
1491 switch (type) {
1492 case AC_WID_AUD_OUT:
384a48d7 1493 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1494 break;
1495 case AC_WID_PIN:
3eaead57 1496 hdmi_add_pin(codec, nid);
079d88cc
WF		 1497 break;
1498 }
1499 }
1500
c9adeefd
DH		 1501#ifdef CONFIG_PM
1502 /* We're seeing some problems with unsolicited hot plug events on
1503 * PantherPoint after S3, if this is not enabled */
1504 if (codec->vendor_id == 0x80862806)
1505 codec->bus->power_keep_link_on = 1;
079d88cc
WF		 1506 /*
1507 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1508 * can be lost and presence sense verb will become inaccurate if the
1509 * HDA link is powered off at hot plug or hw initialization time.
1510 */
c9adeefd 1511 else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
079d88cc
WF		 1512 AC_PWRST_EPSS))
1513 codec->bus->power_keep_link_on = 1;
1514#endif
1515
1516 return 0;
1517}
1518
84eb01be
TI		 1519/*
1520 */
1a6003b5
TI		 1521static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1522{
1523 struct hda_spdif_out *spdif;
1524 bool non_pcm;
1525
1526 mutex_lock(&codec->spdif_mutex);
1527 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1528 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1529 mutex_unlock(&codec->spdif_mutex);
1530 return non_pcm;
1531}
1532
1533
84eb01be
TI		 1534/*
1535 * HDMI callbacks
1536 */
1537
1538static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1539 struct hda_codec *codec,
1540 unsigned int stream_tag,
1541 unsigned int format,
1542 struct snd_pcm_substream *substream)
1543{
384a48d7
SW		 1544 hda_nid_t cvt_nid = hinfo->nid;
1545 struct hdmi_spec *spec = codec->spec;
1546 int pin_idx = hinfo_to_pin_index(spec, hinfo);
b054087d
TI		 1547 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1548 hda_nid_t pin_nid = per_pin->pin_nid;
1a6003b5
TI		 1549 bool non_pcm;
1550
1551 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
b054087d
TI		 1552 per_pin->channels = substream->runtime->channels;
1553 per_pin->setup = true;
384a48d7
SW		 1554
1555 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
84eb01be 1556
b054087d 1557 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
84eb01be 1558
384a48d7 1559 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1560}
1561
8dfaa573
TI		 1562static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1563 struct hda_codec *codec,
1564 struct snd_pcm_substream *substream)
1565{
1566 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1567 return 0;
1568}
1569
f2ad24fa
TI		 1570static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1571 struct hda_codec *codec,
1572 struct snd_pcm_substream *substream)
384a48d7
SW		 1573{
1574 struct hdmi_spec *spec = codec->spec;
1575 int cvt_idx, pin_idx;
1576 struct hdmi_spec_per_cvt *per_cvt;
1577 struct hdmi_spec_per_pin *per_pin;
384a48d7 1578
384a48d7
SW		 1579 if (hinfo->nid) {
1580 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1581 if (snd_BUG_ON(cvt_idx < 0))
1582 return -EINVAL;
bce0d2a8 1583 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1584
1585 snd_BUG_ON(!per_cvt->assigned);
1586 per_cvt->assigned = 0;
1587 hinfo->nid = 0;
1588
1589 pin_idx = hinfo_to_pin_index(spec, hinfo);
1590 if (snd_BUG_ON(pin_idx < 0))
1591 return -EINVAL;
bce0d2a8 1592 per_pin = get_pin(spec, pin_idx);
384a48d7 1593
384a48d7 1594 snd_hda_spdif_ctls_unassign(codec, pin_idx);
d45e6889
TI		 1595 per_pin->chmap_set = false;
1596 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1597
1598 per_pin->setup = false;
1599 per_pin->channels = 0;
384a48d7 1600 }
d45e6889 1601
384a48d7
SW		 1602 return 0;
1603}
1604
1605static const struct hda_pcm_ops generic_ops = {
1606 .open = hdmi_pcm_open,
f2ad24fa 1607 .close = hdmi_pcm_close,
384a48d7 1608 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1609 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1610};
1611
d45e6889
TI		 1612/*
1613 * ALSA API channel-map control callbacks
1614 */
1615static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1616 struct snd_ctl_elem_info *uinfo)
1617{
1618 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1619 struct hda_codec *codec = info->private_data;
1620 struct hdmi_spec *spec = codec->spec;
1621 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1622 uinfo->count = spec->channels_max;
1623 uinfo->value.integer.min = 0;
1624 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1625 return 0;
1626}
1627
1628static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1629 unsigned int size, unsigned int __user *tlv)
1630{
1631 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1632 struct hda_codec *codec = info->private_data;
1633 struct hdmi_spec *spec = codec->spec;
1634 const unsigned int valid_mask =
1635 FL | FR | RL | RR | LFE | FC | RLC | RRC;
1636 unsigned int __user *dst;
1637 int chs, count = 0;
1638
1639 if (size < 8)
1640 return -ENOMEM;
1641 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1642 return -EFAULT;
1643 size -= 8;
1644 dst = tlv + 2;
498dab3a 1645 for (chs = 2; chs <= spec->channels_max; chs++) {
d45e6889
TI		 1646 int i, c;
1647 struct cea_channel_speaker_allocation *cap;
1648 cap = channel_allocations;
1649 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1650 int chs_bytes = chs * 4;
1651 if (cap->channels != chs)
1652 continue;
1653 if (cap->spk_mask & ~valid_mask)
1654 continue;
1655 if (size < 8)
1656 return -ENOMEM;
1657 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
1658 put_user(chs_bytes, dst + 1))
1659 return -EFAULT;
1660 dst += 2;
1661 size -= 8;
1662 count += 8;
1663 if (size < chs_bytes)
1664 return -ENOMEM;
1665 size -= chs_bytes;
1666 count += chs_bytes;
1667 for (c = 7; c >= 0; c--) {
1668 int spk = cap->speakers[c];
1669 if (!spk)
1670 continue;
1671 if (put_user(spk_to_chmap(spk), dst))
1672 return -EFAULT;
1673 dst++;
1674 }
1675 }
1676 }
1677 if (put_user(count, tlv + 1))
1678 return -EFAULT;
1679 return 0;
1680}
1681
1682static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1683 struct snd_ctl_elem_value *ucontrol)
1684{
1685 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1686 struct hda_codec *codec = info->private_data;
1687 struct hdmi_spec *spec = codec->spec;
1688 int pin_idx = kcontrol->private_value;
bce0d2a8 1689 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1690 int i;
1691
1692 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1693 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1694 return 0;
1695}
1696
1697static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1698 struct snd_ctl_elem_value *ucontrol)
1699{
1700 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1701 struct hda_codec *codec = info->private_data;
1702 struct hdmi_spec *spec = codec->spec;
1703 int pin_idx = kcontrol->private_value;
bce0d2a8 1704 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1705 unsigned int ctl_idx;
1706 struct snd_pcm_substream *substream;
1707 unsigned char chmap[8];
1708 int i, ca, prepared = 0;
1709
1710 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1711 substream = snd_pcm_chmap_substream(info, ctl_idx);
1712 if (!substream || !substream->runtime)
6f54c361 1713 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1714 switch (substream->runtime->status->state) {
1715 case SNDRV_PCM_STATE_OPEN:
1716 case SNDRV_PCM_STATE_SETUP:
1717 break;
1718 case SNDRV_PCM_STATE_PREPARED:
1719 prepared = 1;
1720 break;
1721 default:
1722 return -EBUSY;
1723 }
1724 memset(chmap, 0, sizeof(chmap));
1725 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1726 chmap[i] = ucontrol->value.integer.value[i];
1727 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1728 return 0;
1729 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1730 if (ca < 0)
1731 return -EINVAL;
1732 per_pin->chmap_set = true;
1733 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1734 if (prepared)
b054087d 1735 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
d45e6889
TI		 1736
1737 return 0;
1738}
1739
84eb01be
TI		 1740static int generic_hdmi_build_pcms(struct hda_codec *codec)
1741{
1742 struct hdmi_spec *spec = codec->spec;
384a48d7 1743 int pin_idx;
84eb01be 1744
384a48d7
SW		 1745 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1746 struct hda_pcm *info;
84eb01be 1747 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 1748 struct hdmi_spec_per_pin *per_pin;
1749
1750 per_pin = get_pin(spec, pin_idx);
1751 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
1752 info = snd_array_new(&spec->pcm_rec);
1753 if (!info)
1754 return -ENOMEM;
1755 info->name = per_pin->pcm_name;
84eb01be 1756 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1757 info->own_chmap = true;
384a48d7 1758
84eb01be 1759 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1760 pstr->substreams = 1;
1761 pstr->ops = generic_ops;
1762 /* other pstr fields are set in open */
84eb01be
TI		 1763 }
1764
384a48d7 1765 codec->num_pcms = spec->num_pins;
bce0d2a8 1766 codec->pcm_info = spec->pcm_rec.list;
384a48d7 1767
84eb01be
TI		 1768 return 0;
1769}
1770
0b6c49b5
DH		 1771static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1772{
31ef2257 1773 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 1774 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 1775 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1776 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 1777
31ef2257
TI		 1778 if (pcmdev > 0)
1779 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 1780 if (!is_jack_detectable(codec, per_pin->pin_nid))
1781 strncat(hdmi_str, " Phantom",
1782 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 1783
31ef2257 1784 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1785}
1786
84eb01be
TI		 1787static int generic_hdmi_build_controls(struct hda_codec *codec)
1788{
1789 struct hdmi_spec *spec = codec->spec;
1790 int err;
384a48d7 1791 int pin_idx;
84eb01be 1792
384a48d7 1793 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1794 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 1795
1796 err = generic_hdmi_build_jack(codec, pin_idx);
1797 if (err < 0)
1798 return err;
1799
dcda5806
TI		 1800 err = snd_hda_create_dig_out_ctls(codec,
1801 per_pin->pin_nid,
1802 per_pin->mux_nids[0],
1803 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 1804 if (err < 0)
1805 return err;
384a48d7 1806 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1807
1808 /* add control for ELD Bytes */
bce0d2a8
TI		 1809 err = hdmi_create_eld_ctl(codec, pin_idx,
1810 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 1811
1812 if (err < 0)
1813 return err;
31ef2257 1814
82b1d73f 1815 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 1816 }
1817
d45e6889
TI		 1818 /* add channel maps */
1819 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1820 struct snd_pcm_chmap *chmap;
1821 struct snd_kcontrol *kctl;
1822 int i;
2ca320e2
TI		 1823
1824 if (!codec->pcm_info[pin_idx].pcm)
1825 break;
d45e6889
TI		 1826 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
1827 SNDRV_PCM_STREAM_PLAYBACK,
1828 NULL, 0, pin_idx, &chmap);
1829 if (err < 0)
1830 return err;
1831 /* override handlers */
1832 chmap->private_data = codec;
1833 kctl = chmap->kctl;
1834 for (i = 0; i < kctl->count; i++)
1835 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
1836 kctl->info = hdmi_chmap_ctl_info;
1837 kctl->get = hdmi_chmap_ctl_get;
1838 kctl->put = hdmi_chmap_ctl_put;
1839 kctl->tlv.c = hdmi_chmap_ctl_tlv;
1840 }
1841
84eb01be
TI		 1842 return 0;
1843}
1844
8b8d654b 1845static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 1846{
1847 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1848 int pin_idx;
1849
1850 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1851 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1852 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1853
744626da 1854 per_pin->codec = codec;
4bd038f9 1855 mutex_init(&eld->lock);
744626da 1856 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
384a48d7 1857 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be 1858 }
8b8d654b
TI		 1859 return 0;
1860}
1861
1862static int generic_hdmi_init(struct hda_codec *codec)
1863{
1864 struct hdmi_spec *spec = codec->spec;
1865 int pin_idx;
1866
1867 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1868 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 1869 hda_nid_t pin_nid = per_pin->pin_nid;
1870
1871 hdmi_init_pin(codec, pin_nid);
1872 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
1873 }
84eb01be
TI		 1874 return 0;
1875}
1876
bce0d2a8
TI		 1877static void hdmi_array_init(struct hdmi_spec *spec, int nums)
1878{
1879 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
1880 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
1881 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
1882}
1883
1884static void hdmi_array_free(struct hdmi_spec *spec)
1885{
1886 snd_array_free(&spec->pins);
1887 snd_array_free(&spec->cvts);
1888 snd_array_free(&spec->pcm_rec);
1889}
1890
84eb01be
TI		 1891static void generic_hdmi_free(struct hda_codec *codec)
1892{
1893 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1894 int pin_idx;
1895
1896 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1897 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1898 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1899
744626da 1900 cancel_delayed_work(&per_pin->work);
384a48d7
SW		 1901 snd_hda_eld_proc_free(codec, eld);
1902 }
84eb01be 1903
744626da 1904 flush_workqueue(codec->bus->workq);
bce0d2a8 1905 hdmi_array_free(spec);
84eb01be
TI		 1906 kfree(spec);
1907}
1908
28cb72e5
WX		 1909#ifdef CONFIG_PM
1910static int generic_hdmi_resume(struct hda_codec *codec)
1911{
1912 struct hdmi_spec *spec = codec->spec;
1913 int pin_idx;
1914
1915 generic_hdmi_init(codec);
1916 snd_hda_codec_resume_amp(codec);
1917 snd_hda_codec_resume_cache(codec);
1918
1919 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1920 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1921 hdmi_present_sense(per_pin, 1);
1922 }
1923 return 0;
1924}
1925#endif
1926
fb79e1e0 1927static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1928 .init = generic_hdmi_init,
1929 .free = generic_hdmi_free,
1930 .build_pcms = generic_hdmi_build_pcms,
1931 .build_controls = generic_hdmi_build_controls,
1932 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 1933#ifdef CONFIG_PM
1934 .resume = generic_hdmi_resume,
1935#endif
84eb01be
TI		 1936};
1937
6ffe168f 1938
c88d4e84
TI		 1939static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1940 hda_nid_t nid)
1941{
1942 struct hdmi_spec *spec = codec->spec;
1943 hda_nid_t conns[4];
1944 int nconns;
6ffe168f 1945
c88d4e84
TI		 1946 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
1947 if (nconns == spec->num_cvts &&
1948 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 1949 return;
1950
c88d4e84
TI		 1951 /* override pins connection list */
1952 snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
1953 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 1954}
1955
1611a9c9
ML		 1956#define INTEL_VENDOR_NID 0x08
1957#define INTEL_GET_VENDOR_VERB 0xf81
1958#define INTEL_SET_VENDOR_VERB 0x781
1959#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
1960#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
1961
1962static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 1963 bool update_tree)
1611a9c9
ML		 1964{
1965 unsigned int vendor_param;
1966
1611a9c9
ML		 1967 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1968 INTEL_GET_VENDOR_VERB, 0);
1969 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
1970 return;
1971
1972 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
1973 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1974 INTEL_SET_VENDOR_VERB, vendor_param);
1975 if (vendor_param == -1)
1976 return;
1977
17df3f55
TI		 1978 if (update_tree)
1979 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 1980}
1981
c88d4e84
TI		 1982static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
1983{
1984 unsigned int vendor_param;
1985
1986 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1987 INTEL_GET_VENDOR_VERB, 0);
1988 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
1989 return;
1990
1991 /* enable DP1.2 mode */
1992 vendor_param |= INTEL_EN_DP12;
1993 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
1994 INTEL_SET_VENDOR_VERB, vendor_param);
1995}
1996
17df3f55
TI		 1997/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
1998 * Otherwise you may get severe h/w communication errors.
1999 */
2000static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2001 unsigned int power_state)
2002{
2003 if (power_state == AC_PWRST_D0) {
2004 intel_haswell_enable_all_pins(codec, false);
2005 intel_haswell_fixup_enable_dp12(codec);
2006 }
c88d4e84 2007
17df3f55
TI		 2008 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2009 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2010}
6ffe168f 2011
84eb01be
TI		 2012static int patch_generic_hdmi(struct hda_codec *codec)
2013{
2014 struct hdmi_spec *spec;
84eb01be
TI		 2015
2016 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2017 if (spec == NULL)
2018 return -ENOMEM;
2019
2020 codec->spec = spec;
bce0d2a8 2021 hdmi_array_init(spec, 4);
6ffe168f 2022
fb87fa3a 2023 if (is_haswell(codec)) {
17df3f55 2024 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2025 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2026 }
6ffe168f 2027
84eb01be
TI		 2028 if (hdmi_parse_codec(codec) < 0) {
2029 codec->spec = NULL;
2030 kfree(spec);
2031 return -EINVAL;
2032 }
2033 codec->patch_ops = generic_hdmi_patch_ops;
fb87fa3a 2034 if (is_haswell(codec)) {
17df3f55 2035 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2036 codec->dp_mst = true;
2037 }
17df3f55 2038
8b8d654b 2039 generic_hdmi_init_per_pins(codec);
84eb01be 2040
84eb01be
TI		 2041 init_channel_allocations();
2042
2043 return 0;
2044}
2045
3aaf8980
SW		 2046/*
2047 * Shared non-generic implementations
2048 */
2049
2050static int simple_playback_build_pcms(struct hda_codec *codec)
2051{
2052 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2053 struct hda_pcm *info;
8ceb332d
TI		 2054 unsigned int chans;
2055 struct hda_pcm_stream *pstr;
bce0d2a8 2056 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2057
bce0d2a8
TI		 2058 per_cvt = get_cvt(spec, 0);
2059 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2060 chans = get_wcaps_channels(chans);
3aaf8980 2061
bce0d2a8
TI		 2062 info = snd_array_new(&spec->pcm_rec);
2063 if (!info)
2064 return -ENOMEM;
2065 info->name = get_pin(spec, 0)->pcm_name;
2066 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2067 info->pcm_type = HDA_PCM_TYPE_HDMI;
2068 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2069 *pstr = spec->pcm_playback;
bce0d2a8 2070 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2071 if (pstr->channels_max <= 2 && chans && chans <= 16)
2072 pstr->channels_max = chans;
3aaf8980 2073
bce0d2a8
TI		 2074 codec->num_pcms = 1;
2075 codec->pcm_info = info;
2076
3aaf8980
SW		 2077 return 0;
2078}
2079
4b6ace9e
TI		 2080/* unsolicited event for jack sensing */
2081static void simple_hdmi_unsol_event(struct hda_codec *codec,
2082 unsigned int res)
2083{
9dd8cf12 2084 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2085 snd_hda_jack_report_sync(codec);
2086}
2087
2088/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2089 * as long as spec->pins[] is set correctly
2090 */
2091#define simple_hdmi_build_jack generic_hdmi_build_jack
2092
3aaf8980
SW		 2093static int simple_playback_build_controls(struct hda_codec *codec)
2094{
2095 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2096 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2097 int err;
3aaf8980 2098
bce0d2a8
TI		 2099 per_cvt = get_cvt(spec, 0);
2100 err = snd_hda_create_spdif_out_ctls(codec, per_cvt->cvt_nid,
2101 per_cvt->cvt_nid);
8ceb332d
TI		 2102 if (err < 0)
2103 return err;
2104 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2105}
2106
4f0110ce
TI		 2107static int simple_playback_init(struct hda_codec *codec)
2108{
2109 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2110 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2111 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2112
2113 snd_hda_codec_write(codec, pin, 0,
2114 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2115 /* some codecs require to unmute the pin */
2116 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2117 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2118 AMP_OUT_UNMUTE);
2119 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2120 return 0;
2121}
2122
3aaf8980
SW		 2123static void simple_playback_free(struct hda_codec *codec)
2124{
2125 struct hdmi_spec *spec = codec->spec;
2126
bce0d2a8 2127 hdmi_array_free(spec);
3aaf8980
SW		 2128 kfree(spec);
2129}
2130
84eb01be
TI		 2131/*
2132 * Nvidia specific implementations
2133 */
2134
2135#define Nv_VERB_SET_Channel_Allocation 0xF79
2136#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2137#define Nv_VERB_SET_Audio_Protection_On 0xF98
2138#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2139
2140#define nvhdmi_master_con_nid_7x 0x04
2141#define nvhdmi_master_pin_nid_7x 0x05
2142
fb79e1e0 2143static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2144 /*front, rear, clfe, rear_surr */
2145 0x6, 0x8, 0xa, 0xc,
2146};
2147
ceaa86ba
TI		 2148static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2149 /* set audio protect on */
2150 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2151 /* enable digital output on pin widget */
2152 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2153 {} /* terminator */
2154};
2155
2156static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2157 /* set audio protect on */
2158 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2159 /* enable digital output on pin widget */
2160 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2161 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2162 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2163 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2164 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2165 {} /* terminator */
2166};
2167
2168#ifdef LIMITED_RATE_FMT_SUPPORT
2169/* support only the safe format and rate */
2170#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2171#define SUPPORTED_MAXBPS 16
2172#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2173#else
2174/* support all rates and formats */
2175#define SUPPORTED_RATES \
2176 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2177 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2178 SNDRV_PCM_RATE_192000)
2179#define SUPPORTED_MAXBPS 24
2180#define SUPPORTED_FORMATS \
2181 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2182#endif
2183
ceaa86ba
TI		 2184static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2185{
2186 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2187 return 0;
2188}
2189
2190static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2191{
ceaa86ba 2192 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2193 return 0;
2194}
2195
393004b2
ND		 2196static unsigned int channels_2_6_8[] = {
2197 2, 6, 8
2198};
2199
2200static unsigned int channels_2_8[] = {
2201 2, 8
2202};
2203
2204static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2205 .count = ARRAY_SIZE(channels_2_6_8),
2206 .list = channels_2_6_8,
2207 .mask = 0,
2208};
2209
2210static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2211 .count = ARRAY_SIZE(channels_2_8),
2212 .list = channels_2_8,
2213 .mask = 0,
2214};
2215
84eb01be
TI		 2216static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2217 struct hda_codec *codec,
2218 struct snd_pcm_substream *substream)
2219{
2220 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2221 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2222
2223 switch (codec->preset->id) {
2224 case 0x10de0002:
2225 case 0x10de0003:
2226 case 0x10de0005:
2227 case 0x10de0006:
2228 hw_constraints_channels = &hw_constraints_2_8_channels;
2229 break;
2230 case 0x10de0007:
2231 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2232 break;
2233 default:
2234 break;
2235 }
2236
2237 if (hw_constraints_channels != NULL) {
2238 snd_pcm_hw_constraint_list(substream->runtime, 0,
2239 SNDRV_PCM_HW_PARAM_CHANNELS,
2240 hw_constraints_channels);
ad09fc9d
TI		 2241 } else {
2242 snd_pcm_hw_constraint_step(substream->runtime, 0,
2243 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2244 }
2245
84eb01be
TI		 2246 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2247}
2248
2249static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2250 struct hda_codec *codec,
2251 struct snd_pcm_substream *substream)
2252{
2253 struct hdmi_spec *spec = codec->spec;
2254 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2255}
2256
2257static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2258 struct hda_codec *codec,
2259 unsigned int stream_tag,
2260 unsigned int format,
2261 struct snd_pcm_substream *substream)
2262{
2263 struct hdmi_spec *spec = codec->spec;
2264 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2265 stream_tag, format, substream);
2266}
2267
d0b1252d
TI		 2268static const struct hda_pcm_stream simple_pcm_playback = {
2269 .substreams = 1,
2270 .channels_min = 2,
2271 .channels_max = 2,
2272 .ops = {
2273 .open = simple_playback_pcm_open,
2274 .close = simple_playback_pcm_close,
2275 .prepare = simple_playback_pcm_prepare
2276 },
2277};
2278
2279static const struct hda_codec_ops simple_hdmi_patch_ops = {
2280 .build_controls = simple_playback_build_controls,
2281 .build_pcms = simple_playback_build_pcms,
2282 .init = simple_playback_init,
2283 .free = simple_playback_free,
250e41ac 2284 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2285};
2286
2287static int patch_simple_hdmi(struct hda_codec *codec,
2288 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2289{
2290 struct hdmi_spec *spec;
bce0d2a8
TI		 2291 struct hdmi_spec_per_cvt *per_cvt;
2292 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2293
2294 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2295 if (!spec)
2296 return -ENOMEM;
2297
2298 codec->spec = spec;
bce0d2a8 2299 hdmi_array_init(spec, 1);
d0b1252d
TI		 2300
2301 spec->multiout.num_dacs = 0; /* no analog */
2302 spec->multiout.max_channels = 2;
2303 spec->multiout.dig_out_nid = cvt_nid;
2304 spec->num_cvts = 1;
2305 spec->num_pins = 1;
bce0d2a8
TI		 2306 per_pin = snd_array_new(&spec->pins);
2307 per_cvt = snd_array_new(&spec->cvts);
2308 if (!per_pin || !per_cvt) {
2309 simple_playback_free(codec);
2310 return -ENOMEM;
2311 }
2312 per_cvt->cvt_nid = cvt_nid;
2313 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2314 spec->pcm_playback = simple_pcm_playback;
2315
2316 codec->patch_ops = simple_hdmi_patch_ops;
2317
2318 return 0;
2319}
2320
1f348522
AP		 2321static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2322 int channels)
2323{
2324 unsigned int chanmask;
2325 int chan = channels ? (channels - 1) : 1;
2326
2327 switch (channels) {
2328 default:
2329 case 0:
2330 case 2:
2331 chanmask = 0x00;
2332 break;
2333 case 4:
2334 chanmask = 0x08;
2335 break;
2336 case 6:
2337 chanmask = 0x0b;
2338 break;
2339 case 8:
2340 chanmask = 0x13;
2341 break;
2342 }
2343
2344 /* Set the audio infoframe channel allocation and checksum fields. The
2345 * channel count is computed implicitly by the hardware. */
2346 snd_hda_codec_write(codec, 0x1, 0,
2347 Nv_VERB_SET_Channel_Allocation, chanmask);
2348
2349 snd_hda_codec_write(codec, 0x1, 0,
2350 Nv_VERB_SET_Info_Frame_Checksum,
2351 (0x71 - chan - chanmask));
2352}
2353
84eb01be
TI		 2354static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2355 struct hda_codec *codec,
2356 struct snd_pcm_substream *substream)
2357{
2358 struct hdmi_spec *spec = codec->spec;
2359 int i;
2360
2361 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2362 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2363 for (i = 0; i < 4; i++) {
2364 /* set the stream id */
2365 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2366 AC_VERB_SET_CHANNEL_STREAMID, 0);
2367 /* set the stream format */
2368 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2369 AC_VERB_SET_STREAM_FORMAT, 0);
2370 }
2371
1f348522
AP		 2372 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2373 * streams are disabled. */
2374 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2375
84eb01be
TI		 2376 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2377}
2378
2379static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2380 struct hda_codec *codec,
2381 unsigned int stream_tag,
2382 unsigned int format,
2383 struct snd_pcm_substream *substream)
2384{
2385 int chs;
112daa7a 2386 unsigned int dataDCC2, channel_id;
84eb01be 2387 int i;
7c935976 2388 struct hdmi_spec *spec = codec->spec;
e3245cdd 2389 struct hda_spdif_out *spdif;
bce0d2a8 2390 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2391
2392 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2393 per_cvt = get_cvt(spec, 0);
2394 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2395
2396 chs = substream->runtime->channels;
84eb01be 2397
84eb01be
TI		 2398 dataDCC2 = 0x2;
2399
84eb01be 2400 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2401 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2402 snd_hda_codec_write(codec,
2403 nvhdmi_master_con_nid_7x,
2404 0,
2405 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2406 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2407
2408 /* set the stream id */
2409 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2410 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2411
2412 /* set the stream format */
2413 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2414 AC_VERB_SET_STREAM_FORMAT, format);
2415
2416 /* turn on again (if needed) */
2417 /* enable and set the channel status audio/data flag */
7c935976 2418 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2419 snd_hda_codec_write(codec,
2420 nvhdmi_master_con_nid_7x,
2421 0,
2422 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2423 spdif->ctls & 0xff);
84eb01be
TI		 2424 snd_hda_codec_write(codec,
2425 nvhdmi_master_con_nid_7x,
2426 0,
2427 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2428 }
2429
2430 for (i = 0; i < 4; i++) {
2431 if (chs == 2)
2432 channel_id = 0;
2433 else
2434 channel_id = i * 2;
2435
2436 /* turn off SPDIF once;
2437 *otherwise the IEC958 bits won't be updated
2438 */
2439 if (codec->spdif_status_reset &&
7c935976 2440 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2441 snd_hda_codec_write(codec,
2442 nvhdmi_con_nids_7x[i],
2443 0,
2444 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2445 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2446 /* set the stream id */
2447 snd_hda_codec_write(codec,
2448 nvhdmi_con_nids_7x[i],
2449 0,
2450 AC_VERB_SET_CHANNEL_STREAMID,
2451 (stream_tag << 4) | channel_id);
2452 /* set the stream format */
2453 snd_hda_codec_write(codec,
2454 nvhdmi_con_nids_7x[i],
2455 0,
2456 AC_VERB_SET_STREAM_FORMAT,
2457 format);
2458 /* turn on again (if needed) */
2459 /* enable and set the channel status audio/data flag */
2460 if (codec->spdif_status_reset &&
7c935976 2461 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2462 snd_hda_codec_write(codec,
2463 nvhdmi_con_nids_7x[i],
2464 0,
2465 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2466 spdif->ctls & 0xff);
84eb01be
TI		 2467 snd_hda_codec_write(codec,
2468 nvhdmi_con_nids_7x[i],
2469 0,
2470 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2471 }
2472 }
2473
1f348522 2474 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2475
2476 mutex_unlock(&codec->spdif_mutex);
2477 return 0;
2478}
2479
fb79e1e0 2480static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2481 .substreams = 1,
2482 .channels_min = 2,
2483 .channels_max = 8,
2484 .nid = nvhdmi_master_con_nid_7x,
2485 .rates = SUPPORTED_RATES,
2486 .maxbps = SUPPORTED_MAXBPS,
2487 .formats = SUPPORTED_FORMATS,
2488 .ops = {
2489 .open = simple_playback_pcm_open,
2490 .close = nvhdmi_8ch_7x_pcm_close,
2491 .prepare = nvhdmi_8ch_7x_pcm_prepare
2492 },
2493};
2494
84eb01be
TI		 2495static int patch_nvhdmi_2ch(struct hda_codec *codec)
2496{
2497 struct hdmi_spec *spec;
d0b1252d
TI		 2498 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2499 nvhdmi_master_pin_nid_7x);
2500 if (err < 0)
2501 return err;
84eb01be 2502
ceaa86ba 2503 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2504 /* override the PCM rates, etc, as the codec doesn't give full list */
2505 spec = codec->spec;
2506 spec->pcm_playback.rates = SUPPORTED_RATES;
2507 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2508 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2509 return 0;
2510}
2511
53775b0d
TI		 2512static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2513{
2514 struct hdmi_spec *spec = codec->spec;
2515 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2516 if (!err) {
2517 struct hda_pcm *info = get_pcm_rec(spec, 0);
2518 info->own_chmap = true;
2519 }
53775b0d
TI		 2520 return err;
2521}
2522
2523static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2524{
2525 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2526 struct hda_pcm *info;
53775b0d
TI		 2527 struct snd_pcm_chmap *chmap;
2528 int err;
2529
2530 err = simple_playback_build_controls(codec);
2531 if (err < 0)
2532 return err;
2533
2534 /* add channel maps */
bce0d2a8
TI		 2535 info = get_pcm_rec(spec, 0);
2536 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2537 SNDRV_PCM_STREAM_PLAYBACK,
2538 snd_pcm_alt_chmaps, 8, 0, &chmap);
2539 if (err < 0)
2540 return err;
2541 switch (codec->preset->id) {
2542 case 0x10de0002:
2543 case 0x10de0003:
2544 case 0x10de0005:
2545 case 0x10de0006:
2546 chmap->channel_mask = (1U << 2) | (1U << 8);
2547 break;
2548 case 0x10de0007:
2549 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2550 }
2551 return 0;
2552}
2553
84eb01be
TI		 2554static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2555{
2556 struct hdmi_spec *spec;
2557 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2558 if (err < 0)
2559 return err;
2560 spec = codec->spec;
2561 spec->multiout.max_channels = 8;
d0b1252d 2562 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2563 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2564 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2565 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2566
2567 /* Initialize the audio infoframe channel mask and checksum to something
2568 * valid */
2569 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2570
84eb01be
TI		 2571 return 0;
2572}
2573
2574/*
2575 * ATI-specific implementations
2576 *
2577 * FIXME: we may omit the whole this and use the generic code once after
2578 * it's confirmed to work.
2579 */
2580
2581#define ATIHDMI_CVT_NID 0x02 /* audio converter */
2582#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
2583
2584static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2585 struct hda_codec *codec,
2586 unsigned int stream_tag,
2587 unsigned int format,
2588 struct snd_pcm_substream *substream)
2589{
2590 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2591 struct hdmi_spec_per_cvt *per_cvt = get_cvt(spec, 0);
84eb01be
TI		 2592 int chans = substream->runtime->channels;
2593 int i, err;
2594
2595 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
2596 substream);
2597 if (err < 0)
2598 return err;
bce0d2a8 2599 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
384a48d7 2600 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 2601 /* FIXME: XXX */
2602 for (i = 0; i < chans; i++) {
bce0d2a8 2603 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
84eb01be
TI		 2604 AC_VERB_SET_HDMI_CHAN_SLOT,
2605 (i << 4) | i);
2606 }
2607 return 0;
2608}
2609
84eb01be
TI		 2610static int patch_atihdmi(struct hda_codec *codec)
2611{
2612 struct hdmi_spec *spec;
d0b1252d
TI		 2613 int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
2614 if (err < 0)
2615 return err;
2616 spec = codec->spec;
2617 spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
84eb01be
TI		 2618 return 0;
2619}
2620
3de5ff88
AL		 2621/* VIA HDMI Implementation */
2622#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
2623#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
2624
3de5ff88
AL		 2625static int patch_via_hdmi(struct hda_codec *codec)
2626{
250e41ac 2627 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 2628}
84eb01be
TI		 2629
2630/*
2631 * patch entries
2632 */
fb79e1e0 2633static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 2634{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
2635{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
2636{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 2637{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2638{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
2639{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
2640{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
2641{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2642{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2643{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2644{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2645{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 2646{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
2647{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
2648{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
2649{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
2650{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
2651{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
2652{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
2653{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
2654{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
2655{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
2656{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 2657/* 17 is known to be absent */
5d44f927
SW		 2658{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
2659{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
2660{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
2661{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
2662{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
2663{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
2664{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
2665{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
2666{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
2667{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
7ae48b56 2668{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
d52392b1 2669{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2670{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
2671{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 2672{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2673{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2674{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
2675{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2676{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2677{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
2678{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
2679{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
2680{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2681{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 2682{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 2683{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 2684{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2685{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
2686{} /* terminator */
2687};
2688
2689MODULE_ALIAS("snd-hda-codec-id:1002793c");
2690MODULE_ALIAS("snd-hda-codec-id:10027919");
2691MODULE_ALIAS("snd-hda-codec-id:1002791a");
2692MODULE_ALIAS("snd-hda-codec-id:1002aa01");
2693MODULE_ALIAS("snd-hda-codec-id:10951390");
2694MODULE_ALIAS("snd-hda-codec-id:10951392");
2695MODULE_ALIAS("snd-hda-codec-id:10de0002");
2696MODULE_ALIAS("snd-hda-codec-id:10de0003");
2697MODULE_ALIAS("snd-hda-codec-id:10de0005");
2698MODULE_ALIAS("snd-hda-codec-id:10de0006");
2699MODULE_ALIAS("snd-hda-codec-id:10de0007");
2700MODULE_ALIAS("snd-hda-codec-id:10de000a");
2701MODULE_ALIAS("snd-hda-codec-id:10de000b");
2702MODULE_ALIAS("snd-hda-codec-id:10de000c");
2703MODULE_ALIAS("snd-hda-codec-id:10de000d");
2704MODULE_ALIAS("snd-hda-codec-id:10de0010");
2705MODULE_ALIAS("snd-hda-codec-id:10de0011");
2706MODULE_ALIAS("snd-hda-codec-id:10de0012");
2707MODULE_ALIAS("snd-hda-codec-id:10de0013");
2708MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 2709MODULE_ALIAS("snd-hda-codec-id:10de0015");
2710MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 2711MODULE_ALIAS("snd-hda-codec-id:10de0018");
2712MODULE_ALIAS("snd-hda-codec-id:10de0019");
2713MODULE_ALIAS("snd-hda-codec-id:10de001a");
2714MODULE_ALIAS("snd-hda-codec-id:10de001b");
2715MODULE_ALIAS("snd-hda-codec-id:10de001c");
2716MODULE_ALIAS("snd-hda-codec-id:10de0040");
2717MODULE_ALIAS("snd-hda-codec-id:10de0041");
2718MODULE_ALIAS("snd-hda-codec-id:10de0042");
2719MODULE_ALIAS("snd-hda-codec-id:10de0043");
2720MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 2721MODULE_ALIAS("snd-hda-codec-id:10de0051");
d52392b1 2722MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 2723MODULE_ALIAS("snd-hda-codec-id:10de0067");
2724MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 2725MODULE_ALIAS("snd-hda-codec-id:11069f80");
2726MODULE_ALIAS("snd-hda-codec-id:11069f81");
2727MODULE_ALIAS("snd-hda-codec-id:11069f84");
2728MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 2729MODULE_ALIAS("snd-hda-codec-id:17e80047");
2730MODULE_ALIAS("snd-hda-codec-id:80860054");
2731MODULE_ALIAS("snd-hda-codec-id:80862801");
2732MODULE_ALIAS("snd-hda-codec-id:80862802");
2733MODULE_ALIAS("snd-hda-codec-id:80862803");
2734MODULE_ALIAS("snd-hda-codec-id:80862804");
2735MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 2736MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 2737MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 2738MODULE_ALIAS("snd-hda-codec-id:80862880");
84eb01be
TI		 2739MODULE_ALIAS("snd-hda-codec-id:808629fb");
2740
2741MODULE_LICENSE("GPL");
2742MODULE_DESCRIPTION("HDMI HD-audio codec");
2743MODULE_ALIAS("snd-hda-codec-intelhdmi");
2744MODULE_ALIAS("snd-hda-codec-nvhdmi");
2745MODULE_ALIAS("snd-hda-codec-atihdmi");
2746
2747static struct hda_codec_preset_list intel_list = {
2748 .preset = snd_hda_preset_hdmi,
2749 .owner = THIS_MODULE,
2750};
2751
2752static int __init patch_hdmi_init(void)
2753{
2754 return snd_hda_add_codec_preset(&intel_list);
2755}
2756
2757static void __exit patch_hdmi_exit(void)
2758{
2759 snd_hda_delete_codec_preset(&intel_list);
2760}
2761
2762module_init(patch_hdmi_init)
2763module_exit(patch_hdmi_exit)
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