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ALSA: hda - Add jack button support
[mirror_ubuntu-eoan-kernel.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
aaa23f86 36#include <linux/pm_runtime.h>
84eb01be 37#include <sound/core.h>
07acecc1 38#include <sound/jack.h>
433968da 39#include <sound/asoundef.h>
d45e6889 40#include <sound/tlv.h>
25adc137
DH		 41#include <sound/hdaudio.h>
42#include <sound/hda_i915.h>
67b90cb8 43#include <sound/hda_chmap.h>
be57bfff 44#include <sound/hda_codec.h>
84eb01be 45#include "hda_local.h"
1835a0f9 46#include "hda_jack.h"
84eb01be 47
0ebaa24c
TI		 48static bool static_hdmi_pcm;
49module_param(static_hdmi_pcm, bool, 0644);
50MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
51
7639a06c
TI		 52#define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
53#define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
54#define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
e2656412 55#define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
91815d8a 56#define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
b9091b1c
SP		 57#define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
58 ((codec)->core.vendor_id == 0x80862800))
2b4584d0 59#define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
432ac1a2 60#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
91815d8a 61 || is_skylake(codec) || is_broxton(codec) \
2b4584d0
GS		 62 || is_kabylake(codec)) || is_geminilake(codec) \
63 || is_cannonlake(codec)
7639a06c
TI		 64#define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
65#define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
ca2e7224 66#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
fb87fa3a 67
384a48d7
SW		 68struct hdmi_spec_per_cvt {
69 hda_nid_t cvt_nid;
70 int assigned;
71 unsigned int channels_min;
72 unsigned int channels_max;
73 u32 rates;
74 u64 formats;
75 unsigned int maxbps;
76};
079d88cc 77
4eea3091
TI		 78/* max. connections to a widget */
79#define HDA_MAX_CONNECTIONS 32
80
384a48d7
SW		 81struct hdmi_spec_per_pin {
82 hda_nid_t pin_nid;
9152085d 83 int dev_id;
a76056f2
LY		 84 /* pin idx, different device entries on the same pin use the same idx */
85 int pin_nid_idx;
384a48d7
SW		 86 int num_mux_nids;
87 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
2df6742f 88 int mux_idx;
1df5a06a 89 hda_nid_t cvt_nid;
744626da
WF		 90
91 struct hda_codec *codec;
384a48d7 92 struct hdmi_eld sink_eld;
a4e9a38b 93 struct mutex lock;
744626da 94 struct delayed_work work;
2bea241a 95 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
a76056f2 96 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
c6e8453e 97 int repoll_count;
b054087d
TI		 98 bool setup; /* the stream has been set up by prepare callback */
99 int channels; /* current number of channels */
1a6003b5 100 bool non_pcm;
d45e6889
TI		 101 bool chmap_set; /* channel-map override by ALSA API? */
102 unsigned char chmap[8]; /* ALSA API channel-map */
cd6a6503 103#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 104 struct snd_info_entry *proc_entry;
105#endif
384a48d7 106};
079d88cc 107
307229d2
AH		 108/* operations used by generic code that can be overridden by patches */
109struct hdmi_ops {
110 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
111 unsigned char *buf, int *eld_size);
112
307229d2
AH		 113 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
114 int ca, int active_channels, int conn_type);
115
116 /* enable/disable HBR (HD passthrough) */
117 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
118
119 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
120 hda_nid_t pin_nid, u32 stream_tag, int format);
121
4846a67e
TI		 122 void (*pin_cvt_fixup)(struct hda_codec *codec,
123 struct hdmi_spec_per_pin *per_pin,
124 hda_nid_t cvt_nid);
307229d2
AH		 125};
126
2bea241a
LY		 127struct hdmi_pcm {
128 struct hda_pcm *pcm;
129 struct snd_jack *jack;
fb087eaa 130 struct snd_kcontrol *eld_ctl;
2bea241a
LY		 131};
132
384a48d7
SW		 133struct hdmi_spec {
134 int num_cvts;
bce0d2a8
TI		 135 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
136 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 137
9152085d
LY		 138 /*
139 * num_pins is the number of virtual pins
140 * for example, there are 3 pins, and each pin
141 * has 4 device entries, then the num_pins is 12
142 */
384a48d7 143 int num_pins;
9152085d
LY		 144 /*
145 * num_nids is the number of real pins
146 * In the above example, num_nids is 3
147 */
148 int num_nids;
149 /*
150 * dev_num is the number of device entries
151 * on each pin.
152 * In the above example, dev_num is 4
153 */
154 int dev_num;
bce0d2a8 155 struct snd_array pins; /* struct hdmi_spec_per_pin */
2bea241a 156 struct hdmi_pcm pcm_rec[16];
42b29870 157 struct mutex pcm_lock;
a76056f2
LY		 158 /* pcm_bitmap means which pcms have been assigned to pins*/
159 unsigned long pcm_bitmap;
2bf3c85a 160 int pcm_used; /* counter of pcm_rec[] */
ac98379a
LY		 161 /* bitmap shows whether the pcm is opened in user space
162 * bit 0 means the first playback PCM (PCM3);
163 * bit 1 means the second playback PCM, and so on.
164 */
165 unsigned long pcm_in_use;
079d88cc 166
4bd038f9 167 struct hdmi_eld temp_eld;
307229d2 168 struct hdmi_ops ops;
75fae117
SW		 169
170 bool dyn_pin_out;
6590faab 171 bool dyn_pcm_assign;
079d88cc 172 /*
5a613584 173 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 174 */
175 struct hda_multi_out multiout;
d0b1252d 176 struct hda_pcm_stream pcm_playback;
25adc137
DH		 177
178 /* i915/powerwell (Haswell+/Valleyview+) specific */
691be973 179 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
ae891abe 180 struct drm_audio_component_audio_ops drm_audio_ops;
67b90cb8
SP		 181
182 struct hdac_chmap chmap;
a87a4d23 183 hda_nid_t vendor_nid;
079d88cc
WF		 184};
185
a57942bf 186#ifdef CONFIG_SND_HDA_COMPONENT
691be973
TI		 187static inline bool codec_has_acomp(struct hda_codec *codec)
188{
189 struct hdmi_spec *spec = codec->spec;
190 return spec->use_acomp_notifier;
191}
f4e3040b
TI		 192#else
193#define codec_has_acomp(codec) false
194#endif
079d88cc
WF		 195
196struct hdmi_audio_infoframe {
197 u8 type; /* 0x84 */
198 u8 ver; /* 0x01 */
199 u8 len; /* 0x0a */
200
53d7d69d
WF		 201 u8 checksum;
202
079d88cc
WF		 203 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
204 u8 SS01_SF24;
205 u8 CXT04;
206 u8 CA;
207 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 208};
209
210struct dp_audio_infoframe {
211 u8 type; /* 0x84 */
212 u8 len; /* 0x1b */
213 u8 ver; /* 0x11 << 2 */
214
215 u8 CC02_CT47; /* match with HDMI infoframe from this on */
216 u8 SS01_SF24;
217 u8 CXT04;
218 u8 CA;
219 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 220};
221
2b203dbb
TI		 222union audio_infoframe {
223 struct hdmi_audio_infoframe hdmi;
224 struct dp_audio_infoframe dp;
225 u8 bytes[0];
226};
227
079d88cc
WF		 228/*
229 * HDMI routines
230 */
231
bce0d2a8
TI		 232#define get_pin(spec, idx) \
233 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
234#define get_cvt(spec, idx) \
235 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
2bea241a
LY		 236/* obtain hdmi_pcm object assigned to idx */
237#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
238/* obtain hda_pcm object assigned to idx */
239#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
bce0d2a8 240
9152085d
LY		 241static int pin_id_to_pin_index(struct hda_codec *codec,
242 hda_nid_t pin_nid, int dev_id)
079d88cc 243{
4e76a883 244 struct hdmi_spec *spec = codec->spec;
384a48d7 245 int pin_idx;
9152085d 246 struct hdmi_spec_per_pin *per_pin;
079d88cc 247
9152085d
LY		 248 /*
249 * (dev_id == -1) means it is NON-MST pin
250 * return the first virtual pin on this port
251 */
252 if (dev_id == -1)
253 dev_id = 0;
254
255 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
256 per_pin = get_pin(spec, pin_idx);
257 if ((per_pin->pin_nid == pin_nid) &&
258 (per_pin->dev_id == dev_id))
384a48d7 259 return pin_idx;
9152085d 260 }
079d88cc 261
4e76a883 262 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
384a48d7
SW		 263 return -EINVAL;
264}
265
2bf3c85a
LY		 266static int hinfo_to_pcm_index(struct hda_codec *codec,
267 struct hda_pcm_stream *hinfo)
268{
269 struct hdmi_spec *spec = codec->spec;
270 int pcm_idx;
271
272 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
273 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
274 return pcm_idx;
275
276 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
277 return -EINVAL;
278}
279
4e76a883 280static int hinfo_to_pin_index(struct hda_codec *codec,
384a48d7
SW		 281 struct hda_pcm_stream *hinfo)
282{
4e76a883 283 struct hdmi_spec *spec = codec->spec;
6590faab 284 struct hdmi_spec_per_pin *per_pin;
384a48d7
SW		 285 int pin_idx;
286
6590faab
LY		 287 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
288 per_pin = get_pin(spec, pin_idx);
2bea241a
LY		 289 if (per_pin->pcm &&
290 per_pin->pcm->pcm->stream == hinfo)
384a48d7 291 return pin_idx;
6590faab 292 }
384a48d7 293
6590faab 294 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
384a48d7
SW		 295 return -EINVAL;
296}
297
022f344b
LY		 298static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
299 int pcm_idx)
300{
301 int i;
302 struct hdmi_spec_per_pin *per_pin;
303
304 for (i = 0; i < spec->num_pins; i++) {
305 per_pin = get_pin(spec, i);
306 if (per_pin->pcm_idx == pcm_idx)
307 return per_pin;
308 }
309 return NULL;
310}
311
4e76a883 312static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
384a48d7 313{
4e76a883 314 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 315 int cvt_idx;
316
317 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 318 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 319 return cvt_idx;
320
4e76a883 321 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 322 return -EINVAL;
323}
324
14bc52b8
PLB		 325static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
326 struct snd_ctl_elem_info *uinfo)
327{
328 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 329 struct hdmi_spec *spec = codec->spec;
a4e9a38b 330 struct hdmi_spec_per_pin *per_pin;
68e03de9 331 struct hdmi_eld *eld;
fb087eaa 332 int pcm_idx;
14bc52b8 333
14bc52b8
PLB		 334 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
335
fb087eaa
LY		 336 pcm_idx = kcontrol->private_value;
337 mutex_lock(&spec->pcm_lock);
338 per_pin = pcm_idx_to_pin(spec, pcm_idx);
339 if (!per_pin) {
340 /* no pin is bound to the pcm */
341 uinfo->count = 0;
f69548ff 342 goto unlock;
fb087eaa 343 }
a4e9a38b 344 eld = &per_pin->sink_eld;
68e03de9 345 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
14bc52b8 346
f69548ff
TI		 347 unlock:
348 mutex_unlock(&spec->pcm_lock);
14bc52b8
PLB		 349 return 0;
350}
351
352static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
353 struct snd_ctl_elem_value *ucontrol)
354{
355 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 356 struct hdmi_spec *spec = codec->spec;
a4e9a38b 357 struct hdmi_spec_per_pin *per_pin;
68e03de9 358 struct hdmi_eld *eld;
fb087eaa 359 int pcm_idx;
f69548ff 360 int err = 0;
14bc52b8 361
fb087eaa
LY		 362 pcm_idx = kcontrol->private_value;
363 mutex_lock(&spec->pcm_lock);
364 per_pin = pcm_idx_to_pin(spec, pcm_idx);
365 if (!per_pin) {
366 /* no pin is bound to the pcm */
367 memset(ucontrol->value.bytes.data, 0,
368 ARRAY_SIZE(ucontrol->value.bytes.data));
f69548ff 369 goto unlock;
fb087eaa 370 }
68e03de9 371
f69548ff 372 eld = &per_pin->sink_eld;
360a8245
DH		 373 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
374 eld->eld_size > ELD_MAX_SIZE) {
68e03de9 375 snd_BUG();
f69548ff
TI		 376 err = -EINVAL;
377 goto unlock;
68e03de9
DH		 378 }
379
380 memset(ucontrol->value.bytes.data, 0,
381 ARRAY_SIZE(ucontrol->value.bytes.data));
382 if (eld->eld_valid)
383 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
384 eld->eld_size);
14bc52b8 385
f69548ff
TI		 386 unlock:
387 mutex_unlock(&spec->pcm_lock);
388 return err;
14bc52b8
PLB		 389}
390
f3b827e0 391static const struct snd_kcontrol_new eld_bytes_ctl = {
14bc52b8
PLB		 392 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
393 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
394 .name = "ELD",
395 .info = hdmi_eld_ctl_info,
396 .get = hdmi_eld_ctl_get,
397};
398
fb087eaa 399static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
14bc52b8
PLB		 400 int device)
401{
402 struct snd_kcontrol *kctl;
403 struct hdmi_spec *spec = codec->spec;
404 int err;
405
406 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
407 if (!kctl)
408 return -ENOMEM;
fb087eaa 409 kctl->private_value = pcm_idx;
14bc52b8
PLB		 410 kctl->id.device = device;
411
fb087eaa
LY		 412 /* no pin nid is associated with the kctl now
413 * tbd: associate pin nid to eld ctl later
414 */
415 err = snd_hda_ctl_add(codec, 0, kctl);
14bc52b8
PLB		 416 if (err < 0)
417 return err;
418
fb087eaa 419 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
14bc52b8
PLB		 420 return 0;
421}
422
079d88cc
WF		 423#ifdef BE_PARANOID
424static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
425 int *packet_index, int *byte_index)
426{
427 int val;
428
429 val = snd_hda_codec_read(codec, pin_nid, 0,
430 AC_VERB_GET_HDMI_DIP_INDEX, 0);
431
432 *packet_index = val >> 5;
433 *byte_index = val & 0x1f;
434}
435#endif
436
437static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
438 int packet_index, int byte_index)
439{
440 int val;
441
442 val = (packet_index << 5) | (byte_index & 0x1f);
443
444 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
445}
446
447static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
448 unsigned char val)
449{
450 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
451}
452
384a48d7 453static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 454{
75fae117
SW		 455 struct hdmi_spec *spec = codec->spec;
456 int pin_out;
457
079d88cc
WF		 458 /* Unmute */
459 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
460 snd_hda_codec_write(codec, pin_nid, 0,
461 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
75fae117
SW		 462
463 if (spec->dyn_pin_out)
464 /* Disable pin out until stream is active */
465 pin_out = 0;
466 else
467 /* Enable pin out: some machines with GM965 gets broken output
468 * when the pin is disabled or changed while using with HDMI
469 */
470 pin_out = PIN_OUT;
471
079d88cc 472 snd_hda_codec_write(codec, pin_nid, 0,
75fae117 473 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 474}
475
a4e9a38b
TI		 476/*
477 * ELD proc files
478 */
479
cd6a6503 480#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 481static void print_eld_info(struct snd_info_entry *entry,
482 struct snd_info_buffer *buffer)
483{
484 struct hdmi_spec_per_pin *per_pin = entry->private_data;
485
486 mutex_lock(&per_pin->lock);
487 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
488 mutex_unlock(&per_pin->lock);
489}
490
491static void write_eld_info(struct snd_info_entry *entry,
492 struct snd_info_buffer *buffer)
493{
494 struct hdmi_spec_per_pin *per_pin = entry->private_data;
495
496 mutex_lock(&per_pin->lock);
497 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
498 mutex_unlock(&per_pin->lock);
499}
500
501static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
502{
503 char name[32];
504 struct hda_codec *codec = per_pin->codec;
505 struct snd_info_entry *entry;
506 int err;
507
508 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
6efdd851 509 err = snd_card_proc_new(codec->card, name, &entry);
a4e9a38b
TI		 510 if (err < 0)
511 return err;
512
513 snd_info_set_text_ops(entry, per_pin, print_eld_info);
514 entry->c.text.write = write_eld_info;
6a73cf46 515 entry->mode |= 0200;
a4e9a38b
TI		 516 per_pin->proc_entry = entry;
517
518 return 0;
519}
520
521static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
522{
1947a114 523 if (!per_pin->codec->bus->shutdown) {
c560a679 524 snd_info_free_entry(per_pin->proc_entry);
a4e9a38b
TI		 525 per_pin->proc_entry = NULL;
526 }
527}
528#else
b55447a7
TI		 529static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
530 int index)
a4e9a38b
TI		 531{
532 return 0;
533}
b55447a7 534static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 535{
536}
537#endif
079d88cc 538
079d88cc
WF		 539/*
540 * Audio InfoFrame routines
541 */
542
543/*
544 * Enable Audio InfoFrame Transmission
545 */
546static void hdmi_start_infoframe_trans(struct hda_codec *codec,
547 hda_nid_t pin_nid)
548{
549 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
550 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
551 AC_DIPXMIT_BEST);
552}
553
554/*
555 * Disable Audio InfoFrame Transmission
556 */
557static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
558 hda_nid_t pin_nid)
559{
560 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
561 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
562 AC_DIPXMIT_DISABLE);
563}
564
565static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
566{
567#ifdef CONFIG_SND_DEBUG_VERBOSE
568 int i;
569 int size;
570
571 size = snd_hdmi_get_eld_size(codec, pin_nid);
4e76a883 572 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
079d88cc
WF		 573
574 for (i = 0; i < 8; i++) {
575 size = snd_hda_codec_read(codec, pin_nid, 0,
576 AC_VERB_GET_HDMI_DIP_SIZE, i);
4e76a883 577 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
079d88cc
WF		 578 }
579#endif
580}
581
582static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
583{
584#ifdef BE_PARANOID
585 int i, j;
586 int size;
587 int pi, bi;
588 for (i = 0; i < 8; i++) {
589 size = snd_hda_codec_read(codec, pin_nid, 0,
590 AC_VERB_GET_HDMI_DIP_SIZE, i);
591 if (size == 0)
592 continue;
593
594 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
595 for (j = 1; j < 1000; j++) {
596 hdmi_write_dip_byte(codec, pin_nid, 0x0);
597 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
598 if (pi != i)
4e76a883 599 codec_dbg(codec, "dip index %d: %d != %d\n",
079d88cc
WF		 600 bi, pi, i);
601 if (bi == 0) /* byte index wrapped around */
602 break;
603 }
4e76a883 604 codec_dbg(codec,
079d88cc
WF		 605 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
606 i, size, j);
607 }
608#endif
609}
610
53d7d69d 611static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 612{
53d7d69d 613 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 614 u8 sum = 0;
615 int i;
616
53d7d69d 617 hdmi_ai->checksum = 0;
079d88cc 618
53d7d69d 619 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 620 sum += bytes[i];
621
53d7d69d 622 hdmi_ai->checksum = -sum;
079d88cc
WF		 623}
624
625static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
626 hda_nid_t pin_nid,
53d7d69d 627 u8 *dip, int size)
079d88cc 628{
079d88cc
WF		 629 int i;
630
631 hdmi_debug_dip_size(codec, pin_nid);
632 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
633
079d88cc 634 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 635 for (i = 0; i < size; i++)
636 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 637}
638
639static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 640 u8 *dip, int size)
079d88cc 641{
079d88cc
WF		 642 u8 val;
643 int i;
644
645 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
646 != AC_DIPXMIT_BEST)
647 return false;
648
649 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 650 for (i = 0; i < size; i++) {
079d88cc
WF		 651 val = snd_hda_codec_read(codec, pin_nid, 0,
652 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 653 if (val != dip[i])
079d88cc
WF		 654 return false;
655 }
656
657 return true;
658}
659
307229d2
AH		 660static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
661 hda_nid_t pin_nid,
662 int ca, int active_channels,
663 int conn_type)
664{
665 union audio_infoframe ai;
666
caaf5ef9 667 memset(&ai, 0, sizeof(ai));
307229d2
AH		 668 if (conn_type == 0) { /* HDMI */
669 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
670
671 hdmi_ai->type = 0x84;
672 hdmi_ai->ver = 0x01;
673 hdmi_ai->len = 0x0a;
674 hdmi_ai->CC02_CT47 = active_channels - 1;
675 hdmi_ai->CA = ca;
676 hdmi_checksum_audio_infoframe(hdmi_ai);
677 } else if (conn_type == 1) { /* DisplayPort */
678 struct dp_audio_infoframe *dp_ai = &ai.dp;
679
680 dp_ai->type = 0x84;
681 dp_ai->len = 0x1b;
682 dp_ai->ver = 0x11 << 2;
683 dp_ai->CC02_CT47 = active_channels - 1;
684 dp_ai->CA = ca;
685 } else {
4e76a883 686 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
307229d2
AH		 687 pin_nid);
688 return;
689 }
690
691 /*
692 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
693 * sizeof(*dp_ai) to avoid partial match/update problems when
694 * the user switches between HDMI/DP monitors.
695 */
696 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
697 sizeof(ai))) {
4e76a883
TI		 698 codec_dbg(codec,
699 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
307229d2
AH		 700 pin_nid,
701 active_channels, ca);
702 hdmi_stop_infoframe_trans(codec, pin_nid);
703 hdmi_fill_audio_infoframe(codec, pin_nid,
704 ai.bytes, sizeof(ai));
705 hdmi_start_infoframe_trans(codec, pin_nid);
706 }
707}
708
b054087d
TI		 709static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
710 struct hdmi_spec_per_pin *per_pin,
711 bool non_pcm)
079d88cc 712{
307229d2 713 struct hdmi_spec *spec = codec->spec;
739ffee9 714 struct hdac_chmap *chmap = &spec->chmap;
384a48d7 715 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 716 int channels = per_pin->channels;
1df5a06a 717 int active_channels;
384a48d7 718 struct hdmi_eld *eld;
828cb4ed 719 int ca;
079d88cc 720
b054087d
TI		 721 if (!channels)
722 return;
723
44bb6d0c
TI		 724 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
725 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
58f7d28d
ML		 726 snd_hda_codec_write(codec, pin_nid, 0,
727 AC_VERB_SET_AMP_GAIN_MUTE,
728 AMP_OUT_UNMUTE);
729
bce0d2a8 730 eld = &per_pin->sink_eld;
079d88cc 731
bb63f726 732 ca = snd_hdac_channel_allocation(&codec->core,
828cb4ed
SP		 733 eld->info.spk_alloc, channels,
734 per_pin->chmap_set, non_pcm, per_pin->chmap);
384a48d7 735
bb63f726 736 active_channels = snd_hdac_get_active_channels(ca);
1df5a06a 737
739ffee9
SP		 738 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
739 active_channels);
1df5a06a 740
39edac70
AH		 741 /*
742 * always configure channel mapping, it may have been changed by the
743 * user in the meantime
744 */
bb63f726 745 snd_hdac_setup_channel_mapping(&spec->chmap,
828cb4ed
SP		 746 pin_nid, non_pcm, ca, channels,
747 per_pin->chmap, per_pin->chmap_set);
39edac70 748
307229d2
AH		 749 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
750 eld->info.conn_type);
433968da 751
1a6003b5 752 per_pin->non_pcm = non_pcm;
079d88cc
WF		 753}
754
079d88cc
WF		 755/*
756 * Unsolicited events
757 */
758
efe47108 759static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 760
9152085d
LY		 761static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
762 int dev_id)
079d88cc
WF		 763{
764 struct hdmi_spec *spec = codec->spec;
9152085d 765 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
1a4f69d5 766
20ce9029
DH		 767 if (pin_idx < 0)
768 return;
aaa23f86 769 mutex_lock(&spec->pcm_lock);
20ce9029
DH		 770 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
771 snd_hda_jack_report_sync(codec);
aaa23f86 772 mutex_unlock(&spec->pcm_lock);
20ce9029
DH		 773}
774
1a4f69d5
TI		 775static void jack_callback(struct hda_codec *codec,
776 struct hda_jack_callback *jack)
777{
9152085d
LY		 778 /* hda_jack don't support DP MST */
779 check_presence_and_report(codec, jack->nid, 0);
1a4f69d5
TI		 780}
781
20ce9029
DH		 782static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
783{
3a93897e 784 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 785 struct hda_jack_tbl *jack;
2e59e5ab 786 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e 787
9152085d
LY		 788 /*
789 * assume DP MST uses dyn_pcm_assign and acomp and
790 * never comes here
791 * if DP MST supports unsol event, below code need
792 * consider dev_entry
793 */
3a93897e
TI		 794 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
795 if (!jack)
796 return;
3a93897e 797 jack->jack_dirty = 1;
079d88cc 798
4e76a883 799 codec_dbg(codec,
2e59e5ab 800 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 801 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 802 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 803
9152085d
LY		 804 /* hda_jack don't support DP MST */
805 check_presence_and_report(codec, jack->nid, 0);
079d88cc
WF		 806}
807
808static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
809{
810 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
811 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
812 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
813 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
814
4e76a883 815 codec_info(codec,
e9ea8e8f 816 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 817 codec->addr,
079d88cc
WF		 818 tag,
819 subtag,
820 cp_state,
821 cp_ready);
822
823 /* TODO */
824 if (cp_state)
825 ;
826 if (cp_ready)
827 ;
828}
829
830
831static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
832{
079d88cc
WF		 833 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
834 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
835
3a93897e 836 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
4e76a883 837 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
079d88cc
WF		 838 return;
839 }
840
841 if (subtag == 0)
842 hdmi_intrinsic_event(codec, res);
843 else
844 hdmi_non_intrinsic_event(codec, res);
845}
846
58f7d28d 847static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 848 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 849{
58f7d28d 850 int pwr;
83f26ad2 851
53b434f0
WX		 852 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
853 * thus pins could only choose converter 0 for use. Make sure the
854 * converters are in correct power state */
fd678cac 855 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 856 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
857
fd678cac 858 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 859 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
860 AC_PWRST_D0);
861 msleep(40);
862 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
863 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
4e76a883 864 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
83f26ad2 865 }
83f26ad2
DH		 866}
867
079d88cc
WF		 868/*
869 * Callbacks
870 */
871
92f10b3f
TI		 872/* HBR should be Non-PCM, 8 channels */
873#define is_hbr_format(format) \
874 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
875
307229d2
AH		 876static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
877 bool hbr)
079d88cc 878{
307229d2 879 int pinctl, new_pinctl;
83f26ad2 880
384a48d7
SW		 881 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
882 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 883 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
884
13122e6e
AH		 885 if (pinctl < 0)
886 return hbr ? -EINVAL : 0;
887
ea87d1c4 888 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 889 if (hbr)
ea87d1c4
AH		 890 new_pinctl |= AC_PINCTL_EPT_HBR;
891 else
892 new_pinctl |= AC_PINCTL_EPT_NATIVE;
893
4e76a883
TI		 894 codec_dbg(codec,
895 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
384a48d7 896 pin_nid,
ea87d1c4
AH		 897 pinctl == new_pinctl ? "" : "new-",
898 new_pinctl);
899
900 if (pinctl != new_pinctl)
384a48d7 901 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 902 AC_VERB_SET_PIN_WIDGET_CONTROL,
903 new_pinctl);
307229d2
AH		 904 } else if (hbr)
905 return -EINVAL;
ea87d1c4 906
307229d2
AH		 907 return 0;
908}
909
910static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
911 hda_nid_t pin_nid, u32 stream_tag, int format)
912{
913 struct hdmi_spec *spec = codec->spec;
5a5d718f 914 unsigned int param;
307229d2
AH		 915 int err;
916
307229d2
AH		 917 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
918
919 if (err) {
4e76a883 920 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
307229d2 921 return err;
ea87d1c4 922 }
079d88cc 923
5a5d718f
SP		 924 if (is_haswell_plus(codec)) {
925
926 /*
927 * on recent platforms IEC Coding Type is required for HBR
928 * support, read current Digital Converter settings and set
929 * ICT bitfield if needed.
930 */
931 param = snd_hda_codec_read(codec, cvt_nid, 0,
932 AC_VERB_GET_DIGI_CONVERT_1, 0);
933
934 param = (param >> 16) & ~(AC_DIG3_ICT);
935
936 /* on recent platforms ICT mode is required for HBR support */
937 if (is_hbr_format(format))
938 param |= 0x1;
939
940 snd_hda_codec_write(codec, cvt_nid, 0,
941 AC_VERB_SET_DIGI_CONVERT_3, param);
942 }
943
384a48d7 944 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 945 return 0;
079d88cc
WF		 946}
947
42b29870
LY		 948/* Try to find an available converter
949 * If pin_idx is less then zero, just try to find an available converter.
950 * Otherwise, try to find an available converter and get the cvt mux index
951 * of the pin.
952 */
7ef166b8 953static int hdmi_choose_cvt(struct hda_codec *codec,
4846a67e 954 int pin_idx, int *cvt_id)
bbbe3390
TI		 955{
956 struct hdmi_spec *spec = codec->spec;
384a48d7 957 struct hdmi_spec_per_pin *per_pin;
384a48d7 958 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 959 int cvt_idx, mux_idx = 0;
bbbe3390 960
42b29870
LY		 961 /* pin_idx < 0 means no pin will be bound to the converter */
962 if (pin_idx < 0)
963 per_pin = NULL;
964 else
965 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 966
967 /* Dynamically assign converter to stream */
968 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 969 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 970
384a48d7
SW		 971 /* Must not already be assigned */
972 if (per_cvt->assigned)
973 continue;
42b29870
LY		 974 if (per_pin == NULL)
975 break;
384a48d7
SW		 976 /* Must be in pin's mux's list of converters */
977 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
978 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
979 break;
980 /* Not in mux list */
981 if (mux_idx == per_pin->num_mux_nids)
982 continue;
983 break;
984 }
7ef166b8 985
384a48d7
SW		 986 /* No free converters */
987 if (cvt_idx == spec->num_cvts)
42b29870 988 return -EBUSY;
384a48d7 989
42b29870
LY		 990 if (per_pin != NULL)
991 per_pin->mux_idx = mux_idx;
2df6742f 992
7ef166b8
WX		 993 if (cvt_id)
994 *cvt_id = cvt_idx;
7ef166b8
WX		 995
996 return 0;
997}
998
2df6742f
ML		 999/* Assure the pin select the right convetor */
1000static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1001 struct hdmi_spec_per_pin *per_pin)
1002{
1003 hda_nid_t pin_nid = per_pin->pin_nid;
1004 int mux_idx, curr;
1005
1006 mux_idx = per_pin->mux_idx;
1007 curr = snd_hda_codec_read(codec, pin_nid, 0,
1008 AC_VERB_GET_CONNECT_SEL, 0);
1009 if (curr != mux_idx)
1010 snd_hda_codec_write_cache(codec, pin_nid, 0,
1011 AC_VERB_SET_CONNECT_SEL,
1012 mux_idx);
1013}
1014
42b29870
LY		 1015/* get the mux index for the converter of the pins
1016 * converter's mux index is the same for all pins on Intel platform
1017 */
1018static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1019 hda_nid_t cvt_nid)
1020{
1021 int i;
1022
1023 for (i = 0; i < spec->num_cvts; i++)
1024 if (spec->cvt_nids[i] == cvt_nid)
1025 return i;
1026 return -EINVAL;
1027}
1028
300016b9
ML		 1029/* Intel HDMI workaround to fix audio routing issue:
1030 * For some Intel display codecs, pins share the same connection list.
1031 * So a conveter can be selected by multiple pins and playback on any of these
1032 * pins will generate sound on the external display, because audio flows from
1033 * the same converter to the display pipeline. Also muting one pin may make
1034 * other pins have no sound output.
1035 * So this function assures that an assigned converter for a pin is not selected
1036 * by any other pins.
1037 */
1038static void intel_not_share_assigned_cvt(struct hda_codec *codec,
9152085d
LY		 1039 hda_nid_t pin_nid,
1040 int dev_id, int mux_idx)
7ef166b8
WX		 1041{
1042 struct hdmi_spec *spec = codec->spec;
7639a06c 1043 hda_nid_t nid;
f82d7d16
ML		 1044 int cvt_idx, curr;
1045 struct hdmi_spec_per_cvt *per_cvt;
9152085d
LY		 1046 struct hdmi_spec_per_pin *per_pin;
1047 int pin_idx;
1048
1049 /* configure the pins connections */
1050 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1051 int dev_id_saved;
1052 int dev_num;
7ef166b8 1053
9152085d
LY		 1054 per_pin = get_pin(spec, pin_idx);
1055 /*
1056 * pin not connected to monitor
1057 * no need to operate on it
1058 */
1059 if (!per_pin->pcm)
1060 continue;
f82d7d16 1061
9152085d
LY		 1062 if ((per_pin->pin_nid == pin_nid) &&
1063 (per_pin->dev_id == dev_id))
f82d7d16 1064 continue;
7ef166b8 1065
9152085d
LY		 1066 /*
1067 * if per_pin->dev_id >= dev_num,
1068 * snd_hda_get_dev_select() will fail,
1069 * and the following operation is unpredictable.
1070 * So skip this situation.
1071 */
1072 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1073 if (per_pin->dev_id >= dev_num)
7ef166b8
WX		 1074 continue;
1075
9152085d
LY		 1076 nid = per_pin->pin_nid;
1077
1078 /*
1079 * Calling this function should not impact
1080 * on the device entry selection
1081 * So let's save the dev id for each pin,
1082 * and restore it when return
1083 */
1084 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1085 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
f82d7d16 1086 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1087 AC_VERB_GET_CONNECT_SEL, 0);
9152085d
LY		 1088 if (curr != mux_idx) {
1089 snd_hda_set_dev_select(codec, nid, dev_id_saved);
f82d7d16 1090 continue;
9152085d
LY		 1091 }
1092
7ef166b8 1093
f82d7d16
ML		 1094 /* choose an unassigned converter. The conveters in the
1095 * connection list are in the same order as in the codec.
1096 */
1097 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1098 per_cvt = get_cvt(spec, cvt_idx);
1099 if (!per_cvt->assigned) {
4e76a883
TI		 1100 codec_dbg(codec,
1101 "choose cvt %d for pin nid %d\n",
f82d7d16
ML		 1102 cvt_idx, nid);
1103 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1104 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1105 cvt_idx);
1106 break;
1107 }
7ef166b8 1108 }
9152085d 1109 snd_hda_set_dev_select(codec, nid, dev_id_saved);
7ef166b8
WX		 1110 }
1111}
1112
42b29870
LY		 1113/* A wrapper of intel_not_share_asigned_cvt() */
1114static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
9152085d 1115 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
42b29870
LY		 1116{
1117 int mux_idx;
1118 struct hdmi_spec *spec = codec->spec;
1119
42b29870
LY		 1120 /* On Intel platform, the mapping of converter nid to
1121 * mux index of the pins are always the same.
1122 * The pin nid may be 0, this means all pins will not
1123 * share the converter.
1124 */
1125 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1126 if (mux_idx >= 0)
9152085d 1127 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
42b29870
LY		 1128}
1129
4846a67e
TI		 1130/* skeleton caller of pin_cvt_fixup ops */
1131static void pin_cvt_fixup(struct hda_codec *codec,
1132 struct hdmi_spec_per_pin *per_pin,
1133 hda_nid_t cvt_nid)
1134{
1135 struct hdmi_spec *spec = codec->spec;
1136
1137 if (spec->ops.pin_cvt_fixup)
1138 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1139}
1140
42b29870
LY		 1141/* called in hdmi_pcm_open when no pin is assigned to the PCM
1142 * in dyn_pcm_assign mode.
1143 */
1144static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1145 struct hda_codec *codec,
1146 struct snd_pcm_substream *substream)
1147{
1148 struct hdmi_spec *spec = codec->spec;
1149 struct snd_pcm_runtime *runtime = substream->runtime;
ac98379a 1150 int cvt_idx, pcm_idx;
42b29870
LY		 1151 struct hdmi_spec_per_cvt *per_cvt = NULL;
1152 int err;
1153
ac98379a
LY		 1154 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1155 if (pcm_idx < 0)
1156 return -EINVAL;
1157
4846a67e 1158 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
42b29870
LY		 1159 if (err)
1160 return err;
1161
1162 per_cvt = get_cvt(spec, cvt_idx);
1163 per_cvt->assigned = 1;
1164 hinfo->nid = per_cvt->cvt_nid;
1165
4846a67e 1166 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
42b29870 1167
ac98379a 1168 set_bit(pcm_idx, &spec->pcm_in_use);
42b29870
LY		 1169 /* todo: setup spdif ctls assign */
1170
1171 /* Initially set the converter's capabilities */
1172 hinfo->channels_min = per_cvt->channels_min;
1173 hinfo->channels_max = per_cvt->channels_max;
1174 hinfo->rates = per_cvt->rates;
1175 hinfo->formats = per_cvt->formats;
1176 hinfo->maxbps = per_cvt->maxbps;
1177
1178 /* Store the updated parameters */
1179 runtime->hw.channels_min = hinfo->channels_min;
1180 runtime->hw.channels_max = hinfo->channels_max;
1181 runtime->hw.formats = hinfo->formats;
1182 runtime->hw.rates = hinfo->rates;
1183
1184 snd_pcm_hw_constraint_step(substream->runtime, 0,
1185 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1186 return 0;
1187}
1188
7ef166b8
WX		 1189/*
1190 * HDA PCM callbacks
1191 */
1192static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1193 struct hda_codec *codec,
1194 struct snd_pcm_substream *substream)
1195{
1196 struct hdmi_spec *spec = codec->spec;
1197 struct snd_pcm_runtime *runtime = substream->runtime;
4846a67e 1198 int pin_idx, cvt_idx, pcm_idx;
7ef166b8
WX		 1199 struct hdmi_spec_per_pin *per_pin;
1200 struct hdmi_eld *eld;
1201 struct hdmi_spec_per_cvt *per_cvt = NULL;
1202 int err;
1203
1204 /* Validate hinfo */
2bf3c85a
LY		 1205 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1206 if (pcm_idx < 0)
7ef166b8 1207 return -EINVAL;
2bf3c85a 1208
42b29870 1209 mutex_lock(&spec->pcm_lock);
4e76a883 1210 pin_idx = hinfo_to_pin_index(codec, hinfo);
42b29870
LY		 1211 if (!spec->dyn_pcm_assign) {
1212 if (snd_BUG_ON(pin_idx < 0)) {
f69548ff
TI		 1213 err = -EINVAL;
1214 goto unlock;
42b29870
LY		 1215 }
1216 } else {
1217 /* no pin is assigned to the PCM
1218 * PA need pcm open successfully when probe
1219 */
1220 if (pin_idx < 0) {
1221 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
f69548ff 1222 goto unlock;
42b29870
LY		 1223 }
1224 }
7ef166b8 1225
4846a67e 1226 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
f69548ff
TI		 1227 if (err < 0)
1228 goto unlock;
7ef166b8
WX		 1229
1230 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1231 /* Claim converter */
1232 per_cvt->assigned = 1;
42b29870 1233
ac98379a 1234 set_bit(pcm_idx, &spec->pcm_in_use);
42b29870 1235 per_pin = get_pin(spec, pin_idx);
1df5a06a 1236 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1237 hinfo->nid = per_cvt->cvt_nid;
1238
9152085d 1239 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
bddee96b 1240 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7 1241 AC_VERB_SET_CONNECT_SEL,
4846a67e 1242 per_pin->mux_idx);
7ef166b8
WX		 1243
1244 /* configure unused pins to choose other converters */
4846a67e 1245 pin_cvt_fixup(codec, per_pin, 0);
7ef166b8 1246
2bf3c85a 1247 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
bbbe3390 1248
2def8172 1249 /* Initially set the converter's capabilities */
384a48d7
SW		 1250 hinfo->channels_min = per_cvt->channels_min;
1251 hinfo->channels_max = per_cvt->channels_max;
1252 hinfo->rates = per_cvt->rates;
1253 hinfo->formats = per_cvt->formats;
1254 hinfo->maxbps = per_cvt->maxbps;
2def8172 1255
42b29870 1256 eld = &per_pin->sink_eld;
384a48d7 1257 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1258 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1259 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1260 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1261 !hinfo->rates || !hinfo->formats) {
1262 per_cvt->assigned = 0;
1263 hinfo->nid = 0;
2bf3c85a 1264 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
f69548ff
TI		 1265 err = -ENODEV;
1266 goto unlock;
2ad779b7 1267 }
bbbe3390 1268 }
2def8172
SW		 1269
1270 /* Store the updated parameters */
639cef0e
TI		 1271 runtime->hw.channels_min = hinfo->channels_min;
1272 runtime->hw.channels_max = hinfo->channels_max;
1273 runtime->hw.formats = hinfo->formats;
1274 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1275
1276 snd_pcm_hw_constraint_step(substream->runtime, 0,
1277 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
f69548ff
TI		 1278 unlock:
1279 mutex_unlock(&spec->pcm_lock);
1280 return err;
bbbe3390
TI		 1281}
1282
079d88cc
WF		 1283/*
1284 * HDA/HDMI auto parsing
1285 */
384a48d7 1286static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1287{
1288 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1289 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1290 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1291
1292 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
4e76a883
TI		 1293 codec_warn(codec,
1294 "HDMI: pin %d wcaps %#x does not support connection list\n",
079d88cc
WF		 1295 pin_nid, get_wcaps(codec, pin_nid));
1296 return -EINVAL;
1297 }
1298
9152085d 1299 /* all the device entries on the same pin have the same conn list */
384a48d7
SW		 1300 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1301 per_pin->mux_nids,
1302 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1303
1304 return 0;
1305}
1306
a76056f2
LY		 1307static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1308 struct hdmi_spec_per_pin *per_pin)
1309{
1310 int i;
1311
1312 /* try the prefer PCM */
1313 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1314 return per_pin->pin_nid_idx;
1315
1316 /* have a second try; check the "reserved area" over num_pins */
9152085d 1317 for (i = spec->num_nids; i < spec->pcm_used; i++) {
a76056f2
LY		 1318 if (!test_bit(i, &spec->pcm_bitmap))
1319 return i;
1320 }
1321
1322 /* the last try; check the empty slots in pins */
9152085d 1323 for (i = 0; i < spec->num_nids; i++) {
a76056f2
LY		 1324 if (!test_bit(i, &spec->pcm_bitmap))
1325 return i;
1326 }
1327 return -EBUSY;
1328}
1329
1330static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1331 struct hdmi_spec_per_pin *per_pin)
1332{
1333 int idx;
1334
1335 /* pcm already be attached to the pin */
1336 if (per_pin->pcm)
1337 return;
1338 idx = hdmi_find_pcm_slot(spec, per_pin);
d10a80de 1339 if (idx == -EBUSY)
a76056f2
LY		 1340 return;
1341 per_pin->pcm_idx = idx;
2bea241a 1342 per_pin->pcm = get_hdmi_pcm(spec, idx);
a76056f2
LY		 1343 set_bit(idx, &spec->pcm_bitmap);
1344}
1345
1346static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1347 struct hdmi_spec_per_pin *per_pin)
1348{
1349 int idx;
1350
1351 /* pcm already be detached from the pin */
1352 if (!per_pin->pcm)
1353 return;
1354 idx = per_pin->pcm_idx;
1355 per_pin->pcm_idx = -1;
1356 per_pin->pcm = NULL;
1357 if (idx >= 0 && idx < spec->pcm_used)
1358 clear_bit(idx, &spec->pcm_bitmap);
1359}
1360
ac98379a
LY		 1361static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1362 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1363{
1364 int mux_idx;
1365
1366 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1367 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1368 break;
1369 return mux_idx;
1370}
1371
1372static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1373
1374static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1375 struct hdmi_spec_per_pin *per_pin)
1376{
1377 struct hda_codec *codec = per_pin->codec;
1378 struct hda_pcm *pcm;
1379 struct hda_pcm_stream *hinfo;
1380 struct snd_pcm_substream *substream;
1381 int mux_idx;
1382 bool non_pcm;
1383
1384 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
2bea241a 1385 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
ac98379a
LY		 1386 else
1387 return;
8a7d6003
TI		 1388 if (!pcm->pcm)
1389 return;
ac98379a
LY		 1390 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1391 return;
1392
1393 /* hdmi audio only uses playback and one substream */
1394 hinfo = pcm->stream;
1395 substream = pcm->pcm->streams[0].substream;
1396
1397 per_pin->cvt_nid = hinfo->nid;
1398
1399 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
9152085d
LY		 1400 if (mux_idx < per_pin->num_mux_nids) {
1401 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1402 per_pin->dev_id);
ac98379a
LY		 1403 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1404 AC_VERB_SET_CONNECT_SEL,
1405 mux_idx);
9152085d 1406 }
ac98379a
LY		 1407 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1408
1409 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1410 if (substream->runtime)
1411 per_pin->channels = substream->runtime->channels;
1412 per_pin->setup = true;
1413 per_pin->mux_idx = mux_idx;
1414
1415 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1416}
1417
1418static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1419 struct hdmi_spec_per_pin *per_pin)
1420{
1421 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1422 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1423
1424 per_pin->chmap_set = false;
1425 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1426
1427 per_pin->setup = false;
1428 per_pin->channels = 0;
1429}
1430
e90247f9
TI		 1431/* update per_pin ELD from the given new ELD;
1432 * setup info frame and notification accordingly
1433 */
1434static void update_eld(struct hda_codec *codec,
1435 struct hdmi_spec_per_pin *per_pin,
1436 struct hdmi_eld *eld)
1437{
1438 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
a76056f2 1439 struct hdmi_spec *spec = codec->spec;
e90247f9
TI		 1440 bool old_eld_valid = pin_eld->eld_valid;
1441 bool eld_changed;
fb087eaa 1442 int pcm_idx = -1;
e90247f9 1443
fb087eaa
LY		 1444 /* for monitor disconnection, save pcm_idx firstly */
1445 pcm_idx = per_pin->pcm_idx;
a76056f2 1446 if (spec->dyn_pcm_assign) {
ac98379a 1447 if (eld->eld_valid) {
a76056f2 1448 hdmi_attach_hda_pcm(spec, per_pin);
ac98379a
LY		 1449 hdmi_pcm_setup_pin(spec, per_pin);
1450 } else {
1451 hdmi_pcm_reset_pin(spec, per_pin);
a76056f2 1452 hdmi_detach_hda_pcm(spec, per_pin);
ac98379a 1453 }
a76056f2 1454 }
fb087eaa
LY		 1455 /* if pcm_idx == -1, it means this is in monitor connection event
1456 * we can get the correct pcm_idx now.
1457 */
1458 if (pcm_idx == -1)
1459 pcm_idx = per_pin->pcm_idx;
a76056f2 1460
e90247f9
TI		 1461 if (eld->eld_valid)
1462 snd_hdmi_show_eld(codec, &eld->info);
1463
1464 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1465 if (eld->eld_valid && pin_eld->eld_valid)
1466 if (pin_eld->eld_size != eld->eld_size ||
1467 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1468 eld->eld_size) != 0)
1469 eld_changed = true;
1470
bd481285 1471 pin_eld->monitor_present = eld->monitor_present;
e90247f9
TI		 1472 pin_eld->eld_valid = eld->eld_valid;
1473 pin_eld->eld_size = eld->eld_size;
1474 if (eld->eld_valid)
1475 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1476 pin_eld->info = eld->info;
1477
1478 /*
1479 * Re-setup pin and infoframe. This is needed e.g. when
1480 * - sink is first plugged-in
1481 * - transcoder can change during stream playback on Haswell
1482 * and this can make HW reset converter selection on a pin.
1483 */
1484 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
4846a67e 1485 pin_cvt_fixup(codec, per_pin, 0);
e90247f9
TI		 1486 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1487 }
1488
fb087eaa 1489 if (eld_changed && pcm_idx >= 0)
e90247f9
TI		 1490 snd_ctl_notify(codec->card,
1491 SNDRV_CTL_EVENT_MASK_VALUE |
1492 SNDRV_CTL_EVENT_MASK_INFO,
fb087eaa 1493 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
e90247f9
TI		 1494}
1495
788d441a
TI		 1496/* update ELD and jack state via HD-audio verbs */
1497static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1498 int repoll)
079d88cc 1499{
464837a7 1500 struct hda_jack_tbl *jack;
744626da 1501 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1502 struct hdmi_spec *spec = codec->spec;
1503 struct hdmi_eld *eld = &spec->temp_eld;
744626da 1504 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1505 /*
1506 * Always execute a GetPinSense verb here, even when called from
1507 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1508 * response's PD bit is not the real PD value, but indicates that
1509 * the real PD value changed. An older version of the HD-audio
1510 * specification worked this way. Hence, we just ignore the data in
1511 * the unsolicited response to avoid custom WARs.
1512 */
da4a7a39 1513 int present;
efe47108 1514 bool ret;
9a5e5234 1515 bool do_repoll = false;
079d88cc 1516
da4a7a39
DH		 1517 present = snd_hda_pin_sense(codec, pin_nid);
1518
a4e9a38b 1519 mutex_lock(&per_pin->lock);
c44da62b
TI		 1520 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1521 if (eld->monitor_present)
4bd038f9
DH		 1522 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1523 else
1524 eld->eld_valid = false;
079d88cc 1525
4e76a883 1526 codec_dbg(codec,
384a48d7 1527 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
c44da62b 1528 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
5d44f927 1529
4bd038f9 1530 if (eld->eld_valid) {
307229d2 1531 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1532 &eld->eld_size) < 0)
4bd038f9 1533 eld->eld_valid = false;
1613d6b4 1534 else {
79514d47 1535 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1613d6b4 1536 eld->eld_size) < 0)
4bd038f9 1537 eld->eld_valid = false;
1613d6b4 1538 }
9a5e5234
TI		 1539 if (!eld->eld_valid && repoll)
1540 do_repoll = true;
744626da 1541 }
4bd038f9 1542
9a5e5234 1543 if (do_repoll)
e90247f9
TI		 1544 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1545 else
1546 update_eld(codec, per_pin, eld);
92c69e79 1547
c44da62b 1548 ret = !repoll || !eld->monitor_present || eld->eld_valid;
464837a7
DH		 1549
1550 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1551 if (jack)
1552 jack->block_report = !ret;
1553
a4e9a38b 1554 mutex_unlock(&per_pin->lock);
efe47108 1555 return ret;
079d88cc
WF		 1556}
1557
3184270e
LY		 1558static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1559 struct hdmi_spec_per_pin *per_pin)
1560{
1561 struct hdmi_spec *spec = codec->spec;
1562 struct snd_jack *jack = NULL;
1563 struct hda_jack_tbl *jack_tbl;
1564
1565 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1566 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1567 * NULL even after snd_hda_jack_tbl_clear() is called to
1568 * free snd_jack. This may cause access invalid memory
1569 * when calling snd_jack_report
1570 */
1571 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1572 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1573 else if (!spec->dyn_pcm_assign) {
9152085d
LY		 1574 /*
1575 * jack tbl doesn't support DP MST
1576 * DP MST will use dyn_pcm_assign,
1577 * so DP MST will never come here
1578 */
3184270e
LY		 1579 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1580 if (jack_tbl)
1581 jack = jack_tbl->jack;
1582 }
1583 return jack;
1584}
1585
788d441a
TI		 1586/* update ELD and jack state via audio component */
1587static void sync_eld_via_acomp(struct hda_codec *codec,
1588 struct hdmi_spec_per_pin *per_pin)
1589{
788d441a
TI		 1590 struct hdmi_spec *spec = codec->spec;
1591 struct hdmi_eld *eld = &spec->temp_eld;
25e4abb3 1592 struct snd_jack *jack = NULL;
788d441a
TI		 1593 int size;
1594
e2dc7d7d 1595 mutex_lock(&per_pin->lock);
c64c1437 1596 eld->monitor_present = false;
9152085d
LY		 1597 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1598 per_pin->dev_id, &eld->monitor_present,
1599 eld->eld_buffer, ELD_MAX_SIZE);
e2dc7d7d
TI		 1600 if (size > 0) {
1601 size = min(size, ELD_MAX_SIZE);
1602 if (snd_hdmi_parse_eld(codec, &eld->info,
1603 eld->eld_buffer, size) < 0)
1604 size = -EINVAL;
1605 }
788d441a 1606
e2dc7d7d
TI		 1607 if (size > 0) {
1608 eld->eld_valid = true;
1609 eld->eld_size = size;
1610 } else {
1611 eld->eld_valid = false;
1612 eld->eld_size = 0;
788d441a 1613 }
e2dc7d7d 1614
25e4abb3
LY		 1615 /* pcm_idx >=0 before update_eld() means it is in monitor
1616 * disconnected event. Jack must be fetched before update_eld()
1617 */
3184270e 1618 jack = pin_idx_to_jack(codec, per_pin);
e2dc7d7d 1619 update_eld(codec, per_pin, eld);
3184270e
LY		 1620 if (jack == NULL)
1621 jack = pin_idx_to_jack(codec, per_pin);
25e4abb3
LY		 1622 if (jack == NULL)
1623 goto unlock;
1624 snd_jack_report(jack,
e2dc7d7d
TI		 1625 eld->monitor_present ? SND_JACK_AVOUT : 0);
1626 unlock:
1627 mutex_unlock(&per_pin->lock);
788d441a
TI		 1628}
1629
1630static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1631{
1632 struct hda_codec *codec = per_pin->codec;
a76056f2 1633 int ret;
788d441a 1634
222bde03 1635 /* no temporary power up/down needed for component notifier */
aaa23f86
CW		 1636 if (!codec_has_acomp(codec)) {
1637 ret = snd_hda_power_up_pm(codec);
1638 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) {
1639 snd_hda_power_down_pm(codec);
1640 return false;
1641 }
1642 }
222bde03 1643
788d441a
TI		 1644 if (codec_has_acomp(codec)) {
1645 sync_eld_via_acomp(codec, per_pin);
a76056f2 1646 ret = false; /* don't call snd_hda_jack_report_sync() */
788d441a 1647 } else {
a76056f2 1648 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
788d441a 1649 }
a76056f2 1650
222bde03
TI		 1651 if (!codec_has_acomp(codec))
1652 snd_hda_power_down_pm(codec);
1653
a76056f2 1654 return ret;
788d441a
TI		 1655}
1656
744626da
WF		 1657static void hdmi_repoll_eld(struct work_struct *work)
1658{
1659 struct hdmi_spec_per_pin *per_pin =
1660 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
aaa23f86
CW		 1661 struct hda_codec *codec = per_pin->codec;
1662 struct hdmi_spec *spec = codec->spec;
744626da 1663
c6e8453e
WF		 1664 if (per_pin->repoll_count++ > 6)
1665 per_pin->repoll_count = 0;
1666
aaa23f86 1667 mutex_lock(&spec->pcm_lock);
efe47108
TI		 1668 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1669 snd_hda_jack_report_sync(per_pin->codec);
aaa23f86 1670 mutex_unlock(&spec->pcm_lock);
744626da
WF		 1671}
1672
c88d4e84
TI		 1673static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1674 hda_nid_t nid);
1675
079d88cc
WF		 1676static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1677{
1678 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1679 unsigned int caps, config;
1680 int pin_idx;
1681 struct hdmi_spec_per_pin *per_pin;
07acecc1 1682 int err;
9152085d 1683 int dev_num, i;
079d88cc 1684
efc2f8de 1685 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1686 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1687 return 0;
1688
9152085d
LY		 1689 /*
1690 * For DP MST audio, Configuration Default is the same for
1691 * all device entries on the same pin
1692 */
efc2f8de 1693 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1694 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1695 return 0;
1696
9152085d
LY		 1697 /*
1698 * To simplify the implementation, malloc all
1699 * the virtual pins in the initialization statically
1700 */
1701 if (is_haswell_plus(codec)) {
1702 /*
1703 * On Intel platforms, device entries number is
1704 * changed dynamically. If there is a DP MST
1705 * hub connected, the device entries number is 3.
1706 * Otherwise, it is 1.
1707 * Here we manually set dev_num to 3, so that
1708 * we can initialize all the device entries when
1709 * bootup statically.
1710 */
1711 dev_num = 3;
1712 spec->dev_num = 3;
1713 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1714 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1715 /*
1716 * spec->dev_num is the maxinum number of device entries
1717 * among all the pins
1718 */
1719 spec->dev_num = (spec->dev_num > dev_num) ?
1720 spec->dev_num : dev_num;
1721 } else {
1722 /*
1723 * If the platform doesn't support DP MST,
1724 * manually set dev_num to 1. This means
1725 * the pin has only one device entry.
1726 */
1727 dev_num = 1;
1728 spec->dev_num = 1;
2bea241a 1729 }
079d88cc 1730
9152085d
LY		 1731 for (i = 0; i < dev_num; i++) {
1732 pin_idx = spec->num_pins;
1733 per_pin = snd_array_new(&spec->pins);
079d88cc 1734
9152085d
LY		 1735 if (!per_pin)
1736 return -ENOMEM;
1737
1738 if (spec->dyn_pcm_assign) {
1739 per_pin->pcm = NULL;
1740 per_pin->pcm_idx = -1;
1741 } else {
1742 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1743 per_pin->pcm_idx = pin_idx;
1744 }
1745 per_pin->pin_nid = pin_nid;
1746 per_pin->pin_nid_idx = spec->num_nids;
1747 per_pin->dev_id = i;
1748 per_pin->non_pcm = false;
1749 snd_hda_set_dev_select(codec, pin_nid, i);
1750 if (is_haswell_plus(codec))
1751 intel_haswell_fixup_connect_list(codec, pin_nid);
1752 err = hdmi_read_pin_conn(codec, pin_idx);
1753 if (err < 0)
1754 return err;
1755 spec->num_pins++;
1756 }
1757 spec->num_nids++;
079d88cc 1758
384a48d7 1759 return 0;
079d88cc
WF		 1760}
1761
384a48d7 1762static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1763{
1764 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1765 struct hdmi_spec_per_cvt *per_cvt;
1766 unsigned int chans;
1767 int err;
079d88cc 1768
384a48d7
SW		 1769 chans = get_wcaps(codec, cvt_nid);
1770 chans = get_wcaps_channels(chans);
1771
bce0d2a8
TI		 1772 per_cvt = snd_array_new(&spec->cvts);
1773 if (!per_cvt)
1774 return -ENOMEM;
384a48d7
SW		 1775
1776 per_cvt->cvt_nid = cvt_nid;
1777 per_cvt->channels_min = 2;
d45e6889 1778 if (chans <= 16) {
384a48d7 1779 per_cvt->channels_max = chans;
67b90cb8
SP		 1780 if (chans > spec->chmap.channels_max)
1781 spec->chmap.channels_max = chans;
d45e6889 1782 }
384a48d7
SW		 1783
1784 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1785 &per_cvt->rates,
1786 &per_cvt->formats,
1787 &per_cvt->maxbps);
1788 if (err < 0)
1789 return err;
1790
bce0d2a8
TI		 1791 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1792 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1793 spec->num_cvts++;
079d88cc
WF		 1794
1795 return 0;
1796}
1797
1798static int hdmi_parse_codec(struct hda_codec *codec)
1799{
1800 hda_nid_t nid;
1801 int i, nodes;
1802
7639a06c 1803 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
079d88cc 1804 if (!nid || nodes < 0) {
4e76a883 1805 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
079d88cc
WF		 1806 return -EINVAL;
1807 }
1808
1809 for (i = 0; i < nodes; i++, nid++) {
1810 unsigned int caps;
1811 unsigned int type;
1812
efc2f8de 1813 caps = get_wcaps(codec, nid);
079d88cc
WF		 1814 type = get_wcaps_type(caps);
1815
1816 if (!(caps & AC_WCAP_DIGITAL))
1817 continue;
1818
1819 switch (type) {
1820 case AC_WID_AUD_OUT:
384a48d7 1821 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1822 break;
1823 case AC_WID_PIN:
3eaead57 1824 hdmi_add_pin(codec, nid);
079d88cc
WF		 1825 break;
1826 }
1827 }
1828
079d88cc
WF		 1829 return 0;
1830}
1831
84eb01be
TI		 1832/*
1833 */
1a6003b5
TI		 1834static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1835{
1836 struct hda_spdif_out *spdif;
1837 bool non_pcm;
1838
1839 mutex_lock(&codec->spdif_mutex);
1840 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
960a581e
LY		 1841 /* Add sanity check to pass klockwork check.
1842 * This should never happen.
1843 */
1844 if (WARN_ON(spdif == NULL))
1845 return true;
1a6003b5
TI		 1846 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1847 mutex_unlock(&codec->spdif_mutex);
1848 return non_pcm;
1849}
1850
84eb01be
TI		 1851/*
1852 * HDMI callbacks
1853 */
1854
1855static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1856 struct hda_codec *codec,
1857 unsigned int stream_tag,
1858 unsigned int format,
1859 struct snd_pcm_substream *substream)
1860{
384a48d7
SW		 1861 hda_nid_t cvt_nid = hinfo->nid;
1862 struct hdmi_spec *spec = codec->spec;
42b29870
LY		 1863 int pin_idx;
1864 struct hdmi_spec_per_pin *per_pin;
1865 hda_nid_t pin_nid;
ddd621fb 1866 struct snd_pcm_runtime *runtime = substream->runtime;
1a6003b5 1867 bool non_pcm;
75fae117 1868 int pinctl;
f69548ff 1869 int err = 0;
1a6003b5 1870
42b29870
LY		 1871 mutex_lock(&spec->pcm_lock);
1872 pin_idx = hinfo_to_pin_index(codec, hinfo);
1873 if (spec->dyn_pcm_assign && pin_idx < 0) {
1874 /* when dyn_pcm_assign and pcm is not bound to a pin
1875 * skip pin setup and return 0 to make audio playback
1876 * be ongoing
1877 */
4846a67e 1878 pin_cvt_fixup(codec, NULL, cvt_nid);
42b29870
LY		 1879 snd_hda_codec_setup_stream(codec, cvt_nid,
1880 stream_tag, 0, format);
f69548ff 1881 goto unlock;
42b29870 1882 }
1a6003b5 1883
42b29870 1884 if (snd_BUG_ON(pin_idx < 0)) {
f69548ff
TI		 1885 err = -EINVAL;
1886 goto unlock;
42b29870
LY		 1887 }
1888 per_pin = get_pin(spec, pin_idx);
1889 pin_nid = per_pin->pin_nid;
4846a67e
TI		 1890
1891 /* Verify pin:cvt selections to avoid silent audio after S3.
1892 * After S3, the audio driver restores pin:cvt selections
1893 * but this can happen before gfx is ready and such selection
1894 * is overlooked by HW. Thus multiple pins can share a same
1895 * default convertor and mute control will affect each other,
1896 * which can cause a resumed audio playback become silent
1897 * after S3.
1898 */
1899 pin_cvt_fixup(codec, per_pin, 0);
2df6742f 1900
ddd621fb
LY		 1901 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1902 /* Todo: add DP1.2 MST audio support later */
93a9ff15 1903 if (codec_has_acomp(codec))
9152085d 1904 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
f9318941 1905 runtime->rate);
ddd621fb 1906
1a6003b5 1907 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1908 mutex_lock(&per_pin->lock);
b054087d
TI		 1909 per_pin->channels = substream->runtime->channels;
1910 per_pin->setup = true;
384a48d7 1911
b054087d 1912 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1913 mutex_unlock(&per_pin->lock);
75fae117
SW		 1914 if (spec->dyn_pin_out) {
1915 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1916 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1917 snd_hda_codec_write(codec, pin_nid, 0,
1918 AC_VERB_SET_PIN_WIDGET_CONTROL,
1919 pinctl | PIN_OUT);
1920 }
1921
9152085d 1922 /* snd_hda_set_dev_select() has been called before */
42b29870
LY		 1923 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1924 stream_tag, format);
f69548ff 1925 unlock:
42b29870
LY		 1926 mutex_unlock(&spec->pcm_lock);
1927 return err;
84eb01be
TI		 1928}
1929
8dfaa573
TI		 1930static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1931 struct hda_codec *codec,
1932 struct snd_pcm_substream *substream)
1933{
1934 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1935 return 0;
1936}
1937
f2ad24fa
TI		 1938static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1939 struct hda_codec *codec,
1940 struct snd_pcm_substream *substream)
384a48d7
SW		 1941{
1942 struct hdmi_spec *spec = codec->spec;
2bf3c85a 1943 int cvt_idx, pin_idx, pcm_idx;
384a48d7
SW		 1944 struct hdmi_spec_per_cvt *per_cvt;
1945 struct hdmi_spec_per_pin *per_pin;
75fae117 1946 int pinctl;
f69548ff 1947 int err = 0;
384a48d7 1948
384a48d7 1949 if (hinfo->nid) {
2bf3c85a
LY		 1950 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1951 if (snd_BUG_ON(pcm_idx < 0))
1952 return -EINVAL;
4e76a883 1953 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
384a48d7
SW		 1954 if (snd_BUG_ON(cvt_idx < 0))
1955 return -EINVAL;
bce0d2a8 1956 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1957
1958 snd_BUG_ON(!per_cvt->assigned);
1959 per_cvt->assigned = 0;
1960 hinfo->nid = 0;
1961
42b29870 1962 mutex_lock(&spec->pcm_lock);
b09887f8 1963 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
ac98379a 1964 clear_bit(pcm_idx, &spec->pcm_in_use);
4e76a883 1965 pin_idx = hinfo_to_pin_index(codec, hinfo);
f69548ff
TI		 1966 if (spec->dyn_pcm_assign && pin_idx < 0)
1967 goto unlock;
42b29870
LY		 1968
1969 if (snd_BUG_ON(pin_idx < 0)) {
f69548ff
TI		 1970 err = -EINVAL;
1971 goto unlock;
42b29870 1972 }
bce0d2a8 1973 per_pin = get_pin(spec, pin_idx);
384a48d7 1974
75fae117
SW		 1975 if (spec->dyn_pin_out) {
1976 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1977 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1978 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1979 AC_VERB_SET_PIN_WIDGET_CONTROL,
1980 pinctl & ~PIN_OUT);
1981 }
1982
a4e9a38b 1983 mutex_lock(&per_pin->lock);
d45e6889
TI		 1984 per_pin->chmap_set = false;
1985 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1986
1987 per_pin->setup = false;
1988 per_pin->channels = 0;
a4e9a38b 1989 mutex_unlock(&per_pin->lock);
f69548ff 1990 unlock:
42b29870 1991 mutex_unlock(&spec->pcm_lock);
384a48d7 1992 }
d45e6889 1993
f69548ff 1994 return err;
384a48d7
SW		 1995}
1996
1997static const struct hda_pcm_ops generic_ops = {
1998 .open = hdmi_pcm_open,
f2ad24fa 1999 .close = hdmi_pcm_close,
384a48d7 2000 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 2001 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 2002};
2003
44fde3b8
SP		 2004static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2005{
2006 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2007 struct hdmi_spec *spec = codec->spec;
2008 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2009
2010 if (!per_pin)
2011 return 0;
2012
2013 return per_pin->sink_eld.info.spk_alloc;
2014}
2015
9b3dc8aa
SP		 2016static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2017 unsigned char *chmap)
2018{
2019 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2020 struct hdmi_spec *spec = codec->spec;
2021 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2022
2023 /* chmap is already set to 0 in caller */
2024 if (!per_pin)
2025 return;
2026
2027 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2028}
2029
2030static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2031 unsigned char *chmap, int prepared)
2032{
2033 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2034 struct hdmi_spec *spec = codec->spec;
2035 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2036
ed0739b5
LY		 2037 if (!per_pin)
2038 return;
9b3dc8aa
SP		 2039 mutex_lock(&per_pin->lock);
2040 per_pin->chmap_set = true;
2041 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2042 if (prepared)
2043 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2044 mutex_unlock(&per_pin->lock);
2045}
2046
2047static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2048{
2049 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2050 struct hdmi_spec *spec = codec->spec;
2051 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2052
2053 return per_pin ? true:false;
2054}
2055
84eb01be
TI		 2056static int generic_hdmi_build_pcms(struct hda_codec *codec)
2057{
2058 struct hdmi_spec *spec = codec->spec;
9152085d 2059 int idx;
84eb01be 2060
9152085d
LY		 2061 /*
2062 * for non-mst mode, pcm number is the same as before
2063 * for DP MST mode, pcm number is (nid number + dev_num - 1)
2064 * dev_num is the device entry number in a pin
2065 *
2066 */
2067 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
384a48d7 2068 struct hda_pcm *info;
84eb01be 2069 struct hda_pcm_stream *pstr;
bce0d2a8 2070
9152085d 2071 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
bce0d2a8
TI		 2072 if (!info)
2073 return -ENOMEM;
2bea241a 2074
9152085d 2075 spec->pcm_rec[idx].pcm = info;
2bf3c85a 2076 spec->pcm_used++;
84eb01be 2077 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 2078 info->own_chmap = true;
384a48d7 2079
84eb01be 2080 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 2081 pstr->substreams = 1;
2082 pstr->ops = generic_ops;
9152085d
LY		 2083 /* pcm number is less than 16 */
2084 if (spec->pcm_used >= 16)
2085 break;
384a48d7 2086 /* other pstr fields are set in open */
84eb01be
TI		 2087 }
2088
2089 return 0;
2090}
2091
25e4abb3 2092static void free_hdmi_jack_priv(struct snd_jack *jack)
788d441a 2093{
25e4abb3 2094 struct hdmi_pcm *pcm = jack->private_data;
788d441a 2095
25e4abb3 2096 pcm->jack = NULL;
788d441a
TI		 2097}
2098
25e4abb3
LY		 2099static int add_hdmi_jack_kctl(struct hda_codec *codec,
2100 struct hdmi_spec *spec,
2101 int pcm_idx,
788d441a
TI		 2102 const char *name)
2103{
2104 struct snd_jack *jack;
2105 int err;
2106
2107 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2108 true, false);
2109 if (err < 0)
2110 return err;
25e4abb3
LY		 2111
2112 spec->pcm_rec[pcm_idx].jack = jack;
2113 jack->private_data = &spec->pcm_rec[pcm_idx];
2114 jack->private_free = free_hdmi_jack_priv;
788d441a
TI		 2115 return 0;
2116}
2117
25e4abb3 2118static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
0b6c49b5 2119{
31ef2257 2120 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 2121 struct hdmi_spec *spec = codec->spec;
25e4abb3
LY		 2122 struct hdmi_spec_per_pin *per_pin;
2123 struct hda_jack_tbl *jack;
2124 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
909cadc6 2125 bool phantom_jack;
25e4abb3 2126 int ret;
0b6c49b5 2127
31ef2257
TI		 2128 if (pcmdev > 0)
2129 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
25e4abb3
LY		 2130
2131 if (spec->dyn_pcm_assign)
2132 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2133
2134 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2135 /* if !dyn_pcm_assign, it must be non-MST mode.
2136 * This means pcms and pins are statically mapped.
2137 * And pcm_idx is pin_idx.
2138 */
2139 per_pin = get_pin(spec, pcm_idx);
909cadc6
TI		 2140 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2141 if (phantom_jack)
30efd8de
DH		 2142 strncat(hdmi_str, " Phantom",
2143 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
25e4abb3 2144 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
911761c2 2145 phantom_jack, 0, NULL);
25e4abb3
LY		 2146 if (ret < 0)
2147 return ret;
2148 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2149 if (jack == NULL)
2150 return 0;
2151 /* assign jack->jack to pcm_rec[].jack to
2152 * align with dyn_pcm_assign mode
2153 */
2154 spec->pcm_rec[pcm_idx].jack = jack->jack;
2155 return 0;
0b6c49b5
DH		 2156}
2157
84eb01be
TI		 2158static int generic_hdmi_build_controls(struct hda_codec *codec)
2159{
2160 struct hdmi_spec *spec = codec->spec;
1f7f51a6 2161 int dev, err;
25e4abb3 2162 int pin_idx, pcm_idx;
84eb01be 2163
25e4abb3 2164 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
8a7d6003
TI		 2165 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2166 /* no PCM: mark this for skipping permanently */
2167 set_bit(pcm_idx, &spec->pcm_bitmap);
2168 continue;
2169 }
2170
25e4abb3 2171 err = generic_hdmi_build_jack(codec, pcm_idx);
0b6c49b5
DH		 2172 if (err < 0)
2173 return err;
2174
b09887f8
LY		 2175 /* create the spdif for each pcm
2176 * pin will be bound when monitor is connected
2177 */
2178 if (spec->dyn_pcm_assign)
2179 err = snd_hda_create_dig_out_ctls(codec,
2180 0, spec->cvt_nids[0],
2181 HDA_PCM_TYPE_HDMI);
2182 else {
2183 struct hdmi_spec_per_pin *per_pin =
2184 get_pin(spec, pcm_idx);
2185 err = snd_hda_create_dig_out_ctls(codec,
dcda5806
TI		 2186 per_pin->pin_nid,
2187 per_pin->mux_nids[0],
2188 HDA_PCM_TYPE_HDMI);
b09887f8 2189 }
84eb01be
TI		 2190 if (err < 0)
2191 return err;
b09887f8 2192 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
14bc52b8 2193
1f7f51a6
WY		 2194 dev = get_pcm_rec(spec, pcm_idx)->device;
2195 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2196 /* add control for ELD Bytes */
2197 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2198 if (err < 0)
2199 return err;
2200 }
fb087eaa
LY		 2201 }
2202
2203 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2204 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
31ef2257 2205
82b1d73f 2206 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2207 }
2208
d45e6889 2209 /* add channel maps */
022f344b 2210 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
bbbc7e85 2211 struct hda_pcm *pcm;
2ca320e2 2212
022f344b 2213 pcm = get_pcm_rec(spec, pcm_idx);
bbbc7e85 2214 if (!pcm || !pcm->pcm)
2ca320e2 2215 break;
2f6e8a85 2216 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
d45e6889
TI		 2217 if (err < 0)
2218 return err;
d45e6889
TI		 2219 }
2220
84eb01be
TI		 2221 return 0;
2222}
2223
8b8d654b 2224static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2225{
2226 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2227 int pin_idx;
2228
2229 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2230 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2231
744626da 2232 per_pin->codec = codec;
a4e9a38b 2233 mutex_init(&per_pin->lock);
744626da 2234 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2235 eld_proc_new(per_pin, pin_idx);
84eb01be 2236 }
8b8d654b
TI		 2237 return 0;
2238}
2239
2240static int generic_hdmi_init(struct hda_codec *codec)
2241{
2242 struct hdmi_spec *spec = codec->spec;
2243 int pin_idx;
2244
2245 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2246 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b 2247 hda_nid_t pin_nid = per_pin->pin_nid;
9152085d 2248 int dev_id = per_pin->dev_id;
8b8d654b 2249
9152085d 2250 snd_hda_set_dev_select(codec, pin_nid, dev_id);
8b8d654b 2251 hdmi_init_pin(codec, pin_nid);
788d441a
TI		 2252 if (!codec_has_acomp(codec))
2253 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2254 codec->jackpoll_interval > 0 ?
2255 jack_callback : NULL);
8b8d654b 2256 }
84eb01be
TI		 2257 return 0;
2258}
2259
bce0d2a8
TI		 2260static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2261{
2262 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2263 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
bce0d2a8
TI		 2264}
2265
2266static void hdmi_array_free(struct hdmi_spec *spec)
2267{
2268 snd_array_free(&spec->pins);
2269 snd_array_free(&spec->cvts);
bce0d2a8
TI		 2270}
2271
a686632f
TI		 2272static void generic_spec_free(struct hda_codec *codec)
2273{
2274 struct hdmi_spec *spec = codec->spec;
2275
2276 if (spec) {
2277 hdmi_array_free(spec);
2278 kfree(spec);
2279 codec->spec = NULL;
2280 }
2281 codec->dp_mst = false;
2282}
2283
84eb01be
TI		 2284static void generic_hdmi_free(struct hda_codec *codec)
2285{
2286 struct hdmi_spec *spec = codec->spec;
25e4abb3 2287 int pin_idx, pcm_idx;
384a48d7 2288
6603249d 2289 if (codec_has_acomp(codec))
a57942bf 2290 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
25adc137 2291
384a48d7 2292 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2293 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2f35c630 2294 cancel_delayed_work_sync(&per_pin->work);
a4e9a38b 2295 eld_proc_free(per_pin);
25e4abb3
LY		 2296 }
2297
2298 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2299 if (spec->pcm_rec[pcm_idx].jack == NULL)
2300 continue;
2301 if (spec->dyn_pcm_assign)
2302 snd_device_free(codec->card,
2303 spec->pcm_rec[pcm_idx].jack);
2304 else
2305 spec->pcm_rec[pcm_idx].jack = NULL;
384a48d7 2306 }
84eb01be 2307
a686632f 2308 generic_spec_free(codec);
84eb01be
TI		 2309}
2310
28cb72e5
WX		 2311#ifdef CONFIG_PM
2312static int generic_hdmi_resume(struct hda_codec *codec)
2313{
2314 struct hdmi_spec *spec = codec->spec;
2315 int pin_idx;
2316
a2833683 2317 codec->patch_ops.init(codec);
eeecd9d1 2318 regcache_sync(codec->core.regmap);
28cb72e5
WX		 2319
2320 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2321 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2322 hdmi_present_sense(per_pin, 1);
2323 }
2324 return 0;
2325}
2326#endif
2327
fb79e1e0 2328static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2329 .init = generic_hdmi_init,
2330 .free = generic_hdmi_free,
2331 .build_pcms = generic_hdmi_build_pcms,
2332 .build_controls = generic_hdmi_build_controls,
2333 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2334#ifdef CONFIG_PM
2335 .resume = generic_hdmi_resume,
2336#endif
84eb01be
TI		 2337};
2338
307229d2
AH		 2339static const struct hdmi_ops generic_standard_hdmi_ops = {
2340 .pin_get_eld = snd_hdmi_get_eld,
307229d2
AH		 2341 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2342 .pin_hbr_setup = hdmi_pin_hbr_setup,
2343 .setup_stream = hdmi_setup_stream,
67b90cb8
SP		 2344};
2345
a686632f
TI		 2346/* allocate codec->spec and assign/initialize generic parser ops */
2347static int alloc_generic_hdmi(struct hda_codec *codec)
2348{
2349 struct hdmi_spec *spec;
2350
2351 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2352 if (!spec)
2353 return -ENOMEM;
2354
2355 spec->ops = generic_standard_hdmi_ops;
9152085d 2356 spec->dev_num = 1; /* initialize to 1 */
a686632f
TI		 2357 mutex_init(&spec->pcm_lock);
2358 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2359
2360 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2361 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2362 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
44fde3b8 2363 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
a686632f
TI		 2364
2365 codec->spec = spec;
2366 hdmi_array_init(spec, 4);
2367
2368 codec->patch_ops = generic_hdmi_patch_ops;
2369
2370 return 0;
2371}
2372
2373/* generic HDMI parser */
2374static int patch_generic_hdmi(struct hda_codec *codec)
2375{
2376 int err;
2377
2378 err = alloc_generic_hdmi(codec);
2379 if (err < 0)
2380 return err;
2381
2382 err = hdmi_parse_codec(codec);
2383 if (err < 0) {
2384 generic_spec_free(codec);
2385 return err;
2386 }
2387
2388 generic_hdmi_init_per_pins(codec);
2389 return 0;
2390}
2391
2392/*
2393 * Intel codec parsers and helpers
2394 */
2395
c88d4e84
TI		 2396static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2397 hda_nid_t nid)
2398{
2399 struct hdmi_spec *spec = codec->spec;
2400 hda_nid_t conns[4];
2401 int nconns;
6ffe168f 2402
c88d4e84
TI		 2403 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2404 if (nconns == spec->num_cvts &&
2405 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2406 return;
2407
c88d4e84 2408 /* override pins connection list */
4e76a883 2409 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
c88d4e84 2410 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2411}
2412
1611a9c9 2413#define INTEL_VENDOR_NID 0x08
a87a4d23 2414#define INTEL_GLK_VENDOR_NID 0x0B
1611a9c9
ML		 2415#define INTEL_GET_VENDOR_VERB 0xf81
2416#define INTEL_SET_VENDOR_VERB 0x781
2417#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2418#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2419
2420static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2421 bool update_tree)
1611a9c9
ML		 2422{
2423 unsigned int vendor_param;
a87a4d23 2424 struct hdmi_spec *spec = codec->spec;
1611a9c9 2425
a87a4d23 2426 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
1611a9c9
ML		 2427 INTEL_GET_VENDOR_VERB, 0);
2428 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2429 return;
2430
2431 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
a87a4d23 2432 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
1611a9c9
ML		 2433 INTEL_SET_VENDOR_VERB, vendor_param);
2434 if (vendor_param == -1)
2435 return;
2436
17df3f55
TI		 2437 if (update_tree)
2438 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2439}
2440
c88d4e84
TI		 2441static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2442{
2443 unsigned int vendor_param;
a87a4d23 2444 struct hdmi_spec *spec = codec->spec;
c88d4e84 2445
a87a4d23 2446 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
c88d4e84
TI		 2447 INTEL_GET_VENDOR_VERB, 0);
2448 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2449 return;
2450
2451 /* enable DP1.2 mode */
2452 vendor_param |= INTEL_EN_DP12;
a551d914 2453 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
a87a4d23 2454 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
c88d4e84
TI		 2455 INTEL_SET_VENDOR_VERB, vendor_param);
2456}
2457
17df3f55
TI		 2458/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2459 * Otherwise you may get severe h/w communication errors.
2460 */
2461static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2462 unsigned int power_state)
2463{
2464 if (power_state == AC_PWRST_D0) {
2465 intel_haswell_enable_all_pins(codec, false);
2466 intel_haswell_fixup_enable_dp12(codec);
2467 }
c88d4e84 2468
17df3f55
TI		 2469 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2470 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2471}
6ffe168f 2472
a57942bf
TI		 2473/* There is a fixed mapping between audio pin node and display port.
2474 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2475 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2476 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2477 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2478 *
2479 * on VLV, ILK:
2480 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2481 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2482 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2483 */
2484static int intel_base_nid(struct hda_codec *codec)
2485{
2486 switch (codec->core.vendor_id) {
2487 case 0x80860054: /* ILK */
2488 case 0x80862804: /* ILK */
2489 case 0x80862882: /* VLV */
2490 return 4;
2491 default:
2492 return 5;
2493 }
2494}
2495
2496static int intel_pin2port(void *audio_ptr, int pin_nid)
2497{
2498 int base_nid = intel_base_nid(audio_ptr);
2499
2500 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2501 return -1;
2502 return pin_nid - base_nid + 1; /* intel port is 1-based */
2503}
2504
f9318941 2505static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
25adc137
DH		 2506{
2507 struct hda_codec *codec = audio_ptr;
7ff652ff 2508 int pin_nid;
9152085d 2509 int dev_id = pipe;
25adc137 2510
4f8e4f35
TI		 2511 /* we assume only from port-B to port-D */
2512 if (port < 1 || port > 3)
2513 return;
2514
a57942bf 2515 pin_nid = port + intel_base_nid(codec) - 1; /* intel port is 1-based */
7ff652ff 2516
8ae743e8
TI		 2517 /* skip notification during system suspend (but not in runtime PM);
2518 * the state will be updated at resume
2519 */
2520 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2521 return;
eb399d3c 2522 /* ditto during suspend/resume process itself */
feb20fae 2523 if (snd_hdac_is_in_pm(&codec->core))
eb399d3c 2524 return;
8ae743e8 2525
bb03ed21 2526 snd_hdac_i915_set_bclk(&codec->bus->core);
9152085d 2527 check_presence_and_report(codec, pin_nid, dev_id);
25adc137
DH		 2528}
2529
a686632f
TI		 2530/* register i915 component pin_eld_notify callback */
2531static void register_i915_notifier(struct hda_codec *codec)
84eb01be 2532{
a686632f 2533 struct hdmi_spec *spec = codec->spec;
84eb01be 2534
a686632f 2535 spec->use_acomp_notifier = true;
ae891abe 2536 spec->drm_audio_ops.audio_ptr = codec;
a686632f
TI		 2537 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2538 * will call pin_eld_notify with using audio_ptr pointer
2539 * We need make sure audio_ptr is really setup
2540 */
2541 wmb();
a57942bf 2542 spec->drm_audio_ops.pin2port = intel_pin2port;
ae891abe 2543 spec->drm_audio_ops.pin_eld_notify = intel_pin_eld_notify;
a57942bf 2544 snd_hdac_acomp_register_notifier(&codec->bus->core,
82887c0b 2545 &spec->drm_audio_ops);
a686632f 2546}
84eb01be 2547
2c1c9b86
TI		 2548/* setup_stream ops override for HSW+ */
2549static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2550 hda_nid_t pin_nid, u32 stream_tag, int format)
2551{
2552 haswell_verify_D0(codec, cvt_nid, pin_nid);
2553 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2554}
739ffee9 2555
4846a67e
TI		 2556/* pin_cvt_fixup ops override for HSW+ and VLV+ */
2557static void i915_pin_cvt_fixup(struct hda_codec *codec,
2558 struct hdmi_spec_per_pin *per_pin,
2559 hda_nid_t cvt_nid)
2560{
2561 if (per_pin) {
9152085d
LY		 2562 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2563 per_pin->dev_id);
4846a67e
TI		 2564 intel_verify_pin_cvt_connect(codec, per_pin);
2565 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
9152085d 2566 per_pin->dev_id, per_pin->mux_idx);
4846a67e 2567 } else {
9152085d 2568 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
4846a67e
TI		 2569 }
2570}
739ffee9 2571
43f6c8d9
TI		 2572/* precondition and allocation for Intel codecs */
2573static int alloc_intel_hdmi(struct hda_codec *codec)
a686632f 2574{
43f6c8d9 2575 /* requires i915 binding */
a686632f
TI		 2576 if (!codec->bus->core.audio_component) {
2577 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
fdd49c51
TI		 2578 /* set probe_id here to prevent generic fallback binding */
2579 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
a686632f 2580 return -ENODEV;
691be973 2581 }
55913110 2582
43f6c8d9
TI		 2583 return alloc_generic_hdmi(codec);
2584}
2585
2586/* parse and post-process for Intel codecs */
2587static int parse_intel_hdmi(struct hda_codec *codec)
2588{
2589 int err;
2590
2591 err = hdmi_parse_codec(codec);
2592 if (err < 0) {
2593 generic_spec_free(codec);
2594 return err;
2595 }
2596
2597 generic_hdmi_init_per_pins(codec);
2598 register_i915_notifier(codec);
2599 return 0;
2600}
2601
2602/* Intel Haswell and onwards; audio component with eld notifier */
2603static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid)
2604{
2605 struct hdmi_spec *spec;
2606 int err;
2607
2608 err = alloc_intel_hdmi(codec);
a686632f
TI		 2609 if (err < 0)
2610 return err;
2611 spec = codec->spec;
9152085d
LY		 2612 codec->dp_mst = true;
2613 spec->dyn_pcm_assign = true;
a87a4d23 2614 spec->vendor_nid = vendor_nid;
6ffe168f 2615
a686632f
TI		 2616 intel_haswell_enable_all_pins(codec, true);
2617 intel_haswell_fixup_enable_dp12(codec);
2618
2619 /* For Haswell/Broadwell, the controller is also in the power well and
2bd1f73f 2620 * can cover the codec power request, and so need not set this flag.
2bd1f73f 2621 */
a686632f 2622 if (!is_haswell(codec) && !is_broadwell(codec))
2bd1f73f
ML		 2623 codec->core.link_power_control = 1;
2624
a686632f 2625 codec->patch_ops.set_power_state = haswell_set_power_state;
a686632f
TI		 2626 codec->depop_delay = 0;
2627 codec->auto_runtime_pm = 1;
2628
2c1c9b86 2629 spec->ops.setup_stream = i915_hsw_setup_stream;
4846a67e 2630 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2c1c9b86 2631
43f6c8d9 2632 return parse_intel_hdmi(codec);
a686632f
TI		 2633}
2634
a87a4d23
ACDO		 2635static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2636{
2637 return intel_hsw_common_init(codec, INTEL_VENDOR_NID);
2638}
2639
2640static int patch_i915_glk_hdmi(struct hda_codec *codec)
2641{
2642 return intel_hsw_common_init(codec, INTEL_GLK_VENDOR_NID);
2643}
2644
7ff652ff 2645/* Intel Baytrail and Braswell; with eld notifier */
a686632f
TI		 2646static int patch_i915_byt_hdmi(struct hda_codec *codec)
2647{
2648 struct hdmi_spec *spec;
2649 int err;
2650
43f6c8d9 2651 err = alloc_intel_hdmi(codec);
a686632f
TI		 2652 if (err < 0)
2653 return err;
2654 spec = codec->spec;
2377c3c3 2655
a686632f
TI		 2656 /* For Valleyview/Cherryview, only the display codec is in the display
2657 * power well and can use link_power ops to request/release the power.
2658 */
2659 codec->core.link_power_control = 1;
84eb01be 2660
a686632f
TI		 2661 codec->depop_delay = 0;
2662 codec->auto_runtime_pm = 1;
84eb01be 2663
4846a67e
TI		 2664 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2665
43f6c8d9 2666 return parse_intel_hdmi(codec);
84eb01be
TI		 2667}
2668
7ff652ff 2669/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
e85015a3
TI		 2670static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2671{
e85015a3
TI		 2672 int err;
2673
43f6c8d9 2674 err = alloc_intel_hdmi(codec);
e85015a3
TI		 2675 if (err < 0)
2676 return err;
43f6c8d9 2677 return parse_intel_hdmi(codec);
84eb01be
TI		 2678}
2679
3aaf8980
SW		 2680/*
2681 * Shared non-generic implementations
2682 */
2683
2684static int simple_playback_build_pcms(struct hda_codec *codec)
2685{
2686 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2687 struct hda_pcm *info;
8ceb332d
TI		 2688 unsigned int chans;
2689 struct hda_pcm_stream *pstr;
bce0d2a8 2690 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2691
bce0d2a8
TI		 2692 per_cvt = get_cvt(spec, 0);
2693 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2694 chans = get_wcaps_channels(chans);
3aaf8980 2695
bbbc7e85 2696 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
bce0d2a8
TI		 2697 if (!info)
2698 return -ENOMEM;
2bea241a 2699 spec->pcm_rec[0].pcm = info;
8ceb332d
TI		 2700 info->pcm_type = HDA_PCM_TYPE_HDMI;
2701 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2702 *pstr = spec->pcm_playback;
bce0d2a8 2703 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2704 if (pstr->channels_max <= 2 && chans && chans <= 16)
2705 pstr->channels_max = chans;
3aaf8980
SW		 2706
2707 return 0;
2708}
2709
4b6ace9e
TI		 2710/* unsolicited event for jack sensing */
2711static void simple_hdmi_unsol_event(struct hda_codec *codec,
2712 unsigned int res)
2713{
9dd8cf12 2714 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2715 snd_hda_jack_report_sync(codec);
2716}
2717
2718/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2719 * as long as spec->pins[] is set correctly
2720 */
2721#define simple_hdmi_build_jack generic_hdmi_build_jack
2722
3aaf8980
SW		 2723static int simple_playback_build_controls(struct hda_codec *codec)
2724{
2725 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2726 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2727 int err;
3aaf8980 2728
bce0d2a8 2729 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 2730 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2731 per_cvt->cvt_nid,
2732 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 2733 if (err < 0)
2734 return err;
2735 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2736}
2737
4f0110ce
TI		 2738static int simple_playback_init(struct hda_codec *codec)
2739{
2740 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2741 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2742 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2743
2744 snd_hda_codec_write(codec, pin, 0,
2745 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2746 /* some codecs require to unmute the pin */
2747 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2748 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2749 AMP_OUT_UNMUTE);
62f949bf 2750 snd_hda_jack_detect_enable(codec, pin);
4f0110ce
TI		 2751 return 0;
2752}
2753
3aaf8980
SW		 2754static void simple_playback_free(struct hda_codec *codec)
2755{
2756 struct hdmi_spec *spec = codec->spec;
2757
bce0d2a8 2758 hdmi_array_free(spec);
3aaf8980
SW		 2759 kfree(spec);
2760}
2761
84eb01be
TI		 2762/*
2763 * Nvidia specific implementations
2764 */
2765
2766#define Nv_VERB_SET_Channel_Allocation 0xF79
2767#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2768#define Nv_VERB_SET_Audio_Protection_On 0xF98
2769#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2770
2771#define nvhdmi_master_con_nid_7x 0x04
2772#define nvhdmi_master_pin_nid_7x 0x05
2773
fb79e1e0 2774static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2775 /*front, rear, clfe, rear_surr */
2776 0x6, 0x8, 0xa, 0xc,
2777};
2778
ceaa86ba
TI		 2779static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2780 /* set audio protect on */
2781 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2782 /* enable digital output on pin widget */
2783 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2784 {} /* terminator */
2785};
2786
2787static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2788 /* set audio protect on */
2789 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2790 /* enable digital output on pin widget */
2791 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2792 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2793 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2794 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2795 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2796 {} /* terminator */
2797};
2798
2799#ifdef LIMITED_RATE_FMT_SUPPORT
2800/* support only the safe format and rate */
2801#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2802#define SUPPORTED_MAXBPS 16
2803#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2804#else
2805/* support all rates and formats */
2806#define SUPPORTED_RATES \
2807 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2808 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2809 SNDRV_PCM_RATE_192000)
2810#define SUPPORTED_MAXBPS 24
2811#define SUPPORTED_FORMATS \
2812 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2813#endif
2814
ceaa86ba
TI		 2815static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2816{
2817 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2818 return 0;
2819}
2820
2821static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2822{
ceaa86ba 2823 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2824 return 0;
2825}
2826
50c697ad 2827static const unsigned int channels_2_6_8[] = {
393004b2
ND		 2828 2, 6, 8
2829};
2830
50c697ad 2831static const unsigned int channels_2_8[] = {
393004b2
ND		 2832 2, 8
2833};
2834
50c697ad 2835static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
393004b2
ND		 2836 .count = ARRAY_SIZE(channels_2_6_8),
2837 .list = channels_2_6_8,
2838 .mask = 0,
2839};
2840
50c697ad 2841static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
393004b2
ND		 2842 .count = ARRAY_SIZE(channels_2_8),
2843 .list = channels_2_8,
2844 .mask = 0,
2845};
2846
84eb01be
TI		 2847static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2848 struct hda_codec *codec,
2849 struct snd_pcm_substream *substream)
2850{
2851 struct hdmi_spec *spec = codec->spec;
50c697ad 2852 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
393004b2 2853
b9a94a9c 2854 switch (codec->preset->vendor_id) {
393004b2
ND		 2855 case 0x10de0002:
2856 case 0x10de0003:
2857 case 0x10de0005:
2858 case 0x10de0006:
2859 hw_constraints_channels = &hw_constraints_2_8_channels;
2860 break;
2861 case 0x10de0007:
2862 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2863 break;
2864 default:
2865 break;
2866 }
2867
2868 if (hw_constraints_channels != NULL) {
2869 snd_pcm_hw_constraint_list(substream->runtime, 0,
2870 SNDRV_PCM_HW_PARAM_CHANNELS,
2871 hw_constraints_channels);
ad09fc9d
TI		 2872 } else {
2873 snd_pcm_hw_constraint_step(substream->runtime, 0,
2874 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2875 }
2876
84eb01be
TI		 2877 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2878}
2879
2880static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2881 struct hda_codec *codec,
2882 struct snd_pcm_substream *substream)
2883{
2884 struct hdmi_spec *spec = codec->spec;
2885 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2886}
2887
2888static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2889 struct hda_codec *codec,
2890 unsigned int stream_tag,
2891 unsigned int format,
2892 struct snd_pcm_substream *substream)
2893{
2894 struct hdmi_spec *spec = codec->spec;
2895 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2896 stream_tag, format, substream);
2897}
2898
d0b1252d
TI		 2899static const struct hda_pcm_stream simple_pcm_playback = {
2900 .substreams = 1,
2901 .channels_min = 2,
2902 .channels_max = 2,
2903 .ops = {
2904 .open = simple_playback_pcm_open,
2905 .close = simple_playback_pcm_close,
2906 .prepare = simple_playback_pcm_prepare
2907 },
2908};
2909
2910static const struct hda_codec_ops simple_hdmi_patch_ops = {
2911 .build_controls = simple_playback_build_controls,
2912 .build_pcms = simple_playback_build_pcms,
2913 .init = simple_playback_init,
2914 .free = simple_playback_free,
250e41ac 2915 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2916};
2917
2918static int patch_simple_hdmi(struct hda_codec *codec,
2919 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2920{
2921 struct hdmi_spec *spec;
bce0d2a8
TI		 2922 struct hdmi_spec_per_cvt *per_cvt;
2923 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2924
2925 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2926 if (!spec)
2927 return -ENOMEM;
2928
2929 codec->spec = spec;
bce0d2a8 2930 hdmi_array_init(spec, 1);
d0b1252d
TI		 2931
2932 spec->multiout.num_dacs = 0; /* no analog */
2933 spec->multiout.max_channels = 2;
2934 spec->multiout.dig_out_nid = cvt_nid;
2935 spec->num_cvts = 1;
2936 spec->num_pins = 1;
bce0d2a8
TI		 2937 per_pin = snd_array_new(&spec->pins);
2938 per_cvt = snd_array_new(&spec->cvts);
2939 if (!per_pin || !per_cvt) {
2940 simple_playback_free(codec);
2941 return -ENOMEM;
2942 }
2943 per_cvt->cvt_nid = cvt_nid;
2944 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2945 spec->pcm_playback = simple_pcm_playback;
2946
2947 codec->patch_ops = simple_hdmi_patch_ops;
2948
2949 return 0;
2950}
2951
1f348522
AP		 2952static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2953 int channels)
2954{
2955 unsigned int chanmask;
2956 int chan = channels ? (channels - 1) : 1;
2957
2958 switch (channels) {
2959 default:
2960 case 0:
2961 case 2:
2962 chanmask = 0x00;
2963 break;
2964 case 4:
2965 chanmask = 0x08;
2966 break;
2967 case 6:
2968 chanmask = 0x0b;
2969 break;
2970 case 8:
2971 chanmask = 0x13;
2972 break;
2973 }
2974
2975 /* Set the audio infoframe channel allocation and checksum fields. The
2976 * channel count is computed implicitly by the hardware. */
2977 snd_hda_codec_write(codec, 0x1, 0,
2978 Nv_VERB_SET_Channel_Allocation, chanmask);
2979
2980 snd_hda_codec_write(codec, 0x1, 0,
2981 Nv_VERB_SET_Info_Frame_Checksum,
2982 (0x71 - chan - chanmask));
2983}
2984
84eb01be
TI		 2985static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2986 struct hda_codec *codec,
2987 struct snd_pcm_substream *substream)
2988{
2989 struct hdmi_spec *spec = codec->spec;
2990 int i;
2991
2992 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2993 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2994 for (i = 0; i < 4; i++) {
2995 /* set the stream id */
2996 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2997 AC_VERB_SET_CHANNEL_STREAMID, 0);
2998 /* set the stream format */
2999 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3000 AC_VERB_SET_STREAM_FORMAT, 0);
3001 }
3002
1f348522
AP		 3003 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3004 * streams are disabled. */
3005 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3006
84eb01be
TI		 3007 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3008}
3009
3010static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3011 struct hda_codec *codec,
3012 unsigned int stream_tag,
3013 unsigned int format,
3014 struct snd_pcm_substream *substream)
3015{
3016 int chs;
112daa7a 3017 unsigned int dataDCC2, channel_id;
84eb01be 3018 int i;
7c935976 3019 struct hdmi_spec *spec = codec->spec;
e3245cdd 3020 struct hda_spdif_out *spdif;
bce0d2a8 3021 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 3022
3023 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 3024 per_cvt = get_cvt(spec, 0);
3025 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 3026
3027 chs = substream->runtime->channels;
84eb01be 3028
84eb01be
TI		 3029 dataDCC2 = 0x2;
3030
84eb01be 3031 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 3032 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3033 snd_hda_codec_write(codec,
3034 nvhdmi_master_con_nid_7x,
3035 0,
3036 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3037 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3038
3039 /* set the stream id */
3040 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3041 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3042
3043 /* set the stream format */
3044 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3045 AC_VERB_SET_STREAM_FORMAT, format);
3046
3047 /* turn on again (if needed) */
3048 /* enable and set the channel status audio/data flag */
7c935976 3049 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3050 snd_hda_codec_write(codec,
3051 nvhdmi_master_con_nid_7x,
3052 0,
3053 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3054 spdif->ctls & 0xff);
84eb01be
TI		 3055 snd_hda_codec_write(codec,
3056 nvhdmi_master_con_nid_7x,
3057 0,
3058 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3059 }
3060
3061 for (i = 0; i < 4; i++) {
3062 if (chs == 2)
3063 channel_id = 0;
3064 else
3065 channel_id = i * 2;
3066
3067 /* turn off SPDIF once;
3068 *otherwise the IEC958 bits won't be updated
3069 */
3070 if (codec->spdif_status_reset &&
7c935976 3071 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3072 snd_hda_codec_write(codec,
3073 nvhdmi_con_nids_7x[i],
3074 0,
3075 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3076 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3077 /* set the stream id */
3078 snd_hda_codec_write(codec,
3079 nvhdmi_con_nids_7x[i],
3080 0,
3081 AC_VERB_SET_CHANNEL_STREAMID,
3082 (stream_tag << 4) | channel_id);
3083 /* set the stream format */
3084 snd_hda_codec_write(codec,
3085 nvhdmi_con_nids_7x[i],
3086 0,
3087 AC_VERB_SET_STREAM_FORMAT,
3088 format);
3089 /* turn on again (if needed) */
3090 /* enable and set the channel status audio/data flag */
3091 if (codec->spdif_status_reset &&
7c935976 3092 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3093 snd_hda_codec_write(codec,
3094 nvhdmi_con_nids_7x[i],
3095 0,
3096 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3097 spdif->ctls & 0xff);
84eb01be
TI		 3098 snd_hda_codec_write(codec,
3099 nvhdmi_con_nids_7x[i],
3100 0,
3101 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3102 }
3103 }
3104
1f348522 3105 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 3106
3107 mutex_unlock(&codec->spdif_mutex);
3108 return 0;
3109}
3110
fb79e1e0 3111static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 3112 .substreams = 1,
3113 .channels_min = 2,
3114 .channels_max = 8,
3115 .nid = nvhdmi_master_con_nid_7x,
3116 .rates = SUPPORTED_RATES,
3117 .maxbps = SUPPORTED_MAXBPS,
3118 .formats = SUPPORTED_FORMATS,
3119 .ops = {
3120 .open = simple_playback_pcm_open,
3121 .close = nvhdmi_8ch_7x_pcm_close,
3122 .prepare = nvhdmi_8ch_7x_pcm_prepare
3123 },
3124};
3125
84eb01be
TI		 3126static int patch_nvhdmi_2ch(struct hda_codec *codec)
3127{
3128 struct hdmi_spec *spec;
d0b1252d
TI		 3129 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3130 nvhdmi_master_pin_nid_7x);
3131 if (err < 0)
3132 return err;
84eb01be 3133
ceaa86ba 3134 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 3135 /* override the PCM rates, etc, as the codec doesn't give full list */
3136 spec = codec->spec;
3137 spec->pcm_playback.rates = SUPPORTED_RATES;
3138 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3139 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 3140 return 0;
3141}
3142
53775b0d
TI		 3143static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3144{
3145 struct hdmi_spec *spec = codec->spec;
3146 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 3147 if (!err) {
3148 struct hda_pcm *info = get_pcm_rec(spec, 0);
3149 info->own_chmap = true;
3150 }
53775b0d
TI		 3151 return err;
3152}
3153
3154static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3155{
3156 struct hdmi_spec *spec = codec->spec;
bce0d2a8 3157 struct hda_pcm *info;
53775b0d
TI		 3158 struct snd_pcm_chmap *chmap;
3159 int err;
3160
3161 err = simple_playback_build_controls(codec);
3162 if (err < 0)
3163 return err;
3164
3165 /* add channel maps */
bce0d2a8
TI		 3166 info = get_pcm_rec(spec, 0);
3167 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 3168 SNDRV_PCM_STREAM_PLAYBACK,
3169 snd_pcm_alt_chmaps, 8, 0, &chmap);
3170 if (err < 0)
3171 return err;
b9a94a9c 3172 switch (codec->preset->vendor_id) {
53775b0d
TI		 3173 case 0x10de0002:
3174 case 0x10de0003:
3175 case 0x10de0005:
3176 case 0x10de0006:
3177 chmap->channel_mask = (1U << 2) | (1U << 8);
3178 break;
3179 case 0x10de0007:
3180 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3181 }
3182 return 0;
3183}
3184
84eb01be
TI		 3185static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3186{
3187 struct hdmi_spec *spec;
3188 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 3189 if (err < 0)
3190 return err;
3191 spec = codec->spec;
3192 spec->multiout.max_channels = 8;
d0b1252d 3193 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 3194 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 3195 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3196 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 3197
3198 /* Initialize the audio infoframe channel mask and checksum to something
3199 * valid */
3200 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3201
84eb01be
TI		 3202 return 0;
3203}
3204
611885bc
AH		 3205/*
3206 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3207 * - 0x10de0015
3208 * - 0x10de0040
3209 */
67b90cb8 3210static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
f302240d 3211 struct hdac_cea_channel_speaker_allocation *cap, int channels)
611885bc
AH		 3212{
3213 if (cap->ca_index == 0x00 && channels == 2)
3214 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3215
028cb68e
SP		 3216 /* If the speaker allocation matches the channel count, it is OK. */
3217 if (cap->channels != channels)
3218 return -1;
3219
3220 /* all channels are remappable freely */
3221 return SNDRV_CTL_TLVT_CHMAP_VAR;
611885bc
AH		 3222}
3223
828cb4ed
SP		 3224static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3225 int ca, int chs, unsigned char *map)
611885bc
AH		 3226{
3227 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3228 return -EINVAL;
3229
3230 return 0;
3231}
3232
3233static int patch_nvhdmi(struct hda_codec *codec)
3234{
3235 struct hdmi_spec *spec;
3236 int err;
3237
3238 err = patch_generic_hdmi(codec);
3239 if (err)
3240 return err;
3241
3242 spec = codec->spec;
75fae117 3243 spec->dyn_pin_out = true;
611885bc 3244
67b90cb8 3245 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
611885bc 3246 nvhdmi_chmap_cea_alloc_validate_get_type;
67b90cb8 3247 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
611885bc
AH		 3248
3249 return 0;
3250}
3251
26e9a960
TR		 3252/*
3253 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3254 * accessed using vendor-defined verbs. These registers can be used for
3255 * interoperability between the HDA and HDMI drivers.
3256 */
3257
3258/* Audio Function Group node */
3259#define NVIDIA_AFG_NID 0x01
3260
3261/*
3262 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3263 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3264 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3265 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3266 * additional bit (at position 30) to signal the validity of the format.
3267 *
3268 * | 31 | 30 | 29 16 | 15 0 |
3269 * +---------+-------+--------+--------+
3270 * | TRIGGER | VALID | UNUSED | FORMAT |
3271 * +-----------------------------------|
3272 *
3273 * Note that for the trigger bit to take effect it needs to change value
3274 * (i.e. it needs to be toggled).
3275 */
3276#define NVIDIA_GET_SCRATCH0 0xfa6
3277#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3278#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3279#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3280#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3281#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3282#define NVIDIA_SCRATCH_VALID (1 << 6)
3283
3284#define NVIDIA_GET_SCRATCH1 0xfab
3285#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3286#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3287#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3288#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3289
3290/*
3291 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3292 * the format is invalidated so that the HDMI codec can be disabled.
3293 */
3294static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3295{
3296 unsigned int value;
3297
3298 /* bits [31:30] contain the trigger and valid bits */
3299 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3300 NVIDIA_GET_SCRATCH0, 0);
3301 value = (value >> 24) & 0xff;
3302
3303 /* bits [15:0] are used to store the HDA format */
3304 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3305 NVIDIA_SET_SCRATCH0_BYTE0,
3306 (format >> 0) & 0xff);
3307 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3308 NVIDIA_SET_SCRATCH0_BYTE1,
3309 (format >> 8) & 0xff);
3310
3311 /* bits [16:24] are unused */
3312 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3313 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3314
3315 /*
3316 * Bit 30 signals that the data is valid and hence that HDMI audio can
3317 * be enabled.
3318 */
3319 if (format == 0)
3320 value &= ~NVIDIA_SCRATCH_VALID;
3321 else
3322 value |= NVIDIA_SCRATCH_VALID;
3323
3324 /*
3325 * Whenever the trigger bit is toggled, an interrupt is raised in the
3326 * HDMI codec. The HDMI driver will use that as trigger to update its
3327 * configuration.
3328 */
3329 value ^= NVIDIA_SCRATCH_TRIGGER;
3330
3331 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3332 NVIDIA_SET_SCRATCH0_BYTE3, value);
3333}
3334
3335static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3336 struct hda_codec *codec,
3337 unsigned int stream_tag,
3338 unsigned int format,
3339 struct snd_pcm_substream *substream)
3340{
3341 int err;
3342
3343 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3344 format, substream);
3345 if (err < 0)
3346 return err;
3347
3348 /* notify the HDMI codec of the format change */
3349 tegra_hdmi_set_format(codec, format);
3350
3351 return 0;
3352}
3353
3354static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3355 struct hda_codec *codec,
3356 struct snd_pcm_substream *substream)
3357{
3358 /* invalidate the format in the HDMI codec */
3359 tegra_hdmi_set_format(codec, 0);
3360
3361 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3362}
3363
3364static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3365{
3366 struct hdmi_spec *spec = codec->spec;
3367 unsigned int i;
3368
3369 for (i = 0; i < spec->num_pins; i++) {
3370 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3371
3372 if (pcm->pcm_type == type)
3373 return pcm;
3374 }
3375
3376 return NULL;
3377}
3378
3379static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3380{
3381 struct hda_pcm_stream *stream;
3382 struct hda_pcm *pcm;
3383 int err;
3384
3385 err = generic_hdmi_build_pcms(codec);
3386 if (err < 0)
3387 return err;
3388
3389 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3390 if (!pcm)
3391 return -ENODEV;
3392
3393 /*
3394 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3395 * codec about format changes.
3396 */
3397 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3398 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3399 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3400
3401 return 0;
3402}
3403
3404static int patch_tegra_hdmi(struct hda_codec *codec)
3405{
3406 int err;
3407
3408 err = patch_generic_hdmi(codec);
3409 if (err)
3410 return err;
3411
3412 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3413
3414 return 0;
3415}
3416
84eb01be 3417/*
5a613584 3418 * ATI/AMD-specific implementations
84eb01be
TI		 3419 */
3420
5a613584 3421#define is_amdhdmi_rev3_or_later(codec) \
7639a06c
TI		 3422 ((codec)->core.vendor_id == 0x1002aa01 && \
3423 ((codec)->core.revision_id & 0xff00) >= 0x0300)
5a613584
AH		 3424#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3425
3426/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3427#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3428#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3429#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3430#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3431#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3432#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 3433#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 3434#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3435#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3436#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3437#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3438#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3439#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3440#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3441#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3442#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3443#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3444#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 3445#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 3446#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3447#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3448#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3449#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3450#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3451
84d69e79
AH		 3452/* AMD specific HDA cvt verbs */
3453#define ATI_VERB_SET_RAMP_RATE 0x770
3454#define ATI_VERB_GET_RAMP_RATE 0xf70
3455
5a613584
AH		 3456#define ATI_OUT_ENABLE 0x1
3457
3458#define ATI_MULTICHANNEL_MODE_PAIRED 0
3459#define ATI_MULTICHANNEL_MODE_SINGLE 1
3460
461cf6b3
AH		 3461#define ATI_HBR_CAPABLE 0x01
3462#define ATI_HBR_ENABLE 0x10
3463
89250f84
AH		 3464static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3465 unsigned char *buf, int *eld_size)
3466{
3467 /* call hda_eld.c ATI/AMD-specific function */
3468 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3469 is_amdhdmi_rev3_or_later(codec));
3470}
3471
5a613584
AH		 3472static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3473 int active_channels, int conn_type)
3474{
3475 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3476}
3477
3478static int atihdmi_paired_swap_fc_lfe(int pos)
3479{
3480 /*
3481 * ATI/AMD have automatic FC/LFE swap built-in
3482 * when in pairwise mapping mode.
3483 */
3484
3485 switch (pos) {
3486 /* see channel_allocations[].speakers[] */
3487 case 2: return 3;
3488 case 3: return 2;
3489 default: break;
3490 }
3491
3492 return pos;
3493}
3494
828cb4ed
SP		 3495static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3496 int ca, int chs, unsigned char *map)
5a613584 3497{
f302240d 3498 struct hdac_cea_channel_speaker_allocation *cap;
5a613584
AH		 3499 int i, j;
3500
3501 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3502
bb63f726 3503 cap = snd_hdac_get_ch_alloc_from_ca(ca);
5a613584 3504 for (i = 0; i < chs; ++i) {
bb63f726 3505 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
5a613584
AH		 3506 bool ok = false;
3507 bool companion_ok = false;
3508
3509 if (!mask)
3510 continue;
3511
3512 for (j = 0 + i % 2; j < 8; j += 2) {
3513 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3514 if (cap->speakers[chan_idx] == mask) {
3515 /* channel is in a supported position */
3516 ok = true;
3517
3518 if (i % 2 == 0 && i + 1 < chs) {
3519 /* even channel, check the odd companion */
3520 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
bb63f726 3521 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
5a613584
AH		 3522 int comp_mask_act = cap->speakers[comp_chan_idx];
3523
3524 if (comp_mask_req == comp_mask_act)
3525 companion_ok = true;
3526 else
3527 return -EINVAL;
3528 }
3529 break;
3530 }
3531 }
3532
3533 if (!ok)
3534 return -EINVAL;
3535
3536 if (companion_ok)
3537 i++; /* companion channel already checked */
3538 }
3539
3540 return 0;
3541}
3542
739ffee9
SP		 3543static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3544 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
5a613584 3545{
739ffee9 3546 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
5a613584
AH		 3547 int verb;
3548 int ati_channel_setup = 0;
3549
3550 if (hdmi_slot > 7)
3551 return -EINVAL;
3552
3553 if (!has_amd_full_remap_support(codec)) {
3554 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3555
3556 /* In case this is an odd slot but without stream channel, do not
3557 * disable the slot since the corresponding even slot could have a
3558 * channel. In case neither have a channel, the slot pair will be
3559 * disabled when this function is called for the even slot. */
3560 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3561 return 0;
3562
3563 hdmi_slot -= hdmi_slot % 2;
3564
3565 if (stream_channel != 0xf)
3566 stream_channel -= stream_channel % 2;
3567 }
3568
3569 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3570
3571 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3572
3573 if (stream_channel != 0xf)
3574 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3575
3576 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3577}
3578
739ffee9
SP		 3579static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3580 hda_nid_t pin_nid, int asp_slot)
5a613584 3581{
739ffee9 3582 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
5a613584
AH		 3583 bool was_odd = false;
3584 int ati_asp_slot = asp_slot;
3585 int verb;
3586 int ati_channel_setup;
3587
3588 if (asp_slot > 7)
3589 return -EINVAL;
3590
3591 if (!has_amd_full_remap_support(codec)) {
3592 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3593 if (ati_asp_slot % 2 != 0) {
3594 ati_asp_slot -= 1;
3595 was_odd = true;
3596 }
3597 }
3598
3599 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3600
3601 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3602
3603 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3604 return 0xf;
3605
3606 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3607}
84eb01be 3608
67b90cb8
SP		 3609static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3610 struct hdac_chmap *chmap,
f302240d 3611 struct hdac_cea_channel_speaker_allocation *cap,
67b90cb8 3612 int channels)
5a613584
AH		 3613{
3614 int c;
3615
3616 /*
3617 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3618 * we need to take that into account (a single channel may take 2
3619 * channel slots if we need to carry a silent channel next to it).
3620 * On Rev3+ AMD codecs this function is not used.
3621 */
3622 int chanpairs = 0;
3623
3624 /* We only produce even-numbered channel count TLVs */
3625 if ((channels % 2) != 0)
3626 return -1;
3627
3628 for (c = 0; c < 7; c += 2) {
3629 if (cap->speakers[c] || cap->speakers[c+1])
3630 chanpairs++;
3631 }
3632
3633 if (chanpairs * 2 != channels)
3634 return -1;
3635
3636 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3637}
3638
828cb4ed 3639static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
f302240d
SP		 3640 struct hdac_cea_channel_speaker_allocation *cap,
3641 unsigned int *chmap, int channels)
5a613584
AH		 3642{
3643 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3644 int count = 0;
3645 int c;
3646
3647 for (c = 7; c >= 0; c--) {
3648 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3649 int spk = cap->speakers[chan];
3650 if (!spk) {
3651 /* add N/A channel if the companion channel is occupied */
3652 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3653 chmap[count++] = SNDRV_CHMAP_NA;
3654
3655 continue;
3656 }
3657
bb63f726 3658 chmap[count++] = snd_hdac_spk_to_chmap(spk);
5a613584
AH		 3659 }
3660
3661 WARN_ON(count != channels);
3662}
3663
461cf6b3
AH		 3664static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3665 bool hbr)
3666{
3667 int hbr_ctl, hbr_ctl_new;
3668
3669 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3670 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3671 if (hbr)
3672 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3673 else
3674 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3675
4e76a883
TI		 3676 codec_dbg(codec,
3677 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
461cf6b3
AH		 3678 pin_nid,
3679 hbr_ctl == hbr_ctl_new ? "" : "new-",
3680 hbr_ctl_new);
3681
3682 if (hbr_ctl != hbr_ctl_new)
3683 snd_hda_codec_write(codec, pin_nid, 0,
3684 ATI_VERB_SET_HBR_CONTROL,
3685 hbr_ctl_new);
3686
3687 } else if (hbr)
3688 return -EINVAL;
3689
3690 return 0;
3691}
3692
84d69e79
AH		 3693static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3694 hda_nid_t pin_nid, u32 stream_tag, int format)
3695{
3696
3697 if (is_amdhdmi_rev3_or_later(codec)) {
3698 int ramp_rate = 180; /* default as per AMD spec */
3699 /* disable ramp-up/down for non-pcm as per AMD spec */
3700 if (format & AC_FMT_TYPE_NON_PCM)
3701 ramp_rate = 0;
3702
3703 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3704 }
3705
3706 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3707}
3708
3709
5a613584 3710static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3711{
3712 struct hdmi_spec *spec = codec->spec;
5a613584 3713 int pin_idx, err;
84eb01be 3714
5a613584
AH		 3715 err = generic_hdmi_init(codec);
3716
3717 if (err)
84eb01be 3718 return err;
5a613584
AH		 3719
3720 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3721 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3722
3723 /* make sure downmix information in infoframe is zero */
3724 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3725
3726 /* enable channel-wise remap mode if supported */
3727 if (has_amd_full_remap_support(codec))
3728 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3729 ATI_VERB_SET_MULTICHANNEL_MODE,
3730 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3731 }
5a613584 3732
84eb01be
TI		 3733 return 0;
3734}
3735
84eb01be
TI		 3736static int patch_atihdmi(struct hda_codec *codec)
3737{
3738 struct hdmi_spec *spec;
5a613584
AH		 3739 struct hdmi_spec_per_cvt *per_cvt;
3740 int err, cvt_idx;
3741
3742 err = patch_generic_hdmi(codec);
3743
3744 if (err)
d0b1252d 3745 return err;
5a613584
AH		 3746
3747 codec->patch_ops.init = atihdmi_init;
3748
d0b1252d 3749 spec = codec->spec;
5a613584 3750
89250f84 3751 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584 3752 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 3753 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 3754 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584 3755
39669225
TI		 3756 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3757 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3758
5a613584
AH		 3759 if (!has_amd_full_remap_support(codec)) {
3760 /* override to ATI/AMD-specific versions with pairwise mapping */
67b90cb8 3761 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
5a613584 3762 atihdmi_paired_chmap_cea_alloc_validate_get_type;
67b90cb8
SP		 3763 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3764 atihdmi_paired_cea_alloc_to_tlv_chmap;
3765 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
5a613584
AH		 3766 }
3767
3768 /* ATI/AMD converters do not advertise all of their capabilities */
3769 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3770 per_cvt = get_cvt(spec, cvt_idx);
3771 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3772 per_cvt->rates |= SUPPORTED_RATES;
3773 per_cvt->formats |= SUPPORTED_FORMATS;
3774 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3775 }
3776
67b90cb8 3777 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
5a613584 3778
57cb54e5
TI		 3779 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
3780 * the link-down as is. Tell the core to allow it.
3781 */
3782 codec->link_down_at_suspend = 1;
3783
84eb01be
TI		 3784 return 0;
3785}
3786
3de5ff88
AL		 3787/* VIA HDMI Implementation */
3788#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3789#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3790
3de5ff88
AL		 3791static int patch_via_hdmi(struct hda_codec *codec)
3792{
250e41ac 3793 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3794}
84eb01be
TI		 3795
3796/*
3797 * patch entries
3798 */
b9a94a9c
TI		 3799static const struct hda_device_id snd_hda_id_hdmi[] = {
3800HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3801HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3802HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3803HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3804HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3805HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3806HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
74ec1181 3807HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
b9a94a9c
TI		 3808HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3809HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
74ec1181 3810HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
b9a94a9c
TI		 3811HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3812HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3813HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
74ec1181
DD		 3814HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
3815HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
b9a94a9c
TI		 3816HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3817HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3818HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3819HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3820HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3821HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3822HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3823HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3824HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3825HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3826HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
c8900a0f 3827/* 17 is known to be absent */
b9a94a9c
TI		 3828HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3829HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3830HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3831HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3832HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3833HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3834HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3835HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3836HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
917bb90c
TR		 3837HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
3838HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
3839HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
3840HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
b9a94a9c
TI		 3841HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3842HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3843HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3844HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3845HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 3846HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
3847HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
b9a94a9c 3848HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
74ec1181 3849HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
b9a94a9c 3850HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 3851HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
3852HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
b9a94a9c
TI		 3853HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3854HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3855HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3856HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 3857HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
3858HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
3859HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
3860HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
3861HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
b9a94a9c 3862HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
74ec1181 3863HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
af677166 3864HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
74ec1181 3865HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
2d369c74 3866HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3ec622f4 3867HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 3868HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
3869HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
3870HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
3871HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
3872HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
3873HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
3874HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
3875HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
3876HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
3877HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
b9a94a9c 3878HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
74ec1181 3879HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
b9a94a9c
TI		 3880HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3881HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3882HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3883HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
7ff652ff 3884HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
b9a94a9c
TI		 3885HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3886HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3887HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
7ff652ff 3888HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
e85015a3
TI		 3889HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3890HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
a686632f
TI		 3891HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
3892HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
3893HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
3894HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
3895HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
2b4584d0 3896HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
a87a4d23 3897HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
b9091b1c 3898HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
b9a94a9c 3899HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
a686632f
TI		 3900HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3901HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
b9a94a9c 3902HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
d8a766a1 3903/* special ID for generic HDMI */
b9a94a9c 3904HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
84eb01be
TI		 3905{} /* terminator */
3906};
b9a94a9c 3907MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
84eb01be
TI		 3908
3909MODULE_LICENSE("GPL");
3910MODULE_DESCRIPTION("HDMI HD-audio codec");
3911MODULE_ALIAS("snd-hda-codec-intelhdmi");
3912MODULE_ALIAS("snd-hda-codec-nvhdmi");
3913MODULE_ALIAS("snd-hda-codec-atihdmi");
3914
d8a766a1 3915static struct hda_codec_driver hdmi_driver = {
b9a94a9c 3916 .id = snd_hda_id_hdmi,
84eb01be
TI		 3917};
3918
d8a766a1 3919module_hda_codec_driver(hdmi_driver);
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