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Commit | Line | Data |
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079d88cc WF |
1 | /* |
2 | * | |
3 | * patch_hdmi.c - routines for HDMI/DisplayPort codecs | |
4 | * | |
5 | * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. | |
84eb01be TI |
6 | * Copyright (c) 2006 ATI Technologies Inc. |
7 | * Copyright (c) 2008 NVIDIA Corp. All rights reserved. | |
8 | * Copyright (c) 2008 Wei Ni <wni@nvidia.com> | |
5a613584 | 9 | * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> |
079d88cc WF |
10 | * |
11 | * Authors: | |
12 | * Wu Fengguang <wfg@linux.intel.com> | |
13 | * | |
14 | * Maintained by: | |
15 | * Wu Fengguang <wfg@linux.intel.com> | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify it | |
18 | * under the terms of the GNU General Public License as published by the Free | |
19 | * Software Foundation; either version 2 of the License, or (at your option) | |
20 | * any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, but | |
23 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
24 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
25 | * for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software Foundation, | |
29 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
30 | */ | |
31 | ||
84eb01be TI |
32 | #include <linux/init.h> |
33 | #include <linux/delay.h> | |
34 | #include <linux/slab.h> | |
65a77217 | 35 | #include <linux/module.h> |
aaa23f86 | 36 | #include <linux/pm_runtime.h> |
84eb01be | 37 | #include <sound/core.h> |
07acecc1 | 38 | #include <sound/jack.h> |
433968da | 39 | #include <sound/asoundef.h> |
d45e6889 | 40 | #include <sound/tlv.h> |
25adc137 DH |
41 | #include <sound/hdaudio.h> |
42 | #include <sound/hda_i915.h> | |
67b90cb8 | 43 | #include <sound/hda_chmap.h> |
84eb01be TI |
44 | #include "hda_codec.h" |
45 | #include "hda_local.h" | |
1835a0f9 | 46 | #include "hda_jack.h" |
84eb01be | 47 | |
0ebaa24c TI |
48 | static bool static_hdmi_pcm; |
49 | module_param(static_hdmi_pcm, bool, 0644); | |
50 | MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); | |
51 | ||
7639a06c TI |
52 | #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807) |
53 | #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808) | |
54 | #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809) | |
e2656412 | 55 | #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a) |
91815d8a | 56 | #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b) |
b9091b1c SP |
57 | #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \ |
58 | ((codec)->core.vendor_id == 0x80862800)) | |
2b4584d0 | 59 | #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c) |
432ac1a2 | 60 | #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \ |
91815d8a | 61 | || is_skylake(codec) || is_broxton(codec) \ |
2b4584d0 GS |
62 | || is_kabylake(codec)) || is_geminilake(codec) \ |
63 | || is_cannonlake(codec) | |
7639a06c TI |
64 | #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882) |
65 | #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883) | |
ca2e7224 | 66 | #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec)) |
fb87fa3a | 67 | |
384a48d7 SW |
68 | struct hdmi_spec_per_cvt { |
69 | hda_nid_t cvt_nid; | |
70 | int assigned; | |
71 | unsigned int channels_min; | |
72 | unsigned int channels_max; | |
73 | u32 rates; | |
74 | u64 formats; | |
75 | unsigned int maxbps; | |
76 | }; | |
079d88cc | 77 | |
4eea3091 TI |
78 | /* max. connections to a widget */ |
79 | #define HDA_MAX_CONNECTIONS 32 | |
80 | ||
384a48d7 SW |
81 | struct hdmi_spec_per_pin { |
82 | hda_nid_t pin_nid; | |
9152085d | 83 | int dev_id; |
a76056f2 LY |
84 | /* pin idx, different device entries on the same pin use the same idx */ |
85 | int pin_nid_idx; | |
384a48d7 SW |
86 | int num_mux_nids; |
87 | hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; | |
2df6742f | 88 | int mux_idx; |
1df5a06a | 89 | hda_nid_t cvt_nid; |
744626da WF |
90 | |
91 | struct hda_codec *codec; | |
384a48d7 | 92 | struct hdmi_eld sink_eld; |
a4e9a38b | 93 | struct mutex lock; |
744626da | 94 | struct delayed_work work; |
2bea241a | 95 | struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ |
a76056f2 | 96 | int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ |
c6e8453e | 97 | int repoll_count; |
b054087d TI |
98 | bool setup; /* the stream has been set up by prepare callback */ |
99 | int channels; /* current number of channels */ | |
1a6003b5 | 100 | bool non_pcm; |
d45e6889 TI |
101 | bool chmap_set; /* channel-map override by ALSA API? */ |
102 | unsigned char chmap[8]; /* ALSA API channel-map */ | |
cd6a6503 | 103 | #ifdef CONFIG_SND_PROC_FS |
a4e9a38b TI |
104 | struct snd_info_entry *proc_entry; |
105 | #endif | |
384a48d7 | 106 | }; |
079d88cc | 107 | |
307229d2 AH |
108 | /* operations used by generic code that can be overridden by patches */ |
109 | struct hdmi_ops { | |
110 | int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, | |
111 | unsigned char *buf, int *eld_size); | |
112 | ||
307229d2 AH |
113 | void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, |
114 | int ca, int active_channels, int conn_type); | |
115 | ||
116 | /* enable/disable HBR (HD passthrough) */ | |
117 | int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr); | |
118 | ||
119 | int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, | |
120 | hda_nid_t pin_nid, u32 stream_tag, int format); | |
121 | ||
4846a67e TI |
122 | void (*pin_cvt_fixup)(struct hda_codec *codec, |
123 | struct hdmi_spec_per_pin *per_pin, | |
124 | hda_nid_t cvt_nid); | |
307229d2 AH |
125 | }; |
126 | ||
2bea241a LY |
127 | struct hdmi_pcm { |
128 | struct hda_pcm *pcm; | |
129 | struct snd_jack *jack; | |
fb087eaa | 130 | struct snd_kcontrol *eld_ctl; |
2bea241a LY |
131 | }; |
132 | ||
384a48d7 SW |
133 | struct hdmi_spec { |
134 | int num_cvts; | |
bce0d2a8 TI |
135 | struct snd_array cvts; /* struct hdmi_spec_per_cvt */ |
136 | hda_nid_t cvt_nids[4]; /* only for haswell fix */ | |
079d88cc | 137 | |
9152085d LY |
138 | /* |
139 | * num_pins is the number of virtual pins | |
140 | * for example, there are 3 pins, and each pin | |
141 | * has 4 device entries, then the num_pins is 12 | |
142 | */ | |
384a48d7 | 143 | int num_pins; |
9152085d LY |
144 | /* |
145 | * num_nids is the number of real pins | |
146 | * In the above example, num_nids is 3 | |
147 | */ | |
148 | int num_nids; | |
149 | /* | |
150 | * dev_num is the number of device entries | |
151 | * on each pin. | |
152 | * In the above example, dev_num is 4 | |
153 | */ | |
154 | int dev_num; | |
bce0d2a8 | 155 | struct snd_array pins; /* struct hdmi_spec_per_pin */ |
2bea241a | 156 | struct hdmi_pcm pcm_rec[16]; |
42b29870 | 157 | struct mutex pcm_lock; |
a76056f2 LY |
158 | /* pcm_bitmap means which pcms have been assigned to pins*/ |
159 | unsigned long pcm_bitmap; | |
2bf3c85a | 160 | int pcm_used; /* counter of pcm_rec[] */ |
ac98379a LY |
161 | /* bitmap shows whether the pcm is opened in user space |
162 | * bit 0 means the first playback PCM (PCM3); | |
163 | * bit 1 means the second playback PCM, and so on. | |
164 | */ | |
165 | unsigned long pcm_in_use; | |
079d88cc | 166 | |
4bd038f9 | 167 | struct hdmi_eld temp_eld; |
307229d2 | 168 | struct hdmi_ops ops; |
75fae117 SW |
169 | |
170 | bool dyn_pin_out; | |
6590faab | 171 | bool dyn_pcm_assign; |
079d88cc | 172 | /* |
5a613584 | 173 | * Non-generic VIA/NVIDIA specific |
079d88cc WF |
174 | */ |
175 | struct hda_multi_out multiout; | |
d0b1252d | 176 | struct hda_pcm_stream pcm_playback; |
25adc137 DH |
177 | |
178 | /* i915/powerwell (Haswell+/Valleyview+) specific */ | |
691be973 | 179 | bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */ |
ae891abe | 180 | struct drm_audio_component_audio_ops drm_audio_ops; |
67b90cb8 SP |
181 | |
182 | struct hdac_chmap chmap; | |
a87a4d23 | 183 | hda_nid_t vendor_nid; |
079d88cc WF |
184 | }; |
185 | ||
a57942bf | 186 | #ifdef CONFIG_SND_HDA_COMPONENT |
691be973 TI |
187 | static inline bool codec_has_acomp(struct hda_codec *codec) |
188 | { | |
189 | struct hdmi_spec *spec = codec->spec; | |
190 | return spec->use_acomp_notifier; | |
191 | } | |
f4e3040b TI |
192 | #else |
193 | #define codec_has_acomp(codec) false | |
194 | #endif | |
079d88cc WF |
195 | |
196 | struct hdmi_audio_infoframe { | |
197 | u8 type; /* 0x84 */ | |
198 | u8 ver; /* 0x01 */ | |
199 | u8 len; /* 0x0a */ | |
200 | ||
53d7d69d WF |
201 | u8 checksum; |
202 | ||
079d88cc WF |
203 | u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ |
204 | u8 SS01_SF24; | |
205 | u8 CXT04; | |
206 | u8 CA; | |
207 | u8 LFEPBL01_LSV36_DM_INH7; | |
53d7d69d WF |
208 | }; |
209 | ||
210 | struct dp_audio_infoframe { | |
211 | u8 type; /* 0x84 */ | |
212 | u8 len; /* 0x1b */ | |
213 | u8 ver; /* 0x11 << 2 */ | |
214 | ||
215 | u8 CC02_CT47; /* match with HDMI infoframe from this on */ | |
216 | u8 SS01_SF24; | |
217 | u8 CXT04; | |
218 | u8 CA; | |
219 | u8 LFEPBL01_LSV36_DM_INH7; | |
079d88cc WF |
220 | }; |
221 | ||
2b203dbb TI |
222 | union audio_infoframe { |
223 | struct hdmi_audio_infoframe hdmi; | |
224 | struct dp_audio_infoframe dp; | |
225 | u8 bytes[0]; | |
226 | }; | |
227 | ||
079d88cc WF |
228 | /* |
229 | * HDMI routines | |
230 | */ | |
231 | ||
bce0d2a8 TI |
232 | #define get_pin(spec, idx) \ |
233 | ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) | |
234 | #define get_cvt(spec, idx) \ | |
235 | ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) | |
2bea241a LY |
236 | /* obtain hdmi_pcm object assigned to idx */ |
237 | #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) | |
238 | /* obtain hda_pcm object assigned to idx */ | |
239 | #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) | |
bce0d2a8 | 240 | |
9152085d LY |
241 | static int pin_id_to_pin_index(struct hda_codec *codec, |
242 | hda_nid_t pin_nid, int dev_id) | |
079d88cc | 243 | { |
4e76a883 | 244 | struct hdmi_spec *spec = codec->spec; |
384a48d7 | 245 | int pin_idx; |
9152085d | 246 | struct hdmi_spec_per_pin *per_pin; |
079d88cc | 247 | |
9152085d LY |
248 | /* |
249 | * (dev_id == -1) means it is NON-MST pin | |
250 | * return the first virtual pin on this port | |
251 | */ | |
252 | if (dev_id == -1) | |
253 | dev_id = 0; | |
254 | ||
255 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
256 | per_pin = get_pin(spec, pin_idx); | |
257 | if ((per_pin->pin_nid == pin_nid) && | |
258 | (per_pin->dev_id == dev_id)) | |
384a48d7 | 259 | return pin_idx; |
9152085d | 260 | } |
079d88cc | 261 | |
4e76a883 | 262 | codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); |
384a48d7 SW |
263 | return -EINVAL; |
264 | } | |
265 | ||
2bf3c85a LY |
266 | static int hinfo_to_pcm_index(struct hda_codec *codec, |
267 | struct hda_pcm_stream *hinfo) | |
268 | { | |
269 | struct hdmi_spec *spec = codec->spec; | |
270 | int pcm_idx; | |
271 | ||
272 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) | |
273 | if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) | |
274 | return pcm_idx; | |
275 | ||
276 | codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); | |
277 | return -EINVAL; | |
278 | } | |
279 | ||
4e76a883 | 280 | static int hinfo_to_pin_index(struct hda_codec *codec, |
384a48d7 SW |
281 | struct hda_pcm_stream *hinfo) |
282 | { | |
4e76a883 | 283 | struct hdmi_spec *spec = codec->spec; |
6590faab | 284 | struct hdmi_spec_per_pin *per_pin; |
384a48d7 SW |
285 | int pin_idx; |
286 | ||
6590faab LY |
287 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
288 | per_pin = get_pin(spec, pin_idx); | |
2bea241a LY |
289 | if (per_pin->pcm && |
290 | per_pin->pcm->pcm->stream == hinfo) | |
384a48d7 | 291 | return pin_idx; |
6590faab | 292 | } |
384a48d7 | 293 | |
6590faab | 294 | codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); |
384a48d7 SW |
295 | return -EINVAL; |
296 | } | |
297 | ||
022f344b LY |
298 | static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, |
299 | int pcm_idx) | |
300 | { | |
301 | int i; | |
302 | struct hdmi_spec_per_pin *per_pin; | |
303 | ||
304 | for (i = 0; i < spec->num_pins; i++) { | |
305 | per_pin = get_pin(spec, i); | |
306 | if (per_pin->pcm_idx == pcm_idx) | |
307 | return per_pin; | |
308 | } | |
309 | return NULL; | |
310 | } | |
311 | ||
4e76a883 | 312 | static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) |
384a48d7 | 313 | { |
4e76a883 | 314 | struct hdmi_spec *spec = codec->spec; |
384a48d7 SW |
315 | int cvt_idx; |
316 | ||
317 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) | |
bce0d2a8 | 318 | if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) |
384a48d7 SW |
319 | return cvt_idx; |
320 | ||
4e76a883 | 321 | codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); |
079d88cc WF |
322 | return -EINVAL; |
323 | } | |
324 | ||
14bc52b8 PLB |
325 | static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, |
326 | struct snd_ctl_elem_info *uinfo) | |
327 | { | |
328 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
68e03de9 | 329 | struct hdmi_spec *spec = codec->spec; |
a4e9a38b | 330 | struct hdmi_spec_per_pin *per_pin; |
68e03de9 | 331 | struct hdmi_eld *eld; |
fb087eaa | 332 | int pcm_idx; |
14bc52b8 | 333 | |
14bc52b8 PLB |
334 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; |
335 | ||
fb087eaa LY |
336 | pcm_idx = kcontrol->private_value; |
337 | mutex_lock(&spec->pcm_lock); | |
338 | per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
339 | if (!per_pin) { | |
340 | /* no pin is bound to the pcm */ | |
341 | uinfo->count = 0; | |
342 | mutex_unlock(&spec->pcm_lock); | |
343 | return 0; | |
344 | } | |
a4e9a38b | 345 | eld = &per_pin->sink_eld; |
68e03de9 | 346 | uinfo->count = eld->eld_valid ? eld->eld_size : 0; |
fb087eaa | 347 | mutex_unlock(&spec->pcm_lock); |
14bc52b8 PLB |
348 | |
349 | return 0; | |
350 | } | |
351 | ||
352 | static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, | |
353 | struct snd_ctl_elem_value *ucontrol) | |
354 | { | |
355 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
68e03de9 | 356 | struct hdmi_spec *spec = codec->spec; |
a4e9a38b | 357 | struct hdmi_spec_per_pin *per_pin; |
68e03de9 | 358 | struct hdmi_eld *eld; |
fb087eaa | 359 | int pcm_idx; |
14bc52b8 | 360 | |
fb087eaa LY |
361 | pcm_idx = kcontrol->private_value; |
362 | mutex_lock(&spec->pcm_lock); | |
363 | per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
364 | if (!per_pin) { | |
365 | /* no pin is bound to the pcm */ | |
366 | memset(ucontrol->value.bytes.data, 0, | |
367 | ARRAY_SIZE(ucontrol->value.bytes.data)); | |
368 | mutex_unlock(&spec->pcm_lock); | |
369 | return 0; | |
370 | } | |
a4e9a38b | 371 | eld = &per_pin->sink_eld; |
68e03de9 | 372 | |
360a8245 DH |
373 | if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || |
374 | eld->eld_size > ELD_MAX_SIZE) { | |
fb087eaa | 375 | mutex_unlock(&spec->pcm_lock); |
68e03de9 DH |
376 | snd_BUG(); |
377 | return -EINVAL; | |
378 | } | |
379 | ||
380 | memset(ucontrol->value.bytes.data, 0, | |
381 | ARRAY_SIZE(ucontrol->value.bytes.data)); | |
382 | if (eld->eld_valid) | |
383 | memcpy(ucontrol->value.bytes.data, eld->eld_buffer, | |
384 | eld->eld_size); | |
fb087eaa | 385 | mutex_unlock(&spec->pcm_lock); |
14bc52b8 PLB |
386 | |
387 | return 0; | |
388 | } | |
389 | ||
f3b827e0 | 390 | static const struct snd_kcontrol_new eld_bytes_ctl = { |
14bc52b8 PLB |
391 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, |
392 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
393 | .name = "ELD", | |
394 | .info = hdmi_eld_ctl_info, | |
395 | .get = hdmi_eld_ctl_get, | |
396 | }; | |
397 | ||
fb087eaa | 398 | static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, |
14bc52b8 PLB |
399 | int device) |
400 | { | |
401 | struct snd_kcontrol *kctl; | |
402 | struct hdmi_spec *spec = codec->spec; | |
403 | int err; | |
404 | ||
405 | kctl = snd_ctl_new1(&eld_bytes_ctl, codec); | |
406 | if (!kctl) | |
407 | return -ENOMEM; | |
fb087eaa | 408 | kctl->private_value = pcm_idx; |
14bc52b8 PLB |
409 | kctl->id.device = device; |
410 | ||
fb087eaa LY |
411 | /* no pin nid is associated with the kctl now |
412 | * tbd: associate pin nid to eld ctl later | |
413 | */ | |
414 | err = snd_hda_ctl_add(codec, 0, kctl); | |
14bc52b8 PLB |
415 | if (err < 0) |
416 | return err; | |
417 | ||
fb087eaa | 418 | get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; |
14bc52b8 PLB |
419 | return 0; |
420 | } | |
421 | ||
079d88cc WF |
422 | #ifdef BE_PARANOID |
423 | static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, | |
424 | int *packet_index, int *byte_index) | |
425 | { | |
426 | int val; | |
427 | ||
428 | val = snd_hda_codec_read(codec, pin_nid, 0, | |
429 | AC_VERB_GET_HDMI_DIP_INDEX, 0); | |
430 | ||
431 | *packet_index = val >> 5; | |
432 | *byte_index = val & 0x1f; | |
433 | } | |
434 | #endif | |
435 | ||
436 | static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, | |
437 | int packet_index, int byte_index) | |
438 | { | |
439 | int val; | |
440 | ||
441 | val = (packet_index << 5) | (byte_index & 0x1f); | |
442 | ||
443 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); | |
444 | } | |
445 | ||
446 | static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, | |
447 | unsigned char val) | |
448 | { | |
449 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); | |
450 | } | |
451 | ||
384a48d7 | 452 | static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) |
079d88cc | 453 | { |
75fae117 SW |
454 | struct hdmi_spec *spec = codec->spec; |
455 | int pin_out; | |
456 | ||
079d88cc WF |
457 | /* Unmute */ |
458 | if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) | |
459 | snd_hda_codec_write(codec, pin_nid, 0, | |
460 | AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); | |
75fae117 SW |
461 | |
462 | if (spec->dyn_pin_out) | |
463 | /* Disable pin out until stream is active */ | |
464 | pin_out = 0; | |
465 | else | |
466 | /* Enable pin out: some machines with GM965 gets broken output | |
467 | * when the pin is disabled or changed while using with HDMI | |
468 | */ | |
469 | pin_out = PIN_OUT; | |
470 | ||
079d88cc | 471 | snd_hda_codec_write(codec, pin_nid, 0, |
75fae117 | 472 | AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); |
079d88cc WF |
473 | } |
474 | ||
a4e9a38b TI |
475 | /* |
476 | * ELD proc files | |
477 | */ | |
478 | ||
cd6a6503 | 479 | #ifdef CONFIG_SND_PROC_FS |
a4e9a38b TI |
480 | static void print_eld_info(struct snd_info_entry *entry, |
481 | struct snd_info_buffer *buffer) | |
482 | { | |
483 | struct hdmi_spec_per_pin *per_pin = entry->private_data; | |
484 | ||
485 | mutex_lock(&per_pin->lock); | |
486 | snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); | |
487 | mutex_unlock(&per_pin->lock); | |
488 | } | |
489 | ||
490 | static void write_eld_info(struct snd_info_entry *entry, | |
491 | struct snd_info_buffer *buffer) | |
492 | { | |
493 | struct hdmi_spec_per_pin *per_pin = entry->private_data; | |
494 | ||
495 | mutex_lock(&per_pin->lock); | |
496 | snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); | |
497 | mutex_unlock(&per_pin->lock); | |
498 | } | |
499 | ||
500 | static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) | |
501 | { | |
502 | char name[32]; | |
503 | struct hda_codec *codec = per_pin->codec; | |
504 | struct snd_info_entry *entry; | |
505 | int err; | |
506 | ||
507 | snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); | |
6efdd851 | 508 | err = snd_card_proc_new(codec->card, name, &entry); |
a4e9a38b TI |
509 | if (err < 0) |
510 | return err; | |
511 | ||
512 | snd_info_set_text_ops(entry, per_pin, print_eld_info); | |
513 | entry->c.text.write = write_eld_info; | |
6a73cf46 | 514 | entry->mode |= 0200; |
a4e9a38b TI |
515 | per_pin->proc_entry = entry; |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
520 | static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) | |
521 | { | |
1947a114 | 522 | if (!per_pin->codec->bus->shutdown) { |
c560a679 | 523 | snd_info_free_entry(per_pin->proc_entry); |
a4e9a38b TI |
524 | per_pin->proc_entry = NULL; |
525 | } | |
526 | } | |
527 | #else | |
b55447a7 TI |
528 | static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, |
529 | int index) | |
a4e9a38b TI |
530 | { |
531 | return 0; | |
532 | } | |
b55447a7 | 533 | static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) |
a4e9a38b TI |
534 | { |
535 | } | |
536 | #endif | |
079d88cc | 537 | |
079d88cc WF |
538 | /* |
539 | * Audio InfoFrame routines | |
540 | */ | |
541 | ||
542 | /* | |
543 | * Enable Audio InfoFrame Transmission | |
544 | */ | |
545 | static void hdmi_start_infoframe_trans(struct hda_codec *codec, | |
546 | hda_nid_t pin_nid) | |
547 | { | |
548 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
549 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, | |
550 | AC_DIPXMIT_BEST); | |
551 | } | |
552 | ||
553 | /* | |
554 | * Disable Audio InfoFrame Transmission | |
555 | */ | |
556 | static void hdmi_stop_infoframe_trans(struct hda_codec *codec, | |
557 | hda_nid_t pin_nid) | |
558 | { | |
559 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
560 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, | |
561 | AC_DIPXMIT_DISABLE); | |
562 | } | |
563 | ||
564 | static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) | |
565 | { | |
566 | #ifdef CONFIG_SND_DEBUG_VERBOSE | |
567 | int i; | |
568 | int size; | |
569 | ||
570 | size = snd_hdmi_get_eld_size(codec, pin_nid); | |
4e76a883 | 571 | codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); |
079d88cc WF |
572 | |
573 | for (i = 0; i < 8; i++) { | |
574 | size = snd_hda_codec_read(codec, pin_nid, 0, | |
575 | AC_VERB_GET_HDMI_DIP_SIZE, i); | |
4e76a883 | 576 | codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); |
079d88cc WF |
577 | } |
578 | #endif | |
579 | } | |
580 | ||
581 | static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) | |
582 | { | |
583 | #ifdef BE_PARANOID | |
584 | int i, j; | |
585 | int size; | |
586 | int pi, bi; | |
587 | for (i = 0; i < 8; i++) { | |
588 | size = snd_hda_codec_read(codec, pin_nid, 0, | |
589 | AC_VERB_GET_HDMI_DIP_SIZE, i); | |
590 | if (size == 0) | |
591 | continue; | |
592 | ||
593 | hdmi_set_dip_index(codec, pin_nid, i, 0x0); | |
594 | for (j = 1; j < 1000; j++) { | |
595 | hdmi_write_dip_byte(codec, pin_nid, 0x0); | |
596 | hdmi_get_dip_index(codec, pin_nid, &pi, &bi); | |
597 | if (pi != i) | |
4e76a883 | 598 | codec_dbg(codec, "dip index %d: %d != %d\n", |
079d88cc WF |
599 | bi, pi, i); |
600 | if (bi == 0) /* byte index wrapped around */ | |
601 | break; | |
602 | } | |
4e76a883 | 603 | codec_dbg(codec, |
079d88cc WF |
604 | "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", |
605 | i, size, j); | |
606 | } | |
607 | #endif | |
608 | } | |
609 | ||
53d7d69d | 610 | static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) |
079d88cc | 611 | { |
53d7d69d | 612 | u8 *bytes = (u8 *)hdmi_ai; |
079d88cc WF |
613 | u8 sum = 0; |
614 | int i; | |
615 | ||
53d7d69d | 616 | hdmi_ai->checksum = 0; |
079d88cc | 617 | |
53d7d69d | 618 | for (i = 0; i < sizeof(*hdmi_ai); i++) |
079d88cc WF |
619 | sum += bytes[i]; |
620 | ||
53d7d69d | 621 | hdmi_ai->checksum = -sum; |
079d88cc WF |
622 | } |
623 | ||
624 | static void hdmi_fill_audio_infoframe(struct hda_codec *codec, | |
625 | hda_nid_t pin_nid, | |
53d7d69d | 626 | u8 *dip, int size) |
079d88cc | 627 | { |
079d88cc WF |
628 | int i; |
629 | ||
630 | hdmi_debug_dip_size(codec, pin_nid); | |
631 | hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ | |
632 | ||
079d88cc | 633 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); |
53d7d69d WF |
634 | for (i = 0; i < size; i++) |
635 | hdmi_write_dip_byte(codec, pin_nid, dip[i]); | |
079d88cc WF |
636 | } |
637 | ||
638 | static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, | |
53d7d69d | 639 | u8 *dip, int size) |
079d88cc | 640 | { |
079d88cc WF |
641 | u8 val; |
642 | int i; | |
643 | ||
644 | if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) | |
645 | != AC_DIPXMIT_BEST) | |
646 | return false; | |
647 | ||
648 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
53d7d69d | 649 | for (i = 0; i < size; i++) { |
079d88cc WF |
650 | val = snd_hda_codec_read(codec, pin_nid, 0, |
651 | AC_VERB_GET_HDMI_DIP_DATA, 0); | |
53d7d69d | 652 | if (val != dip[i]) |
079d88cc WF |
653 | return false; |
654 | } | |
655 | ||
656 | return true; | |
657 | } | |
658 | ||
307229d2 AH |
659 | static void hdmi_pin_setup_infoframe(struct hda_codec *codec, |
660 | hda_nid_t pin_nid, | |
661 | int ca, int active_channels, | |
662 | int conn_type) | |
663 | { | |
664 | union audio_infoframe ai; | |
665 | ||
caaf5ef9 | 666 | memset(&ai, 0, sizeof(ai)); |
307229d2 AH |
667 | if (conn_type == 0) { /* HDMI */ |
668 | struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; | |
669 | ||
670 | hdmi_ai->type = 0x84; | |
671 | hdmi_ai->ver = 0x01; | |
672 | hdmi_ai->len = 0x0a; | |
673 | hdmi_ai->CC02_CT47 = active_channels - 1; | |
674 | hdmi_ai->CA = ca; | |
675 | hdmi_checksum_audio_infoframe(hdmi_ai); | |
676 | } else if (conn_type == 1) { /* DisplayPort */ | |
677 | struct dp_audio_infoframe *dp_ai = &ai.dp; | |
678 | ||
679 | dp_ai->type = 0x84; | |
680 | dp_ai->len = 0x1b; | |
681 | dp_ai->ver = 0x11 << 2; | |
682 | dp_ai->CC02_CT47 = active_channels - 1; | |
683 | dp_ai->CA = ca; | |
684 | } else { | |
4e76a883 | 685 | codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", |
307229d2 AH |
686 | pin_nid); |
687 | return; | |
688 | } | |
689 | ||
690 | /* | |
691 | * sizeof(ai) is used instead of sizeof(*hdmi_ai) or | |
692 | * sizeof(*dp_ai) to avoid partial match/update problems when | |
693 | * the user switches between HDMI/DP monitors. | |
694 | */ | |
695 | if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, | |
696 | sizeof(ai))) { | |
4e76a883 TI |
697 | codec_dbg(codec, |
698 | "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", | |
307229d2 AH |
699 | pin_nid, |
700 | active_channels, ca); | |
701 | hdmi_stop_infoframe_trans(codec, pin_nid); | |
702 | hdmi_fill_audio_infoframe(codec, pin_nid, | |
703 | ai.bytes, sizeof(ai)); | |
704 | hdmi_start_infoframe_trans(codec, pin_nid); | |
705 | } | |
706 | } | |
707 | ||
b054087d TI |
708 | static void hdmi_setup_audio_infoframe(struct hda_codec *codec, |
709 | struct hdmi_spec_per_pin *per_pin, | |
710 | bool non_pcm) | |
079d88cc | 711 | { |
307229d2 | 712 | struct hdmi_spec *spec = codec->spec; |
739ffee9 | 713 | struct hdac_chmap *chmap = &spec->chmap; |
384a48d7 | 714 | hda_nid_t pin_nid = per_pin->pin_nid; |
b054087d | 715 | int channels = per_pin->channels; |
1df5a06a | 716 | int active_channels; |
384a48d7 | 717 | struct hdmi_eld *eld; |
828cb4ed | 718 | int ca; |
079d88cc | 719 | |
b054087d TI |
720 | if (!channels) |
721 | return; | |
722 | ||
44bb6d0c TI |
723 | /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ |
724 | if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) | |
58f7d28d ML |
725 | snd_hda_codec_write(codec, pin_nid, 0, |
726 | AC_VERB_SET_AMP_GAIN_MUTE, | |
727 | AMP_OUT_UNMUTE); | |
728 | ||
bce0d2a8 | 729 | eld = &per_pin->sink_eld; |
079d88cc | 730 | |
bb63f726 | 731 | ca = snd_hdac_channel_allocation(&codec->core, |
828cb4ed SP |
732 | eld->info.spk_alloc, channels, |
733 | per_pin->chmap_set, non_pcm, per_pin->chmap); | |
384a48d7 | 734 | |
bb63f726 | 735 | active_channels = snd_hdac_get_active_channels(ca); |
1df5a06a | 736 | |
739ffee9 SP |
737 | chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, |
738 | active_channels); | |
1df5a06a | 739 | |
39edac70 AH |
740 | /* |
741 | * always configure channel mapping, it may have been changed by the | |
742 | * user in the meantime | |
743 | */ | |
bb63f726 | 744 | snd_hdac_setup_channel_mapping(&spec->chmap, |
828cb4ed SP |
745 | pin_nid, non_pcm, ca, channels, |
746 | per_pin->chmap, per_pin->chmap_set); | |
39edac70 | 747 | |
307229d2 AH |
748 | spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels, |
749 | eld->info.conn_type); | |
433968da | 750 | |
1a6003b5 | 751 | per_pin->non_pcm = non_pcm; |
079d88cc WF |
752 | } |
753 | ||
079d88cc WF |
754 | /* |
755 | * Unsolicited events | |
756 | */ | |
757 | ||
efe47108 | 758 | static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); |
38faddb1 | 759 | |
9152085d LY |
760 | static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, |
761 | int dev_id) | |
079d88cc WF |
762 | { |
763 | struct hdmi_spec *spec = codec->spec; | |
9152085d | 764 | int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); |
1a4f69d5 | 765 | |
20ce9029 DH |
766 | if (pin_idx < 0) |
767 | return; | |
aaa23f86 | 768 | mutex_lock(&spec->pcm_lock); |
20ce9029 DH |
769 | if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) |
770 | snd_hda_jack_report_sync(codec); | |
aaa23f86 | 771 | mutex_unlock(&spec->pcm_lock); |
20ce9029 DH |
772 | } |
773 | ||
1a4f69d5 TI |
774 | static void jack_callback(struct hda_codec *codec, |
775 | struct hda_jack_callback *jack) | |
776 | { | |
9152085d LY |
777 | /* hda_jack don't support DP MST */ |
778 | check_presence_and_report(codec, jack->nid, 0); | |
1a4f69d5 TI |
779 | } |
780 | ||
20ce9029 DH |
781 | static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) |
782 | { | |
3a93897e | 783 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; |
3a93897e | 784 | struct hda_jack_tbl *jack; |
2e59e5ab | 785 | int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; |
3a93897e | 786 | |
9152085d LY |
787 | /* |
788 | * assume DP MST uses dyn_pcm_assign and acomp and | |
789 | * never comes here | |
790 | * if DP MST supports unsol event, below code need | |
791 | * consider dev_entry | |
792 | */ | |
3a93897e TI |
793 | jack = snd_hda_jack_tbl_get_from_tag(codec, tag); |
794 | if (!jack) | |
795 | return; | |
3a93897e | 796 | jack->jack_dirty = 1; |
079d88cc | 797 | |
4e76a883 | 798 | codec_dbg(codec, |
2e59e5ab | 799 | "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", |
20ce9029 | 800 | codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA), |
fae3d88a | 801 | !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); |
079d88cc | 802 | |
9152085d LY |
803 | /* hda_jack don't support DP MST */ |
804 | check_presence_and_report(codec, jack->nid, 0); | |
079d88cc WF |
805 | } |
806 | ||
807 | static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) | |
808 | { | |
809 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; | |
810 | int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; | |
811 | int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); | |
812 | int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); | |
813 | ||
4e76a883 | 814 | codec_info(codec, |
e9ea8e8f | 815 | "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", |
384a48d7 | 816 | codec->addr, |
079d88cc WF |
817 | tag, |
818 | subtag, | |
819 | cp_state, | |
820 | cp_ready); | |
821 | ||
822 | /* TODO */ | |
823 | if (cp_state) | |
824 | ; | |
825 | if (cp_ready) | |
826 | ; | |
827 | } | |
828 | ||
829 | ||
830 | static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) | |
831 | { | |
079d88cc WF |
832 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; |
833 | int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; | |
834 | ||
3a93897e | 835 | if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) { |
4e76a883 | 836 | codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); |
079d88cc WF |
837 | return; |
838 | } | |
839 | ||
840 | if (subtag == 0) | |
841 | hdmi_intrinsic_event(codec, res); | |
842 | else | |
843 | hdmi_non_intrinsic_event(codec, res); | |
844 | } | |
845 | ||
58f7d28d | 846 | static void haswell_verify_D0(struct hda_codec *codec, |
53b434f0 | 847 | hda_nid_t cvt_nid, hda_nid_t nid) |
83f26ad2 | 848 | { |
58f7d28d | 849 | int pwr; |
83f26ad2 | 850 | |
53b434f0 WX |
851 | /* For Haswell, the converter 1/2 may keep in D3 state after bootup, |
852 | * thus pins could only choose converter 0 for use. Make sure the | |
853 | * converters are in correct power state */ | |
fd678cac | 854 | if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) |
53b434f0 WX |
855 | snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); |
856 | ||
fd678cac | 857 | if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { |
83f26ad2 DH |
858 | snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, |
859 | AC_PWRST_D0); | |
860 | msleep(40); | |
861 | pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); | |
862 | pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; | |
4e76a883 | 863 | codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); |
83f26ad2 | 864 | } |
83f26ad2 DH |
865 | } |
866 | ||
079d88cc WF |
867 | /* |
868 | * Callbacks | |
869 | */ | |
870 | ||
92f10b3f TI |
871 | /* HBR should be Non-PCM, 8 channels */ |
872 | #define is_hbr_format(format) \ | |
873 | ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) | |
874 | ||
307229d2 AH |
875 | static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, |
876 | bool hbr) | |
079d88cc | 877 | { |
307229d2 | 878 | int pinctl, new_pinctl; |
83f26ad2 | 879 | |
384a48d7 SW |
880 | if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { |
881 | pinctl = snd_hda_codec_read(codec, pin_nid, 0, | |
ea87d1c4 AH |
882 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); |
883 | ||
13122e6e AH |
884 | if (pinctl < 0) |
885 | return hbr ? -EINVAL : 0; | |
886 | ||
ea87d1c4 | 887 | new_pinctl = pinctl & ~AC_PINCTL_EPT; |
307229d2 | 888 | if (hbr) |
ea87d1c4 AH |
889 | new_pinctl |= AC_PINCTL_EPT_HBR; |
890 | else | |
891 | new_pinctl |= AC_PINCTL_EPT_NATIVE; | |
892 | ||
4e76a883 TI |
893 | codec_dbg(codec, |
894 | "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", | |
384a48d7 | 895 | pin_nid, |
ea87d1c4 AH |
896 | pinctl == new_pinctl ? "" : "new-", |
897 | new_pinctl); | |
898 | ||
899 | if (pinctl != new_pinctl) | |
384a48d7 | 900 | snd_hda_codec_write(codec, pin_nid, 0, |
ea87d1c4 AH |
901 | AC_VERB_SET_PIN_WIDGET_CONTROL, |
902 | new_pinctl); | |
307229d2 AH |
903 | } else if (hbr) |
904 | return -EINVAL; | |
ea87d1c4 | 905 | |
307229d2 AH |
906 | return 0; |
907 | } | |
908 | ||
909 | static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, | |
910 | hda_nid_t pin_nid, u32 stream_tag, int format) | |
911 | { | |
912 | struct hdmi_spec *spec = codec->spec; | |
5a5d718f | 913 | unsigned int param; |
307229d2 AH |
914 | int err; |
915 | ||
307229d2 AH |
916 | err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format)); |
917 | ||
918 | if (err) { | |
4e76a883 | 919 | codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); |
307229d2 | 920 | return err; |
ea87d1c4 | 921 | } |
079d88cc | 922 | |
5a5d718f SP |
923 | if (is_haswell_plus(codec)) { |
924 | ||
925 | /* | |
926 | * on recent platforms IEC Coding Type is required for HBR | |
927 | * support, read current Digital Converter settings and set | |
928 | * ICT bitfield if needed. | |
929 | */ | |
930 | param = snd_hda_codec_read(codec, cvt_nid, 0, | |
931 | AC_VERB_GET_DIGI_CONVERT_1, 0); | |
932 | ||
933 | param = (param >> 16) & ~(AC_DIG3_ICT); | |
934 | ||
935 | /* on recent platforms ICT mode is required for HBR support */ | |
936 | if (is_hbr_format(format)) | |
937 | param |= 0x1; | |
938 | ||
939 | snd_hda_codec_write(codec, cvt_nid, 0, | |
940 | AC_VERB_SET_DIGI_CONVERT_3, param); | |
941 | } | |
942 | ||
384a48d7 | 943 | snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); |
ea87d1c4 | 944 | return 0; |
079d88cc WF |
945 | } |
946 | ||
42b29870 LY |
947 | /* Try to find an available converter |
948 | * If pin_idx is less then zero, just try to find an available converter. | |
949 | * Otherwise, try to find an available converter and get the cvt mux index | |
950 | * of the pin. | |
951 | */ | |
7ef166b8 | 952 | static int hdmi_choose_cvt(struct hda_codec *codec, |
4846a67e | 953 | int pin_idx, int *cvt_id) |
bbbe3390 TI |
954 | { |
955 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 | 956 | struct hdmi_spec_per_pin *per_pin; |
384a48d7 | 957 | struct hdmi_spec_per_cvt *per_cvt = NULL; |
7ef166b8 | 958 | int cvt_idx, mux_idx = 0; |
bbbe3390 | 959 | |
42b29870 LY |
960 | /* pin_idx < 0 means no pin will be bound to the converter */ |
961 | if (pin_idx < 0) | |
962 | per_pin = NULL; | |
963 | else | |
964 | per_pin = get_pin(spec, pin_idx); | |
384a48d7 SW |
965 | |
966 | /* Dynamically assign converter to stream */ | |
967 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
bce0d2a8 | 968 | per_cvt = get_cvt(spec, cvt_idx); |
bbbe3390 | 969 | |
384a48d7 SW |
970 | /* Must not already be assigned */ |
971 | if (per_cvt->assigned) | |
972 | continue; | |
42b29870 LY |
973 | if (per_pin == NULL) |
974 | break; | |
384a48d7 SW |
975 | /* Must be in pin's mux's list of converters */ |
976 | for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) | |
977 | if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) | |
978 | break; | |
979 | /* Not in mux list */ | |
980 | if (mux_idx == per_pin->num_mux_nids) | |
981 | continue; | |
982 | break; | |
983 | } | |
7ef166b8 | 984 | |
384a48d7 SW |
985 | /* No free converters */ |
986 | if (cvt_idx == spec->num_cvts) | |
42b29870 | 987 | return -EBUSY; |
384a48d7 | 988 | |
42b29870 LY |
989 | if (per_pin != NULL) |
990 | per_pin->mux_idx = mux_idx; | |
2df6742f | 991 | |
7ef166b8 WX |
992 | if (cvt_id) |
993 | *cvt_id = cvt_idx; | |
7ef166b8 WX |
994 | |
995 | return 0; | |
996 | } | |
997 | ||
2df6742f ML |
998 | /* Assure the pin select the right convetor */ |
999 | static void intel_verify_pin_cvt_connect(struct hda_codec *codec, | |
1000 | struct hdmi_spec_per_pin *per_pin) | |
1001 | { | |
1002 | hda_nid_t pin_nid = per_pin->pin_nid; | |
1003 | int mux_idx, curr; | |
1004 | ||
1005 | mux_idx = per_pin->mux_idx; | |
1006 | curr = snd_hda_codec_read(codec, pin_nid, 0, | |
1007 | AC_VERB_GET_CONNECT_SEL, 0); | |
1008 | if (curr != mux_idx) | |
1009 | snd_hda_codec_write_cache(codec, pin_nid, 0, | |
1010 | AC_VERB_SET_CONNECT_SEL, | |
1011 | mux_idx); | |
1012 | } | |
1013 | ||
42b29870 LY |
1014 | /* get the mux index for the converter of the pins |
1015 | * converter's mux index is the same for all pins on Intel platform | |
1016 | */ | |
1017 | static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, | |
1018 | hda_nid_t cvt_nid) | |
1019 | { | |
1020 | int i; | |
1021 | ||
1022 | for (i = 0; i < spec->num_cvts; i++) | |
1023 | if (spec->cvt_nids[i] == cvt_nid) | |
1024 | return i; | |
1025 | return -EINVAL; | |
1026 | } | |
1027 | ||
300016b9 ML |
1028 | /* Intel HDMI workaround to fix audio routing issue: |
1029 | * For some Intel display codecs, pins share the same connection list. | |
1030 | * So a conveter can be selected by multiple pins and playback on any of these | |
1031 | * pins will generate sound on the external display, because audio flows from | |
1032 | * the same converter to the display pipeline. Also muting one pin may make | |
1033 | * other pins have no sound output. | |
1034 | * So this function assures that an assigned converter for a pin is not selected | |
1035 | * by any other pins. | |
1036 | */ | |
1037 | static void intel_not_share_assigned_cvt(struct hda_codec *codec, | |
9152085d LY |
1038 | hda_nid_t pin_nid, |
1039 | int dev_id, int mux_idx) | |
7ef166b8 WX |
1040 | { |
1041 | struct hdmi_spec *spec = codec->spec; | |
7639a06c | 1042 | hda_nid_t nid; |
f82d7d16 ML |
1043 | int cvt_idx, curr; |
1044 | struct hdmi_spec_per_cvt *per_cvt; | |
9152085d LY |
1045 | struct hdmi_spec_per_pin *per_pin; |
1046 | int pin_idx; | |
1047 | ||
1048 | /* configure the pins connections */ | |
1049 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
1050 | int dev_id_saved; | |
1051 | int dev_num; | |
7ef166b8 | 1052 | |
9152085d LY |
1053 | per_pin = get_pin(spec, pin_idx); |
1054 | /* | |
1055 | * pin not connected to monitor | |
1056 | * no need to operate on it | |
1057 | */ | |
1058 | if (!per_pin->pcm) | |
1059 | continue; | |
f82d7d16 | 1060 | |
9152085d LY |
1061 | if ((per_pin->pin_nid == pin_nid) && |
1062 | (per_pin->dev_id == dev_id)) | |
f82d7d16 | 1063 | continue; |
7ef166b8 | 1064 | |
9152085d LY |
1065 | /* |
1066 | * if per_pin->dev_id >= dev_num, | |
1067 | * snd_hda_get_dev_select() will fail, | |
1068 | * and the following operation is unpredictable. | |
1069 | * So skip this situation. | |
1070 | */ | |
1071 | dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; | |
1072 | if (per_pin->dev_id >= dev_num) | |
7ef166b8 WX |
1073 | continue; |
1074 | ||
9152085d LY |
1075 | nid = per_pin->pin_nid; |
1076 | ||
1077 | /* | |
1078 | * Calling this function should not impact | |
1079 | * on the device entry selection | |
1080 | * So let's save the dev id for each pin, | |
1081 | * and restore it when return | |
1082 | */ | |
1083 | dev_id_saved = snd_hda_get_dev_select(codec, nid); | |
1084 | snd_hda_set_dev_select(codec, nid, per_pin->dev_id); | |
f82d7d16 | 1085 | curr = snd_hda_codec_read(codec, nid, 0, |
7ef166b8 | 1086 | AC_VERB_GET_CONNECT_SEL, 0); |
9152085d LY |
1087 | if (curr != mux_idx) { |
1088 | snd_hda_set_dev_select(codec, nid, dev_id_saved); | |
f82d7d16 | 1089 | continue; |
9152085d LY |
1090 | } |
1091 | ||
7ef166b8 | 1092 | |
f82d7d16 ML |
1093 | /* choose an unassigned converter. The conveters in the |
1094 | * connection list are in the same order as in the codec. | |
1095 | */ | |
1096 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
1097 | per_cvt = get_cvt(spec, cvt_idx); | |
1098 | if (!per_cvt->assigned) { | |
4e76a883 TI |
1099 | codec_dbg(codec, |
1100 | "choose cvt %d for pin nid %d\n", | |
f82d7d16 ML |
1101 | cvt_idx, nid); |
1102 | snd_hda_codec_write_cache(codec, nid, 0, | |
7ef166b8 | 1103 | AC_VERB_SET_CONNECT_SEL, |
f82d7d16 ML |
1104 | cvt_idx); |
1105 | break; | |
1106 | } | |
7ef166b8 | 1107 | } |
9152085d | 1108 | snd_hda_set_dev_select(codec, nid, dev_id_saved); |
7ef166b8 WX |
1109 | } |
1110 | } | |
1111 | ||
42b29870 LY |
1112 | /* A wrapper of intel_not_share_asigned_cvt() */ |
1113 | static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, | |
9152085d | 1114 | hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) |
42b29870 LY |
1115 | { |
1116 | int mux_idx; | |
1117 | struct hdmi_spec *spec = codec->spec; | |
1118 | ||
42b29870 LY |
1119 | /* On Intel platform, the mapping of converter nid to |
1120 | * mux index of the pins are always the same. | |
1121 | * The pin nid may be 0, this means all pins will not | |
1122 | * share the converter. | |
1123 | */ | |
1124 | mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); | |
1125 | if (mux_idx >= 0) | |
9152085d | 1126 | intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); |
42b29870 LY |
1127 | } |
1128 | ||
4846a67e TI |
1129 | /* skeleton caller of pin_cvt_fixup ops */ |
1130 | static void pin_cvt_fixup(struct hda_codec *codec, | |
1131 | struct hdmi_spec_per_pin *per_pin, | |
1132 | hda_nid_t cvt_nid) | |
1133 | { | |
1134 | struct hdmi_spec *spec = codec->spec; | |
1135 | ||
1136 | if (spec->ops.pin_cvt_fixup) | |
1137 | spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); | |
1138 | } | |
1139 | ||
42b29870 LY |
1140 | /* called in hdmi_pcm_open when no pin is assigned to the PCM |
1141 | * in dyn_pcm_assign mode. | |
1142 | */ | |
1143 | static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, | |
1144 | struct hda_codec *codec, | |
1145 | struct snd_pcm_substream *substream) | |
1146 | { | |
1147 | struct hdmi_spec *spec = codec->spec; | |
1148 | struct snd_pcm_runtime *runtime = substream->runtime; | |
ac98379a | 1149 | int cvt_idx, pcm_idx; |
42b29870 LY |
1150 | struct hdmi_spec_per_cvt *per_cvt = NULL; |
1151 | int err; | |
1152 | ||
ac98379a LY |
1153 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1154 | if (pcm_idx < 0) | |
1155 | return -EINVAL; | |
1156 | ||
4846a67e | 1157 | err = hdmi_choose_cvt(codec, -1, &cvt_idx); |
42b29870 LY |
1158 | if (err) |
1159 | return err; | |
1160 | ||
1161 | per_cvt = get_cvt(spec, cvt_idx); | |
1162 | per_cvt->assigned = 1; | |
1163 | hinfo->nid = per_cvt->cvt_nid; | |
1164 | ||
4846a67e | 1165 | pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); |
42b29870 | 1166 | |
ac98379a | 1167 | set_bit(pcm_idx, &spec->pcm_in_use); |
42b29870 LY |
1168 | /* todo: setup spdif ctls assign */ |
1169 | ||
1170 | /* Initially set the converter's capabilities */ | |
1171 | hinfo->channels_min = per_cvt->channels_min; | |
1172 | hinfo->channels_max = per_cvt->channels_max; | |
1173 | hinfo->rates = per_cvt->rates; | |
1174 | hinfo->formats = per_cvt->formats; | |
1175 | hinfo->maxbps = per_cvt->maxbps; | |
1176 | ||
1177 | /* Store the updated parameters */ | |
1178 | runtime->hw.channels_min = hinfo->channels_min; | |
1179 | runtime->hw.channels_max = hinfo->channels_max; | |
1180 | runtime->hw.formats = hinfo->formats; | |
1181 | runtime->hw.rates = hinfo->rates; | |
1182 | ||
1183 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1184 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
1185 | return 0; | |
1186 | } | |
1187 | ||
7ef166b8 WX |
1188 | /* |
1189 | * HDA PCM callbacks | |
1190 | */ | |
1191 | static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, | |
1192 | struct hda_codec *codec, | |
1193 | struct snd_pcm_substream *substream) | |
1194 | { | |
1195 | struct hdmi_spec *spec = codec->spec; | |
1196 | struct snd_pcm_runtime *runtime = substream->runtime; | |
4846a67e | 1197 | int pin_idx, cvt_idx, pcm_idx; |
7ef166b8 WX |
1198 | struct hdmi_spec_per_pin *per_pin; |
1199 | struct hdmi_eld *eld; | |
1200 | struct hdmi_spec_per_cvt *per_cvt = NULL; | |
1201 | int err; | |
1202 | ||
1203 | /* Validate hinfo */ | |
2bf3c85a LY |
1204 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1205 | if (pcm_idx < 0) | |
7ef166b8 | 1206 | return -EINVAL; |
2bf3c85a | 1207 | |
42b29870 | 1208 | mutex_lock(&spec->pcm_lock); |
4e76a883 | 1209 | pin_idx = hinfo_to_pin_index(codec, hinfo); |
42b29870 LY |
1210 | if (!spec->dyn_pcm_assign) { |
1211 | if (snd_BUG_ON(pin_idx < 0)) { | |
1212 | mutex_unlock(&spec->pcm_lock); | |
1213 | return -EINVAL; | |
1214 | } | |
1215 | } else { | |
1216 | /* no pin is assigned to the PCM | |
1217 | * PA need pcm open successfully when probe | |
1218 | */ | |
1219 | if (pin_idx < 0) { | |
1220 | err = hdmi_pcm_open_no_pin(hinfo, codec, substream); | |
1221 | mutex_unlock(&spec->pcm_lock); | |
1222 | return err; | |
1223 | } | |
1224 | } | |
7ef166b8 | 1225 | |
4846a67e | 1226 | err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); |
42b29870 LY |
1227 | if (err < 0) { |
1228 | mutex_unlock(&spec->pcm_lock); | |
7ef166b8 | 1229 | return err; |
42b29870 | 1230 | } |
7ef166b8 WX |
1231 | |
1232 | per_cvt = get_cvt(spec, cvt_idx); | |
384a48d7 SW |
1233 | /* Claim converter */ |
1234 | per_cvt->assigned = 1; | |
42b29870 | 1235 | |
ac98379a | 1236 | set_bit(pcm_idx, &spec->pcm_in_use); |
42b29870 | 1237 | per_pin = get_pin(spec, pin_idx); |
1df5a06a | 1238 | per_pin->cvt_nid = per_cvt->cvt_nid; |
384a48d7 SW |
1239 | hinfo->nid = per_cvt->cvt_nid; |
1240 | ||
9152085d | 1241 | snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); |
bddee96b | 1242 | snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, |
384a48d7 | 1243 | AC_VERB_SET_CONNECT_SEL, |
4846a67e | 1244 | per_pin->mux_idx); |
7ef166b8 WX |
1245 | |
1246 | /* configure unused pins to choose other converters */ | |
4846a67e | 1247 | pin_cvt_fixup(codec, per_pin, 0); |
7ef166b8 | 1248 | |
2bf3c85a | 1249 | snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); |
bbbe3390 | 1250 | |
2def8172 | 1251 | /* Initially set the converter's capabilities */ |
384a48d7 SW |
1252 | hinfo->channels_min = per_cvt->channels_min; |
1253 | hinfo->channels_max = per_cvt->channels_max; | |
1254 | hinfo->rates = per_cvt->rates; | |
1255 | hinfo->formats = per_cvt->formats; | |
1256 | hinfo->maxbps = per_cvt->maxbps; | |
2def8172 | 1257 | |
42b29870 | 1258 | eld = &per_pin->sink_eld; |
384a48d7 | 1259 | /* Restrict capabilities by ELD if this isn't disabled */ |
c3d52105 | 1260 | if (!static_hdmi_pcm && eld->eld_valid) { |
1613d6b4 | 1261 | snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); |
bbbe3390 | 1262 | if (hinfo->channels_min > hinfo->channels_max || |
2ad779b7 TI |
1263 | !hinfo->rates || !hinfo->formats) { |
1264 | per_cvt->assigned = 0; | |
1265 | hinfo->nid = 0; | |
2bf3c85a | 1266 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
42b29870 | 1267 | mutex_unlock(&spec->pcm_lock); |
bbbe3390 | 1268 | return -ENODEV; |
2ad779b7 | 1269 | } |
bbbe3390 | 1270 | } |
2def8172 | 1271 | |
42b29870 | 1272 | mutex_unlock(&spec->pcm_lock); |
2def8172 | 1273 | /* Store the updated parameters */ |
639cef0e TI |
1274 | runtime->hw.channels_min = hinfo->channels_min; |
1275 | runtime->hw.channels_max = hinfo->channels_max; | |
1276 | runtime->hw.formats = hinfo->formats; | |
1277 | runtime->hw.rates = hinfo->rates; | |
4fe2ca14 TI |
1278 | |
1279 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1280 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
bbbe3390 TI |
1281 | return 0; |
1282 | } | |
1283 | ||
079d88cc WF |
1284 | /* |
1285 | * HDA/HDMI auto parsing | |
1286 | */ | |
384a48d7 | 1287 | static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) |
079d88cc WF |
1288 | { |
1289 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 1290 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
384a48d7 | 1291 | hda_nid_t pin_nid = per_pin->pin_nid; |
079d88cc WF |
1292 | |
1293 | if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { | |
4e76a883 TI |
1294 | codec_warn(codec, |
1295 | "HDMI: pin %d wcaps %#x does not support connection list\n", | |
079d88cc WF |
1296 | pin_nid, get_wcaps(codec, pin_nid)); |
1297 | return -EINVAL; | |
1298 | } | |
1299 | ||
9152085d | 1300 | /* all the device entries on the same pin have the same conn list */ |
384a48d7 SW |
1301 | per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid, |
1302 | per_pin->mux_nids, | |
1303 | HDA_MAX_CONNECTIONS); | |
079d88cc WF |
1304 | |
1305 | return 0; | |
1306 | } | |
1307 | ||
a76056f2 LY |
1308 | static int hdmi_find_pcm_slot(struct hdmi_spec *spec, |
1309 | struct hdmi_spec_per_pin *per_pin) | |
1310 | { | |
1311 | int i; | |
1312 | ||
1313 | /* try the prefer PCM */ | |
1314 | if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) | |
1315 | return per_pin->pin_nid_idx; | |
1316 | ||
1317 | /* have a second try; check the "reserved area" over num_pins */ | |
9152085d | 1318 | for (i = spec->num_nids; i < spec->pcm_used; i++) { |
a76056f2 LY |
1319 | if (!test_bit(i, &spec->pcm_bitmap)) |
1320 | return i; | |
1321 | } | |
1322 | ||
1323 | /* the last try; check the empty slots in pins */ | |
9152085d | 1324 | for (i = 0; i < spec->num_nids; i++) { |
a76056f2 LY |
1325 | if (!test_bit(i, &spec->pcm_bitmap)) |
1326 | return i; | |
1327 | } | |
1328 | return -EBUSY; | |
1329 | } | |
1330 | ||
1331 | static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, | |
1332 | struct hdmi_spec_per_pin *per_pin) | |
1333 | { | |
1334 | int idx; | |
1335 | ||
1336 | /* pcm already be attached to the pin */ | |
1337 | if (per_pin->pcm) | |
1338 | return; | |
1339 | idx = hdmi_find_pcm_slot(spec, per_pin); | |
d10a80de | 1340 | if (idx == -EBUSY) |
a76056f2 LY |
1341 | return; |
1342 | per_pin->pcm_idx = idx; | |
2bea241a | 1343 | per_pin->pcm = get_hdmi_pcm(spec, idx); |
a76056f2 LY |
1344 | set_bit(idx, &spec->pcm_bitmap); |
1345 | } | |
1346 | ||
1347 | static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, | |
1348 | struct hdmi_spec_per_pin *per_pin) | |
1349 | { | |
1350 | int idx; | |
1351 | ||
1352 | /* pcm already be detached from the pin */ | |
1353 | if (!per_pin->pcm) | |
1354 | return; | |
1355 | idx = per_pin->pcm_idx; | |
1356 | per_pin->pcm_idx = -1; | |
1357 | per_pin->pcm = NULL; | |
1358 | if (idx >= 0 && idx < spec->pcm_used) | |
1359 | clear_bit(idx, &spec->pcm_bitmap); | |
1360 | } | |
1361 | ||
ac98379a LY |
1362 | static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, |
1363 | struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) | |
1364 | { | |
1365 | int mux_idx; | |
1366 | ||
1367 | for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) | |
1368 | if (per_pin->mux_nids[mux_idx] == cvt_nid) | |
1369 | break; | |
1370 | return mux_idx; | |
1371 | } | |
1372 | ||
1373 | static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); | |
1374 | ||
1375 | static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, | |
1376 | struct hdmi_spec_per_pin *per_pin) | |
1377 | { | |
1378 | struct hda_codec *codec = per_pin->codec; | |
1379 | struct hda_pcm *pcm; | |
1380 | struct hda_pcm_stream *hinfo; | |
1381 | struct snd_pcm_substream *substream; | |
1382 | int mux_idx; | |
1383 | bool non_pcm; | |
1384 | ||
1385 | if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) | |
2bea241a | 1386 | pcm = get_pcm_rec(spec, per_pin->pcm_idx); |
ac98379a LY |
1387 | else |
1388 | return; | |
8a7d6003 TI |
1389 | if (!pcm->pcm) |
1390 | return; | |
ac98379a LY |
1391 | if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) |
1392 | return; | |
1393 | ||
1394 | /* hdmi audio only uses playback and one substream */ | |
1395 | hinfo = pcm->stream; | |
1396 | substream = pcm->pcm->streams[0].substream; | |
1397 | ||
1398 | per_pin->cvt_nid = hinfo->nid; | |
1399 | ||
1400 | mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); | |
9152085d LY |
1401 | if (mux_idx < per_pin->num_mux_nids) { |
1402 | snd_hda_set_dev_select(codec, per_pin->pin_nid, | |
1403 | per_pin->dev_id); | |
ac98379a LY |
1404 | snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, |
1405 | AC_VERB_SET_CONNECT_SEL, | |
1406 | mux_idx); | |
9152085d | 1407 | } |
ac98379a LY |
1408 | snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); |
1409 | ||
1410 | non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); | |
1411 | if (substream->runtime) | |
1412 | per_pin->channels = substream->runtime->channels; | |
1413 | per_pin->setup = true; | |
1414 | per_pin->mux_idx = mux_idx; | |
1415 | ||
1416 | hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); | |
1417 | } | |
1418 | ||
1419 | static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, | |
1420 | struct hdmi_spec_per_pin *per_pin) | |
1421 | { | |
1422 | if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) | |
1423 | snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); | |
1424 | ||
1425 | per_pin->chmap_set = false; | |
1426 | memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); | |
1427 | ||
1428 | per_pin->setup = false; | |
1429 | per_pin->channels = 0; | |
1430 | } | |
1431 | ||
e90247f9 TI |
1432 | /* update per_pin ELD from the given new ELD; |
1433 | * setup info frame and notification accordingly | |
1434 | */ | |
1435 | static void update_eld(struct hda_codec *codec, | |
1436 | struct hdmi_spec_per_pin *per_pin, | |
1437 | struct hdmi_eld *eld) | |
1438 | { | |
1439 | struct hdmi_eld *pin_eld = &per_pin->sink_eld; | |
a76056f2 | 1440 | struct hdmi_spec *spec = codec->spec; |
e90247f9 TI |
1441 | bool old_eld_valid = pin_eld->eld_valid; |
1442 | bool eld_changed; | |
fb087eaa | 1443 | int pcm_idx = -1; |
e90247f9 | 1444 | |
fb087eaa LY |
1445 | /* for monitor disconnection, save pcm_idx firstly */ |
1446 | pcm_idx = per_pin->pcm_idx; | |
a76056f2 | 1447 | if (spec->dyn_pcm_assign) { |
ac98379a | 1448 | if (eld->eld_valid) { |
a76056f2 | 1449 | hdmi_attach_hda_pcm(spec, per_pin); |
ac98379a LY |
1450 | hdmi_pcm_setup_pin(spec, per_pin); |
1451 | } else { | |
1452 | hdmi_pcm_reset_pin(spec, per_pin); | |
a76056f2 | 1453 | hdmi_detach_hda_pcm(spec, per_pin); |
ac98379a | 1454 | } |
a76056f2 | 1455 | } |
fb087eaa LY |
1456 | /* if pcm_idx == -1, it means this is in monitor connection event |
1457 | * we can get the correct pcm_idx now. | |
1458 | */ | |
1459 | if (pcm_idx == -1) | |
1460 | pcm_idx = per_pin->pcm_idx; | |
a76056f2 | 1461 | |
e90247f9 TI |
1462 | if (eld->eld_valid) |
1463 | snd_hdmi_show_eld(codec, &eld->info); | |
1464 | ||
1465 | eld_changed = (pin_eld->eld_valid != eld->eld_valid); | |
1466 | if (eld->eld_valid && pin_eld->eld_valid) | |
1467 | if (pin_eld->eld_size != eld->eld_size || | |
1468 | memcmp(pin_eld->eld_buffer, eld->eld_buffer, | |
1469 | eld->eld_size) != 0) | |
1470 | eld_changed = true; | |
1471 | ||
bd481285 | 1472 | pin_eld->monitor_present = eld->monitor_present; |
e90247f9 TI |
1473 | pin_eld->eld_valid = eld->eld_valid; |
1474 | pin_eld->eld_size = eld->eld_size; | |
1475 | if (eld->eld_valid) | |
1476 | memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size); | |
1477 | pin_eld->info = eld->info; | |
1478 | ||
1479 | /* | |
1480 | * Re-setup pin and infoframe. This is needed e.g. when | |
1481 | * - sink is first plugged-in | |
1482 | * - transcoder can change during stream playback on Haswell | |
1483 | * and this can make HW reset converter selection on a pin. | |
1484 | */ | |
1485 | if (eld->eld_valid && !old_eld_valid && per_pin->setup) { | |
4846a67e | 1486 | pin_cvt_fixup(codec, per_pin, 0); |
e90247f9 TI |
1487 | hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); |
1488 | } | |
1489 | ||
fb087eaa | 1490 | if (eld_changed && pcm_idx >= 0) |
e90247f9 TI |
1491 | snd_ctl_notify(codec->card, |
1492 | SNDRV_CTL_EVENT_MASK_VALUE | | |
1493 | SNDRV_CTL_EVENT_MASK_INFO, | |
fb087eaa | 1494 | &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); |
e90247f9 TI |
1495 | } |
1496 | ||
788d441a TI |
1497 | /* update ELD and jack state via HD-audio verbs */ |
1498 | static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, | |
1499 | int repoll) | |
079d88cc | 1500 | { |
464837a7 | 1501 | struct hda_jack_tbl *jack; |
744626da | 1502 | struct hda_codec *codec = per_pin->codec; |
4bd038f9 DH |
1503 | struct hdmi_spec *spec = codec->spec; |
1504 | struct hdmi_eld *eld = &spec->temp_eld; | |
744626da | 1505 | hda_nid_t pin_nid = per_pin->pin_nid; |
5d44f927 SW |
1506 | /* |
1507 | * Always execute a GetPinSense verb here, even when called from | |
1508 | * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited | |
1509 | * response's PD bit is not the real PD value, but indicates that | |
1510 | * the real PD value changed. An older version of the HD-audio | |
1511 | * specification worked this way. Hence, we just ignore the data in | |
1512 | * the unsolicited response to avoid custom WARs. | |
1513 | */ | |
da4a7a39 | 1514 | int present; |
efe47108 | 1515 | bool ret; |
9a5e5234 | 1516 | bool do_repoll = false; |
079d88cc | 1517 | |
da4a7a39 DH |
1518 | present = snd_hda_pin_sense(codec, pin_nid); |
1519 | ||
a4e9a38b | 1520 | mutex_lock(&per_pin->lock); |
c44da62b TI |
1521 | eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); |
1522 | if (eld->monitor_present) | |
4bd038f9 DH |
1523 | eld->eld_valid = !!(present & AC_PINSENSE_ELDV); |
1524 | else | |
1525 | eld->eld_valid = false; | |
079d88cc | 1526 | |
4e76a883 | 1527 | codec_dbg(codec, |
384a48d7 | 1528 | "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", |
c44da62b | 1529 | codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); |
5d44f927 | 1530 | |
4bd038f9 | 1531 | if (eld->eld_valid) { |
307229d2 | 1532 | if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer, |
1613d6b4 | 1533 | &eld->eld_size) < 0) |
4bd038f9 | 1534 | eld->eld_valid = false; |
1613d6b4 | 1535 | else { |
79514d47 | 1536 | if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, |
1613d6b4 | 1537 | eld->eld_size) < 0) |
4bd038f9 | 1538 | eld->eld_valid = false; |
1613d6b4 | 1539 | } |
9a5e5234 TI |
1540 | if (!eld->eld_valid && repoll) |
1541 | do_repoll = true; | |
744626da | 1542 | } |
4bd038f9 | 1543 | |
9a5e5234 | 1544 | if (do_repoll) |
e90247f9 TI |
1545 | schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); |
1546 | else | |
1547 | update_eld(codec, per_pin, eld); | |
92c69e79 | 1548 | |
c44da62b | 1549 | ret = !repoll || !eld->monitor_present || eld->eld_valid; |
464837a7 DH |
1550 | |
1551 | jack = snd_hda_jack_tbl_get(codec, pin_nid); | |
1552 | if (jack) | |
1553 | jack->block_report = !ret; | |
1554 | ||
a4e9a38b | 1555 | mutex_unlock(&per_pin->lock); |
efe47108 | 1556 | return ret; |
079d88cc WF |
1557 | } |
1558 | ||
3184270e LY |
1559 | static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec, |
1560 | struct hdmi_spec_per_pin *per_pin) | |
1561 | { | |
1562 | struct hdmi_spec *spec = codec->spec; | |
1563 | struct snd_jack *jack = NULL; | |
1564 | struct hda_jack_tbl *jack_tbl; | |
1565 | ||
1566 | /* if !dyn_pcm_assign, get jack from hda_jack_tbl | |
1567 | * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not | |
1568 | * NULL even after snd_hda_jack_tbl_clear() is called to | |
1569 | * free snd_jack. This may cause access invalid memory | |
1570 | * when calling snd_jack_report | |
1571 | */ | |
1572 | if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign) | |
1573 | jack = spec->pcm_rec[per_pin->pcm_idx].jack; | |
1574 | else if (!spec->dyn_pcm_assign) { | |
9152085d LY |
1575 | /* |
1576 | * jack tbl doesn't support DP MST | |
1577 | * DP MST will use dyn_pcm_assign, | |
1578 | * so DP MST will never come here | |
1579 | */ | |
3184270e LY |
1580 | jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); |
1581 | if (jack_tbl) | |
1582 | jack = jack_tbl->jack; | |
1583 | } | |
1584 | return jack; | |
1585 | } | |
1586 | ||
788d441a TI |
1587 | /* update ELD and jack state via audio component */ |
1588 | static void sync_eld_via_acomp(struct hda_codec *codec, | |
1589 | struct hdmi_spec_per_pin *per_pin) | |
1590 | { | |
788d441a TI |
1591 | struct hdmi_spec *spec = codec->spec; |
1592 | struct hdmi_eld *eld = &spec->temp_eld; | |
25e4abb3 | 1593 | struct snd_jack *jack = NULL; |
788d441a TI |
1594 | int size; |
1595 | ||
e2dc7d7d | 1596 | mutex_lock(&per_pin->lock); |
c64c1437 | 1597 | eld->monitor_present = false; |
9152085d LY |
1598 | size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, |
1599 | per_pin->dev_id, &eld->monitor_present, | |
1600 | eld->eld_buffer, ELD_MAX_SIZE); | |
e2dc7d7d TI |
1601 | if (size > 0) { |
1602 | size = min(size, ELD_MAX_SIZE); | |
1603 | if (snd_hdmi_parse_eld(codec, &eld->info, | |
1604 | eld->eld_buffer, size) < 0) | |
1605 | size = -EINVAL; | |
1606 | } | |
788d441a | 1607 | |
e2dc7d7d TI |
1608 | if (size > 0) { |
1609 | eld->eld_valid = true; | |
1610 | eld->eld_size = size; | |
1611 | } else { | |
1612 | eld->eld_valid = false; | |
1613 | eld->eld_size = 0; | |
788d441a | 1614 | } |
e2dc7d7d | 1615 | |
25e4abb3 LY |
1616 | /* pcm_idx >=0 before update_eld() means it is in monitor |
1617 | * disconnected event. Jack must be fetched before update_eld() | |
1618 | */ | |
3184270e | 1619 | jack = pin_idx_to_jack(codec, per_pin); |
e2dc7d7d | 1620 | update_eld(codec, per_pin, eld); |
3184270e LY |
1621 | if (jack == NULL) |
1622 | jack = pin_idx_to_jack(codec, per_pin); | |
25e4abb3 LY |
1623 | if (jack == NULL) |
1624 | goto unlock; | |
1625 | snd_jack_report(jack, | |
e2dc7d7d TI |
1626 | eld->monitor_present ? SND_JACK_AVOUT : 0); |
1627 | unlock: | |
1628 | mutex_unlock(&per_pin->lock); | |
788d441a TI |
1629 | } |
1630 | ||
1631 | static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) | |
1632 | { | |
1633 | struct hda_codec *codec = per_pin->codec; | |
a76056f2 | 1634 | int ret; |
788d441a | 1635 | |
222bde03 | 1636 | /* no temporary power up/down needed for component notifier */ |
aaa23f86 CW |
1637 | if (!codec_has_acomp(codec)) { |
1638 | ret = snd_hda_power_up_pm(codec); | |
1639 | if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) { | |
1640 | snd_hda_power_down_pm(codec); | |
1641 | return false; | |
1642 | } | |
1643 | } | |
222bde03 | 1644 | |
788d441a TI |
1645 | if (codec_has_acomp(codec)) { |
1646 | sync_eld_via_acomp(codec, per_pin); | |
a76056f2 | 1647 | ret = false; /* don't call snd_hda_jack_report_sync() */ |
788d441a | 1648 | } else { |
a76056f2 | 1649 | ret = hdmi_present_sense_via_verbs(per_pin, repoll); |
788d441a | 1650 | } |
a76056f2 | 1651 | |
222bde03 TI |
1652 | if (!codec_has_acomp(codec)) |
1653 | snd_hda_power_down_pm(codec); | |
1654 | ||
a76056f2 | 1655 | return ret; |
788d441a TI |
1656 | } |
1657 | ||
744626da WF |
1658 | static void hdmi_repoll_eld(struct work_struct *work) |
1659 | { | |
1660 | struct hdmi_spec_per_pin *per_pin = | |
1661 | container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); | |
aaa23f86 CW |
1662 | struct hda_codec *codec = per_pin->codec; |
1663 | struct hdmi_spec *spec = codec->spec; | |
744626da | 1664 | |
c6e8453e WF |
1665 | if (per_pin->repoll_count++ > 6) |
1666 | per_pin->repoll_count = 0; | |
1667 | ||
aaa23f86 | 1668 | mutex_lock(&spec->pcm_lock); |
efe47108 TI |
1669 | if (hdmi_present_sense(per_pin, per_pin->repoll_count)) |
1670 | snd_hda_jack_report_sync(per_pin->codec); | |
aaa23f86 | 1671 | mutex_unlock(&spec->pcm_lock); |
744626da WF |
1672 | } |
1673 | ||
c88d4e84 TI |
1674 | static void intel_haswell_fixup_connect_list(struct hda_codec *codec, |
1675 | hda_nid_t nid); | |
1676 | ||
079d88cc WF |
1677 | static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) |
1678 | { | |
1679 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
1680 | unsigned int caps, config; |
1681 | int pin_idx; | |
1682 | struct hdmi_spec_per_pin *per_pin; | |
07acecc1 | 1683 | int err; |
9152085d | 1684 | int dev_num, i; |
079d88cc | 1685 | |
efc2f8de | 1686 | caps = snd_hda_query_pin_caps(codec, pin_nid); |
384a48d7 SW |
1687 | if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) |
1688 | return 0; | |
1689 | ||
9152085d LY |
1690 | /* |
1691 | * For DP MST audio, Configuration Default is the same for | |
1692 | * all device entries on the same pin | |
1693 | */ | |
efc2f8de | 1694 | config = snd_hda_codec_get_pincfg(codec, pin_nid); |
384a48d7 SW |
1695 | if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) |
1696 | return 0; | |
1697 | ||
9152085d LY |
1698 | /* |
1699 | * To simplify the implementation, malloc all | |
1700 | * the virtual pins in the initialization statically | |
1701 | */ | |
1702 | if (is_haswell_plus(codec)) { | |
1703 | /* | |
1704 | * On Intel platforms, device entries number is | |
1705 | * changed dynamically. If there is a DP MST | |
1706 | * hub connected, the device entries number is 3. | |
1707 | * Otherwise, it is 1. | |
1708 | * Here we manually set dev_num to 3, so that | |
1709 | * we can initialize all the device entries when | |
1710 | * bootup statically. | |
1711 | */ | |
1712 | dev_num = 3; | |
1713 | spec->dev_num = 3; | |
1714 | } else if (spec->dyn_pcm_assign && codec->dp_mst) { | |
1715 | dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; | |
1716 | /* | |
1717 | * spec->dev_num is the maxinum number of device entries | |
1718 | * among all the pins | |
1719 | */ | |
1720 | spec->dev_num = (spec->dev_num > dev_num) ? | |
1721 | spec->dev_num : dev_num; | |
1722 | } else { | |
1723 | /* | |
1724 | * If the platform doesn't support DP MST, | |
1725 | * manually set dev_num to 1. This means | |
1726 | * the pin has only one device entry. | |
1727 | */ | |
1728 | dev_num = 1; | |
1729 | spec->dev_num = 1; | |
2bea241a | 1730 | } |
079d88cc | 1731 | |
9152085d LY |
1732 | for (i = 0; i < dev_num; i++) { |
1733 | pin_idx = spec->num_pins; | |
1734 | per_pin = snd_array_new(&spec->pins); | |
079d88cc | 1735 | |
9152085d LY |
1736 | if (!per_pin) |
1737 | return -ENOMEM; | |
1738 | ||
1739 | if (spec->dyn_pcm_assign) { | |
1740 | per_pin->pcm = NULL; | |
1741 | per_pin->pcm_idx = -1; | |
1742 | } else { | |
1743 | per_pin->pcm = get_hdmi_pcm(spec, pin_idx); | |
1744 | per_pin->pcm_idx = pin_idx; | |
1745 | } | |
1746 | per_pin->pin_nid = pin_nid; | |
1747 | per_pin->pin_nid_idx = spec->num_nids; | |
1748 | per_pin->dev_id = i; | |
1749 | per_pin->non_pcm = false; | |
1750 | snd_hda_set_dev_select(codec, pin_nid, i); | |
1751 | if (is_haswell_plus(codec)) | |
1752 | intel_haswell_fixup_connect_list(codec, pin_nid); | |
1753 | err = hdmi_read_pin_conn(codec, pin_idx); | |
1754 | if (err < 0) | |
1755 | return err; | |
1756 | spec->num_pins++; | |
1757 | } | |
1758 | spec->num_nids++; | |
079d88cc | 1759 | |
384a48d7 | 1760 | return 0; |
079d88cc WF |
1761 | } |
1762 | ||
384a48d7 | 1763 | static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) |
079d88cc WF |
1764 | { |
1765 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
1766 | struct hdmi_spec_per_cvt *per_cvt; |
1767 | unsigned int chans; | |
1768 | int err; | |
079d88cc | 1769 | |
384a48d7 SW |
1770 | chans = get_wcaps(codec, cvt_nid); |
1771 | chans = get_wcaps_channels(chans); | |
1772 | ||
bce0d2a8 TI |
1773 | per_cvt = snd_array_new(&spec->cvts); |
1774 | if (!per_cvt) | |
1775 | return -ENOMEM; | |
384a48d7 SW |
1776 | |
1777 | per_cvt->cvt_nid = cvt_nid; | |
1778 | per_cvt->channels_min = 2; | |
d45e6889 | 1779 | if (chans <= 16) { |
384a48d7 | 1780 | per_cvt->channels_max = chans; |
67b90cb8 SP |
1781 | if (chans > spec->chmap.channels_max) |
1782 | spec->chmap.channels_max = chans; | |
d45e6889 | 1783 | } |
384a48d7 SW |
1784 | |
1785 | err = snd_hda_query_supported_pcm(codec, cvt_nid, | |
1786 | &per_cvt->rates, | |
1787 | &per_cvt->formats, | |
1788 | &per_cvt->maxbps); | |
1789 | if (err < 0) | |
1790 | return err; | |
1791 | ||
bce0d2a8 TI |
1792 | if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) |
1793 | spec->cvt_nids[spec->num_cvts] = cvt_nid; | |
1794 | spec->num_cvts++; | |
079d88cc WF |
1795 | |
1796 | return 0; | |
1797 | } | |
1798 | ||
1799 | static int hdmi_parse_codec(struct hda_codec *codec) | |
1800 | { | |
1801 | hda_nid_t nid; | |
1802 | int i, nodes; | |
1803 | ||
7639a06c | 1804 | nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); |
079d88cc | 1805 | if (!nid || nodes < 0) { |
4e76a883 | 1806 | codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); |
079d88cc WF |
1807 | return -EINVAL; |
1808 | } | |
1809 | ||
1810 | for (i = 0; i < nodes; i++, nid++) { | |
1811 | unsigned int caps; | |
1812 | unsigned int type; | |
1813 | ||
efc2f8de | 1814 | caps = get_wcaps(codec, nid); |
079d88cc WF |
1815 | type = get_wcaps_type(caps); |
1816 | ||
1817 | if (!(caps & AC_WCAP_DIGITAL)) | |
1818 | continue; | |
1819 | ||
1820 | switch (type) { | |
1821 | case AC_WID_AUD_OUT: | |
384a48d7 | 1822 | hdmi_add_cvt(codec, nid); |
079d88cc WF |
1823 | break; |
1824 | case AC_WID_PIN: | |
3eaead57 | 1825 | hdmi_add_pin(codec, nid); |
079d88cc WF |
1826 | break; |
1827 | } | |
1828 | } | |
1829 | ||
079d88cc WF |
1830 | return 0; |
1831 | } | |
1832 | ||
84eb01be TI |
1833 | /* |
1834 | */ | |
1a6003b5 TI |
1835 | static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) |
1836 | { | |
1837 | struct hda_spdif_out *spdif; | |
1838 | bool non_pcm; | |
1839 | ||
1840 | mutex_lock(&codec->spdif_mutex); | |
1841 | spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); | |
960a581e LY |
1842 | /* Add sanity check to pass klockwork check. |
1843 | * This should never happen. | |
1844 | */ | |
1845 | if (WARN_ON(spdif == NULL)) | |
1846 | return true; | |
1a6003b5 TI |
1847 | non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); |
1848 | mutex_unlock(&codec->spdif_mutex); | |
1849 | return non_pcm; | |
1850 | } | |
1851 | ||
84eb01be TI |
1852 | /* |
1853 | * HDMI callbacks | |
1854 | */ | |
1855 | ||
1856 | static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
1857 | struct hda_codec *codec, | |
1858 | unsigned int stream_tag, | |
1859 | unsigned int format, | |
1860 | struct snd_pcm_substream *substream) | |
1861 | { | |
384a48d7 SW |
1862 | hda_nid_t cvt_nid = hinfo->nid; |
1863 | struct hdmi_spec *spec = codec->spec; | |
42b29870 LY |
1864 | int pin_idx; |
1865 | struct hdmi_spec_per_pin *per_pin; | |
1866 | hda_nid_t pin_nid; | |
ddd621fb | 1867 | struct snd_pcm_runtime *runtime = substream->runtime; |
1a6003b5 | 1868 | bool non_pcm; |
75fae117 | 1869 | int pinctl; |
42b29870 | 1870 | int err; |
1a6003b5 | 1871 | |
42b29870 LY |
1872 | mutex_lock(&spec->pcm_lock); |
1873 | pin_idx = hinfo_to_pin_index(codec, hinfo); | |
1874 | if (spec->dyn_pcm_assign && pin_idx < 0) { | |
1875 | /* when dyn_pcm_assign and pcm is not bound to a pin | |
1876 | * skip pin setup and return 0 to make audio playback | |
1877 | * be ongoing | |
1878 | */ | |
4846a67e | 1879 | pin_cvt_fixup(codec, NULL, cvt_nid); |
42b29870 LY |
1880 | snd_hda_codec_setup_stream(codec, cvt_nid, |
1881 | stream_tag, 0, format); | |
1882 | mutex_unlock(&spec->pcm_lock); | |
1883 | return 0; | |
1884 | } | |
1a6003b5 | 1885 | |
42b29870 LY |
1886 | if (snd_BUG_ON(pin_idx < 0)) { |
1887 | mutex_unlock(&spec->pcm_lock); | |
1888 | return -EINVAL; | |
1889 | } | |
1890 | per_pin = get_pin(spec, pin_idx); | |
1891 | pin_nid = per_pin->pin_nid; | |
4846a67e TI |
1892 | |
1893 | /* Verify pin:cvt selections to avoid silent audio after S3. | |
1894 | * After S3, the audio driver restores pin:cvt selections | |
1895 | * but this can happen before gfx is ready and such selection | |
1896 | * is overlooked by HW. Thus multiple pins can share a same | |
1897 | * default convertor and mute control will affect each other, | |
1898 | * which can cause a resumed audio playback become silent | |
1899 | * after S3. | |
1900 | */ | |
1901 | pin_cvt_fixup(codec, per_pin, 0); | |
2df6742f | 1902 | |
ddd621fb LY |
1903 | /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ |
1904 | /* Todo: add DP1.2 MST audio support later */ | |
93a9ff15 | 1905 | if (codec_has_acomp(codec)) |
9152085d | 1906 | snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id, |
f9318941 | 1907 | runtime->rate); |
ddd621fb | 1908 | |
1a6003b5 | 1909 | non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); |
a4e9a38b | 1910 | mutex_lock(&per_pin->lock); |
b054087d TI |
1911 | per_pin->channels = substream->runtime->channels; |
1912 | per_pin->setup = true; | |
384a48d7 | 1913 | |
b054087d | 1914 | hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); |
a4e9a38b | 1915 | mutex_unlock(&per_pin->lock); |
75fae117 SW |
1916 | if (spec->dyn_pin_out) { |
1917 | pinctl = snd_hda_codec_read(codec, pin_nid, 0, | |
1918 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
1919 | snd_hda_codec_write(codec, pin_nid, 0, | |
1920 | AC_VERB_SET_PIN_WIDGET_CONTROL, | |
1921 | pinctl | PIN_OUT); | |
1922 | } | |
1923 | ||
9152085d | 1924 | /* snd_hda_set_dev_select() has been called before */ |
42b29870 LY |
1925 | err = spec->ops.setup_stream(codec, cvt_nid, pin_nid, |
1926 | stream_tag, format); | |
1927 | mutex_unlock(&spec->pcm_lock); | |
1928 | return err; | |
84eb01be TI |
1929 | } |
1930 | ||
8dfaa573 TI |
1931 | static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, |
1932 | struct hda_codec *codec, | |
1933 | struct snd_pcm_substream *substream) | |
1934 | { | |
1935 | snd_hda_codec_cleanup_stream(codec, hinfo->nid); | |
1936 | return 0; | |
1937 | } | |
1938 | ||
f2ad24fa TI |
1939 | static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, |
1940 | struct hda_codec *codec, | |
1941 | struct snd_pcm_substream *substream) | |
384a48d7 SW |
1942 | { |
1943 | struct hdmi_spec *spec = codec->spec; | |
2bf3c85a | 1944 | int cvt_idx, pin_idx, pcm_idx; |
384a48d7 SW |
1945 | struct hdmi_spec_per_cvt *per_cvt; |
1946 | struct hdmi_spec_per_pin *per_pin; | |
75fae117 | 1947 | int pinctl; |
384a48d7 | 1948 | |
384a48d7 | 1949 | if (hinfo->nid) { |
2bf3c85a LY |
1950 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1951 | if (snd_BUG_ON(pcm_idx < 0)) | |
1952 | return -EINVAL; | |
4e76a883 | 1953 | cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); |
384a48d7 SW |
1954 | if (snd_BUG_ON(cvt_idx < 0)) |
1955 | return -EINVAL; | |
bce0d2a8 | 1956 | per_cvt = get_cvt(spec, cvt_idx); |
384a48d7 SW |
1957 | |
1958 | snd_BUG_ON(!per_cvt->assigned); | |
1959 | per_cvt->assigned = 0; | |
1960 | hinfo->nid = 0; | |
1961 | ||
42b29870 | 1962 | mutex_lock(&spec->pcm_lock); |
b09887f8 | 1963 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
ac98379a | 1964 | clear_bit(pcm_idx, &spec->pcm_in_use); |
4e76a883 | 1965 | pin_idx = hinfo_to_pin_index(codec, hinfo); |
42b29870 LY |
1966 | if (spec->dyn_pcm_assign && pin_idx < 0) { |
1967 | mutex_unlock(&spec->pcm_lock); | |
1968 | return 0; | |
1969 | } | |
1970 | ||
1971 | if (snd_BUG_ON(pin_idx < 0)) { | |
1972 | mutex_unlock(&spec->pcm_lock); | |
384a48d7 | 1973 | return -EINVAL; |
42b29870 | 1974 | } |
bce0d2a8 | 1975 | per_pin = get_pin(spec, pin_idx); |
384a48d7 | 1976 | |
75fae117 SW |
1977 | if (spec->dyn_pin_out) { |
1978 | pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, | |
1979 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
1980 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, | |
1981 | AC_VERB_SET_PIN_WIDGET_CONTROL, | |
1982 | pinctl & ~PIN_OUT); | |
1983 | } | |
1984 | ||
a4e9a38b | 1985 | mutex_lock(&per_pin->lock); |
d45e6889 TI |
1986 | per_pin->chmap_set = false; |
1987 | memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); | |
b054087d TI |
1988 | |
1989 | per_pin->setup = false; | |
1990 | per_pin->channels = 0; | |
a4e9a38b | 1991 | mutex_unlock(&per_pin->lock); |
42b29870 | 1992 | mutex_unlock(&spec->pcm_lock); |
384a48d7 | 1993 | } |
d45e6889 | 1994 | |
384a48d7 SW |
1995 | return 0; |
1996 | } | |
1997 | ||
1998 | static const struct hda_pcm_ops generic_ops = { | |
1999 | .open = hdmi_pcm_open, | |
f2ad24fa | 2000 | .close = hdmi_pcm_close, |
384a48d7 | 2001 | .prepare = generic_hdmi_playback_pcm_prepare, |
8dfaa573 | 2002 | .cleanup = generic_hdmi_playback_pcm_cleanup, |
84eb01be TI |
2003 | }; |
2004 | ||
44fde3b8 SP |
2005 | static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) |
2006 | { | |
2007 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2008 | struct hdmi_spec *spec = codec->spec; | |
2009 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2010 | ||
2011 | if (!per_pin) | |
2012 | return 0; | |
2013 | ||
2014 | return per_pin->sink_eld.info.spk_alloc; | |
2015 | } | |
2016 | ||
9b3dc8aa SP |
2017 | static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, |
2018 | unsigned char *chmap) | |
2019 | { | |
2020 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2021 | struct hdmi_spec *spec = codec->spec; | |
2022 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2023 | ||
2024 | /* chmap is already set to 0 in caller */ | |
2025 | if (!per_pin) | |
2026 | return; | |
2027 | ||
2028 | memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); | |
2029 | } | |
2030 | ||
2031 | static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, | |
2032 | unsigned char *chmap, int prepared) | |
2033 | { | |
2034 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2035 | struct hdmi_spec *spec = codec->spec; | |
2036 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2037 | ||
ed0739b5 LY |
2038 | if (!per_pin) |
2039 | return; | |
9b3dc8aa SP |
2040 | mutex_lock(&per_pin->lock); |
2041 | per_pin->chmap_set = true; | |
2042 | memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); | |
2043 | if (prepared) | |
2044 | hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); | |
2045 | mutex_unlock(&per_pin->lock); | |
2046 | } | |
2047 | ||
2048 | static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) | |
2049 | { | |
2050 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2051 | struct hdmi_spec *spec = codec->spec; | |
2052 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2053 | ||
2054 | return per_pin ? true:false; | |
2055 | } | |
2056 | ||
84eb01be TI |
2057 | static int generic_hdmi_build_pcms(struct hda_codec *codec) |
2058 | { | |
2059 | struct hdmi_spec *spec = codec->spec; | |
9152085d | 2060 | int idx; |
84eb01be | 2061 | |
9152085d LY |
2062 | /* |
2063 | * for non-mst mode, pcm number is the same as before | |
2064 | * for DP MST mode, pcm number is (nid number + dev_num - 1) | |
2065 | * dev_num is the device entry number in a pin | |
2066 | * | |
2067 | */ | |
2068 | for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) { | |
384a48d7 | 2069 | struct hda_pcm *info; |
84eb01be | 2070 | struct hda_pcm_stream *pstr; |
bce0d2a8 | 2071 | |
9152085d | 2072 | info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); |
bce0d2a8 TI |
2073 | if (!info) |
2074 | return -ENOMEM; | |
2bea241a | 2075 | |
9152085d | 2076 | spec->pcm_rec[idx].pcm = info; |
2bf3c85a | 2077 | spec->pcm_used++; |
84eb01be | 2078 | info->pcm_type = HDA_PCM_TYPE_HDMI; |
d45e6889 | 2079 | info->own_chmap = true; |
384a48d7 | 2080 | |
84eb01be | 2081 | pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; |
384a48d7 SW |
2082 | pstr->substreams = 1; |
2083 | pstr->ops = generic_ops; | |
9152085d LY |
2084 | /* pcm number is less than 16 */ |
2085 | if (spec->pcm_used >= 16) | |
2086 | break; | |
384a48d7 | 2087 | /* other pstr fields are set in open */ |
84eb01be TI |
2088 | } |
2089 | ||
2090 | return 0; | |
2091 | } | |
2092 | ||
25e4abb3 | 2093 | static void free_hdmi_jack_priv(struct snd_jack *jack) |
788d441a | 2094 | { |
25e4abb3 | 2095 | struct hdmi_pcm *pcm = jack->private_data; |
788d441a | 2096 | |
25e4abb3 | 2097 | pcm->jack = NULL; |
788d441a TI |
2098 | } |
2099 | ||
25e4abb3 LY |
2100 | static int add_hdmi_jack_kctl(struct hda_codec *codec, |
2101 | struct hdmi_spec *spec, | |
2102 | int pcm_idx, | |
788d441a TI |
2103 | const char *name) |
2104 | { | |
2105 | struct snd_jack *jack; | |
2106 | int err; | |
2107 | ||
2108 | err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack, | |
2109 | true, false); | |
2110 | if (err < 0) | |
2111 | return err; | |
25e4abb3 LY |
2112 | |
2113 | spec->pcm_rec[pcm_idx].jack = jack; | |
2114 | jack->private_data = &spec->pcm_rec[pcm_idx]; | |
2115 | jack->private_free = free_hdmi_jack_priv; | |
788d441a TI |
2116 | return 0; |
2117 | } | |
2118 | ||
25e4abb3 | 2119 | static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) |
0b6c49b5 | 2120 | { |
31ef2257 | 2121 | char hdmi_str[32] = "HDMI/DP"; |
0b6c49b5 | 2122 | struct hdmi_spec *spec = codec->spec; |
25e4abb3 LY |
2123 | struct hdmi_spec_per_pin *per_pin; |
2124 | struct hda_jack_tbl *jack; | |
2125 | int pcmdev = get_pcm_rec(spec, pcm_idx)->device; | |
909cadc6 | 2126 | bool phantom_jack; |
25e4abb3 | 2127 | int ret; |
0b6c49b5 | 2128 | |
31ef2257 TI |
2129 | if (pcmdev > 0) |
2130 | sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); | |
25e4abb3 LY |
2131 | |
2132 | if (spec->dyn_pcm_assign) | |
2133 | return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str); | |
2134 | ||
2135 | /* for !dyn_pcm_assign, we still use hda_jack for compatibility */ | |
2136 | /* if !dyn_pcm_assign, it must be non-MST mode. | |
2137 | * This means pcms and pins are statically mapped. | |
2138 | * And pcm_idx is pin_idx. | |
2139 | */ | |
2140 | per_pin = get_pin(spec, pcm_idx); | |
909cadc6 TI |
2141 | phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); |
2142 | if (phantom_jack) | |
30efd8de DH |
2143 | strncat(hdmi_str, " Phantom", |
2144 | sizeof(hdmi_str) - strlen(hdmi_str) - 1); | |
25e4abb3 LY |
2145 | ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, |
2146 | phantom_jack); | |
2147 | if (ret < 0) | |
2148 | return ret; | |
2149 | jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); | |
2150 | if (jack == NULL) | |
2151 | return 0; | |
2152 | /* assign jack->jack to pcm_rec[].jack to | |
2153 | * align with dyn_pcm_assign mode | |
2154 | */ | |
2155 | spec->pcm_rec[pcm_idx].jack = jack->jack; | |
2156 | return 0; | |
0b6c49b5 DH |
2157 | } |
2158 | ||
84eb01be TI |
2159 | static int generic_hdmi_build_controls(struct hda_codec *codec) |
2160 | { | |
2161 | struct hdmi_spec *spec = codec->spec; | |
1f7f51a6 | 2162 | int dev, err; |
25e4abb3 | 2163 | int pin_idx, pcm_idx; |
84eb01be | 2164 | |
25e4abb3 | 2165 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { |
8a7d6003 TI |
2166 | if (!get_pcm_rec(spec, pcm_idx)->pcm) { |
2167 | /* no PCM: mark this for skipping permanently */ | |
2168 | set_bit(pcm_idx, &spec->pcm_bitmap); | |
2169 | continue; | |
2170 | } | |
2171 | ||
25e4abb3 | 2172 | err = generic_hdmi_build_jack(codec, pcm_idx); |
0b6c49b5 DH |
2173 | if (err < 0) |
2174 | return err; | |
2175 | ||
b09887f8 LY |
2176 | /* create the spdif for each pcm |
2177 | * pin will be bound when monitor is connected | |
2178 | */ | |
2179 | if (spec->dyn_pcm_assign) | |
2180 | err = snd_hda_create_dig_out_ctls(codec, | |
2181 | 0, spec->cvt_nids[0], | |
2182 | HDA_PCM_TYPE_HDMI); | |
2183 | else { | |
2184 | struct hdmi_spec_per_pin *per_pin = | |
2185 | get_pin(spec, pcm_idx); | |
2186 | err = snd_hda_create_dig_out_ctls(codec, | |
dcda5806 TI |
2187 | per_pin->pin_nid, |
2188 | per_pin->mux_nids[0], | |
2189 | HDA_PCM_TYPE_HDMI); | |
b09887f8 | 2190 | } |
84eb01be TI |
2191 | if (err < 0) |
2192 | return err; | |
b09887f8 | 2193 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
14bc52b8 | 2194 | |
1f7f51a6 WY |
2195 | dev = get_pcm_rec(spec, pcm_idx)->device; |
2196 | if (dev != SNDRV_PCM_INVALID_DEVICE) { | |
2197 | /* add control for ELD Bytes */ | |
2198 | err = hdmi_create_eld_ctl(codec, pcm_idx, dev); | |
2199 | if (err < 0) | |
2200 | return err; | |
2201 | } | |
fb087eaa LY |
2202 | } |
2203 | ||
2204 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
2205 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
31ef2257 | 2206 | |
82b1d73f | 2207 | hdmi_present_sense(per_pin, 0); |
84eb01be TI |
2208 | } |
2209 | ||
d45e6889 | 2210 | /* add channel maps */ |
022f344b | 2211 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { |
bbbc7e85 | 2212 | struct hda_pcm *pcm; |
2ca320e2 | 2213 | |
022f344b | 2214 | pcm = get_pcm_rec(spec, pcm_idx); |
bbbc7e85 | 2215 | if (!pcm || !pcm->pcm) |
2ca320e2 | 2216 | break; |
2f6e8a85 | 2217 | err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); |
d45e6889 TI |
2218 | if (err < 0) |
2219 | return err; | |
d45e6889 TI |
2220 | } |
2221 | ||
84eb01be TI |
2222 | return 0; |
2223 | } | |
2224 | ||
8b8d654b | 2225 | static int generic_hdmi_init_per_pins(struct hda_codec *codec) |
84eb01be TI |
2226 | { |
2227 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
2228 | int pin_idx; |
2229 | ||
2230 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
bce0d2a8 | 2231 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
84eb01be | 2232 | |
744626da | 2233 | per_pin->codec = codec; |
a4e9a38b | 2234 | mutex_init(&per_pin->lock); |
744626da | 2235 | INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); |
a4e9a38b | 2236 | eld_proc_new(per_pin, pin_idx); |
84eb01be | 2237 | } |
8b8d654b TI |
2238 | return 0; |
2239 | } | |
2240 | ||
2241 | static int generic_hdmi_init(struct hda_codec *codec) | |
2242 | { | |
2243 | struct hdmi_spec *spec = codec->spec; | |
2244 | int pin_idx; | |
2245 | ||
2246 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
bce0d2a8 | 2247 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
8b8d654b | 2248 | hda_nid_t pin_nid = per_pin->pin_nid; |
9152085d | 2249 | int dev_id = per_pin->dev_id; |
8b8d654b | 2250 | |
9152085d | 2251 | snd_hda_set_dev_select(codec, pin_nid, dev_id); |
8b8d654b | 2252 | hdmi_init_pin(codec, pin_nid); |
788d441a TI |
2253 | if (!codec_has_acomp(codec)) |
2254 | snd_hda_jack_detect_enable_callback(codec, pin_nid, | |
2255 | codec->jackpoll_interval > 0 ? | |
2256 | jack_callback : NULL); | |
8b8d654b | 2257 | } |
84eb01be TI |
2258 | return 0; |
2259 | } | |
2260 | ||
bce0d2a8 TI |
2261 | static void hdmi_array_init(struct hdmi_spec *spec, int nums) |
2262 | { | |
2263 | snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); | |
2264 | snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); | |
bce0d2a8 TI |
2265 | } |
2266 | ||
2267 | static void hdmi_array_free(struct hdmi_spec *spec) | |
2268 | { | |
2269 | snd_array_free(&spec->pins); | |
2270 | snd_array_free(&spec->cvts); | |
bce0d2a8 TI |
2271 | } |
2272 | ||
a686632f TI |
2273 | static void generic_spec_free(struct hda_codec *codec) |
2274 | { | |
2275 | struct hdmi_spec *spec = codec->spec; | |
2276 | ||
2277 | if (spec) { | |
2278 | hdmi_array_free(spec); | |
2279 | kfree(spec); | |
2280 | codec->spec = NULL; | |
2281 | } | |
2282 | codec->dp_mst = false; | |
2283 | } | |
2284 | ||
84eb01be TI |
2285 | static void generic_hdmi_free(struct hda_codec *codec) |
2286 | { | |
2287 | struct hdmi_spec *spec = codec->spec; | |
25e4abb3 | 2288 | int pin_idx, pcm_idx; |
384a48d7 | 2289 | |
6603249d | 2290 | if (codec_has_acomp(codec)) |
a57942bf | 2291 | snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); |
25adc137 | 2292 | |
384a48d7 | 2293 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
bce0d2a8 | 2294 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
2f35c630 | 2295 | cancel_delayed_work_sync(&per_pin->work); |
a4e9a38b | 2296 | eld_proc_free(per_pin); |
25e4abb3 LY |
2297 | } |
2298 | ||
2299 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { | |
2300 | if (spec->pcm_rec[pcm_idx].jack == NULL) | |
2301 | continue; | |
2302 | if (spec->dyn_pcm_assign) | |
2303 | snd_device_free(codec->card, | |
2304 | spec->pcm_rec[pcm_idx].jack); | |
2305 | else | |
2306 | spec->pcm_rec[pcm_idx].jack = NULL; | |
384a48d7 | 2307 | } |
84eb01be | 2308 | |
a686632f | 2309 | generic_spec_free(codec); |
84eb01be TI |
2310 | } |
2311 | ||
28cb72e5 WX |
2312 | #ifdef CONFIG_PM |
2313 | static int generic_hdmi_resume(struct hda_codec *codec) | |
2314 | { | |
2315 | struct hdmi_spec *spec = codec->spec; | |
2316 | int pin_idx; | |
2317 | ||
a2833683 | 2318 | codec->patch_ops.init(codec); |
eeecd9d1 | 2319 | regcache_sync(codec->core.regmap); |
28cb72e5 WX |
2320 | |
2321 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
2322 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
2323 | hdmi_present_sense(per_pin, 1); | |
2324 | } | |
2325 | return 0; | |
2326 | } | |
2327 | #endif | |
2328 | ||
fb79e1e0 | 2329 | static const struct hda_codec_ops generic_hdmi_patch_ops = { |
84eb01be TI |
2330 | .init = generic_hdmi_init, |
2331 | .free = generic_hdmi_free, | |
2332 | .build_pcms = generic_hdmi_build_pcms, | |
2333 | .build_controls = generic_hdmi_build_controls, | |
2334 | .unsol_event = hdmi_unsol_event, | |
28cb72e5 WX |
2335 | #ifdef CONFIG_PM |
2336 | .resume = generic_hdmi_resume, | |
2337 | #endif | |
84eb01be TI |
2338 | }; |
2339 | ||
307229d2 AH |
2340 | static const struct hdmi_ops generic_standard_hdmi_ops = { |
2341 | .pin_get_eld = snd_hdmi_get_eld, | |
307229d2 AH |
2342 | .pin_setup_infoframe = hdmi_pin_setup_infoframe, |
2343 | .pin_hbr_setup = hdmi_pin_hbr_setup, | |
2344 | .setup_stream = hdmi_setup_stream, | |
67b90cb8 SP |
2345 | }; |
2346 | ||
a686632f TI |
2347 | /* allocate codec->spec and assign/initialize generic parser ops */ |
2348 | static int alloc_generic_hdmi(struct hda_codec *codec) | |
2349 | { | |
2350 | struct hdmi_spec *spec; | |
2351 | ||
2352 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
2353 | if (!spec) | |
2354 | return -ENOMEM; | |
2355 | ||
2356 | spec->ops = generic_standard_hdmi_ops; | |
9152085d | 2357 | spec->dev_num = 1; /* initialize to 1 */ |
a686632f TI |
2358 | mutex_init(&spec->pcm_lock); |
2359 | snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); | |
2360 | ||
2361 | spec->chmap.ops.get_chmap = hdmi_get_chmap; | |
2362 | spec->chmap.ops.set_chmap = hdmi_set_chmap; | |
2363 | spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; | |
44fde3b8 | 2364 | spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, |
a686632f TI |
2365 | |
2366 | codec->spec = spec; | |
2367 | hdmi_array_init(spec, 4); | |
2368 | ||
2369 | codec->patch_ops = generic_hdmi_patch_ops; | |
2370 | ||
2371 | return 0; | |
2372 | } | |
2373 | ||
2374 | /* generic HDMI parser */ | |
2375 | static int patch_generic_hdmi(struct hda_codec *codec) | |
2376 | { | |
2377 | int err; | |
2378 | ||
2379 | err = alloc_generic_hdmi(codec); | |
2380 | if (err < 0) | |
2381 | return err; | |
2382 | ||
2383 | err = hdmi_parse_codec(codec); | |
2384 | if (err < 0) { | |
2385 | generic_spec_free(codec); | |
2386 | return err; | |
2387 | } | |
2388 | ||
2389 | generic_hdmi_init_per_pins(codec); | |
2390 | return 0; | |
2391 | } | |
2392 | ||
2393 | /* | |
2394 | * Intel codec parsers and helpers | |
2395 | */ | |
2396 | ||
c88d4e84 TI |
2397 | static void intel_haswell_fixup_connect_list(struct hda_codec *codec, |
2398 | hda_nid_t nid) | |
2399 | { | |
2400 | struct hdmi_spec *spec = codec->spec; | |
2401 | hda_nid_t conns[4]; | |
2402 | int nconns; | |
6ffe168f | 2403 | |
c88d4e84 TI |
2404 | nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns)); |
2405 | if (nconns == spec->num_cvts && | |
2406 | !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t))) | |
6ffe168f ML |
2407 | return; |
2408 | ||
c88d4e84 | 2409 | /* override pins connection list */ |
4e76a883 | 2410 | codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid); |
c88d4e84 | 2411 | snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids); |
6ffe168f ML |
2412 | } |
2413 | ||
1611a9c9 | 2414 | #define INTEL_VENDOR_NID 0x08 |
a87a4d23 | 2415 | #define INTEL_GLK_VENDOR_NID 0x0B |
1611a9c9 ML |
2416 | #define INTEL_GET_VENDOR_VERB 0xf81 |
2417 | #define INTEL_SET_VENDOR_VERB 0x781 | |
2418 | #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ | |
2419 | #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ | |
2420 | ||
2421 | static void intel_haswell_enable_all_pins(struct hda_codec *codec, | |
17df3f55 | 2422 | bool update_tree) |
1611a9c9 ML |
2423 | { |
2424 | unsigned int vendor_param; | |
a87a4d23 | 2425 | struct hdmi_spec *spec = codec->spec; |
1611a9c9 | 2426 | |
a87a4d23 | 2427 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
1611a9c9 ML |
2428 | INTEL_GET_VENDOR_VERB, 0); |
2429 | if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) | |
2430 | return; | |
2431 | ||
2432 | vendor_param |= INTEL_EN_ALL_PIN_CVTS; | |
a87a4d23 | 2433 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
1611a9c9 ML |
2434 | INTEL_SET_VENDOR_VERB, vendor_param); |
2435 | if (vendor_param == -1) | |
2436 | return; | |
2437 | ||
17df3f55 TI |
2438 | if (update_tree) |
2439 | snd_hda_codec_update_widgets(codec); | |
1611a9c9 ML |
2440 | } |
2441 | ||
c88d4e84 TI |
2442 | static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) |
2443 | { | |
2444 | unsigned int vendor_param; | |
a87a4d23 | 2445 | struct hdmi_spec *spec = codec->spec; |
c88d4e84 | 2446 | |
a87a4d23 | 2447 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
c88d4e84 TI |
2448 | INTEL_GET_VENDOR_VERB, 0); |
2449 | if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) | |
2450 | return; | |
2451 | ||
2452 | /* enable DP1.2 mode */ | |
2453 | vendor_param |= INTEL_EN_DP12; | |
a551d914 | 2454 | snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); |
a87a4d23 | 2455 | snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, |
c88d4e84 TI |
2456 | INTEL_SET_VENDOR_VERB, vendor_param); |
2457 | } | |
2458 | ||
17df3f55 TI |
2459 | /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. |
2460 | * Otherwise you may get severe h/w communication errors. | |
2461 | */ | |
2462 | static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, | |
2463 | unsigned int power_state) | |
2464 | { | |
2465 | if (power_state == AC_PWRST_D0) { | |
2466 | intel_haswell_enable_all_pins(codec, false); | |
2467 | intel_haswell_fixup_enable_dp12(codec); | |
2468 | } | |
c88d4e84 | 2469 | |
17df3f55 TI |
2470 | snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); |
2471 | snd_hda_codec_set_power_to_all(codec, fg, power_state); | |
2472 | } | |
6ffe168f | 2473 | |
a57942bf TI |
2474 | /* There is a fixed mapping between audio pin node and display port. |
2475 | * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: | |
2476 | * Pin Widget 5 - PORT B (port = 1 in i915 driver) | |
2477 | * Pin Widget 6 - PORT C (port = 2 in i915 driver) | |
2478 | * Pin Widget 7 - PORT D (port = 3 in i915 driver) | |
2479 | * | |
2480 | * on VLV, ILK: | |
2481 | * Pin Widget 4 - PORT B (port = 1 in i915 driver) | |
2482 | * Pin Widget 5 - PORT C (port = 2 in i915 driver) | |
2483 | * Pin Widget 6 - PORT D (port = 3 in i915 driver) | |
2484 | */ | |
2485 | static int intel_base_nid(struct hda_codec *codec) | |
2486 | { | |
2487 | switch (codec->core.vendor_id) { | |
2488 | case 0x80860054: /* ILK */ | |
2489 | case 0x80862804: /* ILK */ | |
2490 | case 0x80862882: /* VLV */ | |
2491 | return 4; | |
2492 | default: | |
2493 | return 5; | |
2494 | } | |
2495 | } | |
2496 | ||
2497 | static int intel_pin2port(void *audio_ptr, int pin_nid) | |
2498 | { | |
2499 | int base_nid = intel_base_nid(audio_ptr); | |
2500 | ||
2501 | if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) | |
2502 | return -1; | |
2503 | return pin_nid - base_nid + 1; /* intel port is 1-based */ | |
2504 | } | |
2505 | ||
f9318941 | 2506 | static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) |
25adc137 DH |
2507 | { |
2508 | struct hda_codec *codec = audio_ptr; | |
7ff652ff | 2509 | int pin_nid; |
9152085d | 2510 | int dev_id = pipe; |
25adc137 | 2511 | |
4f8e4f35 TI |
2512 | /* we assume only from port-B to port-D */ |
2513 | if (port < 1 || port > 3) | |
2514 | return; | |
2515 | ||
a57942bf | 2516 | pin_nid = port + intel_base_nid(codec) - 1; /* intel port is 1-based */ |
7ff652ff | 2517 | |
8ae743e8 TI |
2518 | /* skip notification during system suspend (but not in runtime PM); |
2519 | * the state will be updated at resume | |
2520 | */ | |
2521 | if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) | |
2522 | return; | |
eb399d3c TI |
2523 | /* ditto during suspend/resume process itself */ |
2524 | if (atomic_read(&(codec)->core.in_pm)) | |
2525 | return; | |
8ae743e8 | 2526 | |
bb03ed21 | 2527 | snd_hdac_i915_set_bclk(&codec->bus->core); |
9152085d | 2528 | check_presence_and_report(codec, pin_nid, dev_id); |
25adc137 DH |
2529 | } |
2530 | ||
a686632f TI |
2531 | /* register i915 component pin_eld_notify callback */ |
2532 | static void register_i915_notifier(struct hda_codec *codec) | |
84eb01be | 2533 | { |
a686632f | 2534 | struct hdmi_spec *spec = codec->spec; |
84eb01be | 2535 | |
a686632f | 2536 | spec->use_acomp_notifier = true; |
ae891abe | 2537 | spec->drm_audio_ops.audio_ptr = codec; |
a686632f TI |
2538 | /* intel_audio_codec_enable() or intel_audio_codec_disable() |
2539 | * will call pin_eld_notify with using audio_ptr pointer | |
2540 | * We need make sure audio_ptr is really setup | |
2541 | */ | |
2542 | wmb(); | |
a57942bf | 2543 | spec->drm_audio_ops.pin2port = intel_pin2port; |
ae891abe | 2544 | spec->drm_audio_ops.pin_eld_notify = intel_pin_eld_notify; |
a57942bf | 2545 | snd_hdac_acomp_register_notifier(&codec->bus->core, |
82887c0b | 2546 | &spec->drm_audio_ops); |
a686632f | 2547 | } |
84eb01be | 2548 | |
2c1c9b86 TI |
2549 | /* setup_stream ops override for HSW+ */ |
2550 | static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, | |
2551 | hda_nid_t pin_nid, u32 stream_tag, int format) | |
2552 | { | |
2553 | haswell_verify_D0(codec, cvt_nid, pin_nid); | |
2554 | return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); | |
2555 | } | |
739ffee9 | 2556 | |
4846a67e TI |
2557 | /* pin_cvt_fixup ops override for HSW+ and VLV+ */ |
2558 | static void i915_pin_cvt_fixup(struct hda_codec *codec, | |
2559 | struct hdmi_spec_per_pin *per_pin, | |
2560 | hda_nid_t cvt_nid) | |
2561 | { | |
2562 | if (per_pin) { | |
9152085d LY |
2563 | snd_hda_set_dev_select(codec, per_pin->pin_nid, |
2564 | per_pin->dev_id); | |
4846a67e TI |
2565 | intel_verify_pin_cvt_connect(codec, per_pin); |
2566 | intel_not_share_assigned_cvt(codec, per_pin->pin_nid, | |
9152085d | 2567 | per_pin->dev_id, per_pin->mux_idx); |
4846a67e | 2568 | } else { |
9152085d | 2569 | intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); |
4846a67e TI |
2570 | } |
2571 | } | |
739ffee9 | 2572 | |
43f6c8d9 TI |
2573 | /* precondition and allocation for Intel codecs */ |
2574 | static int alloc_intel_hdmi(struct hda_codec *codec) | |
a686632f | 2575 | { |
43f6c8d9 | 2576 | /* requires i915 binding */ |
a686632f TI |
2577 | if (!codec->bus->core.audio_component) { |
2578 | codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); | |
2579 | return -ENODEV; | |
691be973 | 2580 | } |
55913110 | 2581 | |
43f6c8d9 TI |
2582 | return alloc_generic_hdmi(codec); |
2583 | } | |
2584 | ||
2585 | /* parse and post-process for Intel codecs */ | |
2586 | static int parse_intel_hdmi(struct hda_codec *codec) | |
2587 | { | |
2588 | int err; | |
2589 | ||
2590 | err = hdmi_parse_codec(codec); | |
2591 | if (err < 0) { | |
2592 | generic_spec_free(codec); | |
2593 | return err; | |
2594 | } | |
2595 | ||
2596 | generic_hdmi_init_per_pins(codec); | |
2597 | register_i915_notifier(codec); | |
2598 | return 0; | |
2599 | } | |
2600 | ||
2601 | /* Intel Haswell and onwards; audio component with eld notifier */ | |
2602 | static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid) | |
2603 | { | |
2604 | struct hdmi_spec *spec; | |
2605 | int err; | |
2606 | ||
2607 | err = alloc_intel_hdmi(codec); | |
a686632f TI |
2608 | if (err < 0) |
2609 | return err; | |
2610 | spec = codec->spec; | |
9152085d LY |
2611 | codec->dp_mst = true; |
2612 | spec->dyn_pcm_assign = true; | |
a87a4d23 | 2613 | spec->vendor_nid = vendor_nid; |
6ffe168f | 2614 | |
a686632f TI |
2615 | intel_haswell_enable_all_pins(codec, true); |
2616 | intel_haswell_fixup_enable_dp12(codec); | |
2617 | ||
2618 | /* For Haswell/Broadwell, the controller is also in the power well and | |
2bd1f73f | 2619 | * can cover the codec power request, and so need not set this flag. |
2bd1f73f | 2620 | */ |
a686632f | 2621 | if (!is_haswell(codec) && !is_broadwell(codec)) |
2bd1f73f ML |
2622 | codec->core.link_power_control = 1; |
2623 | ||
a686632f | 2624 | codec->patch_ops.set_power_state = haswell_set_power_state; |
a686632f TI |
2625 | codec->depop_delay = 0; |
2626 | codec->auto_runtime_pm = 1; | |
2627 | ||
2c1c9b86 | 2628 | spec->ops.setup_stream = i915_hsw_setup_stream; |
4846a67e | 2629 | spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; |
2c1c9b86 | 2630 | |
43f6c8d9 | 2631 | return parse_intel_hdmi(codec); |
a686632f TI |
2632 | } |
2633 | ||
a87a4d23 ACDO |
2634 | static int patch_i915_hsw_hdmi(struct hda_codec *codec) |
2635 | { | |
2636 | return intel_hsw_common_init(codec, INTEL_VENDOR_NID); | |
2637 | } | |
2638 | ||
2639 | static int patch_i915_glk_hdmi(struct hda_codec *codec) | |
2640 | { | |
2641 | return intel_hsw_common_init(codec, INTEL_GLK_VENDOR_NID); | |
2642 | } | |
2643 | ||
7ff652ff | 2644 | /* Intel Baytrail and Braswell; with eld notifier */ |
a686632f TI |
2645 | static int patch_i915_byt_hdmi(struct hda_codec *codec) |
2646 | { | |
2647 | struct hdmi_spec *spec; | |
2648 | int err; | |
2649 | ||
43f6c8d9 | 2650 | err = alloc_intel_hdmi(codec); |
a686632f TI |
2651 | if (err < 0) |
2652 | return err; | |
2653 | spec = codec->spec; | |
2377c3c3 | 2654 | |
a686632f TI |
2655 | /* For Valleyview/Cherryview, only the display codec is in the display |
2656 | * power well and can use link_power ops to request/release the power. | |
2657 | */ | |
2658 | codec->core.link_power_control = 1; | |
84eb01be | 2659 | |
a686632f TI |
2660 | codec->depop_delay = 0; |
2661 | codec->auto_runtime_pm = 1; | |
84eb01be | 2662 | |
4846a67e TI |
2663 | spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; |
2664 | ||
43f6c8d9 | 2665 | return parse_intel_hdmi(codec); |
84eb01be TI |
2666 | } |
2667 | ||
7ff652ff | 2668 | /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ |
e85015a3 TI |
2669 | static int patch_i915_cpt_hdmi(struct hda_codec *codec) |
2670 | { | |
e85015a3 TI |
2671 | int err; |
2672 | ||
43f6c8d9 | 2673 | err = alloc_intel_hdmi(codec); |
e85015a3 TI |
2674 | if (err < 0) |
2675 | return err; | |
43f6c8d9 | 2676 | return parse_intel_hdmi(codec); |
84eb01be TI |
2677 | } |
2678 | ||
3aaf8980 SW |
2679 | /* |
2680 | * Shared non-generic implementations | |
2681 | */ | |
2682 | ||
2683 | static int simple_playback_build_pcms(struct hda_codec *codec) | |
2684 | { | |
2685 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 2686 | struct hda_pcm *info; |
8ceb332d TI |
2687 | unsigned int chans; |
2688 | struct hda_pcm_stream *pstr; | |
bce0d2a8 | 2689 | struct hdmi_spec_per_cvt *per_cvt; |
3aaf8980 | 2690 | |
bce0d2a8 TI |
2691 | per_cvt = get_cvt(spec, 0); |
2692 | chans = get_wcaps(codec, per_cvt->cvt_nid); | |
8ceb332d | 2693 | chans = get_wcaps_channels(chans); |
3aaf8980 | 2694 | |
bbbc7e85 | 2695 | info = snd_hda_codec_pcm_new(codec, "HDMI 0"); |
bce0d2a8 TI |
2696 | if (!info) |
2697 | return -ENOMEM; | |
2bea241a | 2698 | spec->pcm_rec[0].pcm = info; |
8ceb332d TI |
2699 | info->pcm_type = HDA_PCM_TYPE_HDMI; |
2700 | pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; | |
2701 | *pstr = spec->pcm_playback; | |
bce0d2a8 | 2702 | pstr->nid = per_cvt->cvt_nid; |
8ceb332d TI |
2703 | if (pstr->channels_max <= 2 && chans && chans <= 16) |
2704 | pstr->channels_max = chans; | |
3aaf8980 SW |
2705 | |
2706 | return 0; | |
2707 | } | |
2708 | ||
4b6ace9e TI |
2709 | /* unsolicited event for jack sensing */ |
2710 | static void simple_hdmi_unsol_event(struct hda_codec *codec, | |
2711 | unsigned int res) | |
2712 | { | |
9dd8cf12 | 2713 | snd_hda_jack_set_dirty_all(codec); |
4b6ace9e TI |
2714 | snd_hda_jack_report_sync(codec); |
2715 | } | |
2716 | ||
2717 | /* generic_hdmi_build_jack can be used for simple_hdmi, too, | |
2718 | * as long as spec->pins[] is set correctly | |
2719 | */ | |
2720 | #define simple_hdmi_build_jack generic_hdmi_build_jack | |
2721 | ||
3aaf8980 SW |
2722 | static int simple_playback_build_controls(struct hda_codec *codec) |
2723 | { | |
2724 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 2725 | struct hdmi_spec_per_cvt *per_cvt; |
3aaf8980 | 2726 | int err; |
3aaf8980 | 2727 | |
bce0d2a8 | 2728 | per_cvt = get_cvt(spec, 0); |
c9a6338a AH |
2729 | err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, |
2730 | per_cvt->cvt_nid, | |
2731 | HDA_PCM_TYPE_HDMI); | |
8ceb332d TI |
2732 | if (err < 0) |
2733 | return err; | |
2734 | return simple_hdmi_build_jack(codec, 0); | |
3aaf8980 SW |
2735 | } |
2736 | ||
4f0110ce TI |
2737 | static int simple_playback_init(struct hda_codec *codec) |
2738 | { | |
2739 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 TI |
2740 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); |
2741 | hda_nid_t pin = per_pin->pin_nid; | |
8ceb332d TI |
2742 | |
2743 | snd_hda_codec_write(codec, pin, 0, | |
2744 | AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); | |
2745 | /* some codecs require to unmute the pin */ | |
2746 | if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) | |
2747 | snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, | |
2748 | AMP_OUT_UNMUTE); | |
62f949bf | 2749 | snd_hda_jack_detect_enable(codec, pin); |
4f0110ce TI |
2750 | return 0; |
2751 | } | |
2752 | ||
3aaf8980 SW |
2753 | static void simple_playback_free(struct hda_codec *codec) |
2754 | { | |
2755 | struct hdmi_spec *spec = codec->spec; | |
2756 | ||
bce0d2a8 | 2757 | hdmi_array_free(spec); |
3aaf8980 SW |
2758 | kfree(spec); |
2759 | } | |
2760 | ||
84eb01be TI |
2761 | /* |
2762 | * Nvidia specific implementations | |
2763 | */ | |
2764 | ||
2765 | #define Nv_VERB_SET_Channel_Allocation 0xF79 | |
2766 | #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A | |
2767 | #define Nv_VERB_SET_Audio_Protection_On 0xF98 | |
2768 | #define Nv_VERB_SET_Audio_Protection_Off 0xF99 | |
2769 | ||
2770 | #define nvhdmi_master_con_nid_7x 0x04 | |
2771 | #define nvhdmi_master_pin_nid_7x 0x05 | |
2772 | ||
fb79e1e0 | 2773 | static const hda_nid_t nvhdmi_con_nids_7x[4] = { |
84eb01be TI |
2774 | /*front, rear, clfe, rear_surr */ |
2775 | 0x6, 0x8, 0xa, 0xc, | |
2776 | }; | |
2777 | ||
ceaa86ba TI |
2778 | static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { |
2779 | /* set audio protect on */ | |
2780 | { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, | |
2781 | /* enable digital output on pin widget */ | |
2782 | { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2783 | {} /* terminator */ | |
2784 | }; | |
2785 | ||
2786 | static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { | |
84eb01be TI |
2787 | /* set audio protect on */ |
2788 | { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, | |
2789 | /* enable digital output on pin widget */ | |
2790 | { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2791 | { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2792 | { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2793 | { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2794 | { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2795 | {} /* terminator */ | |
2796 | }; | |
2797 | ||
2798 | #ifdef LIMITED_RATE_FMT_SUPPORT | |
2799 | /* support only the safe format and rate */ | |
2800 | #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 | |
2801 | #define SUPPORTED_MAXBPS 16 | |
2802 | #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE | |
2803 | #else | |
2804 | /* support all rates and formats */ | |
2805 | #define SUPPORTED_RATES \ | |
2806 | (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ | |
2807 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ | |
2808 | SNDRV_PCM_RATE_192000) | |
2809 | #define SUPPORTED_MAXBPS 24 | |
2810 | #define SUPPORTED_FORMATS \ | |
2811 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
2812 | #endif | |
2813 | ||
ceaa86ba TI |
2814 | static int nvhdmi_7x_init_2ch(struct hda_codec *codec) |
2815 | { | |
2816 | snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); | |
2817 | return 0; | |
2818 | } | |
2819 | ||
2820 | static int nvhdmi_7x_init_8ch(struct hda_codec *codec) | |
84eb01be | 2821 | { |
ceaa86ba | 2822 | snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); |
84eb01be TI |
2823 | return 0; |
2824 | } | |
2825 | ||
50c697ad | 2826 | static const unsigned int channels_2_6_8[] = { |
393004b2 ND |
2827 | 2, 6, 8 |
2828 | }; | |
2829 | ||
50c697ad | 2830 | static const unsigned int channels_2_8[] = { |
393004b2 ND |
2831 | 2, 8 |
2832 | }; | |
2833 | ||
50c697ad | 2834 | static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { |
393004b2 ND |
2835 | .count = ARRAY_SIZE(channels_2_6_8), |
2836 | .list = channels_2_6_8, | |
2837 | .mask = 0, | |
2838 | }; | |
2839 | ||
50c697ad | 2840 | static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { |
393004b2 ND |
2841 | .count = ARRAY_SIZE(channels_2_8), |
2842 | .list = channels_2_8, | |
2843 | .mask = 0, | |
2844 | }; | |
2845 | ||
84eb01be TI |
2846 | static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, |
2847 | struct hda_codec *codec, | |
2848 | struct snd_pcm_substream *substream) | |
2849 | { | |
2850 | struct hdmi_spec *spec = codec->spec; | |
50c697ad | 2851 | const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; |
393004b2 | 2852 | |
b9a94a9c | 2853 | switch (codec->preset->vendor_id) { |
393004b2 ND |
2854 | case 0x10de0002: |
2855 | case 0x10de0003: | |
2856 | case 0x10de0005: | |
2857 | case 0x10de0006: | |
2858 | hw_constraints_channels = &hw_constraints_2_8_channels; | |
2859 | break; | |
2860 | case 0x10de0007: | |
2861 | hw_constraints_channels = &hw_constraints_2_6_8_channels; | |
2862 | break; | |
2863 | default: | |
2864 | break; | |
2865 | } | |
2866 | ||
2867 | if (hw_constraints_channels != NULL) { | |
2868 | snd_pcm_hw_constraint_list(substream->runtime, 0, | |
2869 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
2870 | hw_constraints_channels); | |
ad09fc9d TI |
2871 | } else { |
2872 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
2873 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
393004b2 ND |
2874 | } |
2875 | ||
84eb01be TI |
2876 | return snd_hda_multi_out_dig_open(codec, &spec->multiout); |
2877 | } | |
2878 | ||
2879 | static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, | |
2880 | struct hda_codec *codec, | |
2881 | struct snd_pcm_substream *substream) | |
2882 | { | |
2883 | struct hdmi_spec *spec = codec->spec; | |
2884 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); | |
2885 | } | |
2886 | ||
2887 | static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
2888 | struct hda_codec *codec, | |
2889 | unsigned int stream_tag, | |
2890 | unsigned int format, | |
2891 | struct snd_pcm_substream *substream) | |
2892 | { | |
2893 | struct hdmi_spec *spec = codec->spec; | |
2894 | return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, | |
2895 | stream_tag, format, substream); | |
2896 | } | |
2897 | ||
d0b1252d TI |
2898 | static const struct hda_pcm_stream simple_pcm_playback = { |
2899 | .substreams = 1, | |
2900 | .channels_min = 2, | |
2901 | .channels_max = 2, | |
2902 | .ops = { | |
2903 | .open = simple_playback_pcm_open, | |
2904 | .close = simple_playback_pcm_close, | |
2905 | .prepare = simple_playback_pcm_prepare | |
2906 | }, | |
2907 | }; | |
2908 | ||
2909 | static const struct hda_codec_ops simple_hdmi_patch_ops = { | |
2910 | .build_controls = simple_playback_build_controls, | |
2911 | .build_pcms = simple_playback_build_pcms, | |
2912 | .init = simple_playback_init, | |
2913 | .free = simple_playback_free, | |
250e41ac | 2914 | .unsol_event = simple_hdmi_unsol_event, |
d0b1252d TI |
2915 | }; |
2916 | ||
2917 | static int patch_simple_hdmi(struct hda_codec *codec, | |
2918 | hda_nid_t cvt_nid, hda_nid_t pin_nid) | |
2919 | { | |
2920 | struct hdmi_spec *spec; | |
bce0d2a8 TI |
2921 | struct hdmi_spec_per_cvt *per_cvt; |
2922 | struct hdmi_spec_per_pin *per_pin; | |
d0b1252d TI |
2923 | |
2924 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
2925 | if (!spec) | |
2926 | return -ENOMEM; | |
2927 | ||
2928 | codec->spec = spec; | |
bce0d2a8 | 2929 | hdmi_array_init(spec, 1); |
d0b1252d TI |
2930 | |
2931 | spec->multiout.num_dacs = 0; /* no analog */ | |
2932 | spec->multiout.max_channels = 2; | |
2933 | spec->multiout.dig_out_nid = cvt_nid; | |
2934 | spec->num_cvts = 1; | |
2935 | spec->num_pins = 1; | |
bce0d2a8 TI |
2936 | per_pin = snd_array_new(&spec->pins); |
2937 | per_cvt = snd_array_new(&spec->cvts); | |
2938 | if (!per_pin || !per_cvt) { | |
2939 | simple_playback_free(codec); | |
2940 | return -ENOMEM; | |
2941 | } | |
2942 | per_cvt->cvt_nid = cvt_nid; | |
2943 | per_pin->pin_nid = pin_nid; | |
d0b1252d TI |
2944 | spec->pcm_playback = simple_pcm_playback; |
2945 | ||
2946 | codec->patch_ops = simple_hdmi_patch_ops; | |
2947 | ||
2948 | return 0; | |
2949 | } | |
2950 | ||
1f348522 AP |
2951 | static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, |
2952 | int channels) | |
2953 | { | |
2954 | unsigned int chanmask; | |
2955 | int chan = channels ? (channels - 1) : 1; | |
2956 | ||
2957 | switch (channels) { | |
2958 | default: | |
2959 | case 0: | |
2960 | case 2: | |
2961 | chanmask = 0x00; | |
2962 | break; | |
2963 | case 4: | |
2964 | chanmask = 0x08; | |
2965 | break; | |
2966 | case 6: | |
2967 | chanmask = 0x0b; | |
2968 | break; | |
2969 | case 8: | |
2970 | chanmask = 0x13; | |
2971 | break; | |
2972 | } | |
2973 | ||
2974 | /* Set the audio infoframe channel allocation and checksum fields. The | |
2975 | * channel count is computed implicitly by the hardware. */ | |
2976 | snd_hda_codec_write(codec, 0x1, 0, | |
2977 | Nv_VERB_SET_Channel_Allocation, chanmask); | |
2978 | ||
2979 | snd_hda_codec_write(codec, 0x1, 0, | |
2980 | Nv_VERB_SET_Info_Frame_Checksum, | |
2981 | (0x71 - chan - chanmask)); | |
2982 | } | |
2983 | ||
84eb01be TI |
2984 | static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, |
2985 | struct hda_codec *codec, | |
2986 | struct snd_pcm_substream *substream) | |
2987 | { | |
2988 | struct hdmi_spec *spec = codec->spec; | |
2989 | int i; | |
2990 | ||
2991 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, | |
2992 | 0, AC_VERB_SET_CHANNEL_STREAMID, 0); | |
2993 | for (i = 0; i < 4; i++) { | |
2994 | /* set the stream id */ | |
2995 | snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, | |
2996 | AC_VERB_SET_CHANNEL_STREAMID, 0); | |
2997 | /* set the stream format */ | |
2998 | snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, | |
2999 | AC_VERB_SET_STREAM_FORMAT, 0); | |
3000 | } | |
3001 | ||
1f348522 AP |
3002 | /* The audio hardware sends a channel count of 0x7 (8ch) when all the |
3003 | * streams are disabled. */ | |
3004 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); | |
3005 | ||
84eb01be TI |
3006 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); |
3007 | } | |
3008 | ||
3009 | static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3010 | struct hda_codec *codec, | |
3011 | unsigned int stream_tag, | |
3012 | unsigned int format, | |
3013 | struct snd_pcm_substream *substream) | |
3014 | { | |
3015 | int chs; | |
112daa7a | 3016 | unsigned int dataDCC2, channel_id; |
84eb01be | 3017 | int i; |
7c935976 | 3018 | struct hdmi_spec *spec = codec->spec; |
e3245cdd | 3019 | struct hda_spdif_out *spdif; |
bce0d2a8 | 3020 | struct hdmi_spec_per_cvt *per_cvt; |
84eb01be TI |
3021 | |
3022 | mutex_lock(&codec->spdif_mutex); | |
bce0d2a8 TI |
3023 | per_cvt = get_cvt(spec, 0); |
3024 | spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); | |
84eb01be TI |
3025 | |
3026 | chs = substream->runtime->channels; | |
84eb01be | 3027 | |
84eb01be TI |
3028 | dataDCC2 = 0x2; |
3029 | ||
84eb01be | 3030 | /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ |
7c935976 | 3031 | if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) |
84eb01be TI |
3032 | snd_hda_codec_write(codec, |
3033 | nvhdmi_master_con_nid_7x, | |
3034 | 0, | |
3035 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3036 | spdif->ctls & ~AC_DIG1_ENABLE & 0xff); |
84eb01be TI |
3037 | |
3038 | /* set the stream id */ | |
3039 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, | |
3040 | AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); | |
3041 | ||
3042 | /* set the stream format */ | |
3043 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, | |
3044 | AC_VERB_SET_STREAM_FORMAT, format); | |
3045 | ||
3046 | /* turn on again (if needed) */ | |
3047 | /* enable and set the channel status audio/data flag */ | |
7c935976 | 3048 | if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { |
84eb01be TI |
3049 | snd_hda_codec_write(codec, |
3050 | nvhdmi_master_con_nid_7x, | |
3051 | 0, | |
3052 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3053 | spdif->ctls & 0xff); |
84eb01be TI |
3054 | snd_hda_codec_write(codec, |
3055 | nvhdmi_master_con_nid_7x, | |
3056 | 0, | |
3057 | AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); | |
3058 | } | |
3059 | ||
3060 | for (i = 0; i < 4; i++) { | |
3061 | if (chs == 2) | |
3062 | channel_id = 0; | |
3063 | else | |
3064 | channel_id = i * 2; | |
3065 | ||
3066 | /* turn off SPDIF once; | |
3067 | *otherwise the IEC958 bits won't be updated | |
3068 | */ | |
3069 | if (codec->spdif_status_reset && | |
7c935976 | 3070 | (spdif->ctls & AC_DIG1_ENABLE)) |
84eb01be TI |
3071 | snd_hda_codec_write(codec, |
3072 | nvhdmi_con_nids_7x[i], | |
3073 | 0, | |
3074 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3075 | spdif->ctls & ~AC_DIG1_ENABLE & 0xff); |
84eb01be TI |
3076 | /* set the stream id */ |
3077 | snd_hda_codec_write(codec, | |
3078 | nvhdmi_con_nids_7x[i], | |
3079 | 0, | |
3080 | AC_VERB_SET_CHANNEL_STREAMID, | |
3081 | (stream_tag << 4) | channel_id); | |
3082 | /* set the stream format */ | |
3083 | snd_hda_codec_write(codec, | |
3084 | nvhdmi_con_nids_7x[i], | |
3085 | 0, | |
3086 | AC_VERB_SET_STREAM_FORMAT, | |
3087 | format); | |
3088 | /* turn on again (if needed) */ | |
3089 | /* enable and set the channel status audio/data flag */ | |
3090 | if (codec->spdif_status_reset && | |
7c935976 | 3091 | (spdif->ctls & AC_DIG1_ENABLE)) { |
84eb01be TI |
3092 | snd_hda_codec_write(codec, |
3093 | nvhdmi_con_nids_7x[i], | |
3094 | 0, | |
3095 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3096 | spdif->ctls & 0xff); |
84eb01be TI |
3097 | snd_hda_codec_write(codec, |
3098 | nvhdmi_con_nids_7x[i], | |
3099 | 0, | |
3100 | AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); | |
3101 | } | |
3102 | } | |
3103 | ||
1f348522 | 3104 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); |
84eb01be TI |
3105 | |
3106 | mutex_unlock(&codec->spdif_mutex); | |
3107 | return 0; | |
3108 | } | |
3109 | ||
fb79e1e0 | 3110 | static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { |
84eb01be TI |
3111 | .substreams = 1, |
3112 | .channels_min = 2, | |
3113 | .channels_max = 8, | |
3114 | .nid = nvhdmi_master_con_nid_7x, | |
3115 | .rates = SUPPORTED_RATES, | |
3116 | .maxbps = SUPPORTED_MAXBPS, | |
3117 | .formats = SUPPORTED_FORMATS, | |
3118 | .ops = { | |
3119 | .open = simple_playback_pcm_open, | |
3120 | .close = nvhdmi_8ch_7x_pcm_close, | |
3121 | .prepare = nvhdmi_8ch_7x_pcm_prepare | |
3122 | }, | |
3123 | }; | |
3124 | ||
84eb01be TI |
3125 | static int patch_nvhdmi_2ch(struct hda_codec *codec) |
3126 | { | |
3127 | struct hdmi_spec *spec; | |
d0b1252d TI |
3128 | int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, |
3129 | nvhdmi_master_pin_nid_7x); | |
3130 | if (err < 0) | |
3131 | return err; | |
84eb01be | 3132 | |
ceaa86ba | 3133 | codec->patch_ops.init = nvhdmi_7x_init_2ch; |
d0b1252d TI |
3134 | /* override the PCM rates, etc, as the codec doesn't give full list */ |
3135 | spec = codec->spec; | |
3136 | spec->pcm_playback.rates = SUPPORTED_RATES; | |
3137 | spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; | |
3138 | spec->pcm_playback.formats = SUPPORTED_FORMATS; | |
84eb01be TI |
3139 | return 0; |
3140 | } | |
3141 | ||
53775b0d TI |
3142 | static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) |
3143 | { | |
3144 | struct hdmi_spec *spec = codec->spec; | |
3145 | int err = simple_playback_build_pcms(codec); | |
bce0d2a8 TI |
3146 | if (!err) { |
3147 | struct hda_pcm *info = get_pcm_rec(spec, 0); | |
3148 | info->own_chmap = true; | |
3149 | } | |
53775b0d TI |
3150 | return err; |
3151 | } | |
3152 | ||
3153 | static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) | |
3154 | { | |
3155 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 3156 | struct hda_pcm *info; |
53775b0d TI |
3157 | struct snd_pcm_chmap *chmap; |
3158 | int err; | |
3159 | ||
3160 | err = simple_playback_build_controls(codec); | |
3161 | if (err < 0) | |
3162 | return err; | |
3163 | ||
3164 | /* add channel maps */ | |
bce0d2a8 TI |
3165 | info = get_pcm_rec(spec, 0); |
3166 | err = snd_pcm_add_chmap_ctls(info->pcm, | |
53775b0d TI |
3167 | SNDRV_PCM_STREAM_PLAYBACK, |
3168 | snd_pcm_alt_chmaps, 8, 0, &chmap); | |
3169 | if (err < 0) | |
3170 | return err; | |
b9a94a9c | 3171 | switch (codec->preset->vendor_id) { |
53775b0d TI |
3172 | case 0x10de0002: |
3173 | case 0x10de0003: | |
3174 | case 0x10de0005: | |
3175 | case 0x10de0006: | |
3176 | chmap->channel_mask = (1U << 2) | (1U << 8); | |
3177 | break; | |
3178 | case 0x10de0007: | |
3179 | chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); | |
3180 | } | |
3181 | return 0; | |
3182 | } | |
3183 | ||
84eb01be TI |
3184 | static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) |
3185 | { | |
3186 | struct hdmi_spec *spec; | |
3187 | int err = patch_nvhdmi_2ch(codec); | |
84eb01be TI |
3188 | if (err < 0) |
3189 | return err; | |
3190 | spec = codec->spec; | |
3191 | spec->multiout.max_channels = 8; | |
d0b1252d | 3192 | spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; |
ceaa86ba | 3193 | codec->patch_ops.init = nvhdmi_7x_init_8ch; |
53775b0d TI |
3194 | codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; |
3195 | codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; | |
1f348522 AP |
3196 | |
3197 | /* Initialize the audio infoframe channel mask and checksum to something | |
3198 | * valid */ | |
3199 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); | |
3200 | ||
84eb01be TI |
3201 | return 0; |
3202 | } | |
3203 | ||
611885bc AH |
3204 | /* |
3205 | * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: | |
3206 | * - 0x10de0015 | |
3207 | * - 0x10de0040 | |
3208 | */ | |
67b90cb8 | 3209 | static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, |
f302240d | 3210 | struct hdac_cea_channel_speaker_allocation *cap, int channels) |
611885bc AH |
3211 | { |
3212 | if (cap->ca_index == 0x00 && channels == 2) | |
3213 | return SNDRV_CTL_TLVT_CHMAP_FIXED; | |
3214 | ||
028cb68e SP |
3215 | /* If the speaker allocation matches the channel count, it is OK. */ |
3216 | if (cap->channels != channels) | |
3217 | return -1; | |
3218 | ||
3219 | /* all channels are remappable freely */ | |
3220 | return SNDRV_CTL_TLVT_CHMAP_VAR; | |
611885bc AH |
3221 | } |
3222 | ||
828cb4ed SP |
3223 | static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, |
3224 | int ca, int chs, unsigned char *map) | |
611885bc AH |
3225 | { |
3226 | if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) | |
3227 | return -EINVAL; | |
3228 | ||
3229 | return 0; | |
3230 | } | |
3231 | ||
3232 | static int patch_nvhdmi(struct hda_codec *codec) | |
3233 | { | |
3234 | struct hdmi_spec *spec; | |
3235 | int err; | |
3236 | ||
3237 | err = patch_generic_hdmi(codec); | |
3238 | if (err) | |
3239 | return err; | |
3240 | ||
3241 | spec = codec->spec; | |
75fae117 | 3242 | spec->dyn_pin_out = true; |
611885bc | 3243 | |
67b90cb8 | 3244 | spec->chmap.ops.chmap_cea_alloc_validate_get_type = |
611885bc | 3245 | nvhdmi_chmap_cea_alloc_validate_get_type; |
67b90cb8 | 3246 | spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; |
611885bc AH |
3247 | |
3248 | return 0; | |
3249 | } | |
3250 | ||
26e9a960 TR |
3251 | /* |
3252 | * The HDA codec on NVIDIA Tegra contains two scratch registers that are | |
3253 | * accessed using vendor-defined verbs. These registers can be used for | |
3254 | * interoperability between the HDA and HDMI drivers. | |
3255 | */ | |
3256 | ||
3257 | /* Audio Function Group node */ | |
3258 | #define NVIDIA_AFG_NID 0x01 | |
3259 | ||
3260 | /* | |
3261 | * The SCRATCH0 register is used to notify the HDMI codec of changes in audio | |
3262 | * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to | |
3263 | * be raised in the HDMI codec. The remainder of the bits is arbitrary. This | |
3264 | * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an | |
3265 | * additional bit (at position 30) to signal the validity of the format. | |
3266 | * | |
3267 | * | 31 | 30 | 29 16 | 15 0 | | |
3268 | * +---------+-------+--------+--------+ | |
3269 | * | TRIGGER | VALID | UNUSED | FORMAT | | |
3270 | * +-----------------------------------| | |
3271 | * | |
3272 | * Note that for the trigger bit to take effect it needs to change value | |
3273 | * (i.e. it needs to be toggled). | |
3274 | */ | |
3275 | #define NVIDIA_GET_SCRATCH0 0xfa6 | |
3276 | #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 | |
3277 | #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 | |
3278 | #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 | |
3279 | #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa | |
3280 | #define NVIDIA_SCRATCH_TRIGGER (1 << 7) | |
3281 | #define NVIDIA_SCRATCH_VALID (1 << 6) | |
3282 | ||
3283 | #define NVIDIA_GET_SCRATCH1 0xfab | |
3284 | #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac | |
3285 | #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad | |
3286 | #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae | |
3287 | #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf | |
3288 | ||
3289 | /* | |
3290 | * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, | |
3291 | * the format is invalidated so that the HDMI codec can be disabled. | |
3292 | */ | |
3293 | static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) | |
3294 | { | |
3295 | unsigned int value; | |
3296 | ||
3297 | /* bits [31:30] contain the trigger and valid bits */ | |
3298 | value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, | |
3299 | NVIDIA_GET_SCRATCH0, 0); | |
3300 | value = (value >> 24) & 0xff; | |
3301 | ||
3302 | /* bits [15:0] are used to store the HDA format */ | |
3303 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3304 | NVIDIA_SET_SCRATCH0_BYTE0, | |
3305 | (format >> 0) & 0xff); | |
3306 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3307 | NVIDIA_SET_SCRATCH0_BYTE1, | |
3308 | (format >> 8) & 0xff); | |
3309 | ||
3310 | /* bits [16:24] are unused */ | |
3311 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3312 | NVIDIA_SET_SCRATCH0_BYTE2, 0); | |
3313 | ||
3314 | /* | |
3315 | * Bit 30 signals that the data is valid and hence that HDMI audio can | |
3316 | * be enabled. | |
3317 | */ | |
3318 | if (format == 0) | |
3319 | value &= ~NVIDIA_SCRATCH_VALID; | |
3320 | else | |
3321 | value |= NVIDIA_SCRATCH_VALID; | |
3322 | ||
3323 | /* | |
3324 | * Whenever the trigger bit is toggled, an interrupt is raised in the | |
3325 | * HDMI codec. The HDMI driver will use that as trigger to update its | |
3326 | * configuration. | |
3327 | */ | |
3328 | value ^= NVIDIA_SCRATCH_TRIGGER; | |
3329 | ||
3330 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3331 | NVIDIA_SET_SCRATCH0_BYTE3, value); | |
3332 | } | |
3333 | ||
3334 | static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3335 | struct hda_codec *codec, | |
3336 | unsigned int stream_tag, | |
3337 | unsigned int format, | |
3338 | struct snd_pcm_substream *substream) | |
3339 | { | |
3340 | int err; | |
3341 | ||
3342 | err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, | |
3343 | format, substream); | |
3344 | if (err < 0) | |
3345 | return err; | |
3346 | ||
3347 | /* notify the HDMI codec of the format change */ | |
3348 | tegra_hdmi_set_format(codec, format); | |
3349 | ||
3350 | return 0; | |
3351 | } | |
3352 | ||
3353 | static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, | |
3354 | struct hda_codec *codec, | |
3355 | struct snd_pcm_substream *substream) | |
3356 | { | |
3357 | /* invalidate the format in the HDMI codec */ | |
3358 | tegra_hdmi_set_format(codec, 0); | |
3359 | ||
3360 | return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); | |
3361 | } | |
3362 | ||
3363 | static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) | |
3364 | { | |
3365 | struct hdmi_spec *spec = codec->spec; | |
3366 | unsigned int i; | |
3367 | ||
3368 | for (i = 0; i < spec->num_pins; i++) { | |
3369 | struct hda_pcm *pcm = get_pcm_rec(spec, i); | |
3370 | ||
3371 | if (pcm->pcm_type == type) | |
3372 | return pcm; | |
3373 | } | |
3374 | ||
3375 | return NULL; | |
3376 | } | |
3377 | ||
3378 | static int tegra_hdmi_build_pcms(struct hda_codec *codec) | |
3379 | { | |
3380 | struct hda_pcm_stream *stream; | |
3381 | struct hda_pcm *pcm; | |
3382 | int err; | |
3383 | ||
3384 | err = generic_hdmi_build_pcms(codec); | |
3385 | if (err < 0) | |
3386 | return err; | |
3387 | ||
3388 | pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); | |
3389 | if (!pcm) | |
3390 | return -ENODEV; | |
3391 | ||
3392 | /* | |
3393 | * Override ->prepare() and ->cleanup() operations to notify the HDMI | |
3394 | * codec about format changes. | |
3395 | */ | |
3396 | stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; | |
3397 | stream->ops.prepare = tegra_hdmi_pcm_prepare; | |
3398 | stream->ops.cleanup = tegra_hdmi_pcm_cleanup; | |
3399 | ||
3400 | return 0; | |
3401 | } | |
3402 | ||
3403 | static int patch_tegra_hdmi(struct hda_codec *codec) | |
3404 | { | |
3405 | int err; | |
3406 | ||
3407 | err = patch_generic_hdmi(codec); | |
3408 | if (err) | |
3409 | return err; | |
3410 | ||
3411 | codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; | |
3412 | ||
3413 | return 0; | |
3414 | } | |
3415 | ||
84eb01be | 3416 | /* |
5a613584 | 3417 | * ATI/AMD-specific implementations |
84eb01be TI |
3418 | */ |
3419 | ||
5a613584 | 3420 | #define is_amdhdmi_rev3_or_later(codec) \ |
7639a06c TI |
3421 | ((codec)->core.vendor_id == 0x1002aa01 && \ |
3422 | ((codec)->core.revision_id & 0xff00) >= 0x0300) | |
5a613584 AH |
3423 | #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) |
3424 | ||
3425 | /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ | |
3426 | #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 | |
3427 | #define ATI_VERB_SET_DOWNMIX_INFO 0x772 | |
3428 | #define ATI_VERB_SET_MULTICHANNEL_01 0x777 | |
3429 | #define ATI_VERB_SET_MULTICHANNEL_23 0x778 | |
3430 | #define ATI_VERB_SET_MULTICHANNEL_45 0x779 | |
3431 | #define ATI_VERB_SET_MULTICHANNEL_67 0x77a | |
461cf6b3 | 3432 | #define ATI_VERB_SET_HBR_CONTROL 0x77c |
5a613584 AH |
3433 | #define ATI_VERB_SET_MULTICHANNEL_1 0x785 |
3434 | #define ATI_VERB_SET_MULTICHANNEL_3 0x786 | |
3435 | #define ATI_VERB_SET_MULTICHANNEL_5 0x787 | |
3436 | #define ATI_VERB_SET_MULTICHANNEL_7 0x788 | |
3437 | #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 | |
3438 | #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 | |
3439 | #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 | |
3440 | #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 | |
3441 | #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 | |
3442 | #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 | |
3443 | #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a | |
461cf6b3 | 3444 | #define ATI_VERB_GET_HBR_CONTROL 0xf7c |
5a613584 AH |
3445 | #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 |
3446 | #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 | |
3447 | #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 | |
3448 | #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 | |
3449 | #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 | |
3450 | ||
84d69e79 AH |
3451 | /* AMD specific HDA cvt verbs */ |
3452 | #define ATI_VERB_SET_RAMP_RATE 0x770 | |
3453 | #define ATI_VERB_GET_RAMP_RATE 0xf70 | |
3454 | ||
5a613584 AH |
3455 | #define ATI_OUT_ENABLE 0x1 |
3456 | ||
3457 | #define ATI_MULTICHANNEL_MODE_PAIRED 0 | |
3458 | #define ATI_MULTICHANNEL_MODE_SINGLE 1 | |
3459 | ||
461cf6b3 AH |
3460 | #define ATI_HBR_CAPABLE 0x01 |
3461 | #define ATI_HBR_ENABLE 0x10 | |
3462 | ||
89250f84 AH |
3463 | static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, |
3464 | unsigned char *buf, int *eld_size) | |
3465 | { | |
3466 | /* call hda_eld.c ATI/AMD-specific function */ | |
3467 | return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, | |
3468 | is_amdhdmi_rev3_or_later(codec)); | |
3469 | } | |
3470 | ||
5a613584 AH |
3471 | static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca, |
3472 | int active_channels, int conn_type) | |
3473 | { | |
3474 | snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); | |
3475 | } | |
3476 | ||
3477 | static int atihdmi_paired_swap_fc_lfe(int pos) | |
3478 | { | |
3479 | /* | |
3480 | * ATI/AMD have automatic FC/LFE swap built-in | |
3481 | * when in pairwise mapping mode. | |
3482 | */ | |
3483 | ||
3484 | switch (pos) { | |
3485 | /* see channel_allocations[].speakers[] */ | |
3486 | case 2: return 3; | |
3487 | case 3: return 2; | |
3488 | default: break; | |
3489 | } | |
3490 | ||
3491 | return pos; | |
3492 | } | |
3493 | ||
828cb4ed SP |
3494 | static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, |
3495 | int ca, int chs, unsigned char *map) | |
5a613584 | 3496 | { |
f302240d | 3497 | struct hdac_cea_channel_speaker_allocation *cap; |
5a613584 AH |
3498 | int i, j; |
3499 | ||
3500 | /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ | |
3501 | ||
bb63f726 | 3502 | cap = snd_hdac_get_ch_alloc_from_ca(ca); |
5a613584 | 3503 | for (i = 0; i < chs; ++i) { |
bb63f726 | 3504 | int mask = snd_hdac_chmap_to_spk_mask(map[i]); |
5a613584 AH |
3505 | bool ok = false; |
3506 | bool companion_ok = false; | |
3507 | ||
3508 | if (!mask) | |
3509 | continue; | |
3510 | ||
3511 | for (j = 0 + i % 2; j < 8; j += 2) { | |
3512 | int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); | |
3513 | if (cap->speakers[chan_idx] == mask) { | |
3514 | /* channel is in a supported position */ | |
3515 | ok = true; | |
3516 | ||
3517 | if (i % 2 == 0 && i + 1 < chs) { | |
3518 | /* even channel, check the odd companion */ | |
3519 | int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); | |
bb63f726 | 3520 | int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); |
5a613584 AH |
3521 | int comp_mask_act = cap->speakers[comp_chan_idx]; |
3522 | ||
3523 | if (comp_mask_req == comp_mask_act) | |
3524 | companion_ok = true; | |
3525 | else | |
3526 | return -EINVAL; | |
3527 | } | |
3528 | break; | |
3529 | } | |
3530 | } | |
3531 | ||
3532 | if (!ok) | |
3533 | return -EINVAL; | |
3534 | ||
3535 | if (companion_ok) | |
3536 | i++; /* companion channel already checked */ | |
3537 | } | |
3538 | ||
3539 | return 0; | |
3540 | } | |
3541 | ||
739ffee9 SP |
3542 | static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, |
3543 | hda_nid_t pin_nid, int hdmi_slot, int stream_channel) | |
5a613584 | 3544 | { |
739ffee9 | 3545 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); |
5a613584 AH |
3546 | int verb; |
3547 | int ati_channel_setup = 0; | |
3548 | ||
3549 | if (hdmi_slot > 7) | |
3550 | return -EINVAL; | |
3551 | ||
3552 | if (!has_amd_full_remap_support(codec)) { | |
3553 | hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); | |
3554 | ||
3555 | /* In case this is an odd slot but without stream channel, do not | |
3556 | * disable the slot since the corresponding even slot could have a | |
3557 | * channel. In case neither have a channel, the slot pair will be | |
3558 | * disabled when this function is called for the even slot. */ | |
3559 | if (hdmi_slot % 2 != 0 && stream_channel == 0xf) | |
3560 | return 0; | |
3561 | ||
3562 | hdmi_slot -= hdmi_slot % 2; | |
3563 | ||
3564 | if (stream_channel != 0xf) | |
3565 | stream_channel -= stream_channel % 2; | |
3566 | } | |
3567 | ||
3568 | verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; | |
3569 | ||
3570 | /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ | |
3571 | ||
3572 | if (stream_channel != 0xf) | |
3573 | ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; | |
3574 | ||
3575 | return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); | |
3576 | } | |
3577 | ||
739ffee9 SP |
3578 | static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, |
3579 | hda_nid_t pin_nid, int asp_slot) | |
5a613584 | 3580 | { |
739ffee9 | 3581 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); |
5a613584 AH |
3582 | bool was_odd = false; |
3583 | int ati_asp_slot = asp_slot; | |
3584 | int verb; | |
3585 | int ati_channel_setup; | |
3586 | ||
3587 | if (asp_slot > 7) | |
3588 | return -EINVAL; | |
3589 | ||
3590 | if (!has_amd_full_remap_support(codec)) { | |
3591 | ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); | |
3592 | if (ati_asp_slot % 2 != 0) { | |
3593 | ati_asp_slot -= 1; | |
3594 | was_odd = true; | |
3595 | } | |
3596 | } | |
3597 | ||
3598 | verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; | |
3599 | ||
3600 | ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); | |
3601 | ||
3602 | if (!(ati_channel_setup & ATI_OUT_ENABLE)) | |
3603 | return 0xf; | |
3604 | ||
3605 | return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; | |
3606 | } | |
84eb01be | 3607 | |
67b90cb8 SP |
3608 | static int atihdmi_paired_chmap_cea_alloc_validate_get_type( |
3609 | struct hdac_chmap *chmap, | |
f302240d | 3610 | struct hdac_cea_channel_speaker_allocation *cap, |
67b90cb8 | 3611 | int channels) |
5a613584 AH |
3612 | { |
3613 | int c; | |
3614 | ||
3615 | /* | |
3616 | * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so | |
3617 | * we need to take that into account (a single channel may take 2 | |
3618 | * channel slots if we need to carry a silent channel next to it). | |
3619 | * On Rev3+ AMD codecs this function is not used. | |
3620 | */ | |
3621 | int chanpairs = 0; | |
3622 | ||
3623 | /* We only produce even-numbered channel count TLVs */ | |
3624 | if ((channels % 2) != 0) | |
3625 | return -1; | |
3626 | ||
3627 | for (c = 0; c < 7; c += 2) { | |
3628 | if (cap->speakers[c] || cap->speakers[c+1]) | |
3629 | chanpairs++; | |
3630 | } | |
3631 | ||
3632 | if (chanpairs * 2 != channels) | |
3633 | return -1; | |
3634 | ||
3635 | return SNDRV_CTL_TLVT_CHMAP_PAIRED; | |
3636 | } | |
3637 | ||
828cb4ed | 3638 | static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, |
f302240d SP |
3639 | struct hdac_cea_channel_speaker_allocation *cap, |
3640 | unsigned int *chmap, int channels) | |
5a613584 AH |
3641 | { |
3642 | /* produce paired maps for pre-rev3 ATI/AMD codecs */ | |
3643 | int count = 0; | |
3644 | int c; | |
3645 | ||
3646 | for (c = 7; c >= 0; c--) { | |
3647 | int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); | |
3648 | int spk = cap->speakers[chan]; | |
3649 | if (!spk) { | |
3650 | /* add N/A channel if the companion channel is occupied */ | |
3651 | if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) | |
3652 | chmap[count++] = SNDRV_CHMAP_NA; | |
3653 | ||
3654 | continue; | |
3655 | } | |
3656 | ||
bb63f726 | 3657 | chmap[count++] = snd_hdac_spk_to_chmap(spk); |
5a613584 AH |
3658 | } |
3659 | ||
3660 | WARN_ON(count != channels); | |
3661 | } | |
3662 | ||
461cf6b3 AH |
3663 | static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, |
3664 | bool hbr) | |
3665 | { | |
3666 | int hbr_ctl, hbr_ctl_new; | |
3667 | ||
3668 | hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); | |
13122e6e | 3669 | if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { |
461cf6b3 AH |
3670 | if (hbr) |
3671 | hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; | |
3672 | else | |
3673 | hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; | |
3674 | ||
4e76a883 TI |
3675 | codec_dbg(codec, |
3676 | "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", | |
461cf6b3 AH |
3677 | pin_nid, |
3678 | hbr_ctl == hbr_ctl_new ? "" : "new-", | |
3679 | hbr_ctl_new); | |
3680 | ||
3681 | if (hbr_ctl != hbr_ctl_new) | |
3682 | snd_hda_codec_write(codec, pin_nid, 0, | |
3683 | ATI_VERB_SET_HBR_CONTROL, | |
3684 | hbr_ctl_new); | |
3685 | ||
3686 | } else if (hbr) | |
3687 | return -EINVAL; | |
3688 | ||
3689 | return 0; | |
3690 | } | |
3691 | ||
84d69e79 AH |
3692 | static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, |
3693 | hda_nid_t pin_nid, u32 stream_tag, int format) | |
3694 | { | |
3695 | ||
3696 | if (is_amdhdmi_rev3_or_later(codec)) { | |
3697 | int ramp_rate = 180; /* default as per AMD spec */ | |
3698 | /* disable ramp-up/down for non-pcm as per AMD spec */ | |
3699 | if (format & AC_FMT_TYPE_NON_PCM) | |
3700 | ramp_rate = 0; | |
3701 | ||
3702 | snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); | |
3703 | } | |
3704 | ||
3705 | return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); | |
3706 | } | |
3707 | ||
3708 | ||
5a613584 | 3709 | static int atihdmi_init(struct hda_codec *codec) |
84eb01be TI |
3710 | { |
3711 | struct hdmi_spec *spec = codec->spec; | |
5a613584 | 3712 | int pin_idx, err; |
84eb01be | 3713 | |
5a613584 AH |
3714 | err = generic_hdmi_init(codec); |
3715 | ||
3716 | if (err) | |
84eb01be | 3717 | return err; |
5a613584 AH |
3718 | |
3719 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
3720 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
3721 | ||
3722 | /* make sure downmix information in infoframe is zero */ | |
3723 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); | |
3724 | ||
3725 | /* enable channel-wise remap mode if supported */ | |
3726 | if (has_amd_full_remap_support(codec)) | |
3727 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, | |
3728 | ATI_VERB_SET_MULTICHANNEL_MODE, | |
3729 | ATI_MULTICHANNEL_MODE_SINGLE); | |
84eb01be | 3730 | } |
5a613584 | 3731 | |
84eb01be TI |
3732 | return 0; |
3733 | } | |
3734 | ||
84eb01be TI |
3735 | static int patch_atihdmi(struct hda_codec *codec) |
3736 | { | |
3737 | struct hdmi_spec *spec; | |
5a613584 AH |
3738 | struct hdmi_spec_per_cvt *per_cvt; |
3739 | int err, cvt_idx; | |
3740 | ||
3741 | err = patch_generic_hdmi(codec); | |
3742 | ||
3743 | if (err) | |
d0b1252d | 3744 | return err; |
5a613584 AH |
3745 | |
3746 | codec->patch_ops.init = atihdmi_init; | |
3747 | ||
d0b1252d | 3748 | spec = codec->spec; |
5a613584 | 3749 | |
89250f84 | 3750 | spec->ops.pin_get_eld = atihdmi_pin_get_eld; |
5a613584 | 3751 | spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; |
461cf6b3 | 3752 | spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; |
84d69e79 | 3753 | spec->ops.setup_stream = atihdmi_setup_stream; |
5a613584 | 3754 | |
39669225 TI |
3755 | spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; |
3756 | spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; | |
3757 | ||
5a613584 AH |
3758 | if (!has_amd_full_remap_support(codec)) { |
3759 | /* override to ATI/AMD-specific versions with pairwise mapping */ | |
67b90cb8 | 3760 | spec->chmap.ops.chmap_cea_alloc_validate_get_type = |
5a613584 | 3761 | atihdmi_paired_chmap_cea_alloc_validate_get_type; |
67b90cb8 SP |
3762 | spec->chmap.ops.cea_alloc_to_tlv_chmap = |
3763 | atihdmi_paired_cea_alloc_to_tlv_chmap; | |
3764 | spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; | |
5a613584 AH |
3765 | } |
3766 | ||
3767 | /* ATI/AMD converters do not advertise all of their capabilities */ | |
3768 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
3769 | per_cvt = get_cvt(spec, cvt_idx); | |
3770 | per_cvt->channels_max = max(per_cvt->channels_max, 8u); | |
3771 | per_cvt->rates |= SUPPORTED_RATES; | |
3772 | per_cvt->formats |= SUPPORTED_FORMATS; | |
3773 | per_cvt->maxbps = max(per_cvt->maxbps, 24u); | |
3774 | } | |
3775 | ||
67b90cb8 | 3776 | spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); |
5a613584 | 3777 | |
57cb54e5 TI |
3778 | /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing |
3779 | * the link-down as is. Tell the core to allow it. | |
3780 | */ | |
3781 | codec->link_down_at_suspend = 1; | |
3782 | ||
84eb01be TI |
3783 | return 0; |
3784 | } | |
3785 | ||
3de5ff88 AL |
3786 | /* VIA HDMI Implementation */ |
3787 | #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ | |
3788 | #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ | |
3789 | ||
3de5ff88 AL |
3790 | static int patch_via_hdmi(struct hda_codec *codec) |
3791 | { | |
250e41ac | 3792 | return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); |
3de5ff88 | 3793 | } |
84eb01be TI |
3794 | |
3795 | /* | |
3796 | * patch entries | |
3797 | */ | |
b9a94a9c TI |
3798 | static const struct hda_device_id snd_hda_id_hdmi[] = { |
3799 | HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), | |
3800 | HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), | |
3801 | HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), | |
3802 | HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), | |
3803 | HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), | |
3804 | HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), | |
3805 | HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), | |
74ec1181 | 3806 | HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), |
b9a94a9c TI |
3807 | HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), |
3808 | HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), | |
74ec1181 | 3809 | HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), |
b9a94a9c TI |
3810 | HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), |
3811 | HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), | |
3812 | HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), | |
74ec1181 DD |
3813 | HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi), |
3814 | HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi), | |
b9a94a9c TI |
3815 | HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi), |
3816 | HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi), | |
3817 | HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi), | |
3818 | HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi), | |
3819 | HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi), | |
3820 | HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi), | |
3821 | HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi), | |
3822 | HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi), | |
3823 | HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi), | |
3824 | HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi), | |
3825 | HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi), | |
c8900a0f | 3826 | /* 17 is known to be absent */ |
b9a94a9c TI |
3827 | HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi), |
3828 | HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi), | |
3829 | HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi), | |
3830 | HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi), | |
3831 | HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi), | |
3832 | HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), | |
3833 | HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), | |
3834 | HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), | |
3835 | HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), | |
3836 | HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), | |
3837 | HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), | |
3838 | HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), | |
3839 | HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), | |
3840 | HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), | |
74ec1181 DD |
3841 | HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), |
3842 | HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 3843 | HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), |
74ec1181 | 3844 | HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), |
b9a94a9c | 3845 | HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), |
74ec1181 DD |
3846 | HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), |
3847 | HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), | |
b9a94a9c TI |
3848 | HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), |
3849 | HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), | |
3850 | HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), | |
3851 | HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), | |
74ec1181 DD |
3852 | HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), |
3853 | HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), | |
3854 | HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), | |
3855 | HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), | |
3856 | HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 3857 | HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), |
74ec1181 | 3858 | HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), |
af677166 | 3859 | HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), |
74ec1181 | 3860 | HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), |
2d369c74 | 3861 | HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), |
3ec622f4 | 3862 | HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), |
74ec1181 DD |
3863 | HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), |
3864 | HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), | |
3865 | HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), | |
3866 | HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), | |
3867 | HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), | |
3868 | HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), | |
3869 | HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), | |
3870 | HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), | |
3871 | HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), | |
3872 | HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 3873 | HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), |
74ec1181 | 3874 | HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), |
b9a94a9c TI |
3875 | HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), |
3876 | HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), | |
3877 | HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), | |
3878 | HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), | |
7ff652ff | 3879 | HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), |
b9a94a9c TI |
3880 | HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), |
3881 | HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), | |
3882 | HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), | |
7ff652ff | 3883 | HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), |
e85015a3 TI |
3884 | HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), |
3885 | HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), | |
a686632f TI |
3886 | HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), |
3887 | HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), | |
3888 | HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), | |
3889 | HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), | |
3890 | HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), | |
2b4584d0 | 3891 | HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), |
a87a4d23 | 3892 | HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), |
b9091b1c | 3893 | HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), |
b9a94a9c | 3894 | HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), |
a686632f TI |
3895 | HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), |
3896 | HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), | |
b9a94a9c | 3897 | HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), |
d8a766a1 | 3898 | /* special ID for generic HDMI */ |
b9a94a9c | 3899 | HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), |
84eb01be TI |
3900 | {} /* terminator */ |
3901 | }; | |
b9a94a9c | 3902 | MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); |
84eb01be TI |
3903 | |
3904 | MODULE_LICENSE("GPL"); | |
3905 | MODULE_DESCRIPTION("HDMI HD-audio codec"); | |
3906 | MODULE_ALIAS("snd-hda-codec-intelhdmi"); | |
3907 | MODULE_ALIAS("snd-hda-codec-nvhdmi"); | |
3908 | MODULE_ALIAS("snd-hda-codec-atihdmi"); | |
3909 | ||
d8a766a1 | 3910 | static struct hda_codec_driver hdmi_driver = { |
b9a94a9c | 3911 | .id = snd_hda_id_hdmi, |
84eb01be TI |
3912 | }; |
3913 | ||
d8a766a1 | 3914 | module_hda_codec_driver(hdmi_driver); |