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Commit | Line | Data |
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079d88cc WF |
1 | /* |
2 | * | |
3 | * patch_hdmi.c - routines for HDMI/DisplayPort codecs | |
4 | * | |
5 | * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. | |
84eb01be TI |
6 | * Copyright (c) 2006 ATI Technologies Inc. |
7 | * Copyright (c) 2008 NVIDIA Corp. All rights reserved. | |
8 | * Copyright (c) 2008 Wei Ni <wni@nvidia.com> | |
5a613584 | 9 | * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> |
079d88cc WF |
10 | * |
11 | * Authors: | |
12 | * Wu Fengguang <wfg@linux.intel.com> | |
13 | * | |
14 | * Maintained by: | |
15 | * Wu Fengguang <wfg@linux.intel.com> | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify it | |
18 | * under the terms of the GNU General Public License as published by the Free | |
19 | * Software Foundation; either version 2 of the License, or (at your option) | |
20 | * any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, but | |
23 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
24 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
25 | * for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software Foundation, | |
29 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
30 | */ | |
31 | ||
84eb01be TI |
32 | #include <linux/init.h> |
33 | #include <linux/delay.h> | |
34 | #include <linux/slab.h> | |
65a77217 | 35 | #include <linux/module.h> |
aaa23f86 | 36 | #include <linux/pm_runtime.h> |
84eb01be | 37 | #include <sound/core.h> |
07acecc1 | 38 | #include <sound/jack.h> |
433968da | 39 | #include <sound/asoundef.h> |
d45e6889 | 40 | #include <sound/tlv.h> |
25adc137 DH |
41 | #include <sound/hdaudio.h> |
42 | #include <sound/hda_i915.h> | |
67b90cb8 | 43 | #include <sound/hda_chmap.h> |
be57bfff | 44 | #include <sound/hda_codec.h> |
84eb01be | 45 | #include "hda_local.h" |
1835a0f9 | 46 | #include "hda_jack.h" |
84eb01be | 47 | |
0ebaa24c TI |
48 | static bool static_hdmi_pcm; |
49 | module_param(static_hdmi_pcm, bool, 0644); | |
50 | MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); | |
51 | ||
7639a06c TI |
52 | #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807) |
53 | #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808) | |
54 | #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809) | |
e2656412 | 55 | #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a) |
91815d8a | 56 | #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b) |
b9091b1c SP |
57 | #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \ |
58 | ((codec)->core.vendor_id == 0x80862800)) | |
2b4584d0 | 59 | #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c) |
b0d8bc50 | 60 | #define is_icelake(codec) ((codec)->core.vendor_id == 0x8086280f) |
432ac1a2 | 61 | #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \ |
91815d8a | 62 | || is_skylake(codec) || is_broxton(codec) \ |
b0d8bc50 JK |
63 | || is_kabylake(codec) || is_geminilake(codec) \ |
64 | || is_cannonlake(codec) || is_icelake(codec)) | |
7639a06c TI |
65 | #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882) |
66 | #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883) | |
ca2e7224 | 67 | #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec)) |
fb87fa3a | 68 | |
384a48d7 SW |
69 | struct hdmi_spec_per_cvt { |
70 | hda_nid_t cvt_nid; | |
71 | int assigned; | |
72 | unsigned int channels_min; | |
73 | unsigned int channels_max; | |
74 | u32 rates; | |
75 | u64 formats; | |
76 | unsigned int maxbps; | |
77 | }; | |
079d88cc | 78 | |
4eea3091 TI |
79 | /* max. connections to a widget */ |
80 | #define HDA_MAX_CONNECTIONS 32 | |
81 | ||
384a48d7 SW |
82 | struct hdmi_spec_per_pin { |
83 | hda_nid_t pin_nid; | |
9152085d | 84 | int dev_id; |
a76056f2 LY |
85 | /* pin idx, different device entries on the same pin use the same idx */ |
86 | int pin_nid_idx; | |
384a48d7 SW |
87 | int num_mux_nids; |
88 | hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; | |
2df6742f | 89 | int mux_idx; |
1df5a06a | 90 | hda_nid_t cvt_nid; |
744626da WF |
91 | |
92 | struct hda_codec *codec; | |
384a48d7 | 93 | struct hdmi_eld sink_eld; |
a4e9a38b | 94 | struct mutex lock; |
744626da | 95 | struct delayed_work work; |
2bea241a | 96 | struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ |
a76056f2 | 97 | int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ |
c6e8453e | 98 | int repoll_count; |
b054087d TI |
99 | bool setup; /* the stream has been set up by prepare callback */ |
100 | int channels; /* current number of channels */ | |
1a6003b5 | 101 | bool non_pcm; |
d45e6889 TI |
102 | bool chmap_set; /* channel-map override by ALSA API? */ |
103 | unsigned char chmap[8]; /* ALSA API channel-map */ | |
cd6a6503 | 104 | #ifdef CONFIG_SND_PROC_FS |
a4e9a38b TI |
105 | struct snd_info_entry *proc_entry; |
106 | #endif | |
384a48d7 | 107 | }; |
079d88cc | 108 | |
307229d2 AH |
109 | /* operations used by generic code that can be overridden by patches */ |
110 | struct hdmi_ops { | |
111 | int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, | |
112 | unsigned char *buf, int *eld_size); | |
113 | ||
307229d2 AH |
114 | void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, |
115 | int ca, int active_channels, int conn_type); | |
116 | ||
117 | /* enable/disable HBR (HD passthrough) */ | |
118 | int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr); | |
119 | ||
120 | int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, | |
121 | hda_nid_t pin_nid, u32 stream_tag, int format); | |
122 | ||
4846a67e TI |
123 | void (*pin_cvt_fixup)(struct hda_codec *codec, |
124 | struct hdmi_spec_per_pin *per_pin, | |
125 | hda_nid_t cvt_nid); | |
307229d2 AH |
126 | }; |
127 | ||
2bea241a LY |
128 | struct hdmi_pcm { |
129 | struct hda_pcm *pcm; | |
130 | struct snd_jack *jack; | |
fb087eaa | 131 | struct snd_kcontrol *eld_ctl; |
2bea241a LY |
132 | }; |
133 | ||
384a48d7 SW |
134 | struct hdmi_spec { |
135 | int num_cvts; | |
bce0d2a8 TI |
136 | struct snd_array cvts; /* struct hdmi_spec_per_cvt */ |
137 | hda_nid_t cvt_nids[4]; /* only for haswell fix */ | |
079d88cc | 138 | |
9152085d LY |
139 | /* |
140 | * num_pins is the number of virtual pins | |
141 | * for example, there are 3 pins, and each pin | |
142 | * has 4 device entries, then the num_pins is 12 | |
143 | */ | |
384a48d7 | 144 | int num_pins; |
9152085d LY |
145 | /* |
146 | * num_nids is the number of real pins | |
147 | * In the above example, num_nids is 3 | |
148 | */ | |
149 | int num_nids; | |
150 | /* | |
151 | * dev_num is the number of device entries | |
152 | * on each pin. | |
153 | * In the above example, dev_num is 4 | |
154 | */ | |
155 | int dev_num; | |
bce0d2a8 | 156 | struct snd_array pins; /* struct hdmi_spec_per_pin */ |
2bea241a | 157 | struct hdmi_pcm pcm_rec[16]; |
42b29870 | 158 | struct mutex pcm_lock; |
a76056f2 LY |
159 | /* pcm_bitmap means which pcms have been assigned to pins*/ |
160 | unsigned long pcm_bitmap; | |
2bf3c85a | 161 | int pcm_used; /* counter of pcm_rec[] */ |
ac98379a LY |
162 | /* bitmap shows whether the pcm is opened in user space |
163 | * bit 0 means the first playback PCM (PCM3); | |
164 | * bit 1 means the second playback PCM, and so on. | |
165 | */ | |
166 | unsigned long pcm_in_use; | |
079d88cc | 167 | |
4bd038f9 | 168 | struct hdmi_eld temp_eld; |
307229d2 | 169 | struct hdmi_ops ops; |
75fae117 SW |
170 | |
171 | bool dyn_pin_out; | |
6590faab | 172 | bool dyn_pcm_assign; |
079d88cc | 173 | /* |
5a613584 | 174 | * Non-generic VIA/NVIDIA specific |
079d88cc WF |
175 | */ |
176 | struct hda_multi_out multiout; | |
d0b1252d | 177 | struct hda_pcm_stream pcm_playback; |
25adc137 DH |
178 | |
179 | /* i915/powerwell (Haswell+/Valleyview+) specific */ | |
691be973 | 180 | bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */ |
ae891abe | 181 | struct drm_audio_component_audio_ops drm_audio_ops; |
67b90cb8 SP |
182 | |
183 | struct hdac_chmap chmap; | |
a87a4d23 | 184 | hda_nid_t vendor_nid; |
b0d8bc50 JK |
185 | const int *port_map; |
186 | int port_num; | |
079d88cc WF |
187 | }; |
188 | ||
a57942bf | 189 | #ifdef CONFIG_SND_HDA_COMPONENT |
691be973 TI |
190 | static inline bool codec_has_acomp(struct hda_codec *codec) |
191 | { | |
192 | struct hdmi_spec *spec = codec->spec; | |
193 | return spec->use_acomp_notifier; | |
194 | } | |
f4e3040b TI |
195 | #else |
196 | #define codec_has_acomp(codec) false | |
197 | #endif | |
079d88cc WF |
198 | |
199 | struct hdmi_audio_infoframe { | |
200 | u8 type; /* 0x84 */ | |
201 | u8 ver; /* 0x01 */ | |
202 | u8 len; /* 0x0a */ | |
203 | ||
53d7d69d WF |
204 | u8 checksum; |
205 | ||
079d88cc WF |
206 | u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ |
207 | u8 SS01_SF24; | |
208 | u8 CXT04; | |
209 | u8 CA; | |
210 | u8 LFEPBL01_LSV36_DM_INH7; | |
53d7d69d WF |
211 | }; |
212 | ||
213 | struct dp_audio_infoframe { | |
214 | u8 type; /* 0x84 */ | |
215 | u8 len; /* 0x1b */ | |
216 | u8 ver; /* 0x11 << 2 */ | |
217 | ||
218 | u8 CC02_CT47; /* match with HDMI infoframe from this on */ | |
219 | u8 SS01_SF24; | |
220 | u8 CXT04; | |
221 | u8 CA; | |
222 | u8 LFEPBL01_LSV36_DM_INH7; | |
079d88cc WF |
223 | }; |
224 | ||
2b203dbb TI |
225 | union audio_infoframe { |
226 | struct hdmi_audio_infoframe hdmi; | |
227 | struct dp_audio_infoframe dp; | |
228 | u8 bytes[0]; | |
229 | }; | |
230 | ||
079d88cc WF |
231 | /* |
232 | * HDMI routines | |
233 | */ | |
234 | ||
bce0d2a8 TI |
235 | #define get_pin(spec, idx) \ |
236 | ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) | |
237 | #define get_cvt(spec, idx) \ | |
238 | ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) | |
2bea241a LY |
239 | /* obtain hdmi_pcm object assigned to idx */ |
240 | #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) | |
241 | /* obtain hda_pcm object assigned to idx */ | |
242 | #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) | |
bce0d2a8 | 243 | |
9152085d LY |
244 | static int pin_id_to_pin_index(struct hda_codec *codec, |
245 | hda_nid_t pin_nid, int dev_id) | |
079d88cc | 246 | { |
4e76a883 | 247 | struct hdmi_spec *spec = codec->spec; |
384a48d7 | 248 | int pin_idx; |
9152085d | 249 | struct hdmi_spec_per_pin *per_pin; |
079d88cc | 250 | |
9152085d LY |
251 | /* |
252 | * (dev_id == -1) means it is NON-MST pin | |
253 | * return the first virtual pin on this port | |
254 | */ | |
255 | if (dev_id == -1) | |
256 | dev_id = 0; | |
257 | ||
258 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
259 | per_pin = get_pin(spec, pin_idx); | |
260 | if ((per_pin->pin_nid == pin_nid) && | |
261 | (per_pin->dev_id == dev_id)) | |
384a48d7 | 262 | return pin_idx; |
9152085d | 263 | } |
079d88cc | 264 | |
4e76a883 | 265 | codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); |
384a48d7 SW |
266 | return -EINVAL; |
267 | } | |
268 | ||
2bf3c85a LY |
269 | static int hinfo_to_pcm_index(struct hda_codec *codec, |
270 | struct hda_pcm_stream *hinfo) | |
271 | { | |
272 | struct hdmi_spec *spec = codec->spec; | |
273 | int pcm_idx; | |
274 | ||
275 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) | |
276 | if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) | |
277 | return pcm_idx; | |
278 | ||
279 | codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); | |
280 | return -EINVAL; | |
281 | } | |
282 | ||
4e76a883 | 283 | static int hinfo_to_pin_index(struct hda_codec *codec, |
384a48d7 SW |
284 | struct hda_pcm_stream *hinfo) |
285 | { | |
4e76a883 | 286 | struct hdmi_spec *spec = codec->spec; |
6590faab | 287 | struct hdmi_spec_per_pin *per_pin; |
384a48d7 SW |
288 | int pin_idx; |
289 | ||
6590faab LY |
290 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
291 | per_pin = get_pin(spec, pin_idx); | |
2bea241a LY |
292 | if (per_pin->pcm && |
293 | per_pin->pcm->pcm->stream == hinfo) | |
384a48d7 | 294 | return pin_idx; |
6590faab | 295 | } |
384a48d7 | 296 | |
6590faab | 297 | codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); |
384a48d7 SW |
298 | return -EINVAL; |
299 | } | |
300 | ||
022f344b LY |
301 | static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, |
302 | int pcm_idx) | |
303 | { | |
304 | int i; | |
305 | struct hdmi_spec_per_pin *per_pin; | |
306 | ||
307 | for (i = 0; i < spec->num_pins; i++) { | |
308 | per_pin = get_pin(spec, i); | |
309 | if (per_pin->pcm_idx == pcm_idx) | |
310 | return per_pin; | |
311 | } | |
312 | return NULL; | |
313 | } | |
314 | ||
4e76a883 | 315 | static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) |
384a48d7 | 316 | { |
4e76a883 | 317 | struct hdmi_spec *spec = codec->spec; |
384a48d7 SW |
318 | int cvt_idx; |
319 | ||
320 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) | |
bce0d2a8 | 321 | if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) |
384a48d7 SW |
322 | return cvt_idx; |
323 | ||
4e76a883 | 324 | codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); |
079d88cc WF |
325 | return -EINVAL; |
326 | } | |
327 | ||
14bc52b8 PLB |
328 | static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, |
329 | struct snd_ctl_elem_info *uinfo) | |
330 | { | |
331 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
68e03de9 | 332 | struct hdmi_spec *spec = codec->spec; |
a4e9a38b | 333 | struct hdmi_spec_per_pin *per_pin; |
68e03de9 | 334 | struct hdmi_eld *eld; |
fb087eaa | 335 | int pcm_idx; |
14bc52b8 | 336 | |
14bc52b8 PLB |
337 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; |
338 | ||
fb087eaa LY |
339 | pcm_idx = kcontrol->private_value; |
340 | mutex_lock(&spec->pcm_lock); | |
341 | per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
342 | if (!per_pin) { | |
343 | /* no pin is bound to the pcm */ | |
344 | uinfo->count = 0; | |
f69548ff | 345 | goto unlock; |
fb087eaa | 346 | } |
a4e9a38b | 347 | eld = &per_pin->sink_eld; |
68e03de9 | 348 | uinfo->count = eld->eld_valid ? eld->eld_size : 0; |
14bc52b8 | 349 | |
f69548ff TI |
350 | unlock: |
351 | mutex_unlock(&spec->pcm_lock); | |
14bc52b8 PLB |
352 | return 0; |
353 | } | |
354 | ||
355 | static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, | |
356 | struct snd_ctl_elem_value *ucontrol) | |
357 | { | |
358 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
68e03de9 | 359 | struct hdmi_spec *spec = codec->spec; |
a4e9a38b | 360 | struct hdmi_spec_per_pin *per_pin; |
68e03de9 | 361 | struct hdmi_eld *eld; |
fb087eaa | 362 | int pcm_idx; |
f69548ff | 363 | int err = 0; |
14bc52b8 | 364 | |
fb087eaa LY |
365 | pcm_idx = kcontrol->private_value; |
366 | mutex_lock(&spec->pcm_lock); | |
367 | per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
368 | if (!per_pin) { | |
369 | /* no pin is bound to the pcm */ | |
370 | memset(ucontrol->value.bytes.data, 0, | |
371 | ARRAY_SIZE(ucontrol->value.bytes.data)); | |
f69548ff | 372 | goto unlock; |
fb087eaa | 373 | } |
68e03de9 | 374 | |
f69548ff | 375 | eld = &per_pin->sink_eld; |
360a8245 DH |
376 | if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || |
377 | eld->eld_size > ELD_MAX_SIZE) { | |
68e03de9 | 378 | snd_BUG(); |
f69548ff TI |
379 | err = -EINVAL; |
380 | goto unlock; | |
68e03de9 DH |
381 | } |
382 | ||
383 | memset(ucontrol->value.bytes.data, 0, | |
384 | ARRAY_SIZE(ucontrol->value.bytes.data)); | |
385 | if (eld->eld_valid) | |
386 | memcpy(ucontrol->value.bytes.data, eld->eld_buffer, | |
387 | eld->eld_size); | |
14bc52b8 | 388 | |
f69548ff TI |
389 | unlock: |
390 | mutex_unlock(&spec->pcm_lock); | |
391 | return err; | |
14bc52b8 PLB |
392 | } |
393 | ||
f3b827e0 | 394 | static const struct snd_kcontrol_new eld_bytes_ctl = { |
14bc52b8 PLB |
395 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, |
396 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
397 | .name = "ELD", | |
398 | .info = hdmi_eld_ctl_info, | |
399 | .get = hdmi_eld_ctl_get, | |
400 | }; | |
401 | ||
fb087eaa | 402 | static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, |
14bc52b8 PLB |
403 | int device) |
404 | { | |
405 | struct snd_kcontrol *kctl; | |
406 | struct hdmi_spec *spec = codec->spec; | |
407 | int err; | |
408 | ||
409 | kctl = snd_ctl_new1(&eld_bytes_ctl, codec); | |
410 | if (!kctl) | |
411 | return -ENOMEM; | |
fb087eaa | 412 | kctl->private_value = pcm_idx; |
14bc52b8 PLB |
413 | kctl->id.device = device; |
414 | ||
fb087eaa LY |
415 | /* no pin nid is associated with the kctl now |
416 | * tbd: associate pin nid to eld ctl later | |
417 | */ | |
418 | err = snd_hda_ctl_add(codec, 0, kctl); | |
14bc52b8 PLB |
419 | if (err < 0) |
420 | return err; | |
421 | ||
fb087eaa | 422 | get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; |
14bc52b8 PLB |
423 | return 0; |
424 | } | |
425 | ||
079d88cc WF |
426 | #ifdef BE_PARANOID |
427 | static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, | |
428 | int *packet_index, int *byte_index) | |
429 | { | |
430 | int val; | |
431 | ||
432 | val = snd_hda_codec_read(codec, pin_nid, 0, | |
433 | AC_VERB_GET_HDMI_DIP_INDEX, 0); | |
434 | ||
435 | *packet_index = val >> 5; | |
436 | *byte_index = val & 0x1f; | |
437 | } | |
438 | #endif | |
439 | ||
440 | static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, | |
441 | int packet_index, int byte_index) | |
442 | { | |
443 | int val; | |
444 | ||
445 | val = (packet_index << 5) | (byte_index & 0x1f); | |
446 | ||
447 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); | |
448 | } | |
449 | ||
450 | static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, | |
451 | unsigned char val) | |
452 | { | |
453 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); | |
454 | } | |
455 | ||
384a48d7 | 456 | static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) |
079d88cc | 457 | { |
75fae117 SW |
458 | struct hdmi_spec *spec = codec->spec; |
459 | int pin_out; | |
460 | ||
079d88cc WF |
461 | /* Unmute */ |
462 | if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) | |
463 | snd_hda_codec_write(codec, pin_nid, 0, | |
464 | AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); | |
75fae117 SW |
465 | |
466 | if (spec->dyn_pin_out) | |
467 | /* Disable pin out until stream is active */ | |
468 | pin_out = 0; | |
469 | else | |
470 | /* Enable pin out: some machines with GM965 gets broken output | |
471 | * when the pin is disabled or changed while using with HDMI | |
472 | */ | |
473 | pin_out = PIN_OUT; | |
474 | ||
079d88cc | 475 | snd_hda_codec_write(codec, pin_nid, 0, |
75fae117 | 476 | AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); |
079d88cc WF |
477 | } |
478 | ||
a4e9a38b TI |
479 | /* |
480 | * ELD proc files | |
481 | */ | |
482 | ||
cd6a6503 | 483 | #ifdef CONFIG_SND_PROC_FS |
a4e9a38b TI |
484 | static void print_eld_info(struct snd_info_entry *entry, |
485 | struct snd_info_buffer *buffer) | |
486 | { | |
487 | struct hdmi_spec_per_pin *per_pin = entry->private_data; | |
488 | ||
489 | mutex_lock(&per_pin->lock); | |
490 | snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); | |
491 | mutex_unlock(&per_pin->lock); | |
492 | } | |
493 | ||
494 | static void write_eld_info(struct snd_info_entry *entry, | |
495 | struct snd_info_buffer *buffer) | |
496 | { | |
497 | struct hdmi_spec_per_pin *per_pin = entry->private_data; | |
498 | ||
499 | mutex_lock(&per_pin->lock); | |
500 | snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); | |
501 | mutex_unlock(&per_pin->lock); | |
502 | } | |
503 | ||
504 | static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) | |
505 | { | |
506 | char name[32]; | |
507 | struct hda_codec *codec = per_pin->codec; | |
508 | struct snd_info_entry *entry; | |
509 | int err; | |
510 | ||
511 | snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); | |
6efdd851 | 512 | err = snd_card_proc_new(codec->card, name, &entry); |
a4e9a38b TI |
513 | if (err < 0) |
514 | return err; | |
515 | ||
516 | snd_info_set_text_ops(entry, per_pin, print_eld_info); | |
517 | entry->c.text.write = write_eld_info; | |
6a73cf46 | 518 | entry->mode |= 0200; |
a4e9a38b TI |
519 | per_pin->proc_entry = entry; |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
524 | static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) | |
525 | { | |
1947a114 | 526 | if (!per_pin->codec->bus->shutdown) { |
c560a679 | 527 | snd_info_free_entry(per_pin->proc_entry); |
a4e9a38b TI |
528 | per_pin->proc_entry = NULL; |
529 | } | |
530 | } | |
531 | #else | |
b55447a7 TI |
532 | static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, |
533 | int index) | |
a4e9a38b TI |
534 | { |
535 | return 0; | |
536 | } | |
b55447a7 | 537 | static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) |
a4e9a38b TI |
538 | { |
539 | } | |
540 | #endif | |
079d88cc | 541 | |
079d88cc WF |
542 | /* |
543 | * Audio InfoFrame routines | |
544 | */ | |
545 | ||
546 | /* | |
547 | * Enable Audio InfoFrame Transmission | |
548 | */ | |
549 | static void hdmi_start_infoframe_trans(struct hda_codec *codec, | |
550 | hda_nid_t pin_nid) | |
551 | { | |
552 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
553 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, | |
554 | AC_DIPXMIT_BEST); | |
555 | } | |
556 | ||
557 | /* | |
558 | * Disable Audio InfoFrame Transmission | |
559 | */ | |
560 | static void hdmi_stop_infoframe_trans(struct hda_codec *codec, | |
561 | hda_nid_t pin_nid) | |
562 | { | |
563 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
564 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, | |
565 | AC_DIPXMIT_DISABLE); | |
566 | } | |
567 | ||
568 | static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) | |
569 | { | |
570 | #ifdef CONFIG_SND_DEBUG_VERBOSE | |
571 | int i; | |
572 | int size; | |
573 | ||
574 | size = snd_hdmi_get_eld_size(codec, pin_nid); | |
4e76a883 | 575 | codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); |
079d88cc WF |
576 | |
577 | for (i = 0; i < 8; i++) { | |
578 | size = snd_hda_codec_read(codec, pin_nid, 0, | |
579 | AC_VERB_GET_HDMI_DIP_SIZE, i); | |
4e76a883 | 580 | codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); |
079d88cc WF |
581 | } |
582 | #endif | |
583 | } | |
584 | ||
585 | static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) | |
586 | { | |
587 | #ifdef BE_PARANOID | |
588 | int i, j; | |
589 | int size; | |
590 | int pi, bi; | |
591 | for (i = 0; i < 8; i++) { | |
592 | size = snd_hda_codec_read(codec, pin_nid, 0, | |
593 | AC_VERB_GET_HDMI_DIP_SIZE, i); | |
594 | if (size == 0) | |
595 | continue; | |
596 | ||
597 | hdmi_set_dip_index(codec, pin_nid, i, 0x0); | |
598 | for (j = 1; j < 1000; j++) { | |
599 | hdmi_write_dip_byte(codec, pin_nid, 0x0); | |
600 | hdmi_get_dip_index(codec, pin_nid, &pi, &bi); | |
601 | if (pi != i) | |
4e76a883 | 602 | codec_dbg(codec, "dip index %d: %d != %d\n", |
079d88cc WF |
603 | bi, pi, i); |
604 | if (bi == 0) /* byte index wrapped around */ | |
605 | break; | |
606 | } | |
4e76a883 | 607 | codec_dbg(codec, |
079d88cc WF |
608 | "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", |
609 | i, size, j); | |
610 | } | |
611 | #endif | |
612 | } | |
613 | ||
53d7d69d | 614 | static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) |
079d88cc | 615 | { |
53d7d69d | 616 | u8 *bytes = (u8 *)hdmi_ai; |
079d88cc WF |
617 | u8 sum = 0; |
618 | int i; | |
619 | ||
53d7d69d | 620 | hdmi_ai->checksum = 0; |
079d88cc | 621 | |
53d7d69d | 622 | for (i = 0; i < sizeof(*hdmi_ai); i++) |
079d88cc WF |
623 | sum += bytes[i]; |
624 | ||
53d7d69d | 625 | hdmi_ai->checksum = -sum; |
079d88cc WF |
626 | } |
627 | ||
628 | static void hdmi_fill_audio_infoframe(struct hda_codec *codec, | |
629 | hda_nid_t pin_nid, | |
53d7d69d | 630 | u8 *dip, int size) |
079d88cc | 631 | { |
079d88cc WF |
632 | int i; |
633 | ||
634 | hdmi_debug_dip_size(codec, pin_nid); | |
635 | hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ | |
636 | ||
079d88cc | 637 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); |
53d7d69d WF |
638 | for (i = 0; i < size; i++) |
639 | hdmi_write_dip_byte(codec, pin_nid, dip[i]); | |
079d88cc WF |
640 | } |
641 | ||
642 | static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, | |
53d7d69d | 643 | u8 *dip, int size) |
079d88cc | 644 | { |
079d88cc WF |
645 | u8 val; |
646 | int i; | |
647 | ||
648 | if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) | |
649 | != AC_DIPXMIT_BEST) | |
650 | return false; | |
651 | ||
652 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
53d7d69d | 653 | for (i = 0; i < size; i++) { |
079d88cc WF |
654 | val = snd_hda_codec_read(codec, pin_nid, 0, |
655 | AC_VERB_GET_HDMI_DIP_DATA, 0); | |
53d7d69d | 656 | if (val != dip[i]) |
079d88cc WF |
657 | return false; |
658 | } | |
659 | ||
660 | return true; | |
661 | } | |
662 | ||
307229d2 AH |
663 | static void hdmi_pin_setup_infoframe(struct hda_codec *codec, |
664 | hda_nid_t pin_nid, | |
665 | int ca, int active_channels, | |
666 | int conn_type) | |
667 | { | |
668 | union audio_infoframe ai; | |
669 | ||
caaf5ef9 | 670 | memset(&ai, 0, sizeof(ai)); |
307229d2 AH |
671 | if (conn_type == 0) { /* HDMI */ |
672 | struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; | |
673 | ||
674 | hdmi_ai->type = 0x84; | |
675 | hdmi_ai->ver = 0x01; | |
676 | hdmi_ai->len = 0x0a; | |
677 | hdmi_ai->CC02_CT47 = active_channels - 1; | |
678 | hdmi_ai->CA = ca; | |
679 | hdmi_checksum_audio_infoframe(hdmi_ai); | |
680 | } else if (conn_type == 1) { /* DisplayPort */ | |
681 | struct dp_audio_infoframe *dp_ai = &ai.dp; | |
682 | ||
683 | dp_ai->type = 0x84; | |
684 | dp_ai->len = 0x1b; | |
685 | dp_ai->ver = 0x11 << 2; | |
686 | dp_ai->CC02_CT47 = active_channels - 1; | |
687 | dp_ai->CA = ca; | |
688 | } else { | |
4e76a883 | 689 | codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", |
307229d2 AH |
690 | pin_nid); |
691 | return; | |
692 | } | |
693 | ||
694 | /* | |
695 | * sizeof(ai) is used instead of sizeof(*hdmi_ai) or | |
696 | * sizeof(*dp_ai) to avoid partial match/update problems when | |
697 | * the user switches between HDMI/DP monitors. | |
698 | */ | |
699 | if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, | |
700 | sizeof(ai))) { | |
4e76a883 TI |
701 | codec_dbg(codec, |
702 | "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", | |
307229d2 AH |
703 | pin_nid, |
704 | active_channels, ca); | |
705 | hdmi_stop_infoframe_trans(codec, pin_nid); | |
706 | hdmi_fill_audio_infoframe(codec, pin_nid, | |
707 | ai.bytes, sizeof(ai)); | |
708 | hdmi_start_infoframe_trans(codec, pin_nid); | |
709 | } | |
710 | } | |
711 | ||
b054087d TI |
712 | static void hdmi_setup_audio_infoframe(struct hda_codec *codec, |
713 | struct hdmi_spec_per_pin *per_pin, | |
714 | bool non_pcm) | |
079d88cc | 715 | { |
307229d2 | 716 | struct hdmi_spec *spec = codec->spec; |
739ffee9 | 717 | struct hdac_chmap *chmap = &spec->chmap; |
384a48d7 | 718 | hda_nid_t pin_nid = per_pin->pin_nid; |
b054087d | 719 | int channels = per_pin->channels; |
1df5a06a | 720 | int active_channels; |
384a48d7 | 721 | struct hdmi_eld *eld; |
828cb4ed | 722 | int ca; |
079d88cc | 723 | |
b054087d TI |
724 | if (!channels) |
725 | return; | |
726 | ||
44bb6d0c TI |
727 | /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ |
728 | if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) | |
58f7d28d ML |
729 | snd_hda_codec_write(codec, pin_nid, 0, |
730 | AC_VERB_SET_AMP_GAIN_MUTE, | |
731 | AMP_OUT_UNMUTE); | |
732 | ||
bce0d2a8 | 733 | eld = &per_pin->sink_eld; |
079d88cc | 734 | |
bb63f726 | 735 | ca = snd_hdac_channel_allocation(&codec->core, |
828cb4ed SP |
736 | eld->info.spk_alloc, channels, |
737 | per_pin->chmap_set, non_pcm, per_pin->chmap); | |
384a48d7 | 738 | |
bb63f726 | 739 | active_channels = snd_hdac_get_active_channels(ca); |
1df5a06a | 740 | |
739ffee9 SP |
741 | chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, |
742 | active_channels); | |
1df5a06a | 743 | |
39edac70 AH |
744 | /* |
745 | * always configure channel mapping, it may have been changed by the | |
746 | * user in the meantime | |
747 | */ | |
bb63f726 | 748 | snd_hdac_setup_channel_mapping(&spec->chmap, |
828cb4ed SP |
749 | pin_nid, non_pcm, ca, channels, |
750 | per_pin->chmap, per_pin->chmap_set); | |
39edac70 | 751 | |
307229d2 AH |
752 | spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels, |
753 | eld->info.conn_type); | |
433968da | 754 | |
1a6003b5 | 755 | per_pin->non_pcm = non_pcm; |
079d88cc WF |
756 | } |
757 | ||
079d88cc WF |
758 | /* |
759 | * Unsolicited events | |
760 | */ | |
761 | ||
efe47108 | 762 | static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); |
38faddb1 | 763 | |
9152085d LY |
764 | static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, |
765 | int dev_id) | |
079d88cc WF |
766 | { |
767 | struct hdmi_spec *spec = codec->spec; | |
9152085d | 768 | int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); |
1a4f69d5 | 769 | |
20ce9029 DH |
770 | if (pin_idx < 0) |
771 | return; | |
aaa23f86 | 772 | mutex_lock(&spec->pcm_lock); |
20ce9029 DH |
773 | if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) |
774 | snd_hda_jack_report_sync(codec); | |
aaa23f86 | 775 | mutex_unlock(&spec->pcm_lock); |
20ce9029 DH |
776 | } |
777 | ||
1a4f69d5 TI |
778 | static void jack_callback(struct hda_codec *codec, |
779 | struct hda_jack_callback *jack) | |
780 | { | |
9152085d LY |
781 | /* hda_jack don't support DP MST */ |
782 | check_presence_and_report(codec, jack->nid, 0); | |
1a4f69d5 TI |
783 | } |
784 | ||
20ce9029 DH |
785 | static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) |
786 | { | |
3a93897e | 787 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; |
3a93897e | 788 | struct hda_jack_tbl *jack; |
2e59e5ab | 789 | int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; |
3a93897e | 790 | |
9152085d LY |
791 | /* |
792 | * assume DP MST uses dyn_pcm_assign and acomp and | |
793 | * never comes here | |
794 | * if DP MST supports unsol event, below code need | |
795 | * consider dev_entry | |
796 | */ | |
3a93897e TI |
797 | jack = snd_hda_jack_tbl_get_from_tag(codec, tag); |
798 | if (!jack) | |
799 | return; | |
3a93897e | 800 | jack->jack_dirty = 1; |
079d88cc | 801 | |
4e76a883 | 802 | codec_dbg(codec, |
2e59e5ab | 803 | "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", |
20ce9029 | 804 | codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA), |
fae3d88a | 805 | !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); |
079d88cc | 806 | |
9152085d LY |
807 | /* hda_jack don't support DP MST */ |
808 | check_presence_and_report(codec, jack->nid, 0); | |
079d88cc WF |
809 | } |
810 | ||
811 | static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) | |
812 | { | |
813 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; | |
814 | int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; | |
815 | int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); | |
816 | int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); | |
817 | ||
4e76a883 | 818 | codec_info(codec, |
e9ea8e8f | 819 | "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", |
384a48d7 | 820 | codec->addr, |
079d88cc WF |
821 | tag, |
822 | subtag, | |
823 | cp_state, | |
824 | cp_ready); | |
825 | ||
826 | /* TODO */ | |
827 | if (cp_state) | |
828 | ; | |
829 | if (cp_ready) | |
830 | ; | |
831 | } | |
832 | ||
833 | ||
834 | static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) | |
835 | { | |
079d88cc WF |
836 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; |
837 | int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; | |
838 | ||
3a93897e | 839 | if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) { |
4e76a883 | 840 | codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); |
079d88cc WF |
841 | return; |
842 | } | |
843 | ||
844 | if (subtag == 0) | |
845 | hdmi_intrinsic_event(codec, res); | |
846 | else | |
847 | hdmi_non_intrinsic_event(codec, res); | |
848 | } | |
849 | ||
58f7d28d | 850 | static void haswell_verify_D0(struct hda_codec *codec, |
53b434f0 | 851 | hda_nid_t cvt_nid, hda_nid_t nid) |
83f26ad2 | 852 | { |
58f7d28d | 853 | int pwr; |
83f26ad2 | 854 | |
53b434f0 WX |
855 | /* For Haswell, the converter 1/2 may keep in D3 state after bootup, |
856 | * thus pins could only choose converter 0 for use. Make sure the | |
857 | * converters are in correct power state */ | |
fd678cac | 858 | if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) |
53b434f0 WX |
859 | snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); |
860 | ||
fd678cac | 861 | if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { |
83f26ad2 DH |
862 | snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, |
863 | AC_PWRST_D0); | |
864 | msleep(40); | |
865 | pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); | |
866 | pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; | |
4e76a883 | 867 | codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); |
83f26ad2 | 868 | } |
83f26ad2 DH |
869 | } |
870 | ||
079d88cc WF |
871 | /* |
872 | * Callbacks | |
873 | */ | |
874 | ||
92f10b3f TI |
875 | /* HBR should be Non-PCM, 8 channels */ |
876 | #define is_hbr_format(format) \ | |
877 | ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) | |
878 | ||
307229d2 AH |
879 | static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, |
880 | bool hbr) | |
079d88cc | 881 | { |
307229d2 | 882 | int pinctl, new_pinctl; |
83f26ad2 | 883 | |
384a48d7 SW |
884 | if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { |
885 | pinctl = snd_hda_codec_read(codec, pin_nid, 0, | |
ea87d1c4 AH |
886 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); |
887 | ||
13122e6e AH |
888 | if (pinctl < 0) |
889 | return hbr ? -EINVAL : 0; | |
890 | ||
ea87d1c4 | 891 | new_pinctl = pinctl & ~AC_PINCTL_EPT; |
307229d2 | 892 | if (hbr) |
ea87d1c4 AH |
893 | new_pinctl |= AC_PINCTL_EPT_HBR; |
894 | else | |
895 | new_pinctl |= AC_PINCTL_EPT_NATIVE; | |
896 | ||
4e76a883 TI |
897 | codec_dbg(codec, |
898 | "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", | |
384a48d7 | 899 | pin_nid, |
ea87d1c4 AH |
900 | pinctl == new_pinctl ? "" : "new-", |
901 | new_pinctl); | |
902 | ||
903 | if (pinctl != new_pinctl) | |
384a48d7 | 904 | snd_hda_codec_write(codec, pin_nid, 0, |
ea87d1c4 AH |
905 | AC_VERB_SET_PIN_WIDGET_CONTROL, |
906 | new_pinctl); | |
307229d2 AH |
907 | } else if (hbr) |
908 | return -EINVAL; | |
ea87d1c4 | 909 | |
307229d2 AH |
910 | return 0; |
911 | } | |
912 | ||
913 | static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, | |
914 | hda_nid_t pin_nid, u32 stream_tag, int format) | |
915 | { | |
916 | struct hdmi_spec *spec = codec->spec; | |
5a5d718f | 917 | unsigned int param; |
307229d2 AH |
918 | int err; |
919 | ||
307229d2 AH |
920 | err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format)); |
921 | ||
922 | if (err) { | |
4e76a883 | 923 | codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); |
307229d2 | 924 | return err; |
ea87d1c4 | 925 | } |
079d88cc | 926 | |
5a5d718f SP |
927 | if (is_haswell_plus(codec)) { |
928 | ||
929 | /* | |
930 | * on recent platforms IEC Coding Type is required for HBR | |
931 | * support, read current Digital Converter settings and set | |
932 | * ICT bitfield if needed. | |
933 | */ | |
934 | param = snd_hda_codec_read(codec, cvt_nid, 0, | |
935 | AC_VERB_GET_DIGI_CONVERT_1, 0); | |
936 | ||
937 | param = (param >> 16) & ~(AC_DIG3_ICT); | |
938 | ||
939 | /* on recent platforms ICT mode is required for HBR support */ | |
940 | if (is_hbr_format(format)) | |
941 | param |= 0x1; | |
942 | ||
943 | snd_hda_codec_write(codec, cvt_nid, 0, | |
944 | AC_VERB_SET_DIGI_CONVERT_3, param); | |
945 | } | |
946 | ||
384a48d7 | 947 | snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); |
ea87d1c4 | 948 | return 0; |
079d88cc WF |
949 | } |
950 | ||
42b29870 LY |
951 | /* Try to find an available converter |
952 | * If pin_idx is less then zero, just try to find an available converter. | |
953 | * Otherwise, try to find an available converter and get the cvt mux index | |
954 | * of the pin. | |
955 | */ | |
7ef166b8 | 956 | static int hdmi_choose_cvt(struct hda_codec *codec, |
4846a67e | 957 | int pin_idx, int *cvt_id) |
bbbe3390 TI |
958 | { |
959 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 | 960 | struct hdmi_spec_per_pin *per_pin; |
384a48d7 | 961 | struct hdmi_spec_per_cvt *per_cvt = NULL; |
7ef166b8 | 962 | int cvt_idx, mux_idx = 0; |
bbbe3390 | 963 | |
42b29870 LY |
964 | /* pin_idx < 0 means no pin will be bound to the converter */ |
965 | if (pin_idx < 0) | |
966 | per_pin = NULL; | |
967 | else | |
968 | per_pin = get_pin(spec, pin_idx); | |
384a48d7 SW |
969 | |
970 | /* Dynamically assign converter to stream */ | |
971 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
bce0d2a8 | 972 | per_cvt = get_cvt(spec, cvt_idx); |
bbbe3390 | 973 | |
384a48d7 SW |
974 | /* Must not already be assigned */ |
975 | if (per_cvt->assigned) | |
976 | continue; | |
42b29870 LY |
977 | if (per_pin == NULL) |
978 | break; | |
384a48d7 SW |
979 | /* Must be in pin's mux's list of converters */ |
980 | for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) | |
981 | if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) | |
982 | break; | |
983 | /* Not in mux list */ | |
984 | if (mux_idx == per_pin->num_mux_nids) | |
985 | continue; | |
986 | break; | |
987 | } | |
7ef166b8 | 988 | |
384a48d7 SW |
989 | /* No free converters */ |
990 | if (cvt_idx == spec->num_cvts) | |
42b29870 | 991 | return -EBUSY; |
384a48d7 | 992 | |
42b29870 LY |
993 | if (per_pin != NULL) |
994 | per_pin->mux_idx = mux_idx; | |
2df6742f | 995 | |
7ef166b8 WX |
996 | if (cvt_id) |
997 | *cvt_id = cvt_idx; | |
7ef166b8 WX |
998 | |
999 | return 0; | |
1000 | } | |
1001 | ||
2df6742f ML |
1002 | /* Assure the pin select the right convetor */ |
1003 | static void intel_verify_pin_cvt_connect(struct hda_codec *codec, | |
1004 | struct hdmi_spec_per_pin *per_pin) | |
1005 | { | |
1006 | hda_nid_t pin_nid = per_pin->pin_nid; | |
1007 | int mux_idx, curr; | |
1008 | ||
1009 | mux_idx = per_pin->mux_idx; | |
1010 | curr = snd_hda_codec_read(codec, pin_nid, 0, | |
1011 | AC_VERB_GET_CONNECT_SEL, 0); | |
1012 | if (curr != mux_idx) | |
1013 | snd_hda_codec_write_cache(codec, pin_nid, 0, | |
1014 | AC_VERB_SET_CONNECT_SEL, | |
1015 | mux_idx); | |
1016 | } | |
1017 | ||
42b29870 LY |
1018 | /* get the mux index for the converter of the pins |
1019 | * converter's mux index is the same for all pins on Intel platform | |
1020 | */ | |
1021 | static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, | |
1022 | hda_nid_t cvt_nid) | |
1023 | { | |
1024 | int i; | |
1025 | ||
1026 | for (i = 0; i < spec->num_cvts; i++) | |
1027 | if (spec->cvt_nids[i] == cvt_nid) | |
1028 | return i; | |
1029 | return -EINVAL; | |
1030 | } | |
1031 | ||
300016b9 ML |
1032 | /* Intel HDMI workaround to fix audio routing issue: |
1033 | * For some Intel display codecs, pins share the same connection list. | |
1034 | * So a conveter can be selected by multiple pins and playback on any of these | |
1035 | * pins will generate sound on the external display, because audio flows from | |
1036 | * the same converter to the display pipeline. Also muting one pin may make | |
1037 | * other pins have no sound output. | |
1038 | * So this function assures that an assigned converter for a pin is not selected | |
1039 | * by any other pins. | |
1040 | */ | |
1041 | static void intel_not_share_assigned_cvt(struct hda_codec *codec, | |
9152085d LY |
1042 | hda_nid_t pin_nid, |
1043 | int dev_id, int mux_idx) | |
7ef166b8 WX |
1044 | { |
1045 | struct hdmi_spec *spec = codec->spec; | |
7639a06c | 1046 | hda_nid_t nid; |
f82d7d16 ML |
1047 | int cvt_idx, curr; |
1048 | struct hdmi_spec_per_cvt *per_cvt; | |
9152085d LY |
1049 | struct hdmi_spec_per_pin *per_pin; |
1050 | int pin_idx; | |
1051 | ||
1052 | /* configure the pins connections */ | |
1053 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
1054 | int dev_id_saved; | |
1055 | int dev_num; | |
7ef166b8 | 1056 | |
9152085d LY |
1057 | per_pin = get_pin(spec, pin_idx); |
1058 | /* | |
1059 | * pin not connected to monitor | |
1060 | * no need to operate on it | |
1061 | */ | |
1062 | if (!per_pin->pcm) | |
1063 | continue; | |
f82d7d16 | 1064 | |
9152085d LY |
1065 | if ((per_pin->pin_nid == pin_nid) && |
1066 | (per_pin->dev_id == dev_id)) | |
f82d7d16 | 1067 | continue; |
7ef166b8 | 1068 | |
9152085d LY |
1069 | /* |
1070 | * if per_pin->dev_id >= dev_num, | |
1071 | * snd_hda_get_dev_select() will fail, | |
1072 | * and the following operation is unpredictable. | |
1073 | * So skip this situation. | |
1074 | */ | |
1075 | dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; | |
1076 | if (per_pin->dev_id >= dev_num) | |
7ef166b8 WX |
1077 | continue; |
1078 | ||
9152085d LY |
1079 | nid = per_pin->pin_nid; |
1080 | ||
1081 | /* | |
1082 | * Calling this function should not impact | |
1083 | * on the device entry selection | |
1084 | * So let's save the dev id for each pin, | |
1085 | * and restore it when return | |
1086 | */ | |
1087 | dev_id_saved = snd_hda_get_dev_select(codec, nid); | |
1088 | snd_hda_set_dev_select(codec, nid, per_pin->dev_id); | |
f82d7d16 | 1089 | curr = snd_hda_codec_read(codec, nid, 0, |
7ef166b8 | 1090 | AC_VERB_GET_CONNECT_SEL, 0); |
9152085d LY |
1091 | if (curr != mux_idx) { |
1092 | snd_hda_set_dev_select(codec, nid, dev_id_saved); | |
f82d7d16 | 1093 | continue; |
9152085d LY |
1094 | } |
1095 | ||
7ef166b8 | 1096 | |
f82d7d16 ML |
1097 | /* choose an unassigned converter. The conveters in the |
1098 | * connection list are in the same order as in the codec. | |
1099 | */ | |
1100 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
1101 | per_cvt = get_cvt(spec, cvt_idx); | |
1102 | if (!per_cvt->assigned) { | |
4e76a883 TI |
1103 | codec_dbg(codec, |
1104 | "choose cvt %d for pin nid %d\n", | |
f82d7d16 ML |
1105 | cvt_idx, nid); |
1106 | snd_hda_codec_write_cache(codec, nid, 0, | |
7ef166b8 | 1107 | AC_VERB_SET_CONNECT_SEL, |
f82d7d16 ML |
1108 | cvt_idx); |
1109 | break; | |
1110 | } | |
7ef166b8 | 1111 | } |
9152085d | 1112 | snd_hda_set_dev_select(codec, nid, dev_id_saved); |
7ef166b8 WX |
1113 | } |
1114 | } | |
1115 | ||
42b29870 LY |
1116 | /* A wrapper of intel_not_share_asigned_cvt() */ |
1117 | static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, | |
9152085d | 1118 | hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) |
42b29870 LY |
1119 | { |
1120 | int mux_idx; | |
1121 | struct hdmi_spec *spec = codec->spec; | |
1122 | ||
42b29870 LY |
1123 | /* On Intel platform, the mapping of converter nid to |
1124 | * mux index of the pins are always the same. | |
1125 | * The pin nid may be 0, this means all pins will not | |
1126 | * share the converter. | |
1127 | */ | |
1128 | mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); | |
1129 | if (mux_idx >= 0) | |
9152085d | 1130 | intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); |
42b29870 LY |
1131 | } |
1132 | ||
4846a67e TI |
1133 | /* skeleton caller of pin_cvt_fixup ops */ |
1134 | static void pin_cvt_fixup(struct hda_codec *codec, | |
1135 | struct hdmi_spec_per_pin *per_pin, | |
1136 | hda_nid_t cvt_nid) | |
1137 | { | |
1138 | struct hdmi_spec *spec = codec->spec; | |
1139 | ||
1140 | if (spec->ops.pin_cvt_fixup) | |
1141 | spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); | |
1142 | } | |
1143 | ||
42b29870 LY |
1144 | /* called in hdmi_pcm_open when no pin is assigned to the PCM |
1145 | * in dyn_pcm_assign mode. | |
1146 | */ | |
1147 | static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, | |
1148 | struct hda_codec *codec, | |
1149 | struct snd_pcm_substream *substream) | |
1150 | { | |
1151 | struct hdmi_spec *spec = codec->spec; | |
1152 | struct snd_pcm_runtime *runtime = substream->runtime; | |
ac98379a | 1153 | int cvt_idx, pcm_idx; |
42b29870 LY |
1154 | struct hdmi_spec_per_cvt *per_cvt = NULL; |
1155 | int err; | |
1156 | ||
ac98379a LY |
1157 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1158 | if (pcm_idx < 0) | |
1159 | return -EINVAL; | |
1160 | ||
4846a67e | 1161 | err = hdmi_choose_cvt(codec, -1, &cvt_idx); |
42b29870 LY |
1162 | if (err) |
1163 | return err; | |
1164 | ||
1165 | per_cvt = get_cvt(spec, cvt_idx); | |
1166 | per_cvt->assigned = 1; | |
1167 | hinfo->nid = per_cvt->cvt_nid; | |
1168 | ||
4846a67e | 1169 | pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); |
42b29870 | 1170 | |
ac98379a | 1171 | set_bit(pcm_idx, &spec->pcm_in_use); |
42b29870 LY |
1172 | /* todo: setup spdif ctls assign */ |
1173 | ||
1174 | /* Initially set the converter's capabilities */ | |
1175 | hinfo->channels_min = per_cvt->channels_min; | |
1176 | hinfo->channels_max = per_cvt->channels_max; | |
1177 | hinfo->rates = per_cvt->rates; | |
1178 | hinfo->formats = per_cvt->formats; | |
1179 | hinfo->maxbps = per_cvt->maxbps; | |
1180 | ||
1181 | /* Store the updated parameters */ | |
1182 | runtime->hw.channels_min = hinfo->channels_min; | |
1183 | runtime->hw.channels_max = hinfo->channels_max; | |
1184 | runtime->hw.formats = hinfo->formats; | |
1185 | runtime->hw.rates = hinfo->rates; | |
1186 | ||
1187 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1188 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
1189 | return 0; | |
1190 | } | |
1191 | ||
7ef166b8 WX |
1192 | /* |
1193 | * HDA PCM callbacks | |
1194 | */ | |
1195 | static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, | |
1196 | struct hda_codec *codec, | |
1197 | struct snd_pcm_substream *substream) | |
1198 | { | |
1199 | struct hdmi_spec *spec = codec->spec; | |
1200 | struct snd_pcm_runtime *runtime = substream->runtime; | |
4846a67e | 1201 | int pin_idx, cvt_idx, pcm_idx; |
7ef166b8 WX |
1202 | struct hdmi_spec_per_pin *per_pin; |
1203 | struct hdmi_eld *eld; | |
1204 | struct hdmi_spec_per_cvt *per_cvt = NULL; | |
1205 | int err; | |
1206 | ||
1207 | /* Validate hinfo */ | |
2bf3c85a LY |
1208 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1209 | if (pcm_idx < 0) | |
7ef166b8 | 1210 | return -EINVAL; |
2bf3c85a | 1211 | |
42b29870 | 1212 | mutex_lock(&spec->pcm_lock); |
4e76a883 | 1213 | pin_idx = hinfo_to_pin_index(codec, hinfo); |
42b29870 LY |
1214 | if (!spec->dyn_pcm_assign) { |
1215 | if (snd_BUG_ON(pin_idx < 0)) { | |
f69548ff TI |
1216 | err = -EINVAL; |
1217 | goto unlock; | |
42b29870 LY |
1218 | } |
1219 | } else { | |
1220 | /* no pin is assigned to the PCM | |
1221 | * PA need pcm open successfully when probe | |
1222 | */ | |
1223 | if (pin_idx < 0) { | |
1224 | err = hdmi_pcm_open_no_pin(hinfo, codec, substream); | |
f69548ff | 1225 | goto unlock; |
42b29870 LY |
1226 | } |
1227 | } | |
7ef166b8 | 1228 | |
4846a67e | 1229 | err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); |
f69548ff TI |
1230 | if (err < 0) |
1231 | goto unlock; | |
7ef166b8 WX |
1232 | |
1233 | per_cvt = get_cvt(spec, cvt_idx); | |
384a48d7 SW |
1234 | /* Claim converter */ |
1235 | per_cvt->assigned = 1; | |
42b29870 | 1236 | |
ac98379a | 1237 | set_bit(pcm_idx, &spec->pcm_in_use); |
42b29870 | 1238 | per_pin = get_pin(spec, pin_idx); |
1df5a06a | 1239 | per_pin->cvt_nid = per_cvt->cvt_nid; |
384a48d7 SW |
1240 | hinfo->nid = per_cvt->cvt_nid; |
1241 | ||
9152085d | 1242 | snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); |
bddee96b | 1243 | snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, |
384a48d7 | 1244 | AC_VERB_SET_CONNECT_SEL, |
4846a67e | 1245 | per_pin->mux_idx); |
7ef166b8 WX |
1246 | |
1247 | /* configure unused pins to choose other converters */ | |
4846a67e | 1248 | pin_cvt_fixup(codec, per_pin, 0); |
7ef166b8 | 1249 | |
2bf3c85a | 1250 | snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); |
bbbe3390 | 1251 | |
2def8172 | 1252 | /* Initially set the converter's capabilities */ |
384a48d7 SW |
1253 | hinfo->channels_min = per_cvt->channels_min; |
1254 | hinfo->channels_max = per_cvt->channels_max; | |
1255 | hinfo->rates = per_cvt->rates; | |
1256 | hinfo->formats = per_cvt->formats; | |
1257 | hinfo->maxbps = per_cvt->maxbps; | |
2def8172 | 1258 | |
42b29870 | 1259 | eld = &per_pin->sink_eld; |
384a48d7 | 1260 | /* Restrict capabilities by ELD if this isn't disabled */ |
c3d52105 | 1261 | if (!static_hdmi_pcm && eld->eld_valid) { |
1613d6b4 | 1262 | snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); |
bbbe3390 | 1263 | if (hinfo->channels_min > hinfo->channels_max || |
2ad779b7 TI |
1264 | !hinfo->rates || !hinfo->formats) { |
1265 | per_cvt->assigned = 0; | |
1266 | hinfo->nid = 0; | |
2bf3c85a | 1267 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
f69548ff TI |
1268 | err = -ENODEV; |
1269 | goto unlock; | |
2ad779b7 | 1270 | } |
bbbe3390 | 1271 | } |
2def8172 SW |
1272 | |
1273 | /* Store the updated parameters */ | |
639cef0e TI |
1274 | runtime->hw.channels_min = hinfo->channels_min; |
1275 | runtime->hw.channels_max = hinfo->channels_max; | |
1276 | runtime->hw.formats = hinfo->formats; | |
1277 | runtime->hw.rates = hinfo->rates; | |
4fe2ca14 TI |
1278 | |
1279 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1280 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
f69548ff TI |
1281 | unlock: |
1282 | mutex_unlock(&spec->pcm_lock); | |
1283 | return err; | |
bbbe3390 TI |
1284 | } |
1285 | ||
079d88cc WF |
1286 | /* |
1287 | * HDA/HDMI auto parsing | |
1288 | */ | |
384a48d7 | 1289 | static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) |
079d88cc WF |
1290 | { |
1291 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 1292 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
384a48d7 | 1293 | hda_nid_t pin_nid = per_pin->pin_nid; |
079d88cc WF |
1294 | |
1295 | if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { | |
4e76a883 TI |
1296 | codec_warn(codec, |
1297 | "HDMI: pin %d wcaps %#x does not support connection list\n", | |
079d88cc WF |
1298 | pin_nid, get_wcaps(codec, pin_nid)); |
1299 | return -EINVAL; | |
1300 | } | |
1301 | ||
9152085d | 1302 | /* all the device entries on the same pin have the same conn list */ |
384a48d7 SW |
1303 | per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid, |
1304 | per_pin->mux_nids, | |
1305 | HDA_MAX_CONNECTIONS); | |
079d88cc WF |
1306 | |
1307 | return 0; | |
1308 | } | |
1309 | ||
a76056f2 LY |
1310 | static int hdmi_find_pcm_slot(struct hdmi_spec *spec, |
1311 | struct hdmi_spec_per_pin *per_pin) | |
1312 | { | |
1313 | int i; | |
1314 | ||
1315 | /* try the prefer PCM */ | |
1316 | if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) | |
1317 | return per_pin->pin_nid_idx; | |
1318 | ||
1319 | /* have a second try; check the "reserved area" over num_pins */ | |
9152085d | 1320 | for (i = spec->num_nids; i < spec->pcm_used; i++) { |
a76056f2 LY |
1321 | if (!test_bit(i, &spec->pcm_bitmap)) |
1322 | return i; | |
1323 | } | |
1324 | ||
1325 | /* the last try; check the empty slots in pins */ | |
9152085d | 1326 | for (i = 0; i < spec->num_nids; i++) { |
a76056f2 LY |
1327 | if (!test_bit(i, &spec->pcm_bitmap)) |
1328 | return i; | |
1329 | } | |
1330 | return -EBUSY; | |
1331 | } | |
1332 | ||
1333 | static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, | |
1334 | struct hdmi_spec_per_pin *per_pin) | |
1335 | { | |
1336 | int idx; | |
1337 | ||
1338 | /* pcm already be attached to the pin */ | |
1339 | if (per_pin->pcm) | |
1340 | return; | |
1341 | idx = hdmi_find_pcm_slot(spec, per_pin); | |
d10a80de | 1342 | if (idx == -EBUSY) |
a76056f2 LY |
1343 | return; |
1344 | per_pin->pcm_idx = idx; | |
2bea241a | 1345 | per_pin->pcm = get_hdmi_pcm(spec, idx); |
a76056f2 LY |
1346 | set_bit(idx, &spec->pcm_bitmap); |
1347 | } | |
1348 | ||
1349 | static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, | |
1350 | struct hdmi_spec_per_pin *per_pin) | |
1351 | { | |
1352 | int idx; | |
1353 | ||
1354 | /* pcm already be detached from the pin */ | |
1355 | if (!per_pin->pcm) | |
1356 | return; | |
1357 | idx = per_pin->pcm_idx; | |
1358 | per_pin->pcm_idx = -1; | |
1359 | per_pin->pcm = NULL; | |
1360 | if (idx >= 0 && idx < spec->pcm_used) | |
1361 | clear_bit(idx, &spec->pcm_bitmap); | |
1362 | } | |
1363 | ||
ac98379a LY |
1364 | static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, |
1365 | struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) | |
1366 | { | |
1367 | int mux_idx; | |
1368 | ||
1369 | for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) | |
1370 | if (per_pin->mux_nids[mux_idx] == cvt_nid) | |
1371 | break; | |
1372 | return mux_idx; | |
1373 | } | |
1374 | ||
1375 | static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); | |
1376 | ||
1377 | static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, | |
1378 | struct hdmi_spec_per_pin *per_pin) | |
1379 | { | |
1380 | struct hda_codec *codec = per_pin->codec; | |
1381 | struct hda_pcm *pcm; | |
1382 | struct hda_pcm_stream *hinfo; | |
1383 | struct snd_pcm_substream *substream; | |
1384 | int mux_idx; | |
1385 | bool non_pcm; | |
1386 | ||
1387 | if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) | |
2bea241a | 1388 | pcm = get_pcm_rec(spec, per_pin->pcm_idx); |
ac98379a LY |
1389 | else |
1390 | return; | |
8a7d6003 TI |
1391 | if (!pcm->pcm) |
1392 | return; | |
ac98379a LY |
1393 | if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) |
1394 | return; | |
1395 | ||
1396 | /* hdmi audio only uses playback and one substream */ | |
1397 | hinfo = pcm->stream; | |
1398 | substream = pcm->pcm->streams[0].substream; | |
1399 | ||
1400 | per_pin->cvt_nid = hinfo->nid; | |
1401 | ||
1402 | mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); | |
9152085d LY |
1403 | if (mux_idx < per_pin->num_mux_nids) { |
1404 | snd_hda_set_dev_select(codec, per_pin->pin_nid, | |
1405 | per_pin->dev_id); | |
ac98379a LY |
1406 | snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, |
1407 | AC_VERB_SET_CONNECT_SEL, | |
1408 | mux_idx); | |
9152085d | 1409 | } |
ac98379a LY |
1410 | snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); |
1411 | ||
1412 | non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); | |
1413 | if (substream->runtime) | |
1414 | per_pin->channels = substream->runtime->channels; | |
1415 | per_pin->setup = true; | |
1416 | per_pin->mux_idx = mux_idx; | |
1417 | ||
1418 | hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); | |
1419 | } | |
1420 | ||
1421 | static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, | |
1422 | struct hdmi_spec_per_pin *per_pin) | |
1423 | { | |
1424 | if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) | |
1425 | snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); | |
1426 | ||
1427 | per_pin->chmap_set = false; | |
1428 | memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); | |
1429 | ||
1430 | per_pin->setup = false; | |
1431 | per_pin->channels = 0; | |
1432 | } | |
1433 | ||
e90247f9 TI |
1434 | /* update per_pin ELD from the given new ELD; |
1435 | * setup info frame and notification accordingly | |
1436 | */ | |
1437 | static void update_eld(struct hda_codec *codec, | |
1438 | struct hdmi_spec_per_pin *per_pin, | |
1439 | struct hdmi_eld *eld) | |
1440 | { | |
1441 | struct hdmi_eld *pin_eld = &per_pin->sink_eld; | |
a76056f2 | 1442 | struct hdmi_spec *spec = codec->spec; |
e90247f9 TI |
1443 | bool old_eld_valid = pin_eld->eld_valid; |
1444 | bool eld_changed; | |
fb087eaa | 1445 | int pcm_idx = -1; |
e90247f9 | 1446 | |
fb087eaa LY |
1447 | /* for monitor disconnection, save pcm_idx firstly */ |
1448 | pcm_idx = per_pin->pcm_idx; | |
a76056f2 | 1449 | if (spec->dyn_pcm_assign) { |
ac98379a | 1450 | if (eld->eld_valid) { |
a76056f2 | 1451 | hdmi_attach_hda_pcm(spec, per_pin); |
ac98379a LY |
1452 | hdmi_pcm_setup_pin(spec, per_pin); |
1453 | } else { | |
1454 | hdmi_pcm_reset_pin(spec, per_pin); | |
a76056f2 | 1455 | hdmi_detach_hda_pcm(spec, per_pin); |
ac98379a | 1456 | } |
a76056f2 | 1457 | } |
fb087eaa LY |
1458 | /* if pcm_idx == -1, it means this is in monitor connection event |
1459 | * we can get the correct pcm_idx now. | |
1460 | */ | |
1461 | if (pcm_idx == -1) | |
1462 | pcm_idx = per_pin->pcm_idx; | |
a76056f2 | 1463 | |
e90247f9 TI |
1464 | if (eld->eld_valid) |
1465 | snd_hdmi_show_eld(codec, &eld->info); | |
1466 | ||
1467 | eld_changed = (pin_eld->eld_valid != eld->eld_valid); | |
1468 | if (eld->eld_valid && pin_eld->eld_valid) | |
1469 | if (pin_eld->eld_size != eld->eld_size || | |
1470 | memcmp(pin_eld->eld_buffer, eld->eld_buffer, | |
1471 | eld->eld_size) != 0) | |
1472 | eld_changed = true; | |
1473 | ||
bd481285 | 1474 | pin_eld->monitor_present = eld->monitor_present; |
e90247f9 TI |
1475 | pin_eld->eld_valid = eld->eld_valid; |
1476 | pin_eld->eld_size = eld->eld_size; | |
1477 | if (eld->eld_valid) | |
1478 | memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size); | |
1479 | pin_eld->info = eld->info; | |
1480 | ||
1481 | /* | |
1482 | * Re-setup pin and infoframe. This is needed e.g. when | |
1483 | * - sink is first plugged-in | |
1484 | * - transcoder can change during stream playback on Haswell | |
1485 | * and this can make HW reset converter selection on a pin. | |
1486 | */ | |
1487 | if (eld->eld_valid && !old_eld_valid && per_pin->setup) { | |
4846a67e | 1488 | pin_cvt_fixup(codec, per_pin, 0); |
e90247f9 TI |
1489 | hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); |
1490 | } | |
1491 | ||
fb087eaa | 1492 | if (eld_changed && pcm_idx >= 0) |
e90247f9 TI |
1493 | snd_ctl_notify(codec->card, |
1494 | SNDRV_CTL_EVENT_MASK_VALUE | | |
1495 | SNDRV_CTL_EVENT_MASK_INFO, | |
fb087eaa | 1496 | &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); |
e90247f9 TI |
1497 | } |
1498 | ||
788d441a TI |
1499 | /* update ELD and jack state via HD-audio verbs */ |
1500 | static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, | |
1501 | int repoll) | |
079d88cc | 1502 | { |
464837a7 | 1503 | struct hda_jack_tbl *jack; |
744626da | 1504 | struct hda_codec *codec = per_pin->codec; |
4bd038f9 DH |
1505 | struct hdmi_spec *spec = codec->spec; |
1506 | struct hdmi_eld *eld = &spec->temp_eld; | |
744626da | 1507 | hda_nid_t pin_nid = per_pin->pin_nid; |
5d44f927 SW |
1508 | /* |
1509 | * Always execute a GetPinSense verb here, even when called from | |
1510 | * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited | |
1511 | * response's PD bit is not the real PD value, but indicates that | |
1512 | * the real PD value changed. An older version of the HD-audio | |
1513 | * specification worked this way. Hence, we just ignore the data in | |
1514 | * the unsolicited response to avoid custom WARs. | |
1515 | */ | |
da4a7a39 | 1516 | int present; |
efe47108 | 1517 | bool ret; |
9a5e5234 | 1518 | bool do_repoll = false; |
079d88cc | 1519 | |
da4a7a39 DH |
1520 | present = snd_hda_pin_sense(codec, pin_nid); |
1521 | ||
a4e9a38b | 1522 | mutex_lock(&per_pin->lock); |
c44da62b TI |
1523 | eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); |
1524 | if (eld->monitor_present) | |
4bd038f9 DH |
1525 | eld->eld_valid = !!(present & AC_PINSENSE_ELDV); |
1526 | else | |
1527 | eld->eld_valid = false; | |
079d88cc | 1528 | |
4e76a883 | 1529 | codec_dbg(codec, |
384a48d7 | 1530 | "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", |
c44da62b | 1531 | codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); |
5d44f927 | 1532 | |
4bd038f9 | 1533 | if (eld->eld_valid) { |
307229d2 | 1534 | if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer, |
1613d6b4 | 1535 | &eld->eld_size) < 0) |
4bd038f9 | 1536 | eld->eld_valid = false; |
1613d6b4 | 1537 | else { |
79514d47 | 1538 | if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, |
1613d6b4 | 1539 | eld->eld_size) < 0) |
4bd038f9 | 1540 | eld->eld_valid = false; |
1613d6b4 | 1541 | } |
9a5e5234 TI |
1542 | if (!eld->eld_valid && repoll) |
1543 | do_repoll = true; | |
744626da | 1544 | } |
4bd038f9 | 1545 | |
9a5e5234 | 1546 | if (do_repoll) |
e90247f9 TI |
1547 | schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); |
1548 | else | |
1549 | update_eld(codec, per_pin, eld); | |
92c69e79 | 1550 | |
c44da62b | 1551 | ret = !repoll || !eld->monitor_present || eld->eld_valid; |
464837a7 DH |
1552 | |
1553 | jack = snd_hda_jack_tbl_get(codec, pin_nid); | |
1554 | if (jack) | |
1555 | jack->block_report = !ret; | |
1556 | ||
a4e9a38b | 1557 | mutex_unlock(&per_pin->lock); |
efe47108 | 1558 | return ret; |
079d88cc WF |
1559 | } |
1560 | ||
3184270e LY |
1561 | static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec, |
1562 | struct hdmi_spec_per_pin *per_pin) | |
1563 | { | |
1564 | struct hdmi_spec *spec = codec->spec; | |
1565 | struct snd_jack *jack = NULL; | |
1566 | struct hda_jack_tbl *jack_tbl; | |
1567 | ||
1568 | /* if !dyn_pcm_assign, get jack from hda_jack_tbl | |
1569 | * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not | |
1570 | * NULL even after snd_hda_jack_tbl_clear() is called to | |
1571 | * free snd_jack. This may cause access invalid memory | |
1572 | * when calling snd_jack_report | |
1573 | */ | |
1574 | if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign) | |
1575 | jack = spec->pcm_rec[per_pin->pcm_idx].jack; | |
1576 | else if (!spec->dyn_pcm_assign) { | |
9152085d LY |
1577 | /* |
1578 | * jack tbl doesn't support DP MST | |
1579 | * DP MST will use dyn_pcm_assign, | |
1580 | * so DP MST will never come here | |
1581 | */ | |
3184270e LY |
1582 | jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); |
1583 | if (jack_tbl) | |
1584 | jack = jack_tbl->jack; | |
1585 | } | |
1586 | return jack; | |
1587 | } | |
1588 | ||
788d441a TI |
1589 | /* update ELD and jack state via audio component */ |
1590 | static void sync_eld_via_acomp(struct hda_codec *codec, | |
1591 | struct hdmi_spec_per_pin *per_pin) | |
1592 | { | |
788d441a TI |
1593 | struct hdmi_spec *spec = codec->spec; |
1594 | struct hdmi_eld *eld = &spec->temp_eld; | |
25e4abb3 | 1595 | struct snd_jack *jack = NULL; |
788d441a TI |
1596 | int size; |
1597 | ||
e2dc7d7d | 1598 | mutex_lock(&per_pin->lock); |
c64c1437 | 1599 | eld->monitor_present = false; |
9152085d LY |
1600 | size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, |
1601 | per_pin->dev_id, &eld->monitor_present, | |
1602 | eld->eld_buffer, ELD_MAX_SIZE); | |
e2dc7d7d TI |
1603 | if (size > 0) { |
1604 | size = min(size, ELD_MAX_SIZE); | |
1605 | if (snd_hdmi_parse_eld(codec, &eld->info, | |
1606 | eld->eld_buffer, size) < 0) | |
1607 | size = -EINVAL; | |
1608 | } | |
788d441a | 1609 | |
e2dc7d7d TI |
1610 | if (size > 0) { |
1611 | eld->eld_valid = true; | |
1612 | eld->eld_size = size; | |
1613 | } else { | |
1614 | eld->eld_valid = false; | |
1615 | eld->eld_size = 0; | |
788d441a | 1616 | } |
e2dc7d7d | 1617 | |
25e4abb3 LY |
1618 | /* pcm_idx >=0 before update_eld() means it is in monitor |
1619 | * disconnected event. Jack must be fetched before update_eld() | |
1620 | */ | |
3184270e | 1621 | jack = pin_idx_to_jack(codec, per_pin); |
e2dc7d7d | 1622 | update_eld(codec, per_pin, eld); |
3184270e LY |
1623 | if (jack == NULL) |
1624 | jack = pin_idx_to_jack(codec, per_pin); | |
25e4abb3 LY |
1625 | if (jack == NULL) |
1626 | goto unlock; | |
1627 | snd_jack_report(jack, | |
e2dc7d7d TI |
1628 | eld->monitor_present ? SND_JACK_AVOUT : 0); |
1629 | unlock: | |
1630 | mutex_unlock(&per_pin->lock); | |
788d441a TI |
1631 | } |
1632 | ||
1633 | static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) | |
1634 | { | |
1635 | struct hda_codec *codec = per_pin->codec; | |
a76056f2 | 1636 | int ret; |
788d441a | 1637 | |
222bde03 | 1638 | /* no temporary power up/down needed for component notifier */ |
aaa23f86 CW |
1639 | if (!codec_has_acomp(codec)) { |
1640 | ret = snd_hda_power_up_pm(codec); | |
1641 | if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) { | |
1642 | snd_hda_power_down_pm(codec); | |
1643 | return false; | |
1644 | } | |
1645 | } | |
222bde03 | 1646 | |
788d441a TI |
1647 | if (codec_has_acomp(codec)) { |
1648 | sync_eld_via_acomp(codec, per_pin); | |
a76056f2 | 1649 | ret = false; /* don't call snd_hda_jack_report_sync() */ |
788d441a | 1650 | } else { |
a76056f2 | 1651 | ret = hdmi_present_sense_via_verbs(per_pin, repoll); |
788d441a | 1652 | } |
a76056f2 | 1653 | |
222bde03 TI |
1654 | if (!codec_has_acomp(codec)) |
1655 | snd_hda_power_down_pm(codec); | |
1656 | ||
a76056f2 | 1657 | return ret; |
788d441a TI |
1658 | } |
1659 | ||
744626da WF |
1660 | static void hdmi_repoll_eld(struct work_struct *work) |
1661 | { | |
1662 | struct hdmi_spec_per_pin *per_pin = | |
1663 | container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); | |
aaa23f86 CW |
1664 | struct hda_codec *codec = per_pin->codec; |
1665 | struct hdmi_spec *spec = codec->spec; | |
744626da | 1666 | |
c6e8453e WF |
1667 | if (per_pin->repoll_count++ > 6) |
1668 | per_pin->repoll_count = 0; | |
1669 | ||
aaa23f86 | 1670 | mutex_lock(&spec->pcm_lock); |
efe47108 TI |
1671 | if (hdmi_present_sense(per_pin, per_pin->repoll_count)) |
1672 | snd_hda_jack_report_sync(per_pin->codec); | |
aaa23f86 | 1673 | mutex_unlock(&spec->pcm_lock); |
744626da WF |
1674 | } |
1675 | ||
c88d4e84 TI |
1676 | static void intel_haswell_fixup_connect_list(struct hda_codec *codec, |
1677 | hda_nid_t nid); | |
1678 | ||
079d88cc WF |
1679 | static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) |
1680 | { | |
1681 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
1682 | unsigned int caps, config; |
1683 | int pin_idx; | |
1684 | struct hdmi_spec_per_pin *per_pin; | |
07acecc1 | 1685 | int err; |
9152085d | 1686 | int dev_num, i; |
079d88cc | 1687 | |
efc2f8de | 1688 | caps = snd_hda_query_pin_caps(codec, pin_nid); |
384a48d7 SW |
1689 | if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) |
1690 | return 0; | |
1691 | ||
9152085d LY |
1692 | /* |
1693 | * For DP MST audio, Configuration Default is the same for | |
1694 | * all device entries on the same pin | |
1695 | */ | |
efc2f8de | 1696 | config = snd_hda_codec_get_pincfg(codec, pin_nid); |
384a48d7 SW |
1697 | if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) |
1698 | return 0; | |
1699 | ||
9152085d LY |
1700 | /* |
1701 | * To simplify the implementation, malloc all | |
1702 | * the virtual pins in the initialization statically | |
1703 | */ | |
1704 | if (is_haswell_plus(codec)) { | |
1705 | /* | |
1706 | * On Intel platforms, device entries number is | |
1707 | * changed dynamically. If there is a DP MST | |
1708 | * hub connected, the device entries number is 3. | |
1709 | * Otherwise, it is 1. | |
1710 | * Here we manually set dev_num to 3, so that | |
1711 | * we can initialize all the device entries when | |
1712 | * bootup statically. | |
1713 | */ | |
1714 | dev_num = 3; | |
1715 | spec->dev_num = 3; | |
1716 | } else if (spec->dyn_pcm_assign && codec->dp_mst) { | |
1717 | dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; | |
1718 | /* | |
1719 | * spec->dev_num is the maxinum number of device entries | |
1720 | * among all the pins | |
1721 | */ | |
1722 | spec->dev_num = (spec->dev_num > dev_num) ? | |
1723 | spec->dev_num : dev_num; | |
1724 | } else { | |
1725 | /* | |
1726 | * If the platform doesn't support DP MST, | |
1727 | * manually set dev_num to 1. This means | |
1728 | * the pin has only one device entry. | |
1729 | */ | |
1730 | dev_num = 1; | |
1731 | spec->dev_num = 1; | |
2bea241a | 1732 | } |
079d88cc | 1733 | |
9152085d LY |
1734 | for (i = 0; i < dev_num; i++) { |
1735 | pin_idx = spec->num_pins; | |
1736 | per_pin = snd_array_new(&spec->pins); | |
079d88cc | 1737 | |
9152085d LY |
1738 | if (!per_pin) |
1739 | return -ENOMEM; | |
1740 | ||
1741 | if (spec->dyn_pcm_assign) { | |
1742 | per_pin->pcm = NULL; | |
1743 | per_pin->pcm_idx = -1; | |
1744 | } else { | |
1745 | per_pin->pcm = get_hdmi_pcm(spec, pin_idx); | |
1746 | per_pin->pcm_idx = pin_idx; | |
1747 | } | |
1748 | per_pin->pin_nid = pin_nid; | |
1749 | per_pin->pin_nid_idx = spec->num_nids; | |
1750 | per_pin->dev_id = i; | |
1751 | per_pin->non_pcm = false; | |
1752 | snd_hda_set_dev_select(codec, pin_nid, i); | |
1753 | if (is_haswell_plus(codec)) | |
1754 | intel_haswell_fixup_connect_list(codec, pin_nid); | |
1755 | err = hdmi_read_pin_conn(codec, pin_idx); | |
1756 | if (err < 0) | |
1757 | return err; | |
1758 | spec->num_pins++; | |
1759 | } | |
1760 | spec->num_nids++; | |
079d88cc | 1761 | |
384a48d7 | 1762 | return 0; |
079d88cc WF |
1763 | } |
1764 | ||
384a48d7 | 1765 | static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) |
079d88cc WF |
1766 | { |
1767 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
1768 | struct hdmi_spec_per_cvt *per_cvt; |
1769 | unsigned int chans; | |
1770 | int err; | |
079d88cc | 1771 | |
384a48d7 SW |
1772 | chans = get_wcaps(codec, cvt_nid); |
1773 | chans = get_wcaps_channels(chans); | |
1774 | ||
bce0d2a8 TI |
1775 | per_cvt = snd_array_new(&spec->cvts); |
1776 | if (!per_cvt) | |
1777 | return -ENOMEM; | |
384a48d7 SW |
1778 | |
1779 | per_cvt->cvt_nid = cvt_nid; | |
1780 | per_cvt->channels_min = 2; | |
d45e6889 | 1781 | if (chans <= 16) { |
384a48d7 | 1782 | per_cvt->channels_max = chans; |
67b90cb8 SP |
1783 | if (chans > spec->chmap.channels_max) |
1784 | spec->chmap.channels_max = chans; | |
d45e6889 | 1785 | } |
384a48d7 SW |
1786 | |
1787 | err = snd_hda_query_supported_pcm(codec, cvt_nid, | |
1788 | &per_cvt->rates, | |
1789 | &per_cvt->formats, | |
1790 | &per_cvt->maxbps); | |
1791 | if (err < 0) | |
1792 | return err; | |
1793 | ||
bce0d2a8 TI |
1794 | if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) |
1795 | spec->cvt_nids[spec->num_cvts] = cvt_nid; | |
1796 | spec->num_cvts++; | |
079d88cc WF |
1797 | |
1798 | return 0; | |
1799 | } | |
1800 | ||
1801 | static int hdmi_parse_codec(struct hda_codec *codec) | |
1802 | { | |
1803 | hda_nid_t nid; | |
1804 | int i, nodes; | |
1805 | ||
7639a06c | 1806 | nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); |
079d88cc | 1807 | if (!nid || nodes < 0) { |
4e76a883 | 1808 | codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); |
079d88cc WF |
1809 | return -EINVAL; |
1810 | } | |
1811 | ||
1812 | for (i = 0; i < nodes; i++, nid++) { | |
1813 | unsigned int caps; | |
1814 | unsigned int type; | |
1815 | ||
efc2f8de | 1816 | caps = get_wcaps(codec, nid); |
079d88cc WF |
1817 | type = get_wcaps_type(caps); |
1818 | ||
1819 | if (!(caps & AC_WCAP_DIGITAL)) | |
1820 | continue; | |
1821 | ||
1822 | switch (type) { | |
1823 | case AC_WID_AUD_OUT: | |
384a48d7 | 1824 | hdmi_add_cvt(codec, nid); |
079d88cc WF |
1825 | break; |
1826 | case AC_WID_PIN: | |
3eaead57 | 1827 | hdmi_add_pin(codec, nid); |
079d88cc WF |
1828 | break; |
1829 | } | |
1830 | } | |
1831 | ||
079d88cc WF |
1832 | return 0; |
1833 | } | |
1834 | ||
84eb01be TI |
1835 | /* |
1836 | */ | |
1a6003b5 TI |
1837 | static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) |
1838 | { | |
1839 | struct hda_spdif_out *spdif; | |
1840 | bool non_pcm; | |
1841 | ||
1842 | mutex_lock(&codec->spdif_mutex); | |
1843 | spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); | |
960a581e LY |
1844 | /* Add sanity check to pass klockwork check. |
1845 | * This should never happen. | |
1846 | */ | |
1847 | if (WARN_ON(spdif == NULL)) | |
1848 | return true; | |
1a6003b5 TI |
1849 | non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); |
1850 | mutex_unlock(&codec->spdif_mutex); | |
1851 | return non_pcm; | |
1852 | } | |
1853 | ||
84eb01be TI |
1854 | /* |
1855 | * HDMI callbacks | |
1856 | */ | |
1857 | ||
1858 | static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
1859 | struct hda_codec *codec, | |
1860 | unsigned int stream_tag, | |
1861 | unsigned int format, | |
1862 | struct snd_pcm_substream *substream) | |
1863 | { | |
384a48d7 SW |
1864 | hda_nid_t cvt_nid = hinfo->nid; |
1865 | struct hdmi_spec *spec = codec->spec; | |
42b29870 LY |
1866 | int pin_idx; |
1867 | struct hdmi_spec_per_pin *per_pin; | |
1868 | hda_nid_t pin_nid; | |
ddd621fb | 1869 | struct snd_pcm_runtime *runtime = substream->runtime; |
1a6003b5 | 1870 | bool non_pcm; |
053b0559 | 1871 | int pinctl, stripe; |
f69548ff | 1872 | int err = 0; |
1a6003b5 | 1873 | |
42b29870 LY |
1874 | mutex_lock(&spec->pcm_lock); |
1875 | pin_idx = hinfo_to_pin_index(codec, hinfo); | |
1876 | if (spec->dyn_pcm_assign && pin_idx < 0) { | |
1877 | /* when dyn_pcm_assign and pcm is not bound to a pin | |
1878 | * skip pin setup and return 0 to make audio playback | |
1879 | * be ongoing | |
1880 | */ | |
4846a67e | 1881 | pin_cvt_fixup(codec, NULL, cvt_nid); |
42b29870 LY |
1882 | snd_hda_codec_setup_stream(codec, cvt_nid, |
1883 | stream_tag, 0, format); | |
f69548ff | 1884 | goto unlock; |
42b29870 | 1885 | } |
1a6003b5 | 1886 | |
42b29870 | 1887 | if (snd_BUG_ON(pin_idx < 0)) { |
f69548ff TI |
1888 | err = -EINVAL; |
1889 | goto unlock; | |
42b29870 LY |
1890 | } |
1891 | per_pin = get_pin(spec, pin_idx); | |
1892 | pin_nid = per_pin->pin_nid; | |
4846a67e TI |
1893 | |
1894 | /* Verify pin:cvt selections to avoid silent audio after S3. | |
1895 | * After S3, the audio driver restores pin:cvt selections | |
1896 | * but this can happen before gfx is ready and such selection | |
1897 | * is overlooked by HW. Thus multiple pins can share a same | |
1898 | * default convertor and mute control will affect each other, | |
1899 | * which can cause a resumed audio playback become silent | |
1900 | * after S3. | |
1901 | */ | |
1902 | pin_cvt_fixup(codec, per_pin, 0); | |
2df6742f | 1903 | |
ddd621fb LY |
1904 | /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ |
1905 | /* Todo: add DP1.2 MST audio support later */ | |
93a9ff15 | 1906 | if (codec_has_acomp(codec)) |
9152085d | 1907 | snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id, |
f9318941 | 1908 | runtime->rate); |
ddd621fb | 1909 | |
1a6003b5 | 1910 | non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); |
a4e9a38b | 1911 | mutex_lock(&per_pin->lock); |
b054087d TI |
1912 | per_pin->channels = substream->runtime->channels; |
1913 | per_pin->setup = true; | |
384a48d7 | 1914 | |
053b0559 SP |
1915 | if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { |
1916 | stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, | |
1917 | substream); | |
1918 | snd_hda_codec_write(codec, cvt_nid, 0, | |
1919 | AC_VERB_SET_STRIPE_CONTROL, | |
1920 | stripe); | |
1921 | } | |
1922 | ||
b054087d | 1923 | hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); |
a4e9a38b | 1924 | mutex_unlock(&per_pin->lock); |
75fae117 SW |
1925 | if (spec->dyn_pin_out) { |
1926 | pinctl = snd_hda_codec_read(codec, pin_nid, 0, | |
1927 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
1928 | snd_hda_codec_write(codec, pin_nid, 0, | |
1929 | AC_VERB_SET_PIN_WIDGET_CONTROL, | |
1930 | pinctl | PIN_OUT); | |
1931 | } | |
1932 | ||
9152085d | 1933 | /* snd_hda_set_dev_select() has been called before */ |
42b29870 LY |
1934 | err = spec->ops.setup_stream(codec, cvt_nid, pin_nid, |
1935 | stream_tag, format); | |
f69548ff | 1936 | unlock: |
42b29870 LY |
1937 | mutex_unlock(&spec->pcm_lock); |
1938 | return err; | |
84eb01be TI |
1939 | } |
1940 | ||
8dfaa573 TI |
1941 | static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, |
1942 | struct hda_codec *codec, | |
1943 | struct snd_pcm_substream *substream) | |
1944 | { | |
1945 | snd_hda_codec_cleanup_stream(codec, hinfo->nid); | |
1946 | return 0; | |
1947 | } | |
1948 | ||
f2ad24fa TI |
1949 | static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, |
1950 | struct hda_codec *codec, | |
1951 | struct snd_pcm_substream *substream) | |
384a48d7 SW |
1952 | { |
1953 | struct hdmi_spec *spec = codec->spec; | |
2bf3c85a | 1954 | int cvt_idx, pin_idx, pcm_idx; |
384a48d7 SW |
1955 | struct hdmi_spec_per_cvt *per_cvt; |
1956 | struct hdmi_spec_per_pin *per_pin; | |
75fae117 | 1957 | int pinctl; |
f69548ff | 1958 | int err = 0; |
384a48d7 | 1959 | |
384a48d7 | 1960 | if (hinfo->nid) { |
2bf3c85a LY |
1961 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1962 | if (snd_BUG_ON(pcm_idx < 0)) | |
1963 | return -EINVAL; | |
4e76a883 | 1964 | cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); |
384a48d7 SW |
1965 | if (snd_BUG_ON(cvt_idx < 0)) |
1966 | return -EINVAL; | |
bce0d2a8 | 1967 | per_cvt = get_cvt(spec, cvt_idx); |
384a48d7 SW |
1968 | |
1969 | snd_BUG_ON(!per_cvt->assigned); | |
1970 | per_cvt->assigned = 0; | |
1971 | hinfo->nid = 0; | |
1972 | ||
42b29870 | 1973 | mutex_lock(&spec->pcm_lock); |
b09887f8 | 1974 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
ac98379a | 1975 | clear_bit(pcm_idx, &spec->pcm_in_use); |
4e76a883 | 1976 | pin_idx = hinfo_to_pin_index(codec, hinfo); |
f69548ff TI |
1977 | if (spec->dyn_pcm_assign && pin_idx < 0) |
1978 | goto unlock; | |
42b29870 LY |
1979 | |
1980 | if (snd_BUG_ON(pin_idx < 0)) { | |
f69548ff TI |
1981 | err = -EINVAL; |
1982 | goto unlock; | |
42b29870 | 1983 | } |
bce0d2a8 | 1984 | per_pin = get_pin(spec, pin_idx); |
384a48d7 | 1985 | |
75fae117 SW |
1986 | if (spec->dyn_pin_out) { |
1987 | pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, | |
1988 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
1989 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, | |
1990 | AC_VERB_SET_PIN_WIDGET_CONTROL, | |
1991 | pinctl & ~PIN_OUT); | |
1992 | } | |
1993 | ||
a4e9a38b | 1994 | mutex_lock(&per_pin->lock); |
d45e6889 TI |
1995 | per_pin->chmap_set = false; |
1996 | memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); | |
b054087d TI |
1997 | |
1998 | per_pin->setup = false; | |
1999 | per_pin->channels = 0; | |
a4e9a38b | 2000 | mutex_unlock(&per_pin->lock); |
f69548ff | 2001 | unlock: |
42b29870 | 2002 | mutex_unlock(&spec->pcm_lock); |
384a48d7 | 2003 | } |
d45e6889 | 2004 | |
f69548ff | 2005 | return err; |
384a48d7 SW |
2006 | } |
2007 | ||
2008 | static const struct hda_pcm_ops generic_ops = { | |
2009 | .open = hdmi_pcm_open, | |
f2ad24fa | 2010 | .close = hdmi_pcm_close, |
384a48d7 | 2011 | .prepare = generic_hdmi_playback_pcm_prepare, |
8dfaa573 | 2012 | .cleanup = generic_hdmi_playback_pcm_cleanup, |
84eb01be TI |
2013 | }; |
2014 | ||
44fde3b8 SP |
2015 | static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) |
2016 | { | |
2017 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2018 | struct hdmi_spec *spec = codec->spec; | |
2019 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2020 | ||
2021 | if (!per_pin) | |
2022 | return 0; | |
2023 | ||
2024 | return per_pin->sink_eld.info.spk_alloc; | |
2025 | } | |
2026 | ||
9b3dc8aa SP |
2027 | static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, |
2028 | unsigned char *chmap) | |
2029 | { | |
2030 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2031 | struct hdmi_spec *spec = codec->spec; | |
2032 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2033 | ||
2034 | /* chmap is already set to 0 in caller */ | |
2035 | if (!per_pin) | |
2036 | return; | |
2037 | ||
2038 | memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); | |
2039 | } | |
2040 | ||
2041 | static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, | |
2042 | unsigned char *chmap, int prepared) | |
2043 | { | |
2044 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2045 | struct hdmi_spec *spec = codec->spec; | |
2046 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2047 | ||
ed0739b5 LY |
2048 | if (!per_pin) |
2049 | return; | |
9b3dc8aa SP |
2050 | mutex_lock(&per_pin->lock); |
2051 | per_pin->chmap_set = true; | |
2052 | memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); | |
2053 | if (prepared) | |
2054 | hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); | |
2055 | mutex_unlock(&per_pin->lock); | |
2056 | } | |
2057 | ||
2058 | static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) | |
2059 | { | |
2060 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2061 | struct hdmi_spec *spec = codec->spec; | |
2062 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2063 | ||
2064 | return per_pin ? true:false; | |
2065 | } | |
2066 | ||
84eb01be TI |
2067 | static int generic_hdmi_build_pcms(struct hda_codec *codec) |
2068 | { | |
2069 | struct hdmi_spec *spec = codec->spec; | |
9152085d | 2070 | int idx; |
84eb01be | 2071 | |
9152085d LY |
2072 | /* |
2073 | * for non-mst mode, pcm number is the same as before | |
2074 | * for DP MST mode, pcm number is (nid number + dev_num - 1) | |
2075 | * dev_num is the device entry number in a pin | |
2076 | * | |
2077 | */ | |
2078 | for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) { | |
384a48d7 | 2079 | struct hda_pcm *info; |
84eb01be | 2080 | struct hda_pcm_stream *pstr; |
bce0d2a8 | 2081 | |
9152085d | 2082 | info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); |
bce0d2a8 TI |
2083 | if (!info) |
2084 | return -ENOMEM; | |
2bea241a | 2085 | |
9152085d | 2086 | spec->pcm_rec[idx].pcm = info; |
2bf3c85a | 2087 | spec->pcm_used++; |
84eb01be | 2088 | info->pcm_type = HDA_PCM_TYPE_HDMI; |
d45e6889 | 2089 | info->own_chmap = true; |
384a48d7 | 2090 | |
84eb01be | 2091 | pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; |
384a48d7 SW |
2092 | pstr->substreams = 1; |
2093 | pstr->ops = generic_ops; | |
9152085d LY |
2094 | /* pcm number is less than 16 */ |
2095 | if (spec->pcm_used >= 16) | |
2096 | break; | |
384a48d7 | 2097 | /* other pstr fields are set in open */ |
84eb01be TI |
2098 | } |
2099 | ||
2100 | return 0; | |
2101 | } | |
2102 | ||
25e4abb3 | 2103 | static void free_hdmi_jack_priv(struct snd_jack *jack) |
788d441a | 2104 | { |
25e4abb3 | 2105 | struct hdmi_pcm *pcm = jack->private_data; |
788d441a | 2106 | |
25e4abb3 | 2107 | pcm->jack = NULL; |
788d441a TI |
2108 | } |
2109 | ||
25e4abb3 LY |
2110 | static int add_hdmi_jack_kctl(struct hda_codec *codec, |
2111 | struct hdmi_spec *spec, | |
2112 | int pcm_idx, | |
788d441a TI |
2113 | const char *name) |
2114 | { | |
2115 | struct snd_jack *jack; | |
2116 | int err; | |
2117 | ||
2118 | err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack, | |
2119 | true, false); | |
2120 | if (err < 0) | |
2121 | return err; | |
25e4abb3 LY |
2122 | |
2123 | spec->pcm_rec[pcm_idx].jack = jack; | |
2124 | jack->private_data = &spec->pcm_rec[pcm_idx]; | |
2125 | jack->private_free = free_hdmi_jack_priv; | |
788d441a TI |
2126 | return 0; |
2127 | } | |
2128 | ||
25e4abb3 | 2129 | static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) |
0b6c49b5 | 2130 | { |
31ef2257 | 2131 | char hdmi_str[32] = "HDMI/DP"; |
0b6c49b5 | 2132 | struct hdmi_spec *spec = codec->spec; |
25e4abb3 LY |
2133 | struct hdmi_spec_per_pin *per_pin; |
2134 | struct hda_jack_tbl *jack; | |
2135 | int pcmdev = get_pcm_rec(spec, pcm_idx)->device; | |
909cadc6 | 2136 | bool phantom_jack; |
25e4abb3 | 2137 | int ret; |
0b6c49b5 | 2138 | |
31ef2257 TI |
2139 | if (pcmdev > 0) |
2140 | sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); | |
25e4abb3 LY |
2141 | |
2142 | if (spec->dyn_pcm_assign) | |
2143 | return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str); | |
2144 | ||
2145 | /* for !dyn_pcm_assign, we still use hda_jack for compatibility */ | |
2146 | /* if !dyn_pcm_assign, it must be non-MST mode. | |
2147 | * This means pcms and pins are statically mapped. | |
2148 | * And pcm_idx is pin_idx. | |
2149 | */ | |
2150 | per_pin = get_pin(spec, pcm_idx); | |
909cadc6 TI |
2151 | phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); |
2152 | if (phantom_jack) | |
30efd8de DH |
2153 | strncat(hdmi_str, " Phantom", |
2154 | sizeof(hdmi_str) - strlen(hdmi_str) - 1); | |
25e4abb3 | 2155 | ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, |
911761c2 | 2156 | phantom_jack, 0, NULL); |
25e4abb3 LY |
2157 | if (ret < 0) |
2158 | return ret; | |
2159 | jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); | |
2160 | if (jack == NULL) | |
2161 | return 0; | |
2162 | /* assign jack->jack to pcm_rec[].jack to | |
2163 | * align with dyn_pcm_assign mode | |
2164 | */ | |
2165 | spec->pcm_rec[pcm_idx].jack = jack->jack; | |
2166 | return 0; | |
0b6c49b5 DH |
2167 | } |
2168 | ||
84eb01be TI |
2169 | static int generic_hdmi_build_controls(struct hda_codec *codec) |
2170 | { | |
2171 | struct hdmi_spec *spec = codec->spec; | |
1f7f51a6 | 2172 | int dev, err; |
25e4abb3 | 2173 | int pin_idx, pcm_idx; |
84eb01be | 2174 | |
25e4abb3 | 2175 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { |
8a7d6003 TI |
2176 | if (!get_pcm_rec(spec, pcm_idx)->pcm) { |
2177 | /* no PCM: mark this for skipping permanently */ | |
2178 | set_bit(pcm_idx, &spec->pcm_bitmap); | |
2179 | continue; | |
2180 | } | |
2181 | ||
25e4abb3 | 2182 | err = generic_hdmi_build_jack(codec, pcm_idx); |
0b6c49b5 DH |
2183 | if (err < 0) |
2184 | return err; | |
2185 | ||
b09887f8 LY |
2186 | /* create the spdif for each pcm |
2187 | * pin will be bound when monitor is connected | |
2188 | */ | |
2189 | if (spec->dyn_pcm_assign) | |
2190 | err = snd_hda_create_dig_out_ctls(codec, | |
2191 | 0, spec->cvt_nids[0], | |
2192 | HDA_PCM_TYPE_HDMI); | |
2193 | else { | |
2194 | struct hdmi_spec_per_pin *per_pin = | |
2195 | get_pin(spec, pcm_idx); | |
2196 | err = snd_hda_create_dig_out_ctls(codec, | |
dcda5806 TI |
2197 | per_pin->pin_nid, |
2198 | per_pin->mux_nids[0], | |
2199 | HDA_PCM_TYPE_HDMI); | |
b09887f8 | 2200 | } |
84eb01be TI |
2201 | if (err < 0) |
2202 | return err; | |
b09887f8 | 2203 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
14bc52b8 | 2204 | |
1f7f51a6 WY |
2205 | dev = get_pcm_rec(spec, pcm_idx)->device; |
2206 | if (dev != SNDRV_PCM_INVALID_DEVICE) { | |
2207 | /* add control for ELD Bytes */ | |
2208 | err = hdmi_create_eld_ctl(codec, pcm_idx, dev); | |
2209 | if (err < 0) | |
2210 | return err; | |
2211 | } | |
fb087eaa LY |
2212 | } |
2213 | ||
2214 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
2215 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
31ef2257 | 2216 | |
82b1d73f | 2217 | hdmi_present_sense(per_pin, 0); |
84eb01be TI |
2218 | } |
2219 | ||
d45e6889 | 2220 | /* add channel maps */ |
022f344b | 2221 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { |
bbbc7e85 | 2222 | struct hda_pcm *pcm; |
2ca320e2 | 2223 | |
022f344b | 2224 | pcm = get_pcm_rec(spec, pcm_idx); |
bbbc7e85 | 2225 | if (!pcm || !pcm->pcm) |
2ca320e2 | 2226 | break; |
2f6e8a85 | 2227 | err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); |
d45e6889 TI |
2228 | if (err < 0) |
2229 | return err; | |
d45e6889 TI |
2230 | } |
2231 | ||
84eb01be TI |
2232 | return 0; |
2233 | } | |
2234 | ||
8b8d654b | 2235 | static int generic_hdmi_init_per_pins(struct hda_codec *codec) |
84eb01be TI |
2236 | { |
2237 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
2238 | int pin_idx; |
2239 | ||
2240 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
bce0d2a8 | 2241 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
84eb01be | 2242 | |
744626da | 2243 | per_pin->codec = codec; |
a4e9a38b | 2244 | mutex_init(&per_pin->lock); |
744626da | 2245 | INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); |
a4e9a38b | 2246 | eld_proc_new(per_pin, pin_idx); |
84eb01be | 2247 | } |
8b8d654b TI |
2248 | return 0; |
2249 | } | |
2250 | ||
2251 | static int generic_hdmi_init(struct hda_codec *codec) | |
2252 | { | |
2253 | struct hdmi_spec *spec = codec->spec; | |
2254 | int pin_idx; | |
2255 | ||
2256 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
bce0d2a8 | 2257 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
8b8d654b | 2258 | hda_nid_t pin_nid = per_pin->pin_nid; |
9152085d | 2259 | int dev_id = per_pin->dev_id; |
8b8d654b | 2260 | |
9152085d | 2261 | snd_hda_set_dev_select(codec, pin_nid, dev_id); |
8b8d654b | 2262 | hdmi_init_pin(codec, pin_nid); |
788d441a TI |
2263 | if (!codec_has_acomp(codec)) |
2264 | snd_hda_jack_detect_enable_callback(codec, pin_nid, | |
2265 | codec->jackpoll_interval > 0 ? | |
2266 | jack_callback : NULL); | |
8b8d654b | 2267 | } |
84eb01be TI |
2268 | return 0; |
2269 | } | |
2270 | ||
bce0d2a8 TI |
2271 | static void hdmi_array_init(struct hdmi_spec *spec, int nums) |
2272 | { | |
2273 | snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); | |
2274 | snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); | |
bce0d2a8 TI |
2275 | } |
2276 | ||
2277 | static void hdmi_array_free(struct hdmi_spec *spec) | |
2278 | { | |
2279 | snd_array_free(&spec->pins); | |
2280 | snd_array_free(&spec->cvts); | |
bce0d2a8 TI |
2281 | } |
2282 | ||
a686632f TI |
2283 | static void generic_spec_free(struct hda_codec *codec) |
2284 | { | |
2285 | struct hdmi_spec *spec = codec->spec; | |
2286 | ||
2287 | if (spec) { | |
2288 | hdmi_array_free(spec); | |
2289 | kfree(spec); | |
2290 | codec->spec = NULL; | |
2291 | } | |
2292 | codec->dp_mst = false; | |
2293 | } | |
2294 | ||
84eb01be TI |
2295 | static void generic_hdmi_free(struct hda_codec *codec) |
2296 | { | |
2297 | struct hdmi_spec *spec = codec->spec; | |
25e4abb3 | 2298 | int pin_idx, pcm_idx; |
384a48d7 | 2299 | |
6603249d | 2300 | if (codec_has_acomp(codec)) |
a57942bf | 2301 | snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); |
25adc137 | 2302 | |
384a48d7 | 2303 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
bce0d2a8 | 2304 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
2f35c630 | 2305 | cancel_delayed_work_sync(&per_pin->work); |
a4e9a38b | 2306 | eld_proc_free(per_pin); |
25e4abb3 LY |
2307 | } |
2308 | ||
2309 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { | |
2310 | if (spec->pcm_rec[pcm_idx].jack == NULL) | |
2311 | continue; | |
2312 | if (spec->dyn_pcm_assign) | |
2313 | snd_device_free(codec->card, | |
2314 | spec->pcm_rec[pcm_idx].jack); | |
2315 | else | |
2316 | spec->pcm_rec[pcm_idx].jack = NULL; | |
384a48d7 | 2317 | } |
84eb01be | 2318 | |
a686632f | 2319 | generic_spec_free(codec); |
84eb01be TI |
2320 | } |
2321 | ||
28cb72e5 WX |
2322 | #ifdef CONFIG_PM |
2323 | static int generic_hdmi_resume(struct hda_codec *codec) | |
2324 | { | |
2325 | struct hdmi_spec *spec = codec->spec; | |
2326 | int pin_idx; | |
2327 | ||
a2833683 | 2328 | codec->patch_ops.init(codec); |
eeecd9d1 | 2329 | regcache_sync(codec->core.regmap); |
28cb72e5 WX |
2330 | |
2331 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
2332 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
2333 | hdmi_present_sense(per_pin, 1); | |
2334 | } | |
2335 | return 0; | |
2336 | } | |
2337 | #endif | |
2338 | ||
fb79e1e0 | 2339 | static const struct hda_codec_ops generic_hdmi_patch_ops = { |
84eb01be TI |
2340 | .init = generic_hdmi_init, |
2341 | .free = generic_hdmi_free, | |
2342 | .build_pcms = generic_hdmi_build_pcms, | |
2343 | .build_controls = generic_hdmi_build_controls, | |
2344 | .unsol_event = hdmi_unsol_event, | |
28cb72e5 WX |
2345 | #ifdef CONFIG_PM |
2346 | .resume = generic_hdmi_resume, | |
2347 | #endif | |
84eb01be TI |
2348 | }; |
2349 | ||
307229d2 AH |
2350 | static const struct hdmi_ops generic_standard_hdmi_ops = { |
2351 | .pin_get_eld = snd_hdmi_get_eld, | |
307229d2 AH |
2352 | .pin_setup_infoframe = hdmi_pin_setup_infoframe, |
2353 | .pin_hbr_setup = hdmi_pin_hbr_setup, | |
2354 | .setup_stream = hdmi_setup_stream, | |
67b90cb8 SP |
2355 | }; |
2356 | ||
a686632f TI |
2357 | /* allocate codec->spec and assign/initialize generic parser ops */ |
2358 | static int alloc_generic_hdmi(struct hda_codec *codec) | |
2359 | { | |
2360 | struct hdmi_spec *spec; | |
2361 | ||
2362 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
2363 | if (!spec) | |
2364 | return -ENOMEM; | |
2365 | ||
2366 | spec->ops = generic_standard_hdmi_ops; | |
9152085d | 2367 | spec->dev_num = 1; /* initialize to 1 */ |
a686632f TI |
2368 | mutex_init(&spec->pcm_lock); |
2369 | snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); | |
2370 | ||
2371 | spec->chmap.ops.get_chmap = hdmi_get_chmap; | |
2372 | spec->chmap.ops.set_chmap = hdmi_set_chmap; | |
2373 | spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; | |
44fde3b8 | 2374 | spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, |
a686632f TI |
2375 | |
2376 | codec->spec = spec; | |
2377 | hdmi_array_init(spec, 4); | |
2378 | ||
2379 | codec->patch_ops = generic_hdmi_patch_ops; | |
2380 | ||
2381 | return 0; | |
2382 | } | |
2383 | ||
2384 | /* generic HDMI parser */ | |
2385 | static int patch_generic_hdmi(struct hda_codec *codec) | |
2386 | { | |
2387 | int err; | |
2388 | ||
2389 | err = alloc_generic_hdmi(codec); | |
2390 | if (err < 0) | |
2391 | return err; | |
2392 | ||
2393 | err = hdmi_parse_codec(codec); | |
2394 | if (err < 0) { | |
2395 | generic_spec_free(codec); | |
2396 | return err; | |
2397 | } | |
2398 | ||
2399 | generic_hdmi_init_per_pins(codec); | |
2400 | return 0; | |
2401 | } | |
2402 | ||
2403 | /* | |
2404 | * Intel codec parsers and helpers | |
2405 | */ | |
2406 | ||
c88d4e84 TI |
2407 | static void intel_haswell_fixup_connect_list(struct hda_codec *codec, |
2408 | hda_nid_t nid) | |
2409 | { | |
2410 | struct hdmi_spec *spec = codec->spec; | |
2411 | hda_nid_t conns[4]; | |
2412 | int nconns; | |
6ffe168f | 2413 | |
c88d4e84 TI |
2414 | nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns)); |
2415 | if (nconns == spec->num_cvts && | |
2416 | !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t))) | |
6ffe168f ML |
2417 | return; |
2418 | ||
c88d4e84 | 2419 | /* override pins connection list */ |
4e76a883 | 2420 | codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid); |
c88d4e84 | 2421 | snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids); |
6ffe168f ML |
2422 | } |
2423 | ||
b0d8bc50 JK |
2424 | #define INTEL_GET_VENDOR_VERB 0xf81 |
2425 | #define INTEL_GET_VENDOR_VERB 0xf81 | |
2426 | #define INTEL_SET_VENDOR_VERB 0x781 | |
2427 | #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ | |
2428 | #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ | |
1611a9c9 ML |
2429 | |
2430 | static void intel_haswell_enable_all_pins(struct hda_codec *codec, | |
17df3f55 | 2431 | bool update_tree) |
1611a9c9 ML |
2432 | { |
2433 | unsigned int vendor_param; | |
a87a4d23 | 2434 | struct hdmi_spec *spec = codec->spec; |
1611a9c9 | 2435 | |
a87a4d23 | 2436 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
1611a9c9 ML |
2437 | INTEL_GET_VENDOR_VERB, 0); |
2438 | if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) | |
2439 | return; | |
2440 | ||
2441 | vendor_param |= INTEL_EN_ALL_PIN_CVTS; | |
a87a4d23 | 2442 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
1611a9c9 ML |
2443 | INTEL_SET_VENDOR_VERB, vendor_param); |
2444 | if (vendor_param == -1) | |
2445 | return; | |
2446 | ||
17df3f55 TI |
2447 | if (update_tree) |
2448 | snd_hda_codec_update_widgets(codec); | |
1611a9c9 ML |
2449 | } |
2450 | ||
c88d4e84 TI |
2451 | static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) |
2452 | { | |
2453 | unsigned int vendor_param; | |
a87a4d23 | 2454 | struct hdmi_spec *spec = codec->spec; |
c88d4e84 | 2455 | |
a87a4d23 | 2456 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
c88d4e84 TI |
2457 | INTEL_GET_VENDOR_VERB, 0); |
2458 | if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) | |
2459 | return; | |
2460 | ||
2461 | /* enable DP1.2 mode */ | |
2462 | vendor_param |= INTEL_EN_DP12; | |
a551d914 | 2463 | snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); |
a87a4d23 | 2464 | snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, |
c88d4e84 TI |
2465 | INTEL_SET_VENDOR_VERB, vendor_param); |
2466 | } | |
2467 | ||
17df3f55 TI |
2468 | /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. |
2469 | * Otherwise you may get severe h/w communication errors. | |
2470 | */ | |
2471 | static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, | |
2472 | unsigned int power_state) | |
2473 | { | |
2474 | if (power_state == AC_PWRST_D0) { | |
2475 | intel_haswell_enable_all_pins(codec, false); | |
2476 | intel_haswell_fixup_enable_dp12(codec); | |
2477 | } | |
c88d4e84 | 2478 | |
17df3f55 TI |
2479 | snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); |
2480 | snd_hda_codec_set_power_to_all(codec, fg, power_state); | |
2481 | } | |
6ffe168f | 2482 | |
a57942bf TI |
2483 | /* There is a fixed mapping between audio pin node and display port. |
2484 | * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: | |
2485 | * Pin Widget 5 - PORT B (port = 1 in i915 driver) | |
2486 | * Pin Widget 6 - PORT C (port = 2 in i915 driver) | |
2487 | * Pin Widget 7 - PORT D (port = 3 in i915 driver) | |
2488 | * | |
2489 | * on VLV, ILK: | |
2490 | * Pin Widget 4 - PORT B (port = 1 in i915 driver) | |
2491 | * Pin Widget 5 - PORT C (port = 2 in i915 driver) | |
2492 | * Pin Widget 6 - PORT D (port = 3 in i915 driver) | |
2493 | */ | |
2494 | static int intel_base_nid(struct hda_codec *codec) | |
2495 | { | |
2496 | switch (codec->core.vendor_id) { | |
2497 | case 0x80860054: /* ILK */ | |
2498 | case 0x80862804: /* ILK */ | |
2499 | case 0x80862882: /* VLV */ | |
2500 | return 4; | |
2501 | default: | |
2502 | return 5; | |
2503 | } | |
2504 | } | |
2505 | ||
2506 | static int intel_pin2port(void *audio_ptr, int pin_nid) | |
2507 | { | |
b0d8bc50 JK |
2508 | struct hda_codec *codec = audio_ptr; |
2509 | struct hdmi_spec *spec = codec->spec; | |
2510 | int base_nid, i; | |
a57942bf | 2511 | |
b0d8bc50 JK |
2512 | if (!spec->port_num) { |
2513 | base_nid = intel_base_nid(codec); | |
2514 | if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) | |
2515 | return -1; | |
2516 | return pin_nid - base_nid + 1; /* intel port is 1-based */ | |
2517 | } | |
2518 | ||
2519 | /* | |
2520 | * looking for the pin number in the mapping table and return | |
2521 | * the index which indicate the port number | |
2522 | */ | |
2523 | for (i = 0; i < spec->port_num; i++) { | |
2524 | if (pin_nid == spec->port_map[i]) | |
2525 | return i + 1; | |
2526 | } | |
2527 | ||
2528 | /* return -1 if pin number exceeds our expectation */ | |
2529 | codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid); | |
2530 | return -1; | |
a57942bf TI |
2531 | } |
2532 | ||
f9318941 | 2533 | static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) |
25adc137 DH |
2534 | { |
2535 | struct hda_codec *codec = audio_ptr; | |
7ff652ff | 2536 | int pin_nid; |
9152085d | 2537 | int dev_id = pipe; |
25adc137 | 2538 | |
4f8e4f35 TI |
2539 | /* we assume only from port-B to port-D */ |
2540 | if (port < 1 || port > 3) | |
2541 | return; | |
2542 | ||
a57942bf | 2543 | pin_nid = port + intel_base_nid(codec) - 1; /* intel port is 1-based */ |
7ff652ff | 2544 | |
8ae743e8 TI |
2545 | /* skip notification during system suspend (but not in runtime PM); |
2546 | * the state will be updated at resume | |
2547 | */ | |
2548 | if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) | |
2549 | return; | |
eb399d3c | 2550 | /* ditto during suspend/resume process itself */ |
feb20fae | 2551 | if (snd_hdac_is_in_pm(&codec->core)) |
eb399d3c | 2552 | return; |
8ae743e8 | 2553 | |
bb03ed21 | 2554 | snd_hdac_i915_set_bclk(&codec->bus->core); |
9152085d | 2555 | check_presence_and_report(codec, pin_nid, dev_id); |
25adc137 DH |
2556 | } |
2557 | ||
a686632f TI |
2558 | /* register i915 component pin_eld_notify callback */ |
2559 | static void register_i915_notifier(struct hda_codec *codec) | |
84eb01be | 2560 | { |
a686632f | 2561 | struct hdmi_spec *spec = codec->spec; |
84eb01be | 2562 | |
a686632f | 2563 | spec->use_acomp_notifier = true; |
ae891abe | 2564 | spec->drm_audio_ops.audio_ptr = codec; |
a686632f TI |
2565 | /* intel_audio_codec_enable() or intel_audio_codec_disable() |
2566 | * will call pin_eld_notify with using audio_ptr pointer | |
2567 | * We need make sure audio_ptr is really setup | |
2568 | */ | |
2569 | wmb(); | |
a57942bf | 2570 | spec->drm_audio_ops.pin2port = intel_pin2port; |
ae891abe | 2571 | spec->drm_audio_ops.pin_eld_notify = intel_pin_eld_notify; |
a57942bf | 2572 | snd_hdac_acomp_register_notifier(&codec->bus->core, |
82887c0b | 2573 | &spec->drm_audio_ops); |
a686632f | 2574 | } |
84eb01be | 2575 | |
2c1c9b86 TI |
2576 | /* setup_stream ops override for HSW+ */ |
2577 | static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, | |
2578 | hda_nid_t pin_nid, u32 stream_tag, int format) | |
2579 | { | |
2580 | haswell_verify_D0(codec, cvt_nid, pin_nid); | |
2581 | return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); | |
2582 | } | |
739ffee9 | 2583 | |
4846a67e TI |
2584 | /* pin_cvt_fixup ops override for HSW+ and VLV+ */ |
2585 | static void i915_pin_cvt_fixup(struct hda_codec *codec, | |
2586 | struct hdmi_spec_per_pin *per_pin, | |
2587 | hda_nid_t cvt_nid) | |
2588 | { | |
2589 | if (per_pin) { | |
9152085d LY |
2590 | snd_hda_set_dev_select(codec, per_pin->pin_nid, |
2591 | per_pin->dev_id); | |
4846a67e TI |
2592 | intel_verify_pin_cvt_connect(codec, per_pin); |
2593 | intel_not_share_assigned_cvt(codec, per_pin->pin_nid, | |
9152085d | 2594 | per_pin->dev_id, per_pin->mux_idx); |
4846a67e | 2595 | } else { |
9152085d | 2596 | intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); |
4846a67e TI |
2597 | } |
2598 | } | |
739ffee9 | 2599 | |
43f6c8d9 TI |
2600 | /* precondition and allocation for Intel codecs */ |
2601 | static int alloc_intel_hdmi(struct hda_codec *codec) | |
a686632f | 2602 | { |
43f6c8d9 | 2603 | /* requires i915 binding */ |
a686632f TI |
2604 | if (!codec->bus->core.audio_component) { |
2605 | codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); | |
fdd49c51 TI |
2606 | /* set probe_id here to prevent generic fallback binding */ |
2607 | codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; | |
a686632f | 2608 | return -ENODEV; |
691be973 | 2609 | } |
55913110 | 2610 | |
43f6c8d9 TI |
2611 | return alloc_generic_hdmi(codec); |
2612 | } | |
2613 | ||
2614 | /* parse and post-process for Intel codecs */ | |
2615 | static int parse_intel_hdmi(struct hda_codec *codec) | |
2616 | { | |
2617 | int err; | |
2618 | ||
2619 | err = hdmi_parse_codec(codec); | |
2620 | if (err < 0) { | |
2621 | generic_spec_free(codec); | |
2622 | return err; | |
2623 | } | |
2624 | ||
2625 | generic_hdmi_init_per_pins(codec); | |
2626 | register_i915_notifier(codec); | |
2627 | return 0; | |
2628 | } | |
2629 | ||
2630 | /* Intel Haswell and onwards; audio component with eld notifier */ | |
b0d8bc50 JK |
2631 | static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, |
2632 | const int *port_map, int port_num) | |
43f6c8d9 TI |
2633 | { |
2634 | struct hdmi_spec *spec; | |
2635 | int err; | |
2636 | ||
2637 | err = alloc_intel_hdmi(codec); | |
a686632f TI |
2638 | if (err < 0) |
2639 | return err; | |
2640 | spec = codec->spec; | |
9152085d LY |
2641 | codec->dp_mst = true; |
2642 | spec->dyn_pcm_assign = true; | |
a87a4d23 | 2643 | spec->vendor_nid = vendor_nid; |
b0d8bc50 JK |
2644 | spec->port_map = port_map; |
2645 | spec->port_num = port_num; | |
6ffe168f | 2646 | |
a686632f TI |
2647 | intel_haswell_enable_all_pins(codec, true); |
2648 | intel_haswell_fixup_enable_dp12(codec); | |
2649 | ||
46594d33 | 2650 | codec->display_power_control = 1; |
2bd1f73f | 2651 | |
a686632f | 2652 | codec->patch_ops.set_power_state = haswell_set_power_state; |
a686632f TI |
2653 | codec->depop_delay = 0; |
2654 | codec->auto_runtime_pm = 1; | |
2655 | ||
2c1c9b86 | 2656 | spec->ops.setup_stream = i915_hsw_setup_stream; |
4846a67e | 2657 | spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; |
2c1c9b86 | 2658 | |
43f6c8d9 | 2659 | return parse_intel_hdmi(codec); |
a686632f TI |
2660 | } |
2661 | ||
a87a4d23 ACDO |
2662 | static int patch_i915_hsw_hdmi(struct hda_codec *codec) |
2663 | { | |
b0d8bc50 | 2664 | return intel_hsw_common_init(codec, 0x08, NULL, 0); |
a87a4d23 ACDO |
2665 | } |
2666 | ||
2667 | static int patch_i915_glk_hdmi(struct hda_codec *codec) | |
2668 | { | |
b0d8bc50 JK |
2669 | return intel_hsw_common_init(codec, 0x0b, NULL, 0); |
2670 | } | |
2671 | ||
2672 | static int patch_i915_icl_hdmi(struct hda_codec *codec) | |
2673 | { | |
2674 | /* | |
2675 | * pin to port mapping table where the value indicate the pin number and | |
2676 | * the index indicate the port number with 1 base. | |
2677 | */ | |
2678 | static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb}; | |
2679 | ||
2680 | return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); | |
a87a4d23 ACDO |
2681 | } |
2682 | ||
7ff652ff | 2683 | /* Intel Baytrail and Braswell; with eld notifier */ |
a686632f TI |
2684 | static int patch_i915_byt_hdmi(struct hda_codec *codec) |
2685 | { | |
2686 | struct hdmi_spec *spec; | |
2687 | int err; | |
2688 | ||
43f6c8d9 | 2689 | err = alloc_intel_hdmi(codec); |
a686632f TI |
2690 | if (err < 0) |
2691 | return err; | |
2692 | spec = codec->spec; | |
2377c3c3 | 2693 | |
a686632f TI |
2694 | /* For Valleyview/Cherryview, only the display codec is in the display |
2695 | * power well and can use link_power ops to request/release the power. | |
2696 | */ | |
029d92c2 | 2697 | codec->display_power_control = 1; |
84eb01be | 2698 | |
a686632f TI |
2699 | codec->depop_delay = 0; |
2700 | codec->auto_runtime_pm = 1; | |
84eb01be | 2701 | |
4846a67e TI |
2702 | spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; |
2703 | ||
43f6c8d9 | 2704 | return parse_intel_hdmi(codec); |
84eb01be TI |
2705 | } |
2706 | ||
7ff652ff | 2707 | /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ |
e85015a3 TI |
2708 | static int patch_i915_cpt_hdmi(struct hda_codec *codec) |
2709 | { | |
e85015a3 TI |
2710 | int err; |
2711 | ||
43f6c8d9 | 2712 | err = alloc_intel_hdmi(codec); |
e85015a3 TI |
2713 | if (err < 0) |
2714 | return err; | |
43f6c8d9 | 2715 | return parse_intel_hdmi(codec); |
84eb01be TI |
2716 | } |
2717 | ||
3aaf8980 SW |
2718 | /* |
2719 | * Shared non-generic implementations | |
2720 | */ | |
2721 | ||
2722 | static int simple_playback_build_pcms(struct hda_codec *codec) | |
2723 | { | |
2724 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 2725 | struct hda_pcm *info; |
8ceb332d TI |
2726 | unsigned int chans; |
2727 | struct hda_pcm_stream *pstr; | |
bce0d2a8 | 2728 | struct hdmi_spec_per_cvt *per_cvt; |
3aaf8980 | 2729 | |
bce0d2a8 TI |
2730 | per_cvt = get_cvt(spec, 0); |
2731 | chans = get_wcaps(codec, per_cvt->cvt_nid); | |
8ceb332d | 2732 | chans = get_wcaps_channels(chans); |
3aaf8980 | 2733 | |
bbbc7e85 | 2734 | info = snd_hda_codec_pcm_new(codec, "HDMI 0"); |
bce0d2a8 TI |
2735 | if (!info) |
2736 | return -ENOMEM; | |
2bea241a | 2737 | spec->pcm_rec[0].pcm = info; |
8ceb332d TI |
2738 | info->pcm_type = HDA_PCM_TYPE_HDMI; |
2739 | pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; | |
2740 | *pstr = spec->pcm_playback; | |
bce0d2a8 | 2741 | pstr->nid = per_cvt->cvt_nid; |
8ceb332d TI |
2742 | if (pstr->channels_max <= 2 && chans && chans <= 16) |
2743 | pstr->channels_max = chans; | |
3aaf8980 SW |
2744 | |
2745 | return 0; | |
2746 | } | |
2747 | ||
4b6ace9e TI |
2748 | /* unsolicited event for jack sensing */ |
2749 | static void simple_hdmi_unsol_event(struct hda_codec *codec, | |
2750 | unsigned int res) | |
2751 | { | |
9dd8cf12 | 2752 | snd_hda_jack_set_dirty_all(codec); |
4b6ace9e TI |
2753 | snd_hda_jack_report_sync(codec); |
2754 | } | |
2755 | ||
2756 | /* generic_hdmi_build_jack can be used for simple_hdmi, too, | |
2757 | * as long as spec->pins[] is set correctly | |
2758 | */ | |
2759 | #define simple_hdmi_build_jack generic_hdmi_build_jack | |
2760 | ||
3aaf8980 SW |
2761 | static int simple_playback_build_controls(struct hda_codec *codec) |
2762 | { | |
2763 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 2764 | struct hdmi_spec_per_cvt *per_cvt; |
3aaf8980 | 2765 | int err; |
3aaf8980 | 2766 | |
bce0d2a8 | 2767 | per_cvt = get_cvt(spec, 0); |
c9a6338a AH |
2768 | err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, |
2769 | per_cvt->cvt_nid, | |
2770 | HDA_PCM_TYPE_HDMI); | |
8ceb332d TI |
2771 | if (err < 0) |
2772 | return err; | |
2773 | return simple_hdmi_build_jack(codec, 0); | |
3aaf8980 SW |
2774 | } |
2775 | ||
4f0110ce TI |
2776 | static int simple_playback_init(struct hda_codec *codec) |
2777 | { | |
2778 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 TI |
2779 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); |
2780 | hda_nid_t pin = per_pin->pin_nid; | |
8ceb332d TI |
2781 | |
2782 | snd_hda_codec_write(codec, pin, 0, | |
2783 | AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); | |
2784 | /* some codecs require to unmute the pin */ | |
2785 | if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) | |
2786 | snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, | |
2787 | AMP_OUT_UNMUTE); | |
62f949bf | 2788 | snd_hda_jack_detect_enable(codec, pin); |
4f0110ce TI |
2789 | return 0; |
2790 | } | |
2791 | ||
3aaf8980 SW |
2792 | static void simple_playback_free(struct hda_codec *codec) |
2793 | { | |
2794 | struct hdmi_spec *spec = codec->spec; | |
2795 | ||
bce0d2a8 | 2796 | hdmi_array_free(spec); |
3aaf8980 SW |
2797 | kfree(spec); |
2798 | } | |
2799 | ||
84eb01be TI |
2800 | /* |
2801 | * Nvidia specific implementations | |
2802 | */ | |
2803 | ||
2804 | #define Nv_VERB_SET_Channel_Allocation 0xF79 | |
2805 | #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A | |
2806 | #define Nv_VERB_SET_Audio_Protection_On 0xF98 | |
2807 | #define Nv_VERB_SET_Audio_Protection_Off 0xF99 | |
2808 | ||
2809 | #define nvhdmi_master_con_nid_7x 0x04 | |
2810 | #define nvhdmi_master_pin_nid_7x 0x05 | |
2811 | ||
fb79e1e0 | 2812 | static const hda_nid_t nvhdmi_con_nids_7x[4] = { |
84eb01be TI |
2813 | /*front, rear, clfe, rear_surr */ |
2814 | 0x6, 0x8, 0xa, 0xc, | |
2815 | }; | |
2816 | ||
ceaa86ba TI |
2817 | static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { |
2818 | /* set audio protect on */ | |
2819 | { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, | |
2820 | /* enable digital output on pin widget */ | |
2821 | { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2822 | {} /* terminator */ | |
2823 | }; | |
2824 | ||
2825 | static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { | |
84eb01be TI |
2826 | /* set audio protect on */ |
2827 | { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, | |
2828 | /* enable digital output on pin widget */ | |
2829 | { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2830 | { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2831 | { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2832 | { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2833 | { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2834 | {} /* terminator */ | |
2835 | }; | |
2836 | ||
2837 | #ifdef LIMITED_RATE_FMT_SUPPORT | |
2838 | /* support only the safe format and rate */ | |
2839 | #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 | |
2840 | #define SUPPORTED_MAXBPS 16 | |
2841 | #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE | |
2842 | #else | |
2843 | /* support all rates and formats */ | |
2844 | #define SUPPORTED_RATES \ | |
2845 | (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ | |
2846 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ | |
2847 | SNDRV_PCM_RATE_192000) | |
2848 | #define SUPPORTED_MAXBPS 24 | |
2849 | #define SUPPORTED_FORMATS \ | |
2850 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
2851 | #endif | |
2852 | ||
ceaa86ba TI |
2853 | static int nvhdmi_7x_init_2ch(struct hda_codec *codec) |
2854 | { | |
2855 | snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); | |
2856 | return 0; | |
2857 | } | |
2858 | ||
2859 | static int nvhdmi_7x_init_8ch(struct hda_codec *codec) | |
84eb01be | 2860 | { |
ceaa86ba | 2861 | snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); |
84eb01be TI |
2862 | return 0; |
2863 | } | |
2864 | ||
50c697ad | 2865 | static const unsigned int channels_2_6_8[] = { |
393004b2 ND |
2866 | 2, 6, 8 |
2867 | }; | |
2868 | ||
50c697ad | 2869 | static const unsigned int channels_2_8[] = { |
393004b2 ND |
2870 | 2, 8 |
2871 | }; | |
2872 | ||
50c697ad | 2873 | static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { |
393004b2 ND |
2874 | .count = ARRAY_SIZE(channels_2_6_8), |
2875 | .list = channels_2_6_8, | |
2876 | .mask = 0, | |
2877 | }; | |
2878 | ||
50c697ad | 2879 | static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { |
393004b2 ND |
2880 | .count = ARRAY_SIZE(channels_2_8), |
2881 | .list = channels_2_8, | |
2882 | .mask = 0, | |
2883 | }; | |
2884 | ||
84eb01be TI |
2885 | static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, |
2886 | struct hda_codec *codec, | |
2887 | struct snd_pcm_substream *substream) | |
2888 | { | |
2889 | struct hdmi_spec *spec = codec->spec; | |
50c697ad | 2890 | const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; |
393004b2 | 2891 | |
b9a94a9c | 2892 | switch (codec->preset->vendor_id) { |
393004b2 ND |
2893 | case 0x10de0002: |
2894 | case 0x10de0003: | |
2895 | case 0x10de0005: | |
2896 | case 0x10de0006: | |
2897 | hw_constraints_channels = &hw_constraints_2_8_channels; | |
2898 | break; | |
2899 | case 0x10de0007: | |
2900 | hw_constraints_channels = &hw_constraints_2_6_8_channels; | |
2901 | break; | |
2902 | default: | |
2903 | break; | |
2904 | } | |
2905 | ||
2906 | if (hw_constraints_channels != NULL) { | |
2907 | snd_pcm_hw_constraint_list(substream->runtime, 0, | |
2908 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
2909 | hw_constraints_channels); | |
ad09fc9d TI |
2910 | } else { |
2911 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
2912 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
393004b2 ND |
2913 | } |
2914 | ||
84eb01be TI |
2915 | return snd_hda_multi_out_dig_open(codec, &spec->multiout); |
2916 | } | |
2917 | ||
2918 | static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, | |
2919 | struct hda_codec *codec, | |
2920 | struct snd_pcm_substream *substream) | |
2921 | { | |
2922 | struct hdmi_spec *spec = codec->spec; | |
2923 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); | |
2924 | } | |
2925 | ||
2926 | static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
2927 | struct hda_codec *codec, | |
2928 | unsigned int stream_tag, | |
2929 | unsigned int format, | |
2930 | struct snd_pcm_substream *substream) | |
2931 | { | |
2932 | struct hdmi_spec *spec = codec->spec; | |
2933 | return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, | |
2934 | stream_tag, format, substream); | |
2935 | } | |
2936 | ||
d0b1252d TI |
2937 | static const struct hda_pcm_stream simple_pcm_playback = { |
2938 | .substreams = 1, | |
2939 | .channels_min = 2, | |
2940 | .channels_max = 2, | |
2941 | .ops = { | |
2942 | .open = simple_playback_pcm_open, | |
2943 | .close = simple_playback_pcm_close, | |
2944 | .prepare = simple_playback_pcm_prepare | |
2945 | }, | |
2946 | }; | |
2947 | ||
2948 | static const struct hda_codec_ops simple_hdmi_patch_ops = { | |
2949 | .build_controls = simple_playback_build_controls, | |
2950 | .build_pcms = simple_playback_build_pcms, | |
2951 | .init = simple_playback_init, | |
2952 | .free = simple_playback_free, | |
250e41ac | 2953 | .unsol_event = simple_hdmi_unsol_event, |
d0b1252d TI |
2954 | }; |
2955 | ||
2956 | static int patch_simple_hdmi(struct hda_codec *codec, | |
2957 | hda_nid_t cvt_nid, hda_nid_t pin_nid) | |
2958 | { | |
2959 | struct hdmi_spec *spec; | |
bce0d2a8 TI |
2960 | struct hdmi_spec_per_cvt *per_cvt; |
2961 | struct hdmi_spec_per_pin *per_pin; | |
d0b1252d TI |
2962 | |
2963 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
2964 | if (!spec) | |
2965 | return -ENOMEM; | |
2966 | ||
2967 | codec->spec = spec; | |
bce0d2a8 | 2968 | hdmi_array_init(spec, 1); |
d0b1252d TI |
2969 | |
2970 | spec->multiout.num_dacs = 0; /* no analog */ | |
2971 | spec->multiout.max_channels = 2; | |
2972 | spec->multiout.dig_out_nid = cvt_nid; | |
2973 | spec->num_cvts = 1; | |
2974 | spec->num_pins = 1; | |
bce0d2a8 TI |
2975 | per_pin = snd_array_new(&spec->pins); |
2976 | per_cvt = snd_array_new(&spec->cvts); | |
2977 | if (!per_pin || !per_cvt) { | |
2978 | simple_playback_free(codec); | |
2979 | return -ENOMEM; | |
2980 | } | |
2981 | per_cvt->cvt_nid = cvt_nid; | |
2982 | per_pin->pin_nid = pin_nid; | |
d0b1252d TI |
2983 | spec->pcm_playback = simple_pcm_playback; |
2984 | ||
2985 | codec->patch_ops = simple_hdmi_patch_ops; | |
2986 | ||
2987 | return 0; | |
2988 | } | |
2989 | ||
1f348522 AP |
2990 | static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, |
2991 | int channels) | |
2992 | { | |
2993 | unsigned int chanmask; | |
2994 | int chan = channels ? (channels - 1) : 1; | |
2995 | ||
2996 | switch (channels) { | |
2997 | default: | |
2998 | case 0: | |
2999 | case 2: | |
3000 | chanmask = 0x00; | |
3001 | break; | |
3002 | case 4: | |
3003 | chanmask = 0x08; | |
3004 | break; | |
3005 | case 6: | |
3006 | chanmask = 0x0b; | |
3007 | break; | |
3008 | case 8: | |
3009 | chanmask = 0x13; | |
3010 | break; | |
3011 | } | |
3012 | ||
3013 | /* Set the audio infoframe channel allocation and checksum fields. The | |
3014 | * channel count is computed implicitly by the hardware. */ | |
3015 | snd_hda_codec_write(codec, 0x1, 0, | |
3016 | Nv_VERB_SET_Channel_Allocation, chanmask); | |
3017 | ||
3018 | snd_hda_codec_write(codec, 0x1, 0, | |
3019 | Nv_VERB_SET_Info_Frame_Checksum, | |
3020 | (0x71 - chan - chanmask)); | |
3021 | } | |
3022 | ||
84eb01be TI |
3023 | static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, |
3024 | struct hda_codec *codec, | |
3025 | struct snd_pcm_substream *substream) | |
3026 | { | |
3027 | struct hdmi_spec *spec = codec->spec; | |
3028 | int i; | |
3029 | ||
3030 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, | |
3031 | 0, AC_VERB_SET_CHANNEL_STREAMID, 0); | |
3032 | for (i = 0; i < 4; i++) { | |
3033 | /* set the stream id */ | |
3034 | snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, | |
3035 | AC_VERB_SET_CHANNEL_STREAMID, 0); | |
3036 | /* set the stream format */ | |
3037 | snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, | |
3038 | AC_VERB_SET_STREAM_FORMAT, 0); | |
3039 | } | |
3040 | ||
1f348522 AP |
3041 | /* The audio hardware sends a channel count of 0x7 (8ch) when all the |
3042 | * streams are disabled. */ | |
3043 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); | |
3044 | ||
84eb01be TI |
3045 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); |
3046 | } | |
3047 | ||
3048 | static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3049 | struct hda_codec *codec, | |
3050 | unsigned int stream_tag, | |
3051 | unsigned int format, | |
3052 | struct snd_pcm_substream *substream) | |
3053 | { | |
3054 | int chs; | |
112daa7a | 3055 | unsigned int dataDCC2, channel_id; |
84eb01be | 3056 | int i; |
7c935976 | 3057 | struct hdmi_spec *spec = codec->spec; |
e3245cdd | 3058 | struct hda_spdif_out *spdif; |
bce0d2a8 | 3059 | struct hdmi_spec_per_cvt *per_cvt; |
84eb01be TI |
3060 | |
3061 | mutex_lock(&codec->spdif_mutex); | |
bce0d2a8 TI |
3062 | per_cvt = get_cvt(spec, 0); |
3063 | spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); | |
84eb01be TI |
3064 | |
3065 | chs = substream->runtime->channels; | |
84eb01be | 3066 | |
84eb01be TI |
3067 | dataDCC2 = 0x2; |
3068 | ||
84eb01be | 3069 | /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ |
7c935976 | 3070 | if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) |
84eb01be TI |
3071 | snd_hda_codec_write(codec, |
3072 | nvhdmi_master_con_nid_7x, | |
3073 | 0, | |
3074 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3075 | spdif->ctls & ~AC_DIG1_ENABLE & 0xff); |
84eb01be TI |
3076 | |
3077 | /* set the stream id */ | |
3078 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, | |
3079 | AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); | |
3080 | ||
3081 | /* set the stream format */ | |
3082 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, | |
3083 | AC_VERB_SET_STREAM_FORMAT, format); | |
3084 | ||
3085 | /* turn on again (if needed) */ | |
3086 | /* enable and set the channel status audio/data flag */ | |
7c935976 | 3087 | if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { |
84eb01be TI |
3088 | snd_hda_codec_write(codec, |
3089 | nvhdmi_master_con_nid_7x, | |
3090 | 0, | |
3091 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3092 | spdif->ctls & 0xff); |
84eb01be TI |
3093 | snd_hda_codec_write(codec, |
3094 | nvhdmi_master_con_nid_7x, | |
3095 | 0, | |
3096 | AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); | |
3097 | } | |
3098 | ||
3099 | for (i = 0; i < 4; i++) { | |
3100 | if (chs == 2) | |
3101 | channel_id = 0; | |
3102 | else | |
3103 | channel_id = i * 2; | |
3104 | ||
3105 | /* turn off SPDIF once; | |
3106 | *otherwise the IEC958 bits won't be updated | |
3107 | */ | |
3108 | if (codec->spdif_status_reset && | |
7c935976 | 3109 | (spdif->ctls & AC_DIG1_ENABLE)) |
84eb01be TI |
3110 | snd_hda_codec_write(codec, |
3111 | nvhdmi_con_nids_7x[i], | |
3112 | 0, | |
3113 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3114 | spdif->ctls & ~AC_DIG1_ENABLE & 0xff); |
84eb01be TI |
3115 | /* set the stream id */ |
3116 | snd_hda_codec_write(codec, | |
3117 | nvhdmi_con_nids_7x[i], | |
3118 | 0, | |
3119 | AC_VERB_SET_CHANNEL_STREAMID, | |
3120 | (stream_tag << 4) | channel_id); | |
3121 | /* set the stream format */ | |
3122 | snd_hda_codec_write(codec, | |
3123 | nvhdmi_con_nids_7x[i], | |
3124 | 0, | |
3125 | AC_VERB_SET_STREAM_FORMAT, | |
3126 | format); | |
3127 | /* turn on again (if needed) */ | |
3128 | /* enable and set the channel status audio/data flag */ | |
3129 | if (codec->spdif_status_reset && | |
7c935976 | 3130 | (spdif->ctls & AC_DIG1_ENABLE)) { |
84eb01be TI |
3131 | snd_hda_codec_write(codec, |
3132 | nvhdmi_con_nids_7x[i], | |
3133 | 0, | |
3134 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3135 | spdif->ctls & 0xff); |
84eb01be TI |
3136 | snd_hda_codec_write(codec, |
3137 | nvhdmi_con_nids_7x[i], | |
3138 | 0, | |
3139 | AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); | |
3140 | } | |
3141 | } | |
3142 | ||
1f348522 | 3143 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); |
84eb01be TI |
3144 | |
3145 | mutex_unlock(&codec->spdif_mutex); | |
3146 | return 0; | |
3147 | } | |
3148 | ||
fb79e1e0 | 3149 | static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { |
84eb01be TI |
3150 | .substreams = 1, |
3151 | .channels_min = 2, | |
3152 | .channels_max = 8, | |
3153 | .nid = nvhdmi_master_con_nid_7x, | |
3154 | .rates = SUPPORTED_RATES, | |
3155 | .maxbps = SUPPORTED_MAXBPS, | |
3156 | .formats = SUPPORTED_FORMATS, | |
3157 | .ops = { | |
3158 | .open = simple_playback_pcm_open, | |
3159 | .close = nvhdmi_8ch_7x_pcm_close, | |
3160 | .prepare = nvhdmi_8ch_7x_pcm_prepare | |
3161 | }, | |
3162 | }; | |
3163 | ||
84eb01be TI |
3164 | static int patch_nvhdmi_2ch(struct hda_codec *codec) |
3165 | { | |
3166 | struct hdmi_spec *spec; | |
d0b1252d TI |
3167 | int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, |
3168 | nvhdmi_master_pin_nid_7x); | |
3169 | if (err < 0) | |
3170 | return err; | |
84eb01be | 3171 | |
ceaa86ba | 3172 | codec->patch_ops.init = nvhdmi_7x_init_2ch; |
d0b1252d TI |
3173 | /* override the PCM rates, etc, as the codec doesn't give full list */ |
3174 | spec = codec->spec; | |
3175 | spec->pcm_playback.rates = SUPPORTED_RATES; | |
3176 | spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; | |
3177 | spec->pcm_playback.formats = SUPPORTED_FORMATS; | |
84eb01be TI |
3178 | return 0; |
3179 | } | |
3180 | ||
53775b0d TI |
3181 | static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) |
3182 | { | |
3183 | struct hdmi_spec *spec = codec->spec; | |
3184 | int err = simple_playback_build_pcms(codec); | |
bce0d2a8 TI |
3185 | if (!err) { |
3186 | struct hda_pcm *info = get_pcm_rec(spec, 0); | |
3187 | info->own_chmap = true; | |
3188 | } | |
53775b0d TI |
3189 | return err; |
3190 | } | |
3191 | ||
3192 | static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) | |
3193 | { | |
3194 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 3195 | struct hda_pcm *info; |
53775b0d TI |
3196 | struct snd_pcm_chmap *chmap; |
3197 | int err; | |
3198 | ||
3199 | err = simple_playback_build_controls(codec); | |
3200 | if (err < 0) | |
3201 | return err; | |
3202 | ||
3203 | /* add channel maps */ | |
bce0d2a8 TI |
3204 | info = get_pcm_rec(spec, 0); |
3205 | err = snd_pcm_add_chmap_ctls(info->pcm, | |
53775b0d TI |
3206 | SNDRV_PCM_STREAM_PLAYBACK, |
3207 | snd_pcm_alt_chmaps, 8, 0, &chmap); | |
3208 | if (err < 0) | |
3209 | return err; | |
b9a94a9c | 3210 | switch (codec->preset->vendor_id) { |
53775b0d TI |
3211 | case 0x10de0002: |
3212 | case 0x10de0003: | |
3213 | case 0x10de0005: | |
3214 | case 0x10de0006: | |
3215 | chmap->channel_mask = (1U << 2) | (1U << 8); | |
3216 | break; | |
3217 | case 0x10de0007: | |
3218 | chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); | |
3219 | } | |
3220 | return 0; | |
3221 | } | |
3222 | ||
84eb01be TI |
3223 | static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) |
3224 | { | |
3225 | struct hdmi_spec *spec; | |
3226 | int err = patch_nvhdmi_2ch(codec); | |
84eb01be TI |
3227 | if (err < 0) |
3228 | return err; | |
3229 | spec = codec->spec; | |
3230 | spec->multiout.max_channels = 8; | |
d0b1252d | 3231 | spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; |
ceaa86ba | 3232 | codec->patch_ops.init = nvhdmi_7x_init_8ch; |
53775b0d TI |
3233 | codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; |
3234 | codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; | |
1f348522 AP |
3235 | |
3236 | /* Initialize the audio infoframe channel mask and checksum to something | |
3237 | * valid */ | |
3238 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); | |
3239 | ||
84eb01be TI |
3240 | return 0; |
3241 | } | |
3242 | ||
611885bc AH |
3243 | /* |
3244 | * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: | |
3245 | * - 0x10de0015 | |
3246 | * - 0x10de0040 | |
3247 | */ | |
67b90cb8 | 3248 | static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, |
f302240d | 3249 | struct hdac_cea_channel_speaker_allocation *cap, int channels) |
611885bc AH |
3250 | { |
3251 | if (cap->ca_index == 0x00 && channels == 2) | |
3252 | return SNDRV_CTL_TLVT_CHMAP_FIXED; | |
3253 | ||
028cb68e SP |
3254 | /* If the speaker allocation matches the channel count, it is OK. */ |
3255 | if (cap->channels != channels) | |
3256 | return -1; | |
3257 | ||
3258 | /* all channels are remappable freely */ | |
3259 | return SNDRV_CTL_TLVT_CHMAP_VAR; | |
611885bc AH |
3260 | } |
3261 | ||
828cb4ed SP |
3262 | static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, |
3263 | int ca, int chs, unsigned char *map) | |
611885bc AH |
3264 | { |
3265 | if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) | |
3266 | return -EINVAL; | |
3267 | ||
3268 | return 0; | |
3269 | } | |
3270 | ||
3271 | static int patch_nvhdmi(struct hda_codec *codec) | |
3272 | { | |
3273 | struct hdmi_spec *spec; | |
3274 | int err; | |
3275 | ||
3276 | err = patch_generic_hdmi(codec); | |
3277 | if (err) | |
3278 | return err; | |
3279 | ||
3280 | spec = codec->spec; | |
75fae117 | 3281 | spec->dyn_pin_out = true; |
611885bc | 3282 | |
67b90cb8 | 3283 | spec->chmap.ops.chmap_cea_alloc_validate_get_type = |
611885bc | 3284 | nvhdmi_chmap_cea_alloc_validate_get_type; |
67b90cb8 | 3285 | spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; |
611885bc AH |
3286 | |
3287 | return 0; | |
3288 | } | |
3289 | ||
26e9a960 TR |
3290 | /* |
3291 | * The HDA codec on NVIDIA Tegra contains two scratch registers that are | |
3292 | * accessed using vendor-defined verbs. These registers can be used for | |
3293 | * interoperability between the HDA and HDMI drivers. | |
3294 | */ | |
3295 | ||
3296 | /* Audio Function Group node */ | |
3297 | #define NVIDIA_AFG_NID 0x01 | |
3298 | ||
3299 | /* | |
3300 | * The SCRATCH0 register is used to notify the HDMI codec of changes in audio | |
3301 | * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to | |
3302 | * be raised in the HDMI codec. The remainder of the bits is arbitrary. This | |
3303 | * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an | |
3304 | * additional bit (at position 30) to signal the validity of the format. | |
3305 | * | |
3306 | * | 31 | 30 | 29 16 | 15 0 | | |
3307 | * +---------+-------+--------+--------+ | |
3308 | * | TRIGGER | VALID | UNUSED | FORMAT | | |
3309 | * +-----------------------------------| | |
3310 | * | |
3311 | * Note that for the trigger bit to take effect it needs to change value | |
3312 | * (i.e. it needs to be toggled). | |
3313 | */ | |
3314 | #define NVIDIA_GET_SCRATCH0 0xfa6 | |
3315 | #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 | |
3316 | #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 | |
3317 | #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 | |
3318 | #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa | |
3319 | #define NVIDIA_SCRATCH_TRIGGER (1 << 7) | |
3320 | #define NVIDIA_SCRATCH_VALID (1 << 6) | |
3321 | ||
3322 | #define NVIDIA_GET_SCRATCH1 0xfab | |
3323 | #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac | |
3324 | #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad | |
3325 | #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae | |
3326 | #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf | |
3327 | ||
3328 | /* | |
3329 | * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, | |
3330 | * the format is invalidated so that the HDMI codec can be disabled. | |
3331 | */ | |
3332 | static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) | |
3333 | { | |
3334 | unsigned int value; | |
3335 | ||
3336 | /* bits [31:30] contain the trigger and valid bits */ | |
3337 | value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, | |
3338 | NVIDIA_GET_SCRATCH0, 0); | |
3339 | value = (value >> 24) & 0xff; | |
3340 | ||
3341 | /* bits [15:0] are used to store the HDA format */ | |
3342 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3343 | NVIDIA_SET_SCRATCH0_BYTE0, | |
3344 | (format >> 0) & 0xff); | |
3345 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3346 | NVIDIA_SET_SCRATCH0_BYTE1, | |
3347 | (format >> 8) & 0xff); | |
3348 | ||
3349 | /* bits [16:24] are unused */ | |
3350 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3351 | NVIDIA_SET_SCRATCH0_BYTE2, 0); | |
3352 | ||
3353 | /* | |
3354 | * Bit 30 signals that the data is valid and hence that HDMI audio can | |
3355 | * be enabled. | |
3356 | */ | |
3357 | if (format == 0) | |
3358 | value &= ~NVIDIA_SCRATCH_VALID; | |
3359 | else | |
3360 | value |= NVIDIA_SCRATCH_VALID; | |
3361 | ||
3362 | /* | |
3363 | * Whenever the trigger bit is toggled, an interrupt is raised in the | |
3364 | * HDMI codec. The HDMI driver will use that as trigger to update its | |
3365 | * configuration. | |
3366 | */ | |
3367 | value ^= NVIDIA_SCRATCH_TRIGGER; | |
3368 | ||
3369 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3370 | NVIDIA_SET_SCRATCH0_BYTE3, value); | |
3371 | } | |
3372 | ||
3373 | static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3374 | struct hda_codec *codec, | |
3375 | unsigned int stream_tag, | |
3376 | unsigned int format, | |
3377 | struct snd_pcm_substream *substream) | |
3378 | { | |
3379 | int err; | |
3380 | ||
3381 | err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, | |
3382 | format, substream); | |
3383 | if (err < 0) | |
3384 | return err; | |
3385 | ||
3386 | /* notify the HDMI codec of the format change */ | |
3387 | tegra_hdmi_set_format(codec, format); | |
3388 | ||
3389 | return 0; | |
3390 | } | |
3391 | ||
3392 | static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, | |
3393 | struct hda_codec *codec, | |
3394 | struct snd_pcm_substream *substream) | |
3395 | { | |
3396 | /* invalidate the format in the HDMI codec */ | |
3397 | tegra_hdmi_set_format(codec, 0); | |
3398 | ||
3399 | return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); | |
3400 | } | |
3401 | ||
3402 | static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) | |
3403 | { | |
3404 | struct hdmi_spec *spec = codec->spec; | |
3405 | unsigned int i; | |
3406 | ||
3407 | for (i = 0; i < spec->num_pins; i++) { | |
3408 | struct hda_pcm *pcm = get_pcm_rec(spec, i); | |
3409 | ||
3410 | if (pcm->pcm_type == type) | |
3411 | return pcm; | |
3412 | } | |
3413 | ||
3414 | return NULL; | |
3415 | } | |
3416 | ||
3417 | static int tegra_hdmi_build_pcms(struct hda_codec *codec) | |
3418 | { | |
3419 | struct hda_pcm_stream *stream; | |
3420 | struct hda_pcm *pcm; | |
3421 | int err; | |
3422 | ||
3423 | err = generic_hdmi_build_pcms(codec); | |
3424 | if (err < 0) | |
3425 | return err; | |
3426 | ||
3427 | pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); | |
3428 | if (!pcm) | |
3429 | return -ENODEV; | |
3430 | ||
3431 | /* | |
3432 | * Override ->prepare() and ->cleanup() operations to notify the HDMI | |
3433 | * codec about format changes. | |
3434 | */ | |
3435 | stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; | |
3436 | stream->ops.prepare = tegra_hdmi_pcm_prepare; | |
3437 | stream->ops.cleanup = tegra_hdmi_pcm_cleanup; | |
3438 | ||
3439 | return 0; | |
3440 | } | |
3441 | ||
3442 | static int patch_tegra_hdmi(struct hda_codec *codec) | |
3443 | { | |
3444 | int err; | |
3445 | ||
3446 | err = patch_generic_hdmi(codec); | |
3447 | if (err) | |
3448 | return err; | |
3449 | ||
3450 | codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; | |
3451 | ||
3452 | return 0; | |
3453 | } | |
3454 | ||
84eb01be | 3455 | /* |
5a613584 | 3456 | * ATI/AMD-specific implementations |
84eb01be TI |
3457 | */ |
3458 | ||
5a613584 | 3459 | #define is_amdhdmi_rev3_or_later(codec) \ |
7639a06c TI |
3460 | ((codec)->core.vendor_id == 0x1002aa01 && \ |
3461 | ((codec)->core.revision_id & 0xff00) >= 0x0300) | |
5a613584 AH |
3462 | #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) |
3463 | ||
3464 | /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ | |
3465 | #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 | |
3466 | #define ATI_VERB_SET_DOWNMIX_INFO 0x772 | |
3467 | #define ATI_VERB_SET_MULTICHANNEL_01 0x777 | |
3468 | #define ATI_VERB_SET_MULTICHANNEL_23 0x778 | |
3469 | #define ATI_VERB_SET_MULTICHANNEL_45 0x779 | |
3470 | #define ATI_VERB_SET_MULTICHANNEL_67 0x77a | |
461cf6b3 | 3471 | #define ATI_VERB_SET_HBR_CONTROL 0x77c |
5a613584 AH |
3472 | #define ATI_VERB_SET_MULTICHANNEL_1 0x785 |
3473 | #define ATI_VERB_SET_MULTICHANNEL_3 0x786 | |
3474 | #define ATI_VERB_SET_MULTICHANNEL_5 0x787 | |
3475 | #define ATI_VERB_SET_MULTICHANNEL_7 0x788 | |
3476 | #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 | |
3477 | #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 | |
3478 | #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 | |
3479 | #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 | |
3480 | #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 | |
3481 | #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 | |
3482 | #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a | |
461cf6b3 | 3483 | #define ATI_VERB_GET_HBR_CONTROL 0xf7c |
5a613584 AH |
3484 | #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 |
3485 | #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 | |
3486 | #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 | |
3487 | #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 | |
3488 | #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 | |
3489 | ||
84d69e79 AH |
3490 | /* AMD specific HDA cvt verbs */ |
3491 | #define ATI_VERB_SET_RAMP_RATE 0x770 | |
3492 | #define ATI_VERB_GET_RAMP_RATE 0xf70 | |
3493 | ||
5a613584 AH |
3494 | #define ATI_OUT_ENABLE 0x1 |
3495 | ||
3496 | #define ATI_MULTICHANNEL_MODE_PAIRED 0 | |
3497 | #define ATI_MULTICHANNEL_MODE_SINGLE 1 | |
3498 | ||
461cf6b3 AH |
3499 | #define ATI_HBR_CAPABLE 0x01 |
3500 | #define ATI_HBR_ENABLE 0x10 | |
3501 | ||
89250f84 AH |
3502 | static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, |
3503 | unsigned char *buf, int *eld_size) | |
3504 | { | |
3505 | /* call hda_eld.c ATI/AMD-specific function */ | |
3506 | return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, | |
3507 | is_amdhdmi_rev3_or_later(codec)); | |
3508 | } | |
3509 | ||
5a613584 AH |
3510 | static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca, |
3511 | int active_channels, int conn_type) | |
3512 | { | |
3513 | snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); | |
3514 | } | |
3515 | ||
3516 | static int atihdmi_paired_swap_fc_lfe(int pos) | |
3517 | { | |
3518 | /* | |
3519 | * ATI/AMD have automatic FC/LFE swap built-in | |
3520 | * when in pairwise mapping mode. | |
3521 | */ | |
3522 | ||
3523 | switch (pos) { | |
3524 | /* see channel_allocations[].speakers[] */ | |
3525 | case 2: return 3; | |
3526 | case 3: return 2; | |
3527 | default: break; | |
3528 | } | |
3529 | ||
3530 | return pos; | |
3531 | } | |
3532 | ||
828cb4ed SP |
3533 | static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, |
3534 | int ca, int chs, unsigned char *map) | |
5a613584 | 3535 | { |
f302240d | 3536 | struct hdac_cea_channel_speaker_allocation *cap; |
5a613584 AH |
3537 | int i, j; |
3538 | ||
3539 | /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ | |
3540 | ||
bb63f726 | 3541 | cap = snd_hdac_get_ch_alloc_from_ca(ca); |
5a613584 | 3542 | for (i = 0; i < chs; ++i) { |
bb63f726 | 3543 | int mask = snd_hdac_chmap_to_spk_mask(map[i]); |
5a613584 AH |
3544 | bool ok = false; |
3545 | bool companion_ok = false; | |
3546 | ||
3547 | if (!mask) | |
3548 | continue; | |
3549 | ||
3550 | for (j = 0 + i % 2; j < 8; j += 2) { | |
3551 | int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); | |
3552 | if (cap->speakers[chan_idx] == mask) { | |
3553 | /* channel is in a supported position */ | |
3554 | ok = true; | |
3555 | ||
3556 | if (i % 2 == 0 && i + 1 < chs) { | |
3557 | /* even channel, check the odd companion */ | |
3558 | int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); | |
bb63f726 | 3559 | int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); |
5a613584 AH |
3560 | int comp_mask_act = cap->speakers[comp_chan_idx]; |
3561 | ||
3562 | if (comp_mask_req == comp_mask_act) | |
3563 | companion_ok = true; | |
3564 | else | |
3565 | return -EINVAL; | |
3566 | } | |
3567 | break; | |
3568 | } | |
3569 | } | |
3570 | ||
3571 | if (!ok) | |
3572 | return -EINVAL; | |
3573 | ||
3574 | if (companion_ok) | |
3575 | i++; /* companion channel already checked */ | |
3576 | } | |
3577 | ||
3578 | return 0; | |
3579 | } | |
3580 | ||
739ffee9 SP |
3581 | static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, |
3582 | hda_nid_t pin_nid, int hdmi_slot, int stream_channel) | |
5a613584 | 3583 | { |
739ffee9 | 3584 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); |
5a613584 AH |
3585 | int verb; |
3586 | int ati_channel_setup = 0; | |
3587 | ||
3588 | if (hdmi_slot > 7) | |
3589 | return -EINVAL; | |
3590 | ||
3591 | if (!has_amd_full_remap_support(codec)) { | |
3592 | hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); | |
3593 | ||
3594 | /* In case this is an odd slot but without stream channel, do not | |
3595 | * disable the slot since the corresponding even slot could have a | |
3596 | * channel. In case neither have a channel, the slot pair will be | |
3597 | * disabled when this function is called for the even slot. */ | |
3598 | if (hdmi_slot % 2 != 0 && stream_channel == 0xf) | |
3599 | return 0; | |
3600 | ||
3601 | hdmi_slot -= hdmi_slot % 2; | |
3602 | ||
3603 | if (stream_channel != 0xf) | |
3604 | stream_channel -= stream_channel % 2; | |
3605 | } | |
3606 | ||
3607 | verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; | |
3608 | ||
3609 | /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ | |
3610 | ||
3611 | if (stream_channel != 0xf) | |
3612 | ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; | |
3613 | ||
3614 | return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); | |
3615 | } | |
3616 | ||
739ffee9 SP |
3617 | static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, |
3618 | hda_nid_t pin_nid, int asp_slot) | |
5a613584 | 3619 | { |
739ffee9 | 3620 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); |
5a613584 AH |
3621 | bool was_odd = false; |
3622 | int ati_asp_slot = asp_slot; | |
3623 | int verb; | |
3624 | int ati_channel_setup; | |
3625 | ||
3626 | if (asp_slot > 7) | |
3627 | return -EINVAL; | |
3628 | ||
3629 | if (!has_amd_full_remap_support(codec)) { | |
3630 | ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); | |
3631 | if (ati_asp_slot % 2 != 0) { | |
3632 | ati_asp_slot -= 1; | |
3633 | was_odd = true; | |
3634 | } | |
3635 | } | |
3636 | ||
3637 | verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; | |
3638 | ||
3639 | ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); | |
3640 | ||
3641 | if (!(ati_channel_setup & ATI_OUT_ENABLE)) | |
3642 | return 0xf; | |
3643 | ||
3644 | return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; | |
3645 | } | |
84eb01be | 3646 | |
67b90cb8 SP |
3647 | static int atihdmi_paired_chmap_cea_alloc_validate_get_type( |
3648 | struct hdac_chmap *chmap, | |
f302240d | 3649 | struct hdac_cea_channel_speaker_allocation *cap, |
67b90cb8 | 3650 | int channels) |
5a613584 AH |
3651 | { |
3652 | int c; | |
3653 | ||
3654 | /* | |
3655 | * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so | |
3656 | * we need to take that into account (a single channel may take 2 | |
3657 | * channel slots if we need to carry a silent channel next to it). | |
3658 | * On Rev3+ AMD codecs this function is not used. | |
3659 | */ | |
3660 | int chanpairs = 0; | |
3661 | ||
3662 | /* We only produce even-numbered channel count TLVs */ | |
3663 | if ((channels % 2) != 0) | |
3664 | return -1; | |
3665 | ||
3666 | for (c = 0; c < 7; c += 2) { | |
3667 | if (cap->speakers[c] || cap->speakers[c+1]) | |
3668 | chanpairs++; | |
3669 | } | |
3670 | ||
3671 | if (chanpairs * 2 != channels) | |
3672 | return -1; | |
3673 | ||
3674 | return SNDRV_CTL_TLVT_CHMAP_PAIRED; | |
3675 | } | |
3676 | ||
828cb4ed | 3677 | static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, |
f302240d SP |
3678 | struct hdac_cea_channel_speaker_allocation *cap, |
3679 | unsigned int *chmap, int channels) | |
5a613584 AH |
3680 | { |
3681 | /* produce paired maps for pre-rev3 ATI/AMD codecs */ | |
3682 | int count = 0; | |
3683 | int c; | |
3684 | ||
3685 | for (c = 7; c >= 0; c--) { | |
3686 | int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); | |
3687 | int spk = cap->speakers[chan]; | |
3688 | if (!spk) { | |
3689 | /* add N/A channel if the companion channel is occupied */ | |
3690 | if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) | |
3691 | chmap[count++] = SNDRV_CHMAP_NA; | |
3692 | ||
3693 | continue; | |
3694 | } | |
3695 | ||
bb63f726 | 3696 | chmap[count++] = snd_hdac_spk_to_chmap(spk); |
5a613584 AH |
3697 | } |
3698 | ||
3699 | WARN_ON(count != channels); | |
3700 | } | |
3701 | ||
461cf6b3 AH |
3702 | static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, |
3703 | bool hbr) | |
3704 | { | |
3705 | int hbr_ctl, hbr_ctl_new; | |
3706 | ||
3707 | hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); | |
13122e6e | 3708 | if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { |
461cf6b3 AH |
3709 | if (hbr) |
3710 | hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; | |
3711 | else | |
3712 | hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; | |
3713 | ||
4e76a883 TI |
3714 | codec_dbg(codec, |
3715 | "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", | |
461cf6b3 AH |
3716 | pin_nid, |
3717 | hbr_ctl == hbr_ctl_new ? "" : "new-", | |
3718 | hbr_ctl_new); | |
3719 | ||
3720 | if (hbr_ctl != hbr_ctl_new) | |
3721 | snd_hda_codec_write(codec, pin_nid, 0, | |
3722 | ATI_VERB_SET_HBR_CONTROL, | |
3723 | hbr_ctl_new); | |
3724 | ||
3725 | } else if (hbr) | |
3726 | return -EINVAL; | |
3727 | ||
3728 | return 0; | |
3729 | } | |
3730 | ||
84d69e79 AH |
3731 | static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, |
3732 | hda_nid_t pin_nid, u32 stream_tag, int format) | |
3733 | { | |
3734 | ||
3735 | if (is_amdhdmi_rev3_or_later(codec)) { | |
3736 | int ramp_rate = 180; /* default as per AMD spec */ | |
3737 | /* disable ramp-up/down for non-pcm as per AMD spec */ | |
3738 | if (format & AC_FMT_TYPE_NON_PCM) | |
3739 | ramp_rate = 0; | |
3740 | ||
3741 | snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); | |
3742 | } | |
3743 | ||
3744 | return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); | |
3745 | } | |
3746 | ||
3747 | ||
5a613584 | 3748 | static int atihdmi_init(struct hda_codec *codec) |
84eb01be TI |
3749 | { |
3750 | struct hdmi_spec *spec = codec->spec; | |
5a613584 | 3751 | int pin_idx, err; |
84eb01be | 3752 | |
5a613584 AH |
3753 | err = generic_hdmi_init(codec); |
3754 | ||
3755 | if (err) | |
84eb01be | 3756 | return err; |
5a613584 AH |
3757 | |
3758 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
3759 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
3760 | ||
3761 | /* make sure downmix information in infoframe is zero */ | |
3762 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); | |
3763 | ||
3764 | /* enable channel-wise remap mode if supported */ | |
3765 | if (has_amd_full_remap_support(codec)) | |
3766 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, | |
3767 | ATI_VERB_SET_MULTICHANNEL_MODE, | |
3768 | ATI_MULTICHANNEL_MODE_SINGLE); | |
84eb01be | 3769 | } |
5a613584 | 3770 | |
84eb01be TI |
3771 | return 0; |
3772 | } | |
3773 | ||
84eb01be TI |
3774 | static int patch_atihdmi(struct hda_codec *codec) |
3775 | { | |
3776 | struct hdmi_spec *spec; | |
5a613584 AH |
3777 | struct hdmi_spec_per_cvt *per_cvt; |
3778 | int err, cvt_idx; | |
3779 | ||
3780 | err = patch_generic_hdmi(codec); | |
3781 | ||
3782 | if (err) | |
d0b1252d | 3783 | return err; |
5a613584 AH |
3784 | |
3785 | codec->patch_ops.init = atihdmi_init; | |
3786 | ||
d0b1252d | 3787 | spec = codec->spec; |
5a613584 | 3788 | |
89250f84 | 3789 | spec->ops.pin_get_eld = atihdmi_pin_get_eld; |
5a613584 | 3790 | spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; |
461cf6b3 | 3791 | spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; |
84d69e79 | 3792 | spec->ops.setup_stream = atihdmi_setup_stream; |
5a613584 | 3793 | |
39669225 TI |
3794 | spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; |
3795 | spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; | |
3796 | ||
5a613584 AH |
3797 | if (!has_amd_full_remap_support(codec)) { |
3798 | /* override to ATI/AMD-specific versions with pairwise mapping */ | |
67b90cb8 | 3799 | spec->chmap.ops.chmap_cea_alloc_validate_get_type = |
5a613584 | 3800 | atihdmi_paired_chmap_cea_alloc_validate_get_type; |
67b90cb8 SP |
3801 | spec->chmap.ops.cea_alloc_to_tlv_chmap = |
3802 | atihdmi_paired_cea_alloc_to_tlv_chmap; | |
3803 | spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; | |
5a613584 AH |
3804 | } |
3805 | ||
3806 | /* ATI/AMD converters do not advertise all of their capabilities */ | |
3807 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
3808 | per_cvt = get_cvt(spec, cvt_idx); | |
3809 | per_cvt->channels_max = max(per_cvt->channels_max, 8u); | |
3810 | per_cvt->rates |= SUPPORTED_RATES; | |
3811 | per_cvt->formats |= SUPPORTED_FORMATS; | |
3812 | per_cvt->maxbps = max(per_cvt->maxbps, 24u); | |
3813 | } | |
3814 | ||
67b90cb8 | 3815 | spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); |
5a613584 | 3816 | |
57cb54e5 TI |
3817 | /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing |
3818 | * the link-down as is. Tell the core to allow it. | |
3819 | */ | |
3820 | codec->link_down_at_suspend = 1; | |
3821 | ||
84eb01be TI |
3822 | return 0; |
3823 | } | |
3824 | ||
3de5ff88 AL |
3825 | /* VIA HDMI Implementation */ |
3826 | #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ | |
3827 | #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ | |
3828 | ||
3de5ff88 AL |
3829 | static int patch_via_hdmi(struct hda_codec *codec) |
3830 | { | |
250e41ac | 3831 | return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); |
3de5ff88 | 3832 | } |
84eb01be TI |
3833 | |
3834 | /* | |
3835 | * patch entries | |
3836 | */ | |
b9a94a9c TI |
3837 | static const struct hda_device_id snd_hda_id_hdmi[] = { |
3838 | HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), | |
3839 | HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), | |
3840 | HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), | |
3841 | HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), | |
3842 | HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), | |
3843 | HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), | |
3844 | HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), | |
74ec1181 | 3845 | HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), |
b9a94a9c TI |
3846 | HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), |
3847 | HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), | |
74ec1181 | 3848 | HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), |
b9a94a9c TI |
3849 | HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), |
3850 | HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), | |
3851 | HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), | |
74ec1181 DD |
3852 | HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi), |
3853 | HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi), | |
b9a94a9c TI |
3854 | HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi), |
3855 | HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi), | |
3856 | HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi), | |
3857 | HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi), | |
3858 | HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi), | |
3859 | HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi), | |
3860 | HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi), | |
3861 | HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi), | |
3862 | HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi), | |
3863 | HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi), | |
3864 | HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi), | |
c8900a0f | 3865 | /* 17 is known to be absent */ |
b9a94a9c TI |
3866 | HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi), |
3867 | HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi), | |
3868 | HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi), | |
3869 | HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi), | |
3870 | HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi), | |
3871 | HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), | |
3872 | HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), | |
3873 | HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), | |
3874 | HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), | |
917bb90c TR |
3875 | HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), |
3876 | HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), | |
3877 | HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), | |
3878 | HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), | |
b9a94a9c TI |
3879 | HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), |
3880 | HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), | |
3881 | HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), | |
3882 | HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), | |
3883 | HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), | |
74ec1181 DD |
3884 | HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), |
3885 | HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 3886 | HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), |
74ec1181 | 3887 | HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), |
b9a94a9c | 3888 | HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), |
74ec1181 DD |
3889 | HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), |
3890 | HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), | |
b9a94a9c TI |
3891 | HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), |
3892 | HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), | |
3893 | HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), | |
3894 | HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), | |
74ec1181 DD |
3895 | HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), |
3896 | HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), | |
3897 | HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), | |
3898 | HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), | |
3899 | HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 3900 | HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), |
74ec1181 | 3901 | HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), |
af677166 | 3902 | HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), |
74ec1181 | 3903 | HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), |
2d369c74 | 3904 | HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), |
3ec622f4 | 3905 | HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), |
74ec1181 DD |
3906 | HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), |
3907 | HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), | |
3908 | HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), | |
3909 | HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), | |
3910 | HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), | |
3911 | HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), | |
3912 | HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), | |
3913 | HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), | |
3914 | HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), | |
3915 | HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 3916 | HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), |
74ec1181 | 3917 | HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), |
b9a94a9c TI |
3918 | HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), |
3919 | HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), | |
3920 | HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), | |
3921 | HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), | |
7ff652ff | 3922 | HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), |
b0d8bc50 | 3923 | HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), |
b9a94a9c TI |
3924 | HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), |
3925 | HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), | |
3926 | HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), | |
7ff652ff | 3927 | HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), |
e85015a3 TI |
3928 | HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), |
3929 | HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), | |
a686632f TI |
3930 | HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), |
3931 | HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), | |
3932 | HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), | |
3933 | HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), | |
3934 | HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), | |
2b4584d0 | 3935 | HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), |
a87a4d23 | 3936 | HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), |
b0d8bc50 | 3937 | HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), |
b9a94a9c | 3938 | HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), |
a686632f TI |
3939 | HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), |
3940 | HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), | |
b9a94a9c | 3941 | HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), |
d8a766a1 | 3942 | /* special ID for generic HDMI */ |
b9a94a9c | 3943 | HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), |
84eb01be TI |
3944 | {} /* terminator */ |
3945 | }; | |
b9a94a9c | 3946 | MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); |
84eb01be TI |
3947 | |
3948 | MODULE_LICENSE("GPL"); | |
3949 | MODULE_DESCRIPTION("HDMI HD-audio codec"); | |
3950 | MODULE_ALIAS("snd-hda-codec-intelhdmi"); | |
3951 | MODULE_ALIAS("snd-hda-codec-nvhdmi"); | |
3952 | MODULE_ALIAS("snd-hda-codec-atihdmi"); | |
3953 | ||
d8a766a1 | 3954 | static struct hda_codec_driver hdmi_driver = { |
b9a94a9c | 3955 | .id = snd_hda_id_hdmi, |
84eb01be TI |
3956 | }; |
3957 | ||
d8a766a1 | 3958 | module_hda_codec_driver(hdmi_driver); |