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ALSA: usb: Fix Processing Unit Descriptor parsers
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
433968da 37#include <sound/asoundef.h>
d45e6889 38#include <sound/tlv.h>
84eb01be
TI		 39#include "hda_codec.h"
40#include "hda_local.h"
1835a0f9 41#include "hda_jack.h"
84eb01be 42
0ebaa24c
TI		 43static bool static_hdmi_pcm;
44module_param(static_hdmi_pcm, bool, 0644);
45MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
46
84eb01be
TI		 47/*
48 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
384a48d7 49 * could support N independent pipes, each of them can be connected to one or
84eb01be
TI		 50 * more ports (DVI, HDMI or DisplayPort).
51 *
52 * The HDA correspondence of pipes/ports are converter/pin nodes.
53 */
a4567cb3
TI		 54#define MAX_HDMI_CVTS 8
55#define MAX_HDMI_PINS 8
079d88cc 56
384a48d7
SW		 57struct hdmi_spec_per_cvt {
58 hda_nid_t cvt_nid;
59 int assigned;
60 unsigned int channels_min;
61 unsigned int channels_max;
62 u32 rates;
63 u64 formats;
64 unsigned int maxbps;
65};
079d88cc 66
4eea3091
TI		 67/* max. connections to a widget */
68#define HDA_MAX_CONNECTIONS 32
69
384a48d7
SW		 70struct hdmi_spec_per_pin {
71 hda_nid_t pin_nid;
72 int num_mux_nids;
73 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
744626da
WF		 74
75 struct hda_codec *codec;
384a48d7 76 struct hdmi_eld sink_eld;
744626da 77 struct delayed_work work;
92c69e79 78 struct snd_kcontrol *eld_ctl;
c6e8453e 79 int repoll_count;
1a6003b5 80 bool non_pcm;
d45e6889
TI		 81 bool chmap_set; /* channel-map override by ALSA API? */
82 unsigned char chmap[8]; /* ALSA API channel-map */
384a48d7 83};
079d88cc 84
384a48d7
SW		 85struct hdmi_spec {
86 int num_cvts;
87 struct hdmi_spec_per_cvt cvts[MAX_HDMI_CVTS];
c88d4e84 88 hda_nid_t cvt_nids[MAX_HDMI_CVTS];
079d88cc 89
384a48d7
SW		 90 int num_pins;
91 struct hdmi_spec_per_pin pins[MAX_HDMI_PINS];
92 struct hda_pcm pcm_rec[MAX_HDMI_PINS];
d45e6889 93 unsigned int channels_max; /* max over all cvts */
079d88cc 94
4bd038f9 95 struct hdmi_eld temp_eld;
079d88cc 96 /*
384a48d7 97 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 98 */
99 struct hda_multi_out multiout;
d0b1252d 100 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 101};
102
103
104struct hdmi_audio_infoframe {
105 u8 type; /* 0x84 */
106 u8 ver; /* 0x01 */
107 u8 len; /* 0x0a */
108
53d7d69d
WF		 109 u8 checksum;
110
079d88cc
WF		 111 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
112 u8 SS01_SF24;
113 u8 CXT04;
114 u8 CA;
115 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 116};
117
118struct dp_audio_infoframe {
119 u8 type; /* 0x84 */
120 u8 len; /* 0x1b */
121 u8 ver; /* 0x11 << 2 */
122
123 u8 CC02_CT47; /* match with HDMI infoframe from this on */
124 u8 SS01_SF24;
125 u8 CXT04;
126 u8 CA;
127 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 128};
129
2b203dbb
TI		 130union audio_infoframe {
131 struct hdmi_audio_infoframe hdmi;
132 struct dp_audio_infoframe dp;
133 u8 bytes[0];
134};
135
079d88cc
WF		 136/*
137 * CEA speaker placement:
138 *
139 * FLH FCH FRH
140 * FLW FL FLC FC FRC FR FRW
141 *
142 * LFE
143 * TC
144 *
145 * RL RLC RC RRC RR
146 *
147 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
148 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
149 */
150enum cea_speaker_placement {
151 FL = (1 << 0), /* Front Left */
152 FC = (1 << 1), /* Front Center */
153 FR = (1 << 2), /* Front Right */
154 FLC = (1 << 3), /* Front Left Center */
155 FRC = (1 << 4), /* Front Right Center */
156 RL = (1 << 5), /* Rear Left */
157 RC = (1 << 6), /* Rear Center */
158 RR = (1 << 7), /* Rear Right */
159 RLC = (1 << 8), /* Rear Left Center */
160 RRC = (1 << 9), /* Rear Right Center */
161 LFE = (1 << 10), /* Low Frequency Effect */
162 FLW = (1 << 11), /* Front Left Wide */
163 FRW = (1 << 12), /* Front Right Wide */
164 FLH = (1 << 13), /* Front Left High */
165 FCH = (1 << 14), /* Front Center High */
166 FRH = (1 << 15), /* Front Right High */
167 TC = (1 << 16), /* Top Center */
168};
169
170/*
171 * ELD SA bits in the CEA Speaker Allocation data block
172 */
173static int eld_speaker_allocation_bits[] = {
174 [0] = FL | FR,
175 [1] = LFE,
176 [2] = FC,
177 [3] = RL | RR,
178 [4] = RC,
179 [5] = FLC | FRC,
180 [6] = RLC | RRC,
181 /* the following are not defined in ELD yet */
182 [7] = FLW | FRW,
183 [8] = FLH | FRH,
184 [9] = TC,
185 [10] = FCH,
186};
187
188struct cea_channel_speaker_allocation {
189 int ca_index;
190 int speakers[8];
191
192 /* derived values, just for convenience */
193 int channels;
194 int spk_mask;
195};
196
197/*
198 * ALSA sequence is:
199 *
200 * surround40 surround41 surround50 surround51 surround71
201 * ch0 front left = = = =
202 * ch1 front right = = = =
203 * ch2 rear left = = = =
204 * ch3 rear right = = = =
205 * ch4 LFE center center center
206 * ch5 LFE LFE
207 * ch6 side left
208 * ch7 side right
209 *
210 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
211 */
212static int hdmi_channel_mapping[0x32][8] = {
213 /* stereo */
214 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
215 /* 2.1 */
216 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
217 /* Dolby Surround */
218 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
219 /* surround40 */
220 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
221 /* 4ch */
222 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
223 /* surround41 */
9396d317 224 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 225 /* surround50 */
226 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
227 /* surround51 */
228 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
229 /* 7.1 */
230 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
231};
232
233/*
234 * This is an ordered list!
235 *
236 * The preceding ones have better chances to be selected by
53d7d69d 237 * hdmi_channel_allocation().
079d88cc
WF		 238 */
239static struct cea_channel_speaker_allocation channel_allocations[] = {
240/* channel: 7 6 5 4 3 2 1 0 */
241{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
242 /* 2.1 */
243{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
244 /* Dolby Surround */
245{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
246 /* surround40 */
247{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
248 /* surround41 */
249{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
250 /* surround50 */
251{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
252 /* surround51 */
253{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
254 /* 6.1 */
255{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
256 /* surround71 */
257{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
258
259{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
260{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
261{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
262{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
263{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
264{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
265{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
266{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
267{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
268{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
269{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
270{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
271{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
272{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
273{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
274{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
275{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
276{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
277{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
278{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
279{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
280{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
281{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
282{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
283{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
284{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
285{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
286{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
287{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
288{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
289{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
290{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
291{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
292{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
293{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
294{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
295{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
296{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
297{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
298{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
299{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
300};
301
302
303/*
304 * HDMI routines
305 */
306
384a48d7 307static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 308{
384a48d7 309 int pin_idx;
079d88cc 310
384a48d7
SW		 311 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
312 if (spec->pins[pin_idx].pin_nid == pin_nid)
313 return pin_idx;
079d88cc 314
384a48d7
SW		 315 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
316 return -EINVAL;
317}
318
319static int hinfo_to_pin_index(struct hdmi_spec *spec,
320 struct hda_pcm_stream *hinfo)
321{
322 int pin_idx;
323
324 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
325 if (&spec->pcm_rec[pin_idx].stream[0] == hinfo)
326 return pin_idx;
327
328 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
329 return -EINVAL;
330}
331
332static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
333{
334 int cvt_idx;
335
336 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
337 if (spec->cvts[cvt_idx].cvt_nid == cvt_nid)
338 return cvt_idx;
339
340 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 341 return -EINVAL;
342}
343
14bc52b8
PLB		 344static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
345 struct snd_ctl_elem_info *uinfo)
346{
347 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 348 struct hdmi_spec *spec = codec->spec;
349 struct hdmi_eld *eld;
14bc52b8
PLB		 350 int pin_idx;
351
14bc52b8
PLB		 352 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
353
354 pin_idx = kcontrol->private_value;
68e03de9
DH		 355 eld = &spec->pins[pin_idx].sink_eld;
356
4bd038f9 357 mutex_lock(&eld->lock);
68e03de9 358 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
4bd038f9 359 mutex_unlock(&eld->lock);
14bc52b8
PLB		 360
361 return 0;
362}
363
364static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
365 struct snd_ctl_elem_value *ucontrol)
366{
367 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 368 struct hdmi_spec *spec = codec->spec;
369 struct hdmi_eld *eld;
14bc52b8
PLB		 370 int pin_idx;
371
14bc52b8 372 pin_idx = kcontrol->private_value;
68e03de9
DH		 373 eld = &spec->pins[pin_idx].sink_eld;
374
4bd038f9 375 mutex_lock(&eld->lock);
68e03de9 376 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
4bd038f9 377 mutex_unlock(&eld->lock);
68e03de9
DH		 378 snd_BUG();
379 return -EINVAL;
380 }
381
382 memset(ucontrol->value.bytes.data, 0,
383 ARRAY_SIZE(ucontrol->value.bytes.data));
384 if (eld->eld_valid)
385 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
386 eld->eld_size);
4bd038f9 387 mutex_unlock(&eld->lock);
14bc52b8
PLB		 388
389 return 0;
390}
391
392static struct snd_kcontrol_new eld_bytes_ctl = {
393 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
394 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
395 .name = "ELD",
396 .info = hdmi_eld_ctl_info,
397 .get = hdmi_eld_ctl_get,
398};
399
400static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
401 int device)
402{
403 struct snd_kcontrol *kctl;
404 struct hdmi_spec *spec = codec->spec;
405 int err;
406
407 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
408 if (!kctl)
409 return -ENOMEM;
410 kctl->private_value = pin_idx;
411 kctl->id.device = device;
412
413 err = snd_hda_ctl_add(codec, spec->pins[pin_idx].pin_nid, kctl);
414 if (err < 0)
415 return err;
416
92c69e79 417 spec->pins[pin_idx].eld_ctl = kctl;
14bc52b8
PLB		 418 return 0;
419}
420
079d88cc
WF		 421#ifdef BE_PARANOID
422static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
423 int *packet_index, int *byte_index)
424{
425 int val;
426
427 val = snd_hda_codec_read(codec, pin_nid, 0,
428 AC_VERB_GET_HDMI_DIP_INDEX, 0);
429
430 *packet_index = val >> 5;
431 *byte_index = val & 0x1f;
432}
433#endif
434
435static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
436 int packet_index, int byte_index)
437{
438 int val;
439
440 val = (packet_index << 5) | (byte_index & 0x1f);
441
442 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
443}
444
445static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
446 unsigned char val)
447{
448 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
449}
450
384a48d7 451static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 452{
453 /* Unmute */
454 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
455 snd_hda_codec_write(codec, pin_nid, 0,
456 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 457 /* Enable pin out: some machines with GM965 gets broken output when
458 * the pin is disabled or changed while using with HDMI
459 */
079d88cc 460 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 461 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 462}
463
384a48d7 464static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 465{
384a48d7 466 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 467 AC_VERB_GET_CVT_CHAN_COUNT, 0);
468}
469
470static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 471 hda_nid_t cvt_nid, int chs)
079d88cc 472{
384a48d7
SW		 473 if (chs != hdmi_get_channel_count(codec, cvt_nid))
474 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 475 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
476}
477
478
479/*
480 * Channel mapping routines
481 */
482
483/*
484 * Compute derived values in channel_allocations[].
485 */
486static void init_channel_allocations(void)
487{
488 int i, j;
489 struct cea_channel_speaker_allocation *p;
490
491 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
492 p = channel_allocations + i;
493 p->channels = 0;
494 p->spk_mask = 0;
495 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
496 if (p->speakers[j]) {
497 p->channels++;
498 p->spk_mask |= p->speakers[j];
499 }
500 }
501}
502
72357c78
WX		 503static int get_channel_allocation_order(int ca)
504{
505 int i;
506
507 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
508 if (channel_allocations[i].ca_index == ca)
509 break;
510 }
511 return i;
512}
513
079d88cc
WF		 514/*
515 * The transformation takes two steps:
516 *
517 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
518 * spk_mask => (channel_allocations[]) => ai->CA
519 *
520 * TODO: it could select the wrong CA from multiple candidates.
521*/
384a48d7 522static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 523{
079d88cc 524 int i;
53d7d69d 525 int ca = 0;
079d88cc 526 int spk_mask = 0;
079d88cc
WF		 527 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
528
529 /*
530 * CA defaults to 0 for basic stereo audio
531 */
532 if (channels <= 2)
533 return 0;
534
079d88cc
WF		 535 /*
536 * expand ELD's speaker allocation mask
537 *
538 * ELD tells the speaker mask in a compact(paired) form,
539 * expand ELD's notions to match the ones used by Audio InfoFrame.
540 */
541 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 542 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 543 spk_mask |= eld_speaker_allocation_bits[i];
544 }
545
546 /* search for the first working match in the CA table */
547 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
548 if (channels == channel_allocations[i].channels &&
549 (spk_mask & channel_allocations[i].spk_mask) ==
550 channel_allocations[i].spk_mask) {
53d7d69d 551 ca = channel_allocations[i].ca_index;
079d88cc
WF		 552 break;
553 }
554 }
555
1613d6b4 556 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 557 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 558 ca, channels, buf);
079d88cc 559
53d7d69d 560 return ca;
079d88cc
WF		 561}
562
563static void hdmi_debug_channel_mapping(struct hda_codec *codec,
564 hda_nid_t pin_nid)
565{
566#ifdef CONFIG_SND_DEBUG_VERBOSE
567 int i;
568 int slot;
569
570 for (i = 0; i < 8; i++) {
571 slot = snd_hda_codec_read(codec, pin_nid, 0,
572 AC_VERB_GET_HDMI_CHAN_SLOT, i);
573 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
574 slot >> 4, slot & 0xf);
575 }
576#endif
577}
578
579
d45e6889 580static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 581 hda_nid_t pin_nid,
433968da 582 bool non_pcm,
53d7d69d 583 int ca)
079d88cc
WF		 584{
585 int i;
079d88cc 586 int err;
72357c78 587 int order;
433968da 588 int non_pcm_mapping[8];
079d88cc 589
72357c78 590 order = get_channel_allocation_order(ca);
433968da 591
079d88cc 592 if (hdmi_channel_mapping[ca][1] == 0) {
72357c78 593 for (i = 0; i < channel_allocations[order].channels; i++)
079d88cc
WF		 594 hdmi_channel_mapping[ca][i] = i | (i << 4);
595 for (; i < 8; i++)
596 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
597 }
598
433968da
WX		 599 if (non_pcm) {
600 for (i = 0; i < channel_allocations[order].channels; i++)
601 non_pcm_mapping[i] = i | (i << 4);
602 for (; i < 8; i++)
603 non_pcm_mapping[i] = 0xf | (i << 4);
604 }
605
079d88cc
WF		 606 for (i = 0; i < 8; i++) {
607 err = snd_hda_codec_write(codec, pin_nid, 0,
608 AC_VERB_SET_HDMI_CHAN_SLOT,
433968da 609 non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]);
079d88cc 610 if (err) {
2abbf439
WF		 611 snd_printdd(KERN_NOTICE
612 "HDMI: channel mapping failed\n");
079d88cc
WF		 613 break;
614 }
615 }
616
617 hdmi_debug_channel_mapping(codec, pin_nid);
618}
619
d45e6889
TI		 620struct channel_map_table {
621 unsigned char map; /* ALSA API channel map position */
622 unsigned char cea_slot; /* CEA slot value */
623 int spk_mask; /* speaker position bit mask */
624};
625
626static struct channel_map_table map_tables[] = {
627 { SNDRV_CHMAP_FL, 0x00, FL },
628 { SNDRV_CHMAP_FR, 0x01, FR },
629 { SNDRV_CHMAP_RL, 0x04, RL },
630 { SNDRV_CHMAP_RR, 0x05, RR },
631 { SNDRV_CHMAP_LFE, 0x02, LFE },
632 { SNDRV_CHMAP_FC, 0x03, FC },
633 { SNDRV_CHMAP_RLC, 0x06, RLC },
634 { SNDRV_CHMAP_RRC, 0x07, RRC },
635 {} /* terminator */
636};
637
638/* from ALSA API channel position to speaker bit mask */
639static int to_spk_mask(unsigned char c)
640{
641 struct channel_map_table *t = map_tables;
642 for (; t->map; t++) {
643 if (t->map == c)
644 return t->spk_mask;
645 }
646 return 0;
647}
648
649/* from ALSA API channel position to CEA slot */
650static int to_cea_slot(unsigned char c)
651{
652 struct channel_map_table *t = map_tables;
653 for (; t->map; t++) {
654 if (t->map == c)
655 return t->cea_slot;
656 }
657 return 0x0f;
658}
659
660/* from CEA slot to ALSA API channel position */
661static int from_cea_slot(unsigned char c)
662{
663 struct channel_map_table *t = map_tables;
664 for (; t->map; t++) {
665 if (t->cea_slot == c)
666 return t->map;
667 }
668 return 0;
669}
670
671/* from speaker bit mask to ALSA API channel position */
672static int spk_to_chmap(int spk)
673{
674 struct channel_map_table *t = map_tables;
675 for (; t->map; t++) {
676 if (t->spk_mask == spk)
677 return t->map;
678 }
679 return 0;
680}
681
682/* get the CA index corresponding to the given ALSA API channel map */
683static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
684{
685 int i, spks = 0, spk_mask = 0;
686
687 for (i = 0; i < chs; i++) {
688 int mask = to_spk_mask(map[i]);
689 if (mask) {
690 spk_mask |= mask;
691 spks++;
692 }
693 }
694
695 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
696 if ((chs == channel_allocations[i].channels ||
697 spks == channel_allocations[i].channels) &&
698 (spk_mask & channel_allocations[i].spk_mask) ==
699 channel_allocations[i].spk_mask)
700 return channel_allocations[i].ca_index;
701 }
702 return -1;
703}
704
705/* set up the channel slots for the given ALSA API channel map */
706static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
707 hda_nid_t pin_nid,
708 int chs, unsigned char *map)
709{
710 int i;
711 for (i = 0; i < 8; i++) {
712 int val, err;
713 if (i < chs)
714 val = to_cea_slot(map[i]);
715 else
716 val = 0xf;
717 val |= (i << 4);
718 err = snd_hda_codec_write(codec, pin_nid, 0,
719 AC_VERB_SET_HDMI_CHAN_SLOT, val);
720 if (err)
721 return -EINVAL;
722 }
723 return 0;
724}
725
726/* store ALSA API channel map from the current default map */
727static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
728{
729 int i;
730 for (i = 0; i < 8; i++) {
731 if (i < channel_allocations[ca].channels)
732 map[i] = from_cea_slot((hdmi_channel_mapping[ca][i] >> 4) & 0x0f);
733 else
734 map[i] = 0;
735 }
736}
737
738static void hdmi_setup_channel_mapping(struct hda_codec *codec,
739 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 740 int channels, unsigned char *map,
741 bool chmap_set)
d45e6889 742{
20608731 743 if (!non_pcm && chmap_set) {
d45e6889
TI		 744 hdmi_manual_setup_channel_mapping(codec, pin_nid,
745 channels, map);
746 } else {
747 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
748 hdmi_setup_fake_chmap(map, ca);
749 }
750}
079d88cc
WF		 751
752/*
753 * Audio InfoFrame routines
754 */
755
756/*
757 * Enable Audio InfoFrame Transmission
758 */
759static void hdmi_start_infoframe_trans(struct hda_codec *codec,
760 hda_nid_t pin_nid)
761{
762 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
763 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
764 AC_DIPXMIT_BEST);
765}
766
767/*
768 * Disable Audio InfoFrame Transmission
769 */
770static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
771 hda_nid_t pin_nid)
772{
773 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
774 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
775 AC_DIPXMIT_DISABLE);
776}
777
778static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
779{
780#ifdef CONFIG_SND_DEBUG_VERBOSE
781 int i;
782 int size;
783
784 size = snd_hdmi_get_eld_size(codec, pin_nid);
785 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
786
787 for (i = 0; i < 8; i++) {
788 size = snd_hda_codec_read(codec, pin_nid, 0,
789 AC_VERB_GET_HDMI_DIP_SIZE, i);
790 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
791 }
792#endif
793}
794
795static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
796{
797#ifdef BE_PARANOID
798 int i, j;
799 int size;
800 int pi, bi;
801 for (i = 0; i < 8; i++) {
802 size = snd_hda_codec_read(codec, pin_nid, 0,
803 AC_VERB_GET_HDMI_DIP_SIZE, i);
804 if (size == 0)
805 continue;
806
807 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
808 for (j = 1; j < 1000; j++) {
809 hdmi_write_dip_byte(codec, pin_nid, 0x0);
810 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
811 if (pi != i)
812 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
813 bi, pi, i);
814 if (bi == 0) /* byte index wrapped around */
815 break;
816 }
817 snd_printd(KERN_INFO
818 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
819 i, size, j);
820 }
821#endif
822}
823
53d7d69d 824static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 825{
53d7d69d 826 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 827 u8 sum = 0;
828 int i;
829
53d7d69d 830 hdmi_ai->checksum = 0;
079d88cc 831
53d7d69d 832 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 833 sum += bytes[i];
834
53d7d69d 835 hdmi_ai->checksum = -sum;
079d88cc
WF		 836}
837
838static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
839 hda_nid_t pin_nid,
53d7d69d 840 u8 *dip, int size)
079d88cc 841{
079d88cc
WF		 842 int i;
843
844 hdmi_debug_dip_size(codec, pin_nid);
845 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
846
079d88cc 847 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 848 for (i = 0; i < size; i++)
849 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 850}
851
852static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 853 u8 *dip, int size)
079d88cc 854{
079d88cc
WF		 855 u8 val;
856 int i;
857
858 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
859 != AC_DIPXMIT_BEST)
860 return false;
861
862 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 863 for (i = 0; i < size; i++) {
079d88cc
WF		 864 val = snd_hda_codec_read(codec, pin_nid, 0,
865 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 866 if (val != dip[i])
079d88cc
WF		 867 return false;
868 }
869
870 return true;
871}
872
384a48d7 873static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
1a6003b5
TI		 874 bool non_pcm,
875 struct snd_pcm_substream *substream)
079d88cc
WF		 876{
877 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 878 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
879 hda_nid_t pin_nid = per_pin->pin_nid;
53d7d69d 880 int channels = substream->runtime->channels;
384a48d7 881 struct hdmi_eld *eld;
53d7d69d 882 int ca;
2b203dbb 883 union audio_infoframe ai;
079d88cc 884
384a48d7
SW		 885 eld = &spec->pins[pin_idx].sink_eld;
886 if (!eld->monitor_present)
887 return;
079d88cc 888
d45e6889
TI		 889 if (!non_pcm && per_pin->chmap_set)
890 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
891 else
892 ca = hdmi_channel_allocation(eld, channels);
893 if (ca < 0)
894 ca = 0;
384a48d7
SW		 895
896 memset(&ai, 0, sizeof(ai));
1613d6b4 897 if (eld->info.conn_type == 0) { /* HDMI */
384a48d7
SW		 898 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
899
900 hdmi_ai->type = 0x84;
901 hdmi_ai->ver = 0x01;
902 hdmi_ai->len = 0x0a;
903 hdmi_ai->CC02_CT47 = channels - 1;
904 hdmi_ai->CA = ca;
905 hdmi_checksum_audio_infoframe(hdmi_ai);
1613d6b4 906 } else if (eld->info.conn_type == 1) { /* DisplayPort */
384a48d7
SW		 907 struct dp_audio_infoframe *dp_ai = &ai.dp;
908
909 dp_ai->type = 0x84;
910 dp_ai->len = 0x1b;
911 dp_ai->ver = 0x11 << 2;
912 dp_ai->CC02_CT47 = channels - 1;
913 dp_ai->CA = ca;
914 } else {
915 snd_printd("HDMI: unknown connection type at pin %d\n",
916 pin_nid);
917 return;
918 }
53d7d69d 919
384a48d7
SW		 920 /*
921 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
922 * sizeof(*dp_ai) to avoid partial match/update problems when
923 * the user switches between HDMI/DP monitors.
924 */
925 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
926 sizeof(ai))) {
927 snd_printdd("hdmi_setup_audio_infoframe: "
928 "pin=%d channels=%d\n",
929 pin_nid,
930 channels);
d45e6889 931 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
20608731
AH		 932 channels, per_pin->chmap,
933 per_pin->chmap_set);
384a48d7
SW		 934 hdmi_stop_infoframe_trans(codec, pin_nid);
935 hdmi_fill_audio_infoframe(codec, pin_nid,
936 ai.bytes, sizeof(ai));
937 hdmi_start_infoframe_trans(codec, pin_nid);
2d7e887c
WX		 938 } else {
939 /* For non-pcm audio switch, setup new channel mapping
940 * accordingly */
1a6003b5 941 if (per_pin->non_pcm != non_pcm)
d45e6889 942 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
20608731
AH		 943 channels, per_pin->chmap,
944 per_pin->chmap_set);
079d88cc 945 }
433968da 946
1a6003b5 947 per_pin->non_pcm = non_pcm;
079d88cc
WF		 948}
949
950
951/*
952 * Unsolicited events
953 */
954
c6e8453e 955static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 956
079d88cc
WF		 957static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
958{
959 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 960 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
961 int pin_nid;
384a48d7 962 int pin_idx;
3a93897e
TI		 963 struct hda_jack_tbl *jack;
964
965 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
966 if (!jack)
967 return;
968 pin_nid = jack->nid;
969 jack->jack_dirty = 1;
079d88cc 970
fae3d88a 971 _snd_printd(SND_PR_VERBOSE,
384a48d7 972 "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
fae3d88a
FW		 973 codec->addr, pin_nid,
974 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 975
384a48d7
SW		 976 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
977 if (pin_idx < 0)
079d88cc
WF		 978 return;
979
c6e8453e 980 hdmi_present_sense(&spec->pins[pin_idx], 1);
01a61e12 981 snd_hda_jack_report_sync(codec);
079d88cc
WF		 982}
983
984static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
985{
986 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
987 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
988 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
989 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
990
991 printk(KERN_INFO
e9ea8e8f 992 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 993 codec->addr,
079d88cc
WF		 994 tag,
995 subtag,
996 cp_state,
997 cp_ready);
998
999 /* TODO */
1000 if (cp_state)
1001 ;
1002 if (cp_ready)
1003 ;
1004}
1005
1006
1007static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1008{
079d88cc
WF		 1009 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1010 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1011
3a93897e 1012 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 1013 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
1014 return;
1015 }
1016
1017 if (subtag == 0)
1018 hdmi_intrinsic_event(codec, res);
1019 else
1020 hdmi_non_intrinsic_event(codec, res);
1021}
1022
1023/*
1024 * Callbacks
1025 */
1026
92f10b3f
TI		 1027/* HBR should be Non-PCM, 8 channels */
1028#define is_hbr_format(format) \
1029 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1030
384a48d7
SW		 1031static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1032 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 1033{
ea87d1c4
AH		 1034 int pinctl;
1035 int new_pinctl = 0;
ea87d1c4 1036
384a48d7
SW		 1037 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1038 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1039 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1040
1041 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 1042 if (is_hbr_format(format))
ea87d1c4
AH		 1043 new_pinctl |= AC_PINCTL_EPT_HBR;
1044 else
1045 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1046
1047 snd_printdd("hdmi_setup_stream: "
1048 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1049 pin_nid,
ea87d1c4
AH		 1050 pinctl == new_pinctl ? "" : "new-",
1051 new_pinctl);
1052
1053 if (pinctl != new_pinctl)
384a48d7 1054 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1055 AC_VERB_SET_PIN_WIDGET_CONTROL,
1056 new_pinctl);
ea87d1c4 1057
384a48d7 1058 }
92f10b3f 1059 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 1060 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
1061 return -EINVAL;
1062 }
079d88cc 1063
384a48d7 1064 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1065 return 0;
079d88cc
WF		 1066}
1067
bbbe3390
TI		 1068/*
1069 * HDA PCM callbacks
1070 */
1071static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1072 struct hda_codec *codec,
1073 struct snd_pcm_substream *substream)
1074{
1075 struct hdmi_spec *spec = codec->spec;
639cef0e 1076 struct snd_pcm_runtime *runtime = substream->runtime;
384a48d7
SW		 1077 int pin_idx, cvt_idx, mux_idx = 0;
1078 struct hdmi_spec_per_pin *per_pin;
1079 struct hdmi_eld *eld;
1080 struct hdmi_spec_per_cvt *per_cvt = NULL;
bbbe3390 1081
384a48d7
SW		 1082 /* Validate hinfo */
1083 pin_idx = hinfo_to_pin_index(spec, hinfo);
1084 if (snd_BUG_ON(pin_idx < 0))
bbbe3390 1085 return -EINVAL;
384a48d7
SW		 1086 per_pin = &spec->pins[pin_idx];
1087 eld = &per_pin->sink_eld;
1088
1089 /* Dynamically assign converter to stream */
1090 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1091 per_cvt = &spec->cvts[cvt_idx];
bbbe3390 1092
384a48d7
SW		 1093 /* Must not already be assigned */
1094 if (per_cvt->assigned)
1095 continue;
1096 /* Must be in pin's mux's list of converters */
1097 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1098 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1099 break;
1100 /* Not in mux list */
1101 if (mux_idx == per_pin->num_mux_nids)
1102 continue;
1103 break;
1104 }
1105 /* No free converters */
1106 if (cvt_idx == spec->num_cvts)
1107 return -ENODEV;
1108
1109 /* Claim converter */
1110 per_cvt->assigned = 1;
1111 hinfo->nid = per_cvt->cvt_nid;
1112
1113 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1114 AC_VERB_SET_CONNECT_SEL,
1115 mux_idx);
384a48d7 1116 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1117
2def8172 1118 /* Initially set the converter's capabilities */
384a48d7
SW		 1119 hinfo->channels_min = per_cvt->channels_min;
1120 hinfo->channels_max = per_cvt->channels_max;
1121 hinfo->rates = per_cvt->rates;
1122 hinfo->formats = per_cvt->formats;
1123 hinfo->maxbps = per_cvt->maxbps;
2def8172 1124
384a48d7 1125 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1126 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1127 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1128 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1129 !hinfo->rates || !hinfo->formats) {
1130 per_cvt->assigned = 0;
1131 hinfo->nid = 0;
1132 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1133 return -ENODEV;
2ad779b7 1134 }
bbbe3390 1135 }
2def8172
SW		 1136
1137 /* Store the updated parameters */
639cef0e
TI		 1138 runtime->hw.channels_min = hinfo->channels_min;
1139 runtime->hw.channels_max = hinfo->channels_max;
1140 runtime->hw.formats = hinfo->formats;
1141 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1142
1143 snd_pcm_hw_constraint_step(substream->runtime, 0,
1144 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1145 return 0;
1146}
1147
079d88cc
WF		 1148/*
1149 * HDA/HDMI auto parsing
1150 */
384a48d7 1151static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1152{
1153 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1154 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1155 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1156
1157 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1158 snd_printk(KERN_WARNING
1159 "HDMI: pin %d wcaps %#x "
1160 "does not support connection list\n",
1161 pin_nid, get_wcaps(codec, pin_nid));
1162 return -EINVAL;
1163 }
1164
384a48d7
SW		 1165 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1166 per_pin->mux_nids,
1167 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1168
1169 return 0;
1170}
1171
c6e8453e 1172static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1173{
744626da 1174 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1175 struct hdmi_spec *spec = codec->spec;
1176 struct hdmi_eld *eld = &spec->temp_eld;
1177 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1178 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1179 /*
1180 * Always execute a GetPinSense verb here, even when called from
1181 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1182 * response's PD bit is not the real PD value, but indicates that
1183 * the real PD value changed. An older version of the HD-audio
1184 * specification worked this way. Hence, we just ignore the data in
1185 * the unsolicited response to avoid custom WARs.
1186 */
079d88cc 1187 int present = snd_hda_pin_sense(codec, pin_nid);
4bd038f9
DH		 1188 bool update_eld = false;
1189 bool eld_changed = false;
079d88cc 1190
4bd038f9
DH		 1191 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1192 if (pin_eld->monitor_present)
1193 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1194 else
1195 eld->eld_valid = false;
079d88cc 1196
fae3d88a 1197 _snd_printd(SND_PR_VERBOSE,
384a48d7 1198 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
4bd038f9 1199 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
5d44f927 1200
4bd038f9 1201 if (eld->eld_valid) {
1613d6b4
DH		 1202 if (snd_hdmi_get_eld(codec, pin_nid, eld->eld_buffer,
1203 &eld->eld_size) < 0)
4bd038f9 1204 eld->eld_valid = false;
1613d6b4
DH		 1205 else {
1206 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1207 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1208 eld->eld_size) < 0)
4bd038f9 1209 eld->eld_valid = false;
1613d6b4
DH		 1210 }
1211
4bd038f9 1212 if (eld->eld_valid) {
1613d6b4 1213 snd_hdmi_show_eld(&eld->info);
4bd038f9 1214 update_eld = true;
1613d6b4 1215 }
c6e8453e 1216 else if (repoll) {
744626da
WF		 1217 queue_delayed_work(codec->bus->workq,
1218 &per_pin->work,
1219 msecs_to_jiffies(300));
4bd038f9 1220 return;
744626da
WF		 1221 }
1222 }
4bd038f9
DH		 1223
1224 mutex_lock(&pin_eld->lock);
92c69e79 1225 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1226 update_eld = true;
92c69e79
DH		 1227 eld_changed = true;
1228 }
4bd038f9
DH		 1229 if (update_eld) {
1230 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1231 eld_changed = pin_eld->eld_size != eld->eld_size ||
1232 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1233 eld->eld_size) != 0;
1234 if (eld_changed)
1235 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1236 eld->eld_size);
1237 pin_eld->eld_size = eld->eld_size;
1238 pin_eld->info = eld->info;
1239 }
1240 mutex_unlock(&pin_eld->lock);
92c69e79
DH		 1241
1242 if (eld_changed)
1243 snd_ctl_notify(codec->bus->card,
1244 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1245 &per_pin->eld_ctl->id);
079d88cc
WF		 1246}
1247
744626da
WF		 1248static void hdmi_repoll_eld(struct work_struct *work)
1249{
1250 struct hdmi_spec_per_pin *per_pin =
1251 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1252
c6e8453e
WF		 1253 if (per_pin->repoll_count++ > 6)
1254 per_pin->repoll_count = 0;
1255
1256 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1257}
1258
c88d4e84
TI		 1259static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1260 hda_nid_t nid);
1261
079d88cc
WF		 1262static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1263{
1264 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1265 unsigned int caps, config;
1266 int pin_idx;
1267 struct hdmi_spec_per_pin *per_pin;
07acecc1 1268 int err;
079d88cc 1269
efc2f8de 1270 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1271 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1272 return 0;
1273
efc2f8de 1274 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1275 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1276 return 0;
1277
1278 if (snd_BUG_ON(spec->num_pins >= MAX_HDMI_PINS))
3eaead57 1279 return -E2BIG;
384a48d7 1280
c88d4e84
TI		 1281 if (codec->vendor_id == 0x80862807)
1282 intel_haswell_fixup_connect_list(codec, pin_nid);
1283
384a48d7
SW		 1284 pin_idx = spec->num_pins;
1285 per_pin = &spec->pins[pin_idx];
384a48d7
SW		 1286
1287 per_pin->pin_nid = pin_nid;
1a6003b5 1288 per_pin->non_pcm = false;
079d88cc 1289
384a48d7
SW		 1290 err = hdmi_read_pin_conn(codec, pin_idx);
1291 if (err < 0)
1292 return err;
079d88cc 1293
079d88cc
WF		 1294 spec->num_pins++;
1295
384a48d7 1296 return 0;
079d88cc
WF		 1297}
1298
384a48d7 1299static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1300{
1301 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1302 int cvt_idx;
1303 struct hdmi_spec_per_cvt *per_cvt;
1304 unsigned int chans;
1305 int err;
079d88cc 1306
116dcde6
DH		 1307 if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
1308 return -E2BIG;
1309
384a48d7
SW		 1310 chans = get_wcaps(codec, cvt_nid);
1311 chans = get_wcaps_channels(chans);
1312
1313 cvt_idx = spec->num_cvts;
1314 per_cvt = &spec->cvts[cvt_idx];
1315
1316 per_cvt->cvt_nid = cvt_nid;
1317 per_cvt->channels_min = 2;
d45e6889 1318 if (chans <= 16) {
384a48d7 1319 per_cvt->channels_max = chans;
d45e6889
TI		 1320 if (chans > spec->channels_max)
1321 spec->channels_max = chans;
1322 }
384a48d7
SW		 1323
1324 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1325 &per_cvt->rates,
1326 &per_cvt->formats,
1327 &per_cvt->maxbps);
1328 if (err < 0)
1329 return err;
1330
c88d4e84 1331 spec->cvt_nids[spec->num_cvts++] = cvt_nid;
079d88cc
WF		 1332
1333 return 0;
1334}
1335
1336static int hdmi_parse_codec(struct hda_codec *codec)
1337{
1338 hda_nid_t nid;
1339 int i, nodes;
1340
1341 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1342 if (!nid || nodes < 0) {
1343 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1344 return -EINVAL;
1345 }
1346
1347 for (i = 0; i < nodes; i++, nid++) {
1348 unsigned int caps;
1349 unsigned int type;
1350
efc2f8de 1351 caps = get_wcaps(codec, nid);
079d88cc
WF		 1352 type = get_wcaps_type(caps);
1353
1354 if (!(caps & AC_WCAP_DIGITAL))
1355 continue;
1356
1357 switch (type) {
1358 case AC_WID_AUD_OUT:
384a48d7 1359 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1360 break;
1361 case AC_WID_PIN:
3eaead57 1362 hdmi_add_pin(codec, nid);
079d88cc
WF		 1363 break;
1364 }
1365 }
1366
c9adeefd
DH		 1367#ifdef CONFIG_PM
1368 /* We're seeing some problems with unsolicited hot plug events on
1369 * PantherPoint after S3, if this is not enabled */
1370 if (codec->vendor_id == 0x80862806)
1371 codec->bus->power_keep_link_on = 1;
079d88cc
WF		 1372 /*
1373 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1374 * can be lost and presence sense verb will become inaccurate if the
1375 * HDA link is powered off at hot plug or hw initialization time.
1376 */
c9adeefd 1377 else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
079d88cc
WF		 1378 AC_PWRST_EPSS))
1379 codec->bus->power_keep_link_on = 1;
1380#endif
1381
1382 return 0;
1383}
1384
84eb01be
TI		 1385/*
1386 */
a4567cb3
TI		 1387static char *get_hdmi_pcm_name(int idx)
1388{
1389 static char names[MAX_HDMI_PINS][8];
1390 sprintf(&names[idx][0], "HDMI %d", idx);
1391 return &names[idx][0];
1392}
84eb01be 1393
1a6003b5
TI		 1394static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1395{
1396 struct hda_spdif_out *spdif;
1397 bool non_pcm;
1398
1399 mutex_lock(&codec->spdif_mutex);
1400 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1401 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1402 mutex_unlock(&codec->spdif_mutex);
1403 return non_pcm;
1404}
1405
1406
84eb01be
TI		 1407/*
1408 * HDMI callbacks
1409 */
1410
1411static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1412 struct hda_codec *codec,
1413 unsigned int stream_tag,
1414 unsigned int format,
1415 struct snd_pcm_substream *substream)
1416{
384a48d7
SW		 1417 hda_nid_t cvt_nid = hinfo->nid;
1418 struct hdmi_spec *spec = codec->spec;
1419 int pin_idx = hinfo_to_pin_index(spec, hinfo);
1420 hda_nid_t pin_nid = spec->pins[pin_idx].pin_nid;
1a6003b5
TI		 1421 bool non_pcm;
1422
1423 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
384a48d7
SW		 1424
1425 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
84eb01be 1426
1a6003b5 1427 hdmi_setup_audio_infoframe(codec, pin_idx, non_pcm, substream);
84eb01be 1428
384a48d7 1429 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1430}
1431
8dfaa573
TI		 1432static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1433 struct hda_codec *codec,
1434 struct snd_pcm_substream *substream)
1435{
1436 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1437 return 0;
1438}
1439
f2ad24fa
TI		 1440static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1441 struct hda_codec *codec,
1442 struct snd_pcm_substream *substream)
384a48d7
SW		 1443{
1444 struct hdmi_spec *spec = codec->spec;
1445 int cvt_idx, pin_idx;
1446 struct hdmi_spec_per_cvt *per_cvt;
1447 struct hdmi_spec_per_pin *per_pin;
384a48d7 1448
384a48d7
SW		 1449 if (hinfo->nid) {
1450 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1451 if (snd_BUG_ON(cvt_idx < 0))
1452 return -EINVAL;
1453 per_cvt = &spec->cvts[cvt_idx];
1454
1455 snd_BUG_ON(!per_cvt->assigned);
1456 per_cvt->assigned = 0;
1457 hinfo->nid = 0;
1458
1459 pin_idx = hinfo_to_pin_index(spec, hinfo);
1460 if (snd_BUG_ON(pin_idx < 0))
1461 return -EINVAL;
1462 per_pin = &spec->pins[pin_idx];
1463
384a48d7 1464 snd_hda_spdif_ctls_unassign(codec, pin_idx);
d45e6889
TI		 1465 per_pin->chmap_set = false;
1466 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
384a48d7 1467 }
d45e6889 1468
384a48d7
SW		 1469 return 0;
1470}
1471
1472static const struct hda_pcm_ops generic_ops = {
1473 .open = hdmi_pcm_open,
f2ad24fa 1474 .close = hdmi_pcm_close,
384a48d7 1475 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1476 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1477};
1478
d45e6889
TI		 1479/*
1480 * ALSA API channel-map control callbacks
1481 */
1482static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1483 struct snd_ctl_elem_info *uinfo)
1484{
1485 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1486 struct hda_codec *codec = info->private_data;
1487 struct hdmi_spec *spec = codec->spec;
1488 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1489 uinfo->count = spec->channels_max;
1490 uinfo->value.integer.min = 0;
1491 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1492 return 0;
1493}
1494
1495static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1496 unsigned int size, unsigned int __user *tlv)
1497{
1498 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1499 struct hda_codec *codec = info->private_data;
1500 struct hdmi_spec *spec = codec->spec;
1501 const unsigned int valid_mask =
1502 FL | FR | RL | RR | LFE | FC | RLC | RRC;
1503 unsigned int __user *dst;
1504 int chs, count = 0;
1505
1506 if (size < 8)
1507 return -ENOMEM;
1508 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1509 return -EFAULT;
1510 size -= 8;
1511 dst = tlv + 2;
498dab3a 1512 for (chs = 2; chs <= spec->channels_max; chs++) {
d45e6889
TI		 1513 int i, c;
1514 struct cea_channel_speaker_allocation *cap;
1515 cap = channel_allocations;
1516 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1517 int chs_bytes = chs * 4;
1518 if (cap->channels != chs)
1519 continue;
1520 if (cap->spk_mask & ~valid_mask)
1521 continue;
1522 if (size < 8)
1523 return -ENOMEM;
1524 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
1525 put_user(chs_bytes, dst + 1))
1526 return -EFAULT;
1527 dst += 2;
1528 size -= 8;
1529 count += 8;
1530 if (size < chs_bytes)
1531 return -ENOMEM;
1532 size -= chs_bytes;
1533 count += chs_bytes;
1534 for (c = 7; c >= 0; c--) {
1535 int spk = cap->speakers[c];
1536 if (!spk)
1537 continue;
1538 if (put_user(spk_to_chmap(spk), dst))
1539 return -EFAULT;
1540 dst++;
1541 }
1542 }
1543 }
1544 if (put_user(count, tlv + 1))
1545 return -EFAULT;
1546 return 0;
1547}
1548
1549static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1550 struct snd_ctl_elem_value *ucontrol)
1551{
1552 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1553 struct hda_codec *codec = info->private_data;
1554 struct hdmi_spec *spec = codec->spec;
1555 int pin_idx = kcontrol->private_value;
1556 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1557 int i;
1558
1559 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1560 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1561 return 0;
1562}
1563
1564static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1565 struct snd_ctl_elem_value *ucontrol)
1566{
1567 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1568 struct hda_codec *codec = info->private_data;
1569 struct hdmi_spec *spec = codec->spec;
1570 int pin_idx = kcontrol->private_value;
1571 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1572 unsigned int ctl_idx;
1573 struct snd_pcm_substream *substream;
1574 unsigned char chmap[8];
1575 int i, ca, prepared = 0;
1576
1577 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1578 substream = snd_pcm_chmap_substream(info, ctl_idx);
1579 if (!substream || !substream->runtime)
6f54c361 1580 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1581 switch (substream->runtime->status->state) {
1582 case SNDRV_PCM_STATE_OPEN:
1583 case SNDRV_PCM_STATE_SETUP:
1584 break;
1585 case SNDRV_PCM_STATE_PREPARED:
1586 prepared = 1;
1587 break;
1588 default:
1589 return -EBUSY;
1590 }
1591 memset(chmap, 0, sizeof(chmap));
1592 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1593 chmap[i] = ucontrol->value.integer.value[i];
1594 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1595 return 0;
1596 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1597 if (ca < 0)
1598 return -EINVAL;
1599 per_pin->chmap_set = true;
1600 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1601 if (prepared)
1602 hdmi_setup_audio_infoframe(codec, pin_idx, per_pin->non_pcm,
1603 substream);
1604
1605 return 0;
1606}
1607
84eb01be
TI		 1608static int generic_hdmi_build_pcms(struct hda_codec *codec)
1609{
1610 struct hdmi_spec *spec = codec->spec;
384a48d7 1611 int pin_idx;
84eb01be 1612
384a48d7
SW		 1613 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1614 struct hda_pcm *info;
84eb01be
TI		 1615 struct hda_pcm_stream *pstr;
1616
384a48d7 1617 info = &spec->pcm_rec[pin_idx];
a4567cb3 1618 info->name = get_hdmi_pcm_name(pin_idx);
84eb01be 1619 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1620 info->own_chmap = true;
384a48d7 1621
84eb01be 1622 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1623 pstr->substreams = 1;
1624 pstr->ops = generic_ops;
1625 /* other pstr fields are set in open */
84eb01be
TI		 1626 }
1627
384a48d7
SW		 1628 codec->num_pcms = spec->num_pins;
1629 codec->pcm_info = spec->pcm_rec;
1630
84eb01be
TI		 1631 return 0;
1632}
1633
0b6c49b5
DH		 1634static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1635{
31ef2257 1636 char hdmi_str[32] = "HDMI/DP";
0b6c49b5
DH		 1637 struct hdmi_spec *spec = codec->spec;
1638 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1639 int pcmdev = spec->pcm_rec[pin_idx].device;
1640
31ef2257
TI		 1641 if (pcmdev > 0)
1642 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
0b6c49b5 1643
31ef2257 1644 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1645}
1646
84eb01be
TI		 1647static int generic_hdmi_build_controls(struct hda_codec *codec)
1648{
1649 struct hdmi_spec *spec = codec->spec;
1650 int err;
384a48d7 1651 int pin_idx;
84eb01be 1652
384a48d7
SW		 1653 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1654 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
0b6c49b5
DH		 1655
1656 err = generic_hdmi_build_jack(codec, pin_idx);
1657 if (err < 0)
1658 return err;
1659
dcda5806
TI		 1660 err = snd_hda_create_dig_out_ctls(codec,
1661 per_pin->pin_nid,
1662 per_pin->mux_nids[0],
1663 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 1664 if (err < 0)
1665 return err;
384a48d7 1666 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1667
1668 /* add control for ELD Bytes */
1669 err = hdmi_create_eld_ctl(codec,
1670 pin_idx,
1671 spec->pcm_rec[pin_idx].device);
1672
1673 if (err < 0)
1674 return err;
31ef2257 1675
82b1d73f 1676 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 1677 }
1678
d45e6889
TI		 1679 /* add channel maps */
1680 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1681 struct snd_pcm_chmap *chmap;
1682 struct snd_kcontrol *kctl;
1683 int i;
1684 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
1685 SNDRV_PCM_STREAM_PLAYBACK,
1686 NULL, 0, pin_idx, &chmap);
1687 if (err < 0)
1688 return err;
1689 /* override handlers */
1690 chmap->private_data = codec;
1691 kctl = chmap->kctl;
1692 for (i = 0; i < kctl->count; i++)
1693 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
1694 kctl->info = hdmi_chmap_ctl_info;
1695 kctl->get = hdmi_chmap_ctl_get;
1696 kctl->put = hdmi_chmap_ctl_put;
1697 kctl->tlv.c = hdmi_chmap_ctl_tlv;
1698 }
1699
84eb01be
TI		 1700 return 0;
1701}
1702
8b8d654b 1703static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 1704{
1705 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1706 int pin_idx;
1707
1708 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1709 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
384a48d7 1710 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1711
744626da 1712 per_pin->codec = codec;
4bd038f9 1713 mutex_init(&eld->lock);
744626da 1714 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
384a48d7 1715 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be 1716 }
8b8d654b
TI		 1717 return 0;
1718}
1719
1720static int generic_hdmi_init(struct hda_codec *codec)
1721{
1722 struct hdmi_spec *spec = codec->spec;
1723 int pin_idx;
1724
1725 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1726 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1727 hda_nid_t pin_nid = per_pin->pin_nid;
1728
1729 hdmi_init_pin(codec, pin_nid);
1730 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
1731 }
84eb01be
TI		 1732 return 0;
1733}
1734
1735static void generic_hdmi_free(struct hda_codec *codec)
1736{
1737 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1738 int pin_idx;
1739
1740 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1741 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1742 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1743
744626da 1744 cancel_delayed_work(&per_pin->work);
384a48d7
SW		 1745 snd_hda_eld_proc_free(codec, eld);
1746 }
84eb01be 1747
744626da 1748 flush_workqueue(codec->bus->workq);
84eb01be
TI		 1749 kfree(spec);
1750}
1751
fb79e1e0 1752static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1753 .init = generic_hdmi_init,
1754 .free = generic_hdmi_free,
1755 .build_pcms = generic_hdmi_build_pcms,
1756 .build_controls = generic_hdmi_build_controls,
1757 .unsol_event = hdmi_unsol_event,
1758};
1759
6ffe168f 1760
c88d4e84
TI		 1761static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1762 hda_nid_t nid)
1763{
1764 struct hdmi_spec *spec = codec->spec;
1765 hda_nid_t conns[4];
1766 int nconns;
6ffe168f 1767
c88d4e84
TI		 1768 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
1769 if (nconns == spec->num_cvts &&
1770 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 1771 return;
1772
c88d4e84
TI		 1773 /* override pins connection list */
1774 snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
1775 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 1776}
1777
1611a9c9
ML		 1778#define INTEL_VENDOR_NID 0x08
1779#define INTEL_GET_VENDOR_VERB 0xf81
1780#define INTEL_SET_VENDOR_VERB 0x781
1781#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
1782#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
1783
1784static void intel_haswell_enable_all_pins(struct hda_codec *codec,
1785 const struct hda_fixup *fix, int action)
1786{
1787 unsigned int vendor_param;
1788
1789 if (action != HDA_FIXUP_ACT_PRE_PROBE)
1790 return;
1791 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1792 INTEL_GET_VENDOR_VERB, 0);
1793 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
1794 return;
1795
1796 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
1797 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1798 INTEL_SET_VENDOR_VERB, vendor_param);
1799 if (vendor_param == -1)
1800 return;
1801
1802 snd_hda_codec_update_widgets(codec);
1803 return;
1804}
1805
c88d4e84
TI		 1806static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
1807{
1808 unsigned int vendor_param;
1809
1810 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1811 INTEL_GET_VENDOR_VERB, 0);
1812 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
1813 return;
1814
1815 /* enable DP1.2 mode */
1816 vendor_param |= INTEL_EN_DP12;
1817 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
1818 INTEL_SET_VENDOR_VERB, vendor_param);
1819}
1820
1821
1611a9c9
ML		 1822
1823/* available models for fixup */
1824enum {
1825 INTEL_HASWELL,
1826};
1827
1828static const struct hda_model_fixup hdmi_models[] = {
1829 {.id = INTEL_HASWELL, .name = "Haswell"},
1830 {}
1831};
1832
1833static const struct snd_pci_quirk hdmi_fixup_tbl[] = {
1834 SND_PCI_QUIRK(0x8086, 0x2010, "Haswell", INTEL_HASWELL),
1835 {} /* terminator */
1836};
1837
1838static const struct hda_fixup hdmi_fixups[] = {
1839 [INTEL_HASWELL] = {
1840 .type = HDA_FIXUP_FUNC,
1841 .v.func = intel_haswell_enable_all_pins,
1842 },
1843};
1844
6ffe168f 1845
84eb01be
TI		 1846static int patch_generic_hdmi(struct hda_codec *codec)
1847{
1848 struct hdmi_spec *spec;
84eb01be
TI		 1849
1850 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1851 if (spec == NULL)
1852 return -ENOMEM;
1853
1854 codec->spec = spec;
6ffe168f 1855
1611a9c9
ML		 1856 snd_hda_pick_fixup(codec, hdmi_models, hdmi_fixup_tbl, hdmi_fixups);
1857 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE);
1858
6ffe168f 1859 if (codec->vendor_id == 0x80862807)
c88d4e84 1860 intel_haswell_fixup_enable_dp12(codec);
6ffe168f 1861
84eb01be
TI		 1862 if (hdmi_parse_codec(codec) < 0) {
1863 codec->spec = NULL;
1864 kfree(spec);
1865 return -EINVAL;
1866 }
1867 codec->patch_ops = generic_hdmi_patch_ops;
8b8d654b 1868 generic_hdmi_init_per_pins(codec);
84eb01be 1869
84eb01be
TI		 1870 init_channel_allocations();
1871
1872 return 0;
1873}
1874
3aaf8980
SW		 1875/*
1876 * Shared non-generic implementations
1877 */
1878
1879static int simple_playback_build_pcms(struct hda_codec *codec)
1880{
1881 struct hdmi_spec *spec = codec->spec;
1882 struct hda_pcm *info = spec->pcm_rec;
8ceb332d
TI		 1883 unsigned int chans;
1884 struct hda_pcm_stream *pstr;
3aaf8980 1885
8ceb332d 1886 codec->num_pcms = 1;
3aaf8980
SW		 1887 codec->pcm_info = info;
1888
8ceb332d
TI		 1889 chans = get_wcaps(codec, spec->cvts[0].cvt_nid);
1890 chans = get_wcaps_channels(chans);
3aaf8980 1891
8ceb332d
TI		 1892 info->name = get_hdmi_pcm_name(0);
1893 info->pcm_type = HDA_PCM_TYPE_HDMI;
1894 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1895 *pstr = spec->pcm_playback;
1896 pstr->nid = spec->cvts[0].cvt_nid;
1897 if (pstr->channels_max <= 2 && chans && chans <= 16)
1898 pstr->channels_max = chans;
3aaf8980
SW		 1899
1900 return 0;
1901}
1902
4b6ace9e
TI		 1903/* unsolicited event for jack sensing */
1904static void simple_hdmi_unsol_event(struct hda_codec *codec,
1905 unsigned int res)
1906{
9dd8cf12 1907 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 1908 snd_hda_jack_report_sync(codec);
1909}
1910
1911/* generic_hdmi_build_jack can be used for simple_hdmi, too,
1912 * as long as spec->pins[] is set correctly
1913 */
1914#define simple_hdmi_build_jack generic_hdmi_build_jack
1915
3aaf8980
SW		 1916static int simple_playback_build_controls(struct hda_codec *codec)
1917{
1918 struct hdmi_spec *spec = codec->spec;
1919 int err;
3aaf8980 1920
8ceb332d
TI		 1921 err = snd_hda_create_spdif_out_ctls(codec,
1922 spec->cvts[0].cvt_nid,
1923 spec->cvts[0].cvt_nid);
1924 if (err < 0)
1925 return err;
1926 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 1927}
1928
4f0110ce
TI		 1929static int simple_playback_init(struct hda_codec *codec)
1930{
1931 struct hdmi_spec *spec = codec->spec;
8ceb332d
TI		 1932 hda_nid_t pin = spec->pins[0].pin_nid;
1933
1934 snd_hda_codec_write(codec, pin, 0,
1935 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
1936 /* some codecs require to unmute the pin */
1937 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
1938 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
1939 AMP_OUT_UNMUTE);
1940 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 1941 return 0;
1942}
1943
3aaf8980
SW		 1944static void simple_playback_free(struct hda_codec *codec)
1945{
1946 struct hdmi_spec *spec = codec->spec;
1947
1948 kfree(spec);
1949}
1950
84eb01be
TI		 1951/*
1952 * Nvidia specific implementations
1953 */
1954
1955#define Nv_VERB_SET_Channel_Allocation 0xF79
1956#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1957#define Nv_VERB_SET_Audio_Protection_On 0xF98
1958#define Nv_VERB_SET_Audio_Protection_Off 0xF99
1959
1960#define nvhdmi_master_con_nid_7x 0x04
1961#define nvhdmi_master_pin_nid_7x 0x05
1962
fb79e1e0 1963static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 1964 /*front, rear, clfe, rear_surr */
1965 0x6, 0x8, 0xa, 0xc,
1966};
1967
ceaa86ba
TI		 1968static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
1969 /* set audio protect on */
1970 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1971 /* enable digital output on pin widget */
1972 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1973 {} /* terminator */
1974};
1975
1976static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 1977 /* set audio protect on */
1978 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1979 /* enable digital output on pin widget */
1980 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1981 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1982 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1983 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1984 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1985 {} /* terminator */
1986};
1987
1988#ifdef LIMITED_RATE_FMT_SUPPORT
1989/* support only the safe format and rate */
1990#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1991#define SUPPORTED_MAXBPS 16
1992#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1993#else
1994/* support all rates and formats */
1995#define SUPPORTED_RATES \
1996 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1997 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1998 SNDRV_PCM_RATE_192000)
1999#define SUPPORTED_MAXBPS 24
2000#define SUPPORTED_FORMATS \
2001 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2002#endif
2003
ceaa86ba
TI		 2004static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2005{
2006 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2007 return 0;
2008}
2009
2010static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2011{
ceaa86ba 2012 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2013 return 0;
2014}
2015
393004b2
ND		 2016static unsigned int channels_2_6_8[] = {
2017 2, 6, 8
2018};
2019
2020static unsigned int channels_2_8[] = {
2021 2, 8
2022};
2023
2024static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2025 .count = ARRAY_SIZE(channels_2_6_8),
2026 .list = channels_2_6_8,
2027 .mask = 0,
2028};
2029
2030static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2031 .count = ARRAY_SIZE(channels_2_8),
2032 .list = channels_2_8,
2033 .mask = 0,
2034};
2035
84eb01be
TI		 2036static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2037 struct hda_codec *codec,
2038 struct snd_pcm_substream *substream)
2039{
2040 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2041 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2042
2043 switch (codec->preset->id) {
2044 case 0x10de0002:
2045 case 0x10de0003:
2046 case 0x10de0005:
2047 case 0x10de0006:
2048 hw_constraints_channels = &hw_constraints_2_8_channels;
2049 break;
2050 case 0x10de0007:
2051 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2052 break;
2053 default:
2054 break;
2055 }
2056
2057 if (hw_constraints_channels != NULL) {
2058 snd_pcm_hw_constraint_list(substream->runtime, 0,
2059 SNDRV_PCM_HW_PARAM_CHANNELS,
2060 hw_constraints_channels);
ad09fc9d
TI		 2061 } else {
2062 snd_pcm_hw_constraint_step(substream->runtime, 0,
2063 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2064 }
2065
84eb01be
TI		 2066 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2067}
2068
2069static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2070 struct hda_codec *codec,
2071 struct snd_pcm_substream *substream)
2072{
2073 struct hdmi_spec *spec = codec->spec;
2074 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2075}
2076
2077static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2078 struct hda_codec *codec,
2079 unsigned int stream_tag,
2080 unsigned int format,
2081 struct snd_pcm_substream *substream)
2082{
2083 struct hdmi_spec *spec = codec->spec;
2084 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2085 stream_tag, format, substream);
2086}
2087
d0b1252d
TI		 2088static const struct hda_pcm_stream simple_pcm_playback = {
2089 .substreams = 1,
2090 .channels_min = 2,
2091 .channels_max = 2,
2092 .ops = {
2093 .open = simple_playback_pcm_open,
2094 .close = simple_playback_pcm_close,
2095 .prepare = simple_playback_pcm_prepare
2096 },
2097};
2098
2099static const struct hda_codec_ops simple_hdmi_patch_ops = {
2100 .build_controls = simple_playback_build_controls,
2101 .build_pcms = simple_playback_build_pcms,
2102 .init = simple_playback_init,
2103 .free = simple_playback_free,
250e41ac 2104 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2105};
2106
2107static int patch_simple_hdmi(struct hda_codec *codec,
2108 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2109{
2110 struct hdmi_spec *spec;
2111
2112 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2113 if (!spec)
2114 return -ENOMEM;
2115
2116 codec->spec = spec;
2117
2118 spec->multiout.num_dacs = 0; /* no analog */
2119 spec->multiout.max_channels = 2;
2120 spec->multiout.dig_out_nid = cvt_nid;
2121 spec->num_cvts = 1;
2122 spec->num_pins = 1;
2123 spec->cvts[0].cvt_nid = cvt_nid;
21cd683d 2124 spec->pins[0].pin_nid = pin_nid;
d0b1252d
TI		 2125 spec->pcm_playback = simple_pcm_playback;
2126
2127 codec->patch_ops = simple_hdmi_patch_ops;
2128
2129 return 0;
2130}
2131
1f348522
AP		 2132static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2133 int channels)
2134{
2135 unsigned int chanmask;
2136 int chan = channels ? (channels - 1) : 1;
2137
2138 switch (channels) {
2139 default:
2140 case 0:
2141 case 2:
2142 chanmask = 0x00;
2143 break;
2144 case 4:
2145 chanmask = 0x08;
2146 break;
2147 case 6:
2148 chanmask = 0x0b;
2149 break;
2150 case 8:
2151 chanmask = 0x13;
2152 break;
2153 }
2154
2155 /* Set the audio infoframe channel allocation and checksum fields. The
2156 * channel count is computed implicitly by the hardware. */
2157 snd_hda_codec_write(codec, 0x1, 0,
2158 Nv_VERB_SET_Channel_Allocation, chanmask);
2159
2160 snd_hda_codec_write(codec, 0x1, 0,
2161 Nv_VERB_SET_Info_Frame_Checksum,
2162 (0x71 - chan - chanmask));
2163}
2164
84eb01be
TI		 2165static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2166 struct hda_codec *codec,
2167 struct snd_pcm_substream *substream)
2168{
2169 struct hdmi_spec *spec = codec->spec;
2170 int i;
2171
2172 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2173 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2174 for (i = 0; i < 4; i++) {
2175 /* set the stream id */
2176 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2177 AC_VERB_SET_CHANNEL_STREAMID, 0);
2178 /* set the stream format */
2179 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2180 AC_VERB_SET_STREAM_FORMAT, 0);
2181 }
2182
1f348522
AP		 2183 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2184 * streams are disabled. */
2185 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2186
84eb01be
TI		 2187 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2188}
2189
2190static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2191 struct hda_codec *codec,
2192 unsigned int stream_tag,
2193 unsigned int format,
2194 struct snd_pcm_substream *substream)
2195{
2196 int chs;
112daa7a 2197 unsigned int dataDCC2, channel_id;
84eb01be 2198 int i;
7c935976 2199 struct hdmi_spec *spec = codec->spec;
e3245cdd 2200 struct hda_spdif_out *spdif;
84eb01be
TI		 2201
2202 mutex_lock(&codec->spdif_mutex);
e3245cdd 2203 spdif = snd_hda_spdif_out_of_nid(codec, spec->cvts[0].cvt_nid);
84eb01be
TI		 2204
2205 chs = substream->runtime->channels;
84eb01be 2206
84eb01be
TI		 2207 dataDCC2 = 0x2;
2208
84eb01be 2209 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2210 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2211 snd_hda_codec_write(codec,
2212 nvhdmi_master_con_nid_7x,
2213 0,
2214 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2215 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2216
2217 /* set the stream id */
2218 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2219 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2220
2221 /* set the stream format */
2222 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2223 AC_VERB_SET_STREAM_FORMAT, format);
2224
2225 /* turn on again (if needed) */
2226 /* enable and set the channel status audio/data flag */
7c935976 2227 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2228 snd_hda_codec_write(codec,
2229 nvhdmi_master_con_nid_7x,
2230 0,
2231 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2232 spdif->ctls & 0xff);
84eb01be
TI		 2233 snd_hda_codec_write(codec,
2234 nvhdmi_master_con_nid_7x,
2235 0,
2236 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2237 }
2238
2239 for (i = 0; i < 4; i++) {
2240 if (chs == 2)
2241 channel_id = 0;
2242 else
2243 channel_id = i * 2;
2244
2245 /* turn off SPDIF once;
2246 *otherwise the IEC958 bits won't be updated
2247 */
2248 if (codec->spdif_status_reset &&
7c935976 2249 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2250 snd_hda_codec_write(codec,
2251 nvhdmi_con_nids_7x[i],
2252 0,
2253 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2254 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2255 /* set the stream id */
2256 snd_hda_codec_write(codec,
2257 nvhdmi_con_nids_7x[i],
2258 0,
2259 AC_VERB_SET_CHANNEL_STREAMID,
2260 (stream_tag << 4) | channel_id);
2261 /* set the stream format */
2262 snd_hda_codec_write(codec,
2263 nvhdmi_con_nids_7x[i],
2264 0,
2265 AC_VERB_SET_STREAM_FORMAT,
2266 format);
2267 /* turn on again (if needed) */
2268 /* enable and set the channel status audio/data flag */
2269 if (codec->spdif_status_reset &&
7c935976 2270 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2271 snd_hda_codec_write(codec,
2272 nvhdmi_con_nids_7x[i],
2273 0,
2274 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2275 spdif->ctls & 0xff);
84eb01be
TI		 2276 snd_hda_codec_write(codec,
2277 nvhdmi_con_nids_7x[i],
2278 0,
2279 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2280 }
2281 }
2282
1f348522 2283 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2284
2285 mutex_unlock(&codec->spdif_mutex);
2286 return 0;
2287}
2288
fb79e1e0 2289static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2290 .substreams = 1,
2291 .channels_min = 2,
2292 .channels_max = 8,
2293 .nid = nvhdmi_master_con_nid_7x,
2294 .rates = SUPPORTED_RATES,
2295 .maxbps = SUPPORTED_MAXBPS,
2296 .formats = SUPPORTED_FORMATS,
2297 .ops = {
2298 .open = simple_playback_pcm_open,
2299 .close = nvhdmi_8ch_7x_pcm_close,
2300 .prepare = nvhdmi_8ch_7x_pcm_prepare
2301 },
2302};
2303
84eb01be
TI		 2304static int patch_nvhdmi_2ch(struct hda_codec *codec)
2305{
2306 struct hdmi_spec *spec;
d0b1252d
TI		 2307 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2308 nvhdmi_master_pin_nid_7x);
2309 if (err < 0)
2310 return err;
84eb01be 2311
ceaa86ba 2312 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2313 /* override the PCM rates, etc, as the codec doesn't give full list */
2314 spec = codec->spec;
2315 spec->pcm_playback.rates = SUPPORTED_RATES;
2316 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2317 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2318 return 0;
2319}
2320
53775b0d
TI		 2321static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2322{
2323 struct hdmi_spec *spec = codec->spec;
2324 int err = simple_playback_build_pcms(codec);
2325 spec->pcm_rec[0].own_chmap = true;
2326 return err;
2327}
2328
2329static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2330{
2331 struct hdmi_spec *spec = codec->spec;
2332 struct snd_pcm_chmap *chmap;
2333 int err;
2334
2335 err = simple_playback_build_controls(codec);
2336 if (err < 0)
2337 return err;
2338
2339 /* add channel maps */
2340 err = snd_pcm_add_chmap_ctls(spec->pcm_rec[0].pcm,
2341 SNDRV_PCM_STREAM_PLAYBACK,
2342 snd_pcm_alt_chmaps, 8, 0, &chmap);
2343 if (err < 0)
2344 return err;
2345 switch (codec->preset->id) {
2346 case 0x10de0002:
2347 case 0x10de0003:
2348 case 0x10de0005:
2349 case 0x10de0006:
2350 chmap->channel_mask = (1U << 2) | (1U << 8);
2351 break;
2352 case 0x10de0007:
2353 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2354 }
2355 return 0;
2356}
2357
84eb01be
TI		 2358static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2359{
2360 struct hdmi_spec *spec;
2361 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2362 if (err < 0)
2363 return err;
2364 spec = codec->spec;
2365 spec->multiout.max_channels = 8;
d0b1252d 2366 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2367 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2368 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2369 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2370
2371 /* Initialize the audio infoframe channel mask and checksum to something
2372 * valid */
2373 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2374
84eb01be
TI		 2375 return 0;
2376}
2377
2378/*
2379 * ATI-specific implementations
2380 *
2381 * FIXME: we may omit the whole this and use the generic code once after
2382 * it's confirmed to work.
2383 */
2384
2385#define ATIHDMI_CVT_NID 0x02 /* audio converter */
2386#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
2387
2388static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2389 struct hda_codec *codec,
2390 unsigned int stream_tag,
2391 unsigned int format,
2392 struct snd_pcm_substream *substream)
2393{
2394 struct hdmi_spec *spec = codec->spec;
2395 int chans = substream->runtime->channels;
2396 int i, err;
2397
2398 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
2399 substream);
2400 if (err < 0)
2401 return err;
384a48d7
SW		 2402 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
2403 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 2404 /* FIXME: XXX */
2405 for (i = 0; i < chans; i++) {
384a48d7 2406 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
84eb01be
TI		 2407 AC_VERB_SET_HDMI_CHAN_SLOT,
2408 (i << 4) | i);
2409 }
2410 return 0;
2411}
2412
84eb01be
TI		 2413static int patch_atihdmi(struct hda_codec *codec)
2414{
2415 struct hdmi_spec *spec;
d0b1252d
TI		 2416 int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
2417 if (err < 0)
2418 return err;
2419 spec = codec->spec;
2420 spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
84eb01be
TI		 2421 return 0;
2422}
2423
3de5ff88
AL		 2424/* VIA HDMI Implementation */
2425#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
2426#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
2427
3de5ff88
AL		 2428static int patch_via_hdmi(struct hda_codec *codec)
2429{
250e41ac 2430 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 2431}
84eb01be
TI		 2432
2433/*
2434 * patch entries
2435 */
fb79e1e0 2436static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 2437{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
2438{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
2439{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 2440{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2441{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
2442{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
2443{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
2444{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2445{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2446{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2447{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2448{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 2449{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
2450{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
2451{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
2452{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
2453{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
2454{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
2455{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
2456{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
2457{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
2458{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
2459{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 2460/* 17 is known to be absent */
5d44f927
SW		 2461{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
2462{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
2463{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
2464{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
2465{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
2466{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
2467{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
2468{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
2469{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
2470{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
7ae48b56 2471{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2472{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
2473{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 2474{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2475{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2476{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
2477{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2478{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2479{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
2480{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
2481{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
2482{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2483{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 2484{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 2485{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 2486{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2487{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
2488{} /* terminator */
2489};
2490
2491MODULE_ALIAS("snd-hda-codec-id:1002793c");
2492MODULE_ALIAS("snd-hda-codec-id:10027919");
2493MODULE_ALIAS("snd-hda-codec-id:1002791a");
2494MODULE_ALIAS("snd-hda-codec-id:1002aa01");
2495MODULE_ALIAS("snd-hda-codec-id:10951390");
2496MODULE_ALIAS("snd-hda-codec-id:10951392");
2497MODULE_ALIAS("snd-hda-codec-id:10de0002");
2498MODULE_ALIAS("snd-hda-codec-id:10de0003");
2499MODULE_ALIAS("snd-hda-codec-id:10de0005");
2500MODULE_ALIAS("snd-hda-codec-id:10de0006");
2501MODULE_ALIAS("snd-hda-codec-id:10de0007");
2502MODULE_ALIAS("snd-hda-codec-id:10de000a");
2503MODULE_ALIAS("snd-hda-codec-id:10de000b");
2504MODULE_ALIAS("snd-hda-codec-id:10de000c");
2505MODULE_ALIAS("snd-hda-codec-id:10de000d");
2506MODULE_ALIAS("snd-hda-codec-id:10de0010");
2507MODULE_ALIAS("snd-hda-codec-id:10de0011");
2508MODULE_ALIAS("snd-hda-codec-id:10de0012");
2509MODULE_ALIAS("snd-hda-codec-id:10de0013");
2510MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 2511MODULE_ALIAS("snd-hda-codec-id:10de0015");
2512MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 2513MODULE_ALIAS("snd-hda-codec-id:10de0018");
2514MODULE_ALIAS("snd-hda-codec-id:10de0019");
2515MODULE_ALIAS("snd-hda-codec-id:10de001a");
2516MODULE_ALIAS("snd-hda-codec-id:10de001b");
2517MODULE_ALIAS("snd-hda-codec-id:10de001c");
2518MODULE_ALIAS("snd-hda-codec-id:10de0040");
2519MODULE_ALIAS("snd-hda-codec-id:10de0041");
2520MODULE_ALIAS("snd-hda-codec-id:10de0042");
2521MODULE_ALIAS("snd-hda-codec-id:10de0043");
2522MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 2523MODULE_ALIAS("snd-hda-codec-id:10de0051");
84eb01be
TI		 2524MODULE_ALIAS("snd-hda-codec-id:10de0067");
2525MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 2526MODULE_ALIAS("snd-hda-codec-id:11069f80");
2527MODULE_ALIAS("snd-hda-codec-id:11069f81");
2528MODULE_ALIAS("snd-hda-codec-id:11069f84");
2529MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 2530MODULE_ALIAS("snd-hda-codec-id:17e80047");
2531MODULE_ALIAS("snd-hda-codec-id:80860054");
2532MODULE_ALIAS("snd-hda-codec-id:80862801");
2533MODULE_ALIAS("snd-hda-codec-id:80862802");
2534MODULE_ALIAS("snd-hda-codec-id:80862803");
2535MODULE_ALIAS("snd-hda-codec-id:80862804");
2536MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 2537MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 2538MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 2539MODULE_ALIAS("snd-hda-codec-id:80862880");
84eb01be
TI		 2540MODULE_ALIAS("snd-hda-codec-id:808629fb");
2541
2542MODULE_LICENSE("GPL");
2543MODULE_DESCRIPTION("HDMI HD-audio codec");
2544MODULE_ALIAS("snd-hda-codec-intelhdmi");
2545MODULE_ALIAS("snd-hda-codec-nvhdmi");
2546MODULE_ALIAS("snd-hda-codec-atihdmi");
2547
2548static struct hda_codec_preset_list intel_list = {
2549 .preset = snd_hda_preset_hdmi,
2550 .owner = THIS_MODULE,
2551};
2552
2553static int __init patch_hdmi_init(void)
2554{
2555 return snd_hda_add_codec_preset(&intel_list);
2556}
2557
2558static void __exit patch_hdmi_exit(void)
2559{
2560 snd_hda_delete_codec_preset(&intel_list);
2561}
2562
2563module_init(patch_hdmi_init)
2564module_exit(patch_hdmi_exit)
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