]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - sound/pci/hda/patch_hdmi.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
079d88cc
WF		 2/*
3 *
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 *
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 11 *
12 * Authors:
13 * Wu Fengguang <wfg@linux.intel.com>
14 *
15 * Maintained by:
16 * Wu Fengguang <wfg@linux.intel.com>
079d88cc
WF		 17 */
18
84eb01be
TI		 19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
65a77217 22#include <linux/module.h>
aaa23f86 23#include <linux/pm_runtime.h>
84eb01be 24#include <sound/core.h>
07acecc1 25#include <sound/jack.h>
433968da 26#include <sound/asoundef.h>
d45e6889 27#include <sound/tlv.h>
25adc137
DH		 28#include <sound/hdaudio.h>
29#include <sound/hda_i915.h>
67b90cb8 30#include <sound/hda_chmap.h>
be57bfff 31#include <sound/hda_codec.h>
84eb01be 32#include "hda_local.h"
1835a0f9 33#include "hda_jack.h"
84eb01be 34
0ebaa24c
TI		 35static bool static_hdmi_pcm;
36module_param(static_hdmi_pcm, bool, 0644);
37MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
38
7639a06c
TI		 39#define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
40#define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
41#define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
e2656412 42#define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
91815d8a 43#define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
b9091b1c
SP		 44#define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
45 ((codec)->core.vendor_id == 0x80862800))
2b4584d0 46#define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
b0d8bc50 47#define is_icelake(codec) ((codec)->core.vendor_id == 0x8086280f)
432ac1a2 48#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
91815d8a 49 || is_skylake(codec) || is_broxton(codec) \
b0d8bc50
JK		 50 || is_kabylake(codec) || is_geminilake(codec) \
51 || is_cannonlake(codec) || is_icelake(codec))
7639a06c
TI		 52#define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
53#define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
ca2e7224 54#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
fb87fa3a 55
384a48d7
SW		 56struct hdmi_spec_per_cvt {
57 hda_nid_t cvt_nid;
58 int assigned;
59 unsigned int channels_min;
60 unsigned int channels_max;
61 u32 rates;
62 u64 formats;
63 unsigned int maxbps;
64};
079d88cc 65
4eea3091
TI		 66/* max. connections to a widget */
67#define HDA_MAX_CONNECTIONS 32
68
384a48d7
SW		 69struct hdmi_spec_per_pin {
70 hda_nid_t pin_nid;
9152085d 71 int dev_id;
a76056f2
LY		 72 /* pin idx, different device entries on the same pin use the same idx */
73 int pin_nid_idx;
384a48d7
SW		 74 int num_mux_nids;
75 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
2df6742f 76 int mux_idx;
1df5a06a 77 hda_nid_t cvt_nid;
744626da
WF		 78
79 struct hda_codec *codec;
384a48d7 80 struct hdmi_eld sink_eld;
a4e9a38b 81 struct mutex lock;
744626da 82 struct delayed_work work;
2bea241a 83 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
a76056f2 84 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
c6e8453e 85 int repoll_count;
b054087d
TI		 86 bool setup; /* the stream has been set up by prepare callback */
87 int channels; /* current number of channels */
1a6003b5 88 bool non_pcm;
d45e6889
TI		 89 bool chmap_set; /* channel-map override by ALSA API? */
90 unsigned char chmap[8]; /* ALSA API channel-map */
cd6a6503 91#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 92 struct snd_info_entry *proc_entry;
93#endif
384a48d7 94};
079d88cc 95
307229d2
AH		 96/* operations used by generic code that can be overridden by patches */
97struct hdmi_ops {
98 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
99 unsigned char *buf, int *eld_size);
100
307229d2
AH		 101 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
102 int ca, int active_channels, int conn_type);
103
104 /* enable/disable HBR (HD passthrough) */
105 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
106
107 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
108 hda_nid_t pin_nid, u32 stream_tag, int format);
109
4846a67e
TI		 110 void (*pin_cvt_fixup)(struct hda_codec *codec,
111 struct hdmi_spec_per_pin *per_pin,
112 hda_nid_t cvt_nid);
307229d2
AH		 113};
114
2bea241a
LY		 115struct hdmi_pcm {
116 struct hda_pcm *pcm;
117 struct snd_jack *jack;
fb087eaa 118 struct snd_kcontrol *eld_ctl;
2bea241a
LY		 119};
120
384a48d7
SW		 121struct hdmi_spec {
122 int num_cvts;
bce0d2a8
TI		 123 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
124 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 125
9152085d
LY		 126 /*
127 * num_pins is the number of virtual pins
128 * for example, there are 3 pins, and each pin
129 * has 4 device entries, then the num_pins is 12
130 */
384a48d7 131 int num_pins;
9152085d
LY		 132 /*
133 * num_nids is the number of real pins
134 * In the above example, num_nids is 3
135 */
136 int num_nids;
137 /*
138 * dev_num is the number of device entries
139 * on each pin.
140 * In the above example, dev_num is 4
141 */
142 int dev_num;
bce0d2a8 143 struct snd_array pins; /* struct hdmi_spec_per_pin */
2bea241a 144 struct hdmi_pcm pcm_rec[16];
42b29870 145 struct mutex pcm_lock;
a76056f2
LY		 146 /* pcm_bitmap means which pcms have been assigned to pins*/
147 unsigned long pcm_bitmap;
2bf3c85a 148 int pcm_used; /* counter of pcm_rec[] */
ac98379a
LY		 149 /* bitmap shows whether the pcm is opened in user space
150 * bit 0 means the first playback PCM (PCM3);
151 * bit 1 means the second playback PCM, and so on.
152 */
153 unsigned long pcm_in_use;
079d88cc 154
4bd038f9 155 struct hdmi_eld temp_eld;
307229d2 156 struct hdmi_ops ops;
75fae117
SW		 157
158 bool dyn_pin_out;
6590faab 159 bool dyn_pcm_assign;
079d88cc 160 /*
5a613584 161 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 162 */
163 struct hda_multi_out multiout;
d0b1252d 164 struct hda_pcm_stream pcm_playback;
25adc137
DH		 165
166 /* i915/powerwell (Haswell+/Valleyview+) specific */
691be973 167 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
ae891abe 168 struct drm_audio_component_audio_ops drm_audio_ops;
67b90cb8
SP		 169
170 struct hdac_chmap chmap;
a87a4d23 171 hda_nid_t vendor_nid;
b0d8bc50
JK		 172 const int *port_map;
173 int port_num;
079d88cc
WF		 174};
175
a57942bf 176#ifdef CONFIG_SND_HDA_COMPONENT
691be973
TI		 177static inline bool codec_has_acomp(struct hda_codec *codec)
178{
179 struct hdmi_spec *spec = codec->spec;
180 return spec->use_acomp_notifier;
181}
f4e3040b
TI		 182#else
183#define codec_has_acomp(codec) false
184#endif
079d88cc
WF		 185
186struct hdmi_audio_infoframe {
187 u8 type; /* 0x84 */
188 u8 ver; /* 0x01 */
189 u8 len; /* 0x0a */
190
53d7d69d
WF		 191 u8 checksum;
192
079d88cc
WF		 193 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
194 u8 SS01_SF24;
195 u8 CXT04;
196 u8 CA;
197 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 198};
199
200struct dp_audio_infoframe {
201 u8 type; /* 0x84 */
202 u8 len; /* 0x1b */
203 u8 ver; /* 0x11 << 2 */
204
205 u8 CC02_CT47; /* match with HDMI infoframe from this on */
206 u8 SS01_SF24;
207 u8 CXT04;
208 u8 CA;
209 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 210};
211
2b203dbb
TI		 212union audio_infoframe {
213 struct hdmi_audio_infoframe hdmi;
214 struct dp_audio_infoframe dp;
215 u8 bytes[0];
216};
217
079d88cc
WF		 218/*
219 * HDMI routines
220 */
221
bce0d2a8
TI		 222#define get_pin(spec, idx) \
223 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
224#define get_cvt(spec, idx) \
225 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
2bea241a
LY		 226/* obtain hdmi_pcm object assigned to idx */
227#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
228/* obtain hda_pcm object assigned to idx */
229#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
bce0d2a8 230
9152085d
LY		 231static int pin_id_to_pin_index(struct hda_codec *codec,
232 hda_nid_t pin_nid, int dev_id)
079d88cc 233{
4e76a883 234 struct hdmi_spec *spec = codec->spec;
384a48d7 235 int pin_idx;
9152085d 236 struct hdmi_spec_per_pin *per_pin;
079d88cc 237
9152085d
LY		 238 /*
239 * (dev_id == -1) means it is NON-MST pin
240 * return the first virtual pin on this port
241 */
242 if (dev_id == -1)
243 dev_id = 0;
244
245 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
246 per_pin = get_pin(spec, pin_idx);
247 if ((per_pin->pin_nid == pin_nid) &&
248 (per_pin->dev_id == dev_id))
384a48d7 249 return pin_idx;
9152085d 250 }
079d88cc 251
4e76a883 252 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
384a48d7
SW		 253 return -EINVAL;
254}
255
2bf3c85a
LY		 256static int hinfo_to_pcm_index(struct hda_codec *codec,
257 struct hda_pcm_stream *hinfo)
258{
259 struct hdmi_spec *spec = codec->spec;
260 int pcm_idx;
261
262 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
263 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
264 return pcm_idx;
265
266 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
267 return -EINVAL;
268}
269
4e76a883 270static int hinfo_to_pin_index(struct hda_codec *codec,
384a48d7
SW		 271 struct hda_pcm_stream *hinfo)
272{
4e76a883 273 struct hdmi_spec *spec = codec->spec;
6590faab 274 struct hdmi_spec_per_pin *per_pin;
384a48d7
SW		 275 int pin_idx;
276
6590faab
LY		 277 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
278 per_pin = get_pin(spec, pin_idx);
2bea241a
LY		 279 if (per_pin->pcm &&
280 per_pin->pcm->pcm->stream == hinfo)
384a48d7 281 return pin_idx;
6590faab 282 }
384a48d7 283
6590faab 284 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
384a48d7
SW		 285 return -EINVAL;
286}
287
022f344b
LY		 288static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
289 int pcm_idx)
290{
291 int i;
292 struct hdmi_spec_per_pin *per_pin;
293
294 for (i = 0; i < spec->num_pins; i++) {
295 per_pin = get_pin(spec, i);
296 if (per_pin->pcm_idx == pcm_idx)
297 return per_pin;
298 }
299 return NULL;
300}
301
4e76a883 302static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
384a48d7 303{
4e76a883 304 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 305 int cvt_idx;
306
307 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 308 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 309 return cvt_idx;
310
4e76a883 311 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 312 return -EINVAL;
313}
314
14bc52b8
PLB		 315static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
316 struct snd_ctl_elem_info *uinfo)
317{
318 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 319 struct hdmi_spec *spec = codec->spec;
a4e9a38b 320 struct hdmi_spec_per_pin *per_pin;
68e03de9 321 struct hdmi_eld *eld;
fb087eaa 322 int pcm_idx;
14bc52b8 323
14bc52b8
PLB		 324 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
325
fb087eaa
LY		 326 pcm_idx = kcontrol->private_value;
327 mutex_lock(&spec->pcm_lock);
328 per_pin = pcm_idx_to_pin(spec, pcm_idx);
329 if (!per_pin) {
330 /* no pin is bound to the pcm */
331 uinfo->count = 0;
f69548ff 332 goto unlock;
fb087eaa 333 }
a4e9a38b 334 eld = &per_pin->sink_eld;
68e03de9 335 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
14bc52b8 336
f69548ff
TI		 337 unlock:
338 mutex_unlock(&spec->pcm_lock);
14bc52b8
PLB		 339 return 0;
340}
341
342static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
343 struct snd_ctl_elem_value *ucontrol)
344{
345 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 346 struct hdmi_spec *spec = codec->spec;
a4e9a38b 347 struct hdmi_spec_per_pin *per_pin;
68e03de9 348 struct hdmi_eld *eld;
fb087eaa 349 int pcm_idx;
f69548ff 350 int err = 0;
14bc52b8 351
fb087eaa
LY		 352 pcm_idx = kcontrol->private_value;
353 mutex_lock(&spec->pcm_lock);
354 per_pin = pcm_idx_to_pin(spec, pcm_idx);
355 if (!per_pin) {
356 /* no pin is bound to the pcm */
357 memset(ucontrol->value.bytes.data, 0,
358 ARRAY_SIZE(ucontrol->value.bytes.data));
f69548ff 359 goto unlock;
fb087eaa 360 }
68e03de9 361
f69548ff 362 eld = &per_pin->sink_eld;
360a8245
DH		 363 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
364 eld->eld_size > ELD_MAX_SIZE) {
68e03de9 365 snd_BUG();
f69548ff
TI		 366 err = -EINVAL;
367 goto unlock;
68e03de9
DH		 368 }
369
370 memset(ucontrol->value.bytes.data, 0,
371 ARRAY_SIZE(ucontrol->value.bytes.data));
372 if (eld->eld_valid)
373 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
374 eld->eld_size);
14bc52b8 375
f69548ff
TI		 376 unlock:
377 mutex_unlock(&spec->pcm_lock);
378 return err;
14bc52b8
PLB		 379}
380
f3b827e0 381static const struct snd_kcontrol_new eld_bytes_ctl = {
14bc52b8
PLB		 382 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
383 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
384 .name = "ELD",
385 .info = hdmi_eld_ctl_info,
386 .get = hdmi_eld_ctl_get,
387};
388
fb087eaa 389static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
14bc52b8
PLB		 390 int device)
391{
392 struct snd_kcontrol *kctl;
393 struct hdmi_spec *spec = codec->spec;
394 int err;
395
396 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
397 if (!kctl)
398 return -ENOMEM;
fb087eaa 399 kctl->private_value = pcm_idx;
14bc52b8
PLB		 400 kctl->id.device = device;
401
fb087eaa
LY		 402 /* no pin nid is associated with the kctl now
403 * tbd: associate pin nid to eld ctl later
404 */
405 err = snd_hda_ctl_add(codec, 0, kctl);
14bc52b8
PLB		 406 if (err < 0)
407 return err;
408
fb087eaa 409 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
14bc52b8
PLB		 410 return 0;
411}
412
079d88cc
WF		 413#ifdef BE_PARANOID
414static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
415 int *packet_index, int *byte_index)
416{
417 int val;
418
419 val = snd_hda_codec_read(codec, pin_nid, 0,
420 AC_VERB_GET_HDMI_DIP_INDEX, 0);
421
422 *packet_index = val >> 5;
423 *byte_index = val & 0x1f;
424}
425#endif
426
427static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
428 int packet_index, int byte_index)
429{
430 int val;
431
432 val = (packet_index << 5) | (byte_index & 0x1f);
433
434 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
435}
436
437static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
438 unsigned char val)
439{
440 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
441}
442
384a48d7 443static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 444{
75fae117
SW		 445 struct hdmi_spec *spec = codec->spec;
446 int pin_out;
447
079d88cc
WF		 448 /* Unmute */
449 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
450 snd_hda_codec_write(codec, pin_nid, 0,
451 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
75fae117
SW		 452
453 if (spec->dyn_pin_out)
454 /* Disable pin out until stream is active */
455 pin_out = 0;
456 else
457 /* Enable pin out: some machines with GM965 gets broken output
458 * when the pin is disabled or changed while using with HDMI
459 */
460 pin_out = PIN_OUT;
461
079d88cc 462 snd_hda_codec_write(codec, pin_nid, 0,
75fae117 463 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 464}
465
a4e9a38b
TI		 466/*
467 * ELD proc files
468 */
469
cd6a6503 470#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 471static void print_eld_info(struct snd_info_entry *entry,
472 struct snd_info_buffer *buffer)
473{
474 struct hdmi_spec_per_pin *per_pin = entry->private_data;
475
476 mutex_lock(&per_pin->lock);
477 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
478 mutex_unlock(&per_pin->lock);
479}
480
481static void write_eld_info(struct snd_info_entry *entry,
482 struct snd_info_buffer *buffer)
483{
484 struct hdmi_spec_per_pin *per_pin = entry->private_data;
485
486 mutex_lock(&per_pin->lock);
487 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
488 mutex_unlock(&per_pin->lock);
489}
490
491static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
492{
493 char name[32];
494 struct hda_codec *codec = per_pin->codec;
495 struct snd_info_entry *entry;
496 int err;
497
498 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
6efdd851 499 err = snd_card_proc_new(codec->card, name, &entry);
a4e9a38b
TI		 500 if (err < 0)
501 return err;
502
503 snd_info_set_text_ops(entry, per_pin, print_eld_info);
504 entry->c.text.write = write_eld_info;
6a73cf46 505 entry->mode |= 0200;
a4e9a38b
TI		 506 per_pin->proc_entry = entry;
507
508 return 0;
509}
510
511static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
512{
1947a114 513 if (!per_pin->codec->bus->shutdown) {
c560a679 514 snd_info_free_entry(per_pin->proc_entry);
a4e9a38b
TI		 515 per_pin->proc_entry = NULL;
516 }
517}
518#else
b55447a7
TI		 519static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
520 int index)
a4e9a38b
TI		 521{
522 return 0;
523}
b55447a7 524static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 525{
526}
527#endif
079d88cc 528
079d88cc
WF		 529/*
530 * Audio InfoFrame routines
531 */
532
533/*
534 * Enable Audio InfoFrame Transmission
535 */
536static void hdmi_start_infoframe_trans(struct hda_codec *codec,
537 hda_nid_t pin_nid)
538{
539 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
540 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
541 AC_DIPXMIT_BEST);
542}
543
544/*
545 * Disable Audio InfoFrame Transmission
546 */
547static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
548 hda_nid_t pin_nid)
549{
550 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
551 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
552 AC_DIPXMIT_DISABLE);
553}
554
555static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
556{
557#ifdef CONFIG_SND_DEBUG_VERBOSE
558 int i;
559 int size;
560
561 size = snd_hdmi_get_eld_size(codec, pin_nid);
4e76a883 562 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
079d88cc
WF		 563
564 for (i = 0; i < 8; i++) {
565 size = snd_hda_codec_read(codec, pin_nid, 0,
566 AC_VERB_GET_HDMI_DIP_SIZE, i);
4e76a883 567 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
079d88cc
WF		 568 }
569#endif
570}
571
572static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
573{
574#ifdef BE_PARANOID
575 int i, j;
576 int size;
577 int pi, bi;
578 for (i = 0; i < 8; i++) {
579 size = snd_hda_codec_read(codec, pin_nid, 0,
580 AC_VERB_GET_HDMI_DIP_SIZE, i);
581 if (size == 0)
582 continue;
583
584 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
585 for (j = 1; j < 1000; j++) {
586 hdmi_write_dip_byte(codec, pin_nid, 0x0);
587 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
588 if (pi != i)
4e76a883 589 codec_dbg(codec, "dip index %d: %d != %d\n",
079d88cc
WF		 590 bi, pi, i);
591 if (bi == 0) /* byte index wrapped around */
592 break;
593 }
4e76a883 594 codec_dbg(codec,
079d88cc
WF		 595 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
596 i, size, j);
597 }
598#endif
599}
600
53d7d69d 601static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 602{
53d7d69d 603 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 604 u8 sum = 0;
605 int i;
606
53d7d69d 607 hdmi_ai->checksum = 0;
079d88cc 608
53d7d69d 609 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 610 sum += bytes[i];
611
53d7d69d 612 hdmi_ai->checksum = -sum;
079d88cc
WF		 613}
614
615static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
616 hda_nid_t pin_nid,
53d7d69d 617 u8 *dip, int size)
079d88cc 618{
079d88cc
WF		 619 int i;
620
621 hdmi_debug_dip_size(codec, pin_nid);
622 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
623
079d88cc 624 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 625 for (i = 0; i < size; i++)
626 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 627}
628
629static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 630 u8 *dip, int size)
079d88cc 631{
079d88cc
WF		 632 u8 val;
633 int i;
634
635 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
636 != AC_DIPXMIT_BEST)
637 return false;
638
639 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 640 for (i = 0; i < size; i++) {
079d88cc
WF		 641 val = snd_hda_codec_read(codec, pin_nid, 0,
642 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 643 if (val != dip[i])
079d88cc
WF		 644 return false;
645 }
646
647 return true;
648}
649
307229d2
AH		 650static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
651 hda_nid_t pin_nid,
652 int ca, int active_channels,
653 int conn_type)
654{
655 union audio_infoframe ai;
656
caaf5ef9 657 memset(&ai, 0, sizeof(ai));
307229d2
AH		 658 if (conn_type == 0) { /* HDMI */
659 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
660
661 hdmi_ai->type = 0x84;
662 hdmi_ai->ver = 0x01;
663 hdmi_ai->len = 0x0a;
664 hdmi_ai->CC02_CT47 = active_channels - 1;
665 hdmi_ai->CA = ca;
666 hdmi_checksum_audio_infoframe(hdmi_ai);
667 } else if (conn_type == 1) { /* DisplayPort */
668 struct dp_audio_infoframe *dp_ai = &ai.dp;
669
670 dp_ai->type = 0x84;
671 dp_ai->len = 0x1b;
672 dp_ai->ver = 0x11 << 2;
673 dp_ai->CC02_CT47 = active_channels - 1;
674 dp_ai->CA = ca;
675 } else {
4e76a883 676 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
307229d2
AH		 677 pin_nid);
678 return;
679 }
680
681 /*
682 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
683 * sizeof(*dp_ai) to avoid partial match/update problems when
684 * the user switches between HDMI/DP monitors.
685 */
686 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
687 sizeof(ai))) {
4e76a883
TI		 688 codec_dbg(codec,
689 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
307229d2
AH		 690 pin_nid,
691 active_channels, ca);
692 hdmi_stop_infoframe_trans(codec, pin_nid);
693 hdmi_fill_audio_infoframe(codec, pin_nid,
694 ai.bytes, sizeof(ai));
695 hdmi_start_infoframe_trans(codec, pin_nid);
696 }
697}
698
b054087d
TI		 699static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
700 struct hdmi_spec_per_pin *per_pin,
701 bool non_pcm)
079d88cc 702{
307229d2 703 struct hdmi_spec *spec = codec->spec;
739ffee9 704 struct hdac_chmap *chmap = &spec->chmap;
384a48d7 705 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 706 int channels = per_pin->channels;
1df5a06a 707 int active_channels;
384a48d7 708 struct hdmi_eld *eld;
828cb4ed 709 int ca;
079d88cc 710
b054087d
TI		 711 if (!channels)
712 return;
713
44bb6d0c
TI		 714 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
715 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
58f7d28d
ML		 716 snd_hda_codec_write(codec, pin_nid, 0,
717 AC_VERB_SET_AMP_GAIN_MUTE,
718 AMP_OUT_UNMUTE);
719
bce0d2a8 720 eld = &per_pin->sink_eld;
079d88cc 721
bb63f726 722 ca = snd_hdac_channel_allocation(&codec->core,
828cb4ed
SP		 723 eld->info.spk_alloc, channels,
724 per_pin->chmap_set, non_pcm, per_pin->chmap);
384a48d7 725
bb63f726 726 active_channels = snd_hdac_get_active_channels(ca);
1df5a06a 727
739ffee9
SP		 728 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
729 active_channels);
1df5a06a 730
39edac70
AH		 731 /*
732 * always configure channel mapping, it may have been changed by the
733 * user in the meantime
734 */
bb63f726 735 snd_hdac_setup_channel_mapping(&spec->chmap,
828cb4ed
SP		 736 pin_nid, non_pcm, ca, channels,
737 per_pin->chmap, per_pin->chmap_set);
39edac70 738
307229d2
AH		 739 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
740 eld->info.conn_type);
433968da 741
1a6003b5 742 per_pin->non_pcm = non_pcm;
079d88cc
WF		 743}
744
079d88cc
WF		 745/*
746 * Unsolicited events
747 */
748
efe47108 749static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 750
9152085d
LY		 751static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
752 int dev_id)
079d88cc
WF		 753{
754 struct hdmi_spec *spec = codec->spec;
9152085d 755 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
1a4f69d5 756
20ce9029
DH		 757 if (pin_idx < 0)
758 return;
aaa23f86 759 mutex_lock(&spec->pcm_lock);
20ce9029
DH		 760 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
761 snd_hda_jack_report_sync(codec);
aaa23f86 762 mutex_unlock(&spec->pcm_lock);
20ce9029
DH		 763}
764
1a4f69d5
TI		 765static void jack_callback(struct hda_codec *codec,
766 struct hda_jack_callback *jack)
767{
9152085d
LY		 768 /* hda_jack don't support DP MST */
769 check_presence_and_report(codec, jack->nid, 0);
1a4f69d5
TI		 770}
771
20ce9029
DH		 772static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
773{
3a93897e 774 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 775 struct hda_jack_tbl *jack;
2e59e5ab 776 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e 777
9152085d
LY		 778 /*
779 * assume DP MST uses dyn_pcm_assign and acomp and
780 * never comes here
781 * if DP MST supports unsol event, below code need
782 * consider dev_entry
783 */
3a93897e
TI		 784 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
785 if (!jack)
786 return;
3a93897e 787 jack->jack_dirty = 1;
079d88cc 788
4e76a883 789 codec_dbg(codec,
2e59e5ab 790 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 791 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 792 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 793
9152085d
LY		 794 /* hda_jack don't support DP MST */
795 check_presence_and_report(codec, jack->nid, 0);
079d88cc
WF		 796}
797
798static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
799{
800 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
801 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
802 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
803 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
804
4e76a883 805 codec_info(codec,
e9ea8e8f 806 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 807 codec->addr,
079d88cc
WF		 808 tag,
809 subtag,
810 cp_state,
811 cp_ready);
812
813 /* TODO */
814 if (cp_state)
815 ;
816 if (cp_ready)
817 ;
818}
819
820
821static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
822{
079d88cc
WF		 823 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
824 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
825
3a93897e 826 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
4e76a883 827 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
079d88cc
WF		 828 return;
829 }
830
831 if (subtag == 0)
832 hdmi_intrinsic_event(codec, res);
833 else
834 hdmi_non_intrinsic_event(codec, res);
835}
836
58f7d28d 837static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 838 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 839{
58f7d28d 840 int pwr;
83f26ad2 841
53b434f0
WX		 842 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
843 * thus pins could only choose converter 0 for use. Make sure the
844 * converters are in correct power state */
fd678cac 845 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 846 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
847
fd678cac 848 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 849 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
850 AC_PWRST_D0);
851 msleep(40);
852 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
853 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
4e76a883 854 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
83f26ad2 855 }
83f26ad2
DH		 856}
857
079d88cc
WF		 858/*
859 * Callbacks
860 */
861
92f10b3f
TI		 862/* HBR should be Non-PCM, 8 channels */
863#define is_hbr_format(format) \
864 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
865
307229d2
AH		 866static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
867 bool hbr)
079d88cc 868{
307229d2 869 int pinctl, new_pinctl;
83f26ad2 870
384a48d7
SW		 871 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
872 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 873 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
874
13122e6e
AH		 875 if (pinctl < 0)
876 return hbr ? -EINVAL : 0;
877
ea87d1c4 878 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 879 if (hbr)
ea87d1c4
AH		 880 new_pinctl |= AC_PINCTL_EPT_HBR;
881 else
882 new_pinctl |= AC_PINCTL_EPT_NATIVE;
883
4e76a883
TI		 884 codec_dbg(codec,
885 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
384a48d7 886 pin_nid,
ea87d1c4
AH		 887 pinctl == new_pinctl ? "" : "new-",
888 new_pinctl);
889
890 if (pinctl != new_pinctl)
384a48d7 891 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 892 AC_VERB_SET_PIN_WIDGET_CONTROL,
893 new_pinctl);
307229d2
AH		 894 } else if (hbr)
895 return -EINVAL;
ea87d1c4 896
307229d2
AH		 897 return 0;
898}
899
900static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
901 hda_nid_t pin_nid, u32 stream_tag, int format)
902{
903 struct hdmi_spec *spec = codec->spec;
5a5d718f 904 unsigned int param;
307229d2
AH		 905 int err;
906
307229d2
AH		 907 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
908
909 if (err) {
4e76a883 910 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
307229d2 911 return err;
ea87d1c4 912 }
079d88cc 913
5a5d718f
SP		 914 if (is_haswell_plus(codec)) {
915
916 /*
917 * on recent platforms IEC Coding Type is required for HBR
918 * support, read current Digital Converter settings and set
919 * ICT bitfield if needed.
920 */
921 param = snd_hda_codec_read(codec, cvt_nid, 0,
922 AC_VERB_GET_DIGI_CONVERT_1, 0);
923
924 param = (param >> 16) & ~(AC_DIG3_ICT);
925
926 /* on recent platforms ICT mode is required for HBR support */
927 if (is_hbr_format(format))
928 param |= 0x1;
929
930 snd_hda_codec_write(codec, cvt_nid, 0,
931 AC_VERB_SET_DIGI_CONVERT_3, param);
932 }
933
384a48d7 934 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 935 return 0;
079d88cc
WF		 936}
937
42b29870
LY		 938/* Try to find an available converter
939 * If pin_idx is less then zero, just try to find an available converter.
940 * Otherwise, try to find an available converter and get the cvt mux index
941 * of the pin.
942 */
7ef166b8 943static int hdmi_choose_cvt(struct hda_codec *codec,
4846a67e 944 int pin_idx, int *cvt_id)
bbbe3390
TI		 945{
946 struct hdmi_spec *spec = codec->spec;
384a48d7 947 struct hdmi_spec_per_pin *per_pin;
384a48d7 948 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 949 int cvt_idx, mux_idx = 0;
bbbe3390 950
42b29870
LY		 951 /* pin_idx < 0 means no pin will be bound to the converter */
952 if (pin_idx < 0)
953 per_pin = NULL;
954 else
955 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 956
957 /* Dynamically assign converter to stream */
958 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 959 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 960
384a48d7
SW		 961 /* Must not already be assigned */
962 if (per_cvt->assigned)
963 continue;
42b29870
LY		 964 if (per_pin == NULL)
965 break;
384a48d7
SW		 966 /* Must be in pin's mux's list of converters */
967 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
968 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
969 break;
970 /* Not in mux list */
971 if (mux_idx == per_pin->num_mux_nids)
972 continue;
973 break;
974 }
7ef166b8 975
384a48d7
SW		 976 /* No free converters */
977 if (cvt_idx == spec->num_cvts)
42b29870 978 return -EBUSY;
384a48d7 979
42b29870
LY		 980 if (per_pin != NULL)
981 per_pin->mux_idx = mux_idx;
2df6742f 982
7ef166b8
WX		 983 if (cvt_id)
984 *cvt_id = cvt_idx;
7ef166b8
WX		 985
986 return 0;
987}
988
2df6742f
ML		 989/* Assure the pin select the right convetor */
990static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
991 struct hdmi_spec_per_pin *per_pin)
992{
993 hda_nid_t pin_nid = per_pin->pin_nid;
994 int mux_idx, curr;
995
996 mux_idx = per_pin->mux_idx;
997 curr = snd_hda_codec_read(codec, pin_nid, 0,
998 AC_VERB_GET_CONNECT_SEL, 0);
999 if (curr != mux_idx)
1000 snd_hda_codec_write_cache(codec, pin_nid, 0,
1001 AC_VERB_SET_CONNECT_SEL,
1002 mux_idx);
1003}
1004
42b29870
LY		 1005/* get the mux index for the converter of the pins
1006 * converter's mux index is the same for all pins on Intel platform
1007 */
1008static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1009 hda_nid_t cvt_nid)
1010{
1011 int i;
1012
1013 for (i = 0; i < spec->num_cvts; i++)
1014 if (spec->cvt_nids[i] == cvt_nid)
1015 return i;
1016 return -EINVAL;
1017}
1018
300016b9
ML		 1019/* Intel HDMI workaround to fix audio routing issue:
1020 * For some Intel display codecs, pins share the same connection list.
1021 * So a conveter can be selected by multiple pins and playback on any of these
1022 * pins will generate sound on the external display, because audio flows from
1023 * the same converter to the display pipeline. Also muting one pin may make
1024 * other pins have no sound output.
1025 * So this function assures that an assigned converter for a pin is not selected
1026 * by any other pins.
1027 */
1028static void intel_not_share_assigned_cvt(struct hda_codec *codec,
9152085d
LY		 1029 hda_nid_t pin_nid,
1030 int dev_id, int mux_idx)
7ef166b8
WX		 1031{
1032 struct hdmi_spec *spec = codec->spec;
7639a06c 1033 hda_nid_t nid;
f82d7d16
ML		 1034 int cvt_idx, curr;
1035 struct hdmi_spec_per_cvt *per_cvt;
9152085d
LY		 1036 struct hdmi_spec_per_pin *per_pin;
1037 int pin_idx;
1038
1039 /* configure the pins connections */
1040 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1041 int dev_id_saved;
1042 int dev_num;
7ef166b8 1043
9152085d
LY		 1044 per_pin = get_pin(spec, pin_idx);
1045 /*
1046 * pin not connected to monitor
1047 * no need to operate on it
1048 */
1049 if (!per_pin->pcm)
1050 continue;
f82d7d16 1051
9152085d
LY		 1052 if ((per_pin->pin_nid == pin_nid) &&
1053 (per_pin->dev_id == dev_id))
f82d7d16 1054 continue;
7ef166b8 1055
9152085d
LY		 1056 /*
1057 * if per_pin->dev_id >= dev_num,
1058 * snd_hda_get_dev_select() will fail,
1059 * and the following operation is unpredictable.
1060 * So skip this situation.
1061 */
1062 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1063 if (per_pin->dev_id >= dev_num)
7ef166b8
WX		 1064 continue;
1065
9152085d
LY		 1066 nid = per_pin->pin_nid;
1067
1068 /*
1069 * Calling this function should not impact
1070 * on the device entry selection
1071 * So let's save the dev id for each pin,
1072 * and restore it when return
1073 */
1074 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1075 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
f82d7d16 1076 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1077 AC_VERB_GET_CONNECT_SEL, 0);
9152085d
LY		 1078 if (curr != mux_idx) {
1079 snd_hda_set_dev_select(codec, nid, dev_id_saved);
f82d7d16 1080 continue;
9152085d
LY		 1081 }
1082
7ef166b8 1083
f82d7d16
ML		 1084 /* choose an unassigned converter. The conveters in the
1085 * connection list are in the same order as in the codec.
1086 */
1087 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1088 per_cvt = get_cvt(spec, cvt_idx);
1089 if (!per_cvt->assigned) {
4e76a883
TI		 1090 codec_dbg(codec,
1091 "choose cvt %d for pin nid %d\n",
f82d7d16
ML		 1092 cvt_idx, nid);
1093 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1094 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1095 cvt_idx);
1096 break;
1097 }
7ef166b8 1098 }
9152085d 1099 snd_hda_set_dev_select(codec, nid, dev_id_saved);
7ef166b8
WX		 1100 }
1101}
1102
42b29870
LY		 1103/* A wrapper of intel_not_share_asigned_cvt() */
1104static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
9152085d 1105 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
42b29870
LY		 1106{
1107 int mux_idx;
1108 struct hdmi_spec *spec = codec->spec;
1109
42b29870
LY		 1110 /* On Intel platform, the mapping of converter nid to
1111 * mux index of the pins are always the same.
1112 * The pin nid may be 0, this means all pins will not
1113 * share the converter.
1114 */
1115 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1116 if (mux_idx >= 0)
9152085d 1117 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
42b29870
LY		 1118}
1119
4846a67e
TI		 1120/* skeleton caller of pin_cvt_fixup ops */
1121static void pin_cvt_fixup(struct hda_codec *codec,
1122 struct hdmi_spec_per_pin *per_pin,
1123 hda_nid_t cvt_nid)
1124{
1125 struct hdmi_spec *spec = codec->spec;
1126
1127 if (spec->ops.pin_cvt_fixup)
1128 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1129}
1130
42b29870
LY		 1131/* called in hdmi_pcm_open when no pin is assigned to the PCM
1132 * in dyn_pcm_assign mode.
1133 */
1134static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1135 struct hda_codec *codec,
1136 struct snd_pcm_substream *substream)
1137{
1138 struct hdmi_spec *spec = codec->spec;
1139 struct snd_pcm_runtime *runtime = substream->runtime;
ac98379a 1140 int cvt_idx, pcm_idx;
42b29870
LY		 1141 struct hdmi_spec_per_cvt *per_cvt = NULL;
1142 int err;
1143
ac98379a
LY		 1144 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1145 if (pcm_idx < 0)
1146 return -EINVAL;
1147
4846a67e 1148 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
42b29870
LY		 1149 if (err)
1150 return err;
1151
1152 per_cvt = get_cvt(spec, cvt_idx);
1153 per_cvt->assigned = 1;
1154 hinfo->nid = per_cvt->cvt_nid;
1155
4846a67e 1156 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
42b29870 1157
ac98379a 1158 set_bit(pcm_idx, &spec->pcm_in_use);
42b29870
LY		 1159 /* todo: setup spdif ctls assign */
1160
1161 /* Initially set the converter's capabilities */
1162 hinfo->channels_min = per_cvt->channels_min;
1163 hinfo->channels_max = per_cvt->channels_max;
1164 hinfo->rates = per_cvt->rates;
1165 hinfo->formats = per_cvt->formats;
1166 hinfo->maxbps = per_cvt->maxbps;
1167
1168 /* Store the updated parameters */
1169 runtime->hw.channels_min = hinfo->channels_min;
1170 runtime->hw.channels_max = hinfo->channels_max;
1171 runtime->hw.formats = hinfo->formats;
1172 runtime->hw.rates = hinfo->rates;
1173
1174 snd_pcm_hw_constraint_step(substream->runtime, 0,
1175 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1176 return 0;
1177}
1178
7ef166b8
WX		 1179/*
1180 * HDA PCM callbacks
1181 */
1182static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1183 struct hda_codec *codec,
1184 struct snd_pcm_substream *substream)
1185{
1186 struct hdmi_spec *spec = codec->spec;
1187 struct snd_pcm_runtime *runtime = substream->runtime;
4846a67e 1188 int pin_idx, cvt_idx, pcm_idx;
7ef166b8
WX		 1189 struct hdmi_spec_per_pin *per_pin;
1190 struct hdmi_eld *eld;
1191 struct hdmi_spec_per_cvt *per_cvt = NULL;
1192 int err;
1193
1194 /* Validate hinfo */
2bf3c85a
LY		 1195 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1196 if (pcm_idx < 0)
7ef166b8 1197 return -EINVAL;
2bf3c85a 1198
42b29870 1199 mutex_lock(&spec->pcm_lock);
4e76a883 1200 pin_idx = hinfo_to_pin_index(codec, hinfo);
42b29870
LY		 1201 if (!spec->dyn_pcm_assign) {
1202 if (snd_BUG_ON(pin_idx < 0)) {
f69548ff
TI		 1203 err = -EINVAL;
1204 goto unlock;
42b29870
LY		 1205 }
1206 } else {
1207 /* no pin is assigned to the PCM
1208 * PA need pcm open successfully when probe
1209 */
1210 if (pin_idx < 0) {
1211 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
f69548ff 1212 goto unlock;
42b29870
LY		 1213 }
1214 }
7ef166b8 1215
4846a67e 1216 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
f69548ff
TI		 1217 if (err < 0)
1218 goto unlock;
7ef166b8
WX		 1219
1220 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1221 /* Claim converter */
1222 per_cvt->assigned = 1;
42b29870 1223
ac98379a 1224 set_bit(pcm_idx, &spec->pcm_in_use);
42b29870 1225 per_pin = get_pin(spec, pin_idx);
1df5a06a 1226 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1227 hinfo->nid = per_cvt->cvt_nid;
1228
9152085d 1229 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
bddee96b 1230 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7 1231 AC_VERB_SET_CONNECT_SEL,
4846a67e 1232 per_pin->mux_idx);
7ef166b8
WX		 1233
1234 /* configure unused pins to choose other converters */
4846a67e 1235 pin_cvt_fixup(codec, per_pin, 0);
7ef166b8 1236
2bf3c85a 1237 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
bbbe3390 1238
2def8172 1239 /* Initially set the converter's capabilities */
384a48d7
SW		 1240 hinfo->channels_min = per_cvt->channels_min;
1241 hinfo->channels_max = per_cvt->channels_max;
1242 hinfo->rates = per_cvt->rates;
1243 hinfo->formats = per_cvt->formats;
1244 hinfo->maxbps = per_cvt->maxbps;
2def8172 1245
42b29870 1246 eld = &per_pin->sink_eld;
384a48d7 1247 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1248 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1249 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1250 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1251 !hinfo->rates || !hinfo->formats) {
1252 per_cvt->assigned = 0;
1253 hinfo->nid = 0;
2bf3c85a 1254 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
f69548ff
TI		 1255 err = -ENODEV;
1256 goto unlock;
2ad779b7 1257 }
bbbe3390 1258 }
2def8172
SW		 1259
1260 /* Store the updated parameters */
639cef0e
TI		 1261 runtime->hw.channels_min = hinfo->channels_min;
1262 runtime->hw.channels_max = hinfo->channels_max;
1263 runtime->hw.formats = hinfo->formats;
1264 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1265
1266 snd_pcm_hw_constraint_step(substream->runtime, 0,
1267 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
f69548ff
TI		 1268 unlock:
1269 mutex_unlock(&spec->pcm_lock);
1270 return err;
bbbe3390
TI		 1271}
1272
079d88cc
WF		 1273/*
1274 * HDA/HDMI auto parsing
1275 */
384a48d7 1276static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1277{
1278 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1279 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1280 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1281
1282 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
4e76a883
TI		 1283 codec_warn(codec,
1284 "HDMI: pin %d wcaps %#x does not support connection list\n",
079d88cc
WF		 1285 pin_nid, get_wcaps(codec, pin_nid));
1286 return -EINVAL;
1287 }
1288
9152085d 1289 /* all the device entries on the same pin have the same conn list */
384a48d7
SW		 1290 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1291 per_pin->mux_nids,
1292 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1293
1294 return 0;
1295}
1296
a76056f2
LY		 1297static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1298 struct hdmi_spec_per_pin *per_pin)
1299{
1300 int i;
1301
1302 /* try the prefer PCM */
1303 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1304 return per_pin->pin_nid_idx;
1305
1306 /* have a second try; check the "reserved area" over num_pins */
9152085d 1307 for (i = spec->num_nids; i < spec->pcm_used; i++) {
a76056f2
LY		 1308 if (!test_bit(i, &spec->pcm_bitmap))
1309 return i;
1310 }
1311
1312 /* the last try; check the empty slots in pins */
9152085d 1313 for (i = 0; i < spec->num_nids; i++) {
a76056f2
LY		 1314 if (!test_bit(i, &spec->pcm_bitmap))
1315 return i;
1316 }
1317 return -EBUSY;
1318}
1319
1320static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1321 struct hdmi_spec_per_pin *per_pin)
1322{
1323 int idx;
1324
1325 /* pcm already be attached to the pin */
1326 if (per_pin->pcm)
1327 return;
1328 idx = hdmi_find_pcm_slot(spec, per_pin);
d10a80de 1329 if (idx == -EBUSY)
a76056f2
LY		 1330 return;
1331 per_pin->pcm_idx = idx;
2bea241a 1332 per_pin->pcm = get_hdmi_pcm(spec, idx);
a76056f2
LY		 1333 set_bit(idx, &spec->pcm_bitmap);
1334}
1335
1336static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1337 struct hdmi_spec_per_pin *per_pin)
1338{
1339 int idx;
1340
1341 /* pcm already be detached from the pin */
1342 if (!per_pin->pcm)
1343 return;
1344 idx = per_pin->pcm_idx;
1345 per_pin->pcm_idx = -1;
1346 per_pin->pcm = NULL;
1347 if (idx >= 0 && idx < spec->pcm_used)
1348 clear_bit(idx, &spec->pcm_bitmap);
1349}
1350
ac98379a
LY		 1351static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1352 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1353{
1354 int mux_idx;
1355
1356 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1357 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1358 break;
1359 return mux_idx;
1360}
1361
1362static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1363
1364static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1365 struct hdmi_spec_per_pin *per_pin)
1366{
1367 struct hda_codec *codec = per_pin->codec;
1368 struct hda_pcm *pcm;
1369 struct hda_pcm_stream *hinfo;
1370 struct snd_pcm_substream *substream;
1371 int mux_idx;
1372 bool non_pcm;
1373
1374 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
2bea241a 1375 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
ac98379a
LY		 1376 else
1377 return;
8a7d6003
TI		 1378 if (!pcm->pcm)
1379 return;
ac98379a
LY		 1380 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1381 return;
1382
1383 /* hdmi audio only uses playback and one substream */
1384 hinfo = pcm->stream;
1385 substream = pcm->pcm->streams[0].substream;
1386
1387 per_pin->cvt_nid = hinfo->nid;
1388
1389 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
9152085d
LY		 1390 if (mux_idx < per_pin->num_mux_nids) {
1391 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1392 per_pin->dev_id);
ac98379a
LY		 1393 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1394 AC_VERB_SET_CONNECT_SEL,
1395 mux_idx);
9152085d 1396 }
ac98379a
LY		 1397 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1398
1399 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1400 if (substream->runtime)
1401 per_pin->channels = substream->runtime->channels;
1402 per_pin->setup = true;
1403 per_pin->mux_idx = mux_idx;
1404
1405 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1406}
1407
1408static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1409 struct hdmi_spec_per_pin *per_pin)
1410{
1411 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1412 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1413
1414 per_pin->chmap_set = false;
1415 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1416
1417 per_pin->setup = false;
1418 per_pin->channels = 0;
1419}
1420
e90247f9
TI		 1421/* update per_pin ELD from the given new ELD;
1422 * setup info frame and notification accordingly
1423 */
1424static void update_eld(struct hda_codec *codec,
1425 struct hdmi_spec_per_pin *per_pin,
1426 struct hdmi_eld *eld)
1427{
1428 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
a76056f2 1429 struct hdmi_spec *spec = codec->spec;
e90247f9
TI		 1430 bool old_eld_valid = pin_eld->eld_valid;
1431 bool eld_changed;
fb087eaa 1432 int pcm_idx = -1;
e90247f9 1433
fb087eaa
LY		 1434 /* for monitor disconnection, save pcm_idx firstly */
1435 pcm_idx = per_pin->pcm_idx;
a76056f2 1436 if (spec->dyn_pcm_assign) {
ac98379a 1437 if (eld->eld_valid) {
a76056f2 1438 hdmi_attach_hda_pcm(spec, per_pin);
ac98379a
LY		 1439 hdmi_pcm_setup_pin(spec, per_pin);
1440 } else {
1441 hdmi_pcm_reset_pin(spec, per_pin);
a76056f2 1442 hdmi_detach_hda_pcm(spec, per_pin);
ac98379a 1443 }
a76056f2 1444 }
fb087eaa
LY		 1445 /* if pcm_idx == -1, it means this is in monitor connection event
1446 * we can get the correct pcm_idx now.
1447 */
1448 if (pcm_idx == -1)
1449 pcm_idx = per_pin->pcm_idx;
a76056f2 1450
e90247f9
TI		 1451 if (eld->eld_valid)
1452 snd_hdmi_show_eld(codec, &eld->info);
1453
1454 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1455 if (eld->eld_valid && pin_eld->eld_valid)
1456 if (pin_eld->eld_size != eld->eld_size ||
1457 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1458 eld->eld_size) != 0)
1459 eld_changed = true;
1460
bd481285 1461 pin_eld->monitor_present = eld->monitor_present;
e90247f9
TI		 1462 pin_eld->eld_valid = eld->eld_valid;
1463 pin_eld->eld_size = eld->eld_size;
1464 if (eld->eld_valid)
1465 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1466 pin_eld->info = eld->info;
1467
1468 /*
1469 * Re-setup pin and infoframe. This is needed e.g. when
1470 * - sink is first plugged-in
1471 * - transcoder can change during stream playback on Haswell
1472 * and this can make HW reset converter selection on a pin.
1473 */
1474 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
4846a67e 1475 pin_cvt_fixup(codec, per_pin, 0);
e90247f9
TI		 1476 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1477 }
1478
fb087eaa 1479 if (eld_changed && pcm_idx >= 0)
e90247f9
TI		 1480 snd_ctl_notify(codec->card,
1481 SNDRV_CTL_EVENT_MASK_VALUE |
1482 SNDRV_CTL_EVENT_MASK_INFO,
fb087eaa 1483 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
e90247f9
TI		 1484}
1485
788d441a
TI		 1486/* update ELD and jack state via HD-audio verbs */
1487static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1488 int repoll)
079d88cc 1489{
464837a7 1490 struct hda_jack_tbl *jack;
744626da 1491 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1492 struct hdmi_spec *spec = codec->spec;
1493 struct hdmi_eld *eld = &spec->temp_eld;
744626da 1494 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1495 /*
1496 * Always execute a GetPinSense verb here, even when called from
1497 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1498 * response's PD bit is not the real PD value, but indicates that
1499 * the real PD value changed. An older version of the HD-audio
1500 * specification worked this way. Hence, we just ignore the data in
1501 * the unsolicited response to avoid custom WARs.
1502 */
da4a7a39 1503 int present;
efe47108 1504 bool ret;
9a5e5234 1505 bool do_repoll = false;
079d88cc 1506
da4a7a39
DH		 1507 present = snd_hda_pin_sense(codec, pin_nid);
1508
a4e9a38b 1509 mutex_lock(&per_pin->lock);
c44da62b
TI		 1510 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1511 if (eld->monitor_present)
4bd038f9
DH		 1512 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1513 else
1514 eld->eld_valid = false;
079d88cc 1515
4e76a883 1516 codec_dbg(codec,
384a48d7 1517 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
c44da62b 1518 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
5d44f927 1519
4bd038f9 1520 if (eld->eld_valid) {
307229d2 1521 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1522 &eld->eld_size) < 0)
4bd038f9 1523 eld->eld_valid = false;
1613d6b4 1524 else {
79514d47 1525 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1613d6b4 1526 eld->eld_size) < 0)
4bd038f9 1527 eld->eld_valid = false;
1613d6b4 1528 }
9a5e5234
TI		 1529 if (!eld->eld_valid && repoll)
1530 do_repoll = true;
744626da 1531 }
4bd038f9 1532
9a5e5234 1533 if (do_repoll)
e90247f9
TI		 1534 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1535 else
1536 update_eld(codec, per_pin, eld);
92c69e79 1537
c44da62b 1538 ret = !repoll || !eld->monitor_present || eld->eld_valid;
464837a7
DH		 1539
1540 jack = snd_hda_jack_tbl_get(codec, pin_nid);
7f641e26 1541 if (jack) {
464837a7 1542 jack->block_report = !ret;
7f641e26
HW		 1543 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ?
1544 AC_PINSENSE_PRESENCE : 0;
1545 }
a4e9a38b 1546 mutex_unlock(&per_pin->lock);
efe47108 1547 return ret;
079d88cc
WF		 1548}
1549
3184270e
LY		 1550static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1551 struct hdmi_spec_per_pin *per_pin)
1552{
1553 struct hdmi_spec *spec = codec->spec;
1554 struct snd_jack *jack = NULL;
1555 struct hda_jack_tbl *jack_tbl;
1556
1557 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1558 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1559 * NULL even after snd_hda_jack_tbl_clear() is called to
1560 * free snd_jack. This may cause access invalid memory
1561 * when calling snd_jack_report
1562 */
1563 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1564 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1565 else if (!spec->dyn_pcm_assign) {
9152085d
LY		 1566 /*
1567 * jack tbl doesn't support DP MST
1568 * DP MST will use dyn_pcm_assign,
1569 * so DP MST will never come here
1570 */
3184270e
LY		 1571 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1572 if (jack_tbl)
1573 jack = jack_tbl->jack;
1574 }
1575 return jack;
1576}
1577
788d441a
TI		 1578/* update ELD and jack state via audio component */
1579static void sync_eld_via_acomp(struct hda_codec *codec,
1580 struct hdmi_spec_per_pin *per_pin)
1581{
788d441a
TI		 1582 struct hdmi_spec *spec = codec->spec;
1583 struct hdmi_eld *eld = &spec->temp_eld;
25e4abb3 1584 struct snd_jack *jack = NULL;
788d441a
TI		 1585 int size;
1586
e2dc7d7d 1587 mutex_lock(&per_pin->lock);
c64c1437 1588 eld->monitor_present = false;
9152085d
LY		 1589 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1590 per_pin->dev_id, &eld->monitor_present,
1591 eld->eld_buffer, ELD_MAX_SIZE);
e2dc7d7d
TI		 1592 if (size > 0) {
1593 size = min(size, ELD_MAX_SIZE);
1594 if (snd_hdmi_parse_eld(codec, &eld->info,
1595 eld->eld_buffer, size) < 0)
1596 size = -EINVAL;
1597 }
788d441a 1598
e2dc7d7d
TI		 1599 if (size > 0) {
1600 eld->eld_valid = true;
1601 eld->eld_size = size;
1602 } else {
1603 eld->eld_valid = false;
1604 eld->eld_size = 0;
788d441a 1605 }
e2dc7d7d 1606
25e4abb3
LY		 1607 /* pcm_idx >=0 before update_eld() means it is in monitor
1608 * disconnected event. Jack must be fetched before update_eld()
1609 */
3184270e 1610 jack = pin_idx_to_jack(codec, per_pin);
e2dc7d7d 1611 update_eld(codec, per_pin, eld);
3184270e
LY		 1612 if (jack == NULL)
1613 jack = pin_idx_to_jack(codec, per_pin);
25e4abb3
LY		 1614 if (jack == NULL)
1615 goto unlock;
1616 snd_jack_report(jack,
e2dc7d7d
TI		 1617 eld->monitor_present ? SND_JACK_AVOUT : 0);
1618 unlock:
1619 mutex_unlock(&per_pin->lock);
788d441a
TI		 1620}
1621
1622static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1623{
1624 struct hda_codec *codec = per_pin->codec;
a76056f2 1625 int ret;
788d441a 1626
222bde03 1627 /* no temporary power up/down needed for component notifier */
aaa23f86
CW		 1628 if (!codec_has_acomp(codec)) {
1629 ret = snd_hda_power_up_pm(codec);
1630 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) {
1631 snd_hda_power_down_pm(codec);
1632 return false;
1633 }
1634 }
222bde03 1635
788d441a
TI		 1636 if (codec_has_acomp(codec)) {
1637 sync_eld_via_acomp(codec, per_pin);
a76056f2 1638 ret = false; /* don't call snd_hda_jack_report_sync() */
788d441a 1639 } else {
a76056f2 1640 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
788d441a 1641 }
a76056f2 1642
222bde03
TI		 1643 if (!codec_has_acomp(codec))
1644 snd_hda_power_down_pm(codec);
1645
a76056f2 1646 return ret;
788d441a
TI		 1647}
1648
744626da
WF		 1649static void hdmi_repoll_eld(struct work_struct *work)
1650{
1651 struct hdmi_spec_per_pin *per_pin =
1652 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
aaa23f86
CW		 1653 struct hda_codec *codec = per_pin->codec;
1654 struct hdmi_spec *spec = codec->spec;
8c2e6728
HW		 1655 struct hda_jack_tbl *jack;
1656
1657 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1658 if (jack)
1659 jack->jack_dirty = 1;
744626da 1660
c6e8453e
WF		 1661 if (per_pin->repoll_count++ > 6)
1662 per_pin->repoll_count = 0;
1663
aaa23f86 1664 mutex_lock(&spec->pcm_lock);
efe47108
TI		 1665 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1666 snd_hda_jack_report_sync(per_pin->codec);
aaa23f86 1667 mutex_unlock(&spec->pcm_lock);
744626da
WF		 1668}
1669
c88d4e84
TI		 1670static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1671 hda_nid_t nid);
1672
079d88cc
WF		 1673static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1674{
1675 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1676 unsigned int caps, config;
1677 int pin_idx;
1678 struct hdmi_spec_per_pin *per_pin;
07acecc1 1679 int err;
9152085d 1680 int dev_num, i;
079d88cc 1681
efc2f8de 1682 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1683 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1684 return 0;
1685
9152085d
LY		 1686 /*
1687 * For DP MST audio, Configuration Default is the same for
1688 * all device entries on the same pin
1689 */
efc2f8de 1690 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1691 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1692 return 0;
1693
9152085d
LY		 1694 /*
1695 * To simplify the implementation, malloc all
1696 * the virtual pins in the initialization statically
1697 */
1698 if (is_haswell_plus(codec)) {
1699 /*
1700 * On Intel platforms, device entries number is
1701 * changed dynamically. If there is a DP MST
1702 * hub connected, the device entries number is 3.
1703 * Otherwise, it is 1.
1704 * Here we manually set dev_num to 3, so that
1705 * we can initialize all the device entries when
1706 * bootup statically.
1707 */
1708 dev_num = 3;
1709 spec->dev_num = 3;
1710 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1711 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1712 /*
1713 * spec->dev_num is the maxinum number of device entries
1714 * among all the pins
1715 */
1716 spec->dev_num = (spec->dev_num > dev_num) ?
1717 spec->dev_num : dev_num;
1718 } else {
1719 /*
1720 * If the platform doesn't support DP MST,
1721 * manually set dev_num to 1. This means
1722 * the pin has only one device entry.
1723 */
1724 dev_num = 1;
1725 spec->dev_num = 1;
2bea241a 1726 }
079d88cc 1727
9152085d
LY		 1728 for (i = 0; i < dev_num; i++) {
1729 pin_idx = spec->num_pins;
1730 per_pin = snd_array_new(&spec->pins);
079d88cc 1731
9152085d
LY		 1732 if (!per_pin)
1733 return -ENOMEM;
1734
1735 if (spec->dyn_pcm_assign) {
1736 per_pin->pcm = NULL;
1737 per_pin->pcm_idx = -1;
1738 } else {
1739 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1740 per_pin->pcm_idx = pin_idx;
1741 }
1742 per_pin->pin_nid = pin_nid;
1743 per_pin->pin_nid_idx = spec->num_nids;
1744 per_pin->dev_id = i;
1745 per_pin->non_pcm = false;
1746 snd_hda_set_dev_select(codec, pin_nid, i);
1747 if (is_haswell_plus(codec))
1748 intel_haswell_fixup_connect_list(codec, pin_nid);
1749 err = hdmi_read_pin_conn(codec, pin_idx);
1750 if (err < 0)
1751 return err;
1752 spec->num_pins++;
1753 }
1754 spec->num_nids++;
079d88cc 1755
384a48d7 1756 return 0;
079d88cc
WF		 1757}
1758
384a48d7 1759static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1760{
1761 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1762 struct hdmi_spec_per_cvt *per_cvt;
1763 unsigned int chans;
1764 int err;
079d88cc 1765
384a48d7
SW		 1766 chans = get_wcaps(codec, cvt_nid);
1767 chans = get_wcaps_channels(chans);
1768
bce0d2a8
TI		 1769 per_cvt = snd_array_new(&spec->cvts);
1770 if (!per_cvt)
1771 return -ENOMEM;
384a48d7
SW		 1772
1773 per_cvt->cvt_nid = cvt_nid;
1774 per_cvt->channels_min = 2;
d45e6889 1775 if (chans <= 16) {
384a48d7 1776 per_cvt->channels_max = chans;
67b90cb8
SP		 1777 if (chans > spec->chmap.channels_max)
1778 spec->chmap.channels_max = chans;
d45e6889 1779 }
384a48d7
SW		 1780
1781 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1782 &per_cvt->rates,
1783 &per_cvt->formats,
1784 &per_cvt->maxbps);
1785 if (err < 0)
1786 return err;
1787
bce0d2a8
TI		 1788 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1789 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1790 spec->num_cvts++;
079d88cc
WF		 1791
1792 return 0;
1793}
1794
1795static int hdmi_parse_codec(struct hda_codec *codec)
1796{
1797 hda_nid_t nid;
1798 int i, nodes;
1799
7639a06c 1800 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
079d88cc 1801 if (!nid || nodes < 0) {
4e76a883 1802 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
079d88cc
WF		 1803 return -EINVAL;
1804 }
1805
1806 for (i = 0; i < nodes; i++, nid++) {
1807 unsigned int caps;
1808 unsigned int type;
1809
efc2f8de 1810 caps = get_wcaps(codec, nid);
079d88cc
WF		 1811 type = get_wcaps_type(caps);
1812
1813 if (!(caps & AC_WCAP_DIGITAL))
1814 continue;
1815
1816 switch (type) {
1817 case AC_WID_AUD_OUT:
384a48d7 1818 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1819 break;
1820 case AC_WID_PIN:
3eaead57 1821 hdmi_add_pin(codec, nid);
079d88cc
WF		 1822 break;
1823 }
1824 }
1825
079d88cc
WF		 1826 return 0;
1827}
1828
84eb01be
TI		 1829/*
1830 */
1a6003b5
TI		 1831static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1832{
1833 struct hda_spdif_out *spdif;
1834 bool non_pcm;
1835
1836 mutex_lock(&codec->spdif_mutex);
1837 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
960a581e
LY		 1838 /* Add sanity check to pass klockwork check.
1839 * This should never happen.
1840 */
1841 if (WARN_ON(spdif == NULL))
1842 return true;
1a6003b5
TI		 1843 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1844 mutex_unlock(&codec->spdif_mutex);
1845 return non_pcm;
1846}
1847
84eb01be
TI		 1848/*
1849 * HDMI callbacks
1850 */
1851
1852static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1853 struct hda_codec *codec,
1854 unsigned int stream_tag,
1855 unsigned int format,
1856 struct snd_pcm_substream *substream)
1857{
384a48d7
SW		 1858 hda_nid_t cvt_nid = hinfo->nid;
1859 struct hdmi_spec *spec = codec->spec;
42b29870
LY		 1860 int pin_idx;
1861 struct hdmi_spec_per_pin *per_pin;
1862 hda_nid_t pin_nid;
ddd621fb 1863 struct snd_pcm_runtime *runtime = substream->runtime;
1a6003b5 1864 bool non_pcm;
053b0559 1865 int pinctl, stripe;
f69548ff 1866 int err = 0;
1a6003b5 1867
42b29870
LY		 1868 mutex_lock(&spec->pcm_lock);
1869 pin_idx = hinfo_to_pin_index(codec, hinfo);
1870 if (spec->dyn_pcm_assign && pin_idx < 0) {
1871 /* when dyn_pcm_assign and pcm is not bound to a pin
1872 * skip pin setup and return 0 to make audio playback
1873 * be ongoing
1874 */
4846a67e 1875 pin_cvt_fixup(codec, NULL, cvt_nid);
42b29870
LY		 1876 snd_hda_codec_setup_stream(codec, cvt_nid,
1877 stream_tag, 0, format);
f69548ff 1878 goto unlock;
42b29870 1879 }
1a6003b5 1880
42b29870 1881 if (snd_BUG_ON(pin_idx < 0)) {
f69548ff
TI		 1882 err = -EINVAL;
1883 goto unlock;
42b29870
LY		 1884 }
1885 per_pin = get_pin(spec, pin_idx);
1886 pin_nid = per_pin->pin_nid;
4846a67e
TI		 1887
1888 /* Verify pin:cvt selections to avoid silent audio after S3.
1889 * After S3, the audio driver restores pin:cvt selections
1890 * but this can happen before gfx is ready and such selection
1891 * is overlooked by HW. Thus multiple pins can share a same
1892 * default convertor and mute control will affect each other,
1893 * which can cause a resumed audio playback become silent
1894 * after S3.
1895 */
1896 pin_cvt_fixup(codec, per_pin, 0);
2df6742f 1897
ddd621fb
LY		 1898 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1899 /* Todo: add DP1.2 MST audio support later */
93a9ff15 1900 if (codec_has_acomp(codec))
9152085d 1901 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
f9318941 1902 runtime->rate);
ddd621fb 1903
1a6003b5 1904 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1905 mutex_lock(&per_pin->lock);
b054087d
TI		 1906 per_pin->channels = substream->runtime->channels;
1907 per_pin->setup = true;
384a48d7 1908
053b0559
SP		 1909 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
1910 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
1911 substream);
1912 snd_hda_codec_write(codec, cvt_nid, 0,
1913 AC_VERB_SET_STRIPE_CONTROL,
1914 stripe);
1915 }
1916
b054087d 1917 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1918 mutex_unlock(&per_pin->lock);
75fae117
SW		 1919 if (spec->dyn_pin_out) {
1920 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1921 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1922 snd_hda_codec_write(codec, pin_nid, 0,
1923 AC_VERB_SET_PIN_WIDGET_CONTROL,
1924 pinctl | PIN_OUT);
1925 }
1926
9152085d 1927 /* snd_hda_set_dev_select() has been called before */
42b29870
LY		 1928 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1929 stream_tag, format);
f69548ff 1930 unlock:
42b29870
LY		 1931 mutex_unlock(&spec->pcm_lock);
1932 return err;
84eb01be
TI		 1933}
1934
8dfaa573
TI		 1935static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1936 struct hda_codec *codec,
1937 struct snd_pcm_substream *substream)
1938{
1939 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1940 return 0;
1941}
1942
f2ad24fa
TI		 1943static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1944 struct hda_codec *codec,
1945 struct snd_pcm_substream *substream)
384a48d7
SW		 1946{
1947 struct hdmi_spec *spec = codec->spec;
2bf3c85a 1948 int cvt_idx, pin_idx, pcm_idx;
384a48d7
SW		 1949 struct hdmi_spec_per_cvt *per_cvt;
1950 struct hdmi_spec_per_pin *per_pin;
75fae117 1951 int pinctl;
f69548ff 1952 int err = 0;
384a48d7 1953
384a48d7 1954 if (hinfo->nid) {
2bf3c85a
LY		 1955 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1956 if (snd_BUG_ON(pcm_idx < 0))
1957 return -EINVAL;
4e76a883 1958 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
384a48d7
SW		 1959 if (snd_BUG_ON(cvt_idx < 0))
1960 return -EINVAL;
bce0d2a8 1961 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1962
1963 snd_BUG_ON(!per_cvt->assigned);
1964 per_cvt->assigned = 0;
1965 hinfo->nid = 0;
1966
42b29870 1967 mutex_lock(&spec->pcm_lock);
b09887f8 1968 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
ac98379a 1969 clear_bit(pcm_idx, &spec->pcm_in_use);
4e76a883 1970 pin_idx = hinfo_to_pin_index(codec, hinfo);
f69548ff
TI		 1971 if (spec->dyn_pcm_assign && pin_idx < 0)
1972 goto unlock;
42b29870
LY		 1973
1974 if (snd_BUG_ON(pin_idx < 0)) {
f69548ff
TI		 1975 err = -EINVAL;
1976 goto unlock;
42b29870 1977 }
bce0d2a8 1978 per_pin = get_pin(spec, pin_idx);
384a48d7 1979
75fae117
SW		 1980 if (spec->dyn_pin_out) {
1981 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1982 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1983 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1984 AC_VERB_SET_PIN_WIDGET_CONTROL,
1985 pinctl & ~PIN_OUT);
1986 }
1987
a4e9a38b 1988 mutex_lock(&per_pin->lock);
d45e6889
TI		 1989 per_pin->chmap_set = false;
1990 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1991
1992 per_pin->setup = false;
1993 per_pin->channels = 0;
a4e9a38b 1994 mutex_unlock(&per_pin->lock);
f69548ff 1995 unlock:
42b29870 1996 mutex_unlock(&spec->pcm_lock);
384a48d7 1997 }
d45e6889 1998
f69548ff 1999 return err;
384a48d7
SW		 2000}
2001
2002static const struct hda_pcm_ops generic_ops = {
2003 .open = hdmi_pcm_open,
f2ad24fa 2004 .close = hdmi_pcm_close,
384a48d7 2005 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 2006 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 2007};
2008
44fde3b8
SP		 2009static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2010{
2011 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2012 struct hdmi_spec *spec = codec->spec;
2013 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2014
2015 if (!per_pin)
2016 return 0;
2017
2018 return per_pin->sink_eld.info.spk_alloc;
2019}
2020
9b3dc8aa
SP		 2021static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2022 unsigned char *chmap)
2023{
2024 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2025 struct hdmi_spec *spec = codec->spec;
2026 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2027
2028 /* chmap is already set to 0 in caller */
2029 if (!per_pin)
2030 return;
2031
2032 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2033}
2034
2035static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2036 unsigned char *chmap, int prepared)
2037{
2038 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2039 struct hdmi_spec *spec = codec->spec;
2040 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2041
ed0739b5
LY		 2042 if (!per_pin)
2043 return;
9b3dc8aa
SP		 2044 mutex_lock(&per_pin->lock);
2045 per_pin->chmap_set = true;
2046 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2047 if (prepared)
2048 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2049 mutex_unlock(&per_pin->lock);
2050}
2051
2052static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2053{
2054 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2055 struct hdmi_spec *spec = codec->spec;
2056 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2057
2058 return per_pin ? true:false;
2059}
2060
84eb01be
TI		 2061static int generic_hdmi_build_pcms(struct hda_codec *codec)
2062{
2063 struct hdmi_spec *spec = codec->spec;
9152085d 2064 int idx;
84eb01be 2065
9152085d
LY		 2066 /*
2067 * for non-mst mode, pcm number is the same as before
2068 * for DP MST mode, pcm number is (nid number + dev_num - 1)
2069 * dev_num is the device entry number in a pin
2070 *
2071 */
2072 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
384a48d7 2073 struct hda_pcm *info;
84eb01be 2074 struct hda_pcm_stream *pstr;
bce0d2a8 2075
9152085d 2076 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
bce0d2a8
TI		 2077 if (!info)
2078 return -ENOMEM;
2bea241a 2079
9152085d 2080 spec->pcm_rec[idx].pcm = info;
2bf3c85a 2081 spec->pcm_used++;
84eb01be 2082 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 2083 info->own_chmap = true;
384a48d7 2084
84eb01be 2085 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 2086 pstr->substreams = 1;
2087 pstr->ops = generic_ops;
9152085d
LY		 2088 /* pcm number is less than 16 */
2089 if (spec->pcm_used >= 16)
2090 break;
384a48d7 2091 /* other pstr fields are set in open */
84eb01be
TI		 2092 }
2093
2094 return 0;
2095}
2096
25e4abb3 2097static void free_hdmi_jack_priv(struct snd_jack *jack)
788d441a 2098{
25e4abb3 2099 struct hdmi_pcm *pcm = jack->private_data;
788d441a 2100
25e4abb3 2101 pcm->jack = NULL;
788d441a
TI		 2102}
2103
25e4abb3
LY		 2104static int add_hdmi_jack_kctl(struct hda_codec *codec,
2105 struct hdmi_spec *spec,
2106 int pcm_idx,
788d441a
TI		 2107 const char *name)
2108{
2109 struct snd_jack *jack;
2110 int err;
2111
2112 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2113 true, false);
2114 if (err < 0)
2115 return err;
25e4abb3
LY		 2116
2117 spec->pcm_rec[pcm_idx].jack = jack;
2118 jack->private_data = &spec->pcm_rec[pcm_idx];
2119 jack->private_free = free_hdmi_jack_priv;
788d441a
TI		 2120 return 0;
2121}
2122
25e4abb3 2123static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
0b6c49b5 2124{
31ef2257 2125 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 2126 struct hdmi_spec *spec = codec->spec;
25e4abb3
LY		 2127 struct hdmi_spec_per_pin *per_pin;
2128 struct hda_jack_tbl *jack;
2129 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
909cadc6 2130 bool phantom_jack;
25e4abb3 2131 int ret;
0b6c49b5 2132
31ef2257
TI		 2133 if (pcmdev > 0)
2134 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
25e4abb3
LY		 2135
2136 if (spec->dyn_pcm_assign)
2137 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2138
2139 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2140 /* if !dyn_pcm_assign, it must be non-MST mode.
2141 * This means pcms and pins are statically mapped.
2142 * And pcm_idx is pin_idx.
2143 */
2144 per_pin = get_pin(spec, pcm_idx);
909cadc6
TI		 2145 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2146 if (phantom_jack)
30efd8de
DH		 2147 strncat(hdmi_str, " Phantom",
2148 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
25e4abb3 2149 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
911761c2 2150 phantom_jack, 0, NULL);
25e4abb3
LY		 2151 if (ret < 0)
2152 return ret;
2153 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2154 if (jack == NULL)
2155 return 0;
2156 /* assign jack->jack to pcm_rec[].jack to
2157 * align with dyn_pcm_assign mode
2158 */
2159 spec->pcm_rec[pcm_idx].jack = jack->jack;
2160 return 0;
0b6c49b5
DH		 2161}
2162
84eb01be
TI		 2163static int generic_hdmi_build_controls(struct hda_codec *codec)
2164{
2165 struct hdmi_spec *spec = codec->spec;
1f7f51a6 2166 int dev, err;
25e4abb3 2167 int pin_idx, pcm_idx;
84eb01be 2168
25e4abb3 2169 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
8a7d6003
TI		 2170 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2171 /* no PCM: mark this for skipping permanently */
2172 set_bit(pcm_idx, &spec->pcm_bitmap);
2173 continue;
2174 }
2175
25e4abb3 2176 err = generic_hdmi_build_jack(codec, pcm_idx);
0b6c49b5
DH		 2177 if (err < 0)
2178 return err;
2179
b09887f8
LY		 2180 /* create the spdif for each pcm
2181 * pin will be bound when monitor is connected
2182 */
2183 if (spec->dyn_pcm_assign)
2184 err = snd_hda_create_dig_out_ctls(codec,
2185 0, spec->cvt_nids[0],
2186 HDA_PCM_TYPE_HDMI);
2187 else {
2188 struct hdmi_spec_per_pin *per_pin =
2189 get_pin(spec, pcm_idx);
2190 err = snd_hda_create_dig_out_ctls(codec,
dcda5806
TI		 2191 per_pin->pin_nid,
2192 per_pin->mux_nids[0],
2193 HDA_PCM_TYPE_HDMI);
b09887f8 2194 }
84eb01be
TI		 2195 if (err < 0)
2196 return err;
b09887f8 2197 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
14bc52b8 2198
1f7f51a6
WY		 2199 dev = get_pcm_rec(spec, pcm_idx)->device;
2200 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2201 /* add control for ELD Bytes */
2202 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2203 if (err < 0)
2204 return err;
2205 }
fb087eaa
LY		 2206 }
2207
2208 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2209 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
31ef2257 2210
82b1d73f 2211 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2212 }
2213
d45e6889 2214 /* add channel maps */
022f344b 2215 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
bbbc7e85 2216 struct hda_pcm *pcm;
2ca320e2 2217
022f344b 2218 pcm = get_pcm_rec(spec, pcm_idx);
bbbc7e85 2219 if (!pcm || !pcm->pcm)
2ca320e2 2220 break;
2f6e8a85 2221 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
d45e6889
TI		 2222 if (err < 0)
2223 return err;
d45e6889
TI		 2224 }
2225
84eb01be
TI		 2226 return 0;
2227}
2228
8b8d654b 2229static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2230{
2231 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2232 int pin_idx;
2233
2234 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2235 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2236
744626da 2237 per_pin->codec = codec;
a4e9a38b 2238 mutex_init(&per_pin->lock);
744626da 2239 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2240 eld_proc_new(per_pin, pin_idx);
84eb01be 2241 }
8b8d654b
TI		 2242 return 0;
2243}
2244
2245static int generic_hdmi_init(struct hda_codec *codec)
2246{
2247 struct hdmi_spec *spec = codec->spec;
2248 int pin_idx;
2249
2250 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2251 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b 2252 hda_nid_t pin_nid = per_pin->pin_nid;
9152085d 2253 int dev_id = per_pin->dev_id;
8b8d654b 2254
9152085d 2255 snd_hda_set_dev_select(codec, pin_nid, dev_id);
8b8d654b 2256 hdmi_init_pin(codec, pin_nid);
788d441a
TI		 2257 if (!codec_has_acomp(codec))
2258 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2259 codec->jackpoll_interval > 0 ?
2260 jack_callback : NULL);
8b8d654b 2261 }
84eb01be
TI		 2262 return 0;
2263}
2264
bce0d2a8
TI		 2265static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2266{
2267 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2268 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
bce0d2a8
TI		 2269}
2270
2271static void hdmi_array_free(struct hdmi_spec *spec)
2272{
2273 snd_array_free(&spec->pins);
2274 snd_array_free(&spec->cvts);
bce0d2a8
TI		 2275}
2276
a686632f
TI		 2277static void generic_spec_free(struct hda_codec *codec)
2278{
2279 struct hdmi_spec *spec = codec->spec;
2280
2281 if (spec) {
2282 hdmi_array_free(spec);
2283 kfree(spec);
2284 codec->spec = NULL;
2285 }
2286 codec->dp_mst = false;
2287}
2288
84eb01be
TI		 2289static void generic_hdmi_free(struct hda_codec *codec)
2290{
2291 struct hdmi_spec *spec = codec->spec;
25e4abb3 2292 int pin_idx, pcm_idx;
384a48d7 2293
6603249d 2294 if (codec_has_acomp(codec))
a57942bf 2295 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
25adc137 2296
384a48d7 2297 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2298 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2f35c630 2299 cancel_delayed_work_sync(&per_pin->work);
a4e9a38b 2300 eld_proc_free(per_pin);
25e4abb3
LY		 2301 }
2302
2303 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2304 if (spec->pcm_rec[pcm_idx].jack == NULL)
2305 continue;
2306 if (spec->dyn_pcm_assign)
2307 snd_device_free(codec->card,
2308 spec->pcm_rec[pcm_idx].jack);
2309 else
2310 spec->pcm_rec[pcm_idx].jack = NULL;
384a48d7 2311 }
84eb01be 2312
a686632f 2313 generic_spec_free(codec);
84eb01be
TI		 2314}
2315
28cb72e5
WX		 2316#ifdef CONFIG_PM
2317static int generic_hdmi_resume(struct hda_codec *codec)
2318{
2319 struct hdmi_spec *spec = codec->spec;
2320 int pin_idx;
2321
a2833683 2322 codec->patch_ops.init(codec);
eeecd9d1 2323 regcache_sync(codec->core.regmap);
28cb72e5
WX		 2324
2325 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2326 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2327 hdmi_present_sense(per_pin, 1);
2328 }
2329 return 0;
2330}
2331#endif
2332
fb79e1e0 2333static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2334 .init = generic_hdmi_init,
2335 .free = generic_hdmi_free,
2336 .build_pcms = generic_hdmi_build_pcms,
2337 .build_controls = generic_hdmi_build_controls,
2338 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2339#ifdef CONFIG_PM
2340 .resume = generic_hdmi_resume,
2341#endif
84eb01be
TI		 2342};
2343
307229d2
AH		 2344static const struct hdmi_ops generic_standard_hdmi_ops = {
2345 .pin_get_eld = snd_hdmi_get_eld,
307229d2
AH		 2346 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2347 .pin_hbr_setup = hdmi_pin_hbr_setup,
2348 .setup_stream = hdmi_setup_stream,
67b90cb8
SP		 2349};
2350
a686632f
TI		 2351/* allocate codec->spec and assign/initialize generic parser ops */
2352static int alloc_generic_hdmi(struct hda_codec *codec)
2353{
2354 struct hdmi_spec *spec;
2355
2356 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2357 if (!spec)
2358 return -ENOMEM;
2359
2360 spec->ops = generic_standard_hdmi_ops;
9152085d 2361 spec->dev_num = 1; /* initialize to 1 */
a686632f
TI		 2362 mutex_init(&spec->pcm_lock);
2363 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2364
2365 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2366 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2367 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
44fde3b8 2368 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
a686632f
TI		 2369
2370 codec->spec = spec;
2371 hdmi_array_init(spec, 4);
2372
2373 codec->patch_ops = generic_hdmi_patch_ops;
2374
2375 return 0;
2376}
2377
2378/* generic HDMI parser */
2379static int patch_generic_hdmi(struct hda_codec *codec)
2380{
2381 int err;
2382
2383 err = alloc_generic_hdmi(codec);
2384 if (err < 0)
2385 return err;
2386
2387 err = hdmi_parse_codec(codec);
2388 if (err < 0) {
2389 generic_spec_free(codec);
2390 return err;
2391 }
2392
2393 generic_hdmi_init_per_pins(codec);
2394 return 0;
2395}
2396
2397/*
2398 * Intel codec parsers and helpers
2399 */
2400
c88d4e84
TI		 2401static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2402 hda_nid_t nid)
2403{
2404 struct hdmi_spec *spec = codec->spec;
2405 hda_nid_t conns[4];
2406 int nconns;
6ffe168f 2407
c88d4e84
TI		 2408 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2409 if (nconns == spec->num_cvts &&
2410 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2411 return;
2412
c88d4e84 2413 /* override pins connection list */
4e76a883 2414 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
c88d4e84 2415 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2416}
2417
b0d8bc50
JK		 2418#define INTEL_GET_VENDOR_VERB 0xf81
2419#define INTEL_GET_VENDOR_VERB 0xf81
2420#define INTEL_SET_VENDOR_VERB 0x781
2421#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2422#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
1611a9c9
ML		 2423
2424static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2425 bool update_tree)
1611a9c9
ML		 2426{
2427 unsigned int vendor_param;
a87a4d23 2428 struct hdmi_spec *spec = codec->spec;
1611a9c9 2429
a87a4d23 2430 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
1611a9c9
ML		 2431 INTEL_GET_VENDOR_VERB, 0);
2432 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2433 return;
2434
2435 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
a87a4d23 2436 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
1611a9c9
ML		 2437 INTEL_SET_VENDOR_VERB, vendor_param);
2438 if (vendor_param == -1)
2439 return;
2440
17df3f55
TI		 2441 if (update_tree)
2442 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2443}
2444
c88d4e84
TI		 2445static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2446{
2447 unsigned int vendor_param;
a87a4d23 2448 struct hdmi_spec *spec = codec->spec;
c88d4e84 2449
a87a4d23 2450 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
c88d4e84
TI		 2451 INTEL_GET_VENDOR_VERB, 0);
2452 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2453 return;
2454
2455 /* enable DP1.2 mode */
2456 vendor_param |= INTEL_EN_DP12;
a551d914 2457 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
a87a4d23 2458 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
c88d4e84
TI		 2459 INTEL_SET_VENDOR_VERB, vendor_param);
2460}
2461
17df3f55
TI		 2462/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2463 * Otherwise you may get severe h/w communication errors.
2464 */
2465static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2466 unsigned int power_state)
2467{
2468 if (power_state == AC_PWRST_D0) {
2469 intel_haswell_enable_all_pins(codec, false);
2470 intel_haswell_fixup_enable_dp12(codec);
2471 }
c88d4e84 2472
17df3f55
TI		 2473 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2474 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2475}
6ffe168f 2476
a57942bf
TI		 2477/* There is a fixed mapping between audio pin node and display port.
2478 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2479 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2480 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2481 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2482 *
2483 * on VLV, ILK:
2484 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2485 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2486 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2487 */
2488static int intel_base_nid(struct hda_codec *codec)
2489{
2490 switch (codec->core.vendor_id) {
2491 case 0x80860054: /* ILK */
2492 case 0x80862804: /* ILK */
2493 case 0x80862882: /* VLV */
2494 return 4;
2495 default:
2496 return 5;
2497 }
2498}
2499
2500static int intel_pin2port(void *audio_ptr, int pin_nid)
2501{
b0d8bc50
JK		 2502 struct hda_codec *codec = audio_ptr;
2503 struct hdmi_spec *spec = codec->spec;
2504 int base_nid, i;
a57942bf 2505
b0d8bc50
JK		 2506 if (!spec->port_num) {
2507 base_nid = intel_base_nid(codec);
2508 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2509 return -1;
2510 return pin_nid - base_nid + 1; /* intel port is 1-based */
2511 }
2512
2513 /*
2514 * looking for the pin number in the mapping table and return
2515 * the index which indicate the port number
2516 */
2517 for (i = 0; i < spec->port_num; i++) {
2518 if (pin_nid == spec->port_map[i])
2519 return i + 1;
2520 }
2521
2522 /* return -1 if pin number exceeds our expectation */
2523 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid);
2524 return -1;
a57942bf
TI		 2525}
2526
f9318941 2527static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
25adc137
DH		 2528{
2529 struct hda_codec *codec = audio_ptr;
7ff652ff 2530 int pin_nid;
9152085d 2531 int dev_id = pipe;
25adc137 2532
4f8e4f35
TI		 2533 /* we assume only from port-B to port-D */
2534 if (port < 1 || port > 3)
2535 return;
2536
a57942bf 2537 pin_nid = port + intel_base_nid(codec) - 1; /* intel port is 1-based */
7ff652ff 2538
8ae743e8
TI		 2539 /* skip notification during system suspend (but not in runtime PM);
2540 * the state will be updated at resume
2541 */
2542 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2543 return;
eb399d3c 2544 /* ditto during suspend/resume process itself */
feb20fae 2545 if (snd_hdac_is_in_pm(&codec->core))
eb399d3c 2546 return;
8ae743e8 2547
bb03ed21 2548 snd_hdac_i915_set_bclk(&codec->bus->core);
9152085d 2549 check_presence_and_report(codec, pin_nid, dev_id);
25adc137
DH		 2550}
2551
a686632f
TI		 2552/* register i915 component pin_eld_notify callback */
2553static void register_i915_notifier(struct hda_codec *codec)
84eb01be 2554{
a686632f 2555 struct hdmi_spec *spec = codec->spec;
84eb01be 2556
a686632f 2557 spec->use_acomp_notifier = true;
ae891abe 2558 spec->drm_audio_ops.audio_ptr = codec;
a686632f
TI		 2559 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2560 * will call pin_eld_notify with using audio_ptr pointer
2561 * We need make sure audio_ptr is really setup
2562 */
2563 wmb();
a57942bf 2564 spec->drm_audio_ops.pin2port = intel_pin2port;
ae891abe 2565 spec->drm_audio_ops.pin_eld_notify = intel_pin_eld_notify;
a57942bf 2566 snd_hdac_acomp_register_notifier(&codec->bus->core,
82887c0b 2567 &spec->drm_audio_ops);
a686632f 2568}
84eb01be 2569
2c1c9b86
TI		 2570/* setup_stream ops override for HSW+ */
2571static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2572 hda_nid_t pin_nid, u32 stream_tag, int format)
2573{
2574 haswell_verify_D0(codec, cvt_nid, pin_nid);
2575 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2576}
739ffee9 2577
4846a67e
TI		 2578/* pin_cvt_fixup ops override for HSW+ and VLV+ */
2579static void i915_pin_cvt_fixup(struct hda_codec *codec,
2580 struct hdmi_spec_per_pin *per_pin,
2581 hda_nid_t cvt_nid)
2582{
2583 if (per_pin) {
9152085d
LY		 2584 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2585 per_pin->dev_id);
4846a67e
TI		 2586 intel_verify_pin_cvt_connect(codec, per_pin);
2587 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
9152085d 2588 per_pin->dev_id, per_pin->mux_idx);
4846a67e 2589 } else {
9152085d 2590 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
4846a67e
TI		 2591 }
2592}
739ffee9 2593
43f6c8d9
TI		 2594/* precondition and allocation for Intel codecs */
2595static int alloc_intel_hdmi(struct hda_codec *codec)
a686632f 2596{
43f6c8d9 2597 /* requires i915 binding */
a686632f
TI		 2598 if (!codec->bus->core.audio_component) {
2599 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
fdd49c51
TI		 2600 /* set probe_id here to prevent generic fallback binding */
2601 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
a686632f 2602 return -ENODEV;
691be973 2603 }
55913110 2604
43f6c8d9
TI		 2605 return alloc_generic_hdmi(codec);
2606}
2607
2608/* parse and post-process for Intel codecs */
2609static int parse_intel_hdmi(struct hda_codec *codec)
2610{
2611 int err;
2612
2613 err = hdmi_parse_codec(codec);
2614 if (err < 0) {
2615 generic_spec_free(codec);
2616 return err;
2617 }
2618
2619 generic_hdmi_init_per_pins(codec);
2620 register_i915_notifier(codec);
2621 return 0;
2622}
2623
2624/* Intel Haswell and onwards; audio component with eld notifier */
b0d8bc50
JK		 2625static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
2626 const int *port_map, int port_num)
43f6c8d9
TI		 2627{
2628 struct hdmi_spec *spec;
2629 int err;
2630
2631 err = alloc_intel_hdmi(codec);
a686632f
TI		 2632 if (err < 0)
2633 return err;
2634 spec = codec->spec;
9152085d
LY		 2635 codec->dp_mst = true;
2636 spec->dyn_pcm_assign = true;
a87a4d23 2637 spec->vendor_nid = vendor_nid;
b0d8bc50
JK		 2638 spec->port_map = port_map;
2639 spec->port_num = port_num;
6ffe168f 2640
a686632f
TI		 2641 intel_haswell_enable_all_pins(codec, true);
2642 intel_haswell_fixup_enable_dp12(codec);
2643
46594d33 2644 codec->display_power_control = 1;
2bd1f73f 2645
a686632f 2646 codec->patch_ops.set_power_state = haswell_set_power_state;
a686632f
TI		 2647 codec->depop_delay = 0;
2648 codec->auto_runtime_pm = 1;
2649
2c1c9b86 2650 spec->ops.setup_stream = i915_hsw_setup_stream;
4846a67e 2651 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2c1c9b86 2652
43f6c8d9 2653 return parse_intel_hdmi(codec);
a686632f
TI		 2654}
2655
a87a4d23
ACDO		 2656static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2657{
b0d8bc50 2658 return intel_hsw_common_init(codec, 0x08, NULL, 0);
a87a4d23
ACDO		 2659}
2660
2661static int patch_i915_glk_hdmi(struct hda_codec *codec)
2662{
b0d8bc50
JK		 2663 return intel_hsw_common_init(codec, 0x0b, NULL, 0);
2664}
2665
2666static int patch_i915_icl_hdmi(struct hda_codec *codec)
2667{
2668 /*
2669 * pin to port mapping table where the value indicate the pin number and
2670 * the index indicate the port number with 1 base.
2671 */
2672 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb};
2673
2674 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
a87a4d23
ACDO		 2675}
2676
7ff652ff 2677/* Intel Baytrail and Braswell; with eld notifier */
a686632f
TI		 2678static int patch_i915_byt_hdmi(struct hda_codec *codec)
2679{
2680 struct hdmi_spec *spec;
2681 int err;
2682
43f6c8d9 2683 err = alloc_intel_hdmi(codec);
a686632f
TI		 2684 if (err < 0)
2685 return err;
2686 spec = codec->spec;
2377c3c3 2687
a686632f
TI		 2688 /* For Valleyview/Cherryview, only the display codec is in the display
2689 * power well and can use link_power ops to request/release the power.
2690 */
029d92c2 2691 codec->display_power_control = 1;
84eb01be 2692
a686632f
TI		 2693 codec->depop_delay = 0;
2694 codec->auto_runtime_pm = 1;
84eb01be 2695
4846a67e
TI		 2696 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2697
43f6c8d9 2698 return parse_intel_hdmi(codec);
84eb01be
TI		 2699}
2700
7ff652ff 2701/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
e85015a3
TI		 2702static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2703{
e85015a3
TI		 2704 int err;
2705
43f6c8d9 2706 err = alloc_intel_hdmi(codec);
e85015a3
TI		 2707 if (err < 0)
2708 return err;
43f6c8d9 2709 return parse_intel_hdmi(codec);
84eb01be
TI		 2710}
2711
3aaf8980
SW		 2712/*
2713 * Shared non-generic implementations
2714 */
2715
2716static int simple_playback_build_pcms(struct hda_codec *codec)
2717{
2718 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2719 struct hda_pcm *info;
8ceb332d
TI		 2720 unsigned int chans;
2721 struct hda_pcm_stream *pstr;
bce0d2a8 2722 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2723
bce0d2a8
TI		 2724 per_cvt = get_cvt(spec, 0);
2725 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2726 chans = get_wcaps_channels(chans);
3aaf8980 2727
bbbc7e85 2728 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
bce0d2a8
TI		 2729 if (!info)
2730 return -ENOMEM;
2bea241a 2731 spec->pcm_rec[0].pcm = info;
8ceb332d
TI		 2732 info->pcm_type = HDA_PCM_TYPE_HDMI;
2733 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2734 *pstr = spec->pcm_playback;
bce0d2a8 2735 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2736 if (pstr->channels_max <= 2 && chans && chans <= 16)
2737 pstr->channels_max = chans;
3aaf8980
SW		 2738
2739 return 0;
2740}
2741
4b6ace9e
TI		 2742/* unsolicited event for jack sensing */
2743static void simple_hdmi_unsol_event(struct hda_codec *codec,
2744 unsigned int res)
2745{
9dd8cf12 2746 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2747 snd_hda_jack_report_sync(codec);
2748}
2749
2750/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2751 * as long as spec->pins[] is set correctly
2752 */
2753#define simple_hdmi_build_jack generic_hdmi_build_jack
2754
3aaf8980
SW		 2755static int simple_playback_build_controls(struct hda_codec *codec)
2756{
2757 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2758 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2759 int err;
3aaf8980 2760
bce0d2a8 2761 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 2762 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2763 per_cvt->cvt_nid,
2764 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 2765 if (err < 0)
2766 return err;
2767 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2768}
2769
4f0110ce
TI		 2770static int simple_playback_init(struct hda_codec *codec)
2771{
2772 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2773 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2774 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2775
2776 snd_hda_codec_write(codec, pin, 0,
2777 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2778 /* some codecs require to unmute the pin */
2779 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2780 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2781 AMP_OUT_UNMUTE);
62f949bf 2782 snd_hda_jack_detect_enable(codec, pin);
4f0110ce
TI		 2783 return 0;
2784}
2785
3aaf8980
SW		 2786static void simple_playback_free(struct hda_codec *codec)
2787{
2788 struct hdmi_spec *spec = codec->spec;
2789
bce0d2a8 2790 hdmi_array_free(spec);
3aaf8980
SW		 2791 kfree(spec);
2792}
2793
84eb01be
TI		 2794/*
2795 * Nvidia specific implementations
2796 */
2797
2798#define Nv_VERB_SET_Channel_Allocation 0xF79
2799#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2800#define Nv_VERB_SET_Audio_Protection_On 0xF98
2801#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2802
2803#define nvhdmi_master_con_nid_7x 0x04
2804#define nvhdmi_master_pin_nid_7x 0x05
2805
fb79e1e0 2806static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2807 /*front, rear, clfe, rear_surr */
2808 0x6, 0x8, 0xa, 0xc,
2809};
2810
ceaa86ba
TI		 2811static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2812 /* set audio protect on */
2813 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2814 /* enable digital output on pin widget */
2815 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2816 {} /* terminator */
2817};
2818
2819static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2820 /* set audio protect on */
2821 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2822 /* enable digital output on pin widget */
2823 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2824 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2825 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2826 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2827 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2828 {} /* terminator */
2829};
2830
2831#ifdef LIMITED_RATE_FMT_SUPPORT
2832/* support only the safe format and rate */
2833#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2834#define SUPPORTED_MAXBPS 16
2835#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2836#else
2837/* support all rates and formats */
2838#define SUPPORTED_RATES \
2839 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2840 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2841 SNDRV_PCM_RATE_192000)
2842#define SUPPORTED_MAXBPS 24
2843#define SUPPORTED_FORMATS \
2844 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2845#endif
2846
ceaa86ba
TI		 2847static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2848{
2849 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2850 return 0;
2851}
2852
2853static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2854{
ceaa86ba 2855 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2856 return 0;
2857}
2858
50c697ad 2859static const unsigned int channels_2_6_8[] = {
393004b2
ND		 2860 2, 6, 8
2861};
2862
50c697ad 2863static const unsigned int channels_2_8[] = {
393004b2
ND		 2864 2, 8
2865};
2866
50c697ad 2867static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
393004b2
ND		 2868 .count = ARRAY_SIZE(channels_2_6_8),
2869 .list = channels_2_6_8,
2870 .mask = 0,
2871};
2872
50c697ad 2873static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
393004b2
ND		 2874 .count = ARRAY_SIZE(channels_2_8),
2875 .list = channels_2_8,
2876 .mask = 0,
2877};
2878
84eb01be
TI		 2879static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2880 struct hda_codec *codec,
2881 struct snd_pcm_substream *substream)
2882{
2883 struct hdmi_spec *spec = codec->spec;
50c697ad 2884 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
393004b2 2885
b9a94a9c 2886 switch (codec->preset->vendor_id) {
393004b2
ND		 2887 case 0x10de0002:
2888 case 0x10de0003:
2889 case 0x10de0005:
2890 case 0x10de0006:
2891 hw_constraints_channels = &hw_constraints_2_8_channels;
2892 break;
2893 case 0x10de0007:
2894 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2895 break;
2896 default:
2897 break;
2898 }
2899
2900 if (hw_constraints_channels != NULL) {
2901 snd_pcm_hw_constraint_list(substream->runtime, 0,
2902 SNDRV_PCM_HW_PARAM_CHANNELS,
2903 hw_constraints_channels);
ad09fc9d
TI		 2904 } else {
2905 snd_pcm_hw_constraint_step(substream->runtime, 0,
2906 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2907 }
2908
84eb01be
TI		 2909 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2910}
2911
2912static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2913 struct hda_codec *codec,
2914 struct snd_pcm_substream *substream)
2915{
2916 struct hdmi_spec *spec = codec->spec;
2917 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2918}
2919
2920static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2921 struct hda_codec *codec,
2922 unsigned int stream_tag,
2923 unsigned int format,
2924 struct snd_pcm_substream *substream)
2925{
2926 struct hdmi_spec *spec = codec->spec;
2927 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2928 stream_tag, format, substream);
2929}
2930
d0b1252d
TI		 2931static const struct hda_pcm_stream simple_pcm_playback = {
2932 .substreams = 1,
2933 .channels_min = 2,
2934 .channels_max = 2,
2935 .ops = {
2936 .open = simple_playback_pcm_open,
2937 .close = simple_playback_pcm_close,
2938 .prepare = simple_playback_pcm_prepare
2939 },
2940};
2941
2942static const struct hda_codec_ops simple_hdmi_patch_ops = {
2943 .build_controls = simple_playback_build_controls,
2944 .build_pcms = simple_playback_build_pcms,
2945 .init = simple_playback_init,
2946 .free = simple_playback_free,
250e41ac 2947 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2948};
2949
2950static int patch_simple_hdmi(struct hda_codec *codec,
2951 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2952{
2953 struct hdmi_spec *spec;
bce0d2a8
TI		 2954 struct hdmi_spec_per_cvt *per_cvt;
2955 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2956
2957 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2958 if (!spec)
2959 return -ENOMEM;
2960
2961 codec->spec = spec;
bce0d2a8 2962 hdmi_array_init(spec, 1);
d0b1252d
TI		 2963
2964 spec->multiout.num_dacs = 0; /* no analog */
2965 spec->multiout.max_channels = 2;
2966 spec->multiout.dig_out_nid = cvt_nid;
2967 spec->num_cvts = 1;
2968 spec->num_pins = 1;
bce0d2a8
TI		 2969 per_pin = snd_array_new(&spec->pins);
2970 per_cvt = snd_array_new(&spec->cvts);
2971 if (!per_pin || !per_cvt) {
2972 simple_playback_free(codec);
2973 return -ENOMEM;
2974 }
2975 per_cvt->cvt_nid = cvt_nid;
2976 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2977 spec->pcm_playback = simple_pcm_playback;
2978
2979 codec->patch_ops = simple_hdmi_patch_ops;
2980
2981 return 0;
2982}
2983
1f348522
AP		 2984static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2985 int channels)
2986{
2987 unsigned int chanmask;
2988 int chan = channels ? (channels - 1) : 1;
2989
2990 switch (channels) {
2991 default:
2992 case 0:
2993 case 2:
2994 chanmask = 0x00;
2995 break;
2996 case 4:
2997 chanmask = 0x08;
2998 break;
2999 case 6:
3000 chanmask = 0x0b;
3001 break;
3002 case 8:
3003 chanmask = 0x13;
3004 break;
3005 }
3006
3007 /* Set the audio infoframe channel allocation and checksum fields. The
3008 * channel count is computed implicitly by the hardware. */
3009 snd_hda_codec_write(codec, 0x1, 0,
3010 Nv_VERB_SET_Channel_Allocation, chanmask);
3011
3012 snd_hda_codec_write(codec, 0x1, 0,
3013 Nv_VERB_SET_Info_Frame_Checksum,
3014 (0x71 - chan - chanmask));
3015}
3016
84eb01be
TI		 3017static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3018 struct hda_codec *codec,
3019 struct snd_pcm_substream *substream)
3020{
3021 struct hdmi_spec *spec = codec->spec;
3022 int i;
3023
3024 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3025 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3026 for (i = 0; i < 4; i++) {
3027 /* set the stream id */
3028 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3029 AC_VERB_SET_CHANNEL_STREAMID, 0);
3030 /* set the stream format */
3031 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3032 AC_VERB_SET_STREAM_FORMAT, 0);
3033 }
3034
1f348522
AP		 3035 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3036 * streams are disabled. */
3037 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3038
84eb01be
TI		 3039 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3040}
3041
3042static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3043 struct hda_codec *codec,
3044 unsigned int stream_tag,
3045 unsigned int format,
3046 struct snd_pcm_substream *substream)
3047{
3048 int chs;
112daa7a 3049 unsigned int dataDCC2, channel_id;
84eb01be 3050 int i;
7c935976 3051 struct hdmi_spec *spec = codec->spec;
e3245cdd 3052 struct hda_spdif_out *spdif;
bce0d2a8 3053 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 3054
3055 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 3056 per_cvt = get_cvt(spec, 0);
3057 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 3058
3059 chs = substream->runtime->channels;
84eb01be 3060
84eb01be
TI		 3061 dataDCC2 = 0x2;
3062
84eb01be 3063 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 3064 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3065 snd_hda_codec_write(codec,
3066 nvhdmi_master_con_nid_7x,
3067 0,
3068 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3069 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3070
3071 /* set the stream id */
3072 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3073 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3074
3075 /* set the stream format */
3076 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3077 AC_VERB_SET_STREAM_FORMAT, format);
3078
3079 /* turn on again (if needed) */
3080 /* enable and set the channel status audio/data flag */
7c935976 3081 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3082 snd_hda_codec_write(codec,
3083 nvhdmi_master_con_nid_7x,
3084 0,
3085 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3086 spdif->ctls & 0xff);
84eb01be
TI		 3087 snd_hda_codec_write(codec,
3088 nvhdmi_master_con_nid_7x,
3089 0,
3090 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3091 }
3092
3093 for (i = 0; i < 4; i++) {
3094 if (chs == 2)
3095 channel_id = 0;
3096 else
3097 channel_id = i * 2;
3098
3099 /* turn off SPDIF once;
3100 *otherwise the IEC958 bits won't be updated
3101 */
3102 if (codec->spdif_status_reset &&
7c935976 3103 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3104 snd_hda_codec_write(codec,
3105 nvhdmi_con_nids_7x[i],
3106 0,
3107 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3108 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3109 /* set the stream id */
3110 snd_hda_codec_write(codec,
3111 nvhdmi_con_nids_7x[i],
3112 0,
3113 AC_VERB_SET_CHANNEL_STREAMID,
3114 (stream_tag << 4) | channel_id);
3115 /* set the stream format */
3116 snd_hda_codec_write(codec,
3117 nvhdmi_con_nids_7x[i],
3118 0,
3119 AC_VERB_SET_STREAM_FORMAT,
3120 format);
3121 /* turn on again (if needed) */
3122 /* enable and set the channel status audio/data flag */
3123 if (codec->spdif_status_reset &&
7c935976 3124 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3125 snd_hda_codec_write(codec,
3126 nvhdmi_con_nids_7x[i],
3127 0,
3128 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3129 spdif->ctls & 0xff);
84eb01be
TI		 3130 snd_hda_codec_write(codec,
3131 nvhdmi_con_nids_7x[i],
3132 0,
3133 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3134 }
3135 }
3136
1f348522 3137 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 3138
3139 mutex_unlock(&codec->spdif_mutex);
3140 return 0;
3141}
3142
fb79e1e0 3143static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 3144 .substreams = 1,
3145 .channels_min = 2,
3146 .channels_max = 8,
3147 .nid = nvhdmi_master_con_nid_7x,
3148 .rates = SUPPORTED_RATES,
3149 .maxbps = SUPPORTED_MAXBPS,
3150 .formats = SUPPORTED_FORMATS,
3151 .ops = {
3152 .open = simple_playback_pcm_open,
3153 .close = nvhdmi_8ch_7x_pcm_close,
3154 .prepare = nvhdmi_8ch_7x_pcm_prepare
3155 },
3156};
3157
84eb01be
TI		 3158static int patch_nvhdmi_2ch(struct hda_codec *codec)
3159{
3160 struct hdmi_spec *spec;
d0b1252d
TI		 3161 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3162 nvhdmi_master_pin_nid_7x);
3163 if (err < 0)
3164 return err;
84eb01be 3165
ceaa86ba 3166 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 3167 /* override the PCM rates, etc, as the codec doesn't give full list */
3168 spec = codec->spec;
3169 spec->pcm_playback.rates = SUPPORTED_RATES;
3170 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3171 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 3172 return 0;
3173}
3174
53775b0d
TI		 3175static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3176{
3177 struct hdmi_spec *spec = codec->spec;
3178 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 3179 if (!err) {
3180 struct hda_pcm *info = get_pcm_rec(spec, 0);
3181 info->own_chmap = true;
3182 }
53775b0d
TI		 3183 return err;
3184}
3185
3186static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3187{
3188 struct hdmi_spec *spec = codec->spec;
bce0d2a8 3189 struct hda_pcm *info;
53775b0d
TI		 3190 struct snd_pcm_chmap *chmap;
3191 int err;
3192
3193 err = simple_playback_build_controls(codec);
3194 if (err < 0)
3195 return err;
3196
3197 /* add channel maps */
bce0d2a8
TI		 3198 info = get_pcm_rec(spec, 0);
3199 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 3200 SNDRV_PCM_STREAM_PLAYBACK,
3201 snd_pcm_alt_chmaps, 8, 0, &chmap);
3202 if (err < 0)
3203 return err;
b9a94a9c 3204 switch (codec->preset->vendor_id) {
53775b0d
TI		 3205 case 0x10de0002:
3206 case 0x10de0003:
3207 case 0x10de0005:
3208 case 0x10de0006:
3209 chmap->channel_mask = (1U << 2) | (1U << 8);
3210 break;
3211 case 0x10de0007:
3212 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3213 }
3214 return 0;
3215}
3216
84eb01be
TI		 3217static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3218{
3219 struct hdmi_spec *spec;
3220 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 3221 if (err < 0)
3222 return err;
3223 spec = codec->spec;
3224 spec->multiout.max_channels = 8;
d0b1252d 3225 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 3226 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 3227 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3228 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 3229
3230 /* Initialize the audio infoframe channel mask and checksum to something
3231 * valid */
3232 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3233
84eb01be
TI		 3234 return 0;
3235}
3236
611885bc
AH		 3237/*
3238 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3239 * - 0x10de0015
3240 * - 0x10de0040
3241 */
67b90cb8 3242static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
f302240d 3243 struct hdac_cea_channel_speaker_allocation *cap, int channels)
611885bc
AH		 3244{
3245 if (cap->ca_index == 0x00 && channels == 2)
3246 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3247
028cb68e
SP		 3248 /* If the speaker allocation matches the channel count, it is OK. */
3249 if (cap->channels != channels)
3250 return -1;
3251
3252 /* all channels are remappable freely */
3253 return SNDRV_CTL_TLVT_CHMAP_VAR;
611885bc
AH		 3254}
3255
828cb4ed
SP		 3256static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3257 int ca, int chs, unsigned char *map)
611885bc
AH		 3258{
3259 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3260 return -EINVAL;
3261
3262 return 0;
3263}
3264
3265static int patch_nvhdmi(struct hda_codec *codec)
3266{
3267 struct hdmi_spec *spec;
3268 int err;
3269
3270 err = patch_generic_hdmi(codec);
3271 if (err)
3272 return err;
3273
3274 spec = codec->spec;
75fae117 3275 spec->dyn_pin_out = true;
611885bc 3276
67b90cb8 3277 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
611885bc 3278 nvhdmi_chmap_cea_alloc_validate_get_type;
67b90cb8 3279 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
611885bc
AH		 3280
3281 return 0;
3282}
3283
26e9a960
TR		 3284/*
3285 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3286 * accessed using vendor-defined verbs. These registers can be used for
3287 * interoperability between the HDA and HDMI drivers.
3288 */
3289
3290/* Audio Function Group node */
3291#define NVIDIA_AFG_NID 0x01
3292
3293/*
3294 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3295 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3296 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3297 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3298 * additional bit (at position 30) to signal the validity of the format.
3299 *
3300 * | 31 | 30 | 29 16 | 15 0 |
3301 * +---------+-------+--------+--------+
3302 * | TRIGGER | VALID | UNUSED | FORMAT |
3303 * +-----------------------------------|
3304 *
3305 * Note that for the trigger bit to take effect it needs to change value
3306 * (i.e. it needs to be toggled).
3307 */
3308#define NVIDIA_GET_SCRATCH0 0xfa6
3309#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3310#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3311#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3312#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3313#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3314#define NVIDIA_SCRATCH_VALID (1 << 6)
3315
3316#define NVIDIA_GET_SCRATCH1 0xfab
3317#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3318#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3319#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3320#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3321
3322/*
3323 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3324 * the format is invalidated so that the HDMI codec can be disabled.
3325 */
3326static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3327{
3328 unsigned int value;
3329
3330 /* bits [31:30] contain the trigger and valid bits */
3331 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3332 NVIDIA_GET_SCRATCH0, 0);
3333 value = (value >> 24) & 0xff;
3334
3335 /* bits [15:0] are used to store the HDA format */
3336 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3337 NVIDIA_SET_SCRATCH0_BYTE0,
3338 (format >> 0) & 0xff);
3339 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3340 NVIDIA_SET_SCRATCH0_BYTE1,
3341 (format >> 8) & 0xff);
3342
3343 /* bits [16:24] are unused */
3344 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3345 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3346
3347 /*
3348 * Bit 30 signals that the data is valid and hence that HDMI audio can
3349 * be enabled.
3350 */
3351 if (format == 0)
3352 value &= ~NVIDIA_SCRATCH_VALID;
3353 else
3354 value |= NVIDIA_SCRATCH_VALID;
3355
3356 /*
3357 * Whenever the trigger bit is toggled, an interrupt is raised in the
3358 * HDMI codec. The HDMI driver will use that as trigger to update its
3359 * configuration.
3360 */
3361 value ^= NVIDIA_SCRATCH_TRIGGER;
3362
3363 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3364 NVIDIA_SET_SCRATCH0_BYTE3, value);
3365}
3366
3367static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3368 struct hda_codec *codec,
3369 unsigned int stream_tag,
3370 unsigned int format,
3371 struct snd_pcm_substream *substream)
3372{
3373 int err;
3374
3375 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3376 format, substream);
3377 if (err < 0)
3378 return err;
3379
3380 /* notify the HDMI codec of the format change */
3381 tegra_hdmi_set_format(codec, format);
3382
3383 return 0;
3384}
3385
3386static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3387 struct hda_codec *codec,
3388 struct snd_pcm_substream *substream)
3389{
3390 /* invalidate the format in the HDMI codec */
3391 tegra_hdmi_set_format(codec, 0);
3392
3393 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3394}
3395
3396static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3397{
3398 struct hdmi_spec *spec = codec->spec;
3399 unsigned int i;
3400
3401 for (i = 0; i < spec->num_pins; i++) {
3402 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3403
3404 if (pcm->pcm_type == type)
3405 return pcm;
3406 }
3407
3408 return NULL;
3409}
3410
3411static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3412{
3413 struct hda_pcm_stream *stream;
3414 struct hda_pcm *pcm;
3415 int err;
3416
3417 err = generic_hdmi_build_pcms(codec);
3418 if (err < 0)
3419 return err;
3420
3421 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3422 if (!pcm)
3423 return -ENODEV;
3424
3425 /*
3426 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3427 * codec about format changes.
3428 */
3429 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3430 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3431 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3432
3433 return 0;
3434}
3435
3436static int patch_tegra_hdmi(struct hda_codec *codec)
3437{
3438 int err;
3439
3440 err = patch_generic_hdmi(codec);
3441 if (err)
3442 return err;
3443
3444 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3445
3446 return 0;
3447}
3448
84eb01be 3449/*
5a613584 3450 * ATI/AMD-specific implementations
84eb01be
TI		 3451 */
3452
5a613584 3453#define is_amdhdmi_rev3_or_later(codec) \
7639a06c
TI		 3454 ((codec)->core.vendor_id == 0x1002aa01 && \
3455 ((codec)->core.revision_id & 0xff00) >= 0x0300)
5a613584
AH		 3456#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3457
3458/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3459#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3460#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3461#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3462#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3463#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3464#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 3465#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 3466#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3467#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3468#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3469#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3470#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3471#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3472#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3473#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3474#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3475#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3476#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 3477#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 3478#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3479#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3480#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3481#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3482#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3483
84d69e79
AH		 3484/* AMD specific HDA cvt verbs */
3485#define ATI_VERB_SET_RAMP_RATE 0x770
3486#define ATI_VERB_GET_RAMP_RATE 0xf70
3487
5a613584
AH		 3488#define ATI_OUT_ENABLE 0x1
3489
3490#define ATI_MULTICHANNEL_MODE_PAIRED 0
3491#define ATI_MULTICHANNEL_MODE_SINGLE 1
3492
461cf6b3
AH		 3493#define ATI_HBR_CAPABLE 0x01
3494#define ATI_HBR_ENABLE 0x10
3495
89250f84
AH		 3496static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3497 unsigned char *buf, int *eld_size)
3498{
3499 /* call hda_eld.c ATI/AMD-specific function */
3500 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3501 is_amdhdmi_rev3_or_later(codec));
3502}
3503
5a613584
AH		 3504static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3505 int active_channels, int conn_type)
3506{
3507 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3508}
3509
3510static int atihdmi_paired_swap_fc_lfe(int pos)
3511{
3512 /*
3513 * ATI/AMD have automatic FC/LFE swap built-in
3514 * when in pairwise mapping mode.
3515 */
3516
3517 switch (pos) {
3518 /* see channel_allocations[].speakers[] */
3519 case 2: return 3;
3520 case 3: return 2;
3521 default: break;
3522 }
3523
3524 return pos;
3525}
3526
828cb4ed
SP		 3527static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3528 int ca, int chs, unsigned char *map)
5a613584 3529{
f302240d 3530 struct hdac_cea_channel_speaker_allocation *cap;
5a613584
AH		 3531 int i, j;
3532
3533 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3534
bb63f726 3535 cap = snd_hdac_get_ch_alloc_from_ca(ca);
5a613584 3536 for (i = 0; i < chs; ++i) {
bb63f726 3537 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
5a613584
AH		 3538 bool ok = false;
3539 bool companion_ok = false;
3540
3541 if (!mask)
3542 continue;
3543
3544 for (j = 0 + i % 2; j < 8; j += 2) {
3545 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3546 if (cap->speakers[chan_idx] == mask) {
3547 /* channel is in a supported position */
3548 ok = true;
3549
3550 if (i % 2 == 0 && i + 1 < chs) {
3551 /* even channel, check the odd companion */
3552 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
bb63f726 3553 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
5a613584
AH		 3554 int comp_mask_act = cap->speakers[comp_chan_idx];
3555
3556 if (comp_mask_req == comp_mask_act)
3557 companion_ok = true;
3558 else
3559 return -EINVAL;
3560 }
3561 break;
3562 }
3563 }
3564
3565 if (!ok)
3566 return -EINVAL;
3567
3568 if (companion_ok)
3569 i++; /* companion channel already checked */
3570 }
3571
3572 return 0;
3573}
3574
739ffee9
SP		 3575static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3576 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
5a613584 3577{
739ffee9 3578 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
5a613584
AH		 3579 int verb;
3580 int ati_channel_setup = 0;
3581
3582 if (hdmi_slot > 7)
3583 return -EINVAL;
3584
3585 if (!has_amd_full_remap_support(codec)) {
3586 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3587
3588 /* In case this is an odd slot but without stream channel, do not
3589 * disable the slot since the corresponding even slot could have a
3590 * channel. In case neither have a channel, the slot pair will be
3591 * disabled when this function is called for the even slot. */
3592 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3593 return 0;
3594
3595 hdmi_slot -= hdmi_slot % 2;
3596
3597 if (stream_channel != 0xf)
3598 stream_channel -= stream_channel % 2;
3599 }
3600
3601 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3602
3603 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3604
3605 if (stream_channel != 0xf)
3606 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3607
3608 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3609}
3610
739ffee9
SP		 3611static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3612 hda_nid_t pin_nid, int asp_slot)
5a613584 3613{
739ffee9 3614 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
5a613584
AH		 3615 bool was_odd = false;
3616 int ati_asp_slot = asp_slot;
3617 int verb;
3618 int ati_channel_setup;
3619
3620 if (asp_slot > 7)
3621 return -EINVAL;
3622
3623 if (!has_amd_full_remap_support(codec)) {
3624 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3625 if (ati_asp_slot % 2 != 0) {
3626 ati_asp_slot -= 1;
3627 was_odd = true;
3628 }
3629 }
3630
3631 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3632
3633 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3634
3635 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3636 return 0xf;
3637
3638 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3639}
84eb01be 3640
67b90cb8
SP		 3641static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3642 struct hdac_chmap *chmap,
f302240d 3643 struct hdac_cea_channel_speaker_allocation *cap,
67b90cb8 3644 int channels)
5a613584
AH		 3645{
3646 int c;
3647
3648 /*
3649 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3650 * we need to take that into account (a single channel may take 2
3651 * channel slots if we need to carry a silent channel next to it).
3652 * On Rev3+ AMD codecs this function is not used.
3653 */
3654 int chanpairs = 0;
3655
3656 /* We only produce even-numbered channel count TLVs */
3657 if ((channels % 2) != 0)
3658 return -1;
3659
3660 for (c = 0; c < 7; c += 2) {
3661 if (cap->speakers[c] || cap->speakers[c+1])
3662 chanpairs++;
3663 }
3664
3665 if (chanpairs * 2 != channels)
3666 return -1;
3667
3668 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3669}
3670
828cb4ed 3671static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
f302240d
SP		 3672 struct hdac_cea_channel_speaker_allocation *cap,
3673 unsigned int *chmap, int channels)
5a613584
AH		 3674{
3675 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3676 int count = 0;
3677 int c;
3678
3679 for (c = 7; c >= 0; c--) {
3680 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3681 int spk = cap->speakers[chan];
3682 if (!spk) {
3683 /* add N/A channel if the companion channel is occupied */
3684 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3685 chmap[count++] = SNDRV_CHMAP_NA;
3686
3687 continue;
3688 }
3689
bb63f726 3690 chmap[count++] = snd_hdac_spk_to_chmap(spk);
5a613584
AH		 3691 }
3692
3693 WARN_ON(count != channels);
3694}
3695
461cf6b3
AH		 3696static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3697 bool hbr)
3698{
3699 int hbr_ctl, hbr_ctl_new;
3700
3701 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3702 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3703 if (hbr)
3704 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3705 else
3706 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3707
4e76a883
TI		 3708 codec_dbg(codec,
3709 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
461cf6b3
AH		 3710 pin_nid,
3711 hbr_ctl == hbr_ctl_new ? "" : "new-",
3712 hbr_ctl_new);
3713
3714 if (hbr_ctl != hbr_ctl_new)
3715 snd_hda_codec_write(codec, pin_nid, 0,
3716 ATI_VERB_SET_HBR_CONTROL,
3717 hbr_ctl_new);
3718
3719 } else if (hbr)
3720 return -EINVAL;
3721
3722 return 0;
3723}
3724
84d69e79
AH		 3725static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3726 hda_nid_t pin_nid, u32 stream_tag, int format)
3727{
3728
3729 if (is_amdhdmi_rev3_or_later(codec)) {
3730 int ramp_rate = 180; /* default as per AMD spec */
3731 /* disable ramp-up/down for non-pcm as per AMD spec */
3732 if (format & AC_FMT_TYPE_NON_PCM)
3733 ramp_rate = 0;
3734
3735 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3736 }
3737
3738 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3739}
3740
3741
5a613584 3742static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3743{
3744 struct hdmi_spec *spec = codec->spec;
5a613584 3745 int pin_idx, err;
84eb01be 3746
5a613584
AH		 3747 err = generic_hdmi_init(codec);
3748
3749 if (err)
84eb01be 3750 return err;
5a613584
AH		 3751
3752 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3753 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3754
3755 /* make sure downmix information in infoframe is zero */
3756 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3757
3758 /* enable channel-wise remap mode if supported */
3759 if (has_amd_full_remap_support(codec))
3760 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3761 ATI_VERB_SET_MULTICHANNEL_MODE,
3762 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3763 }
5a613584 3764
84eb01be
TI		 3765 return 0;
3766}
3767
84eb01be
TI		 3768static int patch_atihdmi(struct hda_codec *codec)
3769{
3770 struct hdmi_spec *spec;
5a613584
AH		 3771 struct hdmi_spec_per_cvt *per_cvt;
3772 int err, cvt_idx;
3773
3774 err = patch_generic_hdmi(codec);
3775
3776 if (err)
d0b1252d 3777 return err;
5a613584
AH		 3778
3779 codec->patch_ops.init = atihdmi_init;
3780
d0b1252d 3781 spec = codec->spec;
5a613584 3782
89250f84 3783 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584 3784 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 3785 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 3786 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584 3787
39669225
TI		 3788 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3789 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3790
5a613584
AH		 3791 if (!has_amd_full_remap_support(codec)) {
3792 /* override to ATI/AMD-specific versions with pairwise mapping */
67b90cb8 3793 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
5a613584 3794 atihdmi_paired_chmap_cea_alloc_validate_get_type;
67b90cb8
SP		 3795 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3796 atihdmi_paired_cea_alloc_to_tlv_chmap;
3797 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
5a613584
AH		 3798 }
3799
3800 /* ATI/AMD converters do not advertise all of their capabilities */
3801 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3802 per_cvt = get_cvt(spec, cvt_idx);
3803 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3804 per_cvt->rates |= SUPPORTED_RATES;
3805 per_cvt->formats |= SUPPORTED_FORMATS;
3806 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3807 }
3808
67b90cb8 3809 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
5a613584 3810
57cb54e5
TI		 3811 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
3812 * the link-down as is. Tell the core to allow it.
3813 */
3814 codec->link_down_at_suspend = 1;
3815
84eb01be
TI		 3816 return 0;
3817}
3818
3de5ff88
AL		 3819/* VIA HDMI Implementation */
3820#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3821#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3822
3de5ff88
AL		 3823static int patch_via_hdmi(struct hda_codec *codec)
3824{
250e41ac 3825 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3826}
84eb01be
TI		 3827
3828/*
3829 * patch entries
3830 */
b9a94a9c
TI		 3831static const struct hda_device_id snd_hda_id_hdmi[] = {
3832HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3833HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3834HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3835HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3836HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3837HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3838HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
74ec1181 3839HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
b9a94a9c
TI		 3840HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3841HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
74ec1181 3842HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
b9a94a9c
TI		 3843HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3844HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3845HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
74ec1181
DD		 3846HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
3847HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
b9a94a9c
TI		 3848HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3849HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3850HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3851HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3852HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3853HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3854HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3855HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3856HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3857HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3858HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
c8900a0f 3859/* 17 is known to be absent */
b9a94a9c
TI		 3860HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3861HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3862HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3863HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3864HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3865HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3866HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3867HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3868HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
917bb90c
TR		 3869HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
3870HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
3871HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
3872HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
b9a94a9c
TI		 3873HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3874HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3875HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3876HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3877HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 3878HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
3879HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
b9a94a9c 3880HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
74ec1181 3881HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
b9a94a9c 3882HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 3883HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
3884HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
b9a94a9c
TI		 3885HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3886HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3887HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3888HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 3889HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
3890HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
3891HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
3892HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
3893HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
b9a94a9c 3894HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
74ec1181 3895HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
af677166 3896HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
74ec1181 3897HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
2d369c74 3898HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3ec622f4 3899HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 3900HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
3901HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
3902HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
3903HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
3904HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
3905HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
3906HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
3907HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
3908HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
3909HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
b9a94a9c 3910HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
74ec1181 3911HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
b9a94a9c
TI		 3912HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3913HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3914HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3915HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
7ff652ff 3916HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
b0d8bc50 3917HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
b9a94a9c
TI		 3918HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3919HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3920HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
7ff652ff 3921HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
e85015a3
TI		 3922HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3923HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
a686632f
TI		 3924HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
3925HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
3926HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
3927HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
3928HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
2b4584d0 3929HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
a87a4d23 3930HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
b0d8bc50 3931HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
b9a94a9c 3932HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
a686632f
TI		 3933HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3934HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
b9a94a9c 3935HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
d8a766a1 3936/* special ID for generic HDMI */
b9a94a9c 3937HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
84eb01be
TI		 3938{} /* terminator */
3939};
b9a94a9c 3940MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
84eb01be
TI		 3941
3942MODULE_LICENSE("GPL");
3943MODULE_DESCRIPTION("HDMI HD-audio codec");
3944MODULE_ALIAS("snd-hda-codec-intelhdmi");
3945MODULE_ALIAS("snd-hda-codec-nvhdmi");
3946MODULE_ALIAS("snd-hda-codec-atihdmi");
3947
d8a766a1 3948static struct hda_codec_driver hdmi_driver = {
b9a94a9c 3949 .id = snd_hda_id_hdmi,
84eb01be
TI		 3950};
3951
d8a766a1 3952module_hda_codec_driver(hdmi_driver);
Ubuntu Jammy Linux kernel mirror