]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - sound/pci/hda/patch_hdmi.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: hda - Clean up async codec PM using standard async infrastructure
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
84eb01be
TI		 40#include "hda_codec.h"
41#include "hda_local.h"
1835a0f9 42#include "hda_jack.h"
84eb01be 43
0ebaa24c
TI		 44static bool static_hdmi_pcm;
45module_param(static_hdmi_pcm, bool, 0644);
46MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
47
fb87fa3a 48#define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
02383854 49#define is_valleyview(codec) ((codec)->vendor_id == 0x80862882)
fb87fa3a 50
384a48d7
SW		 51struct hdmi_spec_per_cvt {
52 hda_nid_t cvt_nid;
53 int assigned;
54 unsigned int channels_min;
55 unsigned int channels_max;
56 u32 rates;
57 u64 formats;
58 unsigned int maxbps;
59};
079d88cc 60
4eea3091
TI		 61/* max. connections to a widget */
62#define HDA_MAX_CONNECTIONS 32
63
384a48d7
SW		 64struct hdmi_spec_per_pin {
65 hda_nid_t pin_nid;
66 int num_mux_nids;
67 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
1df5a06a 68 hda_nid_t cvt_nid;
744626da
WF		 69
70 struct hda_codec *codec;
384a48d7 71 struct hdmi_eld sink_eld;
a4e9a38b 72 struct mutex lock;
744626da 73 struct delayed_work work;
92c69e79 74 struct snd_kcontrol *eld_ctl;
c6e8453e 75 int repoll_count;
b054087d
TI		 76 bool setup; /* the stream has been set up by prepare callback */
77 int channels; /* current number of channels */
1a6003b5 78 bool non_pcm;
d45e6889
TI		 79 bool chmap_set; /* channel-map override by ALSA API? */
80 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 81 char pcm_name[8]; /* filled in build_pcm callbacks */
a4e9a38b
TI		 82#ifdef CONFIG_PROC_FS
83 struct snd_info_entry *proc_entry;
84#endif
384a48d7 85};
079d88cc 86
307229d2
AH		 87struct cea_channel_speaker_allocation;
88
89/* operations used by generic code that can be overridden by patches */
90struct hdmi_ops {
91 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
92 unsigned char *buf, int *eld_size);
93
94 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
95 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
96 int asp_slot);
97 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
98 int asp_slot, int channel);
99
100 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
101 int ca, int active_channels, int conn_type);
102
103 /* enable/disable HBR (HD passthrough) */
104 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
105
106 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
107 hda_nid_t pin_nid, u32 stream_tag, int format);
108
109 /* Helpers for producing the channel map TLVs. These can be overridden
110 * for devices that have non-standard mapping requirements. */
111 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
112 int channels);
113 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
114 unsigned int *chmap, int channels);
115
116 /* check that the user-given chmap is supported */
117 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
118};
119
384a48d7
SW		 120struct hdmi_spec {
121 int num_cvts;
bce0d2a8
TI		 122 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
123 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 124
384a48d7 125 int num_pins;
bce0d2a8
TI		 126 struct snd_array pins; /* struct hdmi_spec_per_pin */
127 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 128 unsigned int channels_max; /* max over all cvts */
079d88cc 129
4bd038f9 130 struct hdmi_eld temp_eld;
307229d2 131 struct hdmi_ops ops;
079d88cc 132 /*
5a613584 133 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 134 */
135 struct hda_multi_out multiout;
d0b1252d 136 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 137};
138
139
140struct hdmi_audio_infoframe {
141 u8 type; /* 0x84 */
142 u8 ver; /* 0x01 */
143 u8 len; /* 0x0a */
144
53d7d69d
WF		 145 u8 checksum;
146
079d88cc
WF		 147 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
148 u8 SS01_SF24;
149 u8 CXT04;
150 u8 CA;
151 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 152};
153
154struct dp_audio_infoframe {
155 u8 type; /* 0x84 */
156 u8 len; /* 0x1b */
157 u8 ver; /* 0x11 << 2 */
158
159 u8 CC02_CT47; /* match with HDMI infoframe from this on */
160 u8 SS01_SF24;
161 u8 CXT04;
162 u8 CA;
163 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 164};
165
2b203dbb
TI		 166union audio_infoframe {
167 struct hdmi_audio_infoframe hdmi;
168 struct dp_audio_infoframe dp;
169 u8 bytes[0];
170};
171
079d88cc
WF		 172/*
173 * CEA speaker placement:
174 *
175 * FLH FCH FRH
176 * FLW FL FLC FC FRC FR FRW
177 *
178 * LFE
179 * TC
180 *
181 * RL RLC RC RRC RR
182 *
183 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
184 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
185 */
186enum cea_speaker_placement {
187 FL = (1 << 0), /* Front Left */
188 FC = (1 << 1), /* Front Center */
189 FR = (1 << 2), /* Front Right */
190 FLC = (1 << 3), /* Front Left Center */
191 FRC = (1 << 4), /* Front Right Center */
192 RL = (1 << 5), /* Rear Left */
193 RC = (1 << 6), /* Rear Center */
194 RR = (1 << 7), /* Rear Right */
195 RLC = (1 << 8), /* Rear Left Center */
196 RRC = (1 << 9), /* Rear Right Center */
197 LFE = (1 << 10), /* Low Frequency Effect */
198 FLW = (1 << 11), /* Front Left Wide */
199 FRW = (1 << 12), /* Front Right Wide */
200 FLH = (1 << 13), /* Front Left High */
201 FCH = (1 << 14), /* Front Center High */
202 FRH = (1 << 15), /* Front Right High */
203 TC = (1 << 16), /* Top Center */
204};
205
206/*
207 * ELD SA bits in the CEA Speaker Allocation data block
208 */
209static int eld_speaker_allocation_bits[] = {
210 [0] = FL | FR,
211 [1] = LFE,
212 [2] = FC,
213 [3] = RL | RR,
214 [4] = RC,
215 [5] = FLC | FRC,
216 [6] = RLC | RRC,
217 /* the following are not defined in ELD yet */
218 [7] = FLW | FRW,
219 [8] = FLH | FRH,
220 [9] = TC,
221 [10] = FCH,
222};
223
224struct cea_channel_speaker_allocation {
225 int ca_index;
226 int speakers[8];
227
228 /* derived values, just for convenience */
229 int channels;
230 int spk_mask;
231};
232
233/*
234 * ALSA sequence is:
235 *
236 * surround40 surround41 surround50 surround51 surround71
237 * ch0 front left = = = =
238 * ch1 front right = = = =
239 * ch2 rear left = = = =
240 * ch3 rear right = = = =
241 * ch4 LFE center center center
242 * ch5 LFE LFE
243 * ch6 side left
244 * ch7 side right
245 *
246 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
247 */
248static int hdmi_channel_mapping[0x32][8] = {
249 /* stereo */
250 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
251 /* 2.1 */
252 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
253 /* Dolby Surround */
254 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
255 /* surround40 */
256 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
257 /* 4ch */
258 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
259 /* surround41 */
9396d317 260 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 261 /* surround50 */
262 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
263 /* surround51 */
264 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
265 /* 7.1 */
266 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
267};
268
269/*
270 * This is an ordered list!
271 *
272 * The preceding ones have better chances to be selected by
53d7d69d 273 * hdmi_channel_allocation().
079d88cc
WF		 274 */
275static struct cea_channel_speaker_allocation channel_allocations[] = {
276/* channel: 7 6 5 4 3 2 1 0 */
277{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
278 /* 2.1 */
279{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
280 /* Dolby Surround */
281{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
282 /* surround40 */
283{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
284 /* surround41 */
285{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
286 /* surround50 */
287{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
288 /* surround51 */
289{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
290 /* 6.1 */
291{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
292 /* surround71 */
293{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
294
295{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
296{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
297{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
298{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
299{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
300{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
301{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
302{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
303{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
304{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
305{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
306{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
307{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
308{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
309{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
310{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
311{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
312{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
313{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
314{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
315{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
316{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
317{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
318{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
319{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
320{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
321{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
322{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
323{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
324{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
325{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
326{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
327{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
328{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
329{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
330{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
331{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
332{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
333{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
334{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
335{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
336};
337
338
339/*
340 * HDMI routines
341 */
342
bce0d2a8
TI		 343#define get_pin(spec, idx) \
344 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
345#define get_cvt(spec, idx) \
346 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
347#define get_pcm_rec(spec, idx) \
348 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
349
384a48d7 350static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 351{
384a48d7 352 int pin_idx;
079d88cc 353
384a48d7 354 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 355 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 356 return pin_idx;
079d88cc 357
384a48d7
SW		 358 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
359 return -EINVAL;
360}
361
362static int hinfo_to_pin_index(struct hdmi_spec *spec,
363 struct hda_pcm_stream *hinfo)
364{
365 int pin_idx;
366
367 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 368 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 369 return pin_idx;
370
371 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
372 return -EINVAL;
373}
374
375static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
376{
377 int cvt_idx;
378
379 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 380 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 381 return cvt_idx;
382
383 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 384 return -EINVAL;
385}
386
14bc52b8
PLB		 387static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
388 struct snd_ctl_elem_info *uinfo)
389{
390 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 391 struct hdmi_spec *spec = codec->spec;
a4e9a38b 392 struct hdmi_spec_per_pin *per_pin;
68e03de9 393 struct hdmi_eld *eld;
14bc52b8
PLB		 394 int pin_idx;
395
14bc52b8
PLB		 396 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
397
398 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 399 per_pin = get_pin(spec, pin_idx);
400 eld = &per_pin->sink_eld;
68e03de9 401
a4e9a38b 402 mutex_lock(&per_pin->lock);
68e03de9 403 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
a4e9a38b 404 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 405
406 return 0;
407}
408
409static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
410 struct snd_ctl_elem_value *ucontrol)
411{
412 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 413 struct hdmi_spec *spec = codec->spec;
a4e9a38b 414 struct hdmi_spec_per_pin *per_pin;
68e03de9 415 struct hdmi_eld *eld;
14bc52b8
PLB		 416 int pin_idx;
417
14bc52b8 418 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 419 per_pin = get_pin(spec, pin_idx);
420 eld = &per_pin->sink_eld;
68e03de9 421
a4e9a38b 422 mutex_lock(&per_pin->lock);
68e03de9 423 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
a4e9a38b 424 mutex_unlock(&per_pin->lock);
68e03de9
DH		 425 snd_BUG();
426 return -EINVAL;
427 }
428
429 memset(ucontrol->value.bytes.data, 0,
430 ARRAY_SIZE(ucontrol->value.bytes.data));
431 if (eld->eld_valid)
432 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
433 eld->eld_size);
a4e9a38b 434 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 435
436 return 0;
437}
438
439static struct snd_kcontrol_new eld_bytes_ctl = {
440 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
441 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
442 .name = "ELD",
443 .info = hdmi_eld_ctl_info,
444 .get = hdmi_eld_ctl_get,
445};
446
447static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
448 int device)
449{
450 struct snd_kcontrol *kctl;
451 struct hdmi_spec *spec = codec->spec;
452 int err;
453
454 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
455 if (!kctl)
456 return -ENOMEM;
457 kctl->private_value = pin_idx;
458 kctl->id.device = device;
459
bce0d2a8 460 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 461 if (err < 0)
462 return err;
463
bce0d2a8 464 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 465 return 0;
466}
467
079d88cc
WF		 468#ifdef BE_PARANOID
469static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
470 int *packet_index, int *byte_index)
471{
472 int val;
473
474 val = snd_hda_codec_read(codec, pin_nid, 0,
475 AC_VERB_GET_HDMI_DIP_INDEX, 0);
476
477 *packet_index = val >> 5;
478 *byte_index = val & 0x1f;
479}
480#endif
481
482static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
483 int packet_index, int byte_index)
484{
485 int val;
486
487 val = (packet_index << 5) | (byte_index & 0x1f);
488
489 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
490}
491
492static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
493 unsigned char val)
494{
495 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
496}
497
384a48d7 498static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 499{
500 /* Unmute */
501 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
502 snd_hda_codec_write(codec, pin_nid, 0,
503 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 504 /* Enable pin out: some machines with GM965 gets broken output when
505 * the pin is disabled or changed while using with HDMI
506 */
079d88cc 507 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 508 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 509}
510
384a48d7 511static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 512{
384a48d7 513 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 514 AC_VERB_GET_CVT_CHAN_COUNT, 0);
515}
516
517static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 518 hda_nid_t cvt_nid, int chs)
079d88cc 519{
384a48d7
SW		 520 if (chs != hdmi_get_channel_count(codec, cvt_nid))
521 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 522 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
523}
524
a4e9a38b
TI		 525/*
526 * ELD proc files
527 */
528
529#ifdef CONFIG_PROC_FS
530static void print_eld_info(struct snd_info_entry *entry,
531 struct snd_info_buffer *buffer)
532{
533 struct hdmi_spec_per_pin *per_pin = entry->private_data;
534
535 mutex_lock(&per_pin->lock);
536 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
537 mutex_unlock(&per_pin->lock);
538}
539
540static void write_eld_info(struct snd_info_entry *entry,
541 struct snd_info_buffer *buffer)
542{
543 struct hdmi_spec_per_pin *per_pin = entry->private_data;
544
545 mutex_lock(&per_pin->lock);
546 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
547 mutex_unlock(&per_pin->lock);
548}
549
550static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
551{
552 char name[32];
553 struct hda_codec *codec = per_pin->codec;
554 struct snd_info_entry *entry;
555 int err;
556
557 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
558 err = snd_card_proc_new(codec->bus->card, name, &entry);
559 if (err < 0)
560 return err;
561
562 snd_info_set_text_ops(entry, per_pin, print_eld_info);
563 entry->c.text.write = write_eld_info;
564 entry->mode |= S_IWUSR;
565 per_pin->proc_entry = entry;
566
567 return 0;
568}
569
570static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
571{
572 if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) {
573 snd_device_free(per_pin->codec->bus->card, per_pin->proc_entry);
574 per_pin->proc_entry = NULL;
575 }
576}
577#else
b55447a7
TI		 578static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
579 int index)
a4e9a38b
TI		 580{
581 return 0;
582}
b55447a7 583static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 584{
585}
586#endif
079d88cc
WF		 587
588/*
589 * Channel mapping routines
590 */
591
592/*
593 * Compute derived values in channel_allocations[].
594 */
595static void init_channel_allocations(void)
596{
597 int i, j;
598 struct cea_channel_speaker_allocation *p;
599
600 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
601 p = channel_allocations + i;
602 p->channels = 0;
603 p->spk_mask = 0;
604 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
605 if (p->speakers[j]) {
606 p->channels++;
607 p->spk_mask |= p->speakers[j];
608 }
609 }
610}
611
72357c78
WX		 612static int get_channel_allocation_order(int ca)
613{
614 int i;
615
616 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
617 if (channel_allocations[i].ca_index == ca)
618 break;
619 }
620 return i;
621}
622
079d88cc
WF		 623/*
624 * The transformation takes two steps:
625 *
626 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
627 * spk_mask => (channel_allocations[]) => ai->CA
628 *
629 * TODO: it could select the wrong CA from multiple candidates.
630*/
384a48d7 631static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 632{
079d88cc 633 int i;
53d7d69d 634 int ca = 0;
079d88cc 635 int spk_mask = 0;
079d88cc
WF		 636 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
637
638 /*
639 * CA defaults to 0 for basic stereo audio
640 */
641 if (channels <= 2)
642 return 0;
643
079d88cc
WF		 644 /*
645 * expand ELD's speaker allocation mask
646 *
647 * ELD tells the speaker mask in a compact(paired) form,
648 * expand ELD's notions to match the ones used by Audio InfoFrame.
649 */
650 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 651 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 652 spk_mask |= eld_speaker_allocation_bits[i];
653 }
654
655 /* search for the first working match in the CA table */
656 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
657 if (channels == channel_allocations[i].channels &&
658 (spk_mask & channel_allocations[i].spk_mask) ==
659 channel_allocations[i].spk_mask) {
53d7d69d 660 ca = channel_allocations[i].ca_index;
079d88cc
WF		 661 break;
662 }
663 }
664
18e39186
AH		 665 if (!ca) {
666 /* if there was no match, select the regular ALSA channel
667 * allocation with the matching number of channels */
668 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
669 if (channels == channel_allocations[i].channels) {
670 ca = channel_allocations[i].ca_index;
671 break;
672 }
673 }
674 }
675
1613d6b4 676 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 677 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 678 ca, channels, buf);
079d88cc 679
53d7d69d 680 return ca;
079d88cc
WF		 681}
682
683static void hdmi_debug_channel_mapping(struct hda_codec *codec,
684 hda_nid_t pin_nid)
685{
686#ifdef CONFIG_SND_DEBUG_VERBOSE
307229d2 687 struct hdmi_spec *spec = codec->spec;
079d88cc 688 int i;
307229d2 689 int channel;
079d88cc
WF		 690
691 for (i = 0; i < 8; i++) {
307229d2 692 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
079d88cc 693 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
307229d2 694 channel, i);
079d88cc
WF		 695 }
696#endif
697}
698
d45e6889 699static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 700 hda_nid_t pin_nid,
433968da 701 bool non_pcm,
53d7d69d 702 int ca)
079d88cc 703{
307229d2 704 struct hdmi_spec *spec = codec->spec;
90f28002 705 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 706 int i;
079d88cc 707 int err;
72357c78 708 int order;
433968da 709 int non_pcm_mapping[8];
079d88cc 710
72357c78 711 order = get_channel_allocation_order(ca);
90f28002 712 ch_alloc = &channel_allocations[order];
433968da 713
079d88cc 714 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 715 int hdmi_slot = 0;
716 /* fill actual channel mappings in ALSA channel (i) order */
717 for (i = 0; i < ch_alloc->channels; i++) {
718 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
719 hdmi_slot++; /* skip zero slots */
720
721 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
722 }
723 /* fill the rest of the slots with ALSA channel 0xf */
724 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
725 if (!ch_alloc->speakers[7 - hdmi_slot])
726 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 727 }
728
433968da 729 if (non_pcm) {
90f28002 730 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 731 non_pcm_mapping[i] = (i << 4) | i;
433968da 732 for (; i < 8; i++)
11f7c52d 733 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 734 }
735
079d88cc 736 for (i = 0; i < 8; i++) {
307229d2
AH		 737 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
738 int hdmi_slot = slotsetup & 0x0f;
739 int channel = (slotsetup & 0xf0) >> 4;
740 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
079d88cc 741 if (err) {
2abbf439
WF		 742 snd_printdd(KERN_NOTICE
743 "HDMI: channel mapping failed\n");
079d88cc
WF		 744 break;
745 }
746 }
079d88cc
WF		 747}
748
d45e6889
TI		 749struct channel_map_table {
750 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 751 int spk_mask; /* speaker position bit mask */
752};
753
754static struct channel_map_table map_tables[] = {
a5b7d510
AH		 755 { SNDRV_CHMAP_FL, FL },
756 { SNDRV_CHMAP_FR, FR },
757 { SNDRV_CHMAP_RL, RL },
758 { SNDRV_CHMAP_RR, RR },
759 { SNDRV_CHMAP_LFE, LFE },
760 { SNDRV_CHMAP_FC, FC },
761 { SNDRV_CHMAP_RLC, RLC },
762 { SNDRV_CHMAP_RRC, RRC },
763 { SNDRV_CHMAP_RC, RC },
764 { SNDRV_CHMAP_FLC, FLC },
765 { SNDRV_CHMAP_FRC, FRC },
94908a39
AH		 766 { SNDRV_CHMAP_TFL, FLH },
767 { SNDRV_CHMAP_TFR, FRH },
a5b7d510
AH		 768 { SNDRV_CHMAP_FLW, FLW },
769 { SNDRV_CHMAP_FRW, FRW },
770 { SNDRV_CHMAP_TC, TC },
94908a39 771 { SNDRV_CHMAP_TFC, FCH },
d45e6889
TI		 772 {} /* terminator */
773};
774
775/* from ALSA API channel position to speaker bit mask */
776static int to_spk_mask(unsigned char c)
777{
778 struct channel_map_table *t = map_tables;
779 for (; t->map; t++) {
780 if (t->map == c)
781 return t->spk_mask;
782 }
783 return 0;
784}
785
786/* from ALSA API channel position to CEA slot */
a5b7d510 787static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 788{
a5b7d510
AH		 789 int mask = to_spk_mask(pos);
790 int i;
d45e6889 791
a5b7d510
AH		 792 if (mask) {
793 for (i = 0; i < 8; i++) {
794 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
795 return i;
796 }
d45e6889 797 }
a5b7d510
AH		 798
799 return -1;
d45e6889
TI		 800}
801
802/* from speaker bit mask to ALSA API channel position */
803static int spk_to_chmap(int spk)
804{
805 struct channel_map_table *t = map_tables;
806 for (; t->map; t++) {
807 if (t->spk_mask == spk)
808 return t->map;
809 }
810 return 0;
811}
812
a5b7d510
AH		 813/* from CEA slot to ALSA API channel position */
814static int from_cea_slot(int ordered_ca, unsigned char slot)
815{
816 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
817
818 return spk_to_chmap(mask);
819}
820
d45e6889
TI		 821/* get the CA index corresponding to the given ALSA API channel map */
822static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
823{
824 int i, spks = 0, spk_mask = 0;
825
826 for (i = 0; i < chs; i++) {
827 int mask = to_spk_mask(map[i]);
828 if (mask) {
829 spk_mask |= mask;
830 spks++;
831 }
832 }
833
834 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
835 if ((chs == channel_allocations[i].channels ||
836 spks == channel_allocations[i].channels) &&
837 (spk_mask & channel_allocations[i].spk_mask) ==
838 channel_allocations[i].spk_mask)
839 return channel_allocations[i].ca_index;
840 }
841 return -1;
842}
843
844/* set up the channel slots for the given ALSA API channel map */
845static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
846 hda_nid_t pin_nid,
a5b7d510
AH		 847 int chs, unsigned char *map,
848 int ca)
d45e6889 849{
307229d2 850 struct hdmi_spec *spec = codec->spec;
a5b7d510 851 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 852 int alsa_pos, hdmi_slot;
853 int assignments[8] = {[0 ... 7] = 0xf};
854
855 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
856
a5b7d510 857 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 858
859 if (hdmi_slot < 0)
860 continue; /* unassigned channel */
861
862 assignments[hdmi_slot] = alsa_pos;
863 }
864
865 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
307229d2 866 int err;
11f7c52d 867
307229d2
AH		 868 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
869 assignments[hdmi_slot]);
d45e6889
TI		 870 if (err)
871 return -EINVAL;
872 }
873 return 0;
874}
875
876/* store ALSA API channel map from the current default map */
877static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
878{
879 int i;
56cac413 880 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 881 for (i = 0; i < 8; i++) {
56cac413 882 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 883 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 884 else
885 map[i] = 0;
886 }
887}
888
889static void hdmi_setup_channel_mapping(struct hda_codec *codec,
890 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 891 int channels, unsigned char *map,
892 bool chmap_set)
d45e6889 893{
20608731 894 if (!non_pcm && chmap_set) {
d45e6889 895 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 896 channels, map, ca);
d45e6889
TI		 897 } else {
898 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
899 hdmi_setup_fake_chmap(map, ca);
900 }
980b2495
AH		 901
902 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 903}
079d88cc 904
307229d2
AH		 905static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
906 int asp_slot, int channel)
907{
908 return snd_hda_codec_write(codec, pin_nid, 0,
909 AC_VERB_SET_HDMI_CHAN_SLOT,
910 (channel << 4) | asp_slot);
911}
912
913static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
914 int asp_slot)
915{
916 return (snd_hda_codec_read(codec, pin_nid, 0,
917 AC_VERB_GET_HDMI_CHAN_SLOT,
918 asp_slot) & 0xf0) >> 4;
919}
920
079d88cc
WF		 921/*
922 * Audio InfoFrame routines
923 */
924
925/*
926 * Enable Audio InfoFrame Transmission
927 */
928static void hdmi_start_infoframe_trans(struct hda_codec *codec,
929 hda_nid_t pin_nid)
930{
931 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
932 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
933 AC_DIPXMIT_BEST);
934}
935
936/*
937 * Disable Audio InfoFrame Transmission
938 */
939static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
940 hda_nid_t pin_nid)
941{
942 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
943 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
944 AC_DIPXMIT_DISABLE);
945}
946
947static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
948{
949#ifdef CONFIG_SND_DEBUG_VERBOSE
950 int i;
951 int size;
952
953 size = snd_hdmi_get_eld_size(codec, pin_nid);
954 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
955
956 for (i = 0; i < 8; i++) {
957 size = snd_hda_codec_read(codec, pin_nid, 0,
958 AC_VERB_GET_HDMI_DIP_SIZE, i);
959 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
960 }
961#endif
962}
963
964static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
965{
966#ifdef BE_PARANOID
967 int i, j;
968 int size;
969 int pi, bi;
970 for (i = 0; i < 8; i++) {
971 size = snd_hda_codec_read(codec, pin_nid, 0,
972 AC_VERB_GET_HDMI_DIP_SIZE, i);
973 if (size == 0)
974 continue;
975
976 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
977 for (j = 1; j < 1000; j++) {
978 hdmi_write_dip_byte(codec, pin_nid, 0x0);
979 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
980 if (pi != i)
981 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
982 bi, pi, i);
983 if (bi == 0) /* byte index wrapped around */
984 break;
985 }
986 snd_printd(KERN_INFO
987 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
988 i, size, j);
989 }
990#endif
991}
992
53d7d69d 993static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 994{
53d7d69d 995 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 996 u8 sum = 0;
997 int i;
998
53d7d69d 999 hdmi_ai->checksum = 0;
079d88cc 1000
53d7d69d 1001 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 1002 sum += bytes[i];
1003
53d7d69d 1004 hdmi_ai->checksum = -sum;
079d88cc
WF		 1005}
1006
1007static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1008 hda_nid_t pin_nid,
53d7d69d 1009 u8 *dip, int size)
079d88cc 1010{
079d88cc
WF		 1011 int i;
1012
1013 hdmi_debug_dip_size(codec, pin_nid);
1014 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1015
079d88cc 1016 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 1017 for (i = 0; i < size; i++)
1018 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 1019}
1020
1021static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 1022 u8 *dip, int size)
079d88cc 1023{
079d88cc
WF		 1024 u8 val;
1025 int i;
1026
1027 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1028 != AC_DIPXMIT_BEST)
1029 return false;
1030
1031 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 1032 for (i = 0; i < size; i++) {
079d88cc
WF		 1033 val = snd_hda_codec_read(codec, pin_nid, 0,
1034 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 1035 if (val != dip[i])
079d88cc
WF		 1036 return false;
1037 }
1038
1039 return true;
1040}
1041
307229d2
AH		 1042static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1043 hda_nid_t pin_nid,
1044 int ca, int active_channels,
1045 int conn_type)
1046{
1047 union audio_infoframe ai;
1048
1049 if (conn_type == 0) { /* HDMI */
1050 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1051
1052 hdmi_ai->type = 0x84;
1053 hdmi_ai->ver = 0x01;
1054 hdmi_ai->len = 0x0a;
1055 hdmi_ai->CC02_CT47 = active_channels - 1;
1056 hdmi_ai->CA = ca;
1057 hdmi_checksum_audio_infoframe(hdmi_ai);
1058 } else if (conn_type == 1) { /* DisplayPort */
1059 struct dp_audio_infoframe *dp_ai = &ai.dp;
1060
1061 dp_ai->type = 0x84;
1062 dp_ai->len = 0x1b;
1063 dp_ai->ver = 0x11 << 2;
1064 dp_ai->CC02_CT47 = active_channels - 1;
1065 dp_ai->CA = ca;
1066 } else {
1067 snd_printd("HDMI: unknown connection type at pin %d\n",
1068 pin_nid);
1069 return;
1070 }
1071
1072 /*
1073 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1074 * sizeof(*dp_ai) to avoid partial match/update problems when
1075 * the user switches between HDMI/DP monitors.
1076 */
1077 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1078 sizeof(ai))) {
1079 snd_printdd("hdmi_pin_setup_infoframe: "
1080 "pin=%d channels=%d ca=0x%02x\n",
1081 pin_nid,
1082 active_channels, ca);
1083 hdmi_stop_infoframe_trans(codec, pin_nid);
1084 hdmi_fill_audio_infoframe(codec, pin_nid,
1085 ai.bytes, sizeof(ai));
1086 hdmi_start_infoframe_trans(codec, pin_nid);
1087 }
1088}
1089
b054087d
TI		 1090static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1091 struct hdmi_spec_per_pin *per_pin,
1092 bool non_pcm)
079d88cc 1093{
307229d2 1094 struct hdmi_spec *spec = codec->spec;
384a48d7 1095 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 1096 int channels = per_pin->channels;
1df5a06a 1097 int active_channels;
384a48d7 1098 struct hdmi_eld *eld;
1df5a06a 1099 int ca, ordered_ca;
079d88cc 1100
b054087d
TI		 1101 if (!channels)
1102 return;
1103
58f7d28d
ML		 1104 if (is_haswell(codec))
1105 snd_hda_codec_write(codec, pin_nid, 0,
1106 AC_VERB_SET_AMP_GAIN_MUTE,
1107 AMP_OUT_UNMUTE);
1108
bce0d2a8 1109 eld = &per_pin->sink_eld;
384a48d7
SW		 1110 if (!eld->monitor_present)
1111 return;
079d88cc 1112
d45e6889
TI		 1113 if (!non_pcm && per_pin->chmap_set)
1114 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1115 else
1116 ca = hdmi_channel_allocation(eld, channels);
1117 if (ca < 0)
1118 ca = 0;
384a48d7 1119
1df5a06a
AH		 1120 ordered_ca = get_channel_allocation_order(ca);
1121 active_channels = channel_allocations[ordered_ca].channels;
1122
1123 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1124
39edac70
AH		 1125 /*
1126 * always configure channel mapping, it may have been changed by the
1127 * user in the meantime
1128 */
1129 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1130 channels, per_pin->chmap,
1131 per_pin->chmap_set);
1132
307229d2
AH		 1133 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1134 eld->info.conn_type);
433968da 1135
1a6003b5 1136 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1137}
1138
079d88cc
WF		 1139/*
1140 * Unsolicited events
1141 */
1142
efe47108 1143static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1144
079d88cc
WF		 1145static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1146{
1147 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 1148 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1149 int pin_nid;
384a48d7 1150 int pin_idx;
3a93897e 1151 struct hda_jack_tbl *jack;
2e59e5ab 1152 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1153
1154 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1155 if (!jack)
1156 return;
1157 pin_nid = jack->nid;
1158 jack->jack_dirty = 1;
079d88cc 1159
fae3d88a 1160 _snd_printd(SND_PR_VERBOSE,
2e59e5ab
ML		 1161 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1162 codec->addr, pin_nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1163 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1164
384a48d7
SW		 1165 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
1166 if (pin_idx < 0)
079d88cc
WF		 1167 return;
1168
efe47108
TI		 1169 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1170 snd_hda_jack_report_sync(codec);
079d88cc
WF		 1171}
1172
1173static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1174{
1175 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1176 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1177 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1178 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1179
1180 printk(KERN_INFO
e9ea8e8f 1181 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1182 codec->addr,
079d88cc
WF		 1183 tag,
1184 subtag,
1185 cp_state,
1186 cp_ready);
1187
1188 /* TODO */
1189 if (cp_state)
1190 ;
1191 if (cp_ready)
1192 ;
1193}
1194
1195
1196static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1197{
079d88cc
WF		 1198 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1199 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1200
3a93897e 1201 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 1202 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
1203 return;
1204 }
1205
1206 if (subtag == 0)
1207 hdmi_intrinsic_event(codec, res);
1208 else
1209 hdmi_non_intrinsic_event(codec, res);
1210}
1211
58f7d28d 1212static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1213 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1214{
58f7d28d 1215 int pwr;
83f26ad2 1216
53b434f0
WX		 1217 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1218 * thus pins could only choose converter 0 for use. Make sure the
1219 * converters are in correct power state */
fd678cac 1220 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1221 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1222
fd678cac 1223 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1224 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1225 AC_PWRST_D0);
1226 msleep(40);
1227 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1228 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1229 snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1230 }
83f26ad2
DH		 1231}
1232
079d88cc
WF		 1233/*
1234 * Callbacks
1235 */
1236
92f10b3f
TI		 1237/* HBR should be Non-PCM, 8 channels */
1238#define is_hbr_format(format) \
1239 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1240
307229d2
AH		 1241static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1242 bool hbr)
079d88cc 1243{
307229d2 1244 int pinctl, new_pinctl;
83f26ad2 1245
384a48d7
SW		 1246 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1247 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1248 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1249
13122e6e
AH		 1250 if (pinctl < 0)
1251 return hbr ? -EINVAL : 0;
1252
ea87d1c4 1253 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 1254 if (hbr)
ea87d1c4
AH		 1255 new_pinctl |= AC_PINCTL_EPT_HBR;
1256 else
1257 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1258
307229d2 1259 snd_printdd("hdmi_pin_hbr_setup: "
ea87d1c4 1260 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1261 pin_nid,
ea87d1c4
AH		 1262 pinctl == new_pinctl ? "" : "new-",
1263 new_pinctl);
1264
1265 if (pinctl != new_pinctl)
384a48d7 1266 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1267 AC_VERB_SET_PIN_WIDGET_CONTROL,
1268 new_pinctl);
307229d2
AH		 1269 } else if (hbr)
1270 return -EINVAL;
ea87d1c4 1271
307229d2
AH		 1272 return 0;
1273}
1274
1275static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1276 hda_nid_t pin_nid, u32 stream_tag, int format)
1277{
1278 struct hdmi_spec *spec = codec->spec;
1279 int err;
1280
1281 if (is_haswell(codec))
1282 haswell_verify_D0(codec, cvt_nid, pin_nid);
1283
1284 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1285
1286 if (err) {
ea87d1c4 1287 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
307229d2 1288 return err;
ea87d1c4 1289 }
079d88cc 1290
384a48d7 1291 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1292 return 0;
079d88cc
WF		 1293}
1294
7ef166b8
WX		 1295static int hdmi_choose_cvt(struct hda_codec *codec,
1296 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1297{
1298 struct hdmi_spec *spec = codec->spec;
384a48d7 1299 struct hdmi_spec_per_pin *per_pin;
384a48d7 1300 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1301 int cvt_idx, mux_idx = 0;
bbbe3390 1302
bce0d2a8 1303 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1304
1305 /* Dynamically assign converter to stream */
1306 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1307 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1308
384a48d7
SW		 1309 /* Must not already be assigned */
1310 if (per_cvt->assigned)
1311 continue;
1312 /* Must be in pin's mux's list of converters */
1313 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1314 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1315 break;
1316 /* Not in mux list */
1317 if (mux_idx == per_pin->num_mux_nids)
1318 continue;
1319 break;
1320 }
7ef166b8 1321
384a48d7
SW		 1322 /* No free converters */
1323 if (cvt_idx == spec->num_cvts)
1324 return -ENODEV;
1325
7ef166b8
WX		 1326 if (cvt_id)
1327 *cvt_id = cvt_idx;
1328 if (mux_id)
1329 *mux_id = mux_idx;
1330
1331 return 0;
1332}
1333
300016b9
ML		 1334/* Intel HDMI workaround to fix audio routing issue:
1335 * For some Intel display codecs, pins share the same connection list.
1336 * So a conveter can be selected by multiple pins and playback on any of these
1337 * pins will generate sound on the external display, because audio flows from
1338 * the same converter to the display pipeline. Also muting one pin may make
1339 * other pins have no sound output.
1340 * So this function assures that an assigned converter for a pin is not selected
1341 * by any other pins.
1342 */
1343static void intel_not_share_assigned_cvt(struct hda_codec *codec,
f82d7d16 1344 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1345{
1346 struct hdmi_spec *spec = codec->spec;
f82d7d16
ML		 1347 hda_nid_t nid, end_nid;
1348 int cvt_idx, curr;
1349 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1350
f82d7d16
ML		 1351 /* configure all pins, including "no physical connection" ones */
1352 end_nid = codec->start_nid + codec->num_nodes;
1353 for (nid = codec->start_nid; nid < end_nid; nid++) {
1354 unsigned int wid_caps = get_wcaps(codec, nid);
1355 unsigned int wid_type = get_wcaps_type(wid_caps);
1356
1357 if (wid_type != AC_WID_PIN)
1358 continue;
7ef166b8 1359
f82d7d16 1360 if (nid == pin_nid)
7ef166b8
WX		 1361 continue;
1362
f82d7d16 1363 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1364 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1365 if (curr != mux_idx)
1366 continue;
7ef166b8 1367
f82d7d16
ML		 1368 /* choose an unassigned converter. The conveters in the
1369 * connection list are in the same order as in the codec.
1370 */
1371 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1372 per_cvt = get_cvt(spec, cvt_idx);
1373 if (!per_cvt->assigned) {
1374 snd_printdd("choose cvt %d for pin nid %d\n",
1375 cvt_idx, nid);
1376 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1377 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1378 cvt_idx);
1379 break;
1380 }
7ef166b8
WX		 1381 }
1382 }
1383}
1384
1385/*
1386 * HDA PCM callbacks
1387 */
1388static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1389 struct hda_codec *codec,
1390 struct snd_pcm_substream *substream)
1391{
1392 struct hdmi_spec *spec = codec->spec;
1393 struct snd_pcm_runtime *runtime = substream->runtime;
1394 int pin_idx, cvt_idx, mux_idx = 0;
1395 struct hdmi_spec_per_pin *per_pin;
1396 struct hdmi_eld *eld;
1397 struct hdmi_spec_per_cvt *per_cvt = NULL;
1398 int err;
1399
1400 /* Validate hinfo */
1401 pin_idx = hinfo_to_pin_index(spec, hinfo);
1402 if (snd_BUG_ON(pin_idx < 0))
1403 return -EINVAL;
1404 per_pin = get_pin(spec, pin_idx);
1405 eld = &per_pin->sink_eld;
1406
1407 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1408 if (err < 0)
1409 return err;
1410
1411 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1412 /* Claim converter */
1413 per_cvt->assigned = 1;
1df5a06a 1414 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1415 hinfo->nid = per_cvt->cvt_nid;
1416
bddee96b 1417 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1418 AC_VERB_SET_CONNECT_SEL,
1419 mux_idx);
7ef166b8
WX		 1420
1421 /* configure unused pins to choose other converters */
02383854 1422 if (is_haswell(codec) || is_valleyview(codec))
300016b9 1423 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1424
384a48d7 1425 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1426
2def8172 1427 /* Initially set the converter's capabilities */
384a48d7
SW		 1428 hinfo->channels_min = per_cvt->channels_min;
1429 hinfo->channels_max = per_cvt->channels_max;
1430 hinfo->rates = per_cvt->rates;
1431 hinfo->formats = per_cvt->formats;
1432 hinfo->maxbps = per_cvt->maxbps;
2def8172 1433
384a48d7 1434 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1435 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1436 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1437 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1438 !hinfo->rates || !hinfo->formats) {
1439 per_cvt->assigned = 0;
1440 hinfo->nid = 0;
1441 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1442 return -ENODEV;
2ad779b7 1443 }
bbbe3390 1444 }
2def8172
SW		 1445
1446 /* Store the updated parameters */
639cef0e
TI		 1447 runtime->hw.channels_min = hinfo->channels_min;
1448 runtime->hw.channels_max = hinfo->channels_max;
1449 runtime->hw.formats = hinfo->formats;
1450 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1451
1452 snd_pcm_hw_constraint_step(substream->runtime, 0,
1453 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1454 return 0;
1455}
1456
079d88cc
WF		 1457/*
1458 * HDA/HDMI auto parsing
1459 */
384a48d7 1460static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1461{
1462 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1463 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1464 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1465
1466 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1467 snd_printk(KERN_WARNING
1468 "HDMI: pin %d wcaps %#x "
1469 "does not support connection list\n",
1470 pin_nid, get_wcaps(codec, pin_nid));
1471 return -EINVAL;
1472 }
1473
384a48d7
SW		 1474 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1475 per_pin->mux_nids,
1476 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1477
1478 return 0;
1479}
1480
efe47108 1481static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1482{
464837a7 1483 struct hda_jack_tbl *jack;
744626da 1484 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1485 struct hdmi_spec *spec = codec->spec;
1486 struct hdmi_eld *eld = &spec->temp_eld;
1487 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1488 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1489 /*
1490 * Always execute a GetPinSense verb here, even when called from
1491 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1492 * response's PD bit is not the real PD value, but indicates that
1493 * the real PD value changed. An older version of the HD-audio
1494 * specification worked this way. Hence, we just ignore the data in
1495 * the unsolicited response to avoid custom WARs.
1496 */
079d88cc 1497 int present = snd_hda_pin_sense(codec, pin_nid);
4bd038f9
DH		 1498 bool update_eld = false;
1499 bool eld_changed = false;
efe47108 1500 bool ret;
079d88cc 1501
a4e9a38b 1502 mutex_lock(&per_pin->lock);
4bd038f9
DH		 1503 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1504 if (pin_eld->monitor_present)
1505 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1506 else
1507 eld->eld_valid = false;
079d88cc 1508
fae3d88a 1509 _snd_printd(SND_PR_VERBOSE,
384a48d7 1510 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1511 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1512
4bd038f9 1513 if (eld->eld_valid) {
307229d2 1514 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1515 &eld->eld_size) < 0)
4bd038f9 1516 eld->eld_valid = false;
1613d6b4
DH		 1517 else {
1518 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1519 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1520 eld->eld_size) < 0)
4bd038f9 1521 eld->eld_valid = false;
1613d6b4
DH		 1522 }
1523
4bd038f9 1524 if (eld->eld_valid) {
1613d6b4 1525 snd_hdmi_show_eld(&eld->info);
4bd038f9 1526 update_eld = true;
1613d6b4 1527 }
c6e8453e 1528 else if (repoll) {
744626da
WF		 1529 queue_delayed_work(codec->bus->workq,
1530 &per_pin->work,
1531 msecs_to_jiffies(300));
cbbaa603 1532 goto unlock;
744626da
WF		 1533 }
1534 }
4bd038f9 1535
92c69e79 1536 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1537 update_eld = true;
92c69e79
DH		 1538 eld_changed = true;
1539 }
4bd038f9 1540 if (update_eld) {
b054087d 1541 bool old_eld_valid = pin_eld->eld_valid;
4bd038f9 1542 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1543 eld_changed = pin_eld->eld_size != eld->eld_size ||
1544 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1545 eld->eld_size) != 0;
1546 if (eld_changed)
1547 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1548 eld->eld_size);
1549 pin_eld->eld_size = eld->eld_size;
1550 pin_eld->info = eld->info;
b054087d 1551
7342017f
AH		 1552 /*
1553 * Re-setup pin and infoframe. This is needed e.g. when
1554 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1555 * - transcoder can change during stream playback on Haswell
b054087d 1556 */
7342017f 1557 if (eld->eld_valid && !old_eld_valid && per_pin->setup)
b054087d
TI		 1558 hdmi_setup_audio_infoframe(codec, per_pin,
1559 per_pin->non_pcm);
4bd038f9 1560 }
92c69e79
DH		 1561
1562 if (eld_changed)
1563 snd_ctl_notify(codec->bus->card,
1564 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1565 &per_pin->eld_ctl->id);
cbbaa603 1566 unlock:
aff747eb 1567 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
464837a7
DH		 1568
1569 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1570 if (jack)
1571 jack->block_report = !ret;
1572
a4e9a38b 1573 mutex_unlock(&per_pin->lock);
efe47108 1574 return ret;
079d88cc
WF		 1575}
1576
744626da
WF		 1577static void hdmi_repoll_eld(struct work_struct *work)
1578{
1579 struct hdmi_spec_per_pin *per_pin =
1580 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1581
c6e8453e
WF		 1582 if (per_pin->repoll_count++ > 6)
1583 per_pin->repoll_count = 0;
1584
efe47108
TI		 1585 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1586 snd_hda_jack_report_sync(per_pin->codec);
744626da
WF		 1587}
1588
c88d4e84
TI		 1589static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1590 hda_nid_t nid);
1591
079d88cc
WF		 1592static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1593{
1594 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1595 unsigned int caps, config;
1596 int pin_idx;
1597 struct hdmi_spec_per_pin *per_pin;
07acecc1 1598 int err;
079d88cc 1599
efc2f8de 1600 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1601 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1602 return 0;
1603
efc2f8de 1604 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1605 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1606 return 0;
1607
fb87fa3a 1608 if (is_haswell(codec))
c88d4e84
TI		 1609 intel_haswell_fixup_connect_list(codec, pin_nid);
1610
384a48d7 1611 pin_idx = spec->num_pins;
bce0d2a8
TI		 1612 per_pin = snd_array_new(&spec->pins);
1613 if (!per_pin)
1614 return -ENOMEM;
384a48d7
SW		 1615
1616 per_pin->pin_nid = pin_nid;
1a6003b5 1617 per_pin->non_pcm = false;
079d88cc 1618
384a48d7
SW		 1619 err = hdmi_read_pin_conn(codec, pin_idx);
1620 if (err < 0)
1621 return err;
079d88cc 1622
079d88cc
WF		 1623 spec->num_pins++;
1624
384a48d7 1625 return 0;
079d88cc
WF		 1626}
1627
384a48d7 1628static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1629{
1630 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1631 struct hdmi_spec_per_cvt *per_cvt;
1632 unsigned int chans;
1633 int err;
079d88cc 1634
384a48d7
SW		 1635 chans = get_wcaps(codec, cvt_nid);
1636 chans = get_wcaps_channels(chans);
1637
bce0d2a8
TI		 1638 per_cvt = snd_array_new(&spec->cvts);
1639 if (!per_cvt)
1640 return -ENOMEM;
384a48d7
SW		 1641
1642 per_cvt->cvt_nid = cvt_nid;
1643 per_cvt->channels_min = 2;
d45e6889 1644 if (chans <= 16) {
384a48d7 1645 per_cvt->channels_max = chans;
d45e6889
TI		 1646 if (chans > spec->channels_max)
1647 spec->channels_max = chans;
1648 }
384a48d7
SW		 1649
1650 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1651 &per_cvt->rates,
1652 &per_cvt->formats,
1653 &per_cvt->maxbps);
1654 if (err < 0)
1655 return err;
1656
bce0d2a8
TI		 1657 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1658 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1659 spec->num_cvts++;
079d88cc
WF		 1660
1661 return 0;
1662}
1663
1664static int hdmi_parse_codec(struct hda_codec *codec)
1665{
1666 hda_nid_t nid;
1667 int i, nodes;
1668
1669 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1670 if (!nid || nodes < 0) {
1671 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1672 return -EINVAL;
1673 }
1674
1675 for (i = 0; i < nodes; i++, nid++) {
1676 unsigned int caps;
1677 unsigned int type;
1678
efc2f8de 1679 caps = get_wcaps(codec, nid);
079d88cc
WF		 1680 type = get_wcaps_type(caps);
1681
1682 if (!(caps & AC_WCAP_DIGITAL))
1683 continue;
1684
1685 switch (type) {
1686 case AC_WID_AUD_OUT:
384a48d7 1687 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1688 break;
1689 case AC_WID_PIN:
3eaead57 1690 hdmi_add_pin(codec, nid);
079d88cc
WF		 1691 break;
1692 }
1693 }
1694
079d88cc
WF		 1695 return 0;
1696}
1697
84eb01be
TI		 1698/*
1699 */
1a6003b5
TI		 1700static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1701{
1702 struct hda_spdif_out *spdif;
1703 bool non_pcm;
1704
1705 mutex_lock(&codec->spdif_mutex);
1706 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1707 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1708 mutex_unlock(&codec->spdif_mutex);
1709 return non_pcm;
1710}
1711
1712
84eb01be
TI		 1713/*
1714 * HDMI callbacks
1715 */
1716
1717static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1718 struct hda_codec *codec,
1719 unsigned int stream_tag,
1720 unsigned int format,
1721 struct snd_pcm_substream *substream)
1722{
384a48d7
SW		 1723 hda_nid_t cvt_nid = hinfo->nid;
1724 struct hdmi_spec *spec = codec->spec;
1725 int pin_idx = hinfo_to_pin_index(spec, hinfo);
b054087d
TI		 1726 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1727 hda_nid_t pin_nid = per_pin->pin_nid;
1a6003b5
TI		 1728 bool non_pcm;
1729
1730 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1731 mutex_lock(&per_pin->lock);
b054087d
TI		 1732 per_pin->channels = substream->runtime->channels;
1733 per_pin->setup = true;
384a48d7 1734
b054087d 1735 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1736 mutex_unlock(&per_pin->lock);
84eb01be 1737
307229d2 1738 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1739}
1740
8dfaa573
TI		 1741static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1742 struct hda_codec *codec,
1743 struct snd_pcm_substream *substream)
1744{
1745 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1746 return 0;
1747}
1748
f2ad24fa
TI		 1749static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1750 struct hda_codec *codec,
1751 struct snd_pcm_substream *substream)
384a48d7
SW		 1752{
1753 struct hdmi_spec *spec = codec->spec;
1754 int cvt_idx, pin_idx;
1755 struct hdmi_spec_per_cvt *per_cvt;
1756 struct hdmi_spec_per_pin *per_pin;
384a48d7 1757
384a48d7
SW		 1758 if (hinfo->nid) {
1759 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1760 if (snd_BUG_ON(cvt_idx < 0))
1761 return -EINVAL;
bce0d2a8 1762 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1763
1764 snd_BUG_ON(!per_cvt->assigned);
1765 per_cvt->assigned = 0;
1766 hinfo->nid = 0;
1767
1768 pin_idx = hinfo_to_pin_index(spec, hinfo);
1769 if (snd_BUG_ON(pin_idx < 0))
1770 return -EINVAL;
bce0d2a8 1771 per_pin = get_pin(spec, pin_idx);
384a48d7 1772
384a48d7 1773 snd_hda_spdif_ctls_unassign(codec, pin_idx);
cbbaa603 1774
a4e9a38b 1775 mutex_lock(&per_pin->lock);
d45e6889
TI		 1776 per_pin->chmap_set = false;
1777 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1778
1779 per_pin->setup = false;
1780 per_pin->channels = 0;
a4e9a38b 1781 mutex_unlock(&per_pin->lock);
384a48d7 1782 }
d45e6889 1783
384a48d7
SW		 1784 return 0;
1785}
1786
1787static const struct hda_pcm_ops generic_ops = {
1788 .open = hdmi_pcm_open,
f2ad24fa 1789 .close = hdmi_pcm_close,
384a48d7 1790 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1791 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1792};
1793
d45e6889
TI		 1794/*
1795 * ALSA API channel-map control callbacks
1796 */
1797static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1798 struct snd_ctl_elem_info *uinfo)
1799{
1800 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1801 struct hda_codec *codec = info->private_data;
1802 struct hdmi_spec *spec = codec->spec;
1803 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1804 uinfo->count = spec->channels_max;
1805 uinfo->value.integer.min = 0;
1806 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1807 return 0;
1808}
1809
307229d2
AH		 1810static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1811 int channels)
1812{
1813 /* If the speaker allocation matches the channel count, it is OK.*/
1814 if (cap->channels != channels)
1815 return -1;
1816
1817 /* all channels are remappable freely */
1818 return SNDRV_CTL_TLVT_CHMAP_VAR;
1819}
1820
1821static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1822 unsigned int *chmap, int channels)
1823{
1824 int count = 0;
1825 int c;
1826
1827 for (c = 7; c >= 0; c--) {
1828 int spk = cap->speakers[c];
1829 if (!spk)
1830 continue;
1831
1832 chmap[count++] = spk_to_chmap(spk);
1833 }
1834
1835 WARN_ON(count != channels);
1836}
1837
d45e6889
TI		 1838static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1839 unsigned int size, unsigned int __user *tlv)
1840{
1841 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1842 struct hda_codec *codec = info->private_data;
1843 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 1844 unsigned int __user *dst;
1845 int chs, count = 0;
1846
1847 if (size < 8)
1848 return -ENOMEM;
1849 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1850 return -EFAULT;
1851 size -= 8;
1852 dst = tlv + 2;
498dab3a 1853 for (chs = 2; chs <= spec->channels_max; chs++) {
307229d2 1854 int i;
d45e6889
TI		 1855 struct cea_channel_speaker_allocation *cap;
1856 cap = channel_allocations;
1857 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1858 int chs_bytes = chs * 4;
307229d2
AH		 1859 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1860 unsigned int tlv_chmap[8];
1861
1862 if (type < 0)
d45e6889 1863 continue;
d45e6889
TI		 1864 if (size < 8)
1865 return -ENOMEM;
307229d2 1866 if (put_user(type, dst) ||
d45e6889
TI		 1867 put_user(chs_bytes, dst + 1))
1868 return -EFAULT;
1869 dst += 2;
1870 size -= 8;
1871 count += 8;
1872 if (size < chs_bytes)
1873 return -ENOMEM;
1874 size -= chs_bytes;
1875 count += chs_bytes;
307229d2
AH		 1876 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1877 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1878 return -EFAULT;
1879 dst += chs;
d45e6889
TI		 1880 }
1881 }
1882 if (put_user(count, tlv + 1))
1883 return -EFAULT;
1884 return 0;
1885}
1886
1887static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1888 struct snd_ctl_elem_value *ucontrol)
1889{
1890 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1891 struct hda_codec *codec = info->private_data;
1892 struct hdmi_spec *spec = codec->spec;
1893 int pin_idx = kcontrol->private_value;
bce0d2a8 1894 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1895 int i;
1896
1897 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1898 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1899 return 0;
1900}
1901
1902static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1903 struct snd_ctl_elem_value *ucontrol)
1904{
1905 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1906 struct hda_codec *codec = info->private_data;
1907 struct hdmi_spec *spec = codec->spec;
1908 int pin_idx = kcontrol->private_value;
bce0d2a8 1909 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1910 unsigned int ctl_idx;
1911 struct snd_pcm_substream *substream;
1912 unsigned char chmap[8];
307229d2 1913 int i, err, ca, prepared = 0;
d45e6889
TI		 1914
1915 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1916 substream = snd_pcm_chmap_substream(info, ctl_idx);
1917 if (!substream || !substream->runtime)
6f54c361 1918 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1919 switch (substream->runtime->status->state) {
1920 case SNDRV_PCM_STATE_OPEN:
1921 case SNDRV_PCM_STATE_SETUP:
1922 break;
1923 case SNDRV_PCM_STATE_PREPARED:
1924 prepared = 1;
1925 break;
1926 default:
1927 return -EBUSY;
1928 }
1929 memset(chmap, 0, sizeof(chmap));
1930 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1931 chmap[i] = ucontrol->value.integer.value[i];
1932 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1933 return 0;
1934 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1935 if (ca < 0)
1936 return -EINVAL;
307229d2
AH		 1937 if (spec->ops.chmap_validate) {
1938 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
1939 if (err)
1940 return err;
1941 }
a4e9a38b 1942 mutex_lock(&per_pin->lock);
d45e6889
TI		 1943 per_pin->chmap_set = true;
1944 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1945 if (prepared)
b054087d 1946 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
a4e9a38b 1947 mutex_unlock(&per_pin->lock);
d45e6889
TI		 1948
1949 return 0;
1950}
1951
84eb01be
TI		 1952static int generic_hdmi_build_pcms(struct hda_codec *codec)
1953{
1954 struct hdmi_spec *spec = codec->spec;
384a48d7 1955 int pin_idx;
84eb01be 1956
384a48d7
SW		 1957 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1958 struct hda_pcm *info;
84eb01be 1959 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 1960 struct hdmi_spec_per_pin *per_pin;
1961
1962 per_pin = get_pin(spec, pin_idx);
1963 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
1964 info = snd_array_new(&spec->pcm_rec);
1965 if (!info)
1966 return -ENOMEM;
1967 info->name = per_pin->pcm_name;
84eb01be 1968 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1969 info->own_chmap = true;
384a48d7 1970
84eb01be 1971 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1972 pstr->substreams = 1;
1973 pstr->ops = generic_ops;
1974 /* other pstr fields are set in open */
84eb01be
TI		 1975 }
1976
384a48d7 1977 codec->num_pcms = spec->num_pins;
bce0d2a8 1978 codec->pcm_info = spec->pcm_rec.list;
384a48d7 1979
84eb01be
TI		 1980 return 0;
1981}
1982
0b6c49b5
DH		 1983static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1984{
31ef2257 1985 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 1986 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 1987 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1988 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 1989
31ef2257
TI		 1990 if (pcmdev > 0)
1991 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 1992 if (!is_jack_detectable(codec, per_pin->pin_nid))
1993 strncat(hdmi_str, " Phantom",
1994 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 1995
31ef2257 1996 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1997}
1998
84eb01be
TI		 1999static int generic_hdmi_build_controls(struct hda_codec *codec)
2000{
2001 struct hdmi_spec *spec = codec->spec;
2002 int err;
384a48d7 2003 int pin_idx;
84eb01be 2004
384a48d7 2005 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2006 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 2007
2008 err = generic_hdmi_build_jack(codec, pin_idx);
2009 if (err < 0)
2010 return err;
2011
dcda5806
TI		 2012 err = snd_hda_create_dig_out_ctls(codec,
2013 per_pin->pin_nid,
2014 per_pin->mux_nids[0],
2015 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 2016 if (err < 0)
2017 return err;
384a48d7 2018 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 2019
2020 /* add control for ELD Bytes */
bce0d2a8
TI		 2021 err = hdmi_create_eld_ctl(codec, pin_idx,
2022 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 2023
2024 if (err < 0)
2025 return err;
31ef2257 2026
82b1d73f 2027 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2028 }
2029
d45e6889
TI		 2030 /* add channel maps */
2031 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2032 struct snd_pcm_chmap *chmap;
2033 struct snd_kcontrol *kctl;
2034 int i;
2ca320e2
TI		 2035
2036 if (!codec->pcm_info[pin_idx].pcm)
2037 break;
d45e6889
TI		 2038 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
2039 SNDRV_PCM_STREAM_PLAYBACK,
2040 NULL, 0, pin_idx, &chmap);
2041 if (err < 0)
2042 return err;
2043 /* override handlers */
2044 chmap->private_data = codec;
2045 kctl = chmap->kctl;
2046 for (i = 0; i < kctl->count; i++)
2047 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2048 kctl->info = hdmi_chmap_ctl_info;
2049 kctl->get = hdmi_chmap_ctl_get;
2050 kctl->put = hdmi_chmap_ctl_put;
2051 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2052 }
2053
84eb01be
TI		 2054 return 0;
2055}
2056
8b8d654b 2057static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2058{
2059 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2060 int pin_idx;
2061
2062 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2063 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2064
744626da 2065 per_pin->codec = codec;
a4e9a38b 2066 mutex_init(&per_pin->lock);
744626da 2067 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2068 eld_proc_new(per_pin, pin_idx);
84eb01be 2069 }
8b8d654b
TI		 2070 return 0;
2071}
2072
2073static int generic_hdmi_init(struct hda_codec *codec)
2074{
2075 struct hdmi_spec *spec = codec->spec;
2076 int pin_idx;
2077
2078 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2079 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2080 hda_nid_t pin_nid = per_pin->pin_nid;
2081
2082 hdmi_init_pin(codec, pin_nid);
2083 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
2084 }
84eb01be
TI		 2085 return 0;
2086}
2087
bce0d2a8
TI		 2088static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2089{
2090 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2091 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2092 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
2093}
2094
2095static void hdmi_array_free(struct hdmi_spec *spec)
2096{
2097 snd_array_free(&spec->pins);
2098 snd_array_free(&spec->cvts);
2099 snd_array_free(&spec->pcm_rec);
2100}
2101
84eb01be
TI		 2102static void generic_hdmi_free(struct hda_codec *codec)
2103{
2104 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2105 int pin_idx;
2106
2107 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2108 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2109
744626da 2110 cancel_delayed_work(&per_pin->work);
a4e9a38b 2111 eld_proc_free(per_pin);
384a48d7 2112 }
84eb01be 2113
744626da 2114 flush_workqueue(codec->bus->workq);
bce0d2a8 2115 hdmi_array_free(spec);
84eb01be
TI		 2116 kfree(spec);
2117}
2118
28cb72e5
WX		 2119#ifdef CONFIG_PM
2120static int generic_hdmi_resume(struct hda_codec *codec)
2121{
2122 struct hdmi_spec *spec = codec->spec;
2123 int pin_idx;
2124
2125 generic_hdmi_init(codec);
2126 snd_hda_codec_resume_amp(codec);
2127 snd_hda_codec_resume_cache(codec);
2128
2129 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2130 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2131 hdmi_present_sense(per_pin, 1);
2132 }
2133 return 0;
2134}
2135#endif
2136
fb79e1e0 2137static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2138 .init = generic_hdmi_init,
2139 .free = generic_hdmi_free,
2140 .build_pcms = generic_hdmi_build_pcms,
2141 .build_controls = generic_hdmi_build_controls,
2142 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2143#ifdef CONFIG_PM
2144 .resume = generic_hdmi_resume,
2145#endif
84eb01be
TI		 2146};
2147
307229d2
AH		 2148static const struct hdmi_ops generic_standard_hdmi_ops = {
2149 .pin_get_eld = snd_hdmi_get_eld,
2150 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2151 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2152 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2153 .pin_hbr_setup = hdmi_pin_hbr_setup,
2154 .setup_stream = hdmi_setup_stream,
2155 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2156 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2157};
2158
6ffe168f 2159
c88d4e84
TI		 2160static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2161 hda_nid_t nid)
2162{
2163 struct hdmi_spec *spec = codec->spec;
2164 hda_nid_t conns[4];
2165 int nconns;
6ffe168f 2166
c88d4e84
TI		 2167 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2168 if (nconns == spec->num_cvts &&
2169 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2170 return;
2171
c88d4e84
TI		 2172 /* override pins connection list */
2173 snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
2174 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2175}
2176
1611a9c9
ML		 2177#define INTEL_VENDOR_NID 0x08
2178#define INTEL_GET_VENDOR_VERB 0xf81
2179#define INTEL_SET_VENDOR_VERB 0x781
2180#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2181#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2182
2183static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2184 bool update_tree)
1611a9c9
ML		 2185{
2186 unsigned int vendor_param;
2187
1611a9c9
ML		 2188 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2189 INTEL_GET_VENDOR_VERB, 0);
2190 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2191 return;
2192
2193 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2194 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2195 INTEL_SET_VENDOR_VERB, vendor_param);
2196 if (vendor_param == -1)
2197 return;
2198
17df3f55
TI		 2199 if (update_tree)
2200 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2201}
2202
c88d4e84
TI		 2203static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2204{
2205 unsigned int vendor_param;
2206
2207 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2208 INTEL_GET_VENDOR_VERB, 0);
2209 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2210 return;
2211
2212 /* enable DP1.2 mode */
2213 vendor_param |= INTEL_EN_DP12;
2214 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2215 INTEL_SET_VENDOR_VERB, vendor_param);
2216}
2217
17df3f55
TI		 2218/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2219 * Otherwise you may get severe h/w communication errors.
2220 */
2221static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2222 unsigned int power_state)
2223{
2224 if (power_state == AC_PWRST_D0) {
2225 intel_haswell_enable_all_pins(codec, false);
2226 intel_haswell_fixup_enable_dp12(codec);
2227 }
c88d4e84 2228
17df3f55
TI		 2229 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2230 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2231}
6ffe168f 2232
84eb01be
TI		 2233static int patch_generic_hdmi(struct hda_codec *codec)
2234{
2235 struct hdmi_spec *spec;
84eb01be
TI		 2236
2237 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2238 if (spec == NULL)
2239 return -ENOMEM;
2240
307229d2 2241 spec->ops = generic_standard_hdmi_ops;
84eb01be 2242 codec->spec = spec;
bce0d2a8 2243 hdmi_array_init(spec, 4);
6ffe168f 2244
fb87fa3a 2245 if (is_haswell(codec)) {
17df3f55 2246 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2247 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2248 }
6ffe168f 2249
84eb01be
TI		 2250 if (hdmi_parse_codec(codec) < 0) {
2251 codec->spec = NULL;
2252 kfree(spec);
2253 return -EINVAL;
2254 }
2255 codec->patch_ops = generic_hdmi_patch_ops;
fb87fa3a 2256 if (is_haswell(codec)) {
17df3f55 2257 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2258 codec->dp_mst = true;
2259 }
17df3f55 2260
8b8d654b 2261 generic_hdmi_init_per_pins(codec);
84eb01be 2262
84eb01be
TI		 2263 init_channel_allocations();
2264
2265 return 0;
2266}
2267
3aaf8980
SW		 2268/*
2269 * Shared non-generic implementations
2270 */
2271
2272static int simple_playback_build_pcms(struct hda_codec *codec)
2273{
2274 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2275 struct hda_pcm *info;
8ceb332d
TI		 2276 unsigned int chans;
2277 struct hda_pcm_stream *pstr;
bce0d2a8 2278 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2279
bce0d2a8
TI		 2280 per_cvt = get_cvt(spec, 0);
2281 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2282 chans = get_wcaps_channels(chans);
3aaf8980 2283
bce0d2a8
TI		 2284 info = snd_array_new(&spec->pcm_rec);
2285 if (!info)
2286 return -ENOMEM;
2287 info->name = get_pin(spec, 0)->pcm_name;
2288 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2289 info->pcm_type = HDA_PCM_TYPE_HDMI;
2290 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2291 *pstr = spec->pcm_playback;
bce0d2a8 2292 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2293 if (pstr->channels_max <= 2 && chans && chans <= 16)
2294 pstr->channels_max = chans;
3aaf8980 2295
bce0d2a8
TI		 2296 codec->num_pcms = 1;
2297 codec->pcm_info = info;
2298
3aaf8980
SW		 2299 return 0;
2300}
2301
4b6ace9e
TI		 2302/* unsolicited event for jack sensing */
2303static void simple_hdmi_unsol_event(struct hda_codec *codec,
2304 unsigned int res)
2305{
9dd8cf12 2306 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2307 snd_hda_jack_report_sync(codec);
2308}
2309
2310/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2311 * as long as spec->pins[] is set correctly
2312 */
2313#define simple_hdmi_build_jack generic_hdmi_build_jack
2314
3aaf8980
SW		 2315static int simple_playback_build_controls(struct hda_codec *codec)
2316{
2317 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2318 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2319 int err;
3aaf8980 2320
bce0d2a8
TI		 2321 per_cvt = get_cvt(spec, 0);
2322 err = snd_hda_create_spdif_out_ctls(codec, per_cvt->cvt_nid,
2323 per_cvt->cvt_nid);
8ceb332d
TI		 2324 if (err < 0)
2325 return err;
2326 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2327}
2328
4f0110ce
TI		 2329static int simple_playback_init(struct hda_codec *codec)
2330{
2331 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2332 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2333 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2334
2335 snd_hda_codec_write(codec, pin, 0,
2336 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2337 /* some codecs require to unmute the pin */
2338 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2339 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2340 AMP_OUT_UNMUTE);
2341 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2342 return 0;
2343}
2344
3aaf8980
SW		 2345static void simple_playback_free(struct hda_codec *codec)
2346{
2347 struct hdmi_spec *spec = codec->spec;
2348
bce0d2a8 2349 hdmi_array_free(spec);
3aaf8980
SW		 2350 kfree(spec);
2351}
2352
84eb01be
TI		 2353/*
2354 * Nvidia specific implementations
2355 */
2356
2357#define Nv_VERB_SET_Channel_Allocation 0xF79
2358#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2359#define Nv_VERB_SET_Audio_Protection_On 0xF98
2360#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2361
2362#define nvhdmi_master_con_nid_7x 0x04
2363#define nvhdmi_master_pin_nid_7x 0x05
2364
fb79e1e0 2365static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2366 /*front, rear, clfe, rear_surr */
2367 0x6, 0x8, 0xa, 0xc,
2368};
2369
ceaa86ba
TI		 2370static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2371 /* set audio protect on */
2372 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2373 /* enable digital output on pin widget */
2374 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2375 {} /* terminator */
2376};
2377
2378static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2379 /* set audio protect on */
2380 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2381 /* enable digital output on pin widget */
2382 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2383 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2384 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2385 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2386 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2387 {} /* terminator */
2388};
2389
2390#ifdef LIMITED_RATE_FMT_SUPPORT
2391/* support only the safe format and rate */
2392#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2393#define SUPPORTED_MAXBPS 16
2394#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2395#else
2396/* support all rates and formats */
2397#define SUPPORTED_RATES \
2398 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2399 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2400 SNDRV_PCM_RATE_192000)
2401#define SUPPORTED_MAXBPS 24
2402#define SUPPORTED_FORMATS \
2403 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2404#endif
2405
ceaa86ba
TI		 2406static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2407{
2408 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2409 return 0;
2410}
2411
2412static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2413{
ceaa86ba 2414 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2415 return 0;
2416}
2417
393004b2
ND		 2418static unsigned int channels_2_6_8[] = {
2419 2, 6, 8
2420};
2421
2422static unsigned int channels_2_8[] = {
2423 2, 8
2424};
2425
2426static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2427 .count = ARRAY_SIZE(channels_2_6_8),
2428 .list = channels_2_6_8,
2429 .mask = 0,
2430};
2431
2432static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2433 .count = ARRAY_SIZE(channels_2_8),
2434 .list = channels_2_8,
2435 .mask = 0,
2436};
2437
84eb01be
TI		 2438static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2439 struct hda_codec *codec,
2440 struct snd_pcm_substream *substream)
2441{
2442 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2443 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2444
2445 switch (codec->preset->id) {
2446 case 0x10de0002:
2447 case 0x10de0003:
2448 case 0x10de0005:
2449 case 0x10de0006:
2450 hw_constraints_channels = &hw_constraints_2_8_channels;
2451 break;
2452 case 0x10de0007:
2453 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2454 break;
2455 default:
2456 break;
2457 }
2458
2459 if (hw_constraints_channels != NULL) {
2460 snd_pcm_hw_constraint_list(substream->runtime, 0,
2461 SNDRV_PCM_HW_PARAM_CHANNELS,
2462 hw_constraints_channels);
ad09fc9d
TI		 2463 } else {
2464 snd_pcm_hw_constraint_step(substream->runtime, 0,
2465 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2466 }
2467
84eb01be
TI		 2468 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2469}
2470
2471static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2472 struct hda_codec *codec,
2473 struct snd_pcm_substream *substream)
2474{
2475 struct hdmi_spec *spec = codec->spec;
2476 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2477}
2478
2479static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2480 struct hda_codec *codec,
2481 unsigned int stream_tag,
2482 unsigned int format,
2483 struct snd_pcm_substream *substream)
2484{
2485 struct hdmi_spec *spec = codec->spec;
2486 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2487 stream_tag, format, substream);
2488}
2489
d0b1252d
TI		 2490static const struct hda_pcm_stream simple_pcm_playback = {
2491 .substreams = 1,
2492 .channels_min = 2,
2493 .channels_max = 2,
2494 .ops = {
2495 .open = simple_playback_pcm_open,
2496 .close = simple_playback_pcm_close,
2497 .prepare = simple_playback_pcm_prepare
2498 },
2499};
2500
2501static const struct hda_codec_ops simple_hdmi_patch_ops = {
2502 .build_controls = simple_playback_build_controls,
2503 .build_pcms = simple_playback_build_pcms,
2504 .init = simple_playback_init,
2505 .free = simple_playback_free,
250e41ac 2506 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2507};
2508
2509static int patch_simple_hdmi(struct hda_codec *codec,
2510 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2511{
2512 struct hdmi_spec *spec;
bce0d2a8
TI		 2513 struct hdmi_spec_per_cvt *per_cvt;
2514 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2515
2516 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2517 if (!spec)
2518 return -ENOMEM;
2519
2520 codec->spec = spec;
bce0d2a8 2521 hdmi_array_init(spec, 1);
d0b1252d
TI		 2522
2523 spec->multiout.num_dacs = 0; /* no analog */
2524 spec->multiout.max_channels = 2;
2525 spec->multiout.dig_out_nid = cvt_nid;
2526 spec->num_cvts = 1;
2527 spec->num_pins = 1;
bce0d2a8
TI		 2528 per_pin = snd_array_new(&spec->pins);
2529 per_cvt = snd_array_new(&spec->cvts);
2530 if (!per_pin || !per_cvt) {
2531 simple_playback_free(codec);
2532 return -ENOMEM;
2533 }
2534 per_cvt->cvt_nid = cvt_nid;
2535 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2536 spec->pcm_playback = simple_pcm_playback;
2537
2538 codec->patch_ops = simple_hdmi_patch_ops;
2539
2540 return 0;
2541}
2542
1f348522
AP		 2543static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2544 int channels)
2545{
2546 unsigned int chanmask;
2547 int chan = channels ? (channels - 1) : 1;
2548
2549 switch (channels) {
2550 default:
2551 case 0:
2552 case 2:
2553 chanmask = 0x00;
2554 break;
2555 case 4:
2556 chanmask = 0x08;
2557 break;
2558 case 6:
2559 chanmask = 0x0b;
2560 break;
2561 case 8:
2562 chanmask = 0x13;
2563 break;
2564 }
2565
2566 /* Set the audio infoframe channel allocation and checksum fields. The
2567 * channel count is computed implicitly by the hardware. */
2568 snd_hda_codec_write(codec, 0x1, 0,
2569 Nv_VERB_SET_Channel_Allocation, chanmask);
2570
2571 snd_hda_codec_write(codec, 0x1, 0,
2572 Nv_VERB_SET_Info_Frame_Checksum,
2573 (0x71 - chan - chanmask));
2574}
2575
84eb01be
TI		 2576static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2577 struct hda_codec *codec,
2578 struct snd_pcm_substream *substream)
2579{
2580 struct hdmi_spec *spec = codec->spec;
2581 int i;
2582
2583 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2584 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2585 for (i = 0; i < 4; i++) {
2586 /* set the stream id */
2587 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2588 AC_VERB_SET_CHANNEL_STREAMID, 0);
2589 /* set the stream format */
2590 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2591 AC_VERB_SET_STREAM_FORMAT, 0);
2592 }
2593
1f348522
AP		 2594 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2595 * streams are disabled. */
2596 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2597
84eb01be
TI		 2598 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2599}
2600
2601static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2602 struct hda_codec *codec,
2603 unsigned int stream_tag,
2604 unsigned int format,
2605 struct snd_pcm_substream *substream)
2606{
2607 int chs;
112daa7a 2608 unsigned int dataDCC2, channel_id;
84eb01be 2609 int i;
7c935976 2610 struct hdmi_spec *spec = codec->spec;
e3245cdd 2611 struct hda_spdif_out *spdif;
bce0d2a8 2612 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2613
2614 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2615 per_cvt = get_cvt(spec, 0);
2616 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2617
2618 chs = substream->runtime->channels;
84eb01be 2619
84eb01be
TI		 2620 dataDCC2 = 0x2;
2621
84eb01be 2622 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2623 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2624 snd_hda_codec_write(codec,
2625 nvhdmi_master_con_nid_7x,
2626 0,
2627 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2628 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2629
2630 /* set the stream id */
2631 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2632 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2633
2634 /* set the stream format */
2635 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2636 AC_VERB_SET_STREAM_FORMAT, format);
2637
2638 /* turn on again (if needed) */
2639 /* enable and set the channel status audio/data flag */
7c935976 2640 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2641 snd_hda_codec_write(codec,
2642 nvhdmi_master_con_nid_7x,
2643 0,
2644 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2645 spdif->ctls & 0xff);
84eb01be
TI		 2646 snd_hda_codec_write(codec,
2647 nvhdmi_master_con_nid_7x,
2648 0,
2649 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2650 }
2651
2652 for (i = 0; i < 4; i++) {
2653 if (chs == 2)
2654 channel_id = 0;
2655 else
2656 channel_id = i * 2;
2657
2658 /* turn off SPDIF once;
2659 *otherwise the IEC958 bits won't be updated
2660 */
2661 if (codec->spdif_status_reset &&
7c935976 2662 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2663 snd_hda_codec_write(codec,
2664 nvhdmi_con_nids_7x[i],
2665 0,
2666 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2667 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2668 /* set the stream id */
2669 snd_hda_codec_write(codec,
2670 nvhdmi_con_nids_7x[i],
2671 0,
2672 AC_VERB_SET_CHANNEL_STREAMID,
2673 (stream_tag << 4) | channel_id);
2674 /* set the stream format */
2675 snd_hda_codec_write(codec,
2676 nvhdmi_con_nids_7x[i],
2677 0,
2678 AC_VERB_SET_STREAM_FORMAT,
2679 format);
2680 /* turn on again (if needed) */
2681 /* enable and set the channel status audio/data flag */
2682 if (codec->spdif_status_reset &&
7c935976 2683 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2684 snd_hda_codec_write(codec,
2685 nvhdmi_con_nids_7x[i],
2686 0,
2687 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2688 spdif->ctls & 0xff);
84eb01be
TI		 2689 snd_hda_codec_write(codec,
2690 nvhdmi_con_nids_7x[i],
2691 0,
2692 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2693 }
2694 }
2695
1f348522 2696 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2697
2698 mutex_unlock(&codec->spdif_mutex);
2699 return 0;
2700}
2701
fb79e1e0 2702static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2703 .substreams = 1,
2704 .channels_min = 2,
2705 .channels_max = 8,
2706 .nid = nvhdmi_master_con_nid_7x,
2707 .rates = SUPPORTED_RATES,
2708 .maxbps = SUPPORTED_MAXBPS,
2709 .formats = SUPPORTED_FORMATS,
2710 .ops = {
2711 .open = simple_playback_pcm_open,
2712 .close = nvhdmi_8ch_7x_pcm_close,
2713 .prepare = nvhdmi_8ch_7x_pcm_prepare
2714 },
2715};
2716
84eb01be
TI		 2717static int patch_nvhdmi_2ch(struct hda_codec *codec)
2718{
2719 struct hdmi_spec *spec;
d0b1252d
TI		 2720 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2721 nvhdmi_master_pin_nid_7x);
2722 if (err < 0)
2723 return err;
84eb01be 2724
ceaa86ba 2725 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2726 /* override the PCM rates, etc, as the codec doesn't give full list */
2727 spec = codec->spec;
2728 spec->pcm_playback.rates = SUPPORTED_RATES;
2729 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2730 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2731 return 0;
2732}
2733
53775b0d
TI		 2734static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2735{
2736 struct hdmi_spec *spec = codec->spec;
2737 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2738 if (!err) {
2739 struct hda_pcm *info = get_pcm_rec(spec, 0);
2740 info->own_chmap = true;
2741 }
53775b0d
TI		 2742 return err;
2743}
2744
2745static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2746{
2747 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2748 struct hda_pcm *info;
53775b0d
TI		 2749 struct snd_pcm_chmap *chmap;
2750 int err;
2751
2752 err = simple_playback_build_controls(codec);
2753 if (err < 0)
2754 return err;
2755
2756 /* add channel maps */
bce0d2a8
TI		 2757 info = get_pcm_rec(spec, 0);
2758 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2759 SNDRV_PCM_STREAM_PLAYBACK,
2760 snd_pcm_alt_chmaps, 8, 0, &chmap);
2761 if (err < 0)
2762 return err;
2763 switch (codec->preset->id) {
2764 case 0x10de0002:
2765 case 0x10de0003:
2766 case 0x10de0005:
2767 case 0x10de0006:
2768 chmap->channel_mask = (1U << 2) | (1U << 8);
2769 break;
2770 case 0x10de0007:
2771 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2772 }
2773 return 0;
2774}
2775
84eb01be
TI		 2776static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2777{
2778 struct hdmi_spec *spec;
2779 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2780 if (err < 0)
2781 return err;
2782 spec = codec->spec;
2783 spec->multiout.max_channels = 8;
d0b1252d 2784 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2785 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2786 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2787 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2788
2789 /* Initialize the audio infoframe channel mask and checksum to something
2790 * valid */
2791 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2792
84eb01be
TI		 2793 return 0;
2794}
2795
611885bc
AH		 2796/*
2797 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2798 * - 0x10de0015
2799 * - 0x10de0040
2800 */
2801static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2802 int channels)
2803{
2804 if (cap->ca_index == 0x00 && channels == 2)
2805 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2806
2807 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2808}
2809
2810static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2811{
2812 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2813 return -EINVAL;
2814
2815 return 0;
2816}
2817
2818static int patch_nvhdmi(struct hda_codec *codec)
2819{
2820 struct hdmi_spec *spec;
2821 int err;
2822
2823 err = patch_generic_hdmi(codec);
2824 if (err)
2825 return err;
2826
2827 spec = codec->spec;
2828
2829 spec->ops.chmap_cea_alloc_validate_get_type =
2830 nvhdmi_chmap_cea_alloc_validate_get_type;
2831 spec->ops.chmap_validate = nvhdmi_chmap_validate;
2832
2833 return 0;
2834}
2835
84eb01be 2836/*
5a613584 2837 * ATI/AMD-specific implementations
84eb01be
TI		 2838 */
2839
5a613584
AH		 2840#define is_amdhdmi_rev3_or_later(codec) \
2841 ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300)
2842#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
2843
2844/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
2845#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
2846#define ATI_VERB_SET_DOWNMIX_INFO 0x772
2847#define ATI_VERB_SET_MULTICHANNEL_01 0x777
2848#define ATI_VERB_SET_MULTICHANNEL_23 0x778
2849#define ATI_VERB_SET_MULTICHANNEL_45 0x779
2850#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 2851#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 2852#define ATI_VERB_SET_MULTICHANNEL_1 0x785
2853#define ATI_VERB_SET_MULTICHANNEL_3 0x786
2854#define ATI_VERB_SET_MULTICHANNEL_5 0x787
2855#define ATI_VERB_SET_MULTICHANNEL_7 0x788
2856#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
2857#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
2858#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
2859#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
2860#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
2861#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
2862#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 2863#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 2864#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
2865#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
2866#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
2867#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
2868#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
2869
84d69e79
AH		 2870/* AMD specific HDA cvt verbs */
2871#define ATI_VERB_SET_RAMP_RATE 0x770
2872#define ATI_VERB_GET_RAMP_RATE 0xf70
2873
5a613584
AH		 2874#define ATI_OUT_ENABLE 0x1
2875
2876#define ATI_MULTICHANNEL_MODE_PAIRED 0
2877#define ATI_MULTICHANNEL_MODE_SINGLE 1
2878
461cf6b3
AH		 2879#define ATI_HBR_CAPABLE 0x01
2880#define ATI_HBR_ENABLE 0x10
2881
89250f84
AH		 2882static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
2883 unsigned char *buf, int *eld_size)
2884{
2885 /* call hda_eld.c ATI/AMD-specific function */
2886 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
2887 is_amdhdmi_rev3_or_later(codec));
2888}
2889
5a613584
AH		 2890static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
2891 int active_channels, int conn_type)
2892{
2893 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
2894}
2895
2896static int atihdmi_paired_swap_fc_lfe(int pos)
2897{
2898 /*
2899 * ATI/AMD have automatic FC/LFE swap built-in
2900 * when in pairwise mapping mode.
2901 */
2902
2903 switch (pos) {
2904 /* see channel_allocations[].speakers[] */
2905 case 2: return 3;
2906 case 3: return 2;
2907 default: break;
2908 }
2909
2910 return pos;
2911}
2912
2913static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
2914{
2915 struct cea_channel_speaker_allocation *cap;
2916 int i, j;
2917
2918 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
2919
2920 cap = &channel_allocations[get_channel_allocation_order(ca)];
2921 for (i = 0; i < chs; ++i) {
2922 int mask = to_spk_mask(map[i]);
2923 bool ok = false;
2924 bool companion_ok = false;
2925
2926 if (!mask)
2927 continue;
2928
2929 for (j = 0 + i % 2; j < 8; j += 2) {
2930 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
2931 if (cap->speakers[chan_idx] == mask) {
2932 /* channel is in a supported position */
2933 ok = true;
2934
2935 if (i % 2 == 0 && i + 1 < chs) {
2936 /* even channel, check the odd companion */
2937 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
2938 int comp_mask_req = to_spk_mask(map[i+1]);
2939 int comp_mask_act = cap->speakers[comp_chan_idx];
2940
2941 if (comp_mask_req == comp_mask_act)
2942 companion_ok = true;
2943 else
2944 return -EINVAL;
2945 }
2946 break;
2947 }
2948 }
2949
2950 if (!ok)
2951 return -EINVAL;
2952
2953 if (companion_ok)
2954 i++; /* companion channel already checked */
2955 }
2956
2957 return 0;
2958}
2959
2960static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
2961 int hdmi_slot, int stream_channel)
2962{
2963 int verb;
2964 int ati_channel_setup = 0;
2965
2966 if (hdmi_slot > 7)
2967 return -EINVAL;
2968
2969 if (!has_amd_full_remap_support(codec)) {
2970 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
2971
2972 /* In case this is an odd slot but without stream channel, do not
2973 * disable the slot since the corresponding even slot could have a
2974 * channel. In case neither have a channel, the slot pair will be
2975 * disabled when this function is called for the even slot. */
2976 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
2977 return 0;
2978
2979 hdmi_slot -= hdmi_slot % 2;
2980
2981 if (stream_channel != 0xf)
2982 stream_channel -= stream_channel % 2;
2983 }
2984
2985 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
2986
2987 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
2988
2989 if (stream_channel != 0xf)
2990 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
2991
2992 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
2993}
2994
2995static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
2996 int asp_slot)
2997{
2998 bool was_odd = false;
2999 int ati_asp_slot = asp_slot;
3000 int verb;
3001 int ati_channel_setup;
3002
3003 if (asp_slot > 7)
3004 return -EINVAL;
3005
3006 if (!has_amd_full_remap_support(codec)) {
3007 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3008 if (ati_asp_slot % 2 != 0) {
3009 ati_asp_slot -= 1;
3010 was_odd = true;
3011 }
3012 }
3013
3014 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3015
3016 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3017
3018 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3019 return 0xf;
3020
3021 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3022}
84eb01be 3023
5a613584
AH		 3024static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3025 int channels)
3026{
3027 int c;
3028
3029 /*
3030 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3031 * we need to take that into account (a single channel may take 2
3032 * channel slots if we need to carry a silent channel next to it).
3033 * On Rev3+ AMD codecs this function is not used.
3034 */
3035 int chanpairs = 0;
3036
3037 /* We only produce even-numbered channel count TLVs */
3038 if ((channels % 2) != 0)
3039 return -1;
3040
3041 for (c = 0; c < 7; c += 2) {
3042 if (cap->speakers[c] || cap->speakers[c+1])
3043 chanpairs++;
3044 }
3045
3046 if (chanpairs * 2 != channels)
3047 return -1;
3048
3049 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3050}
3051
3052static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3053 unsigned int *chmap, int channels)
3054{
3055 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3056 int count = 0;
3057 int c;
3058
3059 for (c = 7; c >= 0; c--) {
3060 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3061 int spk = cap->speakers[chan];
3062 if (!spk) {
3063 /* add N/A channel if the companion channel is occupied */
3064 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3065 chmap[count++] = SNDRV_CHMAP_NA;
3066
3067 continue;
3068 }
3069
3070 chmap[count++] = spk_to_chmap(spk);
3071 }
3072
3073 WARN_ON(count != channels);
3074}
3075
461cf6b3
AH		 3076static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3077 bool hbr)
3078{
3079 int hbr_ctl, hbr_ctl_new;
3080
3081 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3082 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3083 if (hbr)
3084 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3085 else
3086 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3087
3088 snd_printdd("atihdmi_pin_hbr_setup: "
3089 "NID=0x%x, %shbr-ctl=0x%x\n",
3090 pin_nid,
3091 hbr_ctl == hbr_ctl_new ? "" : "new-",
3092 hbr_ctl_new);
3093
3094 if (hbr_ctl != hbr_ctl_new)
3095 snd_hda_codec_write(codec, pin_nid, 0,
3096 ATI_VERB_SET_HBR_CONTROL,
3097 hbr_ctl_new);
3098
3099 } else if (hbr)
3100 return -EINVAL;
3101
3102 return 0;
3103}
3104
84d69e79
AH		 3105static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3106 hda_nid_t pin_nid, u32 stream_tag, int format)
3107{
3108
3109 if (is_amdhdmi_rev3_or_later(codec)) {
3110 int ramp_rate = 180; /* default as per AMD spec */
3111 /* disable ramp-up/down for non-pcm as per AMD spec */
3112 if (format & AC_FMT_TYPE_NON_PCM)
3113 ramp_rate = 0;
3114
3115 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3116 }
3117
3118 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3119}
3120
3121
5a613584 3122static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3123{
3124 struct hdmi_spec *spec = codec->spec;
5a613584 3125 int pin_idx, err;
84eb01be 3126
5a613584
AH		 3127 err = generic_hdmi_init(codec);
3128
3129 if (err)
84eb01be 3130 return err;
5a613584
AH		 3131
3132 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3133 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3134
3135 /* make sure downmix information in infoframe is zero */
3136 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3137
3138 /* enable channel-wise remap mode if supported */
3139 if (has_amd_full_remap_support(codec))
3140 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3141 ATI_VERB_SET_MULTICHANNEL_MODE,
3142 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3143 }
5a613584 3144
84eb01be
TI		 3145 return 0;
3146}
3147
84eb01be
TI		 3148static int patch_atihdmi(struct hda_codec *codec)
3149{
3150 struct hdmi_spec *spec;
5a613584
AH		 3151 struct hdmi_spec_per_cvt *per_cvt;
3152 int err, cvt_idx;
3153
3154 err = patch_generic_hdmi(codec);
3155
3156 if (err)
d0b1252d 3157 return err;
5a613584
AH		 3158
3159 codec->patch_ops.init = atihdmi_init;
3160
d0b1252d 3161 spec = codec->spec;
5a613584 3162
89250f84 3163 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584
AH		 3164 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3165 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3166 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 3167 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 3168 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584
AH		 3169
3170 if (!has_amd_full_remap_support(codec)) {
3171 /* override to ATI/AMD-specific versions with pairwise mapping */
3172 spec->ops.chmap_cea_alloc_validate_get_type =
3173 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3174 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3175 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3176 }
3177
3178 /* ATI/AMD converters do not advertise all of their capabilities */
3179 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3180 per_cvt = get_cvt(spec, cvt_idx);
3181 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3182 per_cvt->rates |= SUPPORTED_RATES;
3183 per_cvt->formats |= SUPPORTED_FORMATS;
3184 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3185 }
3186
3187 spec->channels_max = max(spec->channels_max, 8u);
3188
84eb01be
TI		 3189 return 0;
3190}
3191
3de5ff88
AL		 3192/* VIA HDMI Implementation */
3193#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3194#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3195
3de5ff88
AL		 3196static int patch_via_hdmi(struct hda_codec *codec)
3197{
250e41ac 3198 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3199}
84eb01be 3200
f0639272
TI		 3201/*
3202 * called from hda_codec.c for generic HDMI support
3203 */
3204int snd_hda_parse_hdmi_codec(struct hda_codec *codec)
3205{
3206 return patch_generic_hdmi(codec);
3207}
3208EXPORT_SYMBOL_HDA(snd_hda_parse_hdmi_codec);
3209
84eb01be
TI		 3210/*
3211 * patch entries
3212 */
fb79e1e0 3213static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 3214{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
3215{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
3216{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
5a613584 3217{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
84eb01be
TI		 3218{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
3219{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
3220{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
3221{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3222{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3223{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3224{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3225{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
611885bc
AH		 3226{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
3227{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
3228{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi },
3229{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
3230{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
3231{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
3232{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
3233{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
3234{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
3235{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
3236{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
c8900a0f 3237/* 17 is known to be absent */
611885bc
AH		 3238{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
3239{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
3240{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
3241{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
3242{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
3243{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
3244{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
3245{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
3246{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
3247{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
3248{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
3249{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
84eb01be
TI		 3250{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
3251{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 3252{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3253{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3254{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3255{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 3256{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3257{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
3258{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
3259{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
3260{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3261{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 3262{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 3263{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 3264{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
cc1a95d9 3265{ .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 3266{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
3267{} /* terminator */
3268};
3269
3270MODULE_ALIAS("snd-hda-codec-id:1002793c");
3271MODULE_ALIAS("snd-hda-codec-id:10027919");
3272MODULE_ALIAS("snd-hda-codec-id:1002791a");
3273MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3274MODULE_ALIAS("snd-hda-codec-id:10951390");
3275MODULE_ALIAS("snd-hda-codec-id:10951392");
3276MODULE_ALIAS("snd-hda-codec-id:10de0002");
3277MODULE_ALIAS("snd-hda-codec-id:10de0003");
3278MODULE_ALIAS("snd-hda-codec-id:10de0005");
3279MODULE_ALIAS("snd-hda-codec-id:10de0006");
3280MODULE_ALIAS("snd-hda-codec-id:10de0007");
3281MODULE_ALIAS("snd-hda-codec-id:10de000a");
3282MODULE_ALIAS("snd-hda-codec-id:10de000b");
3283MODULE_ALIAS("snd-hda-codec-id:10de000c");
3284MODULE_ALIAS("snd-hda-codec-id:10de000d");
3285MODULE_ALIAS("snd-hda-codec-id:10de0010");
3286MODULE_ALIAS("snd-hda-codec-id:10de0011");
3287MODULE_ALIAS("snd-hda-codec-id:10de0012");
3288MODULE_ALIAS("snd-hda-codec-id:10de0013");
3289MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 3290MODULE_ALIAS("snd-hda-codec-id:10de0015");
3291MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 3292MODULE_ALIAS("snd-hda-codec-id:10de0018");
3293MODULE_ALIAS("snd-hda-codec-id:10de0019");
3294MODULE_ALIAS("snd-hda-codec-id:10de001a");
3295MODULE_ALIAS("snd-hda-codec-id:10de001b");
3296MODULE_ALIAS("snd-hda-codec-id:10de001c");
3297MODULE_ALIAS("snd-hda-codec-id:10de0040");
3298MODULE_ALIAS("snd-hda-codec-id:10de0041");
3299MODULE_ALIAS("snd-hda-codec-id:10de0042");
3300MODULE_ALIAS("snd-hda-codec-id:10de0043");
3301MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 3302MODULE_ALIAS("snd-hda-codec-id:10de0051");
d52392b1 3303MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 3304MODULE_ALIAS("snd-hda-codec-id:10de0067");
3305MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 3306MODULE_ALIAS("snd-hda-codec-id:11069f80");
3307MODULE_ALIAS("snd-hda-codec-id:11069f81");
3308MODULE_ALIAS("snd-hda-codec-id:11069f84");
3309MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 3310MODULE_ALIAS("snd-hda-codec-id:17e80047");
3311MODULE_ALIAS("snd-hda-codec-id:80860054");
3312MODULE_ALIAS("snd-hda-codec-id:80862801");
3313MODULE_ALIAS("snd-hda-codec-id:80862802");
3314MODULE_ALIAS("snd-hda-codec-id:80862803");
3315MODULE_ALIAS("snd-hda-codec-id:80862804");
3316MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 3317MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 3318MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 3319MODULE_ALIAS("snd-hda-codec-id:80862880");
cc1a95d9 3320MODULE_ALIAS("snd-hda-codec-id:80862882");
84eb01be
TI		 3321MODULE_ALIAS("snd-hda-codec-id:808629fb");
3322
3323MODULE_LICENSE("GPL");
3324MODULE_DESCRIPTION("HDMI HD-audio codec");
3325MODULE_ALIAS("snd-hda-codec-intelhdmi");
3326MODULE_ALIAS("snd-hda-codec-nvhdmi");
3327MODULE_ALIAS("snd-hda-codec-atihdmi");
3328
3329static struct hda_codec_preset_list intel_list = {
3330 .preset = snd_hda_preset_hdmi,
3331 .owner = THIS_MODULE,
3332};
3333
3334static int __init patch_hdmi_init(void)
3335{
3336 return snd_hda_add_codec_preset(&intel_list);
3337}
3338
3339static void __exit patch_hdmi_exit(void)
3340{
3341 snd_hda_delete_codec_preset(&intel_list);
3342}
3343
3344module_init(patch_hdmi_init)
3345module_exit(patch_hdmi_exit)
Ubuntu Artful kernel mirror