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Merge branch 'for-linus' into for-next
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
84eb01be
TI		 40#include "hda_codec.h"
41#include "hda_local.h"
1835a0f9 42#include "hda_jack.h"
84eb01be 43
0ebaa24c
TI		 44static bool static_hdmi_pcm;
45module_param(static_hdmi_pcm, bool, 0644);
46MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
47
fb87fa3a 48#define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
02383854 49#define is_valleyview(codec) ((codec)->vendor_id == 0x80862882)
fb87fa3a 50
384a48d7
SW		 51struct hdmi_spec_per_cvt {
52 hda_nid_t cvt_nid;
53 int assigned;
54 unsigned int channels_min;
55 unsigned int channels_max;
56 u32 rates;
57 u64 formats;
58 unsigned int maxbps;
59};
079d88cc 60
4eea3091
TI		 61/* max. connections to a widget */
62#define HDA_MAX_CONNECTIONS 32
63
384a48d7
SW		 64struct hdmi_spec_per_pin {
65 hda_nid_t pin_nid;
66 int num_mux_nids;
67 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
1df5a06a 68 hda_nid_t cvt_nid;
744626da
WF		 69
70 struct hda_codec *codec;
384a48d7 71 struct hdmi_eld sink_eld;
a4e9a38b 72 struct mutex lock;
744626da 73 struct delayed_work work;
92c69e79 74 struct snd_kcontrol *eld_ctl;
c6e8453e 75 int repoll_count;
b054087d
TI		 76 bool setup; /* the stream has been set up by prepare callback */
77 int channels; /* current number of channels */
1a6003b5 78 bool non_pcm;
d45e6889
TI		 79 bool chmap_set; /* channel-map override by ALSA API? */
80 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 81 char pcm_name[8]; /* filled in build_pcm callbacks */
a4e9a38b
TI		 82#ifdef CONFIG_PROC_FS
83 struct snd_info_entry *proc_entry;
84#endif
384a48d7 85};
079d88cc 86
307229d2
AH		 87struct cea_channel_speaker_allocation;
88
89/* operations used by generic code that can be overridden by patches */
90struct hdmi_ops {
91 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
92 unsigned char *buf, int *eld_size);
93
94 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
95 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
96 int asp_slot);
97 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
98 int asp_slot, int channel);
99
100 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
101 int ca, int active_channels, int conn_type);
102
103 /* enable/disable HBR (HD passthrough) */
104 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
105
106 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
107 hda_nid_t pin_nid, u32 stream_tag, int format);
108
109 /* Helpers for producing the channel map TLVs. These can be overridden
110 * for devices that have non-standard mapping requirements. */
111 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
112 int channels);
113 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
114 unsigned int *chmap, int channels);
115
116 /* check that the user-given chmap is supported */
117 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
118};
119
384a48d7
SW		 120struct hdmi_spec {
121 int num_cvts;
bce0d2a8
TI		 122 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
123 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 124
384a48d7 125 int num_pins;
bce0d2a8
TI		 126 struct snd_array pins; /* struct hdmi_spec_per_pin */
127 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 128 unsigned int channels_max; /* max over all cvts */
079d88cc 129
4bd038f9 130 struct hdmi_eld temp_eld;
307229d2 131 struct hdmi_ops ops;
079d88cc 132 /*
5a613584 133 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 134 */
135 struct hda_multi_out multiout;
d0b1252d 136 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 137};
138
139
140struct hdmi_audio_infoframe {
141 u8 type; /* 0x84 */
142 u8 ver; /* 0x01 */
143 u8 len; /* 0x0a */
144
53d7d69d
WF		 145 u8 checksum;
146
079d88cc
WF		 147 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
148 u8 SS01_SF24;
149 u8 CXT04;
150 u8 CA;
151 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 152};
153
154struct dp_audio_infoframe {
155 u8 type; /* 0x84 */
156 u8 len; /* 0x1b */
157 u8 ver; /* 0x11 << 2 */
158
159 u8 CC02_CT47; /* match with HDMI infoframe from this on */
160 u8 SS01_SF24;
161 u8 CXT04;
162 u8 CA;
163 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 164};
165
2b203dbb
TI		 166union audio_infoframe {
167 struct hdmi_audio_infoframe hdmi;
168 struct dp_audio_infoframe dp;
169 u8 bytes[0];
170};
171
079d88cc
WF		 172/*
173 * CEA speaker placement:
174 *
175 * FLH FCH FRH
176 * FLW FL FLC FC FRC FR FRW
177 *
178 * LFE
179 * TC
180 *
181 * RL RLC RC RRC RR
182 *
183 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
184 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
185 */
186enum cea_speaker_placement {
187 FL = (1 << 0), /* Front Left */
188 FC = (1 << 1), /* Front Center */
189 FR = (1 << 2), /* Front Right */
190 FLC = (1 << 3), /* Front Left Center */
191 FRC = (1 << 4), /* Front Right Center */
192 RL = (1 << 5), /* Rear Left */
193 RC = (1 << 6), /* Rear Center */
194 RR = (1 << 7), /* Rear Right */
195 RLC = (1 << 8), /* Rear Left Center */
196 RRC = (1 << 9), /* Rear Right Center */
197 LFE = (1 << 10), /* Low Frequency Effect */
198 FLW = (1 << 11), /* Front Left Wide */
199 FRW = (1 << 12), /* Front Right Wide */
200 FLH = (1 << 13), /* Front Left High */
201 FCH = (1 << 14), /* Front Center High */
202 FRH = (1 << 15), /* Front Right High */
203 TC = (1 << 16), /* Top Center */
204};
205
206/*
207 * ELD SA bits in the CEA Speaker Allocation data block
208 */
209static int eld_speaker_allocation_bits[] = {
210 [0] = FL | FR,
211 [1] = LFE,
212 [2] = FC,
213 [3] = RL | RR,
214 [4] = RC,
215 [5] = FLC | FRC,
216 [6] = RLC | RRC,
217 /* the following are not defined in ELD yet */
218 [7] = FLW | FRW,
219 [8] = FLH | FRH,
220 [9] = TC,
221 [10] = FCH,
222};
223
224struct cea_channel_speaker_allocation {
225 int ca_index;
226 int speakers[8];
227
228 /* derived values, just for convenience */
229 int channels;
230 int spk_mask;
231};
232
233/*
234 * ALSA sequence is:
235 *
236 * surround40 surround41 surround50 surround51 surround71
237 * ch0 front left = = = =
238 * ch1 front right = = = =
239 * ch2 rear left = = = =
240 * ch3 rear right = = = =
241 * ch4 LFE center center center
242 * ch5 LFE LFE
243 * ch6 side left
244 * ch7 side right
245 *
246 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
247 */
248static int hdmi_channel_mapping[0x32][8] = {
249 /* stereo */
250 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
251 /* 2.1 */
252 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
253 /* Dolby Surround */
254 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
255 /* surround40 */
256 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
257 /* 4ch */
258 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
259 /* surround41 */
9396d317 260 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 261 /* surround50 */
262 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
263 /* surround51 */
264 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
265 /* 7.1 */
266 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
267};
268
269/*
270 * This is an ordered list!
271 *
272 * The preceding ones have better chances to be selected by
53d7d69d 273 * hdmi_channel_allocation().
079d88cc
WF		 274 */
275static struct cea_channel_speaker_allocation channel_allocations[] = {
276/* channel: 7 6 5 4 3 2 1 0 */
277{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
278 /* 2.1 */
279{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
280 /* Dolby Surround */
281{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
282 /* surround40 */
283{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
284 /* surround41 */
285{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
286 /* surround50 */
287{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
288 /* surround51 */
289{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
290 /* 6.1 */
291{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
292 /* surround71 */
293{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
294
295{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
296{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
297{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
298{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
299{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
300{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
301{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
302{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
303{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
304{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
305{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
306{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
307{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
308{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
309{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
310{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
311{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
312{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
313{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
314{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
315{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
316{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
317{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
318{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
319{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
320{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
321{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
322{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
323{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
324{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
325{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
326{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
327{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
328{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
329{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
330{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
331{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
332{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
333{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
334{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
335{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
336};
337
338
339/*
340 * HDMI routines
341 */
342
bce0d2a8
TI		 343#define get_pin(spec, idx) \
344 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
345#define get_cvt(spec, idx) \
346 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
347#define get_pcm_rec(spec, idx) \
348 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
349
384a48d7 350static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 351{
384a48d7 352 int pin_idx;
079d88cc 353
384a48d7 354 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 355 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 356 return pin_idx;
079d88cc 357
384a48d7
SW		 358 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
359 return -EINVAL;
360}
361
362static int hinfo_to_pin_index(struct hdmi_spec *spec,
363 struct hda_pcm_stream *hinfo)
364{
365 int pin_idx;
366
367 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 368 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 369 return pin_idx;
370
371 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
372 return -EINVAL;
373}
374
375static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
376{
377 int cvt_idx;
378
379 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 380 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 381 return cvt_idx;
382
383 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 384 return -EINVAL;
385}
386
14bc52b8
PLB		 387static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
388 struct snd_ctl_elem_info *uinfo)
389{
390 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 391 struct hdmi_spec *spec = codec->spec;
a4e9a38b 392 struct hdmi_spec_per_pin *per_pin;
68e03de9 393 struct hdmi_eld *eld;
14bc52b8
PLB		 394 int pin_idx;
395
14bc52b8
PLB		 396 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
397
398 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 399 per_pin = get_pin(spec, pin_idx);
400 eld = &per_pin->sink_eld;
68e03de9 401
a4e9a38b 402 mutex_lock(&per_pin->lock);
68e03de9 403 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
a4e9a38b 404 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 405
406 return 0;
407}
408
409static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
410 struct snd_ctl_elem_value *ucontrol)
411{
412 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 413 struct hdmi_spec *spec = codec->spec;
a4e9a38b 414 struct hdmi_spec_per_pin *per_pin;
68e03de9 415 struct hdmi_eld *eld;
14bc52b8
PLB		 416 int pin_idx;
417
14bc52b8 418 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 419 per_pin = get_pin(spec, pin_idx);
420 eld = &per_pin->sink_eld;
68e03de9 421
a4e9a38b 422 mutex_lock(&per_pin->lock);
68e03de9 423 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
a4e9a38b 424 mutex_unlock(&per_pin->lock);
68e03de9
DH		 425 snd_BUG();
426 return -EINVAL;
427 }
428
429 memset(ucontrol->value.bytes.data, 0,
430 ARRAY_SIZE(ucontrol->value.bytes.data));
431 if (eld->eld_valid)
432 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
433 eld->eld_size);
a4e9a38b 434 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 435
436 return 0;
437}
438
439static struct snd_kcontrol_new eld_bytes_ctl = {
440 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
441 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
442 .name = "ELD",
443 .info = hdmi_eld_ctl_info,
444 .get = hdmi_eld_ctl_get,
445};
446
447static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
448 int device)
449{
450 struct snd_kcontrol *kctl;
451 struct hdmi_spec *spec = codec->spec;
452 int err;
453
454 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
455 if (!kctl)
456 return -ENOMEM;
457 kctl->private_value = pin_idx;
458 kctl->id.device = device;
459
bce0d2a8 460 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 461 if (err < 0)
462 return err;
463
bce0d2a8 464 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 465 return 0;
466}
467
079d88cc
WF		 468#ifdef BE_PARANOID
469static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
470 int *packet_index, int *byte_index)
471{
472 int val;
473
474 val = snd_hda_codec_read(codec, pin_nid, 0,
475 AC_VERB_GET_HDMI_DIP_INDEX, 0);
476
477 *packet_index = val >> 5;
478 *byte_index = val & 0x1f;
479}
480#endif
481
482static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
483 int packet_index, int byte_index)
484{
485 int val;
486
487 val = (packet_index << 5) | (byte_index & 0x1f);
488
489 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
490}
491
492static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
493 unsigned char val)
494{
495 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
496}
497
384a48d7 498static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 499{
500 /* Unmute */
501 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
502 snd_hda_codec_write(codec, pin_nid, 0,
503 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 504 /* Enable pin out: some machines with GM965 gets broken output when
505 * the pin is disabled or changed while using with HDMI
506 */
079d88cc 507 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 508 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 509}
510
384a48d7 511static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 512{
384a48d7 513 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 514 AC_VERB_GET_CVT_CHAN_COUNT, 0);
515}
516
517static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 518 hda_nid_t cvt_nid, int chs)
079d88cc 519{
384a48d7
SW		 520 if (chs != hdmi_get_channel_count(codec, cvt_nid))
521 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 522 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
523}
524
a4e9a38b
TI		 525/*
526 * ELD proc files
527 */
528
529#ifdef CONFIG_PROC_FS
530static void print_eld_info(struct snd_info_entry *entry,
531 struct snd_info_buffer *buffer)
532{
533 struct hdmi_spec_per_pin *per_pin = entry->private_data;
534
535 mutex_lock(&per_pin->lock);
536 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
537 mutex_unlock(&per_pin->lock);
538}
539
540static void write_eld_info(struct snd_info_entry *entry,
541 struct snd_info_buffer *buffer)
542{
543 struct hdmi_spec_per_pin *per_pin = entry->private_data;
544
545 mutex_lock(&per_pin->lock);
546 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
547 mutex_unlock(&per_pin->lock);
548}
549
550static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
551{
552 char name[32];
553 struct hda_codec *codec = per_pin->codec;
554 struct snd_info_entry *entry;
555 int err;
556
557 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
558 err = snd_card_proc_new(codec->bus->card, name, &entry);
559 if (err < 0)
560 return err;
561
562 snd_info_set_text_ops(entry, per_pin, print_eld_info);
563 entry->c.text.write = write_eld_info;
564 entry->mode |= S_IWUSR;
565 per_pin->proc_entry = entry;
566
567 return 0;
568}
569
570static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
571{
572 if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) {
573 snd_device_free(per_pin->codec->bus->card, per_pin->proc_entry);
574 per_pin->proc_entry = NULL;
575 }
576}
577#else
b55447a7
TI		 578static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
579 int index)
a4e9a38b
TI		 580{
581 return 0;
582}
b55447a7 583static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 584{
585}
586#endif
079d88cc
WF		 587
588/*
589 * Channel mapping routines
590 */
591
592/*
593 * Compute derived values in channel_allocations[].
594 */
595static void init_channel_allocations(void)
596{
597 int i, j;
598 struct cea_channel_speaker_allocation *p;
599
600 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
601 p = channel_allocations + i;
602 p->channels = 0;
603 p->spk_mask = 0;
604 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
605 if (p->speakers[j]) {
606 p->channels++;
607 p->spk_mask |= p->speakers[j];
608 }
609 }
610}
611
72357c78
WX		 612static int get_channel_allocation_order(int ca)
613{
614 int i;
615
616 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
617 if (channel_allocations[i].ca_index == ca)
618 break;
619 }
620 return i;
621}
622
079d88cc
WF		 623/*
624 * The transformation takes two steps:
625 *
626 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
627 * spk_mask => (channel_allocations[]) => ai->CA
628 *
629 * TODO: it could select the wrong CA from multiple candidates.
630*/
384a48d7 631static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 632{
079d88cc 633 int i;
53d7d69d 634 int ca = 0;
079d88cc 635 int spk_mask = 0;
079d88cc
WF		 636 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
637
638 /*
639 * CA defaults to 0 for basic stereo audio
640 */
641 if (channels <= 2)
642 return 0;
643
079d88cc
WF		 644 /*
645 * expand ELD's speaker allocation mask
646 *
647 * ELD tells the speaker mask in a compact(paired) form,
648 * expand ELD's notions to match the ones used by Audio InfoFrame.
649 */
650 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 651 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 652 spk_mask |= eld_speaker_allocation_bits[i];
653 }
654
655 /* search for the first working match in the CA table */
656 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
657 if (channels == channel_allocations[i].channels &&
658 (spk_mask & channel_allocations[i].spk_mask) ==
659 channel_allocations[i].spk_mask) {
53d7d69d 660 ca = channel_allocations[i].ca_index;
079d88cc
WF		 661 break;
662 }
663 }
664
18e39186
AH		 665 if (!ca) {
666 /* if there was no match, select the regular ALSA channel
667 * allocation with the matching number of channels */
668 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
669 if (channels == channel_allocations[i].channels) {
670 ca = channel_allocations[i].ca_index;
671 break;
672 }
673 }
674 }
675
1613d6b4 676 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 677 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 678 ca, channels, buf);
079d88cc 679
53d7d69d 680 return ca;
079d88cc
WF		 681}
682
683static void hdmi_debug_channel_mapping(struct hda_codec *codec,
684 hda_nid_t pin_nid)
685{
686#ifdef CONFIG_SND_DEBUG_VERBOSE
307229d2 687 struct hdmi_spec *spec = codec->spec;
079d88cc 688 int i;
307229d2 689 int channel;
079d88cc
WF		 690
691 for (i = 0; i < 8; i++) {
307229d2 692 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
079d88cc 693 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
307229d2 694 channel, i);
079d88cc
WF		 695 }
696#endif
697}
698
d45e6889 699static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 700 hda_nid_t pin_nid,
433968da 701 bool non_pcm,
53d7d69d 702 int ca)
079d88cc 703{
307229d2 704 struct hdmi_spec *spec = codec->spec;
90f28002 705 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 706 int i;
079d88cc 707 int err;
72357c78 708 int order;
433968da 709 int non_pcm_mapping[8];
079d88cc 710
72357c78 711 order = get_channel_allocation_order(ca);
90f28002 712 ch_alloc = &channel_allocations[order];
433968da 713
079d88cc 714 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 715 int hdmi_slot = 0;
716 /* fill actual channel mappings in ALSA channel (i) order */
717 for (i = 0; i < ch_alloc->channels; i++) {
718 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
719 hdmi_slot++; /* skip zero slots */
720
721 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
722 }
723 /* fill the rest of the slots with ALSA channel 0xf */
724 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
725 if (!ch_alloc->speakers[7 - hdmi_slot])
726 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 727 }
728
433968da 729 if (non_pcm) {
90f28002 730 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 731 non_pcm_mapping[i] = (i << 4) | i;
433968da 732 for (; i < 8; i++)
11f7c52d 733 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 734 }
735
079d88cc 736 for (i = 0; i < 8; i++) {
307229d2
AH		 737 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
738 int hdmi_slot = slotsetup & 0x0f;
739 int channel = (slotsetup & 0xf0) >> 4;
740 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
079d88cc 741 if (err) {
2abbf439
WF		 742 snd_printdd(KERN_NOTICE
743 "HDMI: channel mapping failed\n");
079d88cc
WF		 744 break;
745 }
746 }
079d88cc
WF		 747}
748
d45e6889
TI		 749struct channel_map_table {
750 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 751 int spk_mask; /* speaker position bit mask */
752};
753
754static struct channel_map_table map_tables[] = {
a5b7d510
AH		 755 { SNDRV_CHMAP_FL, FL },
756 { SNDRV_CHMAP_FR, FR },
757 { SNDRV_CHMAP_RL, RL },
758 { SNDRV_CHMAP_RR, RR },
759 { SNDRV_CHMAP_LFE, LFE },
760 { SNDRV_CHMAP_FC, FC },
761 { SNDRV_CHMAP_RLC, RLC },
762 { SNDRV_CHMAP_RRC, RRC },
763 { SNDRV_CHMAP_RC, RC },
764 { SNDRV_CHMAP_FLC, FLC },
765 { SNDRV_CHMAP_FRC, FRC },
766 { SNDRV_CHMAP_FLH, FLH },
767 { SNDRV_CHMAP_FRH, FRH },
768 { SNDRV_CHMAP_FLW, FLW },
769 { SNDRV_CHMAP_FRW, FRW },
770 { SNDRV_CHMAP_TC, TC },
771 { SNDRV_CHMAP_FCH, FCH },
d45e6889
TI		 772 {} /* terminator */
773};
774
775/* from ALSA API channel position to speaker bit mask */
776static int to_spk_mask(unsigned char c)
777{
778 struct channel_map_table *t = map_tables;
779 for (; t->map; t++) {
780 if (t->map == c)
781 return t->spk_mask;
782 }
783 return 0;
784}
785
786/* from ALSA API channel position to CEA slot */
a5b7d510 787static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 788{
a5b7d510
AH		 789 int mask = to_spk_mask(pos);
790 int i;
d45e6889 791
a5b7d510
AH		 792 if (mask) {
793 for (i = 0; i < 8; i++) {
794 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
795 return i;
796 }
d45e6889 797 }
a5b7d510
AH		 798
799 return -1;
d45e6889
TI		 800}
801
802/* from speaker bit mask to ALSA API channel position */
803static int spk_to_chmap(int spk)
804{
805 struct channel_map_table *t = map_tables;
806 for (; t->map; t++) {
807 if (t->spk_mask == spk)
808 return t->map;
809 }
810 return 0;
811}
812
a5b7d510
AH		 813/* from CEA slot to ALSA API channel position */
814static int from_cea_slot(int ordered_ca, unsigned char slot)
815{
816 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
817
818 return spk_to_chmap(mask);
819}
820
d45e6889
TI		 821/* get the CA index corresponding to the given ALSA API channel map */
822static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
823{
824 int i, spks = 0, spk_mask = 0;
825
826 for (i = 0; i < chs; i++) {
827 int mask = to_spk_mask(map[i]);
828 if (mask) {
829 spk_mask |= mask;
830 spks++;
831 }
832 }
833
834 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
835 if ((chs == channel_allocations[i].channels ||
836 spks == channel_allocations[i].channels) &&
837 (spk_mask & channel_allocations[i].spk_mask) ==
838 channel_allocations[i].spk_mask)
839 return channel_allocations[i].ca_index;
840 }
841 return -1;
842}
843
844/* set up the channel slots for the given ALSA API channel map */
845static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
846 hda_nid_t pin_nid,
a5b7d510
AH		 847 int chs, unsigned char *map,
848 int ca)
d45e6889 849{
307229d2 850 struct hdmi_spec *spec = codec->spec;
a5b7d510 851 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 852 int alsa_pos, hdmi_slot;
853 int assignments[8] = {[0 ... 7] = 0xf};
854
855 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
856
a5b7d510 857 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 858
859 if (hdmi_slot < 0)
860 continue; /* unassigned channel */
861
862 assignments[hdmi_slot] = alsa_pos;
863 }
864
865 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
307229d2 866 int err;
11f7c52d 867
307229d2
AH		 868 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
869 assignments[hdmi_slot]);
d45e6889
TI		 870 if (err)
871 return -EINVAL;
872 }
873 return 0;
874}
875
876/* store ALSA API channel map from the current default map */
877static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
878{
879 int i;
56cac413 880 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 881 for (i = 0; i < 8; i++) {
56cac413 882 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 883 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 884 else
885 map[i] = 0;
886 }
887}
888
889static void hdmi_setup_channel_mapping(struct hda_codec *codec,
890 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 891 int channels, unsigned char *map,
892 bool chmap_set)
d45e6889 893{
20608731 894 if (!non_pcm && chmap_set) {
d45e6889 895 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 896 channels, map, ca);
d45e6889
TI		 897 } else {
898 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
899 hdmi_setup_fake_chmap(map, ca);
900 }
980b2495
AH		 901
902 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 903}
079d88cc 904
307229d2
AH		 905static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
906 int asp_slot, int channel)
907{
908 return snd_hda_codec_write(codec, pin_nid, 0,
909 AC_VERB_SET_HDMI_CHAN_SLOT,
910 (channel << 4) | asp_slot);
911}
912
913static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
914 int asp_slot)
915{
916 return (snd_hda_codec_read(codec, pin_nid, 0,
917 AC_VERB_GET_HDMI_CHAN_SLOT,
918 asp_slot) & 0xf0) >> 4;
919}
920
079d88cc
WF		 921/*
922 * Audio InfoFrame routines
923 */
924
925/*
926 * Enable Audio InfoFrame Transmission
927 */
928static void hdmi_start_infoframe_trans(struct hda_codec *codec,
929 hda_nid_t pin_nid)
930{
931 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
932 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
933 AC_DIPXMIT_BEST);
934}
935
936/*
937 * Disable Audio InfoFrame Transmission
938 */
939static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
940 hda_nid_t pin_nid)
941{
942 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
943 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
944 AC_DIPXMIT_DISABLE);
945}
946
947static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
948{
949#ifdef CONFIG_SND_DEBUG_VERBOSE
950 int i;
951 int size;
952
953 size = snd_hdmi_get_eld_size(codec, pin_nid);
954 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
955
956 for (i = 0; i < 8; i++) {
957 size = snd_hda_codec_read(codec, pin_nid, 0,
958 AC_VERB_GET_HDMI_DIP_SIZE, i);
959 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
960 }
961#endif
962}
963
964static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
965{
966#ifdef BE_PARANOID
967 int i, j;
968 int size;
969 int pi, bi;
970 for (i = 0; i < 8; i++) {
971 size = snd_hda_codec_read(codec, pin_nid, 0,
972 AC_VERB_GET_HDMI_DIP_SIZE, i);
973 if (size == 0)
974 continue;
975
976 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
977 for (j = 1; j < 1000; j++) {
978 hdmi_write_dip_byte(codec, pin_nid, 0x0);
979 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
980 if (pi != i)
981 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
982 bi, pi, i);
983 if (bi == 0) /* byte index wrapped around */
984 break;
985 }
986 snd_printd(KERN_INFO
987 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
988 i, size, j);
989 }
990#endif
991}
992
53d7d69d 993static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 994{
53d7d69d 995 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 996 u8 sum = 0;
997 int i;
998
53d7d69d 999 hdmi_ai->checksum = 0;
079d88cc 1000
53d7d69d 1001 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 1002 sum += bytes[i];
1003
53d7d69d 1004 hdmi_ai->checksum = -sum;
079d88cc
WF		 1005}
1006
1007static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1008 hda_nid_t pin_nid,
53d7d69d 1009 u8 *dip, int size)
079d88cc 1010{
079d88cc
WF		 1011 int i;
1012
1013 hdmi_debug_dip_size(codec, pin_nid);
1014 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1015
079d88cc 1016 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 1017 for (i = 0; i < size; i++)
1018 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 1019}
1020
1021static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 1022 u8 *dip, int size)
079d88cc 1023{
079d88cc
WF		 1024 u8 val;
1025 int i;
1026
1027 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1028 != AC_DIPXMIT_BEST)
1029 return false;
1030
1031 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 1032 for (i = 0; i < size; i++) {
079d88cc
WF		 1033 val = snd_hda_codec_read(codec, pin_nid, 0,
1034 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 1035 if (val != dip[i])
079d88cc
WF		 1036 return false;
1037 }
1038
1039 return true;
1040}
1041
307229d2
AH		 1042static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1043 hda_nid_t pin_nid,
1044 int ca, int active_channels,
1045 int conn_type)
1046{
1047 union audio_infoframe ai;
1048
1049 if (conn_type == 0) { /* HDMI */
1050 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1051
1052 hdmi_ai->type = 0x84;
1053 hdmi_ai->ver = 0x01;
1054 hdmi_ai->len = 0x0a;
1055 hdmi_ai->CC02_CT47 = active_channels - 1;
1056 hdmi_ai->CA = ca;
1057 hdmi_checksum_audio_infoframe(hdmi_ai);
1058 } else if (conn_type == 1) { /* DisplayPort */
1059 struct dp_audio_infoframe *dp_ai = &ai.dp;
1060
1061 dp_ai->type = 0x84;
1062 dp_ai->len = 0x1b;
1063 dp_ai->ver = 0x11 << 2;
1064 dp_ai->CC02_CT47 = active_channels - 1;
1065 dp_ai->CA = ca;
1066 } else {
1067 snd_printd("HDMI: unknown connection type at pin %d\n",
1068 pin_nid);
1069 return;
1070 }
1071
1072 /*
1073 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1074 * sizeof(*dp_ai) to avoid partial match/update problems when
1075 * the user switches between HDMI/DP monitors.
1076 */
1077 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1078 sizeof(ai))) {
1079 snd_printdd("hdmi_pin_setup_infoframe: "
1080 "pin=%d channels=%d ca=0x%02x\n",
1081 pin_nid,
1082 active_channels, ca);
1083 hdmi_stop_infoframe_trans(codec, pin_nid);
1084 hdmi_fill_audio_infoframe(codec, pin_nid,
1085 ai.bytes, sizeof(ai));
1086 hdmi_start_infoframe_trans(codec, pin_nid);
1087 }
1088}
1089
b054087d
TI		 1090static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1091 struct hdmi_spec_per_pin *per_pin,
1092 bool non_pcm)
079d88cc 1093{
307229d2 1094 struct hdmi_spec *spec = codec->spec;
384a48d7 1095 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 1096 int channels = per_pin->channels;
1df5a06a 1097 int active_channels;
384a48d7 1098 struct hdmi_eld *eld;
1df5a06a 1099 int ca, ordered_ca;
079d88cc 1100
b054087d
TI		 1101 if (!channels)
1102 return;
1103
58f7d28d
ML		 1104 if (is_haswell(codec))
1105 snd_hda_codec_write(codec, pin_nid, 0,
1106 AC_VERB_SET_AMP_GAIN_MUTE,
1107 AMP_OUT_UNMUTE);
1108
bce0d2a8 1109 eld = &per_pin->sink_eld;
384a48d7
SW		 1110 if (!eld->monitor_present)
1111 return;
079d88cc 1112
d45e6889
TI		 1113 if (!non_pcm && per_pin->chmap_set)
1114 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1115 else
1116 ca = hdmi_channel_allocation(eld, channels);
1117 if (ca < 0)
1118 ca = 0;
384a48d7 1119
1df5a06a
AH		 1120 ordered_ca = get_channel_allocation_order(ca);
1121 active_channels = channel_allocations[ordered_ca].channels;
1122
1123 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1124
39edac70
AH		 1125 /*
1126 * always configure channel mapping, it may have been changed by the
1127 * user in the meantime
1128 */
1129 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1130 channels, per_pin->chmap,
1131 per_pin->chmap_set);
1132
307229d2
AH		 1133 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1134 eld->info.conn_type);
433968da 1135
1a6003b5 1136 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1137}
1138
079d88cc
WF		 1139/*
1140 * Unsolicited events
1141 */
1142
c6e8453e 1143static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1144
079d88cc
WF		 1145static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1146{
1147 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 1148 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1149 int pin_nid;
384a48d7 1150 int pin_idx;
3a93897e 1151 struct hda_jack_tbl *jack;
2e59e5ab 1152 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1153
1154 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1155 if (!jack)
1156 return;
1157 pin_nid = jack->nid;
1158 jack->jack_dirty = 1;
079d88cc 1159
fae3d88a 1160 _snd_printd(SND_PR_VERBOSE,
2e59e5ab
ML		 1161 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1162 codec->addr, pin_nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1163 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1164
384a48d7
SW		 1165 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
1166 if (pin_idx < 0)
079d88cc
WF		 1167 return;
1168
bce0d2a8 1169 hdmi_present_sense(get_pin(spec, pin_idx), 1);
01a61e12 1170 snd_hda_jack_report_sync(codec);
079d88cc
WF		 1171}
1172
1173static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1174{
1175 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1176 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1177 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1178 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1179
1180 printk(KERN_INFO
e9ea8e8f 1181 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1182 codec->addr,
079d88cc
WF		 1183 tag,
1184 subtag,
1185 cp_state,
1186 cp_ready);
1187
1188 /* TODO */
1189 if (cp_state)
1190 ;
1191 if (cp_ready)
1192 ;
1193}
1194
1195
1196static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1197{
079d88cc
WF		 1198 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1199 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1200
3a93897e 1201 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 1202 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
1203 return;
1204 }
1205
1206 if (subtag == 0)
1207 hdmi_intrinsic_event(codec, res);
1208 else
1209 hdmi_non_intrinsic_event(codec, res);
1210}
1211
58f7d28d 1212static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1213 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1214{
58f7d28d 1215 int pwr;
83f26ad2 1216
53b434f0
WX		 1217 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1218 * thus pins could only choose converter 0 for use. Make sure the
1219 * converters are in correct power state */
fd678cac 1220 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1221 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1222
fd678cac 1223 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1224 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1225 AC_PWRST_D0);
1226 msleep(40);
1227 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1228 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1229 snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1230 }
83f26ad2
DH		 1231}
1232
079d88cc
WF		 1233/*
1234 * Callbacks
1235 */
1236
92f10b3f
TI		 1237/* HBR should be Non-PCM, 8 channels */
1238#define is_hbr_format(format) \
1239 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1240
307229d2
AH		 1241static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1242 bool hbr)
079d88cc 1243{
307229d2 1244 int pinctl, new_pinctl;
83f26ad2 1245
384a48d7
SW		 1246 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1247 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1248 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1249
1250 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 1251 if (hbr)
ea87d1c4
AH		 1252 new_pinctl |= AC_PINCTL_EPT_HBR;
1253 else
1254 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1255
307229d2 1256 snd_printdd("hdmi_pin_hbr_setup: "
ea87d1c4 1257 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1258 pin_nid,
ea87d1c4
AH		 1259 pinctl == new_pinctl ? "" : "new-",
1260 new_pinctl);
1261
1262 if (pinctl != new_pinctl)
384a48d7 1263 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1264 AC_VERB_SET_PIN_WIDGET_CONTROL,
1265 new_pinctl);
307229d2
AH		 1266 } else if (hbr)
1267 return -EINVAL;
ea87d1c4 1268
307229d2
AH		 1269 return 0;
1270}
1271
1272static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1273 hda_nid_t pin_nid, u32 stream_tag, int format)
1274{
1275 struct hdmi_spec *spec = codec->spec;
1276 int err;
1277
1278 if (is_haswell(codec))
1279 haswell_verify_D0(codec, cvt_nid, pin_nid);
1280
1281 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1282
1283 if (err) {
ea87d1c4 1284 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
307229d2 1285 return err;
ea87d1c4 1286 }
079d88cc 1287
384a48d7 1288 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1289 return 0;
079d88cc
WF		 1290}
1291
7ef166b8
WX		 1292static int hdmi_choose_cvt(struct hda_codec *codec,
1293 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1294{
1295 struct hdmi_spec *spec = codec->spec;
384a48d7 1296 struct hdmi_spec_per_pin *per_pin;
384a48d7 1297 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1298 int cvt_idx, mux_idx = 0;
bbbe3390 1299
bce0d2a8 1300 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1301
1302 /* Dynamically assign converter to stream */
1303 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1304 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1305
384a48d7
SW		 1306 /* Must not already be assigned */
1307 if (per_cvt->assigned)
1308 continue;
1309 /* Must be in pin's mux's list of converters */
1310 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1311 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1312 break;
1313 /* Not in mux list */
1314 if (mux_idx == per_pin->num_mux_nids)
1315 continue;
1316 break;
1317 }
7ef166b8 1318
384a48d7
SW		 1319 /* No free converters */
1320 if (cvt_idx == spec->num_cvts)
1321 return -ENODEV;
1322
7ef166b8
WX		 1323 if (cvt_id)
1324 *cvt_id = cvt_idx;
1325 if (mux_id)
1326 *mux_id = mux_idx;
1327
1328 return 0;
1329}
1330
02383854 1331static void not_share_unassigned_cvt(struct hda_codec *codec,
f82d7d16 1332 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1333{
1334 struct hdmi_spec *spec = codec->spec;
f82d7d16
ML		 1335 hda_nid_t nid, end_nid;
1336 int cvt_idx, curr;
1337 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1338
f82d7d16
ML		 1339 /* configure all pins, including "no physical connection" ones */
1340 end_nid = codec->start_nid + codec->num_nodes;
1341 for (nid = codec->start_nid; nid < end_nid; nid++) {
1342 unsigned int wid_caps = get_wcaps(codec, nid);
1343 unsigned int wid_type = get_wcaps_type(wid_caps);
1344
1345 if (wid_type != AC_WID_PIN)
1346 continue;
7ef166b8 1347
f82d7d16 1348 if (nid == pin_nid)
7ef166b8
WX		 1349 continue;
1350
f82d7d16 1351 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1352 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1353 if (curr != mux_idx)
1354 continue;
7ef166b8 1355
f82d7d16
ML		 1356 /* choose an unassigned converter. The conveters in the
1357 * connection list are in the same order as in the codec.
1358 */
1359 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1360 per_cvt = get_cvt(spec, cvt_idx);
1361 if (!per_cvt->assigned) {
1362 snd_printdd("choose cvt %d for pin nid %d\n",
1363 cvt_idx, nid);
1364 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1365 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1366 cvt_idx);
1367 break;
1368 }
7ef166b8
WX		 1369 }
1370 }
1371}
1372
1373/*
1374 * HDA PCM callbacks
1375 */
1376static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1377 struct hda_codec *codec,
1378 struct snd_pcm_substream *substream)
1379{
1380 struct hdmi_spec *spec = codec->spec;
1381 struct snd_pcm_runtime *runtime = substream->runtime;
1382 int pin_idx, cvt_idx, mux_idx = 0;
1383 struct hdmi_spec_per_pin *per_pin;
1384 struct hdmi_eld *eld;
1385 struct hdmi_spec_per_cvt *per_cvt = NULL;
1386 int err;
1387
1388 /* Validate hinfo */
1389 pin_idx = hinfo_to_pin_index(spec, hinfo);
1390 if (snd_BUG_ON(pin_idx < 0))
1391 return -EINVAL;
1392 per_pin = get_pin(spec, pin_idx);
1393 eld = &per_pin->sink_eld;
1394
1395 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1396 if (err < 0)
1397 return err;
1398
1399 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1400 /* Claim converter */
1401 per_cvt->assigned = 1;
1df5a06a 1402 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1403 hinfo->nid = per_cvt->cvt_nid;
1404
bddee96b 1405 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1406 AC_VERB_SET_CONNECT_SEL,
1407 mux_idx);
7ef166b8
WX		 1408
1409 /* configure unused pins to choose other converters */
02383854
ML		 1410 if (is_haswell(codec) || is_valleyview(codec))
1411 not_share_unassigned_cvt(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1412
384a48d7 1413 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1414
2def8172 1415 /* Initially set the converter's capabilities */
384a48d7
SW		 1416 hinfo->channels_min = per_cvt->channels_min;
1417 hinfo->channels_max = per_cvt->channels_max;
1418 hinfo->rates = per_cvt->rates;
1419 hinfo->formats = per_cvt->formats;
1420 hinfo->maxbps = per_cvt->maxbps;
2def8172 1421
384a48d7 1422 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1423 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1424 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1425 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1426 !hinfo->rates || !hinfo->formats) {
1427 per_cvt->assigned = 0;
1428 hinfo->nid = 0;
1429 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1430 return -ENODEV;
2ad779b7 1431 }
bbbe3390 1432 }
2def8172
SW		 1433
1434 /* Store the updated parameters */
639cef0e
TI		 1435 runtime->hw.channels_min = hinfo->channels_min;
1436 runtime->hw.channels_max = hinfo->channels_max;
1437 runtime->hw.formats = hinfo->formats;
1438 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1439
1440 snd_pcm_hw_constraint_step(substream->runtime, 0,
1441 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1442 return 0;
1443}
1444
079d88cc
WF		 1445/*
1446 * HDA/HDMI auto parsing
1447 */
384a48d7 1448static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1449{
1450 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1451 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1452 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1453
1454 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1455 snd_printk(KERN_WARNING
1456 "HDMI: pin %d wcaps %#x "
1457 "does not support connection list\n",
1458 pin_nid, get_wcaps(codec, pin_nid));
1459 return -EINVAL;
1460 }
1461
384a48d7
SW		 1462 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1463 per_pin->mux_nids,
1464 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1465
1466 return 0;
1467}
1468
c6e8453e 1469static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1470{
744626da 1471 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1472 struct hdmi_spec *spec = codec->spec;
1473 struct hdmi_eld *eld = &spec->temp_eld;
1474 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1475 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1476 /*
1477 * Always execute a GetPinSense verb here, even when called from
1478 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1479 * response's PD bit is not the real PD value, but indicates that
1480 * the real PD value changed. An older version of the HD-audio
1481 * specification worked this way. Hence, we just ignore the data in
1482 * the unsolicited response to avoid custom WARs.
1483 */
079d88cc 1484 int present = snd_hda_pin_sense(codec, pin_nid);
4bd038f9
DH		 1485 bool update_eld = false;
1486 bool eld_changed = false;
079d88cc 1487
a4e9a38b 1488 mutex_lock(&per_pin->lock);
4bd038f9
DH		 1489 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1490 if (pin_eld->monitor_present)
1491 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1492 else
1493 eld->eld_valid = false;
079d88cc 1494
fae3d88a 1495 _snd_printd(SND_PR_VERBOSE,
384a48d7 1496 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1497 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1498
4bd038f9 1499 if (eld->eld_valid) {
307229d2 1500 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1501 &eld->eld_size) < 0)
4bd038f9 1502 eld->eld_valid = false;
1613d6b4
DH		 1503 else {
1504 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1505 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1506 eld->eld_size) < 0)
4bd038f9 1507 eld->eld_valid = false;
1613d6b4
DH		 1508 }
1509
4bd038f9 1510 if (eld->eld_valid) {
1613d6b4 1511 snd_hdmi_show_eld(&eld->info);
4bd038f9 1512 update_eld = true;
1613d6b4 1513 }
c6e8453e 1514 else if (repoll) {
744626da
WF		 1515 queue_delayed_work(codec->bus->workq,
1516 &per_pin->work,
1517 msecs_to_jiffies(300));
cbbaa603 1518 goto unlock;
744626da
WF		 1519 }
1520 }
4bd038f9 1521
92c69e79 1522 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1523 update_eld = true;
92c69e79
DH		 1524 eld_changed = true;
1525 }
4bd038f9 1526 if (update_eld) {
b054087d 1527 bool old_eld_valid = pin_eld->eld_valid;
4bd038f9 1528 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1529 eld_changed = pin_eld->eld_size != eld->eld_size ||
1530 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1531 eld->eld_size) != 0;
1532 if (eld_changed)
1533 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1534 eld->eld_size);
1535 pin_eld->eld_size = eld->eld_size;
1536 pin_eld->info = eld->info;
b054087d 1537
7342017f
AH		 1538 /*
1539 * Re-setup pin and infoframe. This is needed e.g. when
1540 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1541 * - transcoder can change during stream playback on Haswell
b054087d 1542 */
7342017f 1543 if (eld->eld_valid && !old_eld_valid && per_pin->setup)
b054087d
TI		 1544 hdmi_setup_audio_infoframe(codec, per_pin,
1545 per_pin->non_pcm);
4bd038f9 1546 }
92c69e79
DH		 1547
1548 if (eld_changed)
1549 snd_ctl_notify(codec->bus->card,
1550 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1551 &per_pin->eld_ctl->id);
cbbaa603 1552 unlock:
a4e9a38b 1553 mutex_unlock(&per_pin->lock);
079d88cc
WF		 1554}
1555
744626da
WF		 1556static void hdmi_repoll_eld(struct work_struct *work)
1557{
1558 struct hdmi_spec_per_pin *per_pin =
1559 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1560
c6e8453e
WF		 1561 if (per_pin->repoll_count++ > 6)
1562 per_pin->repoll_count = 0;
1563
1564 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1565}
1566
c88d4e84
TI		 1567static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1568 hda_nid_t nid);
1569
079d88cc
WF		 1570static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1571{
1572 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1573 unsigned int caps, config;
1574 int pin_idx;
1575 struct hdmi_spec_per_pin *per_pin;
07acecc1 1576 int err;
079d88cc 1577
efc2f8de 1578 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1579 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1580 return 0;
1581
efc2f8de 1582 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1583 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1584 return 0;
1585
fb87fa3a 1586 if (is_haswell(codec))
c88d4e84
TI		 1587 intel_haswell_fixup_connect_list(codec, pin_nid);
1588
384a48d7 1589 pin_idx = spec->num_pins;
bce0d2a8
TI		 1590 per_pin = snd_array_new(&spec->pins);
1591 if (!per_pin)
1592 return -ENOMEM;
384a48d7
SW		 1593
1594 per_pin->pin_nid = pin_nid;
1a6003b5 1595 per_pin->non_pcm = false;
079d88cc 1596
384a48d7
SW		 1597 err = hdmi_read_pin_conn(codec, pin_idx);
1598 if (err < 0)
1599 return err;
079d88cc 1600
079d88cc
WF		 1601 spec->num_pins++;
1602
384a48d7 1603 return 0;
079d88cc
WF		 1604}
1605
384a48d7 1606static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1607{
1608 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1609 struct hdmi_spec_per_cvt *per_cvt;
1610 unsigned int chans;
1611 int err;
079d88cc 1612
384a48d7
SW		 1613 chans = get_wcaps(codec, cvt_nid);
1614 chans = get_wcaps_channels(chans);
1615
bce0d2a8
TI		 1616 per_cvt = snd_array_new(&spec->cvts);
1617 if (!per_cvt)
1618 return -ENOMEM;
384a48d7
SW		 1619
1620 per_cvt->cvt_nid = cvt_nid;
1621 per_cvt->channels_min = 2;
d45e6889 1622 if (chans <= 16) {
384a48d7 1623 per_cvt->channels_max = chans;
d45e6889
TI		 1624 if (chans > spec->channels_max)
1625 spec->channels_max = chans;
1626 }
384a48d7
SW		 1627
1628 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1629 &per_cvt->rates,
1630 &per_cvt->formats,
1631 &per_cvt->maxbps);
1632 if (err < 0)
1633 return err;
1634
bce0d2a8
TI		 1635 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1636 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1637 spec->num_cvts++;
079d88cc
WF		 1638
1639 return 0;
1640}
1641
1642static int hdmi_parse_codec(struct hda_codec *codec)
1643{
1644 hda_nid_t nid;
1645 int i, nodes;
1646
1647 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1648 if (!nid || nodes < 0) {
1649 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1650 return -EINVAL;
1651 }
1652
1653 for (i = 0; i < nodes; i++, nid++) {
1654 unsigned int caps;
1655 unsigned int type;
1656
efc2f8de 1657 caps = get_wcaps(codec, nid);
079d88cc
WF		 1658 type = get_wcaps_type(caps);
1659
1660 if (!(caps & AC_WCAP_DIGITAL))
1661 continue;
1662
1663 switch (type) {
1664 case AC_WID_AUD_OUT:
384a48d7 1665 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1666 break;
1667 case AC_WID_PIN:
3eaead57 1668 hdmi_add_pin(codec, nid);
079d88cc
WF		 1669 break;
1670 }
1671 }
1672
c9adeefd
DH		 1673#ifdef CONFIG_PM
1674 /* We're seeing some problems with unsolicited hot plug events on
1675 * PantherPoint after S3, if this is not enabled */
1676 if (codec->vendor_id == 0x80862806)
1677 codec->bus->power_keep_link_on = 1;
079d88cc
WF		 1678 /*
1679 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1680 * can be lost and presence sense verb will become inaccurate if the
1681 * HDA link is powered off at hot plug or hw initialization time.
1682 */
c9adeefd 1683 else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
079d88cc
WF		 1684 AC_PWRST_EPSS))
1685 codec->bus->power_keep_link_on = 1;
1686#endif
1687
1688 return 0;
1689}
1690
84eb01be
TI		 1691/*
1692 */
1a6003b5
TI		 1693static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1694{
1695 struct hda_spdif_out *spdif;
1696 bool non_pcm;
1697
1698 mutex_lock(&codec->spdif_mutex);
1699 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1700 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1701 mutex_unlock(&codec->spdif_mutex);
1702 return non_pcm;
1703}
1704
1705
84eb01be
TI		 1706/*
1707 * HDMI callbacks
1708 */
1709
1710static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1711 struct hda_codec *codec,
1712 unsigned int stream_tag,
1713 unsigned int format,
1714 struct snd_pcm_substream *substream)
1715{
384a48d7
SW		 1716 hda_nid_t cvt_nid = hinfo->nid;
1717 struct hdmi_spec *spec = codec->spec;
1718 int pin_idx = hinfo_to_pin_index(spec, hinfo);
b054087d
TI		 1719 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1720 hda_nid_t pin_nid = per_pin->pin_nid;
1a6003b5
TI		 1721 bool non_pcm;
1722
1723 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1724 mutex_lock(&per_pin->lock);
b054087d
TI		 1725 per_pin->channels = substream->runtime->channels;
1726 per_pin->setup = true;
384a48d7 1727
b054087d 1728 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1729 mutex_unlock(&per_pin->lock);
84eb01be 1730
307229d2 1731 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1732}
1733
8dfaa573
TI		 1734static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1735 struct hda_codec *codec,
1736 struct snd_pcm_substream *substream)
1737{
1738 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1739 return 0;
1740}
1741
f2ad24fa
TI		 1742static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1743 struct hda_codec *codec,
1744 struct snd_pcm_substream *substream)
384a48d7
SW		 1745{
1746 struct hdmi_spec *spec = codec->spec;
1747 int cvt_idx, pin_idx;
1748 struct hdmi_spec_per_cvt *per_cvt;
1749 struct hdmi_spec_per_pin *per_pin;
384a48d7 1750
384a48d7
SW		 1751 if (hinfo->nid) {
1752 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1753 if (snd_BUG_ON(cvt_idx < 0))
1754 return -EINVAL;
bce0d2a8 1755 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1756
1757 snd_BUG_ON(!per_cvt->assigned);
1758 per_cvt->assigned = 0;
1759 hinfo->nid = 0;
1760
1761 pin_idx = hinfo_to_pin_index(spec, hinfo);
1762 if (snd_BUG_ON(pin_idx < 0))
1763 return -EINVAL;
bce0d2a8 1764 per_pin = get_pin(spec, pin_idx);
384a48d7 1765
384a48d7 1766 snd_hda_spdif_ctls_unassign(codec, pin_idx);
cbbaa603 1767
a4e9a38b 1768 mutex_lock(&per_pin->lock);
d45e6889
TI		 1769 per_pin->chmap_set = false;
1770 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1771
1772 per_pin->setup = false;
1773 per_pin->channels = 0;
a4e9a38b 1774 mutex_unlock(&per_pin->lock);
384a48d7 1775 }
d45e6889 1776
384a48d7
SW		 1777 return 0;
1778}
1779
1780static const struct hda_pcm_ops generic_ops = {
1781 .open = hdmi_pcm_open,
f2ad24fa 1782 .close = hdmi_pcm_close,
384a48d7 1783 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1784 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1785};
1786
d45e6889
TI		 1787/*
1788 * ALSA API channel-map control callbacks
1789 */
1790static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1791 struct snd_ctl_elem_info *uinfo)
1792{
1793 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1794 struct hda_codec *codec = info->private_data;
1795 struct hdmi_spec *spec = codec->spec;
1796 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1797 uinfo->count = spec->channels_max;
1798 uinfo->value.integer.min = 0;
1799 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1800 return 0;
1801}
1802
307229d2
AH		 1803static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1804 int channels)
1805{
1806 /* If the speaker allocation matches the channel count, it is OK.*/
1807 if (cap->channels != channels)
1808 return -1;
1809
1810 /* all channels are remappable freely */
1811 return SNDRV_CTL_TLVT_CHMAP_VAR;
1812}
1813
1814static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1815 unsigned int *chmap, int channels)
1816{
1817 int count = 0;
1818 int c;
1819
1820 for (c = 7; c >= 0; c--) {
1821 int spk = cap->speakers[c];
1822 if (!spk)
1823 continue;
1824
1825 chmap[count++] = spk_to_chmap(spk);
1826 }
1827
1828 WARN_ON(count != channels);
1829}
1830
d45e6889
TI		 1831static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1832 unsigned int size, unsigned int __user *tlv)
1833{
1834 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1835 struct hda_codec *codec = info->private_data;
1836 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 1837 unsigned int __user *dst;
1838 int chs, count = 0;
1839
1840 if (size < 8)
1841 return -ENOMEM;
1842 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1843 return -EFAULT;
1844 size -= 8;
1845 dst = tlv + 2;
498dab3a 1846 for (chs = 2; chs <= spec->channels_max; chs++) {
307229d2 1847 int i;
d45e6889
TI		 1848 struct cea_channel_speaker_allocation *cap;
1849 cap = channel_allocations;
1850 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1851 int chs_bytes = chs * 4;
307229d2
AH		 1852 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1853 unsigned int tlv_chmap[8];
1854
1855 if (type < 0)
d45e6889 1856 continue;
d45e6889
TI		 1857 if (size < 8)
1858 return -ENOMEM;
307229d2 1859 if (put_user(type, dst) ||
d45e6889
TI		 1860 put_user(chs_bytes, dst + 1))
1861 return -EFAULT;
1862 dst += 2;
1863 size -= 8;
1864 count += 8;
1865 if (size < chs_bytes)
1866 return -ENOMEM;
1867 size -= chs_bytes;
1868 count += chs_bytes;
307229d2
AH		 1869 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1870 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1871 return -EFAULT;
1872 dst += chs;
d45e6889
TI		 1873 }
1874 }
1875 if (put_user(count, tlv + 1))
1876 return -EFAULT;
1877 return 0;
1878}
1879
1880static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1881 struct snd_ctl_elem_value *ucontrol)
1882{
1883 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1884 struct hda_codec *codec = info->private_data;
1885 struct hdmi_spec *spec = codec->spec;
1886 int pin_idx = kcontrol->private_value;
bce0d2a8 1887 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1888 int i;
1889
1890 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1891 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1892 return 0;
1893}
1894
1895static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1896 struct snd_ctl_elem_value *ucontrol)
1897{
1898 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1899 struct hda_codec *codec = info->private_data;
1900 struct hdmi_spec *spec = codec->spec;
1901 int pin_idx = kcontrol->private_value;
bce0d2a8 1902 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1903 unsigned int ctl_idx;
1904 struct snd_pcm_substream *substream;
1905 unsigned char chmap[8];
307229d2 1906 int i, err, ca, prepared = 0;
d45e6889
TI		 1907
1908 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1909 substream = snd_pcm_chmap_substream(info, ctl_idx);
1910 if (!substream || !substream->runtime)
6f54c361 1911 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1912 switch (substream->runtime->status->state) {
1913 case SNDRV_PCM_STATE_OPEN:
1914 case SNDRV_PCM_STATE_SETUP:
1915 break;
1916 case SNDRV_PCM_STATE_PREPARED:
1917 prepared = 1;
1918 break;
1919 default:
1920 return -EBUSY;
1921 }
1922 memset(chmap, 0, sizeof(chmap));
1923 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1924 chmap[i] = ucontrol->value.integer.value[i];
1925 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1926 return 0;
1927 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1928 if (ca < 0)
1929 return -EINVAL;
307229d2
AH		 1930 if (spec->ops.chmap_validate) {
1931 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
1932 if (err)
1933 return err;
1934 }
a4e9a38b 1935 mutex_lock(&per_pin->lock);
d45e6889
TI		 1936 per_pin->chmap_set = true;
1937 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1938 if (prepared)
b054087d 1939 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
a4e9a38b 1940 mutex_unlock(&per_pin->lock);
d45e6889
TI		 1941
1942 return 0;
1943}
1944
84eb01be
TI		 1945static int generic_hdmi_build_pcms(struct hda_codec *codec)
1946{
1947 struct hdmi_spec *spec = codec->spec;
384a48d7 1948 int pin_idx;
84eb01be 1949
384a48d7
SW		 1950 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1951 struct hda_pcm *info;
84eb01be 1952 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 1953 struct hdmi_spec_per_pin *per_pin;
1954
1955 per_pin = get_pin(spec, pin_idx);
1956 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
1957 info = snd_array_new(&spec->pcm_rec);
1958 if (!info)
1959 return -ENOMEM;
1960 info->name = per_pin->pcm_name;
84eb01be 1961 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1962 info->own_chmap = true;
384a48d7 1963
84eb01be 1964 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1965 pstr->substreams = 1;
1966 pstr->ops = generic_ops;
1967 /* other pstr fields are set in open */
84eb01be
TI		 1968 }
1969
384a48d7 1970 codec->num_pcms = spec->num_pins;
bce0d2a8 1971 codec->pcm_info = spec->pcm_rec.list;
384a48d7 1972
84eb01be
TI		 1973 return 0;
1974}
1975
0b6c49b5
DH		 1976static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1977{
31ef2257 1978 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 1979 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 1980 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1981 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 1982
31ef2257
TI		 1983 if (pcmdev > 0)
1984 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 1985 if (!is_jack_detectable(codec, per_pin->pin_nid))
1986 strncat(hdmi_str, " Phantom",
1987 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 1988
31ef2257 1989 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1990}
1991
84eb01be
TI		 1992static int generic_hdmi_build_controls(struct hda_codec *codec)
1993{
1994 struct hdmi_spec *spec = codec->spec;
1995 int err;
384a48d7 1996 int pin_idx;
84eb01be 1997
384a48d7 1998 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1999 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 2000
2001 err = generic_hdmi_build_jack(codec, pin_idx);
2002 if (err < 0)
2003 return err;
2004
dcda5806
TI		 2005 err = snd_hda_create_dig_out_ctls(codec,
2006 per_pin->pin_nid,
2007 per_pin->mux_nids[0],
2008 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 2009 if (err < 0)
2010 return err;
384a48d7 2011 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 2012
2013 /* add control for ELD Bytes */
bce0d2a8
TI		 2014 err = hdmi_create_eld_ctl(codec, pin_idx,
2015 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 2016
2017 if (err < 0)
2018 return err;
31ef2257 2019
82b1d73f 2020 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2021 }
2022
d45e6889
TI		 2023 /* add channel maps */
2024 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2025 struct snd_pcm_chmap *chmap;
2026 struct snd_kcontrol *kctl;
2027 int i;
2ca320e2
TI		 2028
2029 if (!codec->pcm_info[pin_idx].pcm)
2030 break;
d45e6889
TI		 2031 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
2032 SNDRV_PCM_STREAM_PLAYBACK,
2033 NULL, 0, pin_idx, &chmap);
2034 if (err < 0)
2035 return err;
2036 /* override handlers */
2037 chmap->private_data = codec;
2038 kctl = chmap->kctl;
2039 for (i = 0; i < kctl->count; i++)
2040 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2041 kctl->info = hdmi_chmap_ctl_info;
2042 kctl->get = hdmi_chmap_ctl_get;
2043 kctl->put = hdmi_chmap_ctl_put;
2044 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2045 }
2046
84eb01be
TI		 2047 return 0;
2048}
2049
8b8d654b 2050static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2051{
2052 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2053 int pin_idx;
2054
2055 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2056 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2057
744626da 2058 per_pin->codec = codec;
a4e9a38b 2059 mutex_init(&per_pin->lock);
744626da 2060 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2061 eld_proc_new(per_pin, pin_idx);
84eb01be 2062 }
8b8d654b
TI		 2063 return 0;
2064}
2065
2066static int generic_hdmi_init(struct hda_codec *codec)
2067{
2068 struct hdmi_spec *spec = codec->spec;
2069 int pin_idx;
2070
2071 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2072 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2073 hda_nid_t pin_nid = per_pin->pin_nid;
2074
2075 hdmi_init_pin(codec, pin_nid);
2076 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
2077 }
84eb01be
TI		 2078 return 0;
2079}
2080
bce0d2a8
TI		 2081static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2082{
2083 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2084 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2085 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
2086}
2087
2088static void hdmi_array_free(struct hdmi_spec *spec)
2089{
2090 snd_array_free(&spec->pins);
2091 snd_array_free(&spec->cvts);
2092 snd_array_free(&spec->pcm_rec);
2093}
2094
84eb01be
TI		 2095static void generic_hdmi_free(struct hda_codec *codec)
2096{
2097 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2098 int pin_idx;
2099
2100 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2101 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2102
744626da 2103 cancel_delayed_work(&per_pin->work);
a4e9a38b 2104 eld_proc_free(per_pin);
384a48d7 2105 }
84eb01be 2106
744626da 2107 flush_workqueue(codec->bus->workq);
bce0d2a8 2108 hdmi_array_free(spec);
84eb01be
TI		 2109 kfree(spec);
2110}
2111
28cb72e5
WX		 2112#ifdef CONFIG_PM
2113static int generic_hdmi_resume(struct hda_codec *codec)
2114{
2115 struct hdmi_spec *spec = codec->spec;
2116 int pin_idx;
2117
2118 generic_hdmi_init(codec);
2119 snd_hda_codec_resume_amp(codec);
2120 snd_hda_codec_resume_cache(codec);
2121
2122 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2123 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2124 hdmi_present_sense(per_pin, 1);
2125 }
2126 return 0;
2127}
2128#endif
2129
fb79e1e0 2130static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2131 .init = generic_hdmi_init,
2132 .free = generic_hdmi_free,
2133 .build_pcms = generic_hdmi_build_pcms,
2134 .build_controls = generic_hdmi_build_controls,
2135 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2136#ifdef CONFIG_PM
2137 .resume = generic_hdmi_resume,
2138#endif
84eb01be
TI		 2139};
2140
307229d2
AH		 2141static const struct hdmi_ops generic_standard_hdmi_ops = {
2142 .pin_get_eld = snd_hdmi_get_eld,
2143 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2144 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2145 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2146 .pin_hbr_setup = hdmi_pin_hbr_setup,
2147 .setup_stream = hdmi_setup_stream,
2148 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2149 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2150};
2151
6ffe168f 2152
c88d4e84
TI		 2153static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2154 hda_nid_t nid)
2155{
2156 struct hdmi_spec *spec = codec->spec;
2157 hda_nid_t conns[4];
2158 int nconns;
6ffe168f 2159
c88d4e84
TI		 2160 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2161 if (nconns == spec->num_cvts &&
2162 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2163 return;
2164
c88d4e84
TI		 2165 /* override pins connection list */
2166 snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
2167 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2168}
2169
1611a9c9
ML		 2170#define INTEL_VENDOR_NID 0x08
2171#define INTEL_GET_VENDOR_VERB 0xf81
2172#define INTEL_SET_VENDOR_VERB 0x781
2173#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2174#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2175
2176static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2177 bool update_tree)
1611a9c9
ML		 2178{
2179 unsigned int vendor_param;
2180
1611a9c9
ML		 2181 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2182 INTEL_GET_VENDOR_VERB, 0);
2183 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2184 return;
2185
2186 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2187 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2188 INTEL_SET_VENDOR_VERB, vendor_param);
2189 if (vendor_param == -1)
2190 return;
2191
17df3f55
TI		 2192 if (update_tree)
2193 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2194}
2195
c88d4e84
TI		 2196static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2197{
2198 unsigned int vendor_param;
2199
2200 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2201 INTEL_GET_VENDOR_VERB, 0);
2202 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2203 return;
2204
2205 /* enable DP1.2 mode */
2206 vendor_param |= INTEL_EN_DP12;
2207 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2208 INTEL_SET_VENDOR_VERB, vendor_param);
2209}
2210
17df3f55
TI		 2211/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2212 * Otherwise you may get severe h/w communication errors.
2213 */
2214static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2215 unsigned int power_state)
2216{
2217 if (power_state == AC_PWRST_D0) {
2218 intel_haswell_enable_all_pins(codec, false);
2219 intel_haswell_fixup_enable_dp12(codec);
2220 }
c88d4e84 2221
17df3f55
TI		 2222 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2223 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2224}
6ffe168f 2225
84eb01be
TI		 2226static int patch_generic_hdmi(struct hda_codec *codec)
2227{
2228 struct hdmi_spec *spec;
84eb01be
TI		 2229
2230 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2231 if (spec == NULL)
2232 return -ENOMEM;
2233
307229d2 2234 spec->ops = generic_standard_hdmi_ops;
84eb01be 2235 codec->spec = spec;
bce0d2a8 2236 hdmi_array_init(spec, 4);
6ffe168f 2237
fb87fa3a 2238 if (is_haswell(codec)) {
17df3f55 2239 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2240 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2241 }
6ffe168f 2242
84eb01be
TI		 2243 if (hdmi_parse_codec(codec) < 0) {
2244 codec->spec = NULL;
2245 kfree(spec);
2246 return -EINVAL;
2247 }
2248 codec->patch_ops = generic_hdmi_patch_ops;
fb87fa3a 2249 if (is_haswell(codec)) {
17df3f55 2250 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2251 codec->dp_mst = true;
2252 }
17df3f55 2253
8b8d654b 2254 generic_hdmi_init_per_pins(codec);
84eb01be 2255
84eb01be
TI		 2256 init_channel_allocations();
2257
2258 return 0;
2259}
2260
3aaf8980
SW		 2261/*
2262 * Shared non-generic implementations
2263 */
2264
2265static int simple_playback_build_pcms(struct hda_codec *codec)
2266{
2267 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2268 struct hda_pcm *info;
8ceb332d
TI		 2269 unsigned int chans;
2270 struct hda_pcm_stream *pstr;
bce0d2a8 2271 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2272
bce0d2a8
TI		 2273 per_cvt = get_cvt(spec, 0);
2274 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2275 chans = get_wcaps_channels(chans);
3aaf8980 2276
bce0d2a8
TI		 2277 info = snd_array_new(&spec->pcm_rec);
2278 if (!info)
2279 return -ENOMEM;
2280 info->name = get_pin(spec, 0)->pcm_name;
2281 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2282 info->pcm_type = HDA_PCM_TYPE_HDMI;
2283 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2284 *pstr = spec->pcm_playback;
bce0d2a8 2285 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2286 if (pstr->channels_max <= 2 && chans && chans <= 16)
2287 pstr->channels_max = chans;
3aaf8980 2288
bce0d2a8
TI		 2289 codec->num_pcms = 1;
2290 codec->pcm_info = info;
2291
3aaf8980
SW		 2292 return 0;
2293}
2294
4b6ace9e
TI		 2295/* unsolicited event for jack sensing */
2296static void simple_hdmi_unsol_event(struct hda_codec *codec,
2297 unsigned int res)
2298{
9dd8cf12 2299 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2300 snd_hda_jack_report_sync(codec);
2301}
2302
2303/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2304 * as long as spec->pins[] is set correctly
2305 */
2306#define simple_hdmi_build_jack generic_hdmi_build_jack
2307
3aaf8980
SW		 2308static int simple_playback_build_controls(struct hda_codec *codec)
2309{
2310 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2311 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2312 int err;
3aaf8980 2313
bce0d2a8
TI		 2314 per_cvt = get_cvt(spec, 0);
2315 err = snd_hda_create_spdif_out_ctls(codec, per_cvt->cvt_nid,
2316 per_cvt->cvt_nid);
8ceb332d
TI		 2317 if (err < 0)
2318 return err;
2319 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2320}
2321
4f0110ce
TI		 2322static int simple_playback_init(struct hda_codec *codec)
2323{
2324 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2325 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2326 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2327
2328 snd_hda_codec_write(codec, pin, 0,
2329 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2330 /* some codecs require to unmute the pin */
2331 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2332 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2333 AMP_OUT_UNMUTE);
2334 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2335 return 0;
2336}
2337
3aaf8980
SW		 2338static void simple_playback_free(struct hda_codec *codec)
2339{
2340 struct hdmi_spec *spec = codec->spec;
2341
bce0d2a8 2342 hdmi_array_free(spec);
3aaf8980
SW		 2343 kfree(spec);
2344}
2345
84eb01be
TI		 2346/*
2347 * Nvidia specific implementations
2348 */
2349
2350#define Nv_VERB_SET_Channel_Allocation 0xF79
2351#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2352#define Nv_VERB_SET_Audio_Protection_On 0xF98
2353#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2354
2355#define nvhdmi_master_con_nid_7x 0x04
2356#define nvhdmi_master_pin_nid_7x 0x05
2357
fb79e1e0 2358static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2359 /*front, rear, clfe, rear_surr */
2360 0x6, 0x8, 0xa, 0xc,
2361};
2362
ceaa86ba
TI		 2363static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2364 /* set audio protect on */
2365 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2366 /* enable digital output on pin widget */
2367 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2368 {} /* terminator */
2369};
2370
2371static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2372 /* set audio protect on */
2373 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2374 /* enable digital output on pin widget */
2375 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2376 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2377 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2378 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2379 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2380 {} /* terminator */
2381};
2382
2383#ifdef LIMITED_RATE_FMT_SUPPORT
2384/* support only the safe format and rate */
2385#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2386#define SUPPORTED_MAXBPS 16
2387#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2388#else
2389/* support all rates and formats */
2390#define SUPPORTED_RATES \
2391 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2392 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2393 SNDRV_PCM_RATE_192000)
2394#define SUPPORTED_MAXBPS 24
2395#define SUPPORTED_FORMATS \
2396 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2397#endif
2398
ceaa86ba
TI		 2399static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2400{
2401 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2402 return 0;
2403}
2404
2405static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2406{
ceaa86ba 2407 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2408 return 0;
2409}
2410
393004b2
ND		 2411static unsigned int channels_2_6_8[] = {
2412 2, 6, 8
2413};
2414
2415static unsigned int channels_2_8[] = {
2416 2, 8
2417};
2418
2419static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2420 .count = ARRAY_SIZE(channels_2_6_8),
2421 .list = channels_2_6_8,
2422 .mask = 0,
2423};
2424
2425static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2426 .count = ARRAY_SIZE(channels_2_8),
2427 .list = channels_2_8,
2428 .mask = 0,
2429};
2430
84eb01be
TI		 2431static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2432 struct hda_codec *codec,
2433 struct snd_pcm_substream *substream)
2434{
2435 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2436 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2437
2438 switch (codec->preset->id) {
2439 case 0x10de0002:
2440 case 0x10de0003:
2441 case 0x10de0005:
2442 case 0x10de0006:
2443 hw_constraints_channels = &hw_constraints_2_8_channels;
2444 break;
2445 case 0x10de0007:
2446 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2447 break;
2448 default:
2449 break;
2450 }
2451
2452 if (hw_constraints_channels != NULL) {
2453 snd_pcm_hw_constraint_list(substream->runtime, 0,
2454 SNDRV_PCM_HW_PARAM_CHANNELS,
2455 hw_constraints_channels);
ad09fc9d
TI		 2456 } else {
2457 snd_pcm_hw_constraint_step(substream->runtime, 0,
2458 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2459 }
2460
84eb01be
TI		 2461 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2462}
2463
2464static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2465 struct hda_codec *codec,
2466 struct snd_pcm_substream *substream)
2467{
2468 struct hdmi_spec *spec = codec->spec;
2469 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2470}
2471
2472static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2473 struct hda_codec *codec,
2474 unsigned int stream_tag,
2475 unsigned int format,
2476 struct snd_pcm_substream *substream)
2477{
2478 struct hdmi_spec *spec = codec->spec;
2479 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2480 stream_tag, format, substream);
2481}
2482
d0b1252d
TI		 2483static const struct hda_pcm_stream simple_pcm_playback = {
2484 .substreams = 1,
2485 .channels_min = 2,
2486 .channels_max = 2,
2487 .ops = {
2488 .open = simple_playback_pcm_open,
2489 .close = simple_playback_pcm_close,
2490 .prepare = simple_playback_pcm_prepare
2491 },
2492};
2493
2494static const struct hda_codec_ops simple_hdmi_patch_ops = {
2495 .build_controls = simple_playback_build_controls,
2496 .build_pcms = simple_playback_build_pcms,
2497 .init = simple_playback_init,
2498 .free = simple_playback_free,
250e41ac 2499 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2500};
2501
2502static int patch_simple_hdmi(struct hda_codec *codec,
2503 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2504{
2505 struct hdmi_spec *spec;
bce0d2a8
TI		 2506 struct hdmi_spec_per_cvt *per_cvt;
2507 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2508
2509 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2510 if (!spec)
2511 return -ENOMEM;
2512
2513 codec->spec = spec;
bce0d2a8 2514 hdmi_array_init(spec, 1);
d0b1252d
TI		 2515
2516 spec->multiout.num_dacs = 0; /* no analog */
2517 spec->multiout.max_channels = 2;
2518 spec->multiout.dig_out_nid = cvt_nid;
2519 spec->num_cvts = 1;
2520 spec->num_pins = 1;
bce0d2a8
TI		 2521 per_pin = snd_array_new(&spec->pins);
2522 per_cvt = snd_array_new(&spec->cvts);
2523 if (!per_pin || !per_cvt) {
2524 simple_playback_free(codec);
2525 return -ENOMEM;
2526 }
2527 per_cvt->cvt_nid = cvt_nid;
2528 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2529 spec->pcm_playback = simple_pcm_playback;
2530
2531 codec->patch_ops = simple_hdmi_patch_ops;
2532
2533 return 0;
2534}
2535
1f348522
AP		 2536static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2537 int channels)
2538{
2539 unsigned int chanmask;
2540 int chan = channels ? (channels - 1) : 1;
2541
2542 switch (channels) {
2543 default:
2544 case 0:
2545 case 2:
2546 chanmask = 0x00;
2547 break;
2548 case 4:
2549 chanmask = 0x08;
2550 break;
2551 case 6:
2552 chanmask = 0x0b;
2553 break;
2554 case 8:
2555 chanmask = 0x13;
2556 break;
2557 }
2558
2559 /* Set the audio infoframe channel allocation and checksum fields. The
2560 * channel count is computed implicitly by the hardware. */
2561 snd_hda_codec_write(codec, 0x1, 0,
2562 Nv_VERB_SET_Channel_Allocation, chanmask);
2563
2564 snd_hda_codec_write(codec, 0x1, 0,
2565 Nv_VERB_SET_Info_Frame_Checksum,
2566 (0x71 - chan - chanmask));
2567}
2568
84eb01be
TI		 2569static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2570 struct hda_codec *codec,
2571 struct snd_pcm_substream *substream)
2572{
2573 struct hdmi_spec *spec = codec->spec;
2574 int i;
2575
2576 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2577 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2578 for (i = 0; i < 4; i++) {
2579 /* set the stream id */
2580 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2581 AC_VERB_SET_CHANNEL_STREAMID, 0);
2582 /* set the stream format */
2583 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2584 AC_VERB_SET_STREAM_FORMAT, 0);
2585 }
2586
1f348522
AP		 2587 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2588 * streams are disabled. */
2589 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2590
84eb01be
TI		 2591 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2592}
2593
2594static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2595 struct hda_codec *codec,
2596 unsigned int stream_tag,
2597 unsigned int format,
2598 struct snd_pcm_substream *substream)
2599{
2600 int chs;
112daa7a 2601 unsigned int dataDCC2, channel_id;
84eb01be 2602 int i;
7c935976 2603 struct hdmi_spec *spec = codec->spec;
e3245cdd 2604 struct hda_spdif_out *spdif;
bce0d2a8 2605 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2606
2607 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2608 per_cvt = get_cvt(spec, 0);
2609 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2610
2611 chs = substream->runtime->channels;
84eb01be 2612
84eb01be
TI		 2613 dataDCC2 = 0x2;
2614
84eb01be 2615 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2616 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2617 snd_hda_codec_write(codec,
2618 nvhdmi_master_con_nid_7x,
2619 0,
2620 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2621 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2622
2623 /* set the stream id */
2624 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2625 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2626
2627 /* set the stream format */
2628 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2629 AC_VERB_SET_STREAM_FORMAT, format);
2630
2631 /* turn on again (if needed) */
2632 /* enable and set the channel status audio/data flag */
7c935976 2633 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2634 snd_hda_codec_write(codec,
2635 nvhdmi_master_con_nid_7x,
2636 0,
2637 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2638 spdif->ctls & 0xff);
84eb01be
TI		 2639 snd_hda_codec_write(codec,
2640 nvhdmi_master_con_nid_7x,
2641 0,
2642 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2643 }
2644
2645 for (i = 0; i < 4; i++) {
2646 if (chs == 2)
2647 channel_id = 0;
2648 else
2649 channel_id = i * 2;
2650
2651 /* turn off SPDIF once;
2652 *otherwise the IEC958 bits won't be updated
2653 */
2654 if (codec->spdif_status_reset &&
7c935976 2655 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2656 snd_hda_codec_write(codec,
2657 nvhdmi_con_nids_7x[i],
2658 0,
2659 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2660 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2661 /* set the stream id */
2662 snd_hda_codec_write(codec,
2663 nvhdmi_con_nids_7x[i],
2664 0,
2665 AC_VERB_SET_CHANNEL_STREAMID,
2666 (stream_tag << 4) | channel_id);
2667 /* set the stream format */
2668 snd_hda_codec_write(codec,
2669 nvhdmi_con_nids_7x[i],
2670 0,
2671 AC_VERB_SET_STREAM_FORMAT,
2672 format);
2673 /* turn on again (if needed) */
2674 /* enable and set the channel status audio/data flag */
2675 if (codec->spdif_status_reset &&
7c935976 2676 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2677 snd_hda_codec_write(codec,
2678 nvhdmi_con_nids_7x[i],
2679 0,
2680 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2681 spdif->ctls & 0xff);
84eb01be
TI		 2682 snd_hda_codec_write(codec,
2683 nvhdmi_con_nids_7x[i],
2684 0,
2685 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2686 }
2687 }
2688
1f348522 2689 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2690
2691 mutex_unlock(&codec->spdif_mutex);
2692 return 0;
2693}
2694
fb79e1e0 2695static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2696 .substreams = 1,
2697 .channels_min = 2,
2698 .channels_max = 8,
2699 .nid = nvhdmi_master_con_nid_7x,
2700 .rates = SUPPORTED_RATES,
2701 .maxbps = SUPPORTED_MAXBPS,
2702 .formats = SUPPORTED_FORMATS,
2703 .ops = {
2704 .open = simple_playback_pcm_open,
2705 .close = nvhdmi_8ch_7x_pcm_close,
2706 .prepare = nvhdmi_8ch_7x_pcm_prepare
2707 },
2708};
2709
84eb01be
TI		 2710static int patch_nvhdmi_2ch(struct hda_codec *codec)
2711{
2712 struct hdmi_spec *spec;
d0b1252d
TI		 2713 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2714 nvhdmi_master_pin_nid_7x);
2715 if (err < 0)
2716 return err;
84eb01be 2717
ceaa86ba 2718 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2719 /* override the PCM rates, etc, as the codec doesn't give full list */
2720 spec = codec->spec;
2721 spec->pcm_playback.rates = SUPPORTED_RATES;
2722 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2723 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2724 return 0;
2725}
2726
53775b0d
TI		 2727static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2728{
2729 struct hdmi_spec *spec = codec->spec;
2730 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2731 if (!err) {
2732 struct hda_pcm *info = get_pcm_rec(spec, 0);
2733 info->own_chmap = true;
2734 }
53775b0d
TI		 2735 return err;
2736}
2737
2738static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2739{
2740 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2741 struct hda_pcm *info;
53775b0d
TI		 2742 struct snd_pcm_chmap *chmap;
2743 int err;
2744
2745 err = simple_playback_build_controls(codec);
2746 if (err < 0)
2747 return err;
2748
2749 /* add channel maps */
bce0d2a8
TI		 2750 info = get_pcm_rec(spec, 0);
2751 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2752 SNDRV_PCM_STREAM_PLAYBACK,
2753 snd_pcm_alt_chmaps, 8, 0, &chmap);
2754 if (err < 0)
2755 return err;
2756 switch (codec->preset->id) {
2757 case 0x10de0002:
2758 case 0x10de0003:
2759 case 0x10de0005:
2760 case 0x10de0006:
2761 chmap->channel_mask = (1U << 2) | (1U << 8);
2762 break;
2763 case 0x10de0007:
2764 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2765 }
2766 return 0;
2767}
2768
84eb01be
TI		 2769static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2770{
2771 struct hdmi_spec *spec;
2772 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2773 if (err < 0)
2774 return err;
2775 spec = codec->spec;
2776 spec->multiout.max_channels = 8;
d0b1252d 2777 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2778 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2779 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2780 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2781
2782 /* Initialize the audio infoframe channel mask and checksum to something
2783 * valid */
2784 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2785
84eb01be
TI		 2786 return 0;
2787}
2788
2789/*
5a613584 2790 * ATI/AMD-specific implementations
84eb01be
TI		 2791 */
2792
5a613584
AH		 2793#define is_amdhdmi_rev3_or_later(codec) \
2794 ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300)
2795#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
2796
2797/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
2798#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
2799#define ATI_VERB_SET_DOWNMIX_INFO 0x772
2800#define ATI_VERB_SET_MULTICHANNEL_01 0x777
2801#define ATI_VERB_SET_MULTICHANNEL_23 0x778
2802#define ATI_VERB_SET_MULTICHANNEL_45 0x779
2803#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 2804#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 2805#define ATI_VERB_SET_MULTICHANNEL_1 0x785
2806#define ATI_VERB_SET_MULTICHANNEL_3 0x786
2807#define ATI_VERB_SET_MULTICHANNEL_5 0x787
2808#define ATI_VERB_SET_MULTICHANNEL_7 0x788
2809#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
2810#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
2811#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
2812#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
2813#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
2814#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
2815#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 2816#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 2817#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
2818#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
2819#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
2820#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
2821#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
2822
84d69e79
AH		 2823/* AMD specific HDA cvt verbs */
2824#define ATI_VERB_SET_RAMP_RATE 0x770
2825#define ATI_VERB_GET_RAMP_RATE 0xf70
2826
5a613584
AH		 2827#define ATI_OUT_ENABLE 0x1
2828
2829#define ATI_MULTICHANNEL_MODE_PAIRED 0
2830#define ATI_MULTICHANNEL_MODE_SINGLE 1
2831
461cf6b3
AH		 2832#define ATI_HBR_CAPABLE 0x01
2833#define ATI_HBR_ENABLE 0x10
2834
89250f84
AH		 2835static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
2836 unsigned char *buf, int *eld_size)
2837{
2838 /* call hda_eld.c ATI/AMD-specific function */
2839 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
2840 is_amdhdmi_rev3_or_later(codec));
2841}
2842
5a613584
AH		 2843static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
2844 int active_channels, int conn_type)
2845{
2846 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
2847}
2848
2849static int atihdmi_paired_swap_fc_lfe(int pos)
2850{
2851 /*
2852 * ATI/AMD have automatic FC/LFE swap built-in
2853 * when in pairwise mapping mode.
2854 */
2855
2856 switch (pos) {
2857 /* see channel_allocations[].speakers[] */
2858 case 2: return 3;
2859 case 3: return 2;
2860 default: break;
2861 }
2862
2863 return pos;
2864}
2865
2866static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
2867{
2868 struct cea_channel_speaker_allocation *cap;
2869 int i, j;
2870
2871 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
2872
2873 cap = &channel_allocations[get_channel_allocation_order(ca)];
2874 for (i = 0; i < chs; ++i) {
2875 int mask = to_spk_mask(map[i]);
2876 bool ok = false;
2877 bool companion_ok = false;
2878
2879 if (!mask)
2880 continue;
2881
2882 for (j = 0 + i % 2; j < 8; j += 2) {
2883 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
2884 if (cap->speakers[chan_idx] == mask) {
2885 /* channel is in a supported position */
2886 ok = true;
2887
2888 if (i % 2 == 0 && i + 1 < chs) {
2889 /* even channel, check the odd companion */
2890 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
2891 int comp_mask_req = to_spk_mask(map[i+1]);
2892 int comp_mask_act = cap->speakers[comp_chan_idx];
2893
2894 if (comp_mask_req == comp_mask_act)
2895 companion_ok = true;
2896 else
2897 return -EINVAL;
2898 }
2899 break;
2900 }
2901 }
2902
2903 if (!ok)
2904 return -EINVAL;
2905
2906 if (companion_ok)
2907 i++; /* companion channel already checked */
2908 }
2909
2910 return 0;
2911}
2912
2913static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
2914 int hdmi_slot, int stream_channel)
2915{
2916 int verb;
2917 int ati_channel_setup = 0;
2918
2919 if (hdmi_slot > 7)
2920 return -EINVAL;
2921
2922 if (!has_amd_full_remap_support(codec)) {
2923 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
2924
2925 /* In case this is an odd slot but without stream channel, do not
2926 * disable the slot since the corresponding even slot could have a
2927 * channel. In case neither have a channel, the slot pair will be
2928 * disabled when this function is called for the even slot. */
2929 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
2930 return 0;
2931
2932 hdmi_slot -= hdmi_slot % 2;
2933
2934 if (stream_channel != 0xf)
2935 stream_channel -= stream_channel % 2;
2936 }
2937
2938 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
2939
2940 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
2941
2942 if (stream_channel != 0xf)
2943 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
2944
2945 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
2946}
2947
2948static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
2949 int asp_slot)
2950{
2951 bool was_odd = false;
2952 int ati_asp_slot = asp_slot;
2953 int verb;
2954 int ati_channel_setup;
2955
2956 if (asp_slot > 7)
2957 return -EINVAL;
2958
2959 if (!has_amd_full_remap_support(codec)) {
2960 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
2961 if (ati_asp_slot % 2 != 0) {
2962 ati_asp_slot -= 1;
2963 was_odd = true;
2964 }
2965 }
2966
2967 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
2968
2969 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
2970
2971 if (!(ati_channel_setup & ATI_OUT_ENABLE))
2972 return 0xf;
2973
2974 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
2975}
84eb01be 2976
5a613584
AH		 2977static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2978 int channels)
2979{
2980 int c;
2981
2982 /*
2983 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
2984 * we need to take that into account (a single channel may take 2
2985 * channel slots if we need to carry a silent channel next to it).
2986 * On Rev3+ AMD codecs this function is not used.
2987 */
2988 int chanpairs = 0;
2989
2990 /* We only produce even-numbered channel count TLVs */
2991 if ((channels % 2) != 0)
2992 return -1;
2993
2994 for (c = 0; c < 7; c += 2) {
2995 if (cap->speakers[c] || cap->speakers[c+1])
2996 chanpairs++;
2997 }
2998
2999 if (chanpairs * 2 != channels)
3000 return -1;
3001
3002 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3003}
3004
3005static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3006 unsigned int *chmap, int channels)
3007{
3008 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3009 int count = 0;
3010 int c;
3011
3012 for (c = 7; c >= 0; c--) {
3013 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3014 int spk = cap->speakers[chan];
3015 if (!spk) {
3016 /* add N/A channel if the companion channel is occupied */
3017 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3018 chmap[count++] = SNDRV_CHMAP_NA;
3019
3020 continue;
3021 }
3022
3023 chmap[count++] = spk_to_chmap(spk);
3024 }
3025
3026 WARN_ON(count != channels);
3027}
3028
461cf6b3
AH		 3029static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3030 bool hbr)
3031{
3032 int hbr_ctl, hbr_ctl_new;
3033
3034 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3035 if (hbr_ctl & ATI_HBR_CAPABLE) {
3036 if (hbr)
3037 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3038 else
3039 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3040
3041 snd_printdd("atihdmi_pin_hbr_setup: "
3042 "NID=0x%x, %shbr-ctl=0x%x\n",
3043 pin_nid,
3044 hbr_ctl == hbr_ctl_new ? "" : "new-",
3045 hbr_ctl_new);
3046
3047 if (hbr_ctl != hbr_ctl_new)
3048 snd_hda_codec_write(codec, pin_nid, 0,
3049 ATI_VERB_SET_HBR_CONTROL,
3050 hbr_ctl_new);
3051
3052 } else if (hbr)
3053 return -EINVAL;
3054
3055 return 0;
3056}
3057
84d69e79
AH		 3058static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3059 hda_nid_t pin_nid, u32 stream_tag, int format)
3060{
3061
3062 if (is_amdhdmi_rev3_or_later(codec)) {
3063 int ramp_rate = 180; /* default as per AMD spec */
3064 /* disable ramp-up/down for non-pcm as per AMD spec */
3065 if (format & AC_FMT_TYPE_NON_PCM)
3066 ramp_rate = 0;
3067
3068 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3069 }
3070
3071 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3072}
3073
3074
5a613584 3075static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3076{
3077 struct hdmi_spec *spec = codec->spec;
5a613584 3078 int pin_idx, err;
84eb01be 3079
5a613584
AH		 3080 err = generic_hdmi_init(codec);
3081
3082 if (err)
84eb01be 3083 return err;
5a613584
AH		 3084
3085 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3086 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3087
3088 /* make sure downmix information in infoframe is zero */
3089 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3090
3091 /* enable channel-wise remap mode if supported */
3092 if (has_amd_full_remap_support(codec))
3093 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3094 ATI_VERB_SET_MULTICHANNEL_MODE,
3095 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3096 }
5a613584 3097
84eb01be
TI		 3098 return 0;
3099}
3100
84eb01be
TI		 3101static int patch_atihdmi(struct hda_codec *codec)
3102{
3103 struct hdmi_spec *spec;
5a613584
AH		 3104 struct hdmi_spec_per_cvt *per_cvt;
3105 int err, cvt_idx;
3106
3107 err = patch_generic_hdmi(codec);
3108
3109 if (err)
d0b1252d 3110 return err;
5a613584
AH		 3111
3112 codec->patch_ops.init = atihdmi_init;
3113
d0b1252d 3114 spec = codec->spec;
5a613584 3115
89250f84 3116 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584
AH		 3117 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3118 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3119 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 3120 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 3121 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584
AH		 3122
3123 if (!has_amd_full_remap_support(codec)) {
3124 /* override to ATI/AMD-specific versions with pairwise mapping */
3125 spec->ops.chmap_cea_alloc_validate_get_type =
3126 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3127 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3128 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3129 }
3130
3131 /* ATI/AMD converters do not advertise all of their capabilities */
3132 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3133 per_cvt = get_cvt(spec, cvt_idx);
3134 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3135 per_cvt->rates |= SUPPORTED_RATES;
3136 per_cvt->formats |= SUPPORTED_FORMATS;
3137 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3138 }
3139
3140 spec->channels_max = max(spec->channels_max, 8u);
3141
84eb01be
TI		 3142 return 0;
3143}
3144
3de5ff88
AL		 3145/* VIA HDMI Implementation */
3146#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3147#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3148
3de5ff88
AL		 3149static int patch_via_hdmi(struct hda_codec *codec)
3150{
250e41ac 3151 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3152}
84eb01be
TI		 3153
3154/*
3155 * patch entries
3156 */
fb79e1e0 3157static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 3158{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
3159{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
3160{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
5a613584 3161{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
84eb01be
TI		 3162{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
3163{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
3164{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
3165{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3166{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3167{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3168{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3169{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 3170{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
3171{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
3172{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
3173{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
3174{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
3175{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
3176{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
3177{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
3178{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
3179{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
3180{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 3181/* 17 is known to be absent */
5d44f927
SW		 3182{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
3183{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
3184{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
3185{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
3186{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
3187{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
3188{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
3189{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
3190{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
3191{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
7ae48b56 3192{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
d52392b1 3193{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 3194{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
3195{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 3196{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3197{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3198{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3199{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 3200{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3201{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
3202{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
3203{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
3204{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3205{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 3206{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 3207{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 3208{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
cc1a95d9 3209{ .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 3210{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
3211{} /* terminator */
3212};
3213
3214MODULE_ALIAS("snd-hda-codec-id:1002793c");
3215MODULE_ALIAS("snd-hda-codec-id:10027919");
3216MODULE_ALIAS("snd-hda-codec-id:1002791a");
3217MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3218MODULE_ALIAS("snd-hda-codec-id:10951390");
3219MODULE_ALIAS("snd-hda-codec-id:10951392");
3220MODULE_ALIAS("snd-hda-codec-id:10de0002");
3221MODULE_ALIAS("snd-hda-codec-id:10de0003");
3222MODULE_ALIAS("snd-hda-codec-id:10de0005");
3223MODULE_ALIAS("snd-hda-codec-id:10de0006");
3224MODULE_ALIAS("snd-hda-codec-id:10de0007");
3225MODULE_ALIAS("snd-hda-codec-id:10de000a");
3226MODULE_ALIAS("snd-hda-codec-id:10de000b");
3227MODULE_ALIAS("snd-hda-codec-id:10de000c");
3228MODULE_ALIAS("snd-hda-codec-id:10de000d");
3229MODULE_ALIAS("snd-hda-codec-id:10de0010");
3230MODULE_ALIAS("snd-hda-codec-id:10de0011");
3231MODULE_ALIAS("snd-hda-codec-id:10de0012");
3232MODULE_ALIAS("snd-hda-codec-id:10de0013");
3233MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 3234MODULE_ALIAS("snd-hda-codec-id:10de0015");
3235MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 3236MODULE_ALIAS("snd-hda-codec-id:10de0018");
3237MODULE_ALIAS("snd-hda-codec-id:10de0019");
3238MODULE_ALIAS("snd-hda-codec-id:10de001a");
3239MODULE_ALIAS("snd-hda-codec-id:10de001b");
3240MODULE_ALIAS("snd-hda-codec-id:10de001c");
3241MODULE_ALIAS("snd-hda-codec-id:10de0040");
3242MODULE_ALIAS("snd-hda-codec-id:10de0041");
3243MODULE_ALIAS("snd-hda-codec-id:10de0042");
3244MODULE_ALIAS("snd-hda-codec-id:10de0043");
3245MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 3246MODULE_ALIAS("snd-hda-codec-id:10de0051");
d52392b1 3247MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 3248MODULE_ALIAS("snd-hda-codec-id:10de0067");
3249MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 3250MODULE_ALIAS("snd-hda-codec-id:11069f80");
3251MODULE_ALIAS("snd-hda-codec-id:11069f81");
3252MODULE_ALIAS("snd-hda-codec-id:11069f84");
3253MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 3254MODULE_ALIAS("snd-hda-codec-id:17e80047");
3255MODULE_ALIAS("snd-hda-codec-id:80860054");
3256MODULE_ALIAS("snd-hda-codec-id:80862801");
3257MODULE_ALIAS("snd-hda-codec-id:80862802");
3258MODULE_ALIAS("snd-hda-codec-id:80862803");
3259MODULE_ALIAS("snd-hda-codec-id:80862804");
3260MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 3261MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 3262MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 3263MODULE_ALIAS("snd-hda-codec-id:80862880");
cc1a95d9 3264MODULE_ALIAS("snd-hda-codec-id:80862882");
84eb01be
TI		 3265MODULE_ALIAS("snd-hda-codec-id:808629fb");
3266
3267MODULE_LICENSE("GPL");
3268MODULE_DESCRIPTION("HDMI HD-audio codec");
3269MODULE_ALIAS("snd-hda-codec-intelhdmi");
3270MODULE_ALIAS("snd-hda-codec-nvhdmi");
3271MODULE_ALIAS("snd-hda-codec-atihdmi");
3272
3273static struct hda_codec_preset_list intel_list = {
3274 .preset = snd_hda_preset_hdmi,
3275 .owner = THIS_MODULE,
3276};
3277
3278static int __init patch_hdmi_init(void)
3279{
3280 return snd_hda_add_codec_preset(&intel_list);
3281}
3282
3283static void __exit patch_hdmi_exit(void)
3284{
3285 snd_hda_delete_codec_preset(&intel_list);
3286}
3287
3288module_init(patch_hdmi_init)
3289module_exit(patch_hdmi_exit)
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