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1 | #ifndef __SOUND_ICE1712_H |
2 | #define __SOUND_ICE1712_H | |
3 | ||
4 | /* | |
5 | * ALSA driver for ICEnsemble ICE1712 (Envy24) | |
6 | * | |
7 | * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <sound/control.h> | |
26 | #include <sound/ac97_codec.h> | |
27 | #include <sound/rawmidi.h> | |
28 | #include <sound/i2c.h> | |
29 | #include <sound/ak4xxx-adda.h> | |
30 | #include <sound/ak4114.h> | |
31 | #include <sound/pcm.h> | |
32 | ||
33 | ||
34 | /* | |
35 | * Direct registers | |
36 | */ | |
37 | ||
38 | #define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x) | |
39 | ||
40 | #define ICE1712_REG_CONTROL 0x00 /* byte */ | |
41 | #define ICE1712_RESET 0x80 /* reset whole chip */ | |
42 | #define ICE1712_SERR_LEVEL 0x04 /* SERR# level otherwise edge */ | |
43 | #define ICE1712_NATIVE 0x01 /* native mode otherwise SB */ | |
44 | #define ICE1712_REG_IRQMASK 0x01 /* byte */ | |
45 | #define ICE1712_IRQ_MPU1 0x80 | |
46 | #define ICE1712_IRQ_TIMER 0x40 | |
47 | #define ICE1712_IRQ_MPU2 0x20 | |
48 | #define ICE1712_IRQ_PROPCM 0x10 | |
49 | #define ICE1712_IRQ_FM 0x08 /* FM/MIDI - legacy */ | |
50 | #define ICE1712_IRQ_PBKDS 0x04 /* playback DS channels */ | |
51 | #define ICE1712_IRQ_CONCAP 0x02 /* consumer capture */ | |
52 | #define ICE1712_IRQ_CONPBK 0x01 /* consumer playback */ | |
53 | #define ICE1712_REG_IRQSTAT 0x02 /* byte */ | |
54 | /* look to ICE1712_IRQ_* */ | |
55 | #define ICE1712_REG_INDEX 0x03 /* byte - indirect CCIxx regs */ | |
56 | #define ICE1712_REG_DATA 0x04 /* byte - indirect CCIxx regs */ | |
57 | #define ICE1712_REG_NMI_STAT1 0x05 /* byte */ | |
58 | #define ICE1712_REG_NMI_DATA 0x06 /* byte */ | |
59 | #define ICE1712_REG_NMI_INDEX 0x07 /* byte */ | |
60 | #define ICE1712_REG_AC97_INDEX 0x08 /* byte */ | |
61 | #define ICE1712_REG_AC97_CMD 0x09 /* byte */ | |
62 | #define ICE1712_AC97_COLD 0x80 /* cold reset */ | |
63 | #define ICE1712_AC97_WARM 0x40 /* warm reset */ | |
64 | #define ICE1712_AC97_WRITE 0x20 /* W: write, R: write in progress */ | |
65 | #define ICE1712_AC97_READ 0x10 /* W: read, R: read in progress */ | |
66 | #define ICE1712_AC97_READY 0x08 /* codec ready status bit */ | |
67 | #define ICE1712_AC97_PBK_VSR 0x02 /* playback VSR */ | |
68 | #define ICE1712_AC97_CAP_VSR 0x01 /* capture VSR */ | |
69 | #define ICE1712_REG_AC97_DATA 0x0a /* word (little endian) */ | |
70 | #define ICE1712_REG_MPU1_CTRL 0x0c /* byte */ | |
71 | #define ICE1712_REG_MPU1_DATA 0x0d /* byte */ | |
72 | #define ICE1712_REG_I2C_DEV_ADDR 0x10 /* byte */ | |
73 | #define ICE1712_I2C_WRITE 0x01 /* write direction */ | |
74 | #define ICE1712_REG_I2C_BYTE_ADDR 0x11 /* byte */ | |
75 | #define ICE1712_REG_I2C_DATA 0x12 /* byte */ | |
76 | #define ICE1712_REG_I2C_CTRL 0x13 /* byte */ | |
77 | #define ICE1712_I2C_EEPROM 0x80 /* EEPROM exists */ | |
78 | #define ICE1712_I2C_BUSY 0x01 /* busy bit */ | |
79 | #define ICE1712_REG_CONCAP_ADDR 0x14 /* dword - consumer capture */ | |
80 | #define ICE1712_REG_CONCAP_COUNT 0x18 /* word - current/base count */ | |
81 | #define ICE1712_REG_SERR_SHADOW 0x1b /* byte */ | |
82 | #define ICE1712_REG_MPU2_CTRL 0x1c /* byte */ | |
83 | #define ICE1712_REG_MPU2_DATA 0x1d /* byte */ | |
84 | #define ICE1712_REG_TIMER 0x1e /* word */ | |
85 | ||
86 | /* | |
87 | * Indirect registers | |
88 | */ | |
89 | ||
90 | #define ICE1712_IREG_PBK_COUNT_LO 0x00 | |
91 | #define ICE1712_IREG_PBK_COUNT_HI 0x01 | |
92 | #define ICE1712_IREG_PBK_CTRL 0x02 | |
93 | #define ICE1712_IREG_PBK_LEFT 0x03 /* left volume */ | |
94 | #define ICE1712_IREG_PBK_RIGHT 0x04 /* right volume */ | |
95 | #define ICE1712_IREG_PBK_SOFT 0x05 /* soft volume */ | |
96 | #define ICE1712_IREG_PBK_RATE_LO 0x06 | |
97 | #define ICE1712_IREG_PBK_RATE_MID 0x07 | |
98 | #define ICE1712_IREG_PBK_RATE_HI 0x08 | |
99 | #define ICE1712_IREG_CAP_COUNT_LO 0x10 | |
100 | #define ICE1712_IREG_CAP_COUNT_HI 0x11 | |
101 | #define ICE1712_IREG_CAP_CTRL 0x12 | |
102 | #define ICE1712_IREG_GPIO_DATA 0x20 | |
103 | #define ICE1712_IREG_GPIO_WRITE_MASK 0x21 | |
104 | #define ICE1712_IREG_GPIO_DIRECTION 0x22 | |
105 | #define ICE1712_IREG_CONSUMER_POWERDOWN 0x30 | |
106 | #define ICE1712_IREG_PRO_POWERDOWN 0x31 | |
107 | ||
108 | /* | |
109 | * Consumer section direct DMA registers | |
110 | */ | |
111 | ||
112 | #define ICEDS(ice, x) ((ice)->dmapath_port + ICE1712_DS_##x) | |
113 | ||
114 | #define ICE1712_DS_INTMASK 0x00 /* word - interrupt mask */ | |
115 | #define ICE1712_DS_INTSTAT 0x02 /* word - interrupt status */ | |
116 | #define ICE1712_DS_DATA 0x04 /* dword - channel data */ | |
117 | #define ICE1712_DS_INDEX 0x08 /* dword - channel index */ | |
118 | ||
119 | /* | |
120 | * Consumer section channel registers | |
121 | */ | |
122 | ||
123 | #define ICE1712_DSC_ADDR0 0x00 /* dword - base address 0 */ | |
124 | #define ICE1712_DSC_COUNT0 0x01 /* word - count 0 */ | |
125 | #define ICE1712_DSC_ADDR1 0x02 /* dword - base address 1 */ | |
126 | #define ICE1712_DSC_COUNT1 0x03 /* word - count 1 */ | |
127 | #define ICE1712_DSC_CONTROL 0x04 /* byte - control & status */ | |
128 | #define ICE1712_BUFFER1 0x80 /* buffer1 is active */ | |
129 | #define ICE1712_BUFFER1_AUTO 0x40 /* buffer1 auto init */ | |
130 | #define ICE1712_BUFFER0_AUTO 0x20 /* buffer0 auto init */ | |
131 | #define ICE1712_FLUSH 0x10 /* flush FIFO */ | |
132 | #define ICE1712_STEREO 0x08 /* stereo */ | |
133 | #define ICE1712_16BIT 0x04 /* 16-bit data */ | |
134 | #define ICE1712_PAUSE 0x02 /* pause */ | |
135 | #define ICE1712_START 0x01 /* start */ | |
136 | #define ICE1712_DSC_RATE 0x05 /* dword - rate */ | |
137 | #define ICE1712_DSC_VOLUME 0x06 /* word - volume control */ | |
138 | ||
139 | /* | |
140 | * Professional multi-track direct control registers | |
141 | */ | |
142 | ||
143 | #define ICEMT(ice, x) ((ice)->profi_port + ICE1712_MT_##x) | |
144 | ||
145 | #define ICE1712_MT_IRQ 0x00 /* byte - interrupt mask */ | |
146 | #define ICE1712_MULTI_CAPTURE 0x80 /* capture IRQ */ | |
147 | #define ICE1712_MULTI_PLAYBACK 0x40 /* playback IRQ */ | |
148 | #define ICE1712_MULTI_CAPSTATUS 0x02 /* capture IRQ status */ | |
149 | #define ICE1712_MULTI_PBKSTATUS 0x01 /* playback IRQ status */ | |
150 | #define ICE1712_MT_RATE 0x01 /* byte - sampling rate select */ | |
151 | #define ICE1712_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */ | |
152 | #define ICE1712_MT_I2S_FORMAT 0x02 /* byte - I2S data format */ | |
153 | #define ICE1712_MT_AC97_INDEX 0x04 /* byte - AC'97 index */ | |
154 | #define ICE1712_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */ | |
155 | /* look to ICE1712_AC97_* */ | |
156 | #define ICE1712_MT_AC97_DATA 0x06 /* word - AC'97 data */ | |
157 | #define ICE1712_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */ | |
158 | #define ICE1712_MT_PLAYBACK_SIZE 0x14 /* word - playback size */ | |
159 | #define ICE1712_MT_PLAYBACK_COUNT 0x16 /* word - playback count */ | |
160 | #define ICE1712_MT_PLAYBACK_CONTROL 0x18 /* byte - control */ | |
161 | #define ICE1712_CAPTURE_START_SHADOW 0x04 /* capture start */ | |
162 | #define ICE1712_PLAYBACK_PAUSE 0x02 /* playback pause */ | |
163 | #define ICE1712_PLAYBACK_START 0x01 /* playback start */ | |
164 | #define ICE1712_MT_CAPTURE_ADDR 0x20 /* dword - capture address */ | |
165 | #define ICE1712_MT_CAPTURE_SIZE 0x24 /* word - capture size */ | |
166 | #define ICE1712_MT_CAPTURE_COUNT 0x26 /* word - capture count */ | |
167 | #define ICE1712_MT_CAPTURE_CONTROL 0x28 /* byte - control */ | |
168 | #define ICE1712_CAPTURE_START 0x01 /* capture start */ | |
169 | #define ICE1712_MT_ROUTE_PSDOUT03 0x30 /* word */ | |
170 | #define ICE1712_MT_ROUTE_SPDOUT 0x32 /* word */ | |
171 | #define ICE1712_MT_ROUTE_CAPTURE 0x34 /* dword */ | |
172 | #define ICE1712_MT_MONITOR_VOLUME 0x38 /* word */ | |
173 | #define ICE1712_MT_MONITOR_INDEX 0x3a /* byte */ | |
174 | #define ICE1712_MT_MONITOR_RATE 0x3b /* byte */ | |
175 | #define ICE1712_MT_MONITOR_ROUTECTRL 0x3c /* byte */ | |
176 | #define ICE1712_ROUTE_AC97 0x01 /* route digital mixer output to AC'97 */ | |
177 | #define ICE1712_MT_MONITOR_PEAKINDEX 0x3e /* byte */ | |
178 | #define ICE1712_MT_MONITOR_PEAKDATA 0x3f /* byte */ | |
179 | ||
180 | /* | |
181 | * Codec configuration bits | |
182 | */ | |
183 | ||
184 | /* PCI[60] System Configuration */ | |
185 | #define ICE1712_CFG_CLOCK 0xc0 | |
186 | #define ICE1712_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */ | |
187 | #define ICE1712_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */ | |
188 | #define ICE1712_CFG_EXT 0x80 /* external clock */ | |
189 | #define ICE1712_CFG_2xMPU401 0x20 /* two MPU401 UARTs */ | |
190 | #define ICE1712_CFG_NO_CON_AC97 0x10 /* consumer AC'97 codec is not present */ | |
191 | #define ICE1712_CFG_ADC_MASK 0x0c /* one, two, three, four stereo ADCs */ | |
192 | #define ICE1712_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */ | |
193 | /* PCI[61] AC-Link Configuration */ | |
194 | #define ICE1712_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */ | |
195 | #define ICE1712_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */ | |
196 | /* PCI[62] I2S Features */ | |
197 | #define ICE1712_CFG_I2S_VOLUME 0x80 /* volume/mute capability */ | |
198 | #define ICE1712_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */ | |
199 | #define ICE1712_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */ | |
200 | #define ICE1712_CFG_I2S_OTHER 0x0f /* other I2S IDs */ | |
201 | /* PCI[63] S/PDIF Configuration */ | |
202 | #define ICE1712_CFG_I2S_CHIPID 0xfc /* I2S chip ID */ | |
203 | #define ICE1712_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */ | |
204 | #define ICE1712_CFG_SPDIF_OUT 0x01 /* S/PDIF output is present */ | |
205 | ||
206 | /* | |
207 | * DMA mode values | |
208 | * identical with DMA_XXX on i386 architecture. | |
209 | */ | |
210 | #define ICE1712_DMA_MODE_WRITE 0x48 | |
211 | #define ICE1712_DMA_AUTOINIT 0x10 | |
212 | ||
213 | ||
214 | /* | |
215 | * | |
216 | */ | |
217 | ||
218 | typedef struct _snd_ice1712 ice1712_t; | |
219 | ||
220 | typedef struct { | |
221 | unsigned int subvendor; /* PCI[2c-2f] */ | |
222 | unsigned char size; /* size of EEPROM image in bytes */ | |
223 | unsigned char version; /* must be 1 (or 2 for vt1724) */ | |
224 | unsigned char data[32]; | |
225 | unsigned int gpiomask; | |
226 | unsigned int gpiostate; | |
227 | unsigned int gpiodir; | |
228 | } ice1712_eeprom_t; | |
229 | ||
230 | enum { | |
231 | ICE_EEP1_CODEC = 0, /* 06 */ | |
232 | ICE_EEP1_ACLINK, /* 07 */ | |
233 | ICE_EEP1_I2SID, /* 08 */ | |
234 | ICE_EEP1_SPDIF, /* 09 */ | |
235 | ICE_EEP1_GPIO_MASK, /* 0a */ | |
236 | ICE_EEP1_GPIO_STATE, /* 0b */ | |
237 | ICE_EEP1_GPIO_DIR, /* 0c */ | |
238 | ICE_EEP1_AC97_MAIN_LO, /* 0d */ | |
239 | ICE_EEP1_AC97_MAIN_HI, /* 0e */ | |
240 | ICE_EEP1_AC97_PCM_LO, /* 0f */ | |
241 | ICE_EEP1_AC97_PCM_HI, /* 10 */ | |
242 | ICE_EEP1_AC97_REC_LO, /* 11 */ | |
243 | ICE_EEP1_AC97_REC_HI, /* 12 */ | |
244 | ICE_EEP1_AC97_RECSRC, /* 13 */ | |
245 | ICE_EEP1_DAC_ID, /* 14 */ | |
246 | ICE_EEP1_DAC_ID1, | |
247 | ICE_EEP1_DAC_ID2, | |
248 | ICE_EEP1_DAC_ID3, | |
249 | ICE_EEP1_ADC_ID, /* 18 */ | |
250 | ICE_EEP1_ADC_ID1, | |
251 | ICE_EEP1_ADC_ID2, | |
252 | ICE_EEP1_ADC_ID3 | |
253 | }; | |
254 | ||
255 | #define ice_has_con_ac97(ice) (!((ice)->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) | |
256 | ||
257 | ||
258 | struct snd_ak4xxx_private { | |
259 | unsigned int cif: 1; /* CIF mode */ | |
260 | unsigned char caddr; /* C0 and C1 bits */ | |
261 | unsigned int data_mask; /* DATA gpio bit */ | |
262 | unsigned int clk_mask; /* CLK gpio bit */ | |
263 | unsigned int cs_mask; /* bit mask for select/deselect address */ | |
264 | unsigned int cs_addr; /* bits to select address */ | |
265 | unsigned int cs_none; /* bits to deselect address */ | |
266 | unsigned int add_flags; /* additional bits at init */ | |
267 | unsigned int mask_flags; /* total mask bits */ | |
268 | struct snd_akm4xxx_ops { | |
269 | void (*set_rate_val)(akm4xxx_t *ak, unsigned int rate); | |
270 | } ops; | |
271 | }; | |
272 | ||
273 | struct snd_ice1712_spdif { | |
274 | unsigned char cs8403_bits; | |
275 | unsigned char cs8403_stream_bits; | |
276 | snd_kcontrol_t *stream_ctl; | |
277 | ||
278 | struct snd_ice1712_spdif_ops { | |
279 | void (*open)(ice1712_t *, snd_pcm_substream_t *); | |
280 | void (*setup_rate)(ice1712_t *, int rate); | |
281 | void (*close)(ice1712_t *, snd_pcm_substream_t *); | |
282 | void (*default_get)(ice1712_t *, snd_ctl_elem_value_t * ucontrol); | |
283 | int (*default_put)(ice1712_t *, snd_ctl_elem_value_t * ucontrol); | |
284 | void (*stream_get)(ice1712_t *, snd_ctl_elem_value_t * ucontrol); | |
285 | int (*stream_put)(ice1712_t *, snd_ctl_elem_value_t * ucontrol); | |
286 | } ops; | |
287 | }; | |
288 | ||
289 | ||
290 | struct _snd_ice1712 { | |
291 | unsigned long conp_dma_size; | |
292 | unsigned long conc_dma_size; | |
293 | unsigned long prop_dma_size; | |
294 | unsigned long proc_dma_size; | |
295 | int irq; | |
296 | ||
297 | unsigned long port; | |
298 | unsigned long ddma_port; | |
299 | unsigned long dmapath_port; | |
300 | unsigned long profi_port; | |
301 | ||
302 | struct pci_dev *pci; | |
303 | snd_card_t *card; | |
304 | snd_pcm_t *pcm; | |
305 | snd_pcm_t *pcm_ds; | |
306 | snd_pcm_t *pcm_pro; | |
307 | snd_pcm_substream_t *playback_con_substream; | |
308 | snd_pcm_substream_t *playback_con_substream_ds[6]; | |
309 | snd_pcm_substream_t *capture_con_substream; | |
310 | snd_pcm_substream_t *playback_pro_substream; | |
311 | snd_pcm_substream_t *capture_pro_substream; | |
312 | unsigned int playback_pro_size; | |
313 | unsigned int capture_pro_size; | |
314 | unsigned int playback_con_virt_addr[6]; | |
315 | unsigned int playback_con_active_buf[6]; | |
316 | unsigned int capture_con_virt_addr; | |
317 | unsigned int ac97_ext_id; | |
318 | ac97_t *ac97; | |
319 | snd_rawmidi_t *rmidi[2]; | |
320 | ||
321 | spinlock_t reg_lock; | |
322 | snd_info_entry_t *proc_entry; | |
323 | ||
324 | ice1712_eeprom_t eeprom; | |
325 | ||
326 | unsigned int pro_volumes[20]; | |
327 | unsigned int omni: 1; /* Delta Omni I/O */ | |
328 | unsigned int vt1724: 1; | |
329 | unsigned int vt1720: 1; | |
330 | unsigned int has_spdif: 1; /* VT1720/4 - has SPDIF I/O */ | |
331 | unsigned int force_pdma4: 1; /* VT1720/4 - PDMA4 as non-spdif */ | |
332 | unsigned int force_rdma1: 1; /* VT1720/4 - RDMA1 as non-spdif */ | |
333 | unsigned int num_total_dacs; /* total DACs */ | |
334 | unsigned int num_total_adcs; /* total ADCs */ | |
335 | unsigned int cur_rate; /* current rate */ | |
336 | ||
337 | struct semaphore open_mutex; | |
338 | snd_pcm_substream_t *pcm_reserved[4]; | |
339 | snd_pcm_hw_constraint_list_t *hw_rates; /* card-specific rate constraints */ | |
340 | ||
341 | unsigned int akm_codecs; | |
342 | akm4xxx_t *akm; | |
343 | struct snd_ice1712_spdif spdif; | |
344 | ||
345 | struct semaphore i2c_mutex; /* I2C mutex for ICE1724 registers */ | |
346 | snd_i2c_bus_t *i2c; /* I2C bus */ | |
347 | snd_i2c_device_t *cs8427; /* CS8427 I2C device */ | |
348 | unsigned int cs8427_timeout; /* CS8427 reset timeout in HZ/100 */ | |
349 | ||
350 | struct ice1712_gpio { | |
351 | unsigned int direction; /* current direction bits */ | |
352 | unsigned int write_mask; /* current mask bits */ | |
353 | unsigned int saved[2]; /* for ewx_i2c */ | |
354 | /* operators */ | |
355 | void (*set_mask)(ice1712_t *ice, unsigned int data); | |
356 | void (*set_dir)(ice1712_t *ice, unsigned int data); | |
357 | void (*set_data)(ice1712_t *ice, unsigned int data); | |
358 | unsigned int (*get_data)(ice1712_t *ice); | |
359 | /* misc operators - move to another place? */ | |
360 | void (*set_pro_rate)(ice1712_t *ice, unsigned int rate); | |
361 | void (*i2s_mclk_changed)(ice1712_t *ice); | |
362 | } gpio; | |
363 | struct semaphore gpio_mutex; | |
364 | ||
365 | /* other board-specific data */ | |
366 | union { | |
367 | /* additional i2c devices for EWS boards */ | |
368 | snd_i2c_device_t *i2cdevs[3]; | |
369 | /* AC97 register cache for Aureon */ | |
370 | struct aureon_spec { | |
371 | unsigned short stac9744[64]; | |
372 | unsigned int cs8415_mux; | |
373 | unsigned short master[2]; | |
374 | unsigned short vol[8]; | |
375 | } aureon; | |
376 | /* Hoontech-specific setting */ | |
377 | struct hoontech_spec { | |
378 | unsigned char boxbits[4]; | |
379 | unsigned int config; | |
380 | unsigned short boxconfig[4]; | |
381 | } hoontech; | |
382 | struct { | |
383 | ak4114_t *ak4114; | |
384 | unsigned int analog: 1; | |
385 | } juli; | |
386 | } spec; | |
387 | ||
388 | }; | |
389 | ||
390 | ||
391 | /* | |
392 | * gpio access functions | |
393 | */ | |
394 | static inline void snd_ice1712_gpio_set_dir(ice1712_t *ice, unsigned int bits) | |
395 | { | |
396 | ice->gpio.set_dir(ice, bits); | |
397 | } | |
398 | ||
399 | static inline void snd_ice1712_gpio_set_mask(ice1712_t *ice, unsigned int bits) | |
400 | { | |
401 | ice->gpio.set_mask(ice, bits); | |
402 | } | |
403 | ||
404 | static inline void snd_ice1712_gpio_write(ice1712_t *ice, unsigned int val) | |
405 | { | |
406 | ice->gpio.set_data(ice, val); | |
407 | } | |
408 | ||
409 | static inline unsigned int snd_ice1712_gpio_read(ice1712_t *ice) | |
410 | { | |
411 | return ice->gpio.get_data(ice); | |
412 | } | |
413 | ||
414 | /* | |
415 | * save and restore gpio status | |
416 | * The access to gpio will be protected by mutex, so don't forget to | |
417 | * restore! | |
418 | */ | |
419 | static inline void snd_ice1712_save_gpio_status(ice1712_t *ice) | |
420 | { | |
421 | down(&ice->gpio_mutex); | |
422 | ice->gpio.saved[0] = ice->gpio.direction; | |
423 | ice->gpio.saved[1] = ice->gpio.write_mask; | |
424 | } | |
425 | ||
426 | static inline void snd_ice1712_restore_gpio_status(ice1712_t *ice) | |
427 | { | |
428 | ice->gpio.set_dir(ice, ice->gpio.saved[0]); | |
429 | ice->gpio.set_mask(ice, ice->gpio.saved[1]); | |
430 | ice->gpio.direction = ice->gpio.saved[0]; | |
431 | ice->gpio.write_mask = ice->gpio.saved[1]; | |
432 | up(&ice->gpio_mutex); | |
433 | } | |
434 | ||
435 | /* for bit controls */ | |
436 | #define ICE1712_GPIO(xiface, xname, xindex, mask, invert, xaccess) \ | |
437 | { .iface = xiface, .name = xname, .access = xaccess, .info = snd_ice1712_gpio_info, \ | |
438 | .get = snd_ice1712_gpio_get, .put = snd_ice1712_gpio_put, \ | |
439 | .private_value = mask | (invert << 24) } | |
440 | ||
441 | int snd_ice1712_gpio_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo); | |
442 | int snd_ice1712_gpio_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol); | |
443 | int snd_ice1712_gpio_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol); | |
444 | ||
445 | /* | |
446 | * set gpio direction, write mask and data | |
447 | */ | |
448 | static inline void snd_ice1712_gpio_write_bits(ice1712_t *ice, unsigned int mask, unsigned int bits) | |
449 | { | |
450 | ice->gpio.direction |= mask; | |
451 | snd_ice1712_gpio_set_dir(ice, ice->gpio.direction); | |
452 | snd_ice1712_gpio_set_mask(ice, ~mask); | |
453 | snd_ice1712_gpio_write(ice, mask & bits); | |
454 | } | |
455 | ||
456 | int snd_ice1712_spdif_build_controls(ice1712_t *ice); | |
457 | ||
458 | int snd_ice1712_akm4xxx_init(akm4xxx_t *ak, const akm4xxx_t *template, const struct snd_ak4xxx_private *priv, ice1712_t *ice); | |
459 | void snd_ice1712_akm4xxx_free(ice1712_t *ice); | |
460 | int snd_ice1712_akm4xxx_build_controls(ice1712_t *ice); | |
461 | ||
462 | int snd_ice1712_init_cs8427(ice1712_t *ice, int addr); | |
463 | ||
464 | static inline void snd_ice1712_write(ice1712_t * ice, u8 addr, u8 data) | |
465 | { | |
466 | outb(addr, ICEREG(ice, INDEX)); | |
467 | outb(data, ICEREG(ice, DATA)); | |
468 | } | |
469 | ||
470 | static inline u8 snd_ice1712_read(ice1712_t * ice, u8 addr) | |
471 | { | |
472 | outb(addr, ICEREG(ice, INDEX)); | |
473 | return inb(ICEREG(ice, DATA)); | |
474 | } | |
475 | ||
476 | ||
477 | /* | |
478 | * entry pointer | |
479 | */ | |
480 | ||
481 | struct snd_ice1712_card_info { | |
482 | unsigned int subvendor; | |
483 | char *name; | |
484 | char *model; | |
485 | char *driver; | |
486 | int (*chip_init)(ice1712_t *); | |
487 | int (*build_controls)(ice1712_t *); | |
488 | unsigned int no_mpu401: 1; | |
489 | unsigned int eeprom_size; | |
490 | unsigned char *eeprom_data; | |
491 | }; | |
492 | ||
493 | ||
494 | #endif /* __SOUND_ICE1712_H */ |