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module: remove never implemented MODULE_SUPPORTED_DEVICE
[mirror_ubuntu-jammy-kernel.git] / sound / pci / ice1712 / ice1724.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 * ALSA driver for VT1724 ICEnsemble ICE1724 / VIA VT1724 (Envy24HT)
4 * VIA VT1720 (Envy24PT)
5 *
c1017a4c 6 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
1da177e4
LT		 7 * 2002 James Stafford <jstafford@ampltd.com>
8 * 2003 Takashi Iwai <tiwai@suse.de>
1de9fdc2 9 */
1da177e4 10
1da177e4
LT		 11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/slab.h>
65a77217 16#include <linux/module.h>
62932df8 17#include <linux/mutex.h>
1da177e4
LT		 18#include <sound/core.h>
19#include <sound/info.h>
aea3bfbc 20#include <sound/rawmidi.h>
1da177e4
LT		 21#include <sound/initval.h>
22
23#include <sound/asoundef.h>
24
25#include "ice1712.h"
26#include "envy24ht.h"
27
28/* lowlevel routines */
29#include "amp.h"
30#include "revo.h"
31#include "aureon.h"
32#include "vt1720_mobo.h"
33#include "pontis.h"
34#include "prodigy192.h"
6b8d6e55 35#include "prodigy_hifi.h"
1da177e4 36#include "juli.h"
72cbfd45 37#include "maya44.h"
1da177e4 38#include "phase.h"
f6cdab5f 39#include "wtm.h"
f31639b8 40#include "se.h"
6ef80706 41#include "quartet.h"
77b0b254 42#include "psc724.h"
1da177e4 43
c1017a4c 44MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
1da177e4
LT		 45MODULE_DESCRIPTION("VIA ICEnsemble ICE1724/1720 (Envy24HT/PT)");
46MODULE_LICENSE("GPL");
1da177e4
LT		 47
48static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
49static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
a67ff6a5 50static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
1da177e4
LT		 51static char *model[SNDRV_CARDS];
52
53module_param_array(index, int, NULL, 0444);
54MODULE_PARM_DESC(index, "Index value for ICE1724 soundcard.");
55module_param_array(id, charp, NULL, 0444);
56MODULE_PARM_DESC(id, "ID string for ICE1724 soundcard.");
57module_param_array(enable, bool, NULL, 0444);
58MODULE_PARM_DESC(enable, "Enable ICE1724 soundcard.");
59module_param_array(model, charp, NULL, 0444);
60MODULE_PARM_DESC(model, "Use the given board model.");
61
1da177e4
LT		 62
63/* Both VT1720 and VT1724 have the same PCI IDs */
9baa3c34 64static const struct pci_device_id snd_vt1724_ids[] = {
28d27aae 65 { PCI_VDEVICE(ICE, PCI_DEVICE_ID_VT1724), 0 },
1da177e4
LT		 66 { 0, }
67};
68
69MODULE_DEVICE_TABLE(pci, snd_vt1724_ids);
70
71
72static int PRO_RATE_LOCKED;
73static int PRO_RATE_RESET = 1;
74static unsigned int PRO_RATE_DEFAULT = 44100;
75
a2af050f 76static const char * const ext_clock_names[1] = { "IEC958 In" };
1ff97cb9 77
1da177e4
LT		 78/*
79 * Basic I/O
80 */
1de9fdc2 81
d16be8ed
PH		 82/*
83 * default rates, default clock routines
84 */
85
1da177e4 86/* check whether the clock mode is spdif-in */
d16be8ed 87static inline int stdclock_is_spdif_master(struct snd_ice1712 *ice)
1da177e4
LT		 88{
89 return (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER) ? 1 : 0;
90}
91
6796d5a0
PH		 92/*
93 * locking rate makes sense only for internal clock mode
94 */
ab0c7d72 95static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
1da177e4 96{
6796d5a0 97 return (!ice->is_spdif_master(ice)) && PRO_RATE_LOCKED;
1da177e4
LT		 98}
99
100/*
101 * ac97 section
102 */
103
ab0c7d72 104static unsigned char snd_vt1724_ac97_ready(struct snd_ice1712 *ice)
1da177e4
LT		 105{
106 unsigned char old_cmd;
107 int tm;
108 for (tm = 0; tm < 0x10000; tm++) {
109 old_cmd = inb(ICEMT1724(ice, AC97_CMD));
110 if (old_cmd & (VT1724_AC97_WRITE | VT1724_AC97_READ))
111 continue;
112 if (!(old_cmd & VT1724_AC97_READY))
113 continue;
114 return old_cmd;
115 }
6dfb5aff 116 dev_dbg(ice->card->dev, "snd_vt1724_ac97_ready: timeout\n");
1da177e4
LT		 117 return old_cmd;
118}
119
ab0c7d72 120static int snd_vt1724_ac97_wait_bit(struct snd_ice1712 *ice, unsigned char bit)
1da177e4
LT		 121{
122 int tm;
123 for (tm = 0; tm < 0x10000; tm++)
124 if ((inb(ICEMT1724(ice, AC97_CMD)) & bit) == 0)
125 return 0;
6dfb5aff 126 dev_dbg(ice->card->dev, "snd_vt1724_ac97_wait_bit: timeout\n");
1da177e4
LT		 127 return -EIO;
128}
129
ab0c7d72 130static void snd_vt1724_ac97_write(struct snd_ac97 *ac97,
1da177e4
LT		 131 unsigned short reg,
132 unsigned short val)
133{
ab0c7d72 134 struct snd_ice1712 *ice = ac97->private_data;
1da177e4
LT		 135 unsigned char old_cmd;
136
137 old_cmd = snd_vt1724_ac97_ready(ice);
138 old_cmd &= ~VT1724_AC97_ID_MASK;
139 old_cmd |= ac97->num;
140 outb(reg, ICEMT1724(ice, AC97_INDEX));
141 outw(val, ICEMT1724(ice, AC97_DATA));
142 outb(old_cmd | VT1724_AC97_WRITE, ICEMT1724(ice, AC97_CMD));
143 snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_WRITE);
144}
145
ab0c7d72 146static unsigned short snd_vt1724_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1da177e4 147{
ab0c7d72 148 struct snd_ice1712 *ice = ac97->private_data;
1da177e4
LT		 149 unsigned char old_cmd;
150
151 old_cmd = snd_vt1724_ac97_ready(ice);
152 old_cmd &= ~VT1724_AC97_ID_MASK;
153 old_cmd |= ac97->num;
154 outb(reg, ICEMT1724(ice, AC97_INDEX));
155 outb(old_cmd | VT1724_AC97_READ, ICEMT1724(ice, AC97_CMD));
156 if (snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_READ) < 0)
157 return ~0;
158 return inw(ICEMT1724(ice, AC97_DATA));
159}
160
161
162/*
163 * GPIO operations
164 */
165
166/* set gpio direction 0 = read, 1 = write */
ab0c7d72 167static void snd_vt1724_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
1da177e4
LT		 168{
169 outl(data, ICEREG1724(ice, GPIO_DIRECTION));
170 inw(ICEREG1724(ice, GPIO_DIRECTION)); /* dummy read for pci-posting */
171}
172
49470306
PH		 173/* get gpio direction 0 = read, 1 = write */
174static unsigned int snd_vt1724_get_gpio_dir(struct snd_ice1712 *ice)
175{
176 return inl(ICEREG1724(ice, GPIO_DIRECTION));
177}
178
1da177e4 179/* set the gpio mask (0 = writable) */
ab0c7d72 180static void snd_vt1724_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
1da177e4
LT		 181{
182 outw(data, ICEREG1724(ice, GPIO_WRITE_MASK));
1de9fdc2 183 if (!ice->vt1720) /* VT1720 supports only 16 GPIO bits */
1da177e4
LT		 184 outb((data >> 16) & 0xff, ICEREG1724(ice, GPIO_WRITE_MASK_22));
185 inw(ICEREG1724(ice, GPIO_WRITE_MASK)); /* dummy read for pci-posting */
186}
187
49470306
PH		 188static unsigned int snd_vt1724_get_gpio_mask(struct snd_ice1712 *ice)
189{
190 unsigned int mask;
191 if (!ice->vt1720)
192 mask = (unsigned int)inb(ICEREG1724(ice, GPIO_WRITE_MASK_22));
193 else
194 mask = 0;
195 mask = (mask << 16) | inw(ICEREG1724(ice, GPIO_WRITE_MASK));
196 return mask;
197}
198
ab0c7d72 199static void snd_vt1724_set_gpio_data(struct snd_ice1712 *ice, unsigned int data)
1da177e4
LT		 200{
201 outw(data, ICEREG1724(ice, GPIO_DATA));
1de9fdc2 202 if (!ice->vt1720)
1da177e4
LT		 203 outb(data >> 16, ICEREG1724(ice, GPIO_DATA_22));
204 inw(ICEREG1724(ice, GPIO_DATA)); /* dummy read for pci-posting */
205}
206
ab0c7d72 207static unsigned int snd_vt1724_get_gpio_data(struct snd_ice1712 *ice)
1da177e4
LT		 208{
209 unsigned int data;
1de9fdc2 210 if (!ice->vt1720)
1da177e4
LT		 211 data = (unsigned int)inb(ICEREG1724(ice, GPIO_DATA_22));
212 else
213 data = 0;
214 data = (data << 16) | inw(ICEREG1724(ice, GPIO_DATA));
215 return data;
216}
217
3a841d51 218/*
aea3bfbc 219 * MIDI
3a841d51 220 */
aea3bfbc
CL		 221
222static void vt1724_midi_clear_rx(struct snd_ice1712 *ice)
223{
224 unsigned int count;
225
226 for (count = inb(ICEREG1724(ice, MPU_RXFIFO)); count > 0; --count)
227 inb(ICEREG1724(ice, MPU_DATA));
228}
229
230static inline struct snd_rawmidi_substream *
231get_rawmidi_substream(struct snd_ice1712 *ice, unsigned int stream)
3a841d51 232{
aea3bfbc
CL		 233 return list_first_entry(&ice->rmidi[0]->streams[stream].substreams,
234 struct snd_rawmidi_substream, list);
235}
236
e683ec46
TI		 237static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable);
238
aea3bfbc
CL		 239static void vt1724_midi_write(struct snd_ice1712 *ice)
240{
241 struct snd_rawmidi_substream *s;
242 int count, i;
243 u8 buffer[32];
244
245 s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_OUTPUT);
246 count = 31 - inb(ICEREG1724(ice, MPU_TXFIFO));
247 if (count > 0) {
248 count = snd_rawmidi_transmit(s, buffer, count);
249 for (i = 0; i < count; ++i)
250 outb(buffer[i], ICEREG1724(ice, MPU_DATA));
251 }
e683ec46
TI		 252 /* mask irq when all bytes have been transmitted.
253 * enabled again in output_trigger when the new data comes in.
254 */
255 enable_midi_irq(ice, VT1724_IRQ_MPU_TX,
256 !snd_rawmidi_transmit_empty(s));
aea3bfbc
CL		 257}
258
259static void vt1724_midi_read(struct snd_ice1712 *ice)
260{
261 struct snd_rawmidi_substream *s;
262 int count, i;
263 u8 buffer[32];
264
265 s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_INPUT);
266 count = inb(ICEREG1724(ice, MPU_RXFIFO));
267 if (count > 0) {
268 count = min(count, 32);
269 for (i = 0; i < count; ++i)
270 buffer[i] = inb(ICEREG1724(ice, MPU_DATA));
271 snd_rawmidi_receive(s, buffer, count);
272 }
273}
274
e683ec46
TI		 275/* call with ice->reg_lock */
276static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable)
aea3bfbc 277{
e683ec46 278 u8 mask = inb(ICEREG1724(ice, IRQMASK));
aea3bfbc
CL		 279 if (enable)
280 mask &= ~flag;
3a841d51 281 else
aea3bfbc
CL		 282 mask |= flag;
283 outb(mask, ICEREG1724(ice, IRQMASK));
e683ec46
TI		 284}
285
286static void vt1724_enable_midi_irq(struct snd_rawmidi_substream *substream,
287 u8 flag, int enable)
288{
289 struct snd_ice1712 *ice = substream->rmidi->private_data;
290
291 spin_lock_irq(&ice->reg_lock);
292 enable_midi_irq(ice, flag, enable);
aea3bfbc 293 spin_unlock_irq(&ice->reg_lock);
3a841d51
TI		 294}
295
aea3bfbc 296static int vt1724_midi_output_open(struct snd_rawmidi_substream *s)
3a841d51 297{
aea3bfbc
CL		 298 return 0;
299}
300
301static int vt1724_midi_output_close(struct snd_rawmidi_substream *s)
302{
aea3bfbc 303 return 0;
3a841d51
TI		 304}
305
aea3bfbc
CL		 306static void vt1724_midi_output_trigger(struct snd_rawmidi_substream *s, int up)
307{
308 struct snd_ice1712 *ice = s->rmidi->private_data;
309 unsigned long flags;
310
311 spin_lock_irqsave(&ice->reg_lock, flags);
312 if (up) {
313 ice->midi_output = 1;
314 vt1724_midi_write(ice);
315 } else {
316 ice->midi_output = 0;
e683ec46 317 enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
aea3bfbc
CL		 318 }
319 spin_unlock_irqrestore(&ice->reg_lock, flags);
320}
321
322static void vt1724_midi_output_drain(struct snd_rawmidi_substream *s)
323{
324 struct snd_ice1712 *ice = s->rmidi->private_data;
325 unsigned long timeout;
326
e683ec46 327 vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_TX, 0);
aea3bfbc
CL		 328 /* 32 bytes should be transmitted in less than about 12 ms */
329 timeout = jiffies + msecs_to_jiffies(15);
330 do {
331 if (inb(ICEREG1724(ice, MPU_CTRL)) & VT1724_MPU_TX_EMPTY)
332 break;
333 schedule_timeout_uninterruptible(1);
334 } while (time_after(timeout, jiffies));
335}
336
485885b9 337static const struct snd_rawmidi_ops vt1724_midi_output_ops = {
aea3bfbc
CL		 338 .open = vt1724_midi_output_open,
339 .close = vt1724_midi_output_close,
340 .trigger = vt1724_midi_output_trigger,
341 .drain = vt1724_midi_output_drain,
342};
343
344static int vt1724_midi_input_open(struct snd_rawmidi_substream *s)
345{
346 vt1724_midi_clear_rx(s->rmidi->private_data);
347 vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 1);
348 return 0;
349}
350
351static int vt1724_midi_input_close(struct snd_rawmidi_substream *s)
352{
353 vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 0);
354 return 0;
355}
356
357static void vt1724_midi_input_trigger(struct snd_rawmidi_substream *s, int up)
358{
359 struct snd_ice1712 *ice = s->rmidi->private_data;
360 unsigned long flags;
361
362 spin_lock_irqsave(&ice->reg_lock, flags);
363 if (up) {
364 ice->midi_input = 1;
365 vt1724_midi_read(ice);
366 } else {
367 ice->midi_input = 0;
368 }
369 spin_unlock_irqrestore(&ice->reg_lock, flags);
370}
371
485885b9 372static const struct snd_rawmidi_ops vt1724_midi_input_ops = {
aea3bfbc
CL		 373 .open = vt1724_midi_input_open,
374 .close = vt1724_midi_input_close,
375 .trigger = vt1724_midi_input_trigger,
376};
377
3a841d51 378
1da177e4
LT		 379/*
380 * Interrupt handler
381 */
382
7d12e780 383static irqreturn_t snd_vt1724_interrupt(int irq, void *dev_id)
1da177e4 384{
ab0c7d72 385 struct snd_ice1712 *ice = dev_id;
1da177e4 386 unsigned char status;
3a841d51
TI		 387 unsigned char status_mask =
388 VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX | VT1724_IRQ_MTPCM;
1da177e4 389 int handled = 0;
3a841d51 390 int timeout = 0;
1da177e4
LT		 391
392 while (1) {
393 status = inb(ICEREG1724(ice, IRQSTAT));
3a841d51 394 status &= status_mask;
1da177e4
LT		 395 if (status == 0)
396 break;
e683ec46 397 spin_lock(&ice->reg_lock);
3a841d51 398 if (++timeout > 10) {
1083206f 399 status = inb(ICEREG1724(ice, IRQSTAT));
6dfb5aff
TI		 400 dev_err(ice->card->dev,
401 "Too long irq loop, status = 0x%x\n", status);
1083206f 402 if (status & VT1724_IRQ_MPU_TX) {
6dfb5aff 403 dev_err(ice->card->dev, "Disabling MPU_TX\n");
e683ec46 404 enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
1083206f 405 }
e683ec46 406 spin_unlock(&ice->reg_lock);
3a841d51
TI		 407 break;
408 }
1de9fdc2 409 handled = 1;
3a841d51 410 if (status & VT1724_IRQ_MPU_TX) {
aea3bfbc
CL		 411 if (ice->midi_output)
412 vt1724_midi_write(ice);
e683ec46
TI		 413 else
414 enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
3a841d51
TI		 415 /* Due to mysterical reasons, MPU_TX is always
416 * generated (and can't be cleared) when a PCM
417 * playback is going. So let's ignore at the
418 * next loop.
419 */
420 status_mask &= ~VT1724_IRQ_MPU_TX;
421 }
422 if (status & VT1724_IRQ_MPU_RX) {
aea3bfbc
CL		 423 if (ice->midi_input)
424 vt1724_midi_read(ice);
425 else
426 vt1724_midi_clear_rx(ice);
1da177e4 427 }
3a841d51
TI		 428 /* ack MPU irq */
429 outb(status, ICEREG1724(ice, IRQSTAT));
e683ec46 430 spin_unlock(&ice->reg_lock);
1da177e4
LT		 431 if (status & VT1724_IRQ_MTPCM) {
432 /*
433 * Multi-track PCM
434 * PCM assignment are:
435 * Playback DMA0 (M/C) = playback_pro_substream
436 * Playback DMA1 = playback_con_substream_ds[0]
437 * Playback DMA2 = playback_con_substream_ds[1]
438 * Playback DMA3 = playback_con_substream_ds[2]
439 * Playback DMA4 (SPDIF) = playback_con_substream
440 * Record DMA0 = capture_pro_substream
441 * Record DMA1 = capture_con_substream
442 */
443 unsigned char mtstat = inb(ICEMT1724(ice, IRQ));
444 if (mtstat & VT1724_MULTI_PDMA0) {
445 if (ice->playback_pro_substream)
446 snd_pcm_period_elapsed(ice->playback_pro_substream);
447 }
448 if (mtstat & VT1724_MULTI_RDMA0) {
449 if (ice->capture_pro_substream)
450 snd_pcm_period_elapsed(ice->capture_pro_substream);
451 }
452 if (mtstat & VT1724_MULTI_PDMA1) {
453 if (ice->playback_con_substream_ds[0])
454 snd_pcm_period_elapsed(ice->playback_con_substream_ds[0]);
455 }
456 if (mtstat & VT1724_MULTI_PDMA2) {
457 if (ice->playback_con_substream_ds[1])
458 snd_pcm_period_elapsed(ice->playback_con_substream_ds[1]);
459 }
460 if (mtstat & VT1724_MULTI_PDMA3) {
461 if (ice->playback_con_substream_ds[2])
462 snd_pcm_period_elapsed(ice->playback_con_substream_ds[2]);
463 }
464 if (mtstat & VT1724_MULTI_PDMA4) {
465 if (ice->playback_con_substream)
466 snd_pcm_period_elapsed(ice->playback_con_substream);
467 }
468 if (mtstat & VT1724_MULTI_RDMA1) {
469 if (ice->capture_con_substream)
470 snd_pcm_period_elapsed(ice->capture_con_substream);
471 }
472 /* ack anyway to avoid freeze */
473 outb(mtstat, ICEMT1724(ice, IRQ));
474 /* ought to really handle this properly */
475 if (mtstat & VT1724_MULTI_FIFO_ERR) {
476 unsigned char fstat = inb(ICEMT1724(ice, DMA_FIFO_ERR));
1de9fdc2
AB		 477 outb(fstat, ICEMT1724(ice, DMA_FIFO_ERR));
478 outb(VT1724_MULTI_FIFO_ERR | inb(ICEMT1724(ice, DMA_INT_MASK)), ICEMT1724(ice, DMA_INT_MASK));
1da177e4
LT		 479 /* If I don't do this, I get machine lockup due to continual interrupts */
480 }
481
482 }
483 }
484 return IRQ_RETVAL(handled);
485}
486
487/*
488 * PCM code - professional part (multitrack)
489 */
490
965f19be 491static const unsigned int rates[] = {
1da177e4
LT		 492 8000, 9600, 11025, 12000, 16000, 22050, 24000,
493 32000, 44100, 48000, 64000, 88200, 96000,
494 176400, 192000,
495};
496
965f19be 497static const struct snd_pcm_hw_constraint_list hw_constraints_rates_96 = {
1da177e4
LT		 498 .count = ARRAY_SIZE(rates) - 2, /* up to 96000 */
499 .list = rates,
500 .mask = 0,
501};
502
965f19be 503static const struct snd_pcm_hw_constraint_list hw_constraints_rates_48 = {
1da177e4
LT		 504 .count = ARRAY_SIZE(rates) - 5, /* up to 48000 */
505 .list = rates,
506 .mask = 0,
507};
508
965f19be 509static const struct snd_pcm_hw_constraint_list hw_constraints_rates_192 = {
1da177e4
LT		 510 .count = ARRAY_SIZE(rates),
511 .list = rates,
512 .mask = 0,
513};
514
515struct vt1724_pcm_reg {
516 unsigned int addr; /* ADDR register offset */
517 unsigned int size; /* SIZE register offset */
518 unsigned int count; /* COUNT register offset */
519 unsigned int start; /* start & pause bit */
520};
521
ab0c7d72 522static int snd_vt1724_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 523{
ab0c7d72 524 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 525 unsigned char what;
526 unsigned char old;
ab0c7d72 527 struct snd_pcm_substream *s;
1da177e4
LT		 528
529 what = 0;
ef991b95 530 snd_pcm_group_for_each_entry(s, substream) {
29998d24
CL		 531 if (snd_pcm_substream_chip(s) == ice) {
532 const struct vt1724_pcm_reg *reg;
533 reg = s->runtime->private_data;
534 what |= reg->start;
535 snd_pcm_trigger_done(s, substream);
536 }
1da177e4
LT		 537 }
538
539 switch (cmd) {
540 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
541 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
542 spin_lock(&ice->reg_lock);
543 old = inb(ICEMT1724(ice, DMA_PAUSE));
544 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
545 old |= what;
546 else
547 old &= ~what;
548 outb(old, ICEMT1724(ice, DMA_PAUSE));
549 spin_unlock(&ice->reg_lock);
550 break;
551
552 case SNDRV_PCM_TRIGGER_START:
553 case SNDRV_PCM_TRIGGER_STOP:
b40e9538 554 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 555 spin_lock(&ice->reg_lock);
556 old = inb(ICEMT1724(ice, DMA_CONTROL));
557 if (cmd == SNDRV_PCM_TRIGGER_START)
558 old |= what;
559 else
560 old &= ~what;
561 outb(old, ICEMT1724(ice, DMA_CONTROL));
562 spin_unlock(&ice->reg_lock);
563 break;
564
b40e9538
IC		 565 case SNDRV_PCM_TRIGGER_RESUME:
566 /* apps will have to restart stream */
567 break;
568
1da177e4
LT		 569 default:
570 return -EINVAL;
571 }
572 return 0;
573}
574
575/*
576 */
577
578#define DMA_STARTS (VT1724_RDMA0_START|VT1724_PDMA0_START|VT1724_RDMA1_START|\
579 VT1724_PDMA1_START|VT1724_PDMA2_START|VT1724_PDMA3_START|VT1724_PDMA4_START)
580#define DMA_PAUSES (VT1724_RDMA0_PAUSE|VT1724_PDMA0_PAUSE|VT1724_RDMA1_PAUSE|\
581 VT1724_PDMA1_PAUSE|VT1724_PDMA2_PAUSE|VT1724_PDMA3_PAUSE|VT1724_PDMA4_PAUSE)
582
d16be8ed
PH		 583static const unsigned int stdclock_rate_list[16] = {
584 48000, 24000, 12000, 9600, 32000, 16000, 8000, 96000, 44100,
585 22050, 11025, 88200, 176400, 0, 192000, 64000
586};
587
588static unsigned int stdclock_get_rate(struct snd_ice1712 *ice)
1da177e4 589{
44cc4a01 590 return stdclock_rate_list[inb(ICEMT1724(ice, RATE)) & 15];
d16be8ed
PH		 591}
592
593static void stdclock_set_rate(struct snd_ice1712 *ice, unsigned int rate)
594{
595 int i;
596 for (i = 0; i < ARRAY_SIZE(stdclock_rate_list); i++) {
597 if (stdclock_rate_list[i] == rate) {
598 outb(i, ICEMT1724(ice, RATE));
599 return;
600 }
601 }
602}
603
604static unsigned char stdclock_set_mclk(struct snd_ice1712 *ice,
605 unsigned int rate)
606{
607 unsigned char val, old;
608 /* check MT02 */
1da177e4 609 if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
d16be8ed
PH		 610 val = old = inb(ICEMT1724(ice, I2S_FORMAT));
611 if (rate > 96000)
612 val |= VT1724_MT_I2S_MCLK_128X; /* 128x MCLK */
1da177e4 613 else
d16be8ed
PH		 614 val &= ~VT1724_MT_I2S_MCLK_128X; /* 256x MCLK */
615 if (val != old) {
616 outb(val, ICEMT1724(ice, I2S_FORMAT));
617 /* master clock changed */
618 return 1;
619 }
620 }
621 /* no change in master clock */
622 return 0;
1da177e4
LT		 623}
624
92d71005 625static int snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
ab0c7d72 626 int force)
1da177e4
LT		 627{
628 unsigned long flags;
d16be8ed
PH		 629 unsigned char mclk_change;
630 unsigned int i, old_rate;
0aec96f5 631 bool call_set_rate = false;
1da177e4 632
d16be8ed 633 if (rate > ice->hw_rates->list[ice->hw_rates->count - 1])
92d71005
TI		 634 return -EINVAL;
635
1da177e4 636 spin_lock_irqsave(&ice->reg_lock, flags);
d16be8ed 637 if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) ||
1da177e4
LT		 638 (inb(ICEMT1724(ice, DMA_PAUSE)) & DMA_PAUSES)) {
639 /* running? we cannot change the rate now... */
640 spin_unlock_irqrestore(&ice->reg_lock, flags);
bd3c200e 641 return ((rate == ice->cur_rate) && !force) ? 0 : -EBUSY;
1da177e4
LT		 642 }
643 if (!force && is_pro_rate_locked(ice)) {
6796d5a0
PH		 644 /* comparing required and current rate - makes sense for
645 * internal clock only */
1da177e4 646 spin_unlock_irqrestore(&ice->reg_lock, flags);
92d71005 647 return (rate == ice->cur_rate) ? 0 : -EBUSY;
1da177e4
LT		 648 }
649
6796d5a0
PH		 650 if (force || !ice->is_spdif_master(ice)) {
651 /* force means the rate was switched by ucontrol, otherwise
652 * setting clock rate for internal clock mode */
653 old_rate = ice->get_rate(ice);
654 if (force || (old_rate != rate))
0aec96f5 655 call_set_rate = true;
6796d5a0
PH		 656 else if (rate == ice->cur_rate) {
657 spin_unlock_irqrestore(&ice->reg_lock, flags);
658 return 0;
659 }
1da177e4
LT		 660 }
661
662 ice->cur_rate = rate;
0aec96f5
TI		 663 spin_unlock_irqrestore(&ice->reg_lock, flags);
664
665 if (call_set_rate)
666 ice->set_rate(ice, rate);
1da177e4 667
d16be8ed
PH		 668 /* setting master clock */
669 mclk_change = ice->set_mclk(ice, rate);
670
1da177e4
LT		 671 if (mclk_change && ice->gpio.i2s_mclk_changed)
672 ice->gpio.i2s_mclk_changed(ice);
673 if (ice->gpio.set_pro_rate)
674 ice->gpio.set_pro_rate(ice, rate);
675
676 /* set up codecs */
677 for (i = 0; i < ice->akm_codecs; i++) {
678 if (ice->akm[i].ops.set_rate_val)
679 ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
680 }
681 if (ice->spdif.ops.setup_rate)
682 ice->spdif.ops.setup_rate(ice, rate);
92d71005
TI		 683
684 return 0;
1da177e4
LT		 685}
686
ab0c7d72
TI		 687static int snd_vt1724_pcm_hw_params(struct snd_pcm_substream *substream,
688 struct snd_pcm_hw_params *hw_params)
1da177e4 689{
ab0c7d72 690 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
09e263cd 691 int i, chs;
1da177e4
LT		 692
693 chs = params_channels(hw_params);
62932df8 694 mutex_lock(&ice->open_mutex);
1da177e4
LT		 695 /* mark surround channels */
696 if (substream == ice->playback_pro_substream) {
697 /* PDMA0 can be multi-channel up to 8 */
698 chs = chs / 2 - 1;
699 for (i = 0; i < chs; i++) {
ab0c7d72
TI		 700 if (ice->pcm_reserved[i] &&
701 ice->pcm_reserved[i] != substream) {
62932df8 702 mutex_unlock(&ice->open_mutex);
1da177e4
LT		 703 return -EBUSY;
704 }
705 ice->pcm_reserved[i] = substream;
706 }
707 for (; i < 3; i++) {
708 if (ice->pcm_reserved[i] == substream)
709 ice->pcm_reserved[i] = NULL;
710 }
711 } else {
712 for (i = 0; i < 3; i++) {
713 /* check individual playback stream */
714 if (ice->playback_con_substream_ds[i] == substream) {
ab0c7d72
TI		 715 if (ice->pcm_reserved[i] &&
716 ice->pcm_reserved[i] != substream) {
62932df8 717 mutex_unlock(&ice->open_mutex);
1da177e4
LT		 718 return -EBUSY;
719 }
720 ice->pcm_reserved[i] = substream;
721 break;
722 }
723 }
724 }
62932df8 725 mutex_unlock(&ice->open_mutex);
92d71005 726
09e263cd 727 return snd_vt1724_set_pro_rate(ice, params_rate(hw_params), 0);
1da177e4
LT		 728}
729
ab0c7d72 730static int snd_vt1724_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4 731{
ab0c7d72 732 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 733 int i;
734
62932df8 735 mutex_lock(&ice->open_mutex);
1da177e4
LT		 736 /* unmark surround channels */
737 for (i = 0; i < 3; i++)
738 if (ice->pcm_reserved[i] == substream)
739 ice->pcm_reserved[i] = NULL;
62932df8 740 mutex_unlock(&ice->open_mutex);
09e263cd 741 return 0;
1da177e4
LT		 742}
743
ab0c7d72 744static int snd_vt1724_playback_pro_prepare(struct snd_pcm_substream *substream)
1da177e4 745{
ab0c7d72 746 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 747 unsigned char val;
748 unsigned int size;
749
750 spin_lock_irq(&ice->reg_lock);
751 val = (8 - substream->runtime->channels) >> 1;
752 outb(val, ICEMT1724(ice, BURST));
753
754 outl(substream->runtime->dma_addr, ICEMT1724(ice, PLAYBACK_ADDR));
755
756 size = (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1;
1de9fdc2 757 /* outl(size, ICEMT1724(ice, PLAYBACK_SIZE)); */
1da177e4
LT		 758 outw(size, ICEMT1724(ice, PLAYBACK_SIZE));
759 outb(size >> 16, ICEMT1724(ice, PLAYBACK_SIZE) + 2);
760 size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
1de9fdc2 761 /* outl(size, ICEMT1724(ice, PLAYBACK_COUNT)); */
1da177e4
LT		 762 outw(size, ICEMT1724(ice, PLAYBACK_COUNT));
763 outb(size >> 16, ICEMT1724(ice, PLAYBACK_COUNT) + 2);
764
765 spin_unlock_irq(&ice->reg_lock);
766
e2ea7cfc 767 /*
6dfb5aff 768 dev_dbg(ice->card->dev, "pro prepare: ch = %d, addr = 0x%x, "
e2ea7cfc
TI		 769 "buffer = 0x%x, period = 0x%x\n",
770 substream->runtime->channels,
771 (unsigned int)substream->runtime->dma_addr,
772 snd_pcm_lib_buffer_bytes(substream),
773 snd_pcm_lib_period_bytes(substream));
774 */
1da177e4
LT		 775 return 0;
776}
777
ab0c7d72 778static snd_pcm_uframes_t snd_vt1724_playback_pro_pointer(struct snd_pcm_substream *substream)
1da177e4 779{
ab0c7d72 780 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 781 size_t ptr;
782
783 if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & VT1724_PDMA0_START))
784 return 0;
785#if 0 /* read PLAYBACK_ADDR */
786 ptr = inl(ICEMT1724(ice, PLAYBACK_ADDR));
787 if (ptr < substream->runtime->dma_addr) {
6dfb5aff 788 dev_dbg(ice->card->dev, "invalid negative ptr\n");
1da177e4
LT		 789 return 0;
790 }
791 ptr -= substream->runtime->dma_addr;
792 ptr = bytes_to_frames(substream->runtime, ptr);
793 if (ptr >= substream->runtime->buffer_size) {
6dfb5aff 794 dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
ab0c7d72 795 (int)ptr, (int)substream->runtime->period_size);
1da177e4
LT		 796 return 0;
797 }
798#else /* read PLAYBACK_SIZE */
799 ptr = inl(ICEMT1724(ice, PLAYBACK_SIZE)) & 0xffffff;
800 ptr = (ptr + 1) << 2;
801 ptr = bytes_to_frames(substream->runtime, ptr);
1de9fdc2 802 if (!ptr)
1da177e4
LT		 803 ;
804 else if (ptr <= substream->runtime->buffer_size)
805 ptr = substream->runtime->buffer_size - ptr;
806 else {
6dfb5aff 807 dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
ab0c7d72 808 (int)ptr, (int)substream->runtime->buffer_size);
1da177e4
LT		 809 ptr = 0;
810 }
811#endif
812 return ptr;
813}
814
ab0c7d72 815static int snd_vt1724_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4 816{
ab0c7d72 817 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
32b47da0 818 const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
1da177e4
LT		 819
820 spin_lock_irq(&ice->reg_lock);
821 outl(substream->runtime->dma_addr, ice->profi_port + reg->addr);
ab0c7d72
TI		 822 outw((snd_pcm_lib_buffer_bytes(substream) >> 2) - 1,
823 ice->profi_port + reg->size);
824 outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1,
825 ice->profi_port + reg->count);
1da177e4
LT		 826 spin_unlock_irq(&ice->reg_lock);
827 return 0;
828}
829
ab0c7d72 830static snd_pcm_uframes_t snd_vt1724_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 831{
ab0c7d72 832 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
32b47da0 833 const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
1da177e4
LT		 834 size_t ptr;
835
836 if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & reg->start))
837 return 0;
838#if 0 /* use ADDR register */
839 ptr = inl(ice->profi_port + reg->addr);
840 ptr -= substream->runtime->dma_addr;
841 return bytes_to_frames(substream->runtime, ptr);
842#else /* use SIZE register */
843 ptr = inw(ice->profi_port + reg->size);
844 ptr = (ptr + 1) << 2;
845 ptr = bytes_to_frames(substream->runtime, ptr);
1de9fdc2 846 if (!ptr)
1da177e4
LT		 847 ;
848 else if (ptr <= substream->runtime->buffer_size)
849 ptr = substream->runtime->buffer_size - ptr;
850 else {
6dfb5aff 851 dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
ab0c7d72 852 (int)ptr, (int)substream->runtime->buffer_size);
1da177e4
LT		 853 ptr = 0;
854 }
855 return ptr;
856#endif
857}
858
a5b7b5c1 859static const struct vt1724_pcm_reg vt1724_pdma0_reg = {
1da177e4
LT		 860 .addr = VT1724_MT_PLAYBACK_ADDR,
861 .size = VT1724_MT_PLAYBACK_SIZE,
862 .count = VT1724_MT_PLAYBACK_COUNT,
863 .start = VT1724_PDMA0_START,
864};
865
a5b7b5c1
TI		 866static const struct vt1724_pcm_reg vt1724_pdma4_reg = {
867 .addr = VT1724_MT_PDMA4_ADDR,
868 .size = VT1724_MT_PDMA4_SIZE,
869 .count = VT1724_MT_PDMA4_COUNT,
870 .start = VT1724_PDMA4_START,
871};
872
873static const struct vt1724_pcm_reg vt1724_rdma0_reg = {
1da177e4
LT		 874 .addr = VT1724_MT_CAPTURE_ADDR,
875 .size = VT1724_MT_CAPTURE_SIZE,
876 .count = VT1724_MT_CAPTURE_COUNT,
877 .start = VT1724_RDMA0_START,
878};
879
a5b7b5c1
TI		 880static const struct vt1724_pcm_reg vt1724_rdma1_reg = {
881 .addr = VT1724_MT_RDMA1_ADDR,
882 .size = VT1724_MT_RDMA1_SIZE,
883 .count = VT1724_MT_RDMA1_COUNT,
884 .start = VT1724_RDMA1_START,
885};
886
887#define vt1724_playback_pro_reg vt1724_pdma0_reg
888#define vt1724_playback_spdif_reg vt1724_pdma4_reg
889#define vt1724_capture_pro_reg vt1724_rdma0_reg
890#define vt1724_capture_spdif_reg vt1724_rdma1_reg
891
1de9fdc2 892static const struct snd_pcm_hardware snd_vt1724_playback_pro = {
1da177e4
LT		 893 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
894 SNDRV_PCM_INFO_BLOCK_TRANSFER |
895 SNDRV_PCM_INFO_MMAP_VALID |
896 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
897 .formats = SNDRV_PCM_FMTBIT_S32_LE,
898 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
899 .rate_min = 8000,
900 .rate_max = 192000,
901 .channels_min = 2,
902 .channels_max = 8,
903 .buffer_bytes_max = (1UL << 21), /* 19bits dword */
904 .period_bytes_min = 8 * 4 * 2, /* FIXME: constraints needed */
905 .period_bytes_max = (1UL << 21),
906 .periods_min = 2,
907 .periods_max = 1024,
908};
909
1de9fdc2 910static const struct snd_pcm_hardware snd_vt1724_spdif = {
1da177e4
LT		 911 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
912 SNDRV_PCM_INFO_BLOCK_TRANSFER |
913 SNDRV_PCM_INFO_MMAP_VALID |
914 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
915 .formats = SNDRV_PCM_FMTBIT_S32_LE,
2dfbeca9
TI		 916 .rates = (SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_44100|
917 SNDRV_PCM_RATE_48000|SNDRV_PCM_RATE_88200|
918 SNDRV_PCM_RATE_96000|SNDRV_PCM_RATE_176400|
919 SNDRV_PCM_RATE_192000),
1da177e4 920 .rate_min = 32000,
2dfbeca9 921 .rate_max = 192000,
1da177e4
LT		 922 .channels_min = 2,
923 .channels_max = 2,
924 .buffer_bytes_max = (1UL << 18), /* 16bits dword */
925 .period_bytes_min = 2 * 4 * 2,
926 .period_bytes_max = (1UL << 18),
927 .periods_min = 2,
928 .periods_max = 1024,
929};
930
1de9fdc2 931static const struct snd_pcm_hardware snd_vt1724_2ch_stereo = {
1da177e4
LT		 932 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
933 SNDRV_PCM_INFO_BLOCK_TRANSFER |
934 SNDRV_PCM_INFO_MMAP_VALID |
935 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
936 .formats = SNDRV_PCM_FMTBIT_S32_LE,
937 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
938 .rate_min = 8000,
939 .rate_max = 192000,
940 .channels_min = 2,
941 .channels_max = 2,
942 .buffer_bytes_max = (1UL << 18), /* 16bits dword */
943 .period_bytes_min = 2 * 4 * 2,
944 .period_bytes_max = (1UL << 18),
945 .periods_min = 2,
946 .periods_max = 1024,
947};
948
949/*
950 * set rate constraints
951 */
d16be8ed 952static void set_std_hw_rates(struct snd_ice1712 *ice)
1da177e4 953{
1da177e4
LT		 954 if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
955 /* I2S */
956 /* VT1720 doesn't support more than 96kHz */
957 if ((ice->eeprom.data[ICE_EEP2_I2S] & 0x08) && !ice->vt1720)
d16be8ed
PH		 958 ice->hw_rates = &hw_constraints_rates_192;
959 else
960 ice->hw_rates = &hw_constraints_rates_96;
961 } else {
1da177e4 962 /* ACLINK */
d16be8ed 963 ice->hw_rates = &hw_constraints_rates_48;
1da177e4 964 }
d16be8ed
PH		 965}
966
967static int set_rate_constraints(struct snd_ice1712 *ice,
968 struct snd_pcm_substream *substream)
969{
970 struct snd_pcm_runtime *runtime = substream->runtime;
971
972 runtime->hw.rate_min = ice->hw_rates->list[0];
973 runtime->hw.rate_max = ice->hw_rates->list[ice->hw_rates->count - 1];
974 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
975 return snd_pcm_hw_constraint_list(runtime, 0,
976 SNDRV_PCM_HW_PARAM_RATE,
977 ice->hw_rates);
1da177e4
LT		 978}
979
db05828a
PH		 980/* if the card has the internal rate locked (is_pro_locked), limit runtime
981 hw rates to the current internal rate only.
982*/
983static void constrain_rate_if_locked(struct snd_pcm_substream *substream)
984{
985 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
986 struct snd_pcm_runtime *runtime = substream->runtime;
987 unsigned int rate;
988 if (is_pro_rate_locked(ice)) {
989 rate = ice->get_rate(ice);
990 if (rate >= runtime->hw.rate_min
991 && rate <= runtime->hw.rate_max) {
992 runtime->hw.rate_min = rate;
993 runtime->hw.rate_max = rate;
994 }
995 }
996}
997
998
1da177e4
LT		 999/* multi-channel playback needs alignment 8x32bit regardless of the channels
1000 * actually used
1001 */
1002#define VT1724_BUFFER_ALIGN 0x20
1003
ab0c7d72 1004static int snd_vt1724_playback_pro_open(struct snd_pcm_substream *substream)
1da177e4 1005{
ab0c7d72
TI		 1006 struct snd_pcm_runtime *runtime = substream->runtime;
1007 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
a6b936b9 1008 int chs, num_indeps;
1da177e4 1009
32b47da0 1010 runtime->private_data = (void *)&vt1724_playback_pro_reg;
1da177e4
LT		 1011 ice->playback_pro_substream = substream;
1012 runtime->hw = snd_vt1724_playback_pro;
1013 snd_pcm_set_sync(substream);
1014 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1015 set_rate_constraints(ice, substream);
62932df8 1016 mutex_lock(&ice->open_mutex);
1da177e4 1017 /* calculate the currently available channels */
a6b936b9
TI		 1018 num_indeps = ice->num_total_dacs / 2 - 1;
1019 for (chs = 0; chs < num_indeps; chs++) {
1da177e4
LT		 1020 if (ice->pcm_reserved[chs])
1021 break;
1022 }
1023 chs = (chs + 1) * 2;
1024 runtime->hw.channels_max = chs;
1025 if (chs > 2) /* channels must be even */
1026 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2);
62932df8 1027 mutex_unlock(&ice->open_mutex);
1da177e4
LT		 1028 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1029 VT1724_BUFFER_ALIGN);
1030 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1031 VT1724_BUFFER_ALIGN);
db05828a 1032 constrain_rate_if_locked(substream);
1ff97cb9
PH		 1033 if (ice->pro_open)
1034 ice->pro_open(ice, substream);
1da177e4
LT		 1035 return 0;
1036}
1037
ab0c7d72 1038static int snd_vt1724_capture_pro_open(struct snd_pcm_substream *substream)
1da177e4 1039{
ab0c7d72
TI		 1040 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1041 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1042
32b47da0 1043 runtime->private_data = (void *)&vt1724_capture_pro_reg;
1da177e4
LT		 1044 ice->capture_pro_substream = substream;
1045 runtime->hw = snd_vt1724_2ch_stereo;
1046 snd_pcm_set_sync(substream);
1047 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1048 set_rate_constraints(ice, substream);
1049 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1050 VT1724_BUFFER_ALIGN);
1051 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1052 VT1724_BUFFER_ALIGN);
db05828a 1053 constrain_rate_if_locked(substream);
1ff97cb9
PH		 1054 if (ice->pro_open)
1055 ice->pro_open(ice, substream);
1da177e4
LT		 1056 return 0;
1057}
1058
ab0c7d72 1059static int snd_vt1724_playback_pro_close(struct snd_pcm_substream *substream)
1da177e4 1060{
ab0c7d72 1061 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1062
1063 if (PRO_RATE_RESET)
d16be8ed 1064 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1da177e4
LT		 1065 ice->playback_pro_substream = NULL;
1066
1067 return 0;
1068}
1069
ab0c7d72 1070static int snd_vt1724_capture_pro_close(struct snd_pcm_substream *substream)
1da177e4 1071{
ab0c7d72 1072 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1073
1074 if (PRO_RATE_RESET)
d16be8ed 1075 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1da177e4
LT		 1076 ice->capture_pro_substream = NULL;
1077 return 0;
1078}
1079
6769e988 1080static const struct snd_pcm_ops snd_vt1724_playback_pro_ops = {
1da177e4
LT		 1081 .open = snd_vt1724_playback_pro_open,
1082 .close = snd_vt1724_playback_pro_close,
1da177e4
LT		 1083 .hw_params = snd_vt1724_pcm_hw_params,
1084 .hw_free = snd_vt1724_pcm_hw_free,
1085 .prepare = snd_vt1724_playback_pro_prepare,
1086 .trigger = snd_vt1724_pcm_trigger,
1087 .pointer = snd_vt1724_playback_pro_pointer,
1088};
1089
6769e988 1090static const struct snd_pcm_ops snd_vt1724_capture_pro_ops = {
1da177e4
LT		 1091 .open = snd_vt1724_capture_pro_open,
1092 .close = snd_vt1724_capture_pro_close,
1da177e4
LT		 1093 .hw_params = snd_vt1724_pcm_hw_params,
1094 .hw_free = snd_vt1724_pcm_hw_free,
1095 .prepare = snd_vt1724_pcm_prepare,
1096 .trigger = snd_vt1724_pcm_trigger,
1097 .pointer = snd_vt1724_pcm_pointer,
1098};
1099
e23e7a14 1100static int snd_vt1724_pcm_profi(struct snd_ice1712 *ice, int device)
1da177e4 1101{
ab0c7d72 1102 struct snd_pcm *pcm;
ffd364dd 1103 int capt, err;
1da177e4 1104
ffd364dd
PH		 1105 if ((ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_ADC_MASK) ==
1106 VT1724_CFG_ADC_NONE)
1107 capt = 0;
1108 else
1109 capt = 1;
1110 err = snd_pcm_new(ice->card, "ICE1724", device, 1, capt, &pcm);
1da177e4
LT		 1111 if (err < 0)
1112 return err;
1113
1114 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_vt1724_playback_pro_ops);
ffd364dd
PH		 1115 if (capt)
1116 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1117 &snd_vt1724_capture_pro_ops);
1da177e4
LT		 1118
1119 pcm->private_data = ice;
1120 pcm->info_flags = 0;
1121 strcpy(pcm->name, "ICE1724");
1122
09e263cd
TI		 1123 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1124 &ice->pci->dev, 256*1024, 256*1024);
1da177e4
LT		 1125
1126 ice->pcm_pro = pcm;
1127
1128 return 0;
1129}
1130
1131
1132/*
1133 * SPDIF PCM
1134 */
1135
1da177e4 1136/* update spdif control bits; call with reg_lock */
ab0c7d72 1137static void update_spdif_bits(struct snd_ice1712 *ice, unsigned int val)
1da177e4
LT		 1138{
1139 unsigned char cbit, disabled;
1140
1141 cbit = inb(ICEREG1724(ice, SPDIF_CFG));
1142 disabled = cbit & ~VT1724_CFG_SPDIF_OUT_EN;
1143 if (cbit != disabled)
1144 outb(disabled, ICEREG1724(ice, SPDIF_CFG));
1145 outw(val, ICEMT1724(ice, SPDIF_CTRL));
1146 if (cbit != disabled)
1147 outb(cbit, ICEREG1724(ice, SPDIF_CFG));
1148 outw(val, ICEMT1724(ice, SPDIF_CTRL));
1149}
1150
1151/* update SPDIF control bits according to the given rate */
ab0c7d72 1152static void update_spdif_rate(struct snd_ice1712 *ice, unsigned int rate)
1da177e4
LT		 1153{
1154 unsigned int val, nval;
1155 unsigned long flags;
1156
1157 spin_lock_irqsave(&ice->reg_lock, flags);
1158 nval = val = inw(ICEMT1724(ice, SPDIF_CTRL));
1159 nval &= ~(7 << 12);
1160 switch (rate) {
1161 case 44100: break;
1162 case 48000: nval |= 2 << 12; break;
1163 case 32000: nval |= 3 << 12; break;
2dfbeca9
TI		 1164 case 88200: nval |= 4 << 12; break;
1165 case 96000: nval |= 5 << 12; break;
1166 case 192000: nval |= 6 << 12; break;
1167 case 176400: nval |= 7 << 12; break;
1da177e4
LT		 1168 }
1169 if (val != nval)
1170 update_spdif_bits(ice, nval);
1171 spin_unlock_irqrestore(&ice->reg_lock, flags);
1172}
1173
ab0c7d72 1174static int snd_vt1724_playback_spdif_prepare(struct snd_pcm_substream *substream)
1da177e4 1175{
ab0c7d72 1176 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1de9fdc2 1177 if (!ice->force_pdma4)
1da177e4
LT		 1178 update_spdif_rate(ice, substream->runtime->rate);
1179 return snd_vt1724_pcm_prepare(substream);
1180}
1181
ab0c7d72 1182static int snd_vt1724_playback_spdif_open(struct snd_pcm_substream *substream)
1da177e4 1183{
ab0c7d72
TI		 1184 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1185 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1186
32b47da0 1187 runtime->private_data = (void *)&vt1724_playback_spdif_reg;
1da177e4
LT		 1188 ice->playback_con_substream = substream;
1189 if (ice->force_pdma4) {
1190 runtime->hw = snd_vt1724_2ch_stereo;
1191 set_rate_constraints(ice, substream);
1192 } else
1193 runtime->hw = snd_vt1724_spdif;
1194 snd_pcm_set_sync(substream);
1195 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1196 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1197 VT1724_BUFFER_ALIGN);
1198 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1199 VT1724_BUFFER_ALIGN);
db05828a 1200 constrain_rate_if_locked(substream);
c93f5a1e
TI		 1201 if (ice->spdif.ops.open)
1202 ice->spdif.ops.open(ice, substream);
1da177e4
LT		 1203 return 0;
1204}
1205
ab0c7d72 1206static int snd_vt1724_playback_spdif_close(struct snd_pcm_substream *substream)
1da177e4 1207{
ab0c7d72 1208 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1209
1210 if (PRO_RATE_RESET)
d16be8ed 1211 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1da177e4 1212 ice->playback_con_substream = NULL;
c93f5a1e
TI		 1213 if (ice->spdif.ops.close)
1214 ice->spdif.ops.close(ice, substream);
1da177e4
LT		 1215
1216 return 0;
1217}
1218
ab0c7d72 1219static int snd_vt1724_capture_spdif_open(struct snd_pcm_substream *substream)
1da177e4 1220{
ab0c7d72
TI		 1221 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1222 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1223
32b47da0 1224 runtime->private_data = (void *)&vt1724_capture_spdif_reg;
1da177e4
LT		 1225 ice->capture_con_substream = substream;
1226 if (ice->force_rdma1) {
1227 runtime->hw = snd_vt1724_2ch_stereo;
1228 set_rate_constraints(ice, substream);
1229 } else
1230 runtime->hw = snd_vt1724_spdif;
1231 snd_pcm_set_sync(substream);
1232 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1233 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1234 VT1724_BUFFER_ALIGN);
1235 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1236 VT1724_BUFFER_ALIGN);
db05828a 1237 constrain_rate_if_locked(substream);
c93f5a1e
TI		 1238 if (ice->spdif.ops.open)
1239 ice->spdif.ops.open(ice, substream);
1da177e4
LT		 1240 return 0;
1241}
1242
ab0c7d72 1243static int snd_vt1724_capture_spdif_close(struct snd_pcm_substream *substream)
1da177e4 1244{
ab0c7d72 1245 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1246
1247 if (PRO_RATE_RESET)
d16be8ed 1248 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1da177e4 1249 ice->capture_con_substream = NULL;
c93f5a1e
TI		 1250 if (ice->spdif.ops.close)
1251 ice->spdif.ops.close(ice, substream);
1da177e4
LT		 1252
1253 return 0;
1254}
1255
6769e988 1256static const struct snd_pcm_ops snd_vt1724_playback_spdif_ops = {
1da177e4
LT		 1257 .open = snd_vt1724_playback_spdif_open,
1258 .close = snd_vt1724_playback_spdif_close,
1da177e4
LT		 1259 .hw_params = snd_vt1724_pcm_hw_params,
1260 .hw_free = snd_vt1724_pcm_hw_free,
1261 .prepare = snd_vt1724_playback_spdif_prepare,
1262 .trigger = snd_vt1724_pcm_trigger,
1263 .pointer = snd_vt1724_pcm_pointer,
1264};
1265
6769e988 1266static const struct snd_pcm_ops snd_vt1724_capture_spdif_ops = {
1da177e4
LT		 1267 .open = snd_vt1724_capture_spdif_open,
1268 .close = snd_vt1724_capture_spdif_close,
1da177e4
LT		 1269 .hw_params = snd_vt1724_pcm_hw_params,
1270 .hw_free = snd_vt1724_pcm_hw_free,
1271 .prepare = snd_vt1724_pcm_prepare,
1272 .trigger = snd_vt1724_pcm_trigger,
1273 .pointer = snd_vt1724_pcm_pointer,
1274};
1275
1276
e23e7a14 1277static int snd_vt1724_pcm_spdif(struct snd_ice1712 *ice, int device)
1da177e4
LT		 1278{
1279 char *name;
ab0c7d72 1280 struct snd_pcm *pcm;
1da177e4
LT		 1281 int play, capt;
1282 int err;
1283
1284 if (ice->force_pdma4 ||
1285 (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_OUT_INT)) {
1286 play = 1;
1287 ice->has_spdif = 1;
1288 } else
1289 play = 0;
1290 if (ice->force_rdma1 ||
1291 (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN)) {
1292 capt = 1;
1293 ice->has_spdif = 1;
1294 } else
1295 capt = 0;
1de9fdc2 1296 if (!play && !capt)
1da177e4
LT		 1297 return 0; /* no spdif device */
1298
1299 if (ice->force_pdma4 || ice->force_rdma1)
1300 name = "ICE1724 Secondary";
1301 else
8eca7538 1302 name = "ICE1724 IEC958";
1da177e4
LT		 1303 err = snd_pcm_new(ice->card, name, device, play, capt, &pcm);
1304 if (err < 0)
1305 return err;
1306
1307 if (play)
1308 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1309 &snd_vt1724_playback_spdif_ops);
1310 if (capt)
1311 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1312 &snd_vt1724_capture_spdif_ops);
1313
1314 pcm->private_data = ice;
1315 pcm->info_flags = 0;
1316 strcpy(pcm->name, name);
1317
09e263cd
TI		 1318 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1319 &ice->pci->dev, 256*1024, 256*1024);
1da177e4
LT		 1320
1321 ice->pcm = pcm;
1322
1323 return 0;
1324}
1325
1326
1327/*
1328 * independent surround PCMs
1329 */
1330
32b47da0 1331static const struct vt1724_pcm_reg vt1724_playback_dma_regs[3] = {
1da177e4
LT		 1332 {
1333 .addr = VT1724_MT_PDMA1_ADDR,
1334 .size = VT1724_MT_PDMA1_SIZE,
1335 .count = VT1724_MT_PDMA1_COUNT,
1336 .start = VT1724_PDMA1_START,
1337 },
1338 {
1339 .addr = VT1724_MT_PDMA2_ADDR,
1340 .size = VT1724_MT_PDMA2_SIZE,
1341 .count = VT1724_MT_PDMA2_COUNT,
1342 .start = VT1724_PDMA2_START,
1343 },
1344 {
1345 .addr = VT1724_MT_PDMA3_ADDR,
1346 .size = VT1724_MT_PDMA3_SIZE,
1347 .count = VT1724_MT_PDMA3_COUNT,
1348 .start = VT1724_PDMA3_START,
1349 },
1350};
1351
ab0c7d72 1352static int snd_vt1724_playback_indep_prepare(struct snd_pcm_substream *substream)
1da177e4 1353{
ab0c7d72 1354 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1355 unsigned char val;
1356
1357 spin_lock_irq(&ice->reg_lock);
1358 val = 3 - substream->number;
1359 if (inb(ICEMT1724(ice, BURST)) < val)
1360 outb(val, ICEMT1724(ice, BURST));
1361 spin_unlock_irq(&ice->reg_lock);
1362 return snd_vt1724_pcm_prepare(substream);
1363}
1364
ab0c7d72 1365static int snd_vt1724_playback_indep_open(struct snd_pcm_substream *substream)
1da177e4 1366{
ab0c7d72
TI		 1367 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1368 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1369
62932df8 1370 mutex_lock(&ice->open_mutex);
1da177e4
LT		 1371 /* already used by PDMA0? */
1372 if (ice->pcm_reserved[substream->number]) {
62932df8 1373 mutex_unlock(&ice->open_mutex);
1da177e4
LT		 1374 return -EBUSY; /* FIXME: should handle blocking mode properly */
1375 }
62932df8 1376 mutex_unlock(&ice->open_mutex);
32b47da0 1377 runtime->private_data = (void *)&vt1724_playback_dma_regs[substream->number];
1da177e4
LT		 1378 ice->playback_con_substream_ds[substream->number] = substream;
1379 runtime->hw = snd_vt1724_2ch_stereo;
1380 snd_pcm_set_sync(substream);
1381 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1382 set_rate_constraints(ice, substream);
1383 return 0;
1384}
1385
ab0c7d72 1386static int snd_vt1724_playback_indep_close(struct snd_pcm_substream *substream)
1da177e4 1387{
ab0c7d72 1388 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1389
1390 if (PRO_RATE_RESET)
d16be8ed 1391 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
1da177e4
LT		 1392 ice->playback_con_substream_ds[substream->number] = NULL;
1393 ice->pcm_reserved[substream->number] = NULL;
1394
1395 return 0;
1396}
1397
6769e988 1398static const struct snd_pcm_ops snd_vt1724_playback_indep_ops = {
1da177e4
LT		 1399 .open = snd_vt1724_playback_indep_open,
1400 .close = snd_vt1724_playback_indep_close,
1da177e4
LT		 1401 .hw_params = snd_vt1724_pcm_hw_params,
1402 .hw_free = snd_vt1724_pcm_hw_free,
1403 .prepare = snd_vt1724_playback_indep_prepare,
1404 .trigger = snd_vt1724_pcm_trigger,
1405 .pointer = snd_vt1724_pcm_pointer,
1406};
1407
1408
e23e7a14 1409static int snd_vt1724_pcm_indep(struct snd_ice1712 *ice, int device)
1da177e4 1410{
ab0c7d72 1411 struct snd_pcm *pcm;
1da177e4
LT		 1412 int play;
1413 int err;
1414
1415 play = ice->num_total_dacs / 2 - 1;
1416 if (play <= 0)
1417 return 0;
1418
1419 err = snd_pcm_new(ice->card, "ICE1724 Surrounds", device, play, 0, &pcm);
1420 if (err < 0)
1421 return err;
1422
1423 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1424 &snd_vt1724_playback_indep_ops);
1425
1426 pcm->private_data = ice;
1427 pcm->info_flags = 0;
1428 strcpy(pcm->name, "ICE1724 Surround PCM");
1429
09e263cd
TI		 1430 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1431 &ice->pci->dev, 256*1024, 256*1024);
1da177e4
LT		 1432
1433 ice->pcm_ds = pcm;
1434
1435 return 0;
1436}
1437
1438
1439/*
1440 * Mixer section
1441 */
1442
e23e7a14 1443static int snd_vt1724_ac97_mixer(struct snd_ice1712 *ice)
1da177e4
LT		 1444{
1445 int err;
1446
1de9fdc2 1447 if (!(ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S)) {
ab0c7d72
TI		 1448 struct snd_ac97_bus *pbus;
1449 struct snd_ac97_template ac97;
51055da5 1450 static const struct snd_ac97_bus_ops ops = {
1da177e4
LT		 1451 .write = snd_vt1724_ac97_write,
1452 .read = snd_vt1724_ac97_read,
1453 };
1454
1455 /* cold reset */
1456 outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
1457 mdelay(5); /* FIXME */
1458 outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
1459
1de9fdc2
AB		 1460 err = snd_ac97_bus(ice->card, 0, &ops, NULL, &pbus);
1461 if (err < 0)
1da177e4
LT		 1462 return err;
1463 memset(&ac97, 0, sizeof(ac97));
1464 ac97.private_data = ice;
1de9fdc2
AB		 1465 err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
1466 if (err < 0)
6dfb5aff
TI		 1467 dev_warn(ice->card->dev,
1468 "cannot initialize pro ac97, skipped\n");
1da177e4
LT		 1469 else
1470 return 0;
1471 }
1472 /* I2S mixer only */
1473 strcat(ice->card->mixername, "ICE1724 - multitrack");
1474 return 0;
1475}
1476
1477/*
1478 *
1479 */
1480
ab0c7d72 1481static inline unsigned int eeprom_triple(struct snd_ice1712 *ice, int idx)
1da177e4
LT		 1482{
1483 return (unsigned int)ice->eeprom.data[idx] | \
1484 ((unsigned int)ice->eeprom.data[idx + 1] << 8) | \
1485 ((unsigned int)ice->eeprom.data[idx + 2] << 16);
1486}
1487
1de9fdc2 1488static void snd_vt1724_proc_read(struct snd_info_entry *entry,
ab0c7d72 1489 struct snd_info_buffer *buffer)
1da177e4 1490{
ab0c7d72 1491 struct snd_ice1712 *ice = entry->private_data;
1da177e4
LT		 1492 unsigned int idx;
1493
1494 snd_iprintf(buffer, "%s\n\n", ice->card->longname);
1495 snd_iprintf(buffer, "EEPROM:\n");
1496
1497 snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
1498 snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
1499 snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
ab0c7d72
TI		 1500 snd_iprintf(buffer, " System Config : 0x%x\n",
1501 ice->eeprom.data[ICE_EEP2_SYSCONF]);
1502 snd_iprintf(buffer, " ACLink : 0x%x\n",
1503 ice->eeprom.data[ICE_EEP2_ACLINK]);
1504 snd_iprintf(buffer, " I2S : 0x%x\n",
1505 ice->eeprom.data[ICE_EEP2_I2S]);
1506 snd_iprintf(buffer, " S/PDIF : 0x%x\n",
1507 ice->eeprom.data[ICE_EEP2_SPDIF]);
1508 snd_iprintf(buffer, " GPIO direction : 0x%x\n",
1509 ice->eeprom.gpiodir);
1510 snd_iprintf(buffer, " GPIO mask : 0x%x\n",
1511 ice->eeprom.gpiomask);
1512 snd_iprintf(buffer, " GPIO state : 0x%x\n",
1513 ice->eeprom.gpiostate);
1da177e4 1514 for (idx = 0x12; idx < ice->eeprom.size; idx++)
ab0c7d72
TI		 1515 snd_iprintf(buffer, " Extra #%02i : 0x%x\n",
1516 idx, ice->eeprom.data[idx]);
1da177e4
LT		 1517
1518 snd_iprintf(buffer, "\nRegisters:\n");
1519
ab0c7d72
TI		 1520 snd_iprintf(buffer, " PSDOUT03 : 0x%08x\n",
1521 (unsigned)inl(ICEMT1724(ice, ROUTE_PLAYBACK)));
1da177e4 1522 for (idx = 0x0; idx < 0x20 ; idx++)
ab0c7d72
TI		 1523 snd_iprintf(buffer, " CCS%02x : 0x%02x\n",
1524 idx, inb(ice->port+idx));
1da177e4 1525 for (idx = 0x0; idx < 0x30 ; idx++)
ab0c7d72
TI		 1526 snd_iprintf(buffer, " MT%02x : 0x%02x\n",
1527 idx, inb(ice->profi_port+idx));
1da177e4
LT		 1528}
1529
e23e7a14 1530static void snd_vt1724_proc_init(struct snd_ice1712 *ice)
1da177e4 1531{
47f2769b 1532 snd_card_ro_proc_new(ice->card, "ice1724", ice, snd_vt1724_proc_read);
1da177e4
LT		 1533}
1534
1535/*
1536 *
1537 */
1538
ab0c7d72
TI		 1539static int snd_vt1724_eeprom_info(struct snd_kcontrol *kcontrol,
1540 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1541{
1542 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
ab0c7d72 1543 uinfo->count = sizeof(struct snd_ice1712_eeprom);
1da177e4
LT		 1544 return 0;
1545}
1546
ab0c7d72
TI		 1547static int snd_vt1724_eeprom_get(struct snd_kcontrol *kcontrol,
1548 struct snd_ctl_elem_value *ucontrol)
1da177e4 1549{
ab0c7d72 1550 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1de9fdc2 1551
1da177e4
LT		 1552 memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
1553 return 0;
1554}
1555
f3b827e0 1556static const struct snd_kcontrol_new snd_vt1724_eeprom = {
1da177e4
LT		 1557 .iface = SNDRV_CTL_ELEM_IFACE_CARD,
1558 .name = "ICE1724 EEPROM",
1559 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1560 .info = snd_vt1724_eeprom_info,
1561 .get = snd_vt1724_eeprom_get
1562};
1563
1564/*
1565 */
ab0c7d72
TI		 1566static int snd_vt1724_spdif_info(struct snd_kcontrol *kcontrol,
1567 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1568{
1569 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1570 uinfo->count = 1;
1571 return 0;
1572}
1573
ab0c7d72 1574static unsigned int encode_spdif_bits(struct snd_aes_iec958 *diga)
1da177e4 1575{
2dfbeca9 1576 unsigned int val, rbits;
1da177e4
LT		 1577
1578 val = diga->status[0] & 0x03; /* professional, non-audio */
1579 if (val & 0x01) {
1580 /* professional */
ab0c7d72
TI		 1581 if ((diga->status[0] & IEC958_AES0_PRO_EMPHASIS) ==
1582 IEC958_AES0_PRO_EMPHASIS_5015)
1da177e4 1583 val |= 1U << 3;
2dfbeca9
TI		 1584 rbits = (diga->status[4] >> 3) & 0x0f;
1585 if (rbits) {
1586 switch (rbits) {
1587 case 2: val |= 5 << 12; break; /* 96k */
1588 case 3: val |= 6 << 12; break; /* 192k */
1589 case 10: val |= 4 << 12; break; /* 88.2k */
1590 case 11: val |= 7 << 12; break; /* 176.4k */
1591 }
1592 } else {
1593 switch (diga->status[0] & IEC958_AES0_PRO_FS) {
1594 case IEC958_AES0_PRO_FS_44100:
1595 break;
1596 case IEC958_AES0_PRO_FS_32000:
1597 val |= 3U << 12;
1598 break;
1599 default:
1600 val |= 2U << 12;
1601 break;
1602 }
1da177e4
LT		 1603 }
1604 } else {
1605 /* consumer */
1606 val |= diga->status[1] & 0x04; /* copyright */
ab0c7d72
TI		 1607 if ((diga->status[0] & IEC958_AES0_CON_EMPHASIS) ==
1608 IEC958_AES0_CON_EMPHASIS_5015)
1da177e4
LT		 1609 val |= 1U << 3;
1610 val |= (unsigned int)(diga->status[1] & 0x3f) << 4; /* category */
1611 val |= (unsigned int)(diga->status[3] & IEC958_AES3_CON_FS) << 12; /* fs */
1612 }
1613 return val;
1614}
1615
ab0c7d72 1616static void decode_spdif_bits(struct snd_aes_iec958 *diga, unsigned int val)
1da177e4
LT		 1617{
1618 memset(diga->status, 0, sizeof(diga->status));
1619 diga->status[0] = val & 0x03; /* professional, non-audio */
1620 if (val & 0x01) {
1621 /* professional */
1622 if (val & (1U << 3))
1623 diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015;
1624 switch ((val >> 12) & 0x7) {
1625 case 0:
1626 break;
1627 case 2:
1628 diga->status[0] |= IEC958_AES0_PRO_FS_32000;
1629 break;
1630 default:
1631 diga->status[0] |= IEC958_AES0_PRO_FS_48000;
1632 break;
1633 }
1634 } else {
1635 /* consumer */
1636 diga->status[0] |= val & (1U << 2); /* copyright */
1637 if (val & (1U << 3))
1638 diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015;
1639 diga->status[1] |= (val >> 4) & 0x3f; /* category */
1640 diga->status[3] |= (val >> 12) & 0x07; /* fs */
1641 }
1642}
1643
ab0c7d72
TI		 1644static int snd_vt1724_spdif_default_get(struct snd_kcontrol *kcontrol,
1645 struct snd_ctl_elem_value *ucontrol)
1da177e4 1646{
ab0c7d72 1647 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1648 unsigned int val;
1649 val = inw(ICEMT1724(ice, SPDIF_CTRL));
1650 decode_spdif_bits(&ucontrol->value.iec958, val);
1651 return 0;
1652}
1653
ab0c7d72
TI		 1654static int snd_vt1724_spdif_default_put(struct snd_kcontrol *kcontrol,
1655 struct snd_ctl_elem_value *ucontrol)
1da177e4 1656{
ab0c7d72 1657 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1658 unsigned int val, old;
1659
1660 val = encode_spdif_bits(&ucontrol->value.iec958);
1661 spin_lock_irq(&ice->reg_lock);
1662 old = inw(ICEMT1724(ice, SPDIF_CTRL));
1663 if (val != old)
1664 update_spdif_bits(ice, val);
1665 spin_unlock_irq(&ice->reg_lock);
1de9fdc2 1666 return val != old;
1da177e4
LT		 1667}
1668
f3b827e0 1669static const struct snd_kcontrol_new snd_vt1724_spdif_default =
1da177e4
LT		 1670{
1671 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1de9fdc2 1672 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1da177e4
LT		 1673 .info = snd_vt1724_spdif_info,
1674 .get = snd_vt1724_spdif_default_get,
1675 .put = snd_vt1724_spdif_default_put
1676};
1677
ab0c7d72
TI		 1678static int snd_vt1724_spdif_maskc_get(struct snd_kcontrol *kcontrol,
1679 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1680{
1681 ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
1682 IEC958_AES0_PROFESSIONAL |
1683 IEC958_AES0_CON_NOT_COPYRIGHT |
1684 IEC958_AES0_CON_EMPHASIS;
1685 ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
1686 IEC958_AES1_CON_CATEGORY;
1687 ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
1688 return 0;
1689}
1690
ab0c7d72
TI		 1691static int snd_vt1724_spdif_maskp_get(struct snd_kcontrol *kcontrol,
1692 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1693{
1694 ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
1695 IEC958_AES0_PROFESSIONAL |
1696 IEC958_AES0_PRO_FS |
1697 IEC958_AES0_PRO_EMPHASIS;
1698 return 0;
1699}
1700
f3b827e0 1701static const struct snd_kcontrol_new snd_vt1724_spdif_maskc =
1da177e4
LT		 1702{
1703 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 1704 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1de9fdc2 1705 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1da177e4
LT		 1706 .info = snd_vt1724_spdif_info,
1707 .get = snd_vt1724_spdif_maskc_get,
1708};
1709
f3b827e0 1710static const struct snd_kcontrol_new snd_vt1724_spdif_maskp =
1da177e4
LT		 1711{
1712 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 1713 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1de9fdc2 1714 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1da177e4
LT		 1715 .info = snd_vt1724_spdif_info,
1716 .get = snd_vt1724_spdif_maskp_get,
1717};
1718
a5ce8890 1719#define snd_vt1724_spdif_sw_info snd_ctl_boolean_mono_info
1da177e4 1720
ab0c7d72
TI		 1721static int snd_vt1724_spdif_sw_get(struct snd_kcontrol *kcontrol,
1722 struct snd_ctl_elem_value *ucontrol)
1da177e4 1723{
ab0c7d72
TI		 1724 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1725 ucontrol->value.integer.value[0] = inb(ICEREG1724(ice, SPDIF_CFG)) &
1726 VT1724_CFG_SPDIF_OUT_EN ? 1 : 0;
1da177e4
LT		 1727 return 0;
1728}
1729
ab0c7d72
TI		 1730static int snd_vt1724_spdif_sw_put(struct snd_kcontrol *kcontrol,
1731 struct snd_ctl_elem_value *ucontrol)
1da177e4 1732{
ab0c7d72 1733 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1734 unsigned char old, val;
1735
1736 spin_lock_irq(&ice->reg_lock);
1737 old = val = inb(ICEREG1724(ice, SPDIF_CFG));
1738 val &= ~VT1724_CFG_SPDIF_OUT_EN;
1739 if (ucontrol->value.integer.value[0])
1740 val |= VT1724_CFG_SPDIF_OUT_EN;
1741 if (old != val)
1742 outb(val, ICEREG1724(ice, SPDIF_CFG));
1743 spin_unlock_irq(&ice->reg_lock);
1744 return old != val;
1745}
1746
f3b827e0 1747static const struct snd_kcontrol_new snd_vt1724_spdif_switch =
1da177e4
LT		 1748{
1749 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1750 /* FIXME: the following conflict with IEC958 Playback Route */
1de9fdc2
AB		 1751 /* .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, SWITCH), */
1752 .name = SNDRV_CTL_NAME_IEC958("Output ", NONE, SWITCH),
1da177e4
LT		 1753 .info = snd_vt1724_spdif_sw_info,
1754 .get = snd_vt1724_spdif_sw_get,
1755 .put = snd_vt1724_spdif_sw_put
1756};
1757
1758
1759#if 0 /* NOT USED YET */
1760/*
1761 * GPIO access from extern
1762 */
1763
a5ce8890 1764#define snd_vt1724_gpio_info snd_ctl_boolean_mono_info
1da177e4 1765
ab0c7d72
TI		 1766int snd_vt1724_gpio_get(struct snd_kcontrol *kcontrol,
1767 struct snd_ctl_elem_value *ucontrol)
1da177e4 1768{
ab0c7d72 1769 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1770 int shift = kcontrol->private_value & 0xff;
1771 int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
1de9fdc2 1772
1da177e4 1773 snd_ice1712_save_gpio_status(ice);
ab0c7d72
TI		 1774 ucontrol->value.integer.value[0] =
1775 (snd_ice1712_gpio_read(ice) & (1 << shift) ? 1 : 0) ^ invert;
1da177e4
LT		 1776 snd_ice1712_restore_gpio_status(ice);
1777 return 0;
1778}
1779
ab0c7d72
TI		 1780int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
1781 struct snd_ctl_elem_value *ucontrol)
1da177e4 1782{
ab0c7d72 1783 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1784 int shift = kcontrol->private_value & 0xff;
1785 int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
1786 unsigned int val, nval;
1787
1788 if (kcontrol->private_value & (1 << 31))
1789 return -EPERM;
1790 nval = (ucontrol->value.integer.value[0] ? (1 << shift) : 0) ^ invert;
1791 snd_ice1712_save_gpio_status(ice);
1792 val = snd_ice1712_gpio_read(ice);
1793 nval |= val & ~(1 << shift);
1794 if (val != nval)
1795 snd_ice1712_gpio_write(ice, nval);
1796 snd_ice1712_restore_gpio_status(ice);
1797 return val != nval;
1798}
1799#endif /* NOT USED YET */
1800
1801/*
1802 * rate
1803 */
ab0c7d72
TI		 1804static int snd_vt1724_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
1805 struct snd_ctl_elem_info *uinfo)
1da177e4 1806{
ab0c7d72 1807 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1ff97cb9 1808 int hw_rates_count = ice->hw_rates->count;
1da177e4
LT		 1809 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1810 uinfo->count = 1;
1ff97cb9 1811
219e2cd4
PH		 1812 /* internal clocks */
1813 uinfo->value.enumerated.items = hw_rates_count;
1814 /* external clocks */
1815 if (ice->force_rdma1 ||
1816 (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN))
1817 uinfo->value.enumerated.items += ice->ext_clock_count;
1ff97cb9 1818 /* upper limit - keep at top */
1da177e4
LT		 1819 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1820 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1ff97cb9
PH		 1821 if (uinfo->value.enumerated.item >= hw_rates_count)
1822 /* ext_clock items */
1823 strcpy(uinfo->value.enumerated.name,
1824 ice->ext_clock_names[
1825 uinfo->value.enumerated.item - hw_rates_count]);
d16be8ed 1826 else
1ff97cb9 1827 /* int clock items */
d16be8ed
PH		 1828 sprintf(uinfo->value.enumerated.name, "%d",
1829 ice->hw_rates->list[uinfo->value.enumerated.item]);
1da177e4
LT		 1830 return 0;
1831}
1832
ab0c7d72
TI		 1833static int snd_vt1724_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
1834 struct snd_ctl_elem_value *ucontrol)
1da177e4 1835{
ab0c7d72 1836 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
d16be8ed 1837 unsigned int i, rate;
1de9fdc2 1838
1da177e4 1839 spin_lock_irq(&ice->reg_lock);
d16be8ed 1840 if (ice->is_spdif_master(ice)) {
1ff97cb9
PH		 1841 ucontrol->value.enumerated.item[0] = ice->hw_rates->count +
1842 ice->get_spdif_master_type(ice);
1da177e4 1843 } else {
d16be8ed
PH		 1844 rate = ice->get_rate(ice);
1845 ucontrol->value.enumerated.item[0] = 0;
1846 for (i = 0; i < ice->hw_rates->count; i++) {
1847 if (ice->hw_rates->list[i] == rate) {
1848 ucontrol->value.enumerated.item[0] = i;
1849 break;
1850 }
1da177e4 1851 }
1da177e4
LT		 1852 }
1853 spin_unlock_irq(&ice->reg_lock);
1854 return 0;
1855}
1856
1ff97cb9
PH		 1857static int stdclock_get_spdif_master_type(struct snd_ice1712 *ice)
1858{
1859 /* standard external clock - only single type - SPDIF IN */
1860 return 0;
1861}
1862
d16be8ed 1863/* setting clock to external - SPDIF */
1ff97cb9 1864static int stdclock_set_spdif_clock(struct snd_ice1712 *ice, int type)
d16be8ed
PH		 1865{
1866 unsigned char oval;
1867 unsigned char i2s_oval;
1868 oval = inb(ICEMT1724(ice, RATE));
1869 outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
1870 /* setting 256fs */
1871 i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));
1872 outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X, ICEMT1724(ice, I2S_FORMAT));
1ff97cb9 1873 return 0;
d16be8ed
PH		 1874}
1875
1ff97cb9 1876
ab0c7d72
TI		 1877static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
1878 struct snd_ctl_elem_value *ucontrol)
1da177e4 1879{
ab0c7d72 1880 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
d16be8ed
PH		 1881 unsigned int old_rate, new_rate;
1882 unsigned int item = ucontrol->value.enumerated.item[0];
1ff97cb9 1883 unsigned int first_ext_clock = ice->hw_rates->count;
d16be8ed 1884
1ff97cb9 1885 if (item > first_ext_clock + ice->ext_clock_count - 1)
d16be8ed 1886 return -EINVAL;
1da177e4 1887
1ff97cb9 1888 /* if rate = 0 => external clock */
1da177e4 1889 spin_lock_irq(&ice->reg_lock);
d16be8ed
PH		 1890 if (ice->is_spdif_master(ice))
1891 old_rate = 0;
1892 else
1893 old_rate = ice->get_rate(ice);
1ff97cb9
PH		 1894 if (item >= first_ext_clock) {
1895 /* switching to external clock */
1896 ice->set_spdif_clock(ice, item - first_ext_clock);
d16be8ed 1897 new_rate = 0;
1da177e4 1898 } else {
d16be8ed
PH		 1899 /* internal on-card clock */
1900 new_rate = ice->hw_rates->list[item];
1901 ice->pro_rate_default = new_rate;
1902 spin_unlock_irq(&ice->reg_lock);
1903 snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 1);
1904 spin_lock_irq(&ice->reg_lock);
1da177e4 1905 }
1da177e4
LT		 1906 spin_unlock_irq(&ice->reg_lock);
1907
1ff97cb9 1908 /* the first switch to the ext. clock mode? */
d16be8ed 1909 if (old_rate != new_rate && !new_rate) {
1da177e4 1910 /* notify akm chips as well */
d16be8ed
PH		 1911 unsigned int i;
1912 if (ice->gpio.set_pro_rate)
1913 ice->gpio.set_pro_rate(ice, 0);
1914 for (i = 0; i < ice->akm_codecs; i++) {
1915 if (ice->akm[i].ops.set_rate_val)
1916 ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
1da177e4
LT		 1917 }
1918 }
d16be8ed 1919 return old_rate != new_rate;
1da177e4
LT		 1920}
1921
f3b827e0 1922static const struct snd_kcontrol_new snd_vt1724_pro_internal_clock = {
1da177e4
LT		 1923 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1924 .name = "Multi Track Internal Clock",
1925 .info = snd_vt1724_pro_internal_clock_info,
1926 .get = snd_vt1724_pro_internal_clock_get,
1927 .put = snd_vt1724_pro_internal_clock_put
1928};
1929
a5ce8890 1930#define snd_vt1724_pro_rate_locking_info snd_ctl_boolean_mono_info
1da177e4 1931
ab0c7d72
TI		 1932static int snd_vt1724_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
1933 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1934{
1935 ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
1936 return 0;
1937}
1938
ab0c7d72
TI		 1939static int snd_vt1724_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
1940 struct snd_ctl_elem_value *ucontrol)
1da177e4 1941{
ab0c7d72 1942 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1943 int change = 0, nval;
1944
1945 nval = ucontrol->value.integer.value[0] ? 1 : 0;
1946 spin_lock_irq(&ice->reg_lock);
1947 change = PRO_RATE_LOCKED != nval;
1948 PRO_RATE_LOCKED = nval;
1949 spin_unlock_irq(&ice->reg_lock);
1950 return change;
1951}
1952
f3b827e0 1953static const struct snd_kcontrol_new snd_vt1724_pro_rate_locking = {
1da177e4
LT		 1954 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1955 .name = "Multi Track Rate Locking",
1956 .info = snd_vt1724_pro_rate_locking_info,
1957 .get = snd_vt1724_pro_rate_locking_get,
1958 .put = snd_vt1724_pro_rate_locking_put
1959};
1960
a5ce8890 1961#define snd_vt1724_pro_rate_reset_info snd_ctl_boolean_mono_info
1da177e4 1962
ab0c7d72
TI		 1963static int snd_vt1724_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
1964 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1965{
1966 ucontrol->value.integer.value[0] = PRO_RATE_RESET ? 1 : 0;
1967 return 0;
1968}
1969
ab0c7d72
TI		 1970static int snd_vt1724_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
1971 struct snd_ctl_elem_value *ucontrol)
1da177e4 1972{
ab0c7d72 1973 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1974 int change = 0, nval;
1975
1976 nval = ucontrol->value.integer.value[0] ? 1 : 0;
1977 spin_lock_irq(&ice->reg_lock);
1978 change = PRO_RATE_RESET != nval;
1979 PRO_RATE_RESET = nval;
1980 spin_unlock_irq(&ice->reg_lock);
1981 return change;
1982}
1983
f3b827e0 1984static const struct snd_kcontrol_new snd_vt1724_pro_rate_reset = {
1da177e4
LT		 1985 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1986 .name = "Multi Track Rate Reset",
1987 .info = snd_vt1724_pro_rate_reset_info,
1988 .get = snd_vt1724_pro_rate_reset_get,
1989 .put = snd_vt1724_pro_rate_reset_put
1990};
1991
1992
1993/*
1994 * routing
1995 */
ab0c7d72
TI		 1996static int snd_vt1724_pro_route_info(struct snd_kcontrol *kcontrol,
1997 struct snd_ctl_elem_info *uinfo)
1da177e4 1998{
a2af050f 1999 static const char * const texts[] = {
1da177e4
LT		 2000 "PCM Out", /* 0 */
2001 "H/W In 0", "H/W In 1", /* 1-2 */
2002 "IEC958 In L", "IEC958 In R", /* 3-4 */
2003 };
1de9fdc2 2004
597da2e4 2005 return snd_ctl_enum_info(uinfo, 1, 5, texts);
1da177e4
LT		 2006}
2007
2008static inline int analog_route_shift(int idx)
2009{
2010 return (idx % 2) * 12 + ((idx / 2) * 3) + 8;
2011}
2012
2013static inline int digital_route_shift(int idx)
2014{
2015 return idx * 3;
2016}
2017
2bf864ac 2018int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift)
1da177e4
LT		 2019{
2020 unsigned long val;
2021 unsigned char eitem;
32b47da0 2022 static const unsigned char xlate[8] = {
1da177e4
LT		 2023 0, 255, 1, 2, 255, 255, 3, 4,
2024 };
2025
2026 val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
2027 val >>= shift;
1de9fdc2 2028 val &= 7; /* we now have 3 bits per output */
1da177e4
LT		 2029 eitem = xlate[val];
2030 if (eitem == 255) {
2031 snd_BUG();
2032 return 0;
2033 }
2034 return eitem;
2035}
2036
2bf864ac
TI		 2037int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
2038 int shift)
1da177e4
LT		 2039{
2040 unsigned int old_val, nval;
2041 int change;
32b47da0 2042 static const unsigned char xroute[8] = {
1da177e4
LT		 2043 0, /* PCM */
2044 2, /* PSDIN0 Left */
2045 3, /* PSDIN0 Right */
2046 6, /* SPDIN Left */
2047 7, /* SPDIN Right */
2048 };
2049
2050 nval = xroute[val % 5];
2051 val = old_val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
2052 val &= ~(0x07 << shift);
2053 val |= nval << shift;
2054 change = val != old_val;
2055 if (change)
2056 outl(val, ICEMT1724(ice, ROUTE_PLAYBACK));
2057 return change;
2058}
2059
ab0c7d72
TI		 2060static int snd_vt1724_pro_route_analog_get(struct snd_kcontrol *kcontrol,
2061 struct snd_ctl_elem_value *ucontrol)
1da177e4 2062{
ab0c7d72 2063 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 2064 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
ab0c7d72 2065 ucontrol->value.enumerated.item[0] =
2bf864ac 2066 snd_ice1724_get_route_val(ice, analog_route_shift(idx));
1da177e4
LT		 2067 return 0;
2068}
2069
ab0c7d72
TI		 2070static int snd_vt1724_pro_route_analog_put(struct snd_kcontrol *kcontrol,
2071 struct snd_ctl_elem_value *ucontrol)
1da177e4 2072{
ab0c7d72 2073 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 2074 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2bf864ac
TI		 2075 return snd_ice1724_put_route_val(ice,
2076 ucontrol->value.enumerated.item[0],
2077 analog_route_shift(idx));
1da177e4
LT		 2078}
2079
ab0c7d72
TI		 2080static int snd_vt1724_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
2081 struct snd_ctl_elem_value *ucontrol)
1da177e4 2082{
ab0c7d72 2083 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 2084 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
ab0c7d72 2085 ucontrol->value.enumerated.item[0] =
2bf864ac 2086 snd_ice1724_get_route_val(ice, digital_route_shift(idx));
1da177e4
LT		 2087 return 0;
2088}
2089
ab0c7d72
TI		 2090static int snd_vt1724_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
2091 struct snd_ctl_elem_value *ucontrol)
1da177e4 2092{
ab0c7d72 2093 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 2094 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2bf864ac
TI		 2095 return snd_ice1724_put_route_val(ice,
2096 ucontrol->value.enumerated.item[0],
2097 digital_route_shift(idx));
1da177e4
LT		 2098}
2099
6ba1ad38 2100static const struct snd_kcontrol_new snd_vt1724_mixer_pro_analog_route =
2bf864ac 2101{
1da177e4
LT		 2102 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2103 .name = "H/W Playback Route",
2104 .info = snd_vt1724_pro_route_info,
2105 .get = snd_vt1724_pro_route_analog_get,
2106 .put = snd_vt1724_pro_route_analog_put,
2107};
2108
f3b827e0 2109static const struct snd_kcontrol_new snd_vt1724_mixer_pro_spdif_route = {
1da177e4 2110 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1de9fdc2 2111 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
1da177e4
LT		 2112 .info = snd_vt1724_pro_route_info,
2113 .get = snd_vt1724_pro_route_spdif_get,
2114 .put = snd_vt1724_pro_route_spdif_put,
2115 .count = 2,
2116};
2117
2118
ab0c7d72
TI		 2119static int snd_vt1724_pro_peak_info(struct snd_kcontrol *kcontrol,
2120 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2121{
2122 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2123 uinfo->count = 22; /* FIXME: for compatibility with ice1712... */
2124 uinfo->value.integer.min = 0;
2125 uinfo->value.integer.max = 255;
2126 return 0;
2127}
2128
ab0c7d72
TI		 2129static int snd_vt1724_pro_peak_get(struct snd_kcontrol *kcontrol,
2130 struct snd_ctl_elem_value *ucontrol)
1da177e4 2131{
ab0c7d72 2132 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 2133 int idx;
1de9fdc2 2134
1da177e4
LT		 2135 spin_lock_irq(&ice->reg_lock);
2136 for (idx = 0; idx < 22; idx++) {
2137 outb(idx, ICEMT1724(ice, MONITOR_PEAKINDEX));
ab0c7d72
TI		 2138 ucontrol->value.integer.value[idx] =
2139 inb(ICEMT1724(ice, MONITOR_PEAKDATA));
1da177e4
LT		 2140 }
2141 spin_unlock_irq(&ice->reg_lock);
2142 return 0;
2143}
2144
f3b827e0 2145static const struct snd_kcontrol_new snd_vt1724_mixer_pro_peak = {
2bdf6633 2146 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2147 .name = "Multi Track Peak",
2148 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
2149 .info = snd_vt1724_pro_peak_info,
2150 .get = snd_vt1724_pro_peak_get
2151};
2152
2153/*
2154 *
2155 */
2156
aeb0215c 2157static const struct snd_ice1712_card_info no_matched;
1da177e4 2158
52cd0a76
PH		 2159
2160/*
2161 ooAoo cards with no controls
2162*/
aeb0215c 2163static const unsigned char ooaoo_sq210_eeprom[] = {
52cd0a76
PH		 2164 [ICE_EEP2_SYSCONF] = 0x4c, /* 49MHz crystal, no mpu401, no ADC,
2165 1xDACs */
2166 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
2167 [ICE_EEP2_I2S] = 0x78, /* no volume, 96k, 24bit, 192k */
2168 [ICE_EEP2_SPDIF] = 0xc1, /* out-en, out-int, out-ext */
2169 [ICE_EEP2_GPIO_DIR] = 0x00, /* no GPIOs are used */
2170 [ICE_EEP2_GPIO_DIR1] = 0x00,
2171 [ICE_EEP2_GPIO_DIR2] = 0x00,
2172 [ICE_EEP2_GPIO_MASK] = 0xff,
2173 [ICE_EEP2_GPIO_MASK1] = 0xff,
2174 [ICE_EEP2_GPIO_MASK2] = 0xff,
2175
2176 [ICE_EEP2_GPIO_STATE] = 0x00, /* inputs */
2177 [ICE_EEP2_GPIO_STATE1] = 0x00, /* all 1, but GPIO_CPLD_RW
2178 and GPIO15 always zero */
2179 [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
2180};
2181
2182
aeb0215c 2183static const struct snd_ice1712_card_info snd_vt1724_ooaoo_cards[] = {
52cd0a76
PH		 2184 {
2185 .name = "ooAoo SQ210a",
2186 .model = "sq210a",
2187 .eeprom_size = sizeof(ooaoo_sq210_eeprom),
2188 .eeprom_data = ooaoo_sq210_eeprom,
2189 },
2190 { } /* terminator */
2191};
2192
aeb0215c 2193static const struct snd_ice1712_card_info *card_tables[] = {
1da177e4 2194 snd_vt1724_revo_cards,
1de9fdc2 2195 snd_vt1724_amp_cards,
1da177e4
LT		 2196 snd_vt1724_aureon_cards,
2197 snd_vt1720_mobo_cards,
2198 snd_vt1720_pontis_cards,
6b8d6e55 2199 snd_vt1724_prodigy_hifi_cards,
1da177e4
LT		 2200 snd_vt1724_prodigy192_cards,
2201 snd_vt1724_juli_cards,
72cbfd45 2202 snd_vt1724_maya44_cards,
1da177e4 2203 snd_vt1724_phase_cards,
f6cdab5f 2204 snd_vt1724_wtm_cards,
f31639b8 2205 snd_vt1724_se_cards,
6ef80706 2206 snd_vt1724_qtet_cards,
52cd0a76 2207 snd_vt1724_ooaoo_cards,
77b0b254 2208 snd_vt1724_psc724_cards,
1da177e4
LT		 2209 NULL,
2210};
2211
2212
2213/*
2214 */
2215
ab0c7d72 2216static void wait_i2c_busy(struct snd_ice1712 *ice)
1da177e4
LT		 2217{
2218 int t = 0x10000;
2219 while ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_BUSY) && t--)
2220 ;
2221 if (t == -1)
6dfb5aff 2222 dev_err(ice->card->dev, "i2c busy timeout\n");
1da177e4
LT		 2223}
2224
ab0c7d72
TI		 2225unsigned char snd_vt1724_read_i2c(struct snd_ice1712 *ice,
2226 unsigned char dev, unsigned char addr)
1da177e4
LT		 2227{
2228 unsigned char val;
2229
62932df8 2230 mutex_lock(&ice->i2c_mutex);
acec30ff 2231 wait_i2c_busy(ice);
1da177e4
LT		 2232 outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
2233 outb(dev & ~VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
2234 wait_i2c_busy(ice);
2235 val = inb(ICEREG1724(ice, I2C_DATA));
62932df8 2236 mutex_unlock(&ice->i2c_mutex);
e2ea7cfc 2237 /*
6dfb5aff 2238 dev_dbg(ice->card->dev, "i2c_read: [0x%x,0x%x] = 0x%x\n", dev, addr, val);
e2ea7cfc 2239 */
1da177e4
LT		 2240 return val;
2241}
2242
ab0c7d72
TI		 2243void snd_vt1724_write_i2c(struct snd_ice1712 *ice,
2244 unsigned char dev, unsigned char addr, unsigned char data)
1da177e4 2245{
62932df8 2246 mutex_lock(&ice->i2c_mutex);
1da177e4 2247 wait_i2c_busy(ice);
e2ea7cfc 2248 /*
6dfb5aff 2249 dev_dbg(ice->card->dev, "i2c_write: [0x%x,0x%x] = 0x%x\n", dev, addr, data);
e2ea7cfc 2250 */
1da177e4
LT		 2251 outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
2252 outb(data, ICEREG1724(ice, I2C_DATA));
2253 outb(dev | VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
2254 wait_i2c_busy(ice);
62932df8 2255 mutex_unlock(&ice->i2c_mutex);
1da177e4
LT		 2256}
2257
e23e7a14
BP		 2258static int snd_vt1724_read_eeprom(struct snd_ice1712 *ice,
2259 const char *modelname)
1da177e4
LT		 2260{
2261 const int dev = 0xa0; /* EEPROM device address */
2262 unsigned int i, size;
aeb0215c 2263 const struct snd_ice1712_card_info * const *tbl, *c;
1da177e4 2264
1de9fdc2 2265 if (!modelname || !*modelname) {
1da177e4
LT		 2266 ice->eeprom.subvendor = 0;
2267 if ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_EEPROM) != 0)
2268 ice->eeprom.subvendor =
2269 (snd_vt1724_read_i2c(ice, dev, 0x00) << 0) |
1de9fdc2
AB		 2270 (snd_vt1724_read_i2c(ice, dev, 0x01) << 8) |
2271 (snd_vt1724_read_i2c(ice, dev, 0x02) << 16) |
1da177e4 2272 (snd_vt1724_read_i2c(ice, dev, 0x03) << 24);
ab0c7d72
TI		 2273 if (ice->eeprom.subvendor == 0 ||
2274 ice->eeprom.subvendor == (unsigned int)-1) {
2275 /* invalid subvendor from EEPROM, try the PCI
2276 * subststem ID instead
2277 */
1da177e4 2278 u16 vendor, device;
ab0c7d72
TI		 2279 pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID,
2280 &vendor);
1da177e4 2281 pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
ab0c7d72
TI		 2282 ice->eeprom.subvendor =
2283 ((unsigned int)swab16(vendor) << 16) | swab16(device);
2284 if (ice->eeprom.subvendor == 0 ||
2285 ice->eeprom.subvendor == (unsigned int)-1) {
6dfb5aff
TI		 2286 dev_err(ice->card->dev,
2287 "No valid ID is found\n");
1da177e4
LT		 2288 return -ENXIO;
2289 }
2290 }
2291 }
2292 for (tbl = card_tables; *tbl; tbl++) {
2b151ef7 2293 for (c = *tbl; c->name; c++) {
ab0c7d72 2294 if (modelname && c->model &&
1de9fdc2 2295 !strcmp(modelname, c->model)) {
6dfb5aff
TI		 2296 dev_info(ice->card->dev,
2297 "Using board model %s\n",
ab0c7d72 2298 c->name);
1da177e4
LT		 2299 ice->eeprom.subvendor = c->subvendor;
2300 } else if (c->subvendor != ice->eeprom.subvendor)
2301 continue;
267bccaf 2302 ice->card_info = c;
1de9fdc2 2303 if (!c->eeprom_size || !c->eeprom_data)
1da177e4
LT		 2304 goto found;
2305 /* if the EEPROM is given by the driver, use it */
6dfb5aff 2306 dev_dbg(ice->card->dev, "using the defined eeprom..\n");
1da177e4
LT		 2307 ice->eeprom.version = 2;
2308 ice->eeprom.size = c->eeprom_size + 6;
2309 memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
2310 goto read_skipped;
2311 }
2312 }
6dfb5aff 2313 dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
ab0c7d72 2314 ice->eeprom.subvendor);
063f603c 2315#ifdef CONFIG_PM_SLEEP
ef878445
OZ		 2316 /* assume AC97-only card which can suspend without additional code */
2317 ice->pm_suspend_enabled = 1;
063f603c 2318#endif
1da177e4
LT		 2319
2320 found:
2321 ice->eeprom.size = snd_vt1724_read_i2c(ice, dev, 0x04);
2322 if (ice->eeprom.size < 6)
2323 ice->eeprom.size = 32;
2324 else if (ice->eeprom.size > 32) {
6dfb5aff 2325 dev_err(ice->card->dev, "Invalid EEPROM (size = %i)\n",
ab0c7d72 2326 ice->eeprom.size);
1da177e4
LT		 2327 return -EIO;
2328 }
2329 ice->eeprom.version = snd_vt1724_read_i2c(ice, dev, 0x05);
77b0b254 2330 if (ice->eeprom.version != 1 && ice->eeprom.version != 2)
6dfb5aff 2331 dev_warn(ice->card->dev, "Invalid EEPROM version %i\n",
ab0c7d72 2332 ice->eeprom.version);
1da177e4
LT		 2333 size = ice->eeprom.size - 6;
2334 for (i = 0; i < size; i++)
2335 ice->eeprom.data[i] = snd_vt1724_read_i2c(ice, dev, i + 6);
2336
2337 read_skipped:
2338 ice->eeprom.gpiomask = eeprom_triple(ice, ICE_EEP2_GPIO_MASK);
2339 ice->eeprom.gpiostate = eeprom_triple(ice, ICE_EEP2_GPIO_STATE);
2340 ice->eeprom.gpiodir = eeprom_triple(ice, ICE_EEP2_GPIO_DIR);
2341
2342 return 0;
2343}
2344
2345
2346
cd775387 2347static void snd_vt1724_chip_reset(struct snd_ice1712 *ice)
1da177e4
LT		 2348{
2349 outb(VT1724_RESET , ICEREG1724(ice, CONTROL));
d82b64f4 2350 inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
988f0664 2351 msleep(10);
1da177e4 2352 outb(0, ICEREG1724(ice, CONTROL));
d82b64f4 2353 inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
988f0664
KW		 2354 msleep(10);
2355}
2356
b40e9538 2357static int snd_vt1724_chip_init(struct snd_ice1712 *ice)
988f0664 2358{
1da177e4
LT		 2359 outb(ice->eeprom.data[ICE_EEP2_SYSCONF], ICEREG1724(ice, SYS_CFG));
2360 outb(ice->eeprom.data[ICE_EEP2_ACLINK], ICEREG1724(ice, AC97_CFG));
2361 outb(ice->eeprom.data[ICE_EEP2_I2S], ICEREG1724(ice, I2S_FEATURES));
2362 outb(ice->eeprom.data[ICE_EEP2_SPDIF], ICEREG1724(ice, SPDIF_CFG));
2363
2364 ice->gpio.write_mask = ice->eeprom.gpiomask;
2365 ice->gpio.direction = ice->eeprom.gpiodir;
2366 snd_vt1724_set_gpio_mask(ice, ice->eeprom.gpiomask);
2367 snd_vt1724_set_gpio_dir(ice, ice->eeprom.gpiodir);
2368 snd_vt1724_set_gpio_data(ice, ice->eeprom.gpiostate);
2369
2370 outb(0, ICEREG1724(ice, POWERDOWN));
2371
b40e9538
IC		 2372 /* MPU_RX and TX irq masks are cleared later dynamically */
2373 outb(VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX , ICEREG1724(ice, IRQMASK));
2374
2375 /* don't handle FIFO overrun/underruns (just yet),
2376 * since they cause machine lockups
2377 */
2378 outb(VT1724_MULTI_FIFO_ERR, ICEMT1724(ice, DMA_INT_MASK));
2379
1da177e4
LT		 2380 return 0;
2381}
2382
e23e7a14 2383static int snd_vt1724_spdif_build_controls(struct snd_ice1712 *ice)
1da177e4
LT		 2384{
2385 int err;
ab0c7d72 2386 struct snd_kcontrol *kctl;
1da177e4 2387
da3cec35
TI		 2388 if (snd_BUG_ON(!ice->pcm))
2389 return -EIO;
1da177e4 2390
2bf864ac
TI		 2391 if (!ice->own_routing) {
2392 err = snd_ctl_add(ice->card,
2393 snd_ctl_new1(&snd_vt1724_mixer_pro_spdif_route, ice));
2394 if (err < 0)
2395 return err;
2396 }
1da177e4
LT		 2397
2398 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_spdif_switch, ice));
2399 if (err < 0)
2400 return err;
2401
2402 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_default, ice));
2403 if (err < 0)
2404 return err;
2405 kctl->id.device = ice->pcm->device;
2406 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskc, ice));
2407 if (err < 0)
2408 return err;
2409 kctl->id.device = ice->pcm->device;
2410 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskp, ice));
2411 if (err < 0)
2412 return err;
2413 kctl->id.device = ice->pcm->device;
2414#if 0 /* use default only */
2415 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_stream, ice));
2416 if (err < 0)
2417 return err;
2418 kctl->id.device = ice->pcm->device;
2419 ice->spdif.stream_ctl = kctl;
2420#endif
2421 return 0;
2422}
2423
2424
e23e7a14 2425static int snd_vt1724_build_controls(struct snd_ice1712 *ice)
1da177e4
LT		 2426{
2427 int err;
2428
2429 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_eeprom, ice));
2430 if (err < 0)
2431 return err;
2432 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_internal_clock, ice));
2433 if (err < 0)
2434 return err;
2435
2436 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_locking, ice));
2437 if (err < 0)
2438 return err;
2439 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_reset, ice));
2440 if (err < 0)
2441 return err;
2442
2bf864ac 2443 if (!ice->own_routing && ice->num_total_dacs > 0) {
ab0c7d72 2444 struct snd_kcontrol_new tmp = snd_vt1724_mixer_pro_analog_route;
1da177e4
LT		 2445 tmp.count = ice->num_total_dacs;
2446 if (ice->vt1720 && tmp.count > 2)
2447 tmp.count = 2;
2448 err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
2449 if (err < 0)
2450 return err;
2451 }
2452
387417b5
SM		 2453 return snd_ctl_add(ice->card,
2454 snd_ctl_new1(&snd_vt1724_mixer_pro_peak, ice));
1da177e4
LT		 2455}
2456
ab0c7d72 2457static int snd_vt1724_free(struct snd_ice1712 *ice)
1da177e4 2458{
1de9fdc2 2459 if (!ice->port)
1da177e4
LT		 2460 goto __hw_end;
2461 /* mask all interrupts */
2462 outb(0xff, ICEMT1724(ice, DMA_INT_MASK));
2463 outb(0xff, ICEREG1724(ice, IRQMASK));
2464 /* --- */
1de9fdc2 2465__hw_end:
f000fd80 2466 if (ice->irq >= 0)
ab0c7d72 2467 free_irq(ice->irq, ice);
1da177e4
LT		 2468 pci_release_regions(ice->pci);
2469 snd_ice1712_akm4xxx_free(ice);
2470 pci_disable_device(ice->pci);
7cda8ba9 2471 kfree(ice->spec);
1da177e4
LT		 2472 kfree(ice);
2473 return 0;
2474}
2475
ab0c7d72 2476static int snd_vt1724_dev_free(struct snd_device *device)
1da177e4 2477{
ab0c7d72 2478 struct snd_ice1712 *ice = device->device_data;
1da177e4
LT		 2479 return snd_vt1724_free(ice);
2480}
2481
e23e7a14
BP		 2482static int snd_vt1724_create(struct snd_card *card,
2483 struct pci_dev *pci,
2484 const char *modelname,
2485 struct snd_ice1712 **r_ice1712)
1da177e4 2486{
ab0c7d72 2487 struct snd_ice1712 *ice;
1da177e4 2488 int err;
efb0ad25 2489 static const struct snd_device_ops ops = {
1da177e4
LT		 2490 .dev_free = snd_vt1724_dev_free,
2491 };
2492
2493 *r_ice1712 = NULL;
2494
1de9fdc2
AB		 2495 /* enable PCI device */
2496 err = pci_enable_device(pci);
2497 if (err < 0)
1da177e4
LT		 2498 return err;
2499
e560d8d8 2500 ice = kzalloc(sizeof(*ice), GFP_KERNEL);
1da177e4
LT		 2501 if (ice == NULL) {
2502 pci_disable_device(pci);
2503 return -ENOMEM;
2504 }
2505 ice->vt1724 = 1;
2506 spin_lock_init(&ice->reg_lock);
62932df8
IM		 2507 mutex_init(&ice->gpio_mutex);
2508 mutex_init(&ice->open_mutex);
2509 mutex_init(&ice->i2c_mutex);
1da177e4 2510 ice->gpio.set_mask = snd_vt1724_set_gpio_mask;
49470306 2511 ice->gpio.get_mask = snd_vt1724_get_gpio_mask;
1da177e4 2512 ice->gpio.set_dir = snd_vt1724_set_gpio_dir;
49470306 2513 ice->gpio.get_dir = snd_vt1724_get_gpio_dir;
1da177e4
LT		 2514 ice->gpio.set_data = snd_vt1724_set_gpio_data;
2515 ice->gpio.get_data = snd_vt1724_get_gpio_data;
2516 ice->card = card;
2517 ice->pci = pci;
2518 ice->irq = -1;
2519 pci_set_master(pci);
2520 snd_vt1724_proc_init(ice);
1da177e4 2521
b40e9538
IC		 2522 card->private_data = ice;
2523
1de9fdc2
AB		 2524 err = pci_request_regions(pci, "ICE1724");
2525 if (err < 0) {
1da177e4
LT		 2526 kfree(ice);
2527 pci_disable_device(pci);
2528 return err;
2529 }
2530 ice->port = pci_resource_start(pci, 0);
2531 ice->profi_port = pci_resource_start(pci, 1);
2532
ab0c7d72 2533 if (request_irq(pci->irq, snd_vt1724_interrupt,
934c2b6d 2534 IRQF_SHARED, KBUILD_MODNAME, ice)) {
6dfb5aff 2535 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 2536 snd_vt1724_free(ice);
2537 return -EIO;
2538 }
2539
2540 ice->irq = pci->irq;
b0ad3bbc 2541 card->sync_irq = ice->irq;
1da177e4 2542
988f0664 2543 snd_vt1724_chip_reset(ice);
1da177e4
LT		 2544 if (snd_vt1724_read_eeprom(ice, modelname) < 0) {
2545 snd_vt1724_free(ice);
2546 return -EIO;
2547 }
2548 if (snd_vt1724_chip_init(ice) < 0) {
2549 snd_vt1724_free(ice);
2550 return -EIO;
2551 }
2552
1de9fdc2
AB		 2553 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
2554 if (err < 0) {
1da177e4 2555 snd_vt1724_free(ice);
1de9fdc2 2556 return err;
1da177e4
LT		 2557 }
2558
1da177e4
LT		 2559 *r_ice1712 = ice;
2560 return 0;
2561}
2562
2563
2564/*
2565 *
2566 * Registration
2567 *
2568 */
2569
e23e7a14
BP		 2570static int snd_vt1724_probe(struct pci_dev *pci,
2571 const struct pci_device_id *pci_id)
1da177e4
LT		 2572{
2573 static int dev;
ab0c7d72
TI		 2574 struct snd_card *card;
2575 struct snd_ice1712 *ice;
1da177e4 2576 int pcm_dev = 0, err;
aeb0215c 2577 const struct snd_ice1712_card_info * const *tbl, *c;
1da177e4
LT		 2578
2579 if (dev >= SNDRV_CARDS)
2580 return -ENODEV;
2581 if (!enable[dev]) {
2582 dev++;
2583 return -ENOENT;
2584 }
2585
60c5772b
TI		 2586 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2587 0, &card);
e58de7ba
TI		 2588 if (err < 0)
2589 return err;
1da177e4
LT		 2590
2591 strcpy(card->driver, "ICE1724");
2592 strcpy(card->shortname, "ICEnsemble ICE1724");
1de9fdc2
AB		 2593
2594 err = snd_vt1724_create(card, pci, model[dev], &ice);
2595 if (err < 0) {
1da177e4
LT		 2596 snd_card_free(card);
2597 return err;
2598 }
2599
1ff97cb9
PH		 2600 /* field init before calling chip_init */
2601 ice->ext_clock_count = 0;
2602
1da177e4 2603 for (tbl = card_tables; *tbl; tbl++) {
2b151ef7
PH		 2604 for (c = *tbl; c->name; c++) {
2605 if ((model[dev] && c->model &&
2606 !strcmp(model[dev], c->model)) ||
2607 (c->subvendor == ice->eeprom.subvendor)) {
1da177e4
LT		 2608 strcpy(card->shortname, c->name);
2609 if (c->driver) /* specific driver? */
2610 strcpy(card->driver, c->driver);
2611 if (c->chip_init) {
1de9fdc2
AB		 2612 err = c->chip_init(ice);
2613 if (err < 0) {
1da177e4
LT		 2614 snd_card_free(card);
2615 return err;
2616 }
2617 }
2618 goto __found;
2619 }
2620 }
2621 }
2622 c = &no_matched;
1de9fdc2
AB		 2623__found:
2624 /*
2625 * VT1724 has separate DMAs for the analog and the SPDIF streams while
2626 * ICE1712 has only one for both (mixed up).
2627 *
2628 * Confusingly the analog PCM is named "professional" here because it
2629 * was called so in ice1712 driver, and vt1724 driver is derived from
2630 * ice1712 driver.
2631 */
d16be8ed
PH		 2632 ice->pro_rate_default = PRO_RATE_DEFAULT;
2633 if (!ice->is_spdif_master)
2634 ice->is_spdif_master = stdclock_is_spdif_master;
2635 if (!ice->get_rate)
2636 ice->get_rate = stdclock_get_rate;
2637 if (!ice->set_rate)
2638 ice->set_rate = stdclock_set_rate;
2639 if (!ice->set_mclk)
2640 ice->set_mclk = stdclock_set_mclk;
2641 if (!ice->set_spdif_clock)
2642 ice->set_spdif_clock = stdclock_set_spdif_clock;
1ff97cb9
PH		 2643 if (!ice->get_spdif_master_type)
2644 ice->get_spdif_master_type = stdclock_get_spdif_master_type;
2645 if (!ice->ext_clock_names)
2646 ice->ext_clock_names = ext_clock_names;
2647 if (!ice->ext_clock_count)
2648 ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
2649
d16be8ed
PH		 2650 if (!ice->hw_rates)
2651 set_std_hw_rates(ice);
1da177e4 2652
1de9fdc2
AB		 2653 err = snd_vt1724_pcm_profi(ice, pcm_dev++);
2654 if (err < 0) {
1da177e4
LT		 2655 snd_card_free(card);
2656 return err;
2657 }
1de9fdc2
AB		 2658
2659 err = snd_vt1724_pcm_spdif(ice, pcm_dev++);
2660 if (err < 0) {
1da177e4
LT		 2661 snd_card_free(card);
2662 return err;
2663 }
1de9fdc2
AB		 2664
2665 err = snd_vt1724_pcm_indep(ice, pcm_dev++);
2666 if (err < 0) {
1da177e4
LT		 2667 snd_card_free(card);
2668 return err;
2669 }
2670
1de9fdc2
AB		 2671 err = snd_vt1724_ac97_mixer(ice);
2672 if (err < 0) {
1da177e4
LT		 2673 snd_card_free(card);
2674 return err;
2675 }
2676
1de9fdc2
AB		 2677 err = snd_vt1724_build_controls(ice);
2678 if (err < 0) {
1da177e4
LT		 2679 snd_card_free(card);
2680 return err;
2681 }
2682
2683 if (ice->pcm && ice->has_spdif) { /* has SPDIF I/O */
1de9fdc2
AB		 2684 err = snd_vt1724_spdif_build_controls(ice);
2685 if (err < 0) {
1da177e4
LT		 2686 snd_card_free(card);
2687 return err;
2688 }
2689 }
2690
2691 if (c->build_controls) {
1de9fdc2
AB		 2692 err = c->build_controls(ice);
2693 if (err < 0) {
1da177e4
LT		 2694 snd_card_free(card);
2695 return err;
2696 }
2697 }
2698
1de9fdc2 2699 if (!c->no_mpu401) {
1da177e4 2700 if (ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_MPU401) {
aea3bfbc
CL		 2701 struct snd_rawmidi *rmidi;
2702
2703 err = snd_rawmidi_new(card, "MIDI", 0, 1, 1, &rmidi);
2704 if (err < 0) {
1da177e4
LT		 2705 snd_card_free(card);
2706 return err;
2707 }
aea3bfbc
CL		 2708 ice->rmidi[0] = rmidi;
2709 rmidi->private_data = ice;
2710 strcpy(rmidi->name, "ICE1724 MIDI");
2711 rmidi->info_flags = SNDRV_RAWMIDI_INFO_OUTPUT |
2712 SNDRV_RAWMIDI_INFO_INPUT |
2713 SNDRV_RAWMIDI_INFO_DUPLEX;
2714 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT,
2715 &vt1724_midi_output_ops);
2716 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT,
2717 &vt1724_midi_input_ops);
2718
3a841d51
TI		 2719 /* set watermarks */
2720 outb(VT1724_MPU_RX_FIFO | 0x1,
2721 ICEREG1724(ice, MPU_FIFO_WM));
2722 outb(0x1, ICEREG1724(ice, MPU_FIFO_WM));
aea3bfbc
CL		 2723 /* set UART mode */
2724 outb(VT1724_MPU_UART, ICEREG1724(ice, MPU_CTRL));
1da177e4
LT		 2725 }
2726 }
2727
2728 sprintf(card->longname, "%s at 0x%lx, irq %i",
2729 card->shortname, ice->port, ice->irq);
2730
1de9fdc2
AB		 2731 err = snd_card_register(card);
2732 if (err < 0) {
1da177e4
LT		 2733 snd_card_free(card);
2734 return err;
2735 }
2736 pci_set_drvdata(pci, card);
2737 dev++;
2738 return 0;
2739}
2740
e23e7a14 2741static void snd_vt1724_remove(struct pci_dev *pci)
1da177e4 2742{
267bccaf
OZ		 2743 struct snd_card *card = pci_get_drvdata(pci);
2744 struct snd_ice1712 *ice = card->private_data;
2745
2746 if (ice->card_info && ice->card_info->chip_exit)
2747 ice->card_info->chip_exit(ice);
2748 snd_card_free(card);
1da177e4
LT		 2749}
2750
c7561cd8 2751#ifdef CONFIG_PM_SLEEP
68cb2b55 2752static int snd_vt1724_suspend(struct device *dev)
b40e9538 2753{
68cb2b55 2754 struct snd_card *card = dev_get_drvdata(dev);
b40e9538
IC		 2755 struct snd_ice1712 *ice = card->private_data;
2756
2757 if (!ice->pm_suspend_enabled)
2758 return 0;
2759
2760 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2761
b40e9538
IC		 2762 snd_ac97_suspend(ice->ac97);
2763
2764 spin_lock_irq(&ice->reg_lock);
2765 ice->pm_saved_is_spdif_master = ice->is_spdif_master(ice);
2766 ice->pm_saved_spdif_ctrl = inw(ICEMT1724(ice, SPDIF_CTRL));
2767 ice->pm_saved_spdif_cfg = inb(ICEREG1724(ice, SPDIF_CFG));
2768 ice->pm_saved_route = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
2769 spin_unlock_irq(&ice->reg_lock);
2770
2771 if (ice->pm_suspend)
2772 ice->pm_suspend(ice);
b40e9538
IC		 2773 return 0;
2774}
2775
68cb2b55 2776static int snd_vt1724_resume(struct device *dev)
b40e9538 2777{
68cb2b55 2778 struct snd_card *card = dev_get_drvdata(dev);
b40e9538
IC		 2779 struct snd_ice1712 *ice = card->private_data;
2780
2781 if (!ice->pm_suspend_enabled)
2782 return 0;
2783
b40e9538
IC		 2784 snd_vt1724_chip_reset(ice);
2785
2786 if (snd_vt1724_chip_init(ice) < 0) {
2787 snd_card_disconnect(card);
2788 return -EIO;
2789 }
2790
2791 if (ice->pm_resume)
2792 ice->pm_resume(ice);
2793
2794 if (ice->pm_saved_is_spdif_master) {
2795 /* switching to external clock via SPDIF */
1ff97cb9 2796 ice->set_spdif_clock(ice, 0);
b40e9538
IC		 2797 } else {
2798 /* internal on-card clock */
16c2e1fa
TI		 2799 int rate;
2800 if (ice->cur_rate)
2801 rate = ice->cur_rate;
2802 else
2803 rate = ice->pro_rate_default;
2804 snd_vt1724_set_pro_rate(ice, rate, 1);
b40e9538
IC		 2805 }
2806
2807 update_spdif_bits(ice, ice->pm_saved_spdif_ctrl);
2808
2809 outb(ice->pm_saved_spdif_cfg, ICEREG1724(ice, SPDIF_CFG));
2810 outl(ice->pm_saved_route, ICEMT1724(ice, ROUTE_PLAYBACK));
2811
ae1b2265 2812 snd_ac97_resume(ice->ac97);
b40e9538
IC		 2813
2814 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2815 return 0;
2816}
68cb2b55
TI		 2817
2818static SIMPLE_DEV_PM_OPS(snd_vt1724_pm, snd_vt1724_suspend, snd_vt1724_resume);
2819#define SND_VT1724_PM_OPS &snd_vt1724_pm
2820#else
2821#define SND_VT1724_PM_OPS NULL
c7561cd8 2822#endif /* CONFIG_PM_SLEEP */
b40e9538 2823
e9f66d9b 2824static struct pci_driver vt1724_driver = {
3733e424 2825 .name = KBUILD_MODNAME,
1da177e4
LT		 2826 .id_table = snd_vt1724_ids,
2827 .probe = snd_vt1724_probe,
e23e7a14 2828 .remove = snd_vt1724_remove,
68cb2b55
TI		 2829 .driver = {
2830 .pm = SND_VT1724_PM_OPS,
2831 },
1da177e4
LT		 2832};
2833
e9f66d9b 2834module_pci_driver(vt1724_driver);
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