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[ALSA] ac97 - Suppress power-saving mode on non-supporting drivers
[mirror_ubuntu-bionic-kernel.git] / sound / pci / intel8x0.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <sound/driver.h>
30#include <asm/io.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/slab.h>
36#include <linux/moduleparam.h>
37#include <sound/core.h>
38#include <sound/pcm.h>
39#include <sound/ac97_codec.h>
40#include <sound/info.h>
41#include <sound/initval.h>
42/* for 440MX workaround */
43#include <asm/pgtable.h>
44#include <asm/cacheflush.h>
45
46MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
47MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48MODULE_LICENSE("GPL");
49MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
50 "{Intel,82901AB-ICH0},"
51 "{Intel,82801BA-ICH2},"
52 "{Intel,82801CA-ICH3},"
53 "{Intel,82801DB-ICH4},"
54 "{Intel,ICH5},"
55 "{Intel,ICH6},"
56 "{Intel,ICH7},"
57 "{Intel,6300ESB},"
c4c8ea94 58 "{Intel,ESB2},"
1da177e4
LT		 59 "{Intel,MX440},"
60 "{SiS,SI7012},"
61 "{NVidia,nForce Audio},"
62 "{NVidia,nForce2 Audio},"
63 "{AMD,AMD768},"
64 "{AMD,AMD8111},"
65 "{ALI,M5455}}");
66
b7fe4622
CL		 67static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
68static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
6581f4e7 69static int ac97_clock;
b7fe4622
CL		 70static char *ac97_quirk;
71static int buggy_semaphore;
beef08a5 72static int buggy_irq = -1; /* auto-check */
b7fe4622
CL		 73static int xbox;
74
75module_param(index, int, 0444);
1da177e4 76MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
b7fe4622 77module_param(id, charp, 0444);
1da177e4 78MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
b7fe4622 79module_param(ac97_clock, int, 0444);
1da177e4 80MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
b7fe4622 81module_param(ac97_quirk, charp, 0444);
1da177e4 82MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
b7fe4622 83module_param(buggy_semaphore, bool, 0444);
a06147d2 84MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
b7fe4622 85module_param(buggy_irq, bool, 0444);
1da177e4 86MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
b7fe4622 87module_param(xbox, bool, 0444);
1da177e4
LT		 88MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
89
2b3e584b
TI		 90/* just for backward compatibility */
91static int enable;
698444f3 92module_param(enable, bool, 0444);
2b3e584b
TI		 93static int joystick;
94module_param(joystick, int, 0444);
95
1da177e4
LT		 96/*
97 * Direct registers
98 */
1da177e4
LT		 99enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
100
101#define ICHREG(x) ICH_REG_##x
102
103#define DEFINE_REGSET(name,base) \
104enum { \
105 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
106 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
107 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
108 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
109 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
110 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
111 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
112};
113
114/* busmaster blocks */
115DEFINE_REGSET(OFF, 0); /* offset */
116DEFINE_REGSET(PI, 0x00); /* PCM in */
117DEFINE_REGSET(PO, 0x10); /* PCM out */
118DEFINE_REGSET(MC, 0x20); /* Mic in */
119
120/* ICH4 busmaster blocks */
121DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
122DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
123DEFINE_REGSET(SP, 0x60); /* SPDIF out */
124
125/* values for each busmaster block */
126
127/* LVI */
128#define ICH_REG_LVI_MASK 0x1f
129
130/* SR */
131#define ICH_FIFOE 0x10 /* FIFO error */
132#define ICH_BCIS 0x08 /* buffer completion interrupt status */
133#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
134#define ICH_CELV 0x02 /* current equals last valid */
135#define ICH_DCH 0x01 /* DMA controller halted */
136
137/* PIV */
138#define ICH_REG_PIV_MASK 0x1f /* mask */
139
140/* CR */
141#define ICH_IOCE 0x10 /* interrupt on completion enable */
142#define ICH_FEIE 0x08 /* fifo error interrupt enable */
143#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
144#define ICH_RESETREGS 0x02 /* reset busmaster registers */
145#define ICH_STARTBM 0x01 /* start busmaster operation */
146
147
148/* global block */
149#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
150#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
151#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
152#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
153#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
154#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
155#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
156#define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
157#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
158#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
159#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
160#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
161#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
162#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
163#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
164#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
165#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
166#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
167#define ICH_ACLINK 0x00000008 /* AClink shut off */
168#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
169#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
170#define ICH_GIE 0x00000001 /* GPI interrupt enable */
171#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
172#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
173#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
174#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
175#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
176#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
177#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
178#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
179#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
180#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
84a43bd5
TI		 181#define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
182#define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
1da177e4
LT		 183#define ICH_MD3 0x00020000 /* modem power down semaphore */
184#define ICH_AD3 0x00010000 /* audio power down semaphore */
185#define ICH_RCS 0x00008000 /* read completion status */
186#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
187#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
188#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
189#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
190#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
191#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
192#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
193#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
194#define ICH_POINT 0x00000040 /* playback interrupt */
195#define ICH_PIINT 0x00000020 /* capture interrupt */
196#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
197#define ICH_MOINT 0x00000004 /* modem playback interrupt */
198#define ICH_MIINT 0x00000002 /* modem capture interrupt */
199#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
200#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
201#define ICH_CAS 0x01 /* codec access semaphore */
202#define ICH_REG_SDM 0x80
203#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
204#define ICH_DI2L_SHIFT 6
205#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
206#define ICH_DI1L_SHIFT 4
207#define ICH_SE 0x00000008 /* steer enable */
208#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
209
210#define ICH_MAX_FRAGS 32 /* max hw frags */
211
212
213/*
214 * registers for Ali5455
215 */
216
217/* ALi 5455 busmaster blocks */
218DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
219DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
220DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
221DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
222DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
223DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
224DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
225DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
226DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
227DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
228DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
229
230enum {
231 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
232 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
233 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
234 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
235 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
236 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
237 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
238 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
239 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
240 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
241 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
242 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
243 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
244 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
245 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
246 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
247 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
248 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
249 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
250 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
251 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
252};
253
254#define ALI_CAS_SEM_BUSY 0x80000000
255#define ALI_CPR_ADDR_SECONDARY 0x100
256#define ALI_CPR_ADDR_READ 0x80
257#define ALI_CSPSR_CODEC_READY 0x08
258#define ALI_CSPSR_READ_OK 0x02
259#define ALI_CSPSR_WRITE_OK 0x01
260
261/* interrupts for the whole chip by interrupt status register finish */
262
263#define ALI_INT_MICIN2 (1<<26)
264#define ALI_INT_PCMIN2 (1<<25)
265#define ALI_INT_I2SIN (1<<24)
266#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
267#define ALI_INT_SPDIFIN (1<<22)
268#define ALI_INT_LFEOUT (1<<21)
269#define ALI_INT_CENTEROUT (1<<20)
270#define ALI_INT_CODECSPDIFOUT (1<<19)
271#define ALI_INT_MICIN (1<<18)
272#define ALI_INT_PCMOUT (1<<17)
273#define ALI_INT_PCMIN (1<<16)
274#define ALI_INT_CPRAIS (1<<7) /* command port available */
275#define ALI_INT_SPRAIS (1<<5) /* status port available */
276#define ALI_INT_GPIO (1<<1)
6b75a9d8
TI		 277#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
278 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
1da177e4
LT		 279
280#define ICH_ALI_SC_RESET (1<<31) /* master reset */
281#define ICH_ALI_SC_AC97_DBL (1<<30)
282#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
283#define ICH_ALI_SC_IN_BITS (3<<18)
284#define ICH_ALI_SC_OUT_BITS (3<<16)
285#define ICH_ALI_SC_6CH_CFG (3<<14)
286#define ICH_ALI_SC_PCM_4 (1<<8)
287#define ICH_ALI_SC_PCM_6 (2<<8)
288#define ICH_ALI_SC_PCM_246_MASK (3<<8)
289
290#define ICH_ALI_SS_SEC_ID (3<<5)
291#define ICH_ALI_SS_PRI_ID (3<<3)
292
293#define ICH_ALI_IF_AC97SP (1<<21)
294#define ICH_ALI_IF_MC (1<<20)
295#define ICH_ALI_IF_PI (1<<19)
296#define ICH_ALI_IF_MC2 (1<<18)
297#define ICH_ALI_IF_PI2 (1<<17)
298#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
299#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
300#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
301#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
302#define ICH_ALI_IF_PO_SPDF (1<<3)
303#define ICH_ALI_IF_PO (1<<1)
304
305/*
306 *
307 */
308
6b75a9d8
TI		 309enum {
310 ICHD_PCMIN,
311 ICHD_PCMOUT,
312 ICHD_MIC,
313 ICHD_MIC2,
314 ICHD_PCM2IN,
315 ICHD_SPBAR,
316 ICHD_LAST = ICHD_SPBAR
317};
318enum {
319 NVD_PCMIN,
320 NVD_PCMOUT,
321 NVD_MIC,
322 NVD_SPBAR,
323 NVD_LAST = NVD_SPBAR
324};
325enum {
326 ALID_PCMIN,
327 ALID_PCMOUT,
328 ALID_MIC,
329 ALID_AC97SPDIFOUT,
330 ALID_SPDIFIN,
331 ALID_SPDIFOUT,
332 ALID_LAST = ALID_SPDIFOUT
333};
1da177e4 334
6b75a9d8 335#define get_ichdev(substream) (substream->runtime->private_data)
1da177e4 336
6b75a9d8 337struct ichdev {
1da177e4
LT		 338 unsigned int ichd; /* ich device number */
339 unsigned long reg_offset; /* offset to bmaddr */
340 u32 *bdbar; /* CPU address (32bit) */
341 unsigned int bdbar_addr; /* PCI bus address (32bit) */
6b75a9d8 342 struct snd_pcm_substream *substream;
1da177e4
LT		 343 unsigned int physbuf; /* physical address (32bit) */
344 unsigned int size;
345 unsigned int fragsize;
346 unsigned int fragsize1;
347 unsigned int position;
348 unsigned int pos_shift;
349 int frags;
350 int lvi;
351 int lvi_frag;
352 int civ;
353 int ack;
354 int ack_reload;
355 unsigned int ack_bit;
356 unsigned int roff_sr;
357 unsigned int roff_picb;
358 unsigned int int_sta_mask; /* interrupt status mask */
359 unsigned int ali_slot; /* ALI DMA slot */
360 struct ac97_pcm *pcm;
361 int pcm_open_flag;
362 unsigned int page_attr_changed: 1;
1cfe43d2 363 unsigned int suspended: 1;
6b75a9d8 364};
1da177e4 365
6b75a9d8 366struct intel8x0 {
1da177e4
LT		 367 unsigned int device_type;
368
369 int irq;
370
3388c37e
TI		 371 void __iomem *addr;
372 void __iomem *bmaddr;
1da177e4
LT		 373
374 struct pci_dev *pci;
6b75a9d8 375 struct snd_card *card;
1da177e4
LT		 376
377 int pcm_devs;
6b75a9d8
TI		 378 struct snd_pcm *pcm[6];
379 struct ichdev ichd[6];
1da177e4
LT		 380
381 unsigned multi4: 1,
382 multi6: 1,
383 dra: 1,
384 smp20bit: 1;
385 unsigned in_ac97_init: 1,
386 in_sdin_init: 1;
387 unsigned in_measurement: 1; /* during ac97 clock measurement */
388 unsigned fix_nocache: 1; /* workaround for 440MX */
389 unsigned buggy_irq: 1; /* workaround for buggy mobos */
390 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
a06147d2 391 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
1da177e4
LT		 392
393 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
52b72388 394 unsigned int sdm_saved; /* SDM reg value */
1da177e4 395
6b75a9d8
TI		 396 struct snd_ac97_bus *ac97_bus;
397 struct snd_ac97 *ac97[3];
1da177e4 398 unsigned int ac97_sdin[3];
84a43bd5
TI		 399 unsigned int max_codecs, ncodecs;
400 unsigned int *codec_bit;
401 unsigned int codec_isr_bits;
402 unsigned int codec_ready_bits;
1da177e4
LT		 403
404 spinlock_t reg_lock;
405
406 u32 bdbars_count;
407 struct snd_dma_buffer bdbars;
408 u32 int_sta_reg; /* interrupt status register */
409 u32 int_sta_mask; /* interrupt status mask */
410};
411
f40b6890 412static struct pci_device_id snd_intel8x0_ids[] = {
1da177e4
LT		 413 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
414 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
415 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
416 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
417 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
418 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
419 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
420 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
421 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
c4c8ea94 422 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
1da177e4
LT		 423 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
424 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
425 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
426 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
427 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
428 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
429 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
430 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
431 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
89ac9c25 432 { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP51 */
1da177e4
LT		 433 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
434 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
435 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
436 { 0, }
437};
438
439MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
440
441/*
442 * Lowlevel I/O - busmaster
443 */
444
3388c37e 445static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
1da177e4 446{
3388c37e 447 return ioread8(chip->bmaddr + offset);
1da177e4
LT		 448}
449
3388c37e 450static inline u16 igetword(struct intel8x0 *chip, u32 offset)
1da177e4 451{
3388c37e 452 return ioread16(chip->bmaddr + offset);
1da177e4
LT		 453}
454
3388c37e 455static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
1da177e4 456{
3388c37e 457 return ioread32(chip->bmaddr + offset);
1da177e4
LT		 458}
459
3388c37e 460static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
1da177e4 461{
3388c37e 462 iowrite8(val, chip->bmaddr + offset);
1da177e4
LT		 463}
464
3388c37e 465static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
1da177e4 466{
3388c37e 467 iowrite16(val, chip->bmaddr + offset);
1da177e4
LT		 468}
469
3388c37e 470static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
1da177e4 471{
3388c37e 472 iowrite32(val, chip->bmaddr + offset);
1da177e4
LT		 473}
474
475/*
476 * Lowlevel I/O - AC'97 registers
477 */
478
3388c37e 479static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
1da177e4 480{
3388c37e 481 return ioread16(chip->addr + offset);
1da177e4
LT		 482}
483
3388c37e 484static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
1da177e4 485{
3388c37e 486 iowrite16(val, chip->addr + offset);
1da177e4
LT		 487}
488
489/*
490 * Basic I/O
491 */
492
493/*
494 * access to AC97 codec via normal i/o (for ICH and SIS7012)
495 */
496
6b75a9d8 497static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
1da177e4
LT		 498{
499 int time;
500
501 if (codec > 2)
502 return -EIO;
503 if (chip->in_sdin_init) {
504 /* we don't know the ready bit assignment at the moment */
505 /* so we check any */
84a43bd5 506 codec = chip->codec_isr_bits;
1da177e4 507 } else {
84a43bd5 508 codec = chip->codec_bit[chip->ac97_sdin[codec]];
1da177e4
LT		 509 }
510
511 /* codec ready ? */
512 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
513 return -EIO;
514
a06147d2
TI		 515 if (chip->buggy_semaphore)
516 return 0; /* just ignore ... */
517
1da177e4
LT		 518 /* Anyone holding a semaphore for 1 msec should be shot... */
519 time = 100;
520 do {
521 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
522 return 0;
523 udelay(10);
524 } while (time--);
525
526 /* access to some forbidden (non existant) ac97 registers will not
527 * reset the semaphore. So even if you don't get the semaphore, still
528 * continue the access. We don't need the semaphore anyway. */
99b359ba 529 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
1da177e4
LT		 530 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
531 iagetword(chip, 0); /* clear semaphore flag */
532 /* I don't care about the semaphore */
533 return -EBUSY;
534}
535
6b75a9d8 536static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
1da177e4
LT		 537 unsigned short reg,
538 unsigned short val)
539{
6b75a9d8 540 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 541
542 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
543 if (! chip->in_ac97_init)
99b359ba 544 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 545 }
546 iaputword(chip, reg + ac97->num * 0x80, val);
547}
548
6b75a9d8 549static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
1da177e4
LT		 550 unsigned short reg)
551{
6b75a9d8 552 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 553 unsigned short res;
554 unsigned int tmp;
555
556 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
557 if (! chip->in_ac97_init)
99b359ba 558 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 559 res = 0xffff;
560 } else {
561 res = iagetword(chip, reg + ac97->num * 0x80);
562 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
563 /* reset RCS and preserve other R/WC bits */
6b75a9d8 564 iputdword(chip, ICHREG(GLOB_STA), tmp &
84a43bd5 565 ~(chip->codec_ready_bits | ICH_GSCI));
1da177e4 566 if (! chip->in_ac97_init)
99b359ba 567 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 568 res = 0xffff;
569 }
570 }
571 return res;
572}
573
84a43bd5
TI		 574static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
575 unsigned int codec)
1da177e4
LT		 576{
577 unsigned int tmp;
578
579 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
580 iagetword(chip, codec * 0x80);
581 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
582 /* reset RCS and preserve other R/WC bits */
6b75a9d8 583 iputdword(chip, ICHREG(GLOB_STA), tmp &
84a43bd5 584 ~(chip->codec_ready_bits | ICH_GSCI));
1da177e4
LT		 585 }
586 }
587}
588
589/*
590 * access to AC97 for Ali5455
591 */
6b75a9d8 592static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
1da177e4
LT		 593{
594 int count = 0;
595 for (count = 0; count < 0x7f; count++) {
596 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
597 if (val & mask)
598 return 0;
599 }
79ba34b9
TI		 600 if (! chip->in_ac97_init)
601 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
1da177e4
LT		 602 return -EBUSY;
603}
604
6b75a9d8 605static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
1da177e4
LT		 606{
607 int time = 100;
79ba34b9
TI		 608 if (chip->buggy_semaphore)
609 return 0; /* just ignore ... */
1da177e4
LT		 610 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
611 udelay(1);
79ba34b9 612 if (! time && ! chip->in_ac97_init)
1da177e4
LT		 613 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
614 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
615}
616
6b75a9d8 617static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
1da177e4 618{
6b75a9d8 619 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 620 unsigned short data = 0xffff;
621
622 if (snd_intel8x0_ali_codec_semaphore(chip))
623 goto __err;
624 reg |= ALI_CPR_ADDR_READ;
625 if (ac97->num)
626 reg |= ALI_CPR_ADDR_SECONDARY;
627 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
628 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
629 goto __err;
630 data = igetword(chip, ICHREG(ALI_SPR));
631 __err:
632 return data;
633}
634
6b75a9d8
TI		 635static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
636 unsigned short val)
1da177e4 637{
6b75a9d8 638 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 639
640 if (snd_intel8x0_ali_codec_semaphore(chip))
641 return;
642 iputword(chip, ICHREG(ALI_CPR), val);
643 if (ac97->num)
644 reg |= ALI_CPR_ADDR_SECONDARY;
645 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
646 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
647}
648
649
650/*
651 * DMA I/O
652 */
6b75a9d8 653static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
1da177e4
LT		 654{
655 int idx;
656 u32 *bdbar = ichdev->bdbar;
657 unsigned long port = ichdev->reg_offset;
658
659 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
660 if (ichdev->size == ichdev->fragsize) {
661 ichdev->ack_reload = ichdev->ack = 2;
662 ichdev->fragsize1 = ichdev->fragsize >> 1;
663 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
664 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
665 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
666 ichdev->fragsize1 >> ichdev->pos_shift);
667 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
668 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
669 ichdev->fragsize1 >> ichdev->pos_shift);
670 }
671 ichdev->frags = 2;
672 } else {
673 ichdev->ack_reload = ichdev->ack = 1;
674 ichdev->fragsize1 = ichdev->fragsize;
675 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
6b75a9d8
TI		 676 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
677 (((idx >> 1) * ichdev->fragsize) %
678 ichdev->size));
1da177e4
LT		 679 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
680 ichdev->fragsize >> ichdev->pos_shift);
6b75a9d8
TI		 681#if 0
682 printk("bdbar[%i] = 0x%x [0x%x]\n",
683 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
684#endif
1da177e4
LT		 685 }
686 ichdev->frags = ichdev->size / ichdev->fragsize;
687 }
688 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
689 ichdev->civ = 0;
690 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
691 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
692 ichdev->position = 0;
693#if 0
694 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
695 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
696#endif
697 /* clear interrupts */
698 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
699}
700
701#ifdef __i386__
702/*
703 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
704 * which aborts PCI busmaster for audio transfer. A workaround is to set
705 * the pages as non-cached. For details, see the errata in
706 * http://www.intel.com/design/chipsets/specupdt/245051.htm
707 */
708static void fill_nocache(void *buf, int size, int nocache)
709{
710 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
711 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
712 global_flush_tlb();
713}
714#else
715#define fill_nocache(buf,size,nocache)
716#endif
717
718/*
719 * Interrupt handler
720 */
721
6b75a9d8 722static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
1da177e4
LT		 723{
724 unsigned long port = ichdev->reg_offset;
725 int status, civ, i, step;
726 int ack = 0;
727
728 spin_lock(&chip->reg_lock);
729 status = igetbyte(chip, port + ichdev->roff_sr);
730 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
731 if (!(status & ICH_BCIS)) {
732 step = 0;
733 } else if (civ == ichdev->civ) {
734 // snd_printd("civ same %d\n", civ);
735 step = 1;
736 ichdev->civ++;
737 ichdev->civ &= ICH_REG_LVI_MASK;
738 } else {
739 step = civ - ichdev->civ;
740 if (step < 0)
741 step += ICH_REG_LVI_MASK + 1;
742 // if (step != 1)
743 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
744 ichdev->civ = civ;
745 }
746
747 ichdev->position += step * ichdev->fragsize1;
748 if (! chip->in_measurement)
749 ichdev->position %= ichdev->size;
750 ichdev->lvi += step;
751 ichdev->lvi &= ICH_REG_LVI_MASK;
752 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
753 for (i = 0; i < step; i++) {
754 ichdev->lvi_frag++;
755 ichdev->lvi_frag %= ichdev->frags;
756 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
6b75a9d8
TI		 757#if 0
758 printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
759 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
760 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
761 inl(port + 4), inb(port + ICH_REG_OFF_CR));
762#endif
1da177e4
LT		 763 if (--ichdev->ack == 0) {
764 ichdev->ack = ichdev->ack_reload;
765 ack = 1;
766 }
767 }
768 spin_unlock(&chip->reg_lock);
769 if (ack && ichdev->substream) {
770 snd_pcm_period_elapsed(ichdev->substream);
771 }
772 iputbyte(chip, port + ichdev->roff_sr,
773 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
774}
775
7d12e780 776static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
1da177e4 777{
6b75a9d8
TI		 778 struct intel8x0 *chip = dev_id;
779 struct ichdev *ichdev;
1da177e4
LT		 780 unsigned int status;
781 unsigned int i;
782
783 status = igetdword(chip, chip->int_sta_reg);
784 if (status == 0xffffffff) /* we are not yet resumed */
785 return IRQ_NONE;
786
787 if ((status & chip->int_sta_mask) == 0) {
788 if (status) {
789 /* ack */
790 iputdword(chip, chip->int_sta_reg, status);
791 if (! chip->buggy_irq)
792 status = 0;
793 }
794 return IRQ_RETVAL(status);
795 }
796
797 for (i = 0; i < chip->bdbars_count; i++) {
798 ichdev = &chip->ichd[i];
799 if (status & ichdev->int_sta_mask)
800 snd_intel8x0_update(chip, ichdev);
801 }
802
803 /* ack them */
804 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
805
806 return IRQ_HANDLED;
807}
808
809/*
810 * PCM part
811 */
812
6b75a9d8 813static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 814{
6b75a9d8
TI		 815 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
816 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 817 unsigned char val = 0;
818 unsigned long port = ichdev->reg_offset;
819
820 switch (cmd) {
1da177e4 821 case SNDRV_PCM_TRIGGER_RESUME:
1cfe43d2
TI		 822 ichdev->suspended = 0;
823 /* fallthru */
824 case SNDRV_PCM_TRIGGER_START:
1da177e4
LT		 825 val = ICH_IOCE | ICH_STARTBM;
826 break;
1da177e4 827 case SNDRV_PCM_TRIGGER_SUSPEND:
1cfe43d2
TI		 828 ichdev->suspended = 1;
829 /* fallthru */
830 case SNDRV_PCM_TRIGGER_STOP:
1da177e4
LT		 831 val = 0;
832 break;
833 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
834 val = ICH_IOCE;
835 break;
836 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
837 val = ICH_IOCE | ICH_STARTBM;
838 break;
839 default:
840 return -EINVAL;
841 }
842 iputbyte(chip, port + ICH_REG_OFF_CR, val);
843 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
844 /* wait until DMA stopped */
845 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
846 /* reset whole DMA things */
847 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
848 }
849 return 0;
850}
851
6b75a9d8 852static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 853{
6b75a9d8
TI		 854 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
855 struct ichdev *ichdev = get_ichdev(substream);
1da177e4 856 unsigned long port = ichdev->reg_offset;
6b75a9d8
TI		 857 static int fiforeg[] = {
858 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
859 };
1da177e4
LT		 860 unsigned int val, fifo;
861
862 val = igetdword(chip, ICHREG(ALI_DMACR));
863 switch (cmd) {
1cfe43d2
TI		 864 case SNDRV_PCM_TRIGGER_RESUME:
865 ichdev->suspended = 0;
866 /* fallthru */
1da177e4
LT		 867 case SNDRV_PCM_TRIGGER_START:
868 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1da177e4
LT		 869 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
870 /* clear FIFO for synchronization of channels */
871 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
872 fifo &= ~(0xff << (ichdev->ali_slot % 4));
873 fifo |= 0x83 << (ichdev->ali_slot % 4);
874 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
875 }
876 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
877 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
6b75a9d8
TI		 878 /* start DMA */
879 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
1da177e4 880 break;
1cfe43d2
TI		 881 case SNDRV_PCM_TRIGGER_SUSPEND:
882 ichdev->suspended = 1;
883 /* fallthru */
1da177e4
LT		 884 case SNDRV_PCM_TRIGGER_STOP:
885 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
6b75a9d8
TI		 886 /* pause */
887 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
1da177e4
LT		 888 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
889 while (igetbyte(chip, port + ICH_REG_OFF_CR))
890 ;
891 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
892 break;
893 /* reset whole DMA things */
894 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
895 /* clear interrupts */
6b75a9d8
TI		 896 iputbyte(chip, port + ICH_REG_OFF_SR,
897 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
1da177e4
LT		 898 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
899 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
900 break;
901 default:
902 return -EINVAL;
903 }
904 return 0;
905}
906
6b75a9d8
TI		 907static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
908 struct snd_pcm_hw_params *hw_params)
1da177e4 909{
6b75a9d8
TI		 910 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
911 struct ichdev *ichdev = get_ichdev(substream);
912 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 913 int dbl = params_rate(hw_params) > 48000;
914 int err;
915
916 if (chip->fix_nocache && ichdev->page_attr_changed) {
917 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
918 ichdev->page_attr_changed = 0;
919 }
920 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
921 if (err < 0)
922 return err;
923 if (chip->fix_nocache) {
924 if (runtime->dma_area && ! ichdev->page_attr_changed) {
925 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
926 ichdev->page_attr_changed = 1;
927 }
928 }
929 if (ichdev->pcm_open_flag) {
930 snd_ac97_pcm_close(ichdev->pcm);
931 ichdev->pcm_open_flag = 0;
932 }
933 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
934 params_channels(hw_params),
935 ichdev->pcm->r[dbl].slots);
936 if (err >= 0) {
937 ichdev->pcm_open_flag = 1;
938 /* Force SPDIF setting */
939 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
6b75a9d8
TI		 940 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
941 params_rate(hw_params));
1da177e4
LT		 942 }
943 return err;
944}
945
6b75a9d8 946static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
1da177e4 947{
6b75a9d8
TI		 948 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
949 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 950
951 if (ichdev->pcm_open_flag) {
952 snd_ac97_pcm_close(ichdev->pcm);
953 ichdev->pcm_open_flag = 0;
954 }
955 if (chip->fix_nocache && ichdev->page_attr_changed) {
956 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
957 ichdev->page_attr_changed = 0;
958 }
959 return snd_pcm_lib_free_pages(substream);
960}
961
6b75a9d8
TI		 962static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
963 struct snd_pcm_runtime *runtime)
1da177e4
LT		 964{
965 unsigned int cnt;
966 int dbl = runtime->rate > 48000;
1cfe43d2
TI		 967
968 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 969 switch (chip->device_type) {
970 case DEVICE_ALI:
971 cnt = igetdword(chip, ICHREG(ALI_SCR));
972 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
973 if (runtime->channels == 4 || dbl)
974 cnt |= ICH_ALI_SC_PCM_4;
975 else if (runtime->channels == 6)
976 cnt |= ICH_ALI_SC_PCM_6;
977 iputdword(chip, ICHREG(ALI_SCR), cnt);
978 break;
979 case DEVICE_SIS:
980 cnt = igetdword(chip, ICHREG(GLOB_CNT));
981 cnt &= ~ICH_SIS_PCM_246_MASK;
982 if (runtime->channels == 4 || dbl)
983 cnt |= ICH_SIS_PCM_4;
984 else if (runtime->channels == 6)
985 cnt |= ICH_SIS_PCM_6;
986 iputdword(chip, ICHREG(GLOB_CNT), cnt);
987 break;
988 default:
989 cnt = igetdword(chip, ICHREG(GLOB_CNT));
990 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
991 if (runtime->channels == 4 || dbl)
992 cnt |= ICH_PCM_4;
993 else if (runtime->channels == 6)
994 cnt |= ICH_PCM_6;
995 if (chip->device_type == DEVICE_NFORCE) {
996 /* reset to 2ch once to keep the 6 channel data in alignment,
997 * to start from Front Left always
998 */
999 if (cnt & ICH_PCM_246_MASK) {
1000 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1001 spin_unlock_irq(&chip->reg_lock);
1002 msleep(50); /* grrr... */
1003 spin_lock_irq(&chip->reg_lock);
1004 }
1005 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1006 if (runtime->sample_bits > 16)
1007 cnt |= ICH_PCM_20BIT;
1008 }
1009 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1010 break;
1011 }
1cfe43d2 1012 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1013}
1014
6b75a9d8 1015static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4 1016{
6b75a9d8
TI		 1017 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1018 struct snd_pcm_runtime *runtime = substream->runtime;
1019 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 1020
1021 ichdev->physbuf = runtime->dma_addr;
1022 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1023 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1da177e4
LT		 1024 if (ichdev->ichd == ICHD_PCMOUT) {
1025 snd_intel8x0_setup_pcm_out(chip, runtime);
1cfe43d2 1026 if (chip->device_type == DEVICE_INTEL_ICH4)
1da177e4 1027 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1da177e4
LT		 1028 }
1029 snd_intel8x0_setup_periods(chip, ichdev);
1da177e4
LT		 1030 return 0;
1031}
1032
6b75a9d8 1033static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 1034{
6b75a9d8
TI		 1035 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1036 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 1037 size_t ptr1, ptr;
1038 int civ, timeout = 100;
1039 unsigned int position;
1040
1041 spin_lock(&chip->reg_lock);
1042 do {
1043 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1044 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1045 position = ichdev->position;
1046 if (ptr1 == 0) {
1047 udelay(10);
1048 continue;
1049 }
1050 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1051 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1052 break;
1053 } while (timeout--);
1054 ptr1 <<= ichdev->pos_shift;
1055 ptr = ichdev->fragsize1 - ptr1;
1056 ptr += position;
1057 spin_unlock(&chip->reg_lock);
1058 if (ptr >= ichdev->size)
1059 return 0;
1060 return bytes_to_frames(substream->runtime, ptr);
1061}
1062
6b75a9d8 1063static struct snd_pcm_hardware snd_intel8x0_stream =
1da177e4
LT		 1064{
1065 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1066 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1067 SNDRV_PCM_INFO_MMAP_VALID |
1068 SNDRV_PCM_INFO_PAUSE |
1069 SNDRV_PCM_INFO_RESUME),
1070 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1071 .rates = SNDRV_PCM_RATE_48000,
1072 .rate_min = 48000,
1073 .rate_max = 48000,
1074 .channels_min = 2,
1075 .channels_max = 2,
1076 .buffer_bytes_max = 128 * 1024,
1077 .period_bytes_min = 32,
1078 .period_bytes_max = 128 * 1024,
1079 .periods_min = 1,
1080 .periods_max = 1024,
1081 .fifo_size = 0,
1082};
1083
1084static unsigned int channels4[] = {
1085 2, 4,
1086};
1087
6b75a9d8 1088static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1da177e4
LT		 1089 .count = ARRAY_SIZE(channels4),
1090 .list = channels4,
1091 .mask = 0,
1092};
1093
1094static unsigned int channels6[] = {
1095 2, 4, 6,
1096};
1097
6b75a9d8 1098static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1da177e4
LT		 1099 .count = ARRAY_SIZE(channels6),
1100 .list = channels6,
1101 .mask = 0,
1102};
1103
6b75a9d8 1104static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1da177e4 1105{
6b75a9d8
TI		 1106 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1107 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1108 int err;
1109
1110 ichdev->substream = substream;
1111 runtime->hw = snd_intel8x0_stream;
1112 runtime->hw.rates = ichdev->pcm->rates;
1113 snd_pcm_limit_hw_rates(runtime);
1114 if (chip->device_type == DEVICE_SIS) {
1115 runtime->hw.buffer_bytes_max = 64*1024;
1116 runtime->hw.period_bytes_max = 64*1024;
1117 }
1118 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1119 return err;
1120 runtime->private_data = ichdev;
1121 return 0;
1122}
1123
6b75a9d8 1124static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1da177e4 1125{
6b75a9d8
TI		 1126 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1127 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1128 int err;
1129
1130 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1131 if (err < 0)
1132 return err;
1133
1134 if (chip->multi6) {
1135 runtime->hw.channels_max = 6;
6b75a9d8
TI		 1136 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1137 &hw_constraints_channels6);
1da177e4
LT		 1138 } else if (chip->multi4) {
1139 runtime->hw.channels_max = 4;
6b75a9d8
TI		 1140 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1141 &hw_constraints_channels4);
1da177e4
LT		 1142 }
1143 if (chip->dra) {
1144 snd_ac97_pcm_double_rate_rules(runtime);
1145 }
1146 if (chip->smp20bit) {
1147 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1148 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1149 }
1150 return 0;
1151}
1152
6b75a9d8 1153static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1da177e4 1154{
6b75a9d8 1155 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1156
1157 chip->ichd[ICHD_PCMOUT].substream = NULL;
1158 return 0;
1159}
1160
6b75a9d8 1161static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1da177e4 1162{
6b75a9d8 1163 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1164
1165 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1166}
1167
6b75a9d8 1168static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1da177e4 1169{
6b75a9d8 1170 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1171
1172 chip->ichd[ICHD_PCMIN].substream = NULL;
1173 return 0;
1174}
1175
6b75a9d8 1176static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1da177e4 1177{
6b75a9d8 1178 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1179
1180 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1181}
1182
6b75a9d8 1183static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1da177e4 1184{
6b75a9d8 1185 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1186
1187 chip->ichd[ICHD_MIC].substream = NULL;
1188 return 0;
1189}
1190
6b75a9d8 1191static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1da177e4 1192{
6b75a9d8 1193 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1194
1195 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1196}
1197
6b75a9d8 1198static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1da177e4 1199{
6b75a9d8 1200 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1201
1202 chip->ichd[ICHD_MIC2].substream = NULL;
1203 return 0;
1204}
1205
6b75a9d8 1206static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1da177e4 1207{
6b75a9d8 1208 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1209
1210 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1211}
1212
6b75a9d8 1213static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1da177e4 1214{
6b75a9d8 1215 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1216
1217 chip->ichd[ICHD_PCM2IN].substream = NULL;
1218 return 0;
1219}
1220
6b75a9d8 1221static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1da177e4 1222{
6b75a9d8 1223 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1224 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1225
1226 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1227}
1228
6b75a9d8 1229static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1da177e4 1230{
6b75a9d8 1231 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1232 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1233
1234 chip->ichd[idx].substream = NULL;
1235 return 0;
1236}
1237
6b75a9d8 1238static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1da177e4 1239{
6b75a9d8 1240 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1241 unsigned int val;
1242
1243 spin_lock_irq(&chip->reg_lock);
1244 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1245 val |= ICH_ALI_IF_AC97SP;
1246 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1247 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1248 spin_unlock_irq(&chip->reg_lock);
1249
1250 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1251}
1252
6b75a9d8 1253static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1da177e4 1254{
6b75a9d8 1255 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1256 unsigned int val;
1257
1258 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1259 spin_lock_irq(&chip->reg_lock);
1260 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1261 val &= ~ICH_ALI_IF_AC97SP;
1262 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1263 spin_unlock_irq(&chip->reg_lock);
1264
1265 return 0;
1266}
1267
1a183131 1268#if 0 // NYI
6b75a9d8 1269static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1da177e4 1270{
6b75a9d8 1271 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1272
1273 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1274}
1275
6b75a9d8 1276static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1da177e4 1277{
6b75a9d8 1278 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1279
1280 chip->ichd[ALID_SPDIFIN].substream = NULL;
1281 return 0;
1282}
1283
6b75a9d8 1284static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1da177e4 1285{
6b75a9d8 1286 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1287
1288 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1289}
1290
6b75a9d8 1291static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1da177e4 1292{
6b75a9d8 1293 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1294
1295 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1296 return 0;
1297}
1298#endif
1299
6b75a9d8 1300static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1da177e4
LT		 1301 .open = snd_intel8x0_playback_open,
1302 .close = snd_intel8x0_playback_close,
1303 .ioctl = snd_pcm_lib_ioctl,
1304 .hw_params = snd_intel8x0_hw_params,
1305 .hw_free = snd_intel8x0_hw_free,
1306 .prepare = snd_intel8x0_pcm_prepare,
1307 .trigger = snd_intel8x0_pcm_trigger,
1308 .pointer = snd_intel8x0_pcm_pointer,
1309};
1310
6b75a9d8 1311static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1da177e4
LT		 1312 .open = snd_intel8x0_capture_open,
1313 .close = snd_intel8x0_capture_close,
1314 .ioctl = snd_pcm_lib_ioctl,
1315 .hw_params = snd_intel8x0_hw_params,
1316 .hw_free = snd_intel8x0_hw_free,
1317 .prepare = snd_intel8x0_pcm_prepare,
1318 .trigger = snd_intel8x0_pcm_trigger,
1319 .pointer = snd_intel8x0_pcm_pointer,
1320};
1321
6b75a9d8 1322static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1da177e4
LT		 1323 .open = snd_intel8x0_mic_open,
1324 .close = snd_intel8x0_mic_close,
1325 .ioctl = snd_pcm_lib_ioctl,
1326 .hw_params = snd_intel8x0_hw_params,
1327 .hw_free = snd_intel8x0_hw_free,
1328 .prepare = snd_intel8x0_pcm_prepare,
1329 .trigger = snd_intel8x0_pcm_trigger,
1330 .pointer = snd_intel8x0_pcm_pointer,
1331};
1332
6b75a9d8 1333static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1da177e4
LT		 1334 .open = snd_intel8x0_mic2_open,
1335 .close = snd_intel8x0_mic2_close,
1336 .ioctl = snd_pcm_lib_ioctl,
1337 .hw_params = snd_intel8x0_hw_params,
1338 .hw_free = snd_intel8x0_hw_free,
1339 .prepare = snd_intel8x0_pcm_prepare,
1340 .trigger = snd_intel8x0_pcm_trigger,
1341 .pointer = snd_intel8x0_pcm_pointer,
1342};
1343
6b75a9d8 1344static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1da177e4
LT		 1345 .open = snd_intel8x0_capture2_open,
1346 .close = snd_intel8x0_capture2_close,
1347 .ioctl = snd_pcm_lib_ioctl,
1348 .hw_params = snd_intel8x0_hw_params,
1349 .hw_free = snd_intel8x0_hw_free,
1350 .prepare = snd_intel8x0_pcm_prepare,
1351 .trigger = snd_intel8x0_pcm_trigger,
1352 .pointer = snd_intel8x0_pcm_pointer,
1353};
1354
6b75a9d8 1355static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1da177e4
LT		 1356 .open = snd_intel8x0_spdif_open,
1357 .close = snd_intel8x0_spdif_close,
1358 .ioctl = snd_pcm_lib_ioctl,
1359 .hw_params = snd_intel8x0_hw_params,
1360 .hw_free = snd_intel8x0_hw_free,
1361 .prepare = snd_intel8x0_pcm_prepare,
1362 .trigger = snd_intel8x0_pcm_trigger,
1363 .pointer = snd_intel8x0_pcm_pointer,
1364};
1365
6b75a9d8 1366static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1da177e4
LT		 1367 .open = snd_intel8x0_playback_open,
1368 .close = snd_intel8x0_playback_close,
1369 .ioctl = snd_pcm_lib_ioctl,
1370 .hw_params = snd_intel8x0_hw_params,
1371 .hw_free = snd_intel8x0_hw_free,
1372 .prepare = snd_intel8x0_pcm_prepare,
1373 .trigger = snd_intel8x0_ali_trigger,
1374 .pointer = snd_intel8x0_pcm_pointer,
1375};
1376
6b75a9d8 1377static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1da177e4
LT		 1378 .open = snd_intel8x0_capture_open,
1379 .close = snd_intel8x0_capture_close,
1380 .ioctl = snd_pcm_lib_ioctl,
1381 .hw_params = snd_intel8x0_hw_params,
1382 .hw_free = snd_intel8x0_hw_free,
1383 .prepare = snd_intel8x0_pcm_prepare,
1384 .trigger = snd_intel8x0_ali_trigger,
1385 .pointer = snd_intel8x0_pcm_pointer,
1386};
1387
6b75a9d8 1388static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1da177e4
LT		 1389 .open = snd_intel8x0_mic_open,
1390 .close = snd_intel8x0_mic_close,
1391 .ioctl = snd_pcm_lib_ioctl,
1392 .hw_params = snd_intel8x0_hw_params,
1393 .hw_free = snd_intel8x0_hw_free,
1394 .prepare = snd_intel8x0_pcm_prepare,
1395 .trigger = snd_intel8x0_ali_trigger,
1396 .pointer = snd_intel8x0_pcm_pointer,
1397};
1398
6b75a9d8 1399static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1da177e4
LT		 1400 .open = snd_intel8x0_ali_ac97spdifout_open,
1401 .close = snd_intel8x0_ali_ac97spdifout_close,
1402 .ioctl = snd_pcm_lib_ioctl,
1403 .hw_params = snd_intel8x0_hw_params,
1404 .hw_free = snd_intel8x0_hw_free,
1405 .prepare = snd_intel8x0_pcm_prepare,
1406 .trigger = snd_intel8x0_ali_trigger,
1407 .pointer = snd_intel8x0_pcm_pointer,
1408};
1409
1a183131 1410#if 0 // NYI
6b75a9d8 1411static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1da177e4
LT		 1412 .open = snd_intel8x0_ali_spdifin_open,
1413 .close = snd_intel8x0_ali_spdifin_close,
1414 .ioctl = snd_pcm_lib_ioctl,
1415 .hw_params = snd_intel8x0_hw_params,
1416 .hw_free = snd_intel8x0_hw_free,
1417 .prepare = snd_intel8x0_pcm_prepare,
1418 .trigger = snd_intel8x0_pcm_trigger,
1419 .pointer = snd_intel8x0_pcm_pointer,
1420};
1421
6b75a9d8 1422static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1da177e4
LT		 1423 .open = snd_intel8x0_ali_spdifout_open,
1424 .close = snd_intel8x0_ali_spdifout_close,
1425 .ioctl = snd_pcm_lib_ioctl,
1426 .hw_params = snd_intel8x0_hw_params,
1427 .hw_free = snd_intel8x0_hw_free,
1428 .prepare = snd_intel8x0_pcm_prepare,
1429 .trigger = snd_intel8x0_pcm_trigger,
1430 .pointer = snd_intel8x0_pcm_pointer,
1431};
1432#endif // NYI
1433
1434struct ich_pcm_table {
1435 char *suffix;
6b75a9d8
TI		 1436 struct snd_pcm_ops *playback_ops;
1437 struct snd_pcm_ops *capture_ops;
1da177e4
LT		 1438 size_t prealloc_size;
1439 size_t prealloc_max_size;
1440 int ac97_idx;
1441};
1442
6b75a9d8
TI		 1443static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1444 struct ich_pcm_table *rec)
1da177e4 1445{
6b75a9d8 1446 struct snd_pcm *pcm;
1da177e4
LT		 1447 int err;
1448 char name[32];
1449
1450 if (rec->suffix)
1451 sprintf(name, "Intel ICH - %s", rec->suffix);
1452 else
1453 strcpy(name, "Intel ICH");
1454 err = snd_pcm_new(chip->card, name, device,
1455 rec->playback_ops ? 1 : 0,
1456 rec->capture_ops ? 1 : 0, &pcm);
1457 if (err < 0)
1458 return err;
1459
1460 if (rec->playback_ops)
1461 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1462 if (rec->capture_ops)
1463 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1464
1465 pcm->private_data = chip;
1466 pcm->info_flags = 0;
1467 if (rec->suffix)
1468 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1469 else
1470 strcpy(pcm->name, chip->card->shortname);
1471 chip->pcm[device] = pcm;
1472
6b75a9d8
TI		 1473 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1474 snd_dma_pci_data(chip->pci),
1da177e4
LT		 1475 rec->prealloc_size, rec->prealloc_max_size);
1476
1477 return 0;
1478}
1479
1480static struct ich_pcm_table intel_pcms[] __devinitdata = {
1481 {
1482 .playback_ops = &snd_intel8x0_playback_ops,
1483 .capture_ops = &snd_intel8x0_capture_ops,
1484 .prealloc_size = 64 * 1024,
1485 .prealloc_max_size = 128 * 1024,
1486 },
1487 {
1488 .suffix = "MIC ADC",
1489 .capture_ops = &snd_intel8x0_capture_mic_ops,
1490 .prealloc_size = 0,
1491 .prealloc_max_size = 128 * 1024,
1492 .ac97_idx = ICHD_MIC,
1493 },
1494 {
1495 .suffix = "MIC2 ADC",
1496 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1497 .prealloc_size = 0,
1498 .prealloc_max_size = 128 * 1024,
1499 .ac97_idx = ICHD_MIC2,
1500 },
1501 {
1502 .suffix = "ADC2",
1503 .capture_ops = &snd_intel8x0_capture2_ops,
1504 .prealloc_size = 0,
1505 .prealloc_max_size = 128 * 1024,
1506 .ac97_idx = ICHD_PCM2IN,
1507 },
1508 {
1509 .suffix = "IEC958",
1510 .playback_ops = &snd_intel8x0_spdif_ops,
1511 .prealloc_size = 64 * 1024,
1512 .prealloc_max_size = 128 * 1024,
1513 .ac97_idx = ICHD_SPBAR,
1514 },
1515};
1516
1517static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1518 {
1519 .playback_ops = &snd_intel8x0_playback_ops,
1520 .capture_ops = &snd_intel8x0_capture_ops,
1521 .prealloc_size = 64 * 1024,
1522 .prealloc_max_size = 128 * 1024,
1523 },
1524 {
1525 .suffix = "MIC ADC",
1526 .capture_ops = &snd_intel8x0_capture_mic_ops,
1527 .prealloc_size = 0,
1528 .prealloc_max_size = 128 * 1024,
1529 .ac97_idx = NVD_MIC,
1530 },
1531 {
1532 .suffix = "IEC958",
1533 .playback_ops = &snd_intel8x0_spdif_ops,
1534 .prealloc_size = 64 * 1024,
1535 .prealloc_max_size = 128 * 1024,
1536 .ac97_idx = NVD_SPBAR,
1537 },
1538};
1539
1540static struct ich_pcm_table ali_pcms[] __devinitdata = {
1541 {
1542 .playback_ops = &snd_intel8x0_ali_playback_ops,
1543 .capture_ops = &snd_intel8x0_ali_capture_ops,
1544 .prealloc_size = 64 * 1024,
1545 .prealloc_max_size = 128 * 1024,
1546 },
1547 {
1548 .suffix = "MIC ADC",
1549 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1550 .prealloc_size = 0,
1551 .prealloc_max_size = 128 * 1024,
1552 .ac97_idx = ALID_MIC,
1553 },
1554 {
1555 .suffix = "IEC958",
1556 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1a183131 1557 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
1da177e4
LT		 1558 .prealloc_size = 64 * 1024,
1559 .prealloc_max_size = 128 * 1024,
1560 .ac97_idx = ALID_AC97SPDIFOUT,
1561 },
1562#if 0 // NYI
1563 {
1564 .suffix = "HW IEC958",
1565 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1566 .prealloc_size = 64 * 1024,
1567 .prealloc_max_size = 128 * 1024,
1568 },
1569#endif
1570};
1571
6b75a9d8 1572static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1da177e4
LT		 1573{
1574 int i, tblsize, device, err;
1575 struct ich_pcm_table *tbl, *rec;
1576
1577 switch (chip->device_type) {
1578 case DEVICE_INTEL_ICH4:
1579 tbl = intel_pcms;
1580 tblsize = ARRAY_SIZE(intel_pcms);
1581 break;
1582 case DEVICE_NFORCE:
1583 tbl = nforce_pcms;
1584 tblsize = ARRAY_SIZE(nforce_pcms);
1585 break;
1586 case DEVICE_ALI:
1587 tbl = ali_pcms;
1588 tblsize = ARRAY_SIZE(ali_pcms);
1589 break;
1590 default:
1591 tbl = intel_pcms;
1592 tblsize = 2;
1593 break;
1594 }
1595
1596 device = 0;
1597 for (i = 0; i < tblsize; i++) {
1598 rec = tbl + i;
1599 if (i > 0 && rec->ac97_idx) {
1600 /* activate PCM only when associated AC'97 codec */
1601 if (! chip->ichd[rec->ac97_idx].pcm)
1602 continue;
1603 }
1604 err = snd_intel8x0_pcm1(chip, device, rec);
1605 if (err < 0)
1606 return err;
1607 device++;
1608 }
1609
1610 chip->pcm_devs = device;
1611 return 0;
1612}
1613
1614
1615/*
1616 * Mixer part
1617 */
1618
6b75a9d8 1619static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1da177e4 1620{
6b75a9d8 1621 struct intel8x0 *chip = bus->private_data;
1da177e4
LT		 1622 chip->ac97_bus = NULL;
1623}
1624
6b75a9d8 1625static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1626{
6b75a9d8 1627 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 1628 chip->ac97[ac97->num] = NULL;
1629}
1630
1631static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1632 /* front PCM */
1633 {
1634 .exclusive = 1,
1635 .r = { {
1636 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1637 (1 << AC97_SLOT_PCM_RIGHT) |
1638 (1 << AC97_SLOT_PCM_CENTER) |
1639 (1 << AC97_SLOT_PCM_SLEFT) |
1640 (1 << AC97_SLOT_PCM_SRIGHT) |
1641 (1 << AC97_SLOT_LFE)
1642 },
1643 {
1644 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1645 (1 << AC97_SLOT_PCM_RIGHT) |
1646 (1 << AC97_SLOT_PCM_LEFT_0) |
1647 (1 << AC97_SLOT_PCM_RIGHT_0)
1648 }
1649 }
1650 },
1651 /* PCM IN #1 */
1652 {
1653 .stream = 1,
1654 .exclusive = 1,
1655 .r = { {
1656 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1657 (1 << AC97_SLOT_PCM_RIGHT)
1658 }
1659 }
1660 },
1661 /* MIC IN #1 */
1662 {
1663 .stream = 1,
1664 .exclusive = 1,
1665 .r = { {
1666 .slots = (1 << AC97_SLOT_MIC)
1667 }
1668 }
1669 },
1670 /* S/PDIF PCM */
1671 {
1672 .exclusive = 1,
1673 .spdif = 1,
1674 .r = { {
1675 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1676 (1 << AC97_SLOT_SPDIF_RIGHT2)
1677 }
1678 }
1679 },
1680 /* PCM IN #2 */
1681 {
1682 .stream = 1,
1683 .exclusive = 1,
1684 .r = { {
1685 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1686 (1 << AC97_SLOT_PCM_RIGHT)
1687 }
1688 }
1689 },
1690 /* MIC IN #2 */
1691 {
1692 .stream = 1,
1693 .exclusive = 1,
1694 .r = { {
1695 .slots = (1 << AC97_SLOT_MIC)
1696 }
1697 }
1698 },
1699};
1700
1701static struct ac97_quirk ac97_quirks[] __devinitdata = {
1702 {
6fd8b87f
JCD		 1703 .subvendor = 0x0e11,
1704 .subdevice = 0x008a,
1da177e4
LT		 1705 .name = "Compaq Evo W4000", /* AD1885 */
1706 .type = AC97_TUNE_HP_ONLY
1707 },
1708 {
6fd8b87f
JCD		 1709 .subvendor = 0x0e11,
1710 .subdevice = 0x00b8,
1da177e4
LT		 1711 .name = "Compaq Evo D510C",
1712 .type = AC97_TUNE_HP_ONLY
1713 },
1714 {
6fd8b87f
JCD		 1715 .subvendor = 0x0e11,
1716 .subdevice = 0x0860,
1da177e4
LT		 1717 .name = "HP/Compaq nx7010",
1718 .type = AC97_TUNE_MUTE_LED
1719 },
1720 {
6fd8b87f
JCD		 1721 .subvendor = 0x1014,
1722 .subdevice = 0x1f00,
1da177e4
LT		 1723 .name = "MS-9128",
1724 .type = AC97_TUNE_ALC_JACK
1725 },
5d529390
TI		 1726 {
1727 .subvendor = 0x1014,
1728 .subdevice = 0x0267,
1729 .name = "IBM NetVista A30p", /* AD1981B */
1730 .type = AC97_TUNE_HP_ONLY
1731 },
72c8986c
DS		 1732 {
1733 .subvendor = 0x1025,
1734 .subdevice = 0x0083,
1735 .name = "Acer Aspire 3003LCi",
1736 .type = AC97_TUNE_HP_ONLY
1737 },
1da177e4 1738 {
6fd8b87f
JCD		 1739 .subvendor = 0x1028,
1740 .subdevice = 0x00d8,
1da177e4
LT		 1741 .name = "Dell Precision 530", /* AD1885 */
1742 .type = AC97_TUNE_HP_ONLY
1743 },
1744 {
6fd8b87f
JCD		 1745 .subvendor = 0x1028,
1746 .subdevice = 0x010d,
1da177e4
LT		 1747 .name = "Dell", /* which model? AD1885 */
1748 .type = AC97_TUNE_HP_ONLY
1749 },
1750 {
6fd8b87f
JCD		 1751 .subvendor = 0x1028,
1752 .subdevice = 0x0126,
1da177e4
LT		 1753 .name = "Dell Optiplex GX260", /* AD1981A */
1754 .type = AC97_TUNE_HP_ONLY
1755 },
1756 {
6fd8b87f
JCD		 1757 .subvendor = 0x1028,
1758 .subdevice = 0x012c,
1da177e4
LT		 1759 .name = "Dell Precision 650", /* AD1981A */
1760 .type = AC97_TUNE_HP_ONLY
1761 },
1762 {
6fd8b87f
JCD		 1763 .subvendor = 0x1028,
1764 .subdevice = 0x012d,
1da177e4
LT		 1765 .name = "Dell Precision 450", /* AD1981B*/
1766 .type = AC97_TUNE_HP_ONLY
1767 },
1768 {
6fd8b87f
JCD		 1769 .subvendor = 0x1028,
1770 .subdevice = 0x0147,
1da177e4
LT		 1771 .name = "Dell", /* which model? AD1981B*/
1772 .type = AC97_TUNE_HP_ONLY
1773 },
c9fe51c4
CB		 1774 {
1775 .subvendor = 0x1028,
1776 .subdevice = 0x0151,
1777 .name = "Dell Optiplex GX270", /* AD1981B */
1778 .type = AC97_TUNE_HP_ONLY
1779 },
1781a9af
DC		 1780 {
1781 .subvendor = 0x1028,
1782 .subdevice = 0x014e,
1783 .name = "Dell D800", /* STAC9750/51 */
1784 .type = AC97_TUNE_HP_ONLY
1785 },
1da177e4 1786 {
6fd8b87f
JCD		 1787 .subvendor = 0x1028,
1788 .subdevice = 0x0163,
1da177e4
LT		 1789 .name = "Dell Unknown", /* STAC9750/51 */
1790 .type = AC97_TUNE_HP_ONLY
1791 },
6d6f9156
KL		 1792 {
1793 .subvendor = 0x1028,
1794 .subdevice = 0x0191,
1795 .name = "Dell Inspiron 8600",
1796 .type = AC97_TUNE_HP_ONLY
1797 },
1da177e4 1798 {
6fd8b87f
JCD		 1799 .subvendor = 0x103c,
1800 .subdevice = 0x006d,
1da177e4
LT		 1801 .name = "HP zv5000",
1802 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1803 },
1804 { /* FIXME: which codec? */
6fd8b87f
JCD		 1805 .subvendor = 0x103c,
1806 .subdevice = 0x00c3,
1da177e4
LT		 1807 .name = "HP xw6000",
1808 .type = AC97_TUNE_HP_ONLY
1809 },
1810 {
6fd8b87f
JCD		 1811 .subvendor = 0x103c,
1812 .subdevice = 0x088c,
1da177e4
LT		 1813 .name = "HP nc8000",
1814 .type = AC97_TUNE_MUTE_LED
1815 },
1816 {
6fd8b87f
JCD		 1817 .subvendor = 0x103c,
1818 .subdevice = 0x0890,
1da177e4
LT		 1819 .name = "HP nc6000",
1820 .type = AC97_TUNE_MUTE_LED
1821 },
e0c93cf3
DH		 1822 {
1823 .subvendor = 0x103c,
1824 .subdevice = 0x0934,
1825 .name = "HP nx8220",
1826 .type = AC97_TUNE_MUTE_LED
1827 },
1da177e4 1828 {
6fd8b87f
JCD		 1829 .subvendor = 0x103c,
1830 .subdevice = 0x129d,
1da177e4
LT		 1831 .name = "HP xw8000",
1832 .type = AC97_TUNE_HP_ONLY
1833 },
a0faefed
MG		 1834 {
1835 .subvendor = 0x103c,
1836 .subdevice = 0x0938,
1837 .name = "HP nc4200",
1838 .type = AC97_TUNE_HP_MUTE_LED
1839 },
1840 {
1841 .subvendor = 0x103c,
1842 .subdevice = 0x099c,
d82ed2ff 1843 .name = "HP nx6110/nc6120",
a0faefed
MG		 1844 .type = AC97_TUNE_HP_MUTE_LED
1845 },
1846 {
1847 .subvendor = 0x103c,
1848 .subdevice = 0x0944,
1849 .name = "HP nc6220",
1850 .type = AC97_TUNE_HP_MUTE_LED
1851 },
1852 {
1853 .subvendor = 0x103c,
1854 .subdevice = 0x0934,
1855 .name = "HP nc8220",
1856 .type = AC97_TUNE_HP_MUTE_LED
1857 },
1da177e4 1858 {
6fd8b87f
JCD		 1859 .subvendor = 0x103c,
1860 .subdevice = 0x12f1,
1da177e4
LT		 1861 .name = "HP xw8200", /* AD1981B*/
1862 .type = AC97_TUNE_HP_ONLY
1863 },
1864 {
6fd8b87f
JCD		 1865 .subvendor = 0x103c,
1866 .subdevice = 0x12f2,
1da177e4
LT		 1867 .name = "HP xw6200",
1868 .type = AC97_TUNE_HP_ONLY
1869 },
1870 {
6fd8b87f
JCD		 1871 .subvendor = 0x103c,
1872 .subdevice = 0x3008,
1da177e4
LT		 1873 .name = "HP xw4200", /* AD1981B*/
1874 .type = AC97_TUNE_HP_ONLY
1875 },
1876 {
6fd8b87f
JCD		 1877 .subvendor = 0x104d,
1878 .subdevice = 0x8197,
1da177e4
LT		 1879 .name = "Sony S1XP",
1880 .type = AC97_TUNE_INV_EAPD
1881 },
1882 {
6fd8b87f
JCD		 1883 .subvendor = 0x1043,
1884 .subdevice = 0x80f3,
1da177e4
LT		 1885 .name = "ASUS ICH5/AD1985",
1886 .type = AC97_TUNE_AD_SHARING
1887 },
1888 {
6fd8b87f
JCD		 1889 .subvendor = 0x10cf,
1890 .subdevice = 0x11c3,
1da177e4
LT		 1891 .name = "Fujitsu-Siemens E4010",
1892 .type = AC97_TUNE_HP_ONLY
1893 },
98c7f212
TI		 1894 {
1895 .subvendor = 0x10cf,
1896 .subdevice = 0x1225,
1897 .name = "Fujitsu-Siemens T3010",
1898 .type = AC97_TUNE_HP_ONLY
1899 },
1da177e4 1900 {
6fd8b87f
JCD		 1901 .subvendor = 0x10cf,
1902 .subdevice = 0x1253,
1da177e4
LT		 1903 .name = "Fujitsu S6210", /* STAC9750/51 */
1904 .type = AC97_TUNE_HP_ONLY
1905 },
9970dce5
TI		 1906 {
1907 .subvendor = 0x10cf,
1908 .subdevice = 0x12ec,
1909 .name = "Fujitsu-Siemens 4010",
1910 .type = AC97_TUNE_HP_ONLY
1911 },
2eb061f4
JK		 1912 {
1913 .subvendor = 0x10cf,
1914 .subdevice = 0x12f2,
1915 .name = "Fujitsu-Siemens Celsius H320",
1916 .type = AC97_TUNE_SWAP_HP
1917 },
1da177e4 1918 {
6fd8b87f
JCD		 1919 .subvendor = 0x10f1,
1920 .subdevice = 0x2665,
1da177e4
LT		 1921 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1922 .type = AC97_TUNE_HP_ONLY
1923 },
1924 {
6fd8b87f
JCD		 1925 .subvendor = 0x10f1,
1926 .subdevice = 0x2885,
1da177e4
LT		 1927 .name = "AMD64 Mobo", /* ALC650 */
1928 .type = AC97_TUNE_HP_ONLY
1929 },
4f42bcc1
TI		 1930 {
1931 .subvendor = 0x10f1,
1932 .subdevice = 0x2895,
1933 .name = "Tyan Thunder K8WE",
1934 .type = AC97_TUNE_HP_ONLY
1935 },
6c504447
KP		 1936 {
1937 .subvendor = 0x10f7,
1938 .subdevice = 0x834c,
1939 .name = "Panasonic CF-R4",
1940 .type = AC97_TUNE_HP_ONLY,
1941 },
1da177e4 1942 {
6fd8b87f
JCD		 1943 .subvendor = 0x110a,
1944 .subdevice = 0x0056,
1da177e4
LT		 1945 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1946 .type = AC97_TUNE_HP_ONLY
1947 },
1948 {
6fd8b87f
JCD		 1949 .subvendor = 0x11d4,
1950 .subdevice = 0x5375,
1da177e4
LT		 1951 .name = "ADI AD1985 (discrete)",
1952 .type = AC97_TUNE_HP_ONLY
1953 },
1954 {
6fd8b87f
JCD		 1955 .subvendor = 0x1462,
1956 .subdevice = 0x5470,
1da177e4
LT		 1957 .name = "MSI P4 ATX 645 Ultra",
1958 .type = AC97_TUNE_HP_ONLY
1959 },
1960 {
6fd8b87f
JCD		 1961 .subvendor = 0x1734,
1962 .subdevice = 0x0088,
1da177e4
LT		 1963 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1964 .type = AC97_TUNE_HP_ONLY
1965 },
1966 {
6fd8b87f
JCD		 1967 .subvendor = 0x8086,
1968 .subdevice = 0x2000,
1da177e4
LT		 1969 .mask = 0xfff0,
1970 .name = "Intel ICH5/AD1985",
1971 .type = AC97_TUNE_AD_SHARING
1972 },
1973 {
6fd8b87f
JCD		 1974 .subvendor = 0x8086,
1975 .subdevice = 0x4000,
1da177e4
LT		 1976 .mask = 0xfff0,
1977 .name = "Intel ICH5/AD1985",
1978 .type = AC97_TUNE_AD_SHARING
1979 },
1980 {
6fd8b87f
JCD		 1981 .subvendor = 0x8086,
1982 .subdevice = 0x4856,
1da177e4
LT		 1983 .name = "Intel D845WN (82801BA)",
1984 .type = AC97_TUNE_SWAP_HP
1985 },
1986 {
6fd8b87f
JCD		 1987 .subvendor = 0x8086,
1988 .subdevice = 0x4d44,
1da177e4
LT		 1989 .name = "Intel D850EMV2", /* AD1885 */
1990 .type = AC97_TUNE_HP_ONLY
1991 },
1992 {
6fd8b87f
JCD		 1993 .subvendor = 0x8086,
1994 .subdevice = 0x4d56,
1da177e4
LT		 1995 .name = "Intel ICH/AD1885",
1996 .type = AC97_TUNE_HP_ONLY
1997 },
1998 {
6fd8b87f
JCD		 1999 .subvendor = 0x8086,
2000 .subdevice = 0x6000,
1da177e4
LT		 2001 .mask = 0xfff0,
2002 .name = "Intel ICH5/AD1985",
2003 .type = AC97_TUNE_AD_SHARING
2004 },
2005 {
6fd8b87f
JCD		 2006 .subvendor = 0x8086,
2007 .subdevice = 0xe000,
1da177e4
LT		 2008 .mask = 0xfff0,
2009 .name = "Intel ICH5/AD1985",
2010 .type = AC97_TUNE_AD_SHARING
2011 },
2012#if 0 /* FIXME: this seems wrong on most boards */
2013 {
6fd8b87f
JCD		 2014 .subvendor = 0x8086,
2015 .subdevice = 0xa000,
1da177e4
LT		 2016 .mask = 0xfff0,
2017 .name = "Intel ICH5/AD1985",
2018 .type = AC97_TUNE_HP_ONLY
2019 },
2020#endif
2021 { } /* terminator */
2022};
2023
6b75a9d8
TI		 2024static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2025 const char *quirk_override)
1da177e4 2026{
6b75a9d8
TI		 2027 struct snd_ac97_bus *pbus;
2028 struct snd_ac97_template ac97;
1da177e4
LT		 2029 int err;
2030 unsigned int i, codecs;
2031 unsigned int glob_sta = 0;
6b75a9d8
TI		 2032 struct snd_ac97_bus_ops *ops;
2033 static struct snd_ac97_bus_ops standard_bus_ops = {
1da177e4
LT		 2034 .write = snd_intel8x0_codec_write,
2035 .read = snd_intel8x0_codec_read,
2036 };
6b75a9d8 2037 static struct snd_ac97_bus_ops ali_bus_ops = {
1da177e4
LT		 2038 .write = snd_intel8x0_ali_codec_write,
2039 .read = snd_intel8x0_ali_codec_read,
2040 };
2041
2042 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2043 switch (chip->device_type) {
2044 case DEVICE_NFORCE:
2045 chip->spdif_idx = NVD_SPBAR;
2046 break;
2047 case DEVICE_ALI:
2048 chip->spdif_idx = ALID_AC97SPDIFOUT;
2049 break;
2050 case DEVICE_INTEL_ICH4:
2051 chip->spdif_idx = ICHD_SPBAR;
2052 break;
2053 };
2054
2055 chip->in_ac97_init = 1;
2056
2057 memset(&ac97, 0, sizeof(ac97));
2058 ac97.private_data = chip;
2059 ac97.private_free = snd_intel8x0_mixer_free_ac97;
f1a63a38 2060 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
1da177e4
LT		 2061 if (chip->xbox)
2062 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2063 if (chip->device_type != DEVICE_ALI) {
2064 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2065 ops = &standard_bus_ops;
84a43bd5
TI		 2066 chip->in_sdin_init = 1;
2067 codecs = 0;
2068 for (i = 0; i < chip->max_codecs; i++) {
2069 if (! (glob_sta & chip->codec_bit[i]))
2070 continue;
2071 if (chip->device_type == DEVICE_INTEL_ICH4) {
2072 snd_intel8x0_codec_read_test(chip, codecs);
2073 chip->ac97_sdin[codecs] =
2074 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2075 snd_assert(chip->ac97_sdin[codecs] < 3,
2076 chip->ac97_sdin[codecs] = 0);
2077 } else
2078 chip->ac97_sdin[codecs] = i;
2079 codecs++;
1da177e4 2080 }
84a43bd5
TI		 2081 chip->in_sdin_init = 0;
2082 if (! codecs)
2083 codecs = 1;
1da177e4
LT		 2084 } else {
2085 ops = &ali_bus_ops;
2086 codecs = 1;
2087 /* detect the secondary codec */
2088 for (i = 0; i < 100; i++) {
2089 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2090 if (reg & 0x40) {
2091 codecs = 2;
2092 break;
2093 }
2094 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2095 udelay(1);
2096 }
2097 }
2098 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2099 goto __err;
2100 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
1da177e4
LT		 2101 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2102 pbus->clock = ac97_clock;
2103 /* FIXME: my test board doesn't work well with VRA... */
2104 if (chip->device_type == DEVICE_ALI)
2105 pbus->no_vra = 1;
2106 else
2107 pbus->dra = 1;
2108 chip->ac97_bus = pbus;
84a43bd5 2109 chip->ncodecs = codecs;
1da177e4
LT		 2110
2111 ac97.pci = chip->pci;
2112 for (i = 0; i < codecs; i++) {
2113 ac97.num = i;
2114 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2115 if (err != -EACCES)
2116 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2117 if (i == 0)
2118 goto __err;
2119 continue;
2120 }
2121 }
2122 /* tune up the primary codec */
2123 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2124 /* enable separate SDINs for ICH4 */
2125 if (chip->device_type == DEVICE_INTEL_ICH4)
2126 pbus->isdin = 1;
2127 /* find the available PCM streams */
2128 i = ARRAY_SIZE(ac97_pcm_defs);
2129 if (chip->device_type != DEVICE_INTEL_ICH4)
2130 i -= 2; /* do not allocate PCM2IN and MIC2 */
2131 if (chip->spdif_idx < 0)
2132 i--; /* do not allocate S/PDIF */
2133 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2134 if (err < 0)
2135 goto __err;
2136 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2137 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2138 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2139 if (chip->spdif_idx >= 0)
2140 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2141 if (chip->device_type == DEVICE_INTEL_ICH4) {
2142 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2143 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2144 }
2145 /* enable separate SDINs for ICH4 */
2146 if (chip->device_type == DEVICE_INTEL_ICH4) {
2147 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2148 u8 tmp = igetbyte(chip, ICHREG(SDM));
2149 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2150 if (pcm) {
2151 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2152 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2153 for (i = 1; i < 4; i++) {
2154 if (pcm->r[0].codec[i]) {
2155 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2156 break;
2157 }
2158 }
2159 } else {
2160 tmp &= ~ICH_SE; /* steer disable */
2161 }
2162 iputbyte(chip, ICHREG(SDM), tmp);
2163 }
2164 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2165 chip->multi4 = 1;
2166 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2167 chip->multi6 = 1;
2168 }
2169 if (pbus->pcms[0].r[1].rslots[0]) {
2170 chip->dra = 1;
2171 }
2172 if (chip->device_type == DEVICE_INTEL_ICH4) {
2173 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2174 chip->smp20bit = 1;
2175 }
2176 if (chip->device_type == DEVICE_NFORCE) {
2177 /* 48kHz only */
2178 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2179 }
2180 if (chip->device_type == DEVICE_INTEL_ICH4) {
2181 /* use slot 10/11 for SPDIF */
2182 u32 val;
2183 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2184 val |= ICH_PCM_SPDIF_1011;
2185 iputdword(chip, ICHREG(GLOB_CNT), val);
2186 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2187 }
2188 chip->in_ac97_init = 0;
2189 return 0;
2190
2191 __err:
2192 /* clear the cold-reset bit for the next chance */
2193 if (chip->device_type != DEVICE_ALI)
6b75a9d8
TI		 2194 iputdword(chip, ICHREG(GLOB_CNT),
2195 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
1da177e4
LT		 2196 return err;
2197}
2198
2199
2200/*
2201 *
2202 */
2203
6b75a9d8 2204static void do_ali_reset(struct intel8x0 *chip)
1da177e4
LT		 2205{
2206 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2207 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2208 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2209 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2210 iputdword(chip, ICHREG(ALI_INTERFACECR),
d78bec21 2211 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
1da177e4
LT		 2212 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2213 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2214}
2215
6b75a9d8 2216static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
1da177e4
LT		 2217{
2218 unsigned long end_time;
2219 unsigned int cnt, status, nstatus;
2220
2221 /* put logic to right state */
2222 /* first clear status bits */
2223 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2224 if (chip->device_type == DEVICE_NFORCE)
2225 status |= ICH_NVSPINT;
2226 cnt = igetdword(chip, ICHREG(GLOB_STA));
2227 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2228
2229 /* ACLink on, 2 channels */
2230 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2231 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
6dbe6628
TI		 2232#ifdef CONFIG_SND_AC97_POWER_SAVE
2233 /* do cold reset - the full ac97 powerdown may leave the controller
2234 * in a warm state but actually it cannot communicate with the codec.
2235 */
2236 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
2237 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2238 udelay(10);
2239 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
2240 msleep(1);
2241#else
1da177e4
LT		 2242 /* finish cold or do warm reset */
2243 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2244 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2245 end_time = (jiffies + (HZ / 4)) + 1;
2246 do {
2247 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2248 goto __ok;
954bea35 2249 schedule_timeout_uninterruptible(1);
1da177e4 2250 } while (time_after_eq(end_time, jiffies));
6b75a9d8
TI		 2251 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2252 igetdword(chip, ICHREG(GLOB_CNT)));
1da177e4
LT		 2253 return -EIO;
2254
2255 __ok:
6dbe6628 2256#endif
1da177e4
LT		 2257 if (probing) {
2258 /* wait for any codec ready status.
2259 * Once it becomes ready it should remain ready
2260 * as long as we do not disable the ac97 link.
2261 */
2262 end_time = jiffies + HZ;
2263 do {
6b75a9d8 2264 status = igetdword(chip, ICHREG(GLOB_STA)) &
84a43bd5 2265 chip->codec_isr_bits;
1da177e4
LT		 2266 if (status)
2267 break;
954bea35 2268 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2269 } while (time_after_eq(end_time, jiffies));
2270 if (! status) {
2271 /* no codec is found */
6b75a9d8
TI		 2272 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2273 igetdword(chip, ICHREG(GLOB_STA)));
1da177e4
LT		 2274 return -EIO;
2275 }
2276
1da177e4
LT		 2277 /* wait for other codecs ready status. */
2278 end_time = jiffies + HZ / 4;
84a43bd5
TI		 2279 while (status != chip->codec_isr_bits &&
2280 time_after_eq(end_time, jiffies)) {
954bea35 2281 schedule_timeout_uninterruptible(1);
84a43bd5
TI		 2282 status |= igetdword(chip, ICHREG(GLOB_STA)) &
2283 chip->codec_isr_bits;
1da177e4
LT		 2284 }
2285
2286 } else {
2287 /* resume phase */
2288 int i;
2289 status = 0;
84a43bd5 2290 for (i = 0; i < chip->ncodecs; i++)
1da177e4 2291 if (chip->ac97[i])
84a43bd5 2292 status |= chip->codec_bit[chip->ac97_sdin[i]];
1da177e4
LT		 2293 /* wait until all the probed codecs are ready */
2294 end_time = jiffies + HZ;
2295 do {
6b75a9d8 2296 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
84a43bd5 2297 chip->codec_isr_bits;
1da177e4
LT		 2298 if (status == nstatus)
2299 break;
954bea35 2300 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2301 } while (time_after_eq(end_time, jiffies));
2302 }
2303
2304 if (chip->device_type == DEVICE_SIS) {
2305 /* unmute the output on SIS7012 */
2306 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2307 }
2308 if (chip->device_type == DEVICE_NFORCE) {
2309 /* enable SPDIF interrupt */
2310 unsigned int val;
2311 pci_read_config_dword(chip->pci, 0x4c, &val);
2312 val |= 0x1000000;
2313 pci_write_config_dword(chip->pci, 0x4c, val);
2314 }
2315 return 0;
2316}
2317
6b75a9d8 2318static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
1da177e4
LT		 2319{
2320 u32 reg;
2321 int i = 0;
2322
2323 reg = igetdword(chip, ICHREG(ALI_SCR));
2324 if ((reg & 2) == 0) /* Cold required */
2325 reg |= 2;
2326 else
2327 reg |= 1; /* Warm */
2328 reg &= ~0x80000000; /* ACLink on */
2329 iputdword(chip, ICHREG(ALI_SCR), reg);
2330
2331 for (i = 0; i < HZ / 2; i++) {
2332 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2333 goto __ok;
954bea35 2334 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2335 }
2336 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2337 if (probing)
2338 return -EIO;
2339
2340 __ok:
2341 for (i = 0; i < HZ / 2; i++) {
2342 reg = igetdword(chip, ICHREG(ALI_RTSR));
2343 if (reg & 0x80) /* primary codec */
2344 break;
2345 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
954bea35 2346 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2347 }
2348
2349 do_ali_reset(chip);
2350 return 0;
2351}
2352
6b75a9d8 2353static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
1da177e4 2354{
253b999f 2355 unsigned int i, timeout;
1da177e4
LT		 2356 int err;
2357
2358 if (chip->device_type != DEVICE_ALI) {
2359 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2360 return err;
2361 iagetword(chip, 0); /* clear semaphore flag */
2362 } else {
2363 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2364 return err;
2365 }
2366
2367 /* disable interrupts */
2368 for (i = 0; i < chip->bdbars_count; i++)
2369 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2370 /* reset channels */
2371 for (i = 0; i < chip->bdbars_count; i++)
2372 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
253b999f
JK		 2373 for (i = 0; i < chip->bdbars_count; i++) {
2374 timeout = 100000;
2375 while (--timeout != 0) {
2376 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
2377 break;
2378 }
2379 if (timeout == 0)
2380 printk(KERN_ERR "intel8x0: reset of registers failed?\n");
2381 }
1da177e4
LT		 2382 /* initialize Buffer Descriptor Lists */
2383 for (i = 0; i < chip->bdbars_count; i++)
6b75a9d8
TI		 2384 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2385 chip->ichd[i].bdbar_addr);
1da177e4
LT		 2386 return 0;
2387}
2388
6b75a9d8 2389static int snd_intel8x0_free(struct intel8x0 *chip)
1da177e4
LT		 2390{
2391 unsigned int i;
2392
2393 if (chip->irq < 0)
2394 goto __hw_end;
2395 /* disable interrupts */
2396 for (i = 0; i < chip->bdbars_count; i++)
2397 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2398 /* reset channels */
2399 for (i = 0; i < chip->bdbars_count; i++)
2400 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2401 if (chip->device_type == DEVICE_NFORCE) {
2402 /* stop the spdif interrupt */
2403 unsigned int val;
2404 pci_read_config_dword(chip->pci, 0x4c, &val);
2405 val &= ~0x1000000;
2406 pci_write_config_dword(chip->pci, 0x4c, val);
2407 }
2408 /* --- */
2409 synchronize_irq(chip->irq);
2410 __hw_end:
2411 if (chip->irq >= 0)
6b75a9d8 2412 free_irq(chip->irq, chip);
1da177e4
LT		 2413 if (chip->bdbars.area) {
2414 if (chip->fix_nocache)
2415 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2416 snd_dma_free_pages(&chip->bdbars);
2417 }
3388c37e
TI		 2418 if (chip->addr)
2419 pci_iounmap(chip->pci, chip->addr);
2420 if (chip->bmaddr)
2421 pci_iounmap(chip->pci, chip->bmaddr);
1da177e4
LT		 2422 pci_release_regions(chip->pci);
2423 pci_disable_device(chip->pci);
2424 kfree(chip);
2425 return 0;
2426}
2427
2428#ifdef CONFIG_PM
2429/*
2430 * power management
2431 */
5809c6c4 2432static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2433{
5809c6c4
TI		 2434 struct snd_card *card = pci_get_drvdata(pci);
2435 struct intel8x0 *chip = card->private_data;
1da177e4
LT		 2436 int i;
2437
5809c6c4 2438 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1da177e4
LT		 2439 for (i = 0; i < chip->pcm_devs; i++)
2440 snd_pcm_suspend_all(chip->pcm[i]);
2441 /* clear nocache */
2442 if (chip->fix_nocache) {
2443 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2444 struct ichdev *ichdev = &chip->ichd[i];
1da177e4 2445 if (ichdev->substream && ichdev->page_attr_changed) {
6b75a9d8 2446 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
1da177e4
LT		 2447 if (runtime->dma_area)
2448 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2449 }
2450 }
2451 }
84a43bd5 2452 for (i = 0; i < chip->ncodecs; i++)
5809c6c4 2453 snd_ac97_suspend(chip->ac97[i]);
52b72388
TI		 2454 if (chip->device_type == DEVICE_INTEL_ICH4)
2455 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
adbedd34 2456
30b35399
TI		 2457 if (chip->irq >= 0) {
2458 synchronize_irq(chip->irq);
6b75a9d8 2459 free_irq(chip->irq, chip);
30b35399
TI		 2460 chip->irq = -1;
2461 }
5809c6c4
TI		 2462 pci_disable_device(pci);
2463 pci_save_state(pci);
30b35399 2464 pci_set_power_state(pci, pci_choose_state(pci, state));
1da177e4
LT		 2465 return 0;
2466}
2467
5809c6c4 2468static int intel8x0_resume(struct pci_dev *pci)
1da177e4 2469{
5809c6c4
TI		 2470 struct snd_card *card = pci_get_drvdata(pci);
2471 struct intel8x0 *chip = card->private_data;
1da177e4
LT		 2472 int i;
2473
30b35399 2474 pci_set_power_state(pci, PCI_D0);
5809c6c4 2475 pci_restore_state(pci);
30b35399
TI		 2476 if (pci_enable_device(pci) < 0) {
2477 printk(KERN_ERR "intel8x0: pci_enable_device failed, "
2478 "disabling device\n");
2479 snd_card_disconnect(card);
2480 return -EIO;
2481 }
5809c6c4 2482 pci_set_master(pci);
30b35399 2483 if (request_irq(pci->irq, snd_intel8x0_interrupt,
437a5a46 2484 IRQF_SHARED, card->shortname, chip)) {
30b35399
TI		 2485 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
2486 "disabling device\n", pci->irq);
2487 snd_card_disconnect(card);
2488 return -EIO;
2489 }
5809c6c4 2490 chip->irq = pci->irq;
90158b83 2491 synchronize_irq(chip->irq);
6dbe6628 2492 snd_intel8x0_chip_init(chip, 0);
1da177e4 2493
52b72388
TI		 2494 /* re-initialize mixer stuff */
2495 if (chip->device_type == DEVICE_INTEL_ICH4) {
2496 /* enable separate SDINs for ICH4 */
2497 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2498 /* use slot 10/11 for SPDIF */
2499 iputdword(chip, ICHREG(GLOB_CNT),
2500 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2501 ICH_PCM_SPDIF_1011);
2502 }
2503
1da177e4
LT		 2504 /* refill nocache */
2505 if (chip->fix_nocache)
2506 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2507
84a43bd5 2508 for (i = 0; i < chip->ncodecs; i++)
5809c6c4 2509 snd_ac97_resume(chip->ac97[i]);
1da177e4
LT		 2510
2511 /* refill nocache */
2512 if (chip->fix_nocache) {
2513 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2514 struct ichdev *ichdev = &chip->ichd[i];
1da177e4 2515 if (ichdev->substream && ichdev->page_attr_changed) {
6b75a9d8 2516 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
1da177e4
LT		 2517 if (runtime->dma_area)
2518 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2519 }
2520 }
2521 }
2522
1cfe43d2
TI		 2523 /* resume status */
2524 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2525 struct ichdev *ichdev = &chip->ichd[i];
1cfe43d2
TI		 2526 unsigned long port = ichdev->reg_offset;
2527 if (! ichdev->substream || ! ichdev->suspended)
2528 continue;
2529 if (ichdev->ichd == ICHD_PCMOUT)
2530 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2531 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2532 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2533 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2534 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2535 }
2536
5809c6c4 2537 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2538 return 0;
2539}
2540#endif /* CONFIG_PM */
2541
2542#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2543
6b75a9d8 2544static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
1da177e4 2545{
6b75a9d8
TI		 2546 struct snd_pcm_substream *subs;
2547 struct ichdev *ichdev;
1da177e4
LT		 2548 unsigned long port;
2549 unsigned long pos, t;
2550 struct timeval start_time, stop_time;
2551
2552 if (chip->ac97_bus->clock != 48000)
2553 return; /* specified in module option */
2554
2555 subs = chip->pcm[0]->streams[0].substream;
2556 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
99b359ba 2557 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
1da177e4
LT		 2558 return;
2559 }
2560 ichdev = &chip->ichd[ICHD_PCMOUT];
2561 ichdev->physbuf = subs->dma_buffer.addr;
2562 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2563 ichdev->substream = NULL; /* don't process interrupts */
2564
2565 /* set rate */
2566 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2567 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2568 return;
2569 }
2570 snd_intel8x0_setup_periods(chip, ichdev);
2571 port = ichdev->reg_offset;
2572 spin_lock_irq(&chip->reg_lock);
2573 chip->in_measurement = 1;
2574 /* trigger */
2575 if (chip->device_type != DEVICE_ALI)
2576 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2577 else {
2578 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2579 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2580 }
2581 do_gettimeofday(&start_time);
2582 spin_unlock_irq(&chip->reg_lock);
ef21ca24 2583 msleep(50);
1da177e4
LT		 2584 spin_lock_irq(&chip->reg_lock);
2585 /* check the position */
2586 pos = ichdev->fragsize1;
2587 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2588 pos += ichdev->position;
2589 chip->in_measurement = 0;
2590 do_gettimeofday(&stop_time);
2591 /* stop */
2592 if (chip->device_type == DEVICE_ALI) {
d78bec21 2593 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
1da177e4
LT		 2594 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2595 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2596 ;
2597 } else {
2598 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2599 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2600 ;
2601 }
2602 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2603 spin_unlock_irq(&chip->reg_lock);
2604
2605 t = stop_time.tv_sec - start_time.tv_sec;
2606 t *= 1000000;
2607 t += stop_time.tv_usec - start_time.tv_usec;
2608 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2609 if (t == 0) {
2610 snd_printk(KERN_ERR "?? calculation error..\n");
2611 return;
2612 }
2613 pos = (pos / 4) * 1000;
2614 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2615 if (pos < 40000 || pos >= 60000)
2616 /* abnormal value. hw problem? */
2617 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2618 else if (pos < 47500 || pos > 48500)
2619 /* not 48000Hz, tuning the clock.. */
2620 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2621 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
6dbe6628 2622 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
1da177e4
LT		 2623}
2624
adf1b3d2 2625#ifdef CONFIG_PROC_FS
6b75a9d8
TI		 2626static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2627 struct snd_info_buffer *buffer)
1da177e4 2628{
6b75a9d8 2629 struct intel8x0 *chip = entry->private_data;
1da177e4
LT		 2630 unsigned int tmp;
2631
2632 snd_iprintf(buffer, "Intel8x0\n\n");
2633 if (chip->device_type == DEVICE_ALI)
2634 return;
2635 tmp = igetdword(chip, ICHREG(GLOB_STA));
2636 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2637 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2638 if (chip->device_type == DEVICE_INTEL_ICH4)
2639 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
84a43bd5
TI		 2640 snd_iprintf(buffer, "AC'97 codecs ready :");
2641 if (tmp & chip->codec_isr_bits) {
2642 int i;
2643 static const char *codecs[3] = {
2644 "primary", "secondary", "tertiary"
2645 };
2646 for (i = 0; i < chip->max_codecs; i++)
2647 if (tmp & chip->codec_bit[i])
2648 snd_iprintf(buffer, " %s", codecs[i]);
2649 } else
2650 snd_iprintf(buffer, " none");
2651 snd_iprintf(buffer, "\n");
2652 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2653 chip->device_type == DEVICE_SIS)
1da177e4
LT		 2654 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2655 chip->ac97_sdin[0],
2656 chip->ac97_sdin[1],
2657 chip->ac97_sdin[2]);
2658}
2659
6b75a9d8 2660static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
1da177e4 2661{
6b75a9d8 2662 struct snd_info_entry *entry;
1da177e4
LT		 2663
2664 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
bf850204 2665 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
1da177e4 2666}
adf1b3d2
TI		 2667#else
2668#define snd_intel8x0_proc_init(x)
2669#endif
1da177e4 2670
6b75a9d8 2671static int snd_intel8x0_dev_free(struct snd_device *device)
1da177e4 2672{
6b75a9d8 2673 struct intel8x0 *chip = device->device_data;
1da177e4
LT		 2674 return snd_intel8x0_free(chip);
2675}
2676
2677struct ich_reg_info {
2678 unsigned int int_sta_mask;
2679 unsigned int offset;
2680};
2681
84a43bd5
TI		 2682static unsigned int ich_codec_bits[3] = {
2683 ICH_PCR, ICH_SCR, ICH_TCR
2684};
2685static unsigned int sis_codec_bits[3] = {
2686 ICH_PCR, ICH_SCR, ICH_SIS_TCR
2687};
2688
6b75a9d8 2689static int __devinit snd_intel8x0_create(struct snd_card *card,
1da177e4
LT		 2690 struct pci_dev *pci,
2691 unsigned long device_type,
6b75a9d8 2692 struct intel8x0 ** r_intel8x0)
1da177e4 2693{
6b75a9d8 2694 struct intel8x0 *chip;
1da177e4
LT		 2695 int err;
2696 unsigned int i;
2697 unsigned int int_sta_masks;
6b75a9d8
TI		 2698 struct ichdev *ichdev;
2699 static struct snd_device_ops ops = {
1da177e4
LT		 2700 .dev_free = snd_intel8x0_dev_free,
2701 };
2702
2703 static unsigned int bdbars[] = {
2704 3, /* DEVICE_INTEL */
2705 6, /* DEVICE_INTEL_ICH4 */
2706 3, /* DEVICE_SIS */
2707 6, /* DEVICE_ALI */
2708 4, /* DEVICE_NFORCE */
2709 };
2710 static struct ich_reg_info intel_regs[6] = {
2711 { ICH_PIINT, 0 },
2712 { ICH_POINT, 0x10 },
2713 { ICH_MCINT, 0x20 },
2714 { ICH_M2INT, 0x40 },
2715 { ICH_P2INT, 0x50 },
2716 { ICH_SPINT, 0x60 },
2717 };
2718 static struct ich_reg_info nforce_regs[4] = {
2719 { ICH_PIINT, 0 },
2720 { ICH_POINT, 0x10 },
2721 { ICH_MCINT, 0x20 },
2722 { ICH_NVSPINT, 0x70 },
2723 };
2724 static struct ich_reg_info ali_regs[6] = {
2725 { ALI_INT_PCMIN, 0x40 },
2726 { ALI_INT_PCMOUT, 0x50 },
2727 { ALI_INT_MICIN, 0x60 },
2728 { ALI_INT_CODECSPDIFOUT, 0x70 },
2729 { ALI_INT_SPDIFIN, 0xa0 },
2730 { ALI_INT_SPDIFOUT, 0xb0 },
2731 };
2732 struct ich_reg_info *tbl;
2733
2734 *r_intel8x0 = NULL;
2735
2736 if ((err = pci_enable_device(pci)) < 0)
2737 return err;
2738
e560d8d8 2739 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 2740 if (chip == NULL) {
2741 pci_disable_device(pci);
2742 return -ENOMEM;
2743 }
2744 spin_lock_init(&chip->reg_lock);
2745 chip->device_type = device_type;
2746 chip->card = card;
2747 chip->pci = pci;
2748 chip->irq = -1;
c829b052
TI		 2749
2750 /* module parameters */
2751 chip->buggy_irq = buggy_irq;
2752 chip->buggy_semaphore = buggy_semaphore;
2753 if (xbox)
2754 chip->xbox = 1;
1da177e4
LT		 2755
2756 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2757 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2758 chip->fix_nocache = 1; /* enable workaround */
2759
1da177e4
LT		 2760 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2761 kfree(chip);
2762 pci_disable_device(pci);
2763 return err;
2764 }
2765
2766 if (device_type == DEVICE_ALI) {
2767 /* ALI5455 has no ac97 region */
3388c37e 2768 chip->bmaddr = pci_iomap(pci, 0, 0);
1da177e4
LT		 2769 goto port_inited;
2770 }
2771
3388c37e
TI		 2772 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
2773 chip->addr = pci_iomap(pci, 2, 0);
2774 else
2775 chip->addr = pci_iomap(pci, 0, 0);
2776 if (!chip->addr) {
2777 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
2778 snd_intel8x0_free(chip);
2779 return -EIO;
2780 }
2781 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
2782 chip->bmaddr = pci_iomap(pci, 3, 0);
2783 else
2784 chip->bmaddr = pci_iomap(pci, 1, 0);
2785 if (!chip->bmaddr) {
2786 snd_printk(KERN_ERR "Controller space ioremap problem\n");
2787 snd_intel8x0_free(chip);
2788 return -EIO;
1da177e4
LT		 2789 }
2790
2791 port_inited:
1da177e4
LT		 2792 chip->bdbars_count = bdbars[device_type];
2793
2794 /* initialize offsets */
2795 switch (device_type) {
2796 case DEVICE_NFORCE:
2797 tbl = nforce_regs;
2798 break;
2799 case DEVICE_ALI:
2800 tbl = ali_regs;
2801 break;
2802 default:
2803 tbl = intel_regs;
2804 break;
2805 }
2806 for (i = 0; i < chip->bdbars_count; i++) {
2807 ichdev = &chip->ichd[i];
2808 ichdev->ichd = i;
2809 ichdev->reg_offset = tbl[i].offset;
2810 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2811 if (device_type == DEVICE_SIS) {
2812 /* SiS 7012 swaps the registers */
2813 ichdev->roff_sr = ICH_REG_OFF_PICB;
2814 ichdev->roff_picb = ICH_REG_OFF_SR;
2815 } else {
2816 ichdev->roff_sr = ICH_REG_OFF_SR;
2817 ichdev->roff_picb = ICH_REG_OFF_PICB;
2818 }
2819 if (device_type == DEVICE_ALI)
2820 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2821 /* SIS7012 handles the pcm data in bytes, others are in samples */
2822 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2823 }
2824
2825 /* allocate buffer descriptor lists */
2826 /* the start of each lists must be aligned to 8 bytes */
2827 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2828 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2829 &chip->bdbars) < 0) {
2830 snd_intel8x0_free(chip);
2831 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2832 return -ENOMEM;
2833 }
2834 /* tables must be aligned to 8 bytes here, but the kernel pages
2835 are much bigger, so we don't care (on i386) */
2836 /* workaround for 440MX */
2837 if (chip->fix_nocache)
2838 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2839 int_sta_masks = 0;
2840 for (i = 0; i < chip->bdbars_count; i++) {
2841 ichdev = &chip->ichd[i];
beef08a5
TI		 2842 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2843 (i * ICH_MAX_FRAGS * 2);
2844 ichdev->bdbar_addr = chip->bdbars.addr +
2845 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1da177e4
LT		 2846 int_sta_masks |= ichdev->int_sta_mask;
2847 }
beef08a5
TI		 2848 chip->int_sta_reg = device_type == DEVICE_ALI ?
2849 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
1da177e4
LT		 2850 chip->int_sta_mask = int_sta_masks;
2851
beef08a5
TI		 2852 /* request irq after initializaing int_sta_mask, etc */
2853 if (request_irq(pci->irq, snd_intel8x0_interrupt,
437a5a46 2854 IRQF_SHARED, card->shortname, chip)) {
beef08a5
TI		 2855 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2856 snd_intel8x0_free(chip);
2857 return -EBUSY;
2858 }
2859 chip->irq = pci->irq;
2860 pci_set_master(pci);
2861 synchronize_irq(chip->irq);
2862
84a43bd5
TI		 2863 switch(chip->device_type) {
2864 case DEVICE_INTEL_ICH4:
2865 /* ICH4 can have three codecs */
2866 chip->max_codecs = 3;
2867 chip->codec_bit = ich_codec_bits;
2868 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
2869 break;
2870 case DEVICE_SIS:
2871 /* recent SIS7012 can have three codecs */
2872 chip->max_codecs = 3;
2873 chip->codec_bit = sis_codec_bits;
2874 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
2875 break;
2876 default:
2877 /* others up to two codecs */
2878 chip->max_codecs = 2;
2879 chip->codec_bit = ich_codec_bits;
2880 chip->codec_ready_bits = ICH_PRI | ICH_SRI;
2881 break;
2882 }
2883 for (i = 0; i < chip->max_codecs; i++)
2884 chip->codec_isr_bits |= chip->codec_bit[i];
2885
1da177e4
LT		 2886 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2887 snd_intel8x0_free(chip);
2888 return err;
2889 }
2890
1da177e4
LT		 2891 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2892 snd_intel8x0_free(chip);
2893 return err;
2894 }
2895
2896 snd_card_set_dev(card, &pci->dev);
2897
2898 *r_intel8x0 = chip;
2899 return 0;
2900}
2901
2902static struct shortname_table {
2903 unsigned int id;
2904 const char *s;
2905} shortnames[] __devinitdata = {
8cdfd251
TI		 2906 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
2907 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
2908 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
1da177e4 2909 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
8cdfd251
TI		 2910 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
2911 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
2912 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
1da177e4
LT		 2913 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2914 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2915 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3437c5df 2916 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
1da177e4 2917 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
8cdfd251 2918 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
1da177e4
LT		 2919 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2920 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2921 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2922 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2923 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2924 { 0x003a, "NVidia MCP04" },
2925 { 0x746d, "AMD AMD8111" },
2926 { 0x7445, "AMD AMD768" },
2927 { 0x5455, "ALi M5455" },
2928 { 0, NULL },
2929};
2930
2931static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2932 const struct pci_device_id *pci_id)
2933{
6b75a9d8
TI		 2934 struct snd_card *card;
2935 struct intel8x0 *chip;
1da177e4
LT		 2936 int err;
2937 struct shortname_table *name;
2938
b7fe4622 2939 card = snd_card_new(index, id, THIS_MODULE, 0);
1da177e4
LT		 2940 if (card == NULL)
2941 return -ENOMEM;
2942
2943 switch (pci_id->driver_data) {
2944 case DEVICE_NFORCE:
2945 strcpy(card->driver, "NFORCE");
2946 break;
2947 case DEVICE_INTEL_ICH4:
2948 strcpy(card->driver, "ICH4");
2949 break;
2950 default:
2951 strcpy(card->driver, "ICH");
2952 break;
2953 }
2954
2955 strcpy(card->shortname, "Intel ICH");
2956 for (name = shortnames; name->id; name++) {
2957 if (pci->device == name->id) {
2958 strcpy(card->shortname, name->s);
2959 break;
2960 }
2961 }
2962
beef08a5
TI		 2963 if (buggy_irq < 0) {
2964 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2965 * Needs to return IRQ_HANDLED for unknown irqs.
2966 */
2967 if (pci_id->driver_data == DEVICE_NFORCE)
2968 buggy_irq = 1;
2969 else
2970 buggy_irq = 0;
2971 }
2972
a06147d2 2973 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
c829b052 2974 &chip)) < 0) {
1da177e4
LT		 2975 snd_card_free(card);
2976 return err;
2977 }
5809c6c4 2978 card->private_data = chip;
1da177e4 2979
b7fe4622 2980 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
1da177e4
LT		 2981 snd_card_free(card);
2982 return err;
2983 }
2984 if ((err = snd_intel8x0_pcm(chip)) < 0) {
2985 snd_card_free(card);
2986 return err;
2987 }
2988
2989 snd_intel8x0_proc_init(chip);
2990
2991 snprintf(card->longname, sizeof(card->longname),
3388c37e
TI		 2992 "%s with %s at irq %i", card->shortname,
2993 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
1da177e4 2994
b7fe4622 2995 if (! ac97_clock)
1da177e4
LT		 2996 intel8x0_measure_ac97_clock(chip);
2997
2998 if ((err = snd_card_register(card)) < 0) {
2999 snd_card_free(card);
3000 return err;
3001 }
3002 pci_set_drvdata(pci, card);
1da177e4
LT		 3003 return 0;
3004}
3005
3006static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3007{
3008 snd_card_free(pci_get_drvdata(pci));
3009 pci_set_drvdata(pci, NULL);
3010}
3011
3012static struct pci_driver driver = {
3013 .name = "Intel ICH",
3014 .id_table = snd_intel8x0_ids,
3015 .probe = snd_intel8x0_probe,
3016 .remove = __devexit_p(snd_intel8x0_remove),
5809c6c4
TI		 3017#ifdef CONFIG_PM
3018 .suspend = intel8x0_suspend,
3019 .resume = intel8x0_resume,
3020#endif
1da177e4
LT		 3021};
3022
3023
3024static int __init alsa_card_intel8x0_init(void)
3025{
01d25d46 3026 return pci_register_driver(&driver);
1da177e4
LT		 3027}
3028
3029static void __exit alsa_card_intel8x0_exit(void)
3030{
3031 pci_unregister_driver(&driver);
3032}
3033
3034module_init(alsa_card_intel8x0_init)
3035module_exit(alsa_card_intel8x0_exit)
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