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1da177e4 LT |
1 | /* |
2 | * ALSA modem driver for Intel ICH (i8x0) chipsets | |
3 | * | |
4 | * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz> | |
5 | * | |
f01cc521 | 6 | * This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version |
1da177e4 LT |
7 | * of ALSA ICH sound driver intel8x0.c . |
8 | * | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | */ | |
25 | ||
26 | #include <sound/driver.h> | |
27 | #include <asm/io.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/pci.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/moduleparam.h> | |
34 | #include <sound/core.h> | |
35 | #include <sound/pcm.h> | |
36 | #include <sound/ac97_codec.h> | |
37 | #include <sound/info.h> | |
1da177e4 LT |
38 | #include <sound/initval.h> |
39 | ||
40 | MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>"); | |
6b75a9d8 TI |
41 | MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; " |
42 | "SiS 7013; NVidia MCP/2/2S/3 modems"); | |
1da177e4 LT |
43 | MODULE_LICENSE("GPL"); |
44 | MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," | |
45 | "{Intel,82901AB-ICH0}," | |
46 | "{Intel,82801BA-ICH2}," | |
47 | "{Intel,82801CA-ICH3}," | |
48 | "{Intel,82801DB-ICH4}," | |
49 | "{Intel,ICH5}," | |
50 | "{Intel,ICH6}," | |
51 | "{Intel,ICH7}," | |
52 | "{Intel,MX440}," | |
53 | "{SiS,7013}," | |
54 | "{NVidia,NForce Modem}," | |
55 | "{NVidia,NForce2 Modem}," | |
56 | "{NVidia,NForce2s Modem}," | |
57 | "{NVidia,NForce3 Modem}," | |
58 | "{AMD,AMD768}}"); | |
59 | ||
b7fe4622 CL |
60 | static int index = -2; /* Exclude the first card */ |
61 | static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ | |
62 | static int ac97_clock = 0; | |
1da177e4 | 63 | |
b7fe4622 | 64 | module_param(index, int, 0444); |
1da177e4 | 65 | MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard."); |
b7fe4622 | 66 | module_param(id, charp, 0444); |
1da177e4 | 67 | MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard."); |
b7fe4622 | 68 | module_param(ac97_clock, int, 0444); |
1da177e4 LT |
69 | MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect)."); |
70 | ||
2b3e584b TI |
71 | /* just for backward compatibility */ |
72 | static int enable; | |
698444f3 | 73 | module_param(enable, bool, 0444); |
2b3e584b | 74 | |
1da177e4 LT |
75 | /* |
76 | * Direct registers | |
77 | */ | |
1da177e4 LT |
78 | enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; |
79 | ||
80 | #define ICHREG(x) ICH_REG_##x | |
81 | ||
82 | #define DEFINE_REGSET(name,base) \ | |
83 | enum { \ | |
84 | ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ | |
85 | ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ | |
86 | ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ | |
87 | ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ | |
88 | ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ | |
89 | ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ | |
90 | ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ | |
91 | }; | |
92 | ||
93 | /* busmaster blocks */ | |
94 | DEFINE_REGSET(OFF, 0); /* offset */ | |
95 | ||
96 | /* values for each busmaster block */ | |
97 | ||
98 | /* LVI */ | |
99 | #define ICH_REG_LVI_MASK 0x1f | |
100 | ||
101 | /* SR */ | |
102 | #define ICH_FIFOE 0x10 /* FIFO error */ | |
103 | #define ICH_BCIS 0x08 /* buffer completion interrupt status */ | |
104 | #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ | |
105 | #define ICH_CELV 0x02 /* current equals last valid */ | |
106 | #define ICH_DCH 0x01 /* DMA controller halted */ | |
107 | ||
108 | /* PIV */ | |
109 | #define ICH_REG_PIV_MASK 0x1f /* mask */ | |
110 | ||
111 | /* CR */ | |
112 | #define ICH_IOCE 0x10 /* interrupt on completion enable */ | |
113 | #define ICH_FEIE 0x08 /* fifo error interrupt enable */ | |
114 | #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ | |
115 | #define ICH_RESETREGS 0x02 /* reset busmaster registers */ | |
116 | #define ICH_STARTBM 0x01 /* start busmaster operation */ | |
117 | ||
118 | ||
119 | /* global block */ | |
120 | #define ICH_REG_GLOB_CNT 0x3c /* dword - global control */ | |
121 | #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ | |
122 | #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ | |
123 | #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ | |
124 | #define ICH_ACLINK 0x00000008 /* AClink shut off */ | |
125 | #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ | |
126 | #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ | |
127 | #define ICH_GIE 0x00000001 /* GPI interrupt enable */ | |
128 | #define ICH_REG_GLOB_STA 0x40 /* dword - global status */ | |
129 | #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ | |
130 | #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ | |
131 | #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ | |
132 | #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ | |
133 | #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ | |
134 | #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ | |
135 | #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ | |
136 | #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ | |
137 | #define ICH_MD3 0x00020000 /* modem power down semaphore */ | |
138 | #define ICH_AD3 0x00010000 /* audio power down semaphore */ | |
139 | #define ICH_RCS 0x00008000 /* read completion status */ | |
140 | #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ | |
141 | #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ | |
142 | #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ | |
143 | #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ | |
144 | #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ | |
145 | #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ | |
146 | #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ | |
147 | #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ | |
148 | #define ICH_POINT 0x00000040 /* playback interrupt */ | |
149 | #define ICH_PIINT 0x00000020 /* capture interrupt */ | |
150 | #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ | |
151 | #define ICH_MOINT 0x00000004 /* modem playback interrupt */ | |
152 | #define ICH_MIINT 0x00000002 /* modem capture interrupt */ | |
153 | #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ | |
154 | #define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */ | |
155 | #define ICH_CAS 0x01 /* codec access semaphore */ | |
156 | ||
157 | #define ICH_MAX_FRAGS 32 /* max hw frags */ | |
158 | ||
159 | ||
160 | /* | |
161 | * | |
162 | */ | |
163 | ||
164 | enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT }; | |
165 | enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT }; | |
166 | ||
6b75a9d8 | 167 | #define get_ichdev(substream) (substream->runtime->private_data) |
1da177e4 | 168 | |
6b75a9d8 | 169 | struct ichdev { |
1da177e4 LT |
170 | unsigned int ichd; /* ich device number */ |
171 | unsigned long reg_offset; /* offset to bmaddr */ | |
172 | u32 *bdbar; /* CPU address (32bit) */ | |
173 | unsigned int bdbar_addr; /* PCI bus address (32bit) */ | |
6b75a9d8 | 174 | struct snd_pcm_substream *substream; |
1da177e4 LT |
175 | unsigned int physbuf; /* physical address (32bit) */ |
176 | unsigned int size; | |
177 | unsigned int fragsize; | |
178 | unsigned int fragsize1; | |
179 | unsigned int position; | |
180 | int frags; | |
181 | int lvi; | |
182 | int lvi_frag; | |
183 | int civ; | |
184 | int ack; | |
185 | int ack_reload; | |
186 | unsigned int ack_bit; | |
187 | unsigned int roff_sr; | |
188 | unsigned int roff_picb; | |
189 | unsigned int int_sta_mask; /* interrupt status mask */ | |
190 | unsigned int ali_slot; /* ALI DMA slot */ | |
6b75a9d8 TI |
191 | struct snd_ac97 *ac97; |
192 | }; | |
1da177e4 | 193 | |
6b75a9d8 | 194 | struct intel8x0m { |
1da177e4 LT |
195 | unsigned int device_type; |
196 | ||
197 | int irq; | |
198 | ||
199 | unsigned int mmio; | |
200 | unsigned long addr; | |
201 | void __iomem *remap_addr; | |
202 | unsigned int bm_mmio; | |
203 | unsigned long bmaddr; | |
204 | void __iomem *remap_bmaddr; | |
205 | ||
206 | struct pci_dev *pci; | |
6b75a9d8 | 207 | struct snd_card *card; |
1da177e4 LT |
208 | |
209 | int pcm_devs; | |
6b75a9d8 TI |
210 | struct snd_pcm *pcm[2]; |
211 | struct ichdev ichd[2]; | |
1da177e4 LT |
212 | |
213 | unsigned int in_ac97_init: 1; | |
214 | ||
6b75a9d8 TI |
215 | struct snd_ac97_bus *ac97_bus; |
216 | struct snd_ac97 *ac97; | |
1da177e4 LT |
217 | |
218 | spinlock_t reg_lock; | |
219 | ||
220 | struct snd_dma_buffer bdbars; | |
221 | u32 bdbars_count; | |
222 | u32 int_sta_reg; /* interrupt status register */ | |
223 | u32 int_sta_mask; /* interrupt status mask */ | |
224 | unsigned int pcm_pos_shift; | |
225 | }; | |
226 | ||
227 | static struct pci_device_id snd_intel8x0m_ids[] = { | |
228 | { 0x8086, 0x2416, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */ | |
229 | { 0x8086, 0x2426, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */ | |
230 | { 0x8086, 0x2446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */ | |
231 | { 0x8086, 0x2486, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */ | |
232 | { 0x8086, 0x24c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH4 */ | |
233 | { 0x8086, 0x24d6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH5 */ | |
234 | { 0x8086, 0x266d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH6 */ | |
235 | { 0x8086, 0x27dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH7 */ | |
236 | { 0x8086, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */ | |
237 | { 0x1022, 0x7446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */ | |
238 | { 0x1039, 0x7013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7013 */ | |
239 | { 0x10de, 0x01c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */ | |
240 | { 0x10de, 0x0069, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */ | |
241 | { 0x10de, 0x0089, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2s */ | |
242 | { 0x10de, 0x00d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */ | |
243 | #if 0 | |
244 | { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */ | |
245 | { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */ | |
246 | #endif | |
247 | { 0, } | |
248 | }; | |
1da177e4 LT |
249 | |
250 | MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids); | |
251 | ||
1da177e4 LT |
252 | /* |
253 | * Lowlevel I/O - busmaster | |
254 | */ | |
255 | ||
6b75a9d8 | 256 | static u8 igetbyte(struct intel8x0m *chip, u32 offset) |
1da177e4 LT |
257 | { |
258 | if (chip->bm_mmio) | |
259 | return readb(chip->remap_bmaddr + offset); | |
260 | else | |
261 | return inb(chip->bmaddr + offset); | |
262 | } | |
263 | ||
6b75a9d8 | 264 | static u16 igetword(struct intel8x0m *chip, u32 offset) |
1da177e4 LT |
265 | { |
266 | if (chip->bm_mmio) | |
267 | return readw(chip->remap_bmaddr + offset); | |
268 | else | |
269 | return inw(chip->bmaddr + offset); | |
270 | } | |
271 | ||
6b75a9d8 | 272 | static u32 igetdword(struct intel8x0m *chip, u32 offset) |
1da177e4 LT |
273 | { |
274 | if (chip->bm_mmio) | |
275 | return readl(chip->remap_bmaddr + offset); | |
276 | else | |
277 | return inl(chip->bmaddr + offset); | |
278 | } | |
279 | ||
6b75a9d8 | 280 | static void iputbyte(struct intel8x0m *chip, u32 offset, u8 val) |
1da177e4 LT |
281 | { |
282 | if (chip->bm_mmio) | |
283 | writeb(val, chip->remap_bmaddr + offset); | |
284 | else | |
285 | outb(val, chip->bmaddr + offset); | |
286 | } | |
287 | ||
6b75a9d8 | 288 | static void iputword(struct intel8x0m *chip, u32 offset, u16 val) |
1da177e4 LT |
289 | { |
290 | if (chip->bm_mmio) | |
291 | writew(val, chip->remap_bmaddr + offset); | |
292 | else | |
293 | outw(val, chip->bmaddr + offset); | |
294 | } | |
295 | ||
6b75a9d8 | 296 | static void iputdword(struct intel8x0m *chip, u32 offset, u32 val) |
1da177e4 LT |
297 | { |
298 | if (chip->bm_mmio) | |
299 | writel(val, chip->remap_bmaddr + offset); | |
300 | else | |
301 | outl(val, chip->bmaddr + offset); | |
302 | } | |
303 | ||
304 | /* | |
305 | * Lowlevel I/O - AC'97 registers | |
306 | */ | |
307 | ||
6b75a9d8 | 308 | static u16 iagetword(struct intel8x0m *chip, u32 offset) |
1da177e4 LT |
309 | { |
310 | if (chip->mmio) | |
311 | return readw(chip->remap_addr + offset); | |
312 | else | |
313 | return inw(chip->addr + offset); | |
314 | } | |
315 | ||
6b75a9d8 | 316 | static void iaputword(struct intel8x0m *chip, u32 offset, u16 val) |
1da177e4 LT |
317 | { |
318 | if (chip->mmio) | |
319 | writew(val, chip->remap_addr + offset); | |
320 | else | |
321 | outw(val, chip->addr + offset); | |
322 | } | |
323 | ||
324 | /* | |
325 | * Basic I/O | |
326 | */ | |
327 | ||
328 | /* | |
329 | * access to AC97 codec via normal i/o (for ICH and SIS7013) | |
330 | */ | |
331 | ||
332 | /* return the GLOB_STA bit for the corresponding codec */ | |
6b75a9d8 | 333 | static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec) |
1da177e4 LT |
334 | { |
335 | static unsigned int codec_bit[3] = { | |
336 | ICH_PCR, ICH_SCR, ICH_TCR | |
337 | }; | |
338 | snd_assert(codec < 3, return ICH_PCR); | |
339 | return codec_bit[codec]; | |
340 | } | |
341 | ||
6b75a9d8 | 342 | static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec) |
1da177e4 LT |
343 | { |
344 | int time; | |
345 | ||
346 | if (codec > 1) | |
347 | return -EIO; | |
348 | codec = get_ich_codec_bit(chip, codec); | |
349 | ||
350 | /* codec ready ? */ | |
351 | if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) | |
352 | return -EIO; | |
353 | ||
354 | /* Anyone holding a semaphore for 1 msec should be shot... */ | |
355 | time = 100; | |
356 | do { | |
357 | if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) | |
358 | return 0; | |
359 | udelay(10); | |
360 | } while (time--); | |
361 | ||
362 | /* access to some forbidden (non existant) ac97 registers will not | |
363 | * reset the semaphore. So even if you don't get the semaphore, still | |
364 | * continue the access. We don't need the semaphore anyway. */ | |
99b359ba | 365 | snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", |
1da177e4 LT |
366 | igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); |
367 | iagetword(chip, 0); /* clear semaphore flag */ | |
368 | /* I don't care about the semaphore */ | |
369 | return -EBUSY; | |
370 | } | |
371 | ||
6b75a9d8 | 372 | static void snd_intel8x0_codec_write(struct snd_ac97 *ac97, |
1da177e4 LT |
373 | unsigned short reg, |
374 | unsigned short val) | |
375 | { | |
6b75a9d8 | 376 | struct intel8x0m *chip = ac97->private_data; |
1da177e4 LT |
377 | |
378 | if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { | |
379 | if (! chip->in_ac97_init) | |
99b359ba | 380 | snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); |
1da177e4 LT |
381 | } |
382 | iaputword(chip, reg + ac97->num * 0x80, val); | |
383 | } | |
384 | ||
6b75a9d8 | 385 | static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97, |
1da177e4 LT |
386 | unsigned short reg) |
387 | { | |
6b75a9d8 | 388 | struct intel8x0m *chip = ac97->private_data; |
1da177e4 LT |
389 | unsigned short res; |
390 | unsigned int tmp; | |
391 | ||
392 | if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { | |
393 | if (! chip->in_ac97_init) | |
99b359ba | 394 | snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); |
1da177e4 LT |
395 | res = 0xffff; |
396 | } else { | |
397 | res = iagetword(chip, reg + ac97->num * 0x80); | |
398 | if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { | |
399 | /* reset RCS and preserve other R/WC bits */ | |
6b75a9d8 TI |
400 | iputdword(chip, ICHREG(GLOB_STA), |
401 | tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI)); | |
1da177e4 | 402 | if (! chip->in_ac97_init) |
99b359ba | 403 | snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg); |
1da177e4 LT |
404 | res = 0xffff; |
405 | } | |
406 | } | |
2c56c47f SK |
407 | if (reg == AC97_GPIO_STATUS) |
408 | iagetword(chip, 0); /* clear semaphore */ | |
1da177e4 LT |
409 | return res; |
410 | } | |
411 | ||
412 | ||
413 | /* | |
414 | * DMA I/O | |
415 | */ | |
6b75a9d8 | 416 | static void snd_intel8x0_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev) |
1da177e4 LT |
417 | { |
418 | int idx; | |
419 | u32 *bdbar = ichdev->bdbar; | |
420 | unsigned long port = ichdev->reg_offset; | |
421 | ||
422 | iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); | |
423 | if (ichdev->size == ichdev->fragsize) { | |
424 | ichdev->ack_reload = ichdev->ack = 2; | |
425 | ichdev->fragsize1 = ichdev->fragsize >> 1; | |
426 | for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { | |
427 | bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); | |
428 | bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ | |
429 | ichdev->fragsize1 >> chip->pcm_pos_shift); | |
430 | bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); | |
431 | bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ | |
432 | ichdev->fragsize1 >> chip->pcm_pos_shift); | |
433 | } | |
434 | ichdev->frags = 2; | |
435 | } else { | |
436 | ichdev->ack_reload = ichdev->ack = 1; | |
437 | ichdev->fragsize1 = ichdev->fragsize; | |
438 | for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { | |
439 | bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size)); | |
440 | bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ | |
441 | ichdev->fragsize >> chip->pcm_pos_shift); | |
442 | // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]); | |
443 | } | |
444 | ichdev->frags = ichdev->size / ichdev->fragsize; | |
445 | } | |
446 | iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); | |
447 | ichdev->civ = 0; | |
448 | iputbyte(chip, port + ICH_REG_OFF_CIV, 0); | |
449 | ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; | |
450 | ichdev->position = 0; | |
451 | #if 0 | |
452 | printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", | |
453 | ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1); | |
454 | #endif | |
455 | /* clear interrupts */ | |
456 | iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); | |
457 | } | |
458 | ||
459 | /* | |
460 | * Interrupt handler | |
461 | */ | |
462 | ||
6b75a9d8 | 463 | static inline void snd_intel8x0_update(struct intel8x0m *chip, struct ichdev *ichdev) |
1da177e4 LT |
464 | { |
465 | unsigned long port = ichdev->reg_offset; | |
466 | int civ, i, step; | |
467 | int ack = 0; | |
468 | ||
469 | civ = igetbyte(chip, port + ICH_REG_OFF_CIV); | |
470 | if (civ == ichdev->civ) { | |
471 | // snd_printd("civ same %d\n", civ); | |
472 | step = 1; | |
473 | ichdev->civ++; | |
474 | ichdev->civ &= ICH_REG_LVI_MASK; | |
475 | } else { | |
476 | step = civ - ichdev->civ; | |
477 | if (step < 0) | |
478 | step += ICH_REG_LVI_MASK + 1; | |
479 | // if (step != 1) | |
480 | // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); | |
481 | ichdev->civ = civ; | |
482 | } | |
483 | ||
484 | ichdev->position += step * ichdev->fragsize1; | |
485 | ichdev->position %= ichdev->size; | |
486 | ichdev->lvi += step; | |
487 | ichdev->lvi &= ICH_REG_LVI_MASK; | |
488 | iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); | |
489 | for (i = 0; i < step; i++) { | |
490 | ichdev->lvi_frag++; | |
491 | ichdev->lvi_frag %= ichdev->frags; | |
6b75a9d8 TI |
492 | ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + |
493 | ichdev->lvi_frag * | |
494 | ichdev->fragsize1); | |
495 | #if 0 | |
496 | printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", | |
497 | ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], | |
498 | ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), | |
499 | inl(port + 4), inb(port + ICH_REG_OFF_CR)); | |
500 | #endif | |
1da177e4 LT |
501 | if (--ichdev->ack == 0) { |
502 | ichdev->ack = ichdev->ack_reload; | |
503 | ack = 1; | |
504 | } | |
505 | } | |
506 | if (ack && ichdev->substream) { | |
507 | spin_unlock(&chip->reg_lock); | |
508 | snd_pcm_period_elapsed(ichdev->substream); | |
509 | spin_lock(&chip->reg_lock); | |
510 | } | |
511 | iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); | |
512 | } | |
513 | ||
514 | static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
515 | { | |
6b75a9d8 TI |
516 | struct intel8x0m *chip = dev_id; |
517 | struct ichdev *ichdev; | |
1da177e4 LT |
518 | unsigned int status; |
519 | unsigned int i; | |
520 | ||
521 | spin_lock(&chip->reg_lock); | |
522 | status = igetdword(chip, chip->int_sta_reg); | |
523 | if (status == 0xffffffff) { /* we are not yet resumed */ | |
524 | spin_unlock(&chip->reg_lock); | |
525 | return IRQ_NONE; | |
526 | } | |
527 | if ((status & chip->int_sta_mask) == 0) { | |
528 | if (status) | |
529 | iputdword(chip, chip->int_sta_reg, status); | |
530 | spin_unlock(&chip->reg_lock); | |
531 | return IRQ_NONE; | |
532 | } | |
533 | ||
534 | for (i = 0; i < chip->bdbars_count; i++) { | |
535 | ichdev = &chip->ichd[i]; | |
536 | if (status & ichdev->int_sta_mask) | |
537 | snd_intel8x0_update(chip, ichdev); | |
538 | } | |
539 | ||
540 | /* ack them */ | |
541 | iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); | |
542 | spin_unlock(&chip->reg_lock); | |
543 | ||
544 | return IRQ_HANDLED; | |
545 | } | |
546 | ||
547 | /* | |
548 | * PCM part | |
549 | */ | |
550 | ||
6b75a9d8 | 551 | static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 | 552 | { |
6b75a9d8 TI |
553 | struct intel8x0m *chip = snd_pcm_substream_chip(substream); |
554 | struct ichdev *ichdev = get_ichdev(substream); | |
1da177e4 LT |
555 | unsigned char val = 0; |
556 | unsigned long port = ichdev->reg_offset; | |
557 | ||
558 | switch (cmd) { | |
559 | case SNDRV_PCM_TRIGGER_START: | |
560 | case SNDRV_PCM_TRIGGER_RESUME: | |
561 | val = ICH_IOCE | ICH_STARTBM; | |
562 | break; | |
563 | case SNDRV_PCM_TRIGGER_STOP: | |
564 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
565 | val = 0; | |
566 | break; | |
567 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
568 | val = ICH_IOCE; | |
569 | break; | |
570 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
571 | val = ICH_IOCE | ICH_STARTBM; | |
572 | break; | |
573 | default: | |
574 | return -EINVAL; | |
575 | } | |
576 | iputbyte(chip, port + ICH_REG_OFF_CR, val); | |
577 | if (cmd == SNDRV_PCM_TRIGGER_STOP) { | |
578 | /* wait until DMA stopped */ | |
579 | while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; | |
580 | /* reset whole DMA things */ | |
581 | iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); | |
582 | } | |
583 | return 0; | |
584 | } | |
585 | ||
6b75a9d8 TI |
586 | static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream, |
587 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 LT |
588 | { |
589 | return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
590 | } | |
591 | ||
6b75a9d8 | 592 | static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream) |
1da177e4 LT |
593 | { |
594 | return snd_pcm_lib_free_pages(substream); | |
595 | } | |
596 | ||
6b75a9d8 | 597 | static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 598 | { |
6b75a9d8 TI |
599 | struct intel8x0m *chip = snd_pcm_substream_chip(substream); |
600 | struct ichdev *ichdev = get_ichdev(substream); | |
1da177e4 LT |
601 | size_t ptr1, ptr; |
602 | ||
603 | ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift; | |
604 | if (ptr1 != 0) | |
605 | ptr = ichdev->fragsize1 - ptr1; | |
606 | else | |
607 | ptr = 0; | |
608 | ptr += ichdev->position; | |
609 | if (ptr >= ichdev->size) | |
610 | return 0; | |
611 | return bytes_to_frames(substream->runtime, ptr); | |
612 | } | |
613 | ||
6b75a9d8 | 614 | static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 615 | { |
6b75a9d8 TI |
616 | struct intel8x0m *chip = snd_pcm_substream_chip(substream); |
617 | struct snd_pcm_runtime *runtime = substream->runtime; | |
618 | struct ichdev *ichdev = get_ichdev(substream); | |
1da177e4 LT |
619 | |
620 | ichdev->physbuf = runtime->dma_addr; | |
621 | ichdev->size = snd_pcm_lib_buffer_bytes(substream); | |
622 | ichdev->fragsize = snd_pcm_lib_period_bytes(substream); | |
623 | snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate); | |
624 | snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0); | |
625 | snd_intel8x0_setup_periods(chip, ichdev); | |
626 | return 0; | |
627 | } | |
628 | ||
6b75a9d8 | 629 | static struct snd_pcm_hardware snd_intel8x0m_stream = |
1da177e4 LT |
630 | { |
631 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
632 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
633 | SNDRV_PCM_INFO_MMAP_VALID | | |
634 | SNDRV_PCM_INFO_PAUSE | | |
635 | SNDRV_PCM_INFO_RESUME), | |
636 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
637 | .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT, | |
638 | .rate_min = 8000, | |
639 | .rate_max = 16000, | |
640 | .channels_min = 1, | |
641 | .channels_max = 1, | |
642 | .buffer_bytes_max = 64 * 1024, | |
643 | .period_bytes_min = 32, | |
644 | .period_bytes_max = 64 * 1024, | |
645 | .periods_min = 1, | |
646 | .periods_max = 1024, | |
647 | .fifo_size = 0, | |
648 | }; | |
649 | ||
650 | ||
6b75a9d8 | 651 | static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) |
1da177e4 LT |
652 | { |
653 | static unsigned int rates[] = { 8000, 9600, 12000, 16000 }; | |
6b75a9d8 | 654 | static struct snd_pcm_hw_constraint_list hw_constraints_rates = { |
1da177e4 LT |
655 | .count = ARRAY_SIZE(rates), |
656 | .list = rates, | |
657 | .mask = 0, | |
658 | }; | |
6b75a9d8 | 659 | struct snd_pcm_runtime *runtime = substream->runtime; |
1da177e4 LT |
660 | int err; |
661 | ||
662 | ichdev->substream = substream; | |
663 | runtime->hw = snd_intel8x0m_stream; | |
6b75a9d8 TI |
664 | err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, |
665 | &hw_constraints_rates); | |
1da177e4 LT |
666 | if ( err < 0 ) |
667 | return err; | |
668 | runtime->private_data = ichdev; | |
669 | return 0; | |
670 | } | |
671 | ||
6b75a9d8 | 672 | static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream) |
1da177e4 | 673 | { |
6b75a9d8 | 674 | struct intel8x0m *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
675 | |
676 | return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]); | |
677 | } | |
678 | ||
6b75a9d8 | 679 | static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream) |
1da177e4 | 680 | { |
6b75a9d8 | 681 | struct intel8x0m *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
682 | |
683 | chip->ichd[ICHD_MDMOUT].substream = NULL; | |
684 | return 0; | |
685 | } | |
686 | ||
6b75a9d8 | 687 | static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 688 | { |
6b75a9d8 | 689 | struct intel8x0m *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
690 | |
691 | return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]); | |
692 | } | |
693 | ||
6b75a9d8 | 694 | static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream) |
1da177e4 | 695 | { |
6b75a9d8 | 696 | struct intel8x0m *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
697 | |
698 | chip->ichd[ICHD_MDMIN].substream = NULL; | |
699 | return 0; | |
700 | } | |
701 | ||
702 | ||
6b75a9d8 | 703 | static struct snd_pcm_ops snd_intel8x0m_playback_ops = { |
1da177e4 LT |
704 | .open = snd_intel8x0m_playback_open, |
705 | .close = snd_intel8x0m_playback_close, | |
706 | .ioctl = snd_pcm_lib_ioctl, | |
707 | .hw_params = snd_intel8x0_hw_params, | |
708 | .hw_free = snd_intel8x0_hw_free, | |
709 | .prepare = snd_intel8x0m_pcm_prepare, | |
83a5b72a | 710 | .trigger = snd_intel8x0_pcm_trigger, |
1da177e4 LT |
711 | .pointer = snd_intel8x0_pcm_pointer, |
712 | }; | |
713 | ||
6b75a9d8 | 714 | static struct snd_pcm_ops snd_intel8x0m_capture_ops = { |
1da177e4 LT |
715 | .open = snd_intel8x0m_capture_open, |
716 | .close = snd_intel8x0m_capture_close, | |
717 | .ioctl = snd_pcm_lib_ioctl, | |
718 | .hw_params = snd_intel8x0_hw_params, | |
719 | .hw_free = snd_intel8x0_hw_free, | |
720 | .prepare = snd_intel8x0m_pcm_prepare, | |
83a5b72a | 721 | .trigger = snd_intel8x0_pcm_trigger, |
1da177e4 LT |
722 | .pointer = snd_intel8x0_pcm_pointer, |
723 | }; | |
724 | ||
725 | ||
726 | struct ich_pcm_table { | |
727 | char *suffix; | |
6b75a9d8 TI |
728 | struct snd_pcm_ops *playback_ops; |
729 | struct snd_pcm_ops *capture_ops; | |
1da177e4 LT |
730 | size_t prealloc_size; |
731 | size_t prealloc_max_size; | |
732 | int ac97_idx; | |
733 | }; | |
734 | ||
6b75a9d8 TI |
735 | static int __devinit snd_intel8x0_pcm1(struct intel8x0m *chip, int device, |
736 | struct ich_pcm_table *rec) | |
1da177e4 | 737 | { |
6b75a9d8 | 738 | struct snd_pcm *pcm; |
1da177e4 LT |
739 | int err; |
740 | char name[32]; | |
741 | ||
742 | if (rec->suffix) | |
743 | sprintf(name, "Intel ICH - %s", rec->suffix); | |
744 | else | |
745 | strcpy(name, "Intel ICH"); | |
746 | err = snd_pcm_new(chip->card, name, device, | |
747 | rec->playback_ops ? 1 : 0, | |
748 | rec->capture_ops ? 1 : 0, &pcm); | |
749 | if (err < 0) | |
750 | return err; | |
751 | ||
752 | if (rec->playback_ops) | |
753 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); | |
754 | if (rec->capture_ops) | |
755 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); | |
756 | ||
757 | pcm->private_data = chip; | |
758 | pcm->info_flags = 0; | |
6632d198 | 759 | pcm->dev_class = SNDRV_PCM_CLASS_MODEM; |
1da177e4 LT |
760 | if (rec->suffix) |
761 | sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); | |
762 | else | |
763 | strcpy(pcm->name, chip->card->shortname); | |
764 | chip->pcm[device] = pcm; | |
765 | ||
766 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
767 | snd_dma_pci_data(chip->pci), | |
768 | rec->prealloc_size, | |
769 | rec->prealloc_max_size); | |
770 | ||
771 | return 0; | |
772 | } | |
773 | ||
774 | static struct ich_pcm_table intel_pcms[] __devinitdata = { | |
775 | { | |
776 | .suffix = "Modem", | |
777 | .playback_ops = &snd_intel8x0m_playback_ops, | |
778 | .capture_ops = &snd_intel8x0m_capture_ops, | |
779 | .prealloc_size = 32 * 1024, | |
780 | .prealloc_max_size = 64 * 1024, | |
781 | }, | |
782 | }; | |
783 | ||
6b75a9d8 | 784 | static int __devinit snd_intel8x0_pcm(struct intel8x0m *chip) |
1da177e4 LT |
785 | { |
786 | int i, tblsize, device, err; | |
787 | struct ich_pcm_table *tbl, *rec; | |
788 | ||
789 | #if 1 | |
790 | tbl = intel_pcms; | |
791 | tblsize = 1; | |
792 | #else | |
793 | switch (chip->device_type) { | |
794 | case DEVICE_NFORCE: | |
795 | tbl = nforce_pcms; | |
796 | tblsize = ARRAY_SIZE(nforce_pcms); | |
797 | break; | |
798 | case DEVICE_ALI: | |
799 | tbl = ali_pcms; | |
800 | tblsize = ARRAY_SIZE(ali_pcms); | |
801 | break; | |
802 | default: | |
803 | tbl = intel_pcms; | |
804 | tblsize = 2; | |
805 | break; | |
806 | } | |
807 | #endif | |
808 | device = 0; | |
809 | for (i = 0; i < tblsize; i++) { | |
810 | rec = tbl + i; | |
811 | if (i > 0 && rec->ac97_idx) { | |
812 | /* activate PCM only when associated AC'97 codec */ | |
813 | if (! chip->ichd[rec->ac97_idx].ac97) | |
814 | continue; | |
815 | } | |
816 | err = snd_intel8x0_pcm1(chip, device, rec); | |
817 | if (err < 0) | |
818 | return err; | |
819 | device++; | |
820 | } | |
821 | ||
822 | chip->pcm_devs = device; | |
823 | return 0; | |
824 | } | |
825 | ||
826 | ||
827 | /* | |
828 | * Mixer part | |
829 | */ | |
830 | ||
6b75a9d8 | 831 | static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus) |
1da177e4 | 832 | { |
6b75a9d8 | 833 | struct intel8x0m *chip = bus->private_data; |
1da177e4 LT |
834 | chip->ac97_bus = NULL; |
835 | } | |
836 | ||
6b75a9d8 | 837 | static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97) |
1da177e4 | 838 | { |
6b75a9d8 | 839 | struct intel8x0m *chip = ac97->private_data; |
1da177e4 LT |
840 | chip->ac97 = NULL; |
841 | } | |
842 | ||
843 | ||
6b75a9d8 | 844 | static int __devinit snd_intel8x0_mixer(struct intel8x0m *chip, int ac97_clock) |
1da177e4 | 845 | { |
6b75a9d8 TI |
846 | struct snd_ac97_bus *pbus; |
847 | struct snd_ac97_template ac97; | |
848 | struct snd_ac97 *x97; | |
1da177e4 LT |
849 | int err; |
850 | unsigned int glob_sta = 0; | |
6b75a9d8 | 851 | static struct snd_ac97_bus_ops ops = { |
1da177e4 LT |
852 | .write = snd_intel8x0_codec_write, |
853 | .read = snd_intel8x0_codec_read, | |
854 | }; | |
855 | ||
856 | chip->in_ac97_init = 1; | |
857 | ||
858 | memset(&ac97, 0, sizeof(ac97)); | |
859 | ac97.private_data = chip; | |
860 | ac97.private_free = snd_intel8x0_mixer_free_ac97; | |
861 | ac97.scaps = AC97_SCAP_SKIP_AUDIO; | |
862 | ||
863 | glob_sta = igetdword(chip, ICHREG(GLOB_STA)); | |
864 | ||
865 | if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0) | |
866 | goto __err; | |
867 | pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; | |
1da177e4 LT |
868 | if (ac97_clock >= 8000 && ac97_clock <= 48000) |
869 | pbus->clock = ac97_clock; | |
870 | chip->ac97_bus = pbus; | |
871 | ||
872 | ac97.pci = chip->pci; | |
873 | ac97.num = glob_sta & ICH_SCR ? 1 : 0; | |
874 | if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) { | |
875 | snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num); | |
876 | if (ac97.num == 0) | |
877 | goto __err; | |
878 | return err; | |
879 | } | |
880 | chip->ac97 = x97; | |
881 | if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) { | |
882 | chip->ichd[ICHD_MDMIN].ac97 = x97; | |
883 | chip->ichd[ICHD_MDMOUT].ac97 = x97; | |
884 | } | |
1da177e4 LT |
885 | |
886 | chip->in_ac97_init = 0; | |
887 | return 0; | |
888 | ||
889 | __err: | |
890 | /* clear the cold-reset bit for the next chance */ | |
891 | if (chip->device_type != DEVICE_ALI) | |
6b75a9d8 TI |
892 | iputdword(chip, ICHREG(GLOB_CNT), |
893 | igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); | |
1da177e4 LT |
894 | return err; |
895 | } | |
896 | ||
897 | ||
898 | /* | |
899 | * | |
900 | */ | |
901 | ||
6b75a9d8 | 902 | static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing) |
1da177e4 LT |
903 | { |
904 | unsigned long end_time; | |
905 | unsigned int cnt, status, nstatus; | |
906 | ||
907 | /* put logic to right state */ | |
908 | /* first clear status bits */ | |
909 | status = ICH_RCS | ICH_MIINT | ICH_MOINT; | |
910 | cnt = igetdword(chip, ICHREG(GLOB_STA)); | |
911 | iputdword(chip, ICHREG(GLOB_STA), cnt & status); | |
912 | ||
913 | /* ACLink on, 2 channels */ | |
914 | cnt = igetdword(chip, ICHREG(GLOB_CNT)); | |
915 | cnt &= ~(ICH_ACLINK); | |
916 | /* finish cold or do warm reset */ | |
917 | cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; | |
918 | iputdword(chip, ICHREG(GLOB_CNT), cnt); | |
919 | end_time = (jiffies + (HZ / 4)) + 1; | |
920 | do { | |
921 | if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) | |
922 | goto __ok; | |
954bea35 | 923 | schedule_timeout_uninterruptible(1); |
1da177e4 | 924 | } while (time_after_eq(end_time, jiffies)); |
6b75a9d8 TI |
925 | snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n", |
926 | igetdword(chip, ICHREG(GLOB_CNT))); | |
1da177e4 LT |
927 | return -EIO; |
928 | ||
929 | __ok: | |
930 | if (probing) { | |
931 | /* wait for any codec ready status. | |
932 | * Once it becomes ready it should remain ready | |
933 | * as long as we do not disable the ac97 link. | |
934 | */ | |
935 | end_time = jiffies + HZ; | |
936 | do { | |
6b75a9d8 TI |
937 | status = igetdword(chip, ICHREG(GLOB_STA)) & |
938 | (ICH_PCR | ICH_SCR | ICH_TCR); | |
1da177e4 LT |
939 | if (status) |
940 | break; | |
954bea35 | 941 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
942 | } while (time_after_eq(end_time, jiffies)); |
943 | if (! status) { | |
944 | /* no codec is found */ | |
6b75a9d8 TI |
945 | snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", |
946 | igetdword(chip, ICHREG(GLOB_STA))); | |
1da177e4 LT |
947 | return -EIO; |
948 | } | |
949 | ||
950 | /* up to two codecs (modem cannot be tertiary with ICH4) */ | |
951 | nstatus = ICH_PCR | ICH_SCR; | |
952 | ||
953 | /* wait for other codecs ready status. */ | |
954 | end_time = jiffies + HZ / 4; | |
955 | while (status != nstatus && time_after_eq(end_time, jiffies)) { | |
954bea35 | 956 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
957 | status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus; |
958 | } | |
959 | ||
960 | } else { | |
961 | /* resume phase */ | |
962 | status = 0; | |
963 | if (chip->ac97) | |
964 | status |= get_ich_codec_bit(chip, chip->ac97->num); | |
965 | /* wait until all the probed codecs are ready */ | |
966 | end_time = jiffies + HZ; | |
967 | do { | |
6b75a9d8 TI |
968 | nstatus = igetdword(chip, ICHREG(GLOB_STA)) & |
969 | (ICH_PCR | ICH_SCR | ICH_TCR); | |
1da177e4 LT |
970 | if (status == nstatus) |
971 | break; | |
954bea35 | 972 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
973 | } while (time_after_eq(end_time, jiffies)); |
974 | } | |
975 | ||
976 | if (chip->device_type == DEVICE_SIS) { | |
977 | /* unmute the output on SIS7012 */ | |
978 | iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); | |
979 | } | |
980 | ||
981 | return 0; | |
982 | } | |
983 | ||
6b75a9d8 | 984 | static int snd_intel8x0_chip_init(struct intel8x0m *chip, int probing) |
1da177e4 LT |
985 | { |
986 | unsigned int i; | |
987 | int err; | |
988 | ||
989 | if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0) | |
990 | return err; | |
991 | iagetword(chip, 0); /* clear semaphore flag */ | |
992 | ||
993 | /* disable interrupts */ | |
994 | for (i = 0; i < chip->bdbars_count; i++) | |
995 | iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); | |
996 | /* reset channels */ | |
997 | for (i = 0; i < chip->bdbars_count; i++) | |
998 | iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); | |
999 | /* initialize Buffer Descriptor Lists */ | |
1000 | for (i = 0; i < chip->bdbars_count; i++) | |
1001 | iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr); | |
1002 | return 0; | |
1003 | } | |
1004 | ||
6b75a9d8 | 1005 | static int snd_intel8x0_free(struct intel8x0m *chip) |
1da177e4 LT |
1006 | { |
1007 | unsigned int i; | |
1008 | ||
1009 | if (chip->irq < 0) | |
1010 | goto __hw_end; | |
1011 | /* disable interrupts */ | |
1012 | for (i = 0; i < chip->bdbars_count; i++) | |
1013 | iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); | |
1014 | /* reset channels */ | |
1015 | for (i = 0; i < chip->bdbars_count; i++) | |
1016 | iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); | |
1017 | /* --- */ | |
1018 | synchronize_irq(chip->irq); | |
1019 | __hw_end: | |
1020 | if (chip->bdbars.area) | |
1021 | snd_dma_free_pages(&chip->bdbars); | |
1022 | if (chip->remap_addr) | |
1023 | iounmap(chip->remap_addr); | |
1024 | if (chip->remap_bmaddr) | |
1025 | iounmap(chip->remap_bmaddr); | |
1026 | if (chip->irq >= 0) | |
6b75a9d8 | 1027 | free_irq(chip->irq, chip); |
1da177e4 LT |
1028 | pci_release_regions(chip->pci); |
1029 | pci_disable_device(chip->pci); | |
1030 | kfree(chip); | |
1031 | return 0; | |
1032 | } | |
1033 | ||
1034 | #ifdef CONFIG_PM | |
1035 | /* | |
1036 | * power management | |
1037 | */ | |
5809c6c4 | 1038 | static int intel8x0m_suspend(struct pci_dev *pci, pm_message_t state) |
1da177e4 | 1039 | { |
5809c6c4 TI |
1040 | struct snd_card *card = pci_get_drvdata(pci); |
1041 | struct intel8x0m *chip = card->private_data; | |
1da177e4 LT |
1042 | int i; |
1043 | ||
5809c6c4 | 1044 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
1da177e4 LT |
1045 | for (i = 0; i < chip->pcm_devs; i++) |
1046 | snd_pcm_suspend_all(chip->pcm[i]); | |
5809c6c4 TI |
1047 | snd_ac97_suspend(chip->ac97); |
1048 | pci_disable_device(pci); | |
1049 | pci_save_state(pci); | |
1da177e4 LT |
1050 | return 0; |
1051 | } | |
1052 | ||
5809c6c4 | 1053 | static int intel8x0m_resume(struct pci_dev *pci) |
1da177e4 | 1054 | { |
5809c6c4 TI |
1055 | struct snd_card *card = pci_get_drvdata(pci); |
1056 | struct intel8x0m *chip = card->private_data; | |
1057 | ||
1058 | pci_restore_state(pci); | |
1059 | pci_enable_device(pci); | |
1060 | pci_set_master(pci); | |
1da177e4 | 1061 | snd_intel8x0_chip_init(chip, 0); |
5809c6c4 | 1062 | snd_ac97_resume(chip->ac97); |
1da177e4 | 1063 | |
5809c6c4 | 1064 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
1da177e4 LT |
1065 | return 0; |
1066 | } | |
1067 | #endif /* CONFIG_PM */ | |
1068 | ||
adf1b3d2 | 1069 | #ifdef CONFIG_PROC_FS |
6b75a9d8 TI |
1070 | static void snd_intel8x0m_proc_read(struct snd_info_entry * entry, |
1071 | struct snd_info_buffer *buffer) | |
1da177e4 | 1072 | { |
6b75a9d8 | 1073 | struct intel8x0m *chip = entry->private_data; |
1da177e4 LT |
1074 | unsigned int tmp; |
1075 | ||
1076 | snd_iprintf(buffer, "Intel8x0m\n\n"); | |
1077 | if (chip->device_type == DEVICE_ALI) | |
1078 | return; | |
1079 | tmp = igetdword(chip, ICHREG(GLOB_STA)); | |
6b75a9d8 TI |
1080 | snd_iprintf(buffer, "Global control : 0x%08x\n", |
1081 | igetdword(chip, ICHREG(GLOB_CNT))); | |
1da177e4 LT |
1082 | snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); |
1083 | snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n", | |
1084 | tmp & ICH_PCR ? " primary" : "", | |
1085 | tmp & ICH_SCR ? " secondary" : "", | |
1086 | tmp & ICH_TCR ? " tertiary" : "", | |
1087 | (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : ""); | |
1088 | } | |
1089 | ||
6b75a9d8 | 1090 | static void __devinit snd_intel8x0m_proc_init(struct intel8x0m * chip) |
1da177e4 | 1091 | { |
6b75a9d8 | 1092 | struct snd_info_entry *entry; |
1da177e4 LT |
1093 | |
1094 | if (! snd_card_proc_new(chip->card, "intel8x0m", &entry)) | |
1095 | snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0m_proc_read); | |
1096 | } | |
adf1b3d2 TI |
1097 | #else /* !CONFIG_PROC_FS */ |
1098 | #define snd_intel8x0m_proc_init(chip) | |
1099 | #endif /* CONFIG_PROC_FS */ | |
1100 | ||
1da177e4 | 1101 | |
6b75a9d8 | 1102 | static int snd_intel8x0_dev_free(struct snd_device *device) |
1da177e4 | 1103 | { |
6b75a9d8 | 1104 | struct intel8x0m *chip = device->device_data; |
1da177e4 LT |
1105 | return snd_intel8x0_free(chip); |
1106 | } | |
1107 | ||
1108 | struct ich_reg_info { | |
1109 | unsigned int int_sta_mask; | |
1110 | unsigned int offset; | |
1111 | }; | |
1112 | ||
6b75a9d8 | 1113 | static int __devinit snd_intel8x0m_create(struct snd_card *card, |
1da177e4 LT |
1114 | struct pci_dev *pci, |
1115 | unsigned long device_type, | |
6b75a9d8 | 1116 | struct intel8x0m ** r_intel8x0) |
1da177e4 | 1117 | { |
6b75a9d8 | 1118 | struct intel8x0m *chip; |
1da177e4 LT |
1119 | int err; |
1120 | unsigned int i; | |
1121 | unsigned int int_sta_masks; | |
6b75a9d8 TI |
1122 | struct ichdev *ichdev; |
1123 | static struct snd_device_ops ops = { | |
1da177e4 LT |
1124 | .dev_free = snd_intel8x0_dev_free, |
1125 | }; | |
1126 | static struct ich_reg_info intel_regs[2] = { | |
1127 | { ICH_MIINT, 0 }, | |
1128 | { ICH_MOINT, 0x10 }, | |
1129 | }; | |
1130 | struct ich_reg_info *tbl; | |
1131 | ||
1132 | *r_intel8x0 = NULL; | |
1133 | ||
1134 | if ((err = pci_enable_device(pci)) < 0) | |
1135 | return err; | |
1136 | ||
e560d8d8 | 1137 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
1da177e4 LT |
1138 | if (chip == NULL) { |
1139 | pci_disable_device(pci); | |
1140 | return -ENOMEM; | |
1141 | } | |
1142 | spin_lock_init(&chip->reg_lock); | |
1143 | chip->device_type = device_type; | |
1144 | chip->card = card; | |
1145 | chip->pci = pci; | |
1146 | chip->irq = -1; | |
1147 | ||
1148 | if ((err = pci_request_regions(pci, card->shortname)) < 0) { | |
1149 | kfree(chip); | |
1150 | pci_disable_device(pci); | |
1151 | return err; | |
1152 | } | |
1153 | ||
1154 | if (device_type == DEVICE_ALI) { | |
1155 | /* ALI5455 has no ac97 region */ | |
1156 | chip->bmaddr = pci_resource_start(pci, 0); | |
1157 | goto port_inited; | |
1158 | } | |
1159 | ||
1160 | if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */ | |
1161 | chip->mmio = 1; | |
1162 | chip->addr = pci_resource_start(pci, 2); | |
1163 | chip->remap_addr = ioremap_nocache(chip->addr, | |
1164 | pci_resource_len(pci, 2)); | |
1165 | if (chip->remap_addr == NULL) { | |
99b359ba | 1166 | snd_printk(KERN_ERR "AC'97 space ioremap problem\n"); |
1da177e4 LT |
1167 | snd_intel8x0_free(chip); |
1168 | return -EIO; | |
1169 | } | |
1170 | } else { | |
1171 | chip->addr = pci_resource_start(pci, 0); | |
1172 | } | |
1173 | if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */ | |
1174 | chip->bm_mmio = 1; | |
1175 | chip->bmaddr = pci_resource_start(pci, 3); | |
1176 | chip->remap_bmaddr = ioremap_nocache(chip->bmaddr, | |
1177 | pci_resource_len(pci, 3)); | |
1178 | if (chip->remap_bmaddr == NULL) { | |
99b359ba | 1179 | snd_printk(KERN_ERR "Controller space ioremap problem\n"); |
1da177e4 LT |
1180 | snd_intel8x0_free(chip); |
1181 | return -EIO; | |
1182 | } | |
1183 | } else { | |
1184 | chip->bmaddr = pci_resource_start(pci, 1); | |
1185 | } | |
1186 | ||
1187 | port_inited: | |
6b75a9d8 TI |
1188 | if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, |
1189 | card->shortname, chip)) { | |
99b359ba | 1190 | snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); |
1da177e4 LT |
1191 | snd_intel8x0_free(chip); |
1192 | return -EBUSY; | |
1193 | } | |
1194 | chip->irq = pci->irq; | |
1195 | pci_set_master(pci); | |
1196 | synchronize_irq(chip->irq); | |
1197 | ||
1198 | /* initialize offsets */ | |
1199 | chip->bdbars_count = 2; | |
1200 | tbl = intel_regs; | |
1201 | ||
1202 | for (i = 0; i < chip->bdbars_count; i++) { | |
1203 | ichdev = &chip->ichd[i]; | |
1204 | ichdev->ichd = i; | |
1205 | ichdev->reg_offset = tbl[i].offset; | |
1206 | ichdev->int_sta_mask = tbl[i].int_sta_mask; | |
1207 | if (device_type == DEVICE_SIS) { | |
1208 | /* SiS 7013 swaps the registers */ | |
1209 | ichdev->roff_sr = ICH_REG_OFF_PICB; | |
1210 | ichdev->roff_picb = ICH_REG_OFF_SR; | |
1211 | } else { | |
1212 | ichdev->roff_sr = ICH_REG_OFF_SR; | |
1213 | ichdev->roff_picb = ICH_REG_OFF_PICB; | |
1214 | } | |
1215 | if (device_type == DEVICE_ALI) | |
1216 | ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; | |
1217 | } | |
1218 | /* SIS7013 handles the pcm data in bytes, others are in words */ | |
1219 | chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; | |
1220 | ||
1221 | /* allocate buffer descriptor lists */ | |
1222 | /* the start of each lists must be aligned to 8 bytes */ | |
1223 | if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), | |
1224 | chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, | |
1225 | &chip->bdbars) < 0) { | |
1226 | snd_intel8x0_free(chip); | |
1227 | return -ENOMEM; | |
1228 | } | |
1229 | /* tables must be aligned to 8 bytes here, but the kernel pages | |
1230 | are much bigger, so we don't care (on i386) */ | |
1231 | int_sta_masks = 0; | |
1232 | for (i = 0; i < chip->bdbars_count; i++) { | |
1233 | ichdev = &chip->ichd[i]; | |
1234 | ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2); | |
1235 | ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2); | |
1236 | int_sta_masks |= ichdev->int_sta_mask; | |
1237 | } | |
1238 | chip->int_sta_reg = ICH_REG_GLOB_STA; | |
1239 | chip->int_sta_mask = int_sta_masks; | |
1240 | ||
1241 | if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { | |
1242 | snd_intel8x0_free(chip); | |
1243 | return err; | |
1244 | } | |
1245 | ||
1da177e4 LT |
1246 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { |
1247 | snd_intel8x0_free(chip); | |
1248 | return err; | |
1249 | } | |
1250 | ||
1251 | snd_card_set_dev(card, &pci->dev); | |
1252 | ||
1253 | *r_intel8x0 = chip; | |
1254 | return 0; | |
1255 | } | |
1256 | ||
1257 | static struct shortname_table { | |
1258 | unsigned int id; | |
1259 | const char *s; | |
1260 | } shortnames[] __devinitdata = { | |
8cdfd251 TI |
1261 | { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" }, |
1262 | { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" }, | |
1da177e4 LT |
1263 | { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" }, |
1264 | { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" }, | |
8cdfd251 TI |
1265 | { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" }, |
1266 | { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" }, | |
1267 | { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" }, | |
1268 | { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" }, | |
1269 | { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" }, | |
1da177e4 LT |
1270 | { 0x7446, "AMD AMD768" }, |
1271 | { PCI_DEVICE_ID_SI_7013, "SiS SI7013" }, | |
8cdfd251 | 1272 | { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" }, |
1da177e4 LT |
1273 | { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" }, |
1274 | { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" }, | |
1275 | { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" }, | |
1276 | #if 0 | |
1277 | { 0x5455, "ALi M5455" }, | |
1278 | { 0x746d, "AMD AMD8111" }, | |
1279 | #endif | |
1280 | { 0 }, | |
1281 | }; | |
1282 | ||
1283 | static int __devinit snd_intel8x0m_probe(struct pci_dev *pci, | |
1284 | const struct pci_device_id *pci_id) | |
1285 | { | |
6b75a9d8 TI |
1286 | struct snd_card *card; |
1287 | struct intel8x0m *chip; | |
1da177e4 LT |
1288 | int err; |
1289 | struct shortname_table *name; | |
1290 | ||
b7fe4622 | 1291 | card = snd_card_new(index, id, THIS_MODULE, 0); |
1da177e4 LT |
1292 | if (card == NULL) |
1293 | return -ENOMEM; | |
1294 | ||
1295 | strcpy(card->driver, "ICH-MODEM"); | |
1296 | strcpy(card->shortname, "Intel ICH"); | |
1297 | for (name = shortnames; name->id; name++) { | |
1298 | if (pci->device == name->id) { | |
1299 | strcpy(card->shortname, name->s); | |
1300 | break; | |
1301 | } | |
1302 | } | |
1303 | strcat(card->shortname," Modem"); | |
1304 | ||
1305 | if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) { | |
1306 | snd_card_free(card); | |
1307 | return err; | |
1308 | } | |
5809c6c4 | 1309 | card->private_data = chip; |
1da177e4 | 1310 | |
b7fe4622 | 1311 | if ((err = snd_intel8x0_mixer(chip, ac97_clock)) < 0) { |
1da177e4 LT |
1312 | snd_card_free(card); |
1313 | return err; | |
1314 | } | |
1315 | if ((err = snd_intel8x0_pcm(chip)) < 0) { | |
1316 | snd_card_free(card); | |
1317 | return err; | |
1318 | } | |
1319 | ||
1320 | snd_intel8x0m_proc_init(chip); | |
1321 | ||
1322 | sprintf(card->longname, "%s at 0x%lx, irq %i", | |
1323 | card->shortname, chip->addr, chip->irq); | |
1324 | ||
1325 | if ((err = snd_card_register(card)) < 0) { | |
1326 | snd_card_free(card); | |
1327 | return err; | |
1328 | } | |
1329 | pci_set_drvdata(pci, card); | |
1da177e4 LT |
1330 | return 0; |
1331 | } | |
1332 | ||
1333 | static void __devexit snd_intel8x0m_remove(struct pci_dev *pci) | |
1334 | { | |
1335 | snd_card_free(pci_get_drvdata(pci)); | |
1336 | pci_set_drvdata(pci, NULL); | |
1337 | } | |
1338 | ||
1339 | static struct pci_driver driver = { | |
1340 | .name = "Intel ICH Modem", | |
1341 | .id_table = snd_intel8x0m_ids, | |
1342 | .probe = snd_intel8x0m_probe, | |
1343 | .remove = __devexit_p(snd_intel8x0m_remove), | |
5809c6c4 TI |
1344 | #ifdef CONFIG_PM |
1345 | .suspend = intel8x0m_suspend, | |
1346 | .resume = intel8x0m_resume, | |
1347 | #endif | |
1da177e4 LT |
1348 | }; |
1349 | ||
1350 | ||
1351 | static int __init alsa_card_intel8x0m_init(void) | |
1352 | { | |
01d25d46 | 1353 | return pci_register_driver(&driver); |
1da177e4 LT |
1354 | } |
1355 | ||
1356 | static void __exit alsa_card_intel8x0m_exit(void) | |
1357 | { | |
1358 | pci_unregister_driver(&driver); | |
1359 | } | |
1360 | ||
1361 | module_init(alsa_card_intel8x0m_init) | |
1362 | module_exit(alsa_card_intel8x0m_exit) |