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PCI: Remove DEFINE_PCI_DEVICE_TABLE macro use
[mirror_ubuntu-bionic-kernel.git] / sound / pci / nm256 / nm256.c
CommitLineData
1da177e4
LT		 1/*
2 * Driver for NeoMagic 256AV and 256ZX chipsets.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * Based on nm256_audio.c OSS driver in linux kernel.
6 * The original author of OSS nm256 driver wishes to remain anonymous,
7 * so I just put my acknoledgment to him/her here.
8 * The original author's web page is found at
9 * http://www.uglx.org/sony.html
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */
26
1da177e4
LT		 27#include <asm/io.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/slab.h>
65a77217 33#include <linux/module.h>
62932df8
IM		 34#include <linux/mutex.h>
35
1da177e4
LT		 36#include <sound/core.h>
37#include <sound/info.h>
38#include <sound/control.h>
39#include <sound/pcm.h>
40#include <sound/ac97_codec.h>
41#include <sound/initval.h>
42
43#define CARD_NAME "NeoMagic 256AV/ZX"
44#define DRIVER_NAME "NM256"
45
46MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
47MODULE_DESCRIPTION("NeoMagic NM256AV/ZX");
48MODULE_LICENSE("GPL");
49MODULE_SUPPORTED_DEVICE("{{NeoMagic,NM256AV},"
50 "{NeoMagic,NM256ZX}}");
51
52/*
53 * some compile conditions.
54 */
55
8a3fb4d0
TI		 56static int index = SNDRV_DEFAULT_IDX1; /* Index */
57static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
58static int playback_bufsize = 16;
59static int capture_bufsize = 16;
a67ff6a5 60static bool force_ac97; /* disabled as default */
8a3fb4d0 61static int buffer_top; /* not specified */
a67ff6a5
RR		 62static bool use_cache; /* disabled */
63static bool vaio_hack; /* disabled */
64static bool reset_workaround;
65static bool reset_workaround_2;
8a3fb4d0
TI		 66
67module_param(index, int, 0444);
1da177e4 68MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
8a3fb4d0 69module_param(id, charp, 0444);
1da177e4 70MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
8a3fb4d0 71module_param(playback_bufsize, int, 0444);
1da177e4 72MODULE_PARM_DESC(playback_bufsize, "DAC frame size in kB for " CARD_NAME " soundcard.");
8a3fb4d0 73module_param(capture_bufsize, int, 0444);
1da177e4 74MODULE_PARM_DESC(capture_bufsize, "ADC frame size in kB for " CARD_NAME " soundcard.");
8a3fb4d0 75module_param(force_ac97, bool, 0444);
1da177e4 76MODULE_PARM_DESC(force_ac97, "Force to use AC97 codec for " CARD_NAME " soundcard.");
8a3fb4d0 77module_param(buffer_top, int, 0444);
1da177e4 78MODULE_PARM_DESC(buffer_top, "Set the top address of audio buffer for " CARD_NAME " soundcard.");
8a3fb4d0 79module_param(use_cache, bool, 0444);
1da177e4 80MODULE_PARM_DESC(use_cache, "Enable the cache for coefficient table access.");
8a3fb4d0 81module_param(vaio_hack, bool, 0444);
1da177e4 82MODULE_PARM_DESC(vaio_hack, "Enable workaround for Sony VAIO notebooks.");
8a3fb4d0 83module_param(reset_workaround, bool, 0444);
1da177e4 84MODULE_PARM_DESC(reset_workaround, "Enable AC97 RESET workaround for some laptops.");
8a3fb4d0 85module_param(reset_workaround_2, bool, 0444);
47530cf4 86MODULE_PARM_DESC(reset_workaround_2, "Enable extended AC97 RESET workaround for some other laptops.");
1da177e4 87
8a3fb4d0 88/* just for backward compatibility */
a67ff6a5 89static bool enable;
8a3fb4d0
TI		 90module_param(enable, bool, 0444);
91
92
93
1da177e4
LT		 94/*
95 * hw definitions
96 */
97
98/* The BIOS signature. */
99#define NM_SIGNATURE 0x4e4d0000
100/* Signature mask. */
101#define NM_SIG_MASK 0xffff0000
102
103/* Size of the second memory area. */
104#define NM_PORT2_SIZE 4096
105
106/* The base offset of the mixer in the second memory area. */
107#define NM_MIXER_OFFSET 0x600
108
109/* The maximum size of a coefficient entry. */
110#define NM_MAX_PLAYBACK_COEF_SIZE 0x5000
111#define NM_MAX_RECORD_COEF_SIZE 0x1260
112
113/* The interrupt register. */
114#define NM_INT_REG 0xa04
115/* And its bits. */
116#define NM_PLAYBACK_INT 0x40
117#define NM_RECORD_INT 0x100
118#define NM_MISC_INT_1 0x4000
119#define NM_MISC_INT_2 0x1
120#define NM_ACK_INT(chip, X) snd_nm256_writew(chip, NM_INT_REG, (X) << 1)
121
122/* The AV's "mixer ready" status bit and location. */
123#define NM_MIXER_STATUS_OFFSET 0xa04
124#define NM_MIXER_READY_MASK 0x0800
125#define NM_MIXER_PRESENCE 0xa06
126#define NM_PRESENCE_MASK 0x0050
127#define NM_PRESENCE_VALUE 0x0040
128
129/*
130 * For the ZX. It uses the same interrupt register, but it holds 32
131 * bits instead of 16.
132 */
133#define NM2_PLAYBACK_INT 0x10000
134#define NM2_RECORD_INT 0x80000
135#define NM2_MISC_INT_1 0x8
136#define NM2_MISC_INT_2 0x2
137#define NM2_ACK_INT(chip, X) snd_nm256_writel(chip, NM_INT_REG, (X))
138
139/* The ZX's "mixer ready" status bit and location. */
140#define NM2_MIXER_STATUS_OFFSET 0xa06
141#define NM2_MIXER_READY_MASK 0x0800
142
143/* The playback registers start from here. */
144#define NM_PLAYBACK_REG_OFFSET 0x0
145/* The record registers start from here. */
146#define NM_RECORD_REG_OFFSET 0x200
147
148/* The rate register is located 2 bytes from the start of the register area. */
149#define NM_RATE_REG_OFFSET 2
150
151/* Mono/stereo flag, number of bits on playback, and rate mask. */
152#define NM_RATE_STEREO 1
153#define NM_RATE_BITS_16 2
154#define NM_RATE_MASK 0xf0
155
156/* Playback enable register. */
157#define NM_PLAYBACK_ENABLE_REG (NM_PLAYBACK_REG_OFFSET + 0x1)
158#define NM_PLAYBACK_ENABLE_FLAG 1
159#define NM_PLAYBACK_ONESHOT 2
160#define NM_PLAYBACK_FREERUN 4
161
162/* Mutes the audio output. */
163#define NM_AUDIO_MUTE_REG (NM_PLAYBACK_REG_OFFSET + 0x18)
164#define NM_AUDIO_MUTE_LEFT 0x8000
165#define NM_AUDIO_MUTE_RIGHT 0x0080
166
167/* Recording enable register. */
168#define NM_RECORD_ENABLE_REG (NM_RECORD_REG_OFFSET + 0)
169#define NM_RECORD_ENABLE_FLAG 1
170#define NM_RECORD_FREERUN 2
171
172/* coefficient buffer pointer */
173#define NM_COEFF_START_OFFSET 0x1c
174#define NM_COEFF_END_OFFSET 0x20
175
176/* DMA buffer offsets */
177#define NM_RBUFFER_START (NM_RECORD_REG_OFFSET + 0x4)
178#define NM_RBUFFER_END (NM_RECORD_REG_OFFSET + 0x10)
179#define NM_RBUFFER_WMARK (NM_RECORD_REG_OFFSET + 0xc)
180#define NM_RBUFFER_CURRP (NM_RECORD_REG_OFFSET + 0x8)
181
182#define NM_PBUFFER_START (NM_PLAYBACK_REG_OFFSET + 0x4)
183#define NM_PBUFFER_END (NM_PLAYBACK_REG_OFFSET + 0x14)
184#define NM_PBUFFER_WMARK (NM_PLAYBACK_REG_OFFSET + 0xc)
185#define NM_PBUFFER_CURRP (NM_PLAYBACK_REG_OFFSET + 0x8)
186
10754f53 187struct nm256_stream {
1da177e4 188
10754f53
TI		 189 struct nm256 *chip;
190 struct snd_pcm_substream *substream;
1da177e4 191 int running;
1204de32 192 int suspended;
1da177e4
LT		 193
194 u32 buf; /* offset from chip->buffer */
195 int bufsize; /* buffer size in bytes */
196 void __iomem *bufptr; /* mapped pointer */
197 unsigned long bufptr_addr; /* physical address of the mapped pointer */
198
199 int dma_size; /* buffer size of the substream in bytes */
200 int period_size; /* period size in bytes */
201 int periods; /* # of periods */
202 int shift; /* bit shifts */
203 int cur_period; /* current period # */
204
205};
206
10754f53 207struct nm256 {
1da177e4 208
10754f53 209 struct snd_card *card;
1da177e4
LT		 210
211 void __iomem *cport; /* control port */
212 struct resource *res_cport; /* its resource */
213 unsigned long cport_addr; /* physical address */
214
215 void __iomem *buffer; /* buffer */
216 struct resource *res_buffer; /* its resource */
217 unsigned long buffer_addr; /* buffer phyiscal address */
218
219 u32 buffer_start; /* start offset from pci resource 0 */
220 u32 buffer_end; /* end offset */
221 u32 buffer_size; /* total buffer size */
222
223 u32 all_coeff_buf; /* coefficient buffer */
224 u32 coeff_buf[2]; /* coefficient buffer for each stream */
225
226 unsigned int coeffs_current: 1; /* coeff. table is loaded? */
227 unsigned int use_cache: 1; /* use one big coef. table */
228 unsigned int reset_workaround: 1; /* Workaround for some laptops to avoid freeze */
47530cf4 229 unsigned int reset_workaround_2: 1; /* Extended workaround for some other laptops to avoid freeze */
a23446c0 230 unsigned int in_resume: 1;
1da177e4
LT		 231
232 int mixer_base; /* register offset of ac97 mixer */
233 int mixer_status_offset; /* offset of mixer status reg. */
234 int mixer_status_mask; /* bit mask to test the mixer status */
235
236 int irq;
1204de32 237 int irq_acks;
7d12e780 238 irq_handler_t interrupt;
1da177e4 239 int badintrcount; /* counter to check bogus interrupts */
62932df8 240 struct mutex irq_mutex;
1da177e4 241
10754f53 242 struct nm256_stream streams[2];
1da177e4 243
10754f53 244 struct snd_ac97 *ac97;
a23446c0 245 unsigned short *ac97_regs; /* register caches, only for valid regs */
1da177e4 246
10754f53 247 struct snd_pcm *pcm;
1da177e4
LT		 248
249 struct pci_dev *pci;
250
251 spinlock_t reg_lock;
252
253};
254
255
256/*
257 * include coefficient table
258 */
259#include "nm256_coef.c"
260
261
262/*
263 * PCI ids
264 */
9baa3c34 265static const struct pci_device_id snd_nm256_ids[] = {
28d27aae
JP		 266 {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO), 0},
267 {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO), 0},
268 {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO), 0},
1da177e4
LT		 269 {0,},
270};
271
272MODULE_DEVICE_TABLE(pci, snd_nm256_ids);
273
274
275/*
276 * lowlvel stuffs
277 */
278
77933d72 279static inline u8
10754f53 280snd_nm256_readb(struct nm256 *chip, int offset)
1da177e4
LT		 281{
282 return readb(chip->cport + offset);
283}
284
77933d72 285static inline u16
10754f53 286snd_nm256_readw(struct nm256 *chip, int offset)
1da177e4
LT		 287{
288 return readw(chip->cport + offset);
289}
290
77933d72 291static inline u32
10754f53 292snd_nm256_readl(struct nm256 *chip, int offset)
1da177e4
LT		 293{
294 return readl(chip->cport + offset);
295}
296
77933d72 297static inline void
10754f53 298snd_nm256_writeb(struct nm256 *chip, int offset, u8 val)
1da177e4
LT		 299{
300 writeb(val, chip->cport + offset);
301}
302
77933d72 303static inline void
10754f53 304snd_nm256_writew(struct nm256 *chip, int offset, u16 val)
1da177e4
LT		 305{
306 writew(val, chip->cport + offset);
307}
308
77933d72 309static inline void
10754f53 310snd_nm256_writel(struct nm256 *chip, int offset, u32 val)
1da177e4
LT		 311{
312 writel(val, chip->cport + offset);
313}
314
77933d72 315static inline void
10754f53 316snd_nm256_write_buffer(struct nm256 *chip, void *src, int offset, int size)
1da177e4
LT		 317{
318 offset -= chip->buffer_start;
99b359ba 319#ifdef CONFIG_SND_DEBUG
1da177e4 320 if (offset < 0 || offset >= chip->buffer_size) {
a3fe03f4
TI		 321 dev_err(chip->card->dev,
322 "write_buffer invalid offset = %d size = %d\n",
10754f53 323 offset, size);
1da177e4
LT		 324 return;
325 }
326#endif
327 memcpy_toio(chip->buffer + offset, src, size);
328}
329
330/*
331 * coefficient handlers -- what a magic!
332 */
333
334static u16
335snd_nm256_get_start_offset(int which)
336{
337 u16 offset = 0;
338 while (which-- > 0)
339 offset += coefficient_sizes[which];
340 return offset;
341}
342
343static void
10754f53 344snd_nm256_load_one_coefficient(struct nm256 *chip, int stream, u32 port, int which)
1da177e4
LT		 345{
346 u32 coeff_buf = chip->coeff_buf[stream];
347 u16 offset = snd_nm256_get_start_offset(which);
348 u16 size = coefficient_sizes[which];
349
350 snd_nm256_write_buffer(chip, coefficients + offset, coeff_buf, size);
351 snd_nm256_writel(chip, port, coeff_buf);
352 /* ??? Record seems to behave differently than playback. */
353 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
354 size--;
355 snd_nm256_writel(chip, port + 4, coeff_buf + size);
356}
357
358static void
10754f53 359snd_nm256_load_coefficient(struct nm256 *chip, int stream, int number)
1da177e4
LT		 360{
361 /* The enable register for the specified engine. */
10754f53
TI		 362 u32 poffset = (stream == SNDRV_PCM_STREAM_CAPTURE ?
363 NM_RECORD_ENABLE_REG : NM_PLAYBACK_ENABLE_REG);
1da177e4
LT		 364 u32 addr = NM_COEFF_START_OFFSET;
365
10754f53
TI		 366 addr += (stream == SNDRV_PCM_STREAM_CAPTURE ?
367 NM_RECORD_REG_OFFSET : NM_PLAYBACK_REG_OFFSET);
1da177e4
LT		 368
369 if (snd_nm256_readb(chip, poffset) & 1) {
a3fe03f4
TI		 370 dev_dbg(chip->card->dev,
371 "NM256: Engine was enabled while loading coefficients!\n");
1da177e4
LT		 372 return;
373 }
374
375 /* The recording engine uses coefficient values 8-15. */
376 number &= 7;
377 if (stream == SNDRV_PCM_STREAM_CAPTURE)
378 number += 8;
379
380 if (! chip->use_cache) {
381 snd_nm256_load_one_coefficient(chip, stream, addr, number);
382 return;
383 }
384 if (! chip->coeffs_current) {
385 snd_nm256_write_buffer(chip, coefficients, chip->all_coeff_buf,
386 NM_TOTAL_COEFF_COUNT * 4);
387 chip->coeffs_current = 1;
388 } else {
389 u32 base = chip->all_coeff_buf;
390 u32 offset = snd_nm256_get_start_offset(number);
391 u32 end_offset = offset + coefficient_sizes[number];
392 snd_nm256_writel(chip, addr, base + offset);
393 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
394 end_offset--;
395 snd_nm256_writel(chip, addr + 4, base + end_offset);
396 }
397}
398
399
400/* The actual rates supported by the card. */
401static unsigned int samplerates[8] = {
402 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
403};
10754f53 404static struct snd_pcm_hw_constraint_list constraints_rates = {
1da177e4
LT		 405 .count = ARRAY_SIZE(samplerates),
406 .list = samplerates,
407 .mask = 0,
408};
409
410/*
411 * return the index of the target rate
412 */
413static int
414snd_nm256_fixed_rate(unsigned int rate)
415{
416 unsigned int i;
417 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
418 if (rate == samplerates[i])
419 return i;
420 }
421 snd_BUG();
422 return 0;
423}
424
425/*
426 * set sample rate and format
427 */
428static void
10754f53
TI		 429snd_nm256_set_format(struct nm256 *chip, struct nm256_stream *s,
430 struct snd_pcm_substream *substream)
1da177e4 431{
10754f53 432 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 433 int rate_index = snd_nm256_fixed_rate(runtime->rate);
434 unsigned char ratebits = (rate_index << 4) & NM_RATE_MASK;
435
436 s->shift = 0;
437 if (snd_pcm_format_width(runtime->format) == 16) {
438 ratebits |= NM_RATE_BITS_16;
439 s->shift++;
440 }
441 if (runtime->channels > 1) {
442 ratebits |= NM_RATE_STEREO;
443 s->shift++;
444 }
445
446 runtime->rate = samplerates[rate_index];
447
448 switch (substream->stream) {
449 case SNDRV_PCM_STREAM_PLAYBACK:
450 snd_nm256_load_coefficient(chip, 0, rate_index); /* 0 = playback */
451 snd_nm256_writeb(chip,
452 NM_PLAYBACK_REG_OFFSET + NM_RATE_REG_OFFSET,
453 ratebits);
454 break;
455 case SNDRV_PCM_STREAM_CAPTURE:
456 snd_nm256_load_coefficient(chip, 1, rate_index); /* 1 = record */
457 snd_nm256_writeb(chip,
458 NM_RECORD_REG_OFFSET + NM_RATE_REG_OFFSET,
459 ratebits);
460 break;
461 }
462}
463
1204de32 464/* acquire interrupt */
10754f53 465static int snd_nm256_acquire_irq(struct nm256 *chip)
1204de32 466{
62932df8 467 mutex_lock(&chip->irq_mutex);
1204de32 468 if (chip->irq < 0) {
437a5a46 469 if (request_irq(chip->pci->irq, chip->interrupt, IRQF_SHARED,
934c2b6d 470 KBUILD_MODNAME, chip)) {
a3fe03f4
TI		 471 dev_err(chip->card->dev,
472 "unable to grab IRQ %d\n", chip->pci->irq);
62932df8 473 mutex_unlock(&chip->irq_mutex);
1204de32
TI		 474 return -EBUSY;
475 }
476 chip->irq = chip->pci->irq;
477 }
478 chip->irq_acks++;
62932df8 479 mutex_unlock(&chip->irq_mutex);
1204de32
TI		 480 return 0;
481}
482
483/* release interrupt */
10754f53 484static void snd_nm256_release_irq(struct nm256 *chip)
1204de32 485{
62932df8 486 mutex_lock(&chip->irq_mutex);
1204de32
TI		 487 if (chip->irq_acks > 0)
488 chip->irq_acks--;
489 if (chip->irq_acks == 0 && chip->irq >= 0) {
10754f53 490 free_irq(chip->irq, chip);
1204de32
TI		 491 chip->irq = -1;
492 }
62932df8 493 mutex_unlock(&chip->irq_mutex);
1204de32
TI		 494}
495
1da177e4
LT		 496/*
497 * start / stop
498 */
499
500/* update the watermark (current period) */
10754f53 501static void snd_nm256_pcm_mark(struct nm256 *chip, struct nm256_stream *s, int reg)
1da177e4
LT		 502{
503 s->cur_period++;
504 s->cur_period %= s->periods;
505 snd_nm256_writel(chip, reg, s->buf + s->cur_period * s->period_size);
506}
507
508#define snd_nm256_playback_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_PBUFFER_WMARK)
509#define snd_nm256_capture_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_RBUFFER_WMARK)
510
511static void
10754f53
TI		 512snd_nm256_playback_start(struct nm256 *chip, struct nm256_stream *s,
513 struct snd_pcm_substream *substream)
1da177e4
LT		 514{
515 /* program buffer pointers */
516 snd_nm256_writel(chip, NM_PBUFFER_START, s->buf);
517 snd_nm256_writel(chip, NM_PBUFFER_END, s->buf + s->dma_size - (1 << s->shift));
518 snd_nm256_writel(chip, NM_PBUFFER_CURRP, s->buf);
519 snd_nm256_playback_mark(chip, s);
520
521 /* Enable playback engine and interrupts. */
522 snd_nm256_writeb(chip, NM_PLAYBACK_ENABLE_REG,
523 NM_PLAYBACK_ENABLE_FLAG | NM_PLAYBACK_FREERUN);
524 /* Enable both channels. */
525 snd_nm256_writew(chip, NM_AUDIO_MUTE_REG, 0x0);
526}
527
528static void
10754f53
TI		 529snd_nm256_capture_start(struct nm256 *chip, struct nm256_stream *s,
530 struct snd_pcm_substream *substream)
1da177e4
LT		 531{
532 /* program buffer pointers */
533 snd_nm256_writel(chip, NM_RBUFFER_START, s->buf);
534 snd_nm256_writel(chip, NM_RBUFFER_END, s->buf + s->dma_size);
535 snd_nm256_writel(chip, NM_RBUFFER_CURRP, s->buf);
536 snd_nm256_capture_mark(chip, s);
537
538 /* Enable playback engine and interrupts. */
539 snd_nm256_writeb(chip, NM_RECORD_ENABLE_REG,
540 NM_RECORD_ENABLE_FLAG | NM_RECORD_FREERUN);
541}
542
543/* Stop the play engine. */
544static void
10754f53 545snd_nm256_playback_stop(struct nm256 *chip)
1da177e4
LT		 546{
547 /* Shut off sound from both channels. */
548 snd_nm256_writew(chip, NM_AUDIO_MUTE_REG,
549 NM_AUDIO_MUTE_LEFT | NM_AUDIO_MUTE_RIGHT);
550 /* Disable play engine. */
551 snd_nm256_writeb(chip, NM_PLAYBACK_ENABLE_REG, 0);
552}
553
554static void
10754f53 555snd_nm256_capture_stop(struct nm256 *chip)
1da177e4
LT		 556{
557 /* Disable recording engine. */
558 snd_nm256_writeb(chip, NM_RECORD_ENABLE_REG, 0);
559}
560
561static int
10754f53 562snd_nm256_playback_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 563{
10754f53
TI		 564 struct nm256 *chip = snd_pcm_substream_chip(substream);
565 struct nm256_stream *s = substream->runtime->private_data;
1da177e4
LT		 566 int err = 0;
567
da3cec35
TI		 568 if (snd_BUG_ON(!s))
569 return -ENXIO;
1da177e4
LT		 570
571 spin_lock(&chip->reg_lock);
572 switch (cmd) {
1da177e4 573 case SNDRV_PCM_TRIGGER_RESUME:
1204de32
TI		 574 s->suspended = 0;
575 /* fallthru */
576 case SNDRV_PCM_TRIGGER_START:
1da177e4
LT		 577 if (! s->running) {
578 snd_nm256_playback_start(chip, s, substream);
579 s->running = 1;
580 }
581 break;
1da177e4 582 case SNDRV_PCM_TRIGGER_SUSPEND:
1204de32
TI		 583 s->suspended = 1;
584 /* fallthru */
585 case SNDRV_PCM_TRIGGER_STOP:
1da177e4
LT		 586 if (s->running) {
587 snd_nm256_playback_stop(chip);
588 s->running = 0;
589 }
590 break;
591 default:
592 err = -EINVAL;
593 break;
594 }
595 spin_unlock(&chip->reg_lock);
596 return err;
597}
598
599static int
10754f53 600snd_nm256_capture_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 601{
10754f53
TI		 602 struct nm256 *chip = snd_pcm_substream_chip(substream);
603 struct nm256_stream *s = substream->runtime->private_data;
1da177e4
LT		 604 int err = 0;
605
da3cec35
TI		 606 if (snd_BUG_ON(!s))
607 return -ENXIO;
1da177e4
LT		 608
609 spin_lock(&chip->reg_lock);
610 switch (cmd) {
611 case SNDRV_PCM_TRIGGER_START:
612 case SNDRV_PCM_TRIGGER_RESUME:
613 if (! s->running) {
614 snd_nm256_capture_start(chip, s, substream);
615 s->running = 1;
616 }
617 break;
618 case SNDRV_PCM_TRIGGER_STOP:
619 case SNDRV_PCM_TRIGGER_SUSPEND:
620 if (s->running) {
621 snd_nm256_capture_stop(chip);
622 s->running = 0;
623 }
624 break;
625 default:
626 err = -EINVAL;
627 break;
628 }
629 spin_unlock(&chip->reg_lock);
630 return err;
631}
632
633
634/*
635 * prepare playback/capture channel
636 */
10754f53 637static int snd_nm256_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4 638{
10754f53
TI		 639 struct nm256 *chip = snd_pcm_substream_chip(substream);
640 struct snd_pcm_runtime *runtime = substream->runtime;
641 struct nm256_stream *s = runtime->private_data;
1da177e4 642
da3cec35
TI		 643 if (snd_BUG_ON(!s))
644 return -ENXIO;
1da177e4
LT		 645 s->dma_size = frames_to_bytes(runtime, substream->runtime->buffer_size);
646 s->period_size = frames_to_bytes(runtime, substream->runtime->period_size);
647 s->periods = substream->runtime->periods;
648 s->cur_period = 0;
649
650 spin_lock_irq(&chip->reg_lock);
651 s->running = 0;
652 snd_nm256_set_format(chip, s, substream);
653 spin_unlock_irq(&chip->reg_lock);
654
655 return 0;
656}
657
658
659/*
660 * get the current pointer
661 */
662static snd_pcm_uframes_t
10754f53 663snd_nm256_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 664{
10754f53
TI		 665 struct nm256 *chip = snd_pcm_substream_chip(substream);
666 struct nm256_stream *s = substream->runtime->private_data;
1da177e4
LT		 667 unsigned long curp;
668
da3cec35
TI		 669 if (snd_BUG_ON(!s))
670 return 0;
1da177e4
LT		 671 curp = snd_nm256_readl(chip, NM_PBUFFER_CURRP) - (unsigned long)s->buf;
672 curp %= s->dma_size;
673 return bytes_to_frames(substream->runtime, curp);
674}
675
676static snd_pcm_uframes_t
10754f53 677snd_nm256_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 678{
10754f53
TI		 679 struct nm256 *chip = snd_pcm_substream_chip(substream);
680 struct nm256_stream *s = substream->runtime->private_data;
1da177e4
LT		 681 unsigned long curp;
682
da3cec35
TI		 683 if (snd_BUG_ON(!s))
684 return 0;
1da177e4
LT		 685 curp = snd_nm256_readl(chip, NM_RBUFFER_CURRP) - (unsigned long)s->buf;
686 curp %= s->dma_size;
687 return bytes_to_frames(substream->runtime, curp);
688}
689
690/* Remapped I/O space can be accessible as pointer on i386 */
691/* This might be changed in the future */
692#ifndef __i386__
693/*
694 * silence / copy for playback
695 */
696static int
10754f53 697snd_nm256_playback_silence(struct snd_pcm_substream *substream,
1da177e4
LT		 698 int channel, /* not used (interleaved data) */
699 snd_pcm_uframes_t pos,
700 snd_pcm_uframes_t count)
701{
10754f53
TI		 702 struct snd_pcm_runtime *runtime = substream->runtime;
703 struct nm256_stream *s = runtime->private_data;
1da177e4
LT		 704 count = frames_to_bytes(runtime, count);
705 pos = frames_to_bytes(runtime, pos);
706 memset_io(s->bufptr + pos, 0, count);
707 return 0;
708}
709
710static int
10754f53 711snd_nm256_playback_copy(struct snd_pcm_substream *substream,
1da177e4
LT		 712 int channel, /* not used (interleaved data) */
713 snd_pcm_uframes_t pos,
714 void __user *src,
715 snd_pcm_uframes_t count)
716{
10754f53
TI		 717 struct snd_pcm_runtime *runtime = substream->runtime;
718 struct nm256_stream *s = runtime->private_data;
1da177e4
LT		 719 count = frames_to_bytes(runtime, count);
720 pos = frames_to_bytes(runtime, pos);
721 if (copy_from_user_toio(s->bufptr + pos, src, count))
722 return -EFAULT;
723 return 0;
724}
725
726/*
727 * copy to user
728 */
729static int
10754f53 730snd_nm256_capture_copy(struct snd_pcm_substream *substream,
1da177e4
LT		 731 int channel, /* not used (interleaved data) */
732 snd_pcm_uframes_t pos,
733 void __user *dst,
734 snd_pcm_uframes_t count)
735{
10754f53
TI		 736 struct snd_pcm_runtime *runtime = substream->runtime;
737 struct nm256_stream *s = runtime->private_data;
1da177e4
LT		 738 count = frames_to_bytes(runtime, count);
739 pos = frames_to_bytes(runtime, pos);
740 if (copy_to_user_fromio(dst, s->bufptr + pos, count))
741 return -EFAULT;
742 return 0;
743}
744
745#endif /* !__i386__ */
746
747
748/*
749 * update playback/capture watermarks
750 */
751
752/* spinlock held! */
753static void
10754f53 754snd_nm256_playback_update(struct nm256 *chip)
1da177e4 755{
10754f53 756 struct nm256_stream *s;
1da177e4
LT		 757
758 s = &chip->streams[SNDRV_PCM_STREAM_PLAYBACK];
759 if (s->running && s->substream) {
760 spin_unlock(&chip->reg_lock);
761 snd_pcm_period_elapsed(s->substream);
762 spin_lock(&chip->reg_lock);
763 snd_nm256_playback_mark(chip, s);
764 }
765}
766
767/* spinlock held! */
768static void
10754f53 769snd_nm256_capture_update(struct nm256 *chip)
1da177e4 770{
10754f53 771 struct nm256_stream *s;
1da177e4
LT		 772
773 s = &chip->streams[SNDRV_PCM_STREAM_CAPTURE];
774 if (s->running && s->substream) {
775 spin_unlock(&chip->reg_lock);
776 snd_pcm_period_elapsed(s->substream);
777 spin_lock(&chip->reg_lock);
778 snd_nm256_capture_mark(chip, s);
779 }
780}
781
782/*
783 * hardware info
784 */
10754f53 785static struct snd_pcm_hardware snd_nm256_playback =
1da177e4
LT		 786{
787 .info = SNDRV_PCM_INFO_MMAP_IOMEM |SNDRV_PCM_INFO_MMAP_VALID |
788 SNDRV_PCM_INFO_INTERLEAVED |
789 /*SNDRV_PCM_INFO_PAUSE |*/
790 SNDRV_PCM_INFO_RESUME,
791 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
792 .rates = SNDRV_PCM_RATE_KNOT/*24k*/ | SNDRV_PCM_RATE_8000_48000,
793 .rate_min = 8000,
794 .rate_max = 48000,
795 .channels_min = 1,
796 .channels_max = 2,
797 .periods_min = 2,
798 .periods_max = 1024,
799 .buffer_bytes_max = 128 * 1024,
800 .period_bytes_min = 256,
801 .period_bytes_max = 128 * 1024,
802};
803
10754f53 804static struct snd_pcm_hardware snd_nm256_capture =
1da177e4
LT		 805{
806 .info = SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID |
807 SNDRV_PCM_INFO_INTERLEAVED |
808 /*SNDRV_PCM_INFO_PAUSE |*/
809 SNDRV_PCM_INFO_RESUME,
810 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
811 .rates = SNDRV_PCM_RATE_KNOT/*24k*/ | SNDRV_PCM_RATE_8000_48000,
812 .rate_min = 8000,
813 .rate_max = 48000,
814 .channels_min = 1,
815 .channels_max = 2,
816 .periods_min = 2,
817 .periods_max = 1024,
818 .buffer_bytes_max = 128 * 1024,
819 .period_bytes_min = 256,
820 .period_bytes_max = 128 * 1024,
821};
822
823
824/* set dma transfer size */
10754f53
TI		 825static int snd_nm256_pcm_hw_params(struct snd_pcm_substream *substream,
826 struct snd_pcm_hw_params *hw_params)
1da177e4
LT		 827{
828 /* area and addr are already set and unchanged */
829 substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
830 return 0;
831}
832
833/*
834 * open
835 */
10754f53
TI		 836static void snd_nm256_setup_stream(struct nm256 *chip, struct nm256_stream *s,
837 struct snd_pcm_substream *substream,
838 struct snd_pcm_hardware *hw_ptr)
1da177e4 839{
10754f53 840 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 841
842 s->running = 0;
843 runtime->hw = *hw_ptr;
844 runtime->hw.buffer_bytes_max = s->bufsize;
845 runtime->hw.period_bytes_max = s->bufsize / 2;
4d23359b 846 runtime->dma_area = (void __force *) s->bufptr;
1da177e4
LT		 847 runtime->dma_addr = s->bufptr_addr;
848 runtime->dma_bytes = s->bufsize;
849 runtime->private_data = s;
850 s->substream = substream;
851
1da177e4
LT		 852 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
853 &constraints_rates);
854}
855
856static int
10754f53 857snd_nm256_playback_open(struct snd_pcm_substream *substream)
1da177e4 858{
10754f53 859 struct nm256 *chip = snd_pcm_substream_chip(substream);
1da177e4 860
1204de32
TI		 861 if (snd_nm256_acquire_irq(chip) < 0)
862 return -EBUSY;
1da177e4
LT		 863 snd_nm256_setup_stream(chip, &chip->streams[SNDRV_PCM_STREAM_PLAYBACK],
864 substream, &snd_nm256_playback);
865 return 0;
866}
867
868static int
10754f53 869snd_nm256_capture_open(struct snd_pcm_substream *substream)
1da177e4 870{
10754f53 871 struct nm256 *chip = snd_pcm_substream_chip(substream);
1da177e4 872
1204de32
TI		 873 if (snd_nm256_acquire_irq(chip) < 0)
874 return -EBUSY;
1da177e4
LT		 875 snd_nm256_setup_stream(chip, &chip->streams[SNDRV_PCM_STREAM_CAPTURE],
876 substream, &snd_nm256_capture);
877 return 0;
878}
879
880/*
881 * close - we don't have to do special..
882 */
883static int
10754f53 884snd_nm256_playback_close(struct snd_pcm_substream *substream)
1da177e4 885{
10754f53 886 struct nm256 *chip = snd_pcm_substream_chip(substream);
1204de32
TI		 887
888 snd_nm256_release_irq(chip);
1da177e4
LT		 889 return 0;
890}
891
892
893static int
10754f53 894snd_nm256_capture_close(struct snd_pcm_substream *substream)
1da177e4 895{
10754f53 896 struct nm256 *chip = snd_pcm_substream_chip(substream);
1204de32
TI		 897
898 snd_nm256_release_irq(chip);
1da177e4
LT		 899 return 0;
900}
901
902/*
903 * create a pcm instance
904 */
10754f53 905static struct snd_pcm_ops snd_nm256_playback_ops = {
1da177e4
LT		 906 .open = snd_nm256_playback_open,
907 .close = snd_nm256_playback_close,
908 .ioctl = snd_pcm_lib_ioctl,
909 .hw_params = snd_nm256_pcm_hw_params,
910 .prepare = snd_nm256_pcm_prepare,
911 .trigger = snd_nm256_playback_trigger,
912 .pointer = snd_nm256_playback_pointer,
913#ifndef __i386__
914 .copy = snd_nm256_playback_copy,
915 .silence = snd_nm256_playback_silence,
916#endif
917 .mmap = snd_pcm_lib_mmap_iomem,
918};
919
10754f53 920static struct snd_pcm_ops snd_nm256_capture_ops = {
1da177e4
LT		 921 .open = snd_nm256_capture_open,
922 .close = snd_nm256_capture_close,
923 .ioctl = snd_pcm_lib_ioctl,
924 .hw_params = snd_nm256_pcm_hw_params,
925 .prepare = snd_nm256_pcm_prepare,
926 .trigger = snd_nm256_capture_trigger,
927 .pointer = snd_nm256_capture_pointer,
928#ifndef __i386__
929 .copy = snd_nm256_capture_copy,
930#endif
931 .mmap = snd_pcm_lib_mmap_iomem,
932};
933
e23e7a14 934static int
10754f53 935snd_nm256_pcm(struct nm256 *chip, int device)
1da177e4 936{
10754f53 937 struct snd_pcm *pcm;
1da177e4
LT		 938 int i, err;
939
940 for (i = 0; i < 2; i++) {
10754f53 941 struct nm256_stream *s = &chip->streams[i];
1da177e4
LT		 942 s->bufptr = chip->buffer + (s->buf - chip->buffer_start);
943 s->bufptr_addr = chip->buffer_addr + (s->buf - chip->buffer_start);
944 }
945
946 err = snd_pcm_new(chip->card, chip->card->driver, device,
947 1, 1, &pcm);
948 if (err < 0)
949 return err;
950
951 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_nm256_playback_ops);
952 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_nm256_capture_ops);
953
954 pcm->private_data = chip;
955 pcm->info_flags = 0;
956 chip->pcm = pcm;
957
958 return 0;
959}
960
961
962/*
963 * Initialize the hardware.
964 */
965static void
10754f53 966snd_nm256_init_chip(struct nm256 *chip)
1da177e4 967{
1da177e4
LT		 968 /* Reset everything. */
969 snd_nm256_writeb(chip, 0x0, 0x11);
970 snd_nm256_writew(chip, 0x214, 0);
971 /* stop sounds.. */
972 //snd_nm256_playback_stop(chip);
973 //snd_nm256_capture_stop(chip);
1da177e4
LT		 974}
975
976
1204de32 977static irqreturn_t
10754f53 978snd_nm256_intr_check(struct nm256 *chip)
1da177e4
LT		 979{
980 if (chip->badintrcount++ > 1000) {
981 /*
982 * I'm not sure if the best thing is to stop the card from
983 * playing or just release the interrupt (after all, we're in
984 * a bad situation, so doing fancy stuff may not be such a good
985 * idea).
986 *
987 * I worry about the card engine continuing to play noise
988 * over and over, however--that could become a very
989 * obnoxious problem. And we know that when this usually
990 * happens things are fairly safe, it just means the user's
991 * inserted a PCMCIA card and someone's spamming us with IRQ 9s.
992 */
993 if (chip->streams[SNDRV_PCM_STREAM_PLAYBACK].running)
994 snd_nm256_playback_stop(chip);
995 if (chip->streams[SNDRV_PCM_STREAM_CAPTURE].running)
996 snd_nm256_capture_stop(chip);
997 chip->badintrcount = 0;
1204de32 998 return IRQ_HANDLED;
1da177e4 999 }
1204de32 1000 return IRQ_NONE;
1da177e4
LT		 1001}
1002
1003/*
1004 * Handle a potential interrupt for the device referred to by DEV_ID.
1005 *
1006 * I don't like the cut-n-paste job here either between the two routines,
1007 * but there are sufficient differences between the two interrupt handlers
1008 * that parameterizing it isn't all that great either. (Could use a macro,
1009 * I suppose...yucky bleah.)
1010 */
1011
1012static irqreturn_t
7d12e780 1013snd_nm256_interrupt(int irq, void *dev_id)
1da177e4 1014{
10754f53 1015 struct nm256 *chip = dev_id;
1da177e4
LT		 1016 u16 status;
1017 u8 cbyte;
1018
1019 status = snd_nm256_readw(chip, NM_INT_REG);
1020
1021 /* Not ours. */
1204de32
TI		 1022 if (status == 0)
1023 return snd_nm256_intr_check(chip);
1da177e4
LT		 1024
1025 chip->badintrcount = 0;
1026
1027 /* Rather boring; check for individual interrupts and process them. */
1028
1029 spin_lock(&chip->reg_lock);
1030 if (status & NM_PLAYBACK_INT) {
1031 status &= ~NM_PLAYBACK_INT;
1032 NM_ACK_INT(chip, NM_PLAYBACK_INT);
1033 snd_nm256_playback_update(chip);
1034 }
1035
1036 if (status & NM_RECORD_INT) {
1037 status &= ~NM_RECORD_INT;
1038 NM_ACK_INT(chip, NM_RECORD_INT);
1039 snd_nm256_capture_update(chip);
1040 }
1041
1042 if (status & NM_MISC_INT_1) {
1043 status &= ~NM_MISC_INT_1;
1044 NM_ACK_INT(chip, NM_MISC_INT_1);
a3fe03f4 1045 dev_dbg(chip->card->dev, "NM256: Got misc interrupt #1\n");
1da177e4
LT		 1046 snd_nm256_writew(chip, NM_INT_REG, 0x8000);
1047 cbyte = snd_nm256_readb(chip, 0x400);
1048 snd_nm256_writeb(chip, 0x400, cbyte | 2);
1049 }
1050
1051 if (status & NM_MISC_INT_2) {
1052 status &= ~NM_MISC_INT_2;
1053 NM_ACK_INT(chip, NM_MISC_INT_2);
a3fe03f4 1054 dev_dbg(chip->card->dev, "NM256: Got misc interrupt #2\n");
1da177e4
LT		 1055 cbyte = snd_nm256_readb(chip, 0x400);
1056 snd_nm256_writeb(chip, 0x400, cbyte & ~2);
1057 }
1058
1059 /* Unknown interrupt. */
1060 if (status) {
a3fe03f4
TI		 1061 dev_dbg(chip->card->dev,
1062 "NM256: Fire in the hole! Unknown status 0x%x\n",
1da177e4
LT		 1063 status);
1064 /* Pray. */
1065 NM_ACK_INT(chip, status);
1066 }
1067
1068 spin_unlock(&chip->reg_lock);
1069 return IRQ_HANDLED;
1070}
1071
1072/*
1073 * Handle a potential interrupt for the device referred to by DEV_ID.
1074 * This handler is for the 256ZX, and is very similar to the non-ZX
1075 * routine.
1076 */
1077
1078static irqreturn_t
7d12e780 1079snd_nm256_interrupt_zx(int irq, void *dev_id)
1da177e4 1080{
10754f53 1081 struct nm256 *chip = dev_id;
1da177e4
LT		 1082 u32 status;
1083 u8 cbyte;
1084
1085 status = snd_nm256_readl(chip, NM_INT_REG);
1086
1087 /* Not ours. */
1204de32
TI		 1088 if (status == 0)
1089 return snd_nm256_intr_check(chip);
1da177e4
LT		 1090
1091 chip->badintrcount = 0;
1092
1093 /* Rather boring; check for individual interrupts and process them. */
1094
1095 spin_lock(&chip->reg_lock);
1096 if (status & NM2_PLAYBACK_INT) {
1097 status &= ~NM2_PLAYBACK_INT;
1098 NM2_ACK_INT(chip, NM2_PLAYBACK_INT);
1099 snd_nm256_playback_update(chip);
1100 }
1101
1102 if (status & NM2_RECORD_INT) {
1103 status &= ~NM2_RECORD_INT;
1104 NM2_ACK_INT(chip, NM2_RECORD_INT);
1105 snd_nm256_capture_update(chip);
1106 }
1107
1108 if (status & NM2_MISC_INT_1) {
1109 status &= ~NM2_MISC_INT_1;
1110 NM2_ACK_INT(chip, NM2_MISC_INT_1);
a3fe03f4 1111 dev_dbg(chip->card->dev, "NM256: Got misc interrupt #1\n");
1da177e4
LT		 1112 cbyte = snd_nm256_readb(chip, 0x400);
1113 snd_nm256_writeb(chip, 0x400, cbyte | 2);
1114 }
1115
1116 if (status & NM2_MISC_INT_2) {
1117 status &= ~NM2_MISC_INT_2;
1118 NM2_ACK_INT(chip, NM2_MISC_INT_2);
a3fe03f4 1119 dev_dbg(chip->card->dev, "NM256: Got misc interrupt #2\n");
1da177e4
LT		 1120 cbyte = snd_nm256_readb(chip, 0x400);
1121 snd_nm256_writeb(chip, 0x400, cbyte & ~2);
1122 }
1123
1124 /* Unknown interrupt. */
1125 if (status) {
a3fe03f4
TI		 1126 dev_dbg(chip->card->dev,
1127 "NM256: Fire in the hole! Unknown status 0x%x\n",
1da177e4
LT		 1128 status);
1129 /* Pray. */
1130 NM2_ACK_INT(chip, status);
1131 }
1132
1133 spin_unlock(&chip->reg_lock);
1134 return IRQ_HANDLED;
1135}
1136
1137/*
1138 * AC97 interface
1139 */
1140
1141/*
1142 * Waits for the mixer to become ready to be written; returns a zero value
1143 * if it timed out.
1144 */
1145static int
10754f53 1146snd_nm256_ac97_ready(struct nm256 *chip)
1da177e4
LT		 1147{
1148 int timeout = 10;
1149 u32 testaddr;
1150 u16 testb;
1151
1152 testaddr = chip->mixer_status_offset;
1153 testb = chip->mixer_status_mask;
1154
1155 /*
1156 * Loop around waiting for the mixer to become ready.
1157 */
1158 while (timeout-- > 0) {
1159 if ((snd_nm256_readw(chip, testaddr) & testb) == 0)
1160 return 1;
1161 udelay(100);
1162 }
1163 return 0;
1164}
1165
a23446c0
FS		 1166/*
1167 * Initial register values to be written to the AC97 mixer.
1168 * While most of these are identical to the reset values, we do this
1169 * so that we have most of the register contents cached--this avoids
1170 * reading from the mixer directly (which seems to be problematic,
1171 * probably due to ignorance).
1172 */
1173
1174struct initialValues {
1175 unsigned short reg;
1176 unsigned short value;
1177};
1178
1179static struct initialValues nm256_ac97_init_val[] =
1180{
1181 { AC97_MASTER, 0x8000 },
1182 { AC97_HEADPHONE, 0x8000 },
1183 { AC97_MASTER_MONO, 0x8000 },
1184 { AC97_PC_BEEP, 0x8000 },
1185 { AC97_PHONE, 0x8008 },
1186 { AC97_MIC, 0x8000 },
1187 { AC97_LINE, 0x8808 },
1188 { AC97_CD, 0x8808 },
1189 { AC97_VIDEO, 0x8808 },
1190 { AC97_AUX, 0x8808 },
1191 { AC97_PCM, 0x8808 },
1192 { AC97_REC_SEL, 0x0000 },
1193 { AC97_REC_GAIN, 0x0B0B },
1194 { AC97_GENERAL_PURPOSE, 0x0000 },
1195 { AC97_3D_CONTROL, 0x8000 },
1196 { AC97_VENDOR_ID1, 0x8384 },
1197 { AC97_VENDOR_ID2, 0x7609 },
1198};
1199
1200static int nm256_ac97_idx(unsigned short reg)
1201{
1202 int i;
1203 for (i = 0; i < ARRAY_SIZE(nm256_ac97_init_val); i++)
1204 if (nm256_ac97_init_val[i].reg == reg)
1205 return i;
1206 return -1;
1207}
1208
1da177e4 1209/*
a23446c0
FS		 1210 * some nm256 easily crash when reading from mixer registers
1211 * thus we're treating it as a write-only mixer and cache the
1212 * written values
1da177e4
LT		 1213 */
1214static unsigned short
10754f53 1215snd_nm256_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1da177e4 1216{
10754f53 1217 struct nm256 *chip = ac97->private_data;
a23446c0 1218 int idx = nm256_ac97_idx(reg);
1da177e4 1219
a23446c0 1220 if (idx < 0)
1da177e4 1221 return 0;
a23446c0 1222 return chip->ac97_regs[idx];
1da177e4
LT		 1223}
1224
1225/*
1226 */
1227static void
10754f53 1228snd_nm256_ac97_write(struct snd_ac97 *ac97,
1da177e4
LT		 1229 unsigned short reg, unsigned short val)
1230{
10754f53 1231 struct nm256 *chip = ac97->private_data;
1da177e4 1232 int tries = 2;
a23446c0 1233 int idx = nm256_ac97_idx(reg);
1da177e4
LT		 1234 u32 base;
1235
a23446c0
FS		 1236 if (idx < 0)
1237 return;
1238
1da177e4
LT		 1239 base = chip->mixer_base;
1240
1241 snd_nm256_ac97_ready(chip);
1242
1243 /* Wait for the write to take, too. */
1244 while (tries-- > 0) {
1245 snd_nm256_writew(chip, base + reg, val);
1246 msleep(1); /* a little delay here seems better.. */
a23446c0
FS		 1247 if (snd_nm256_ac97_ready(chip)) {
1248 /* successful write: set cache */
1249 chip->ac97_regs[idx] = val;
1da177e4 1250 return;
a23446c0 1251 }
1da177e4 1252 }
a3fe03f4 1253 dev_dbg(chip->card->dev, "nm256: ac97 codec not ready..\n");
1da177e4
LT		 1254}
1255
a23446c0
FS		 1256/* static resolution table */
1257static struct snd_ac97_res_table nm256_res_table[] = {
1258 { AC97_MASTER, 0x1f1f },
1259 { AC97_HEADPHONE, 0x1f1f },
1260 { AC97_MASTER_MONO, 0x001f },
1261 { AC97_PC_BEEP, 0x001f },
1262 { AC97_PHONE, 0x001f },
1263 { AC97_MIC, 0x001f },
1264 { AC97_LINE, 0x1f1f },
1265 { AC97_CD, 0x1f1f },
1266 { AC97_VIDEO, 0x1f1f },
1267 { AC97_AUX, 0x1f1f },
1268 { AC97_PCM, 0x1f1f },
1269 { AC97_REC_GAIN, 0x0f0f },
1270 { } /* terminator */
1271};
1272
1da177e4
LT		 1273/* initialize the ac97 into a known state */
1274static void
10754f53 1275snd_nm256_ac97_reset(struct snd_ac97 *ac97)
1da177e4 1276{
10754f53 1277 struct nm256 *chip = ac97->private_data;
1da177e4
LT		 1278
1279 /* Reset the mixer. 'Tis magic! */
1280 snd_nm256_writeb(chip, 0x6c0, 1);
1281 if (! chip->reset_workaround) {
1282 /* Dell latitude LS will lock up by this */
1283 snd_nm256_writeb(chip, 0x6cc, 0x87);
1284 }
47530cf4
JL		 1285 if (! chip->reset_workaround_2) {
1286 /* Dell latitude CSx will lock up by this */
1287 snd_nm256_writeb(chip, 0x6cc, 0x80);
1288 snd_nm256_writeb(chip, 0x6cc, 0x0);
1289 }
a23446c0
FS		 1290 if (! chip->in_resume) {
1291 int i;
1292 for (i = 0; i < ARRAY_SIZE(nm256_ac97_init_val); i++) {
1293 /* preload the cache, so as to avoid even a single
1294 * read of the mixer regs
1295 */
1296 snd_nm256_ac97_write(ac97, nm256_ac97_init_val[i].reg,
1297 nm256_ac97_init_val[i].value);
1298 }
1299 }
1da177e4
LT		 1300}
1301
1302/* create an ac97 mixer interface */
e23e7a14 1303static int
10754f53 1304snd_nm256_mixer(struct nm256 *chip)
1da177e4 1305{
10754f53
TI		 1306 struct snd_ac97_bus *pbus;
1307 struct snd_ac97_template ac97;
a23446c0 1308 int err;
10754f53 1309 static struct snd_ac97_bus_ops ops = {
1da177e4
LT		 1310 .reset = snd_nm256_ac97_reset,
1311 .write = snd_nm256_ac97_write,
1312 .read = snd_nm256_ac97_read,
1313 };
a23446c0 1314
80ca9a70
MM		 1315 chip->ac97_regs = kcalloc(ARRAY_SIZE(nm256_ac97_init_val),
1316 sizeof(short), GFP_KERNEL);
a23446c0
FS		 1317 if (! chip->ac97_regs)
1318 return -ENOMEM;
1da177e4
LT		 1319
1320 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
1321 return err;
1322
1323 memset(&ac97, 0, sizeof(ac97));
1324 ac97.scaps = AC97_SCAP_AUDIO; /* we support audio! */
1da177e4 1325 ac97.private_data = chip;
a23446c0 1326 ac97.res_table = nm256_res_table;
1204de32 1327 pbus->no_vra = 1;
1da177e4
LT		 1328 err = snd_ac97_mixer(pbus, &ac97, &chip->ac97);
1329 if (err < 0)
1330 return err;
1331 if (! (chip->ac97->id & (0xf0000000))) {
1332 /* looks like an invalid id */
1333 sprintf(chip->card->mixername, "%s AC97", chip->card->driver);
1334 }
1335 return 0;
1336}
1337
1338/*
1339 * See if the signature left by the NM256 BIOS is intact; if so, we use
1340 * the associated address as the end of our audio buffer in the video
1341 * RAM.
1342 */
1343
e23e7a14 1344static int
10754f53 1345snd_nm256_peek_for_sig(struct nm256 *chip)
1da177e4
LT		 1346{
1347 /* The signature is located 1K below the end of video RAM. */
1348 void __iomem *temp;
1349 /* Default buffer end is 5120 bytes below the top of RAM. */
1350 unsigned long pointer_found = chip->buffer_end - 0x1400;
1351 u32 sig;
1352
1353 temp = ioremap_nocache(chip->buffer_addr + chip->buffer_end - 0x400, 16);
1354 if (temp == NULL) {
a3fe03f4
TI		 1355 dev_err(chip->card->dev,
1356 "Unable to scan for card signature in video RAM\n");
1da177e4
LT		 1357 return -EBUSY;
1358 }
1359
1360 sig = readl(temp);
1361 if ((sig & NM_SIG_MASK) == NM_SIGNATURE) {
1362 u32 pointer = readl(temp + 4);
1363
1364 /*
1365 * If it's obviously invalid, don't use it
1366 */
1367 if (pointer == 0xffffffff ||
1368 pointer < chip->buffer_size ||
1369 pointer > chip->buffer_end) {
a3fe03f4
TI		 1370 dev_err(chip->card->dev,
1371 "invalid signature found: 0x%x\n", pointer);
1da177e4
LT		 1372 iounmap(temp);
1373 return -ENODEV;
1374 } else {
1375 pointer_found = pointer;
a3fe03f4
TI		 1376 dev_info(chip->card->dev,
1377 "found card signature in video RAM: 0x%x\n",
10754f53 1378 pointer);
1da177e4
LT		 1379 }
1380 }
1381
1382 iounmap(temp);
1383 chip->buffer_end = pointer_found;
1384
1385 return 0;
1386}
1387
c7561cd8 1388#ifdef CONFIG_PM_SLEEP
1da177e4
LT		 1389/*
1390 * APM event handler, so the card is properly reinitialized after a power
1391 * event.
1392 */
68cb2b55 1393static int nm256_suspend(struct device *dev)
1da177e4 1394{
68cb2b55
TI		 1395 struct pci_dev *pci = to_pci_dev(dev);
1396 struct snd_card *card = dev_get_drvdata(dev);
3fcf7d2c 1397 struct nm256 *chip = card->private_data;
1da177e4 1398
3fcf7d2c 1399 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1da177e4
LT		 1400 snd_pcm_suspend_all(chip->pcm);
1401 snd_ac97_suspend(chip->ac97);
1402 chip->coeffs_current = 0;
3fcf7d2c
TI		 1403 pci_disable_device(pci);
1404 pci_save_state(pci);
68cb2b55 1405 pci_set_power_state(pci, PCI_D3hot);
1da177e4
LT		 1406 return 0;
1407}
1408
68cb2b55 1409static int nm256_resume(struct device *dev)
1da177e4 1410{
68cb2b55
TI		 1411 struct pci_dev *pci = to_pci_dev(dev);
1412 struct snd_card *card = dev_get_drvdata(dev);
3fcf7d2c 1413 struct nm256 *chip = card->private_data;
1204de32 1414 int i;
1da177e4
LT		 1415
1416 /* Perform a full reset on the hardware */
a23446c0 1417 chip->in_resume = 1;
30b35399
TI		 1418
1419 pci_set_power_state(pci, PCI_D0);
3fcf7d2c 1420 pci_restore_state(pci);
30b35399 1421 if (pci_enable_device(pci) < 0) {
a3fe03f4 1422 dev_err(dev, "pci_enable_device failed, disabling device\n");
30b35399
TI		 1423 snd_card_disconnect(card);
1424 return -EIO;
1425 }
1426 pci_set_master(pci);
1427
1da177e4
LT		 1428 snd_nm256_init_chip(chip);
1429
1430 /* restore ac97 */
1431 snd_ac97_resume(chip->ac97);
1432
1204de32 1433 for (i = 0; i < 2; i++) {
10754f53 1434 struct nm256_stream *s = &chip->streams[i];
1204de32
TI		 1435 if (s->substream && s->suspended) {
1436 spin_lock_irq(&chip->reg_lock);
1437 snd_nm256_set_format(chip, s, s->substream);
1438 spin_unlock_irq(&chip->reg_lock);
1439 }
1440 }
1441
3fcf7d2c 1442 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
a23446c0 1443 chip->in_resume = 0;
1da177e4
LT		 1444 return 0;
1445}
68cb2b55
TI		 1446
1447static SIMPLE_DEV_PM_OPS(nm256_pm, nm256_suspend, nm256_resume);
1448#define NM256_PM_OPS &nm256_pm
1449#else
1450#define NM256_PM_OPS NULL
c7561cd8 1451#endif /* CONFIG_PM_SLEEP */
1da177e4 1452
10754f53 1453static int snd_nm256_free(struct nm256 *chip)
1da177e4
LT		 1454{
1455 if (chip->streams[SNDRV_PCM_STREAM_PLAYBACK].running)
1456 snd_nm256_playback_stop(chip);
1457 if (chip->streams[SNDRV_PCM_STREAM_CAPTURE].running)
1458 snd_nm256_capture_stop(chip);
1459
1460 if (chip->irq >= 0)
ebf029da 1461 free_irq(chip->irq, chip);
1da177e4
LT		 1462
1463 if (chip->cport)
1464 iounmap(chip->cport);
1465 if (chip->buffer)
1466 iounmap(chip->buffer);
b1d5776d
TI		 1467 release_and_free_resource(chip->res_cport);
1468 release_and_free_resource(chip->res_buffer);
1da177e4
LT		 1469
1470 pci_disable_device(chip->pci);
a23446c0 1471 kfree(chip->ac97_regs);
1da177e4
LT		 1472 kfree(chip);
1473 return 0;
1474}
1475
10754f53 1476static int snd_nm256_dev_free(struct snd_device *device)
1da177e4 1477{
10754f53 1478 struct nm256 *chip = device->device_data;
1da177e4
LT		 1479 return snd_nm256_free(chip);
1480}
1481
e23e7a14 1482static int
10754f53
TI		 1483snd_nm256_create(struct snd_card *card, struct pci_dev *pci,
1484 struct nm256 **chip_ret)
1da177e4 1485{
10754f53 1486 struct nm256 *chip;
1da177e4 1487 int err, pval;
10754f53 1488 static struct snd_device_ops ops = {
1da177e4
LT		 1489 .dev_free = snd_nm256_dev_free,
1490 };
1491 u32 addr;
1492
1493 *chip_ret = NULL;
1494
1495 if ((err = pci_enable_device(pci)) < 0)
1496 return err;
1497
e560d8d8 1498 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 1499 if (chip == NULL) {
1500 pci_disable_device(pci);
1501 return -ENOMEM;
1502 }
1503
1504 chip->card = card;
1505 chip->pci = pci;
3f05f868 1506 chip->use_cache = use_cache;
1da177e4
LT		 1507 spin_lock_init(&chip->reg_lock);
1508 chip->irq = -1;
62932df8 1509 mutex_init(&chip->irq_mutex);
1da177e4 1510
3f05f868
TI		 1511 /* store buffer sizes in bytes */
1512 chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize = playback_bufsize * 1024;
1513 chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize = capture_bufsize * 1024;
1da177e4
LT		 1514
1515 /*
1516 * The NM256 has two memory ports. The first port is nothing
1517 * more than a chunk of video RAM, which is used as the I/O ring
1518 * buffer. The second port has the actual juicy stuff (like the
1519 * mixer and the playback engine control registers).
1520 */
1521
1522 chip->buffer_addr = pci_resource_start(pci, 0);
1523 chip->cport_addr = pci_resource_start(pci, 1);
1524
1525 /* Init the memory port info. */
1526 /* remap control port (#2) */
1527 chip->res_cport = request_mem_region(chip->cport_addr, NM_PORT2_SIZE,
1528 card->driver);
1529 if (chip->res_cport == NULL) {
a3fe03f4 1530 dev_err(card->dev, "memory region 0x%lx (size 0x%x) busy\n",
1da177e4
LT		 1531 chip->cport_addr, NM_PORT2_SIZE);
1532 err = -EBUSY;
1533 goto __error;
1534 }
1535 chip->cport = ioremap_nocache(chip->cport_addr, NM_PORT2_SIZE);
1536 if (chip->cport == NULL) {
a3fe03f4
TI		 1537 dev_err(card->dev, "unable to map control port %lx\n",
1538 chip->cport_addr);
1da177e4
LT		 1539 err = -ENOMEM;
1540 goto __error;
1541 }
1542
1543 if (!strcmp(card->driver, "NM256AV")) {
1544 /* Ok, try to see if this is a non-AC97 version of the hardware. */
1545 pval = snd_nm256_readw(chip, NM_MIXER_PRESENCE);
1546 if ((pval & NM_PRESENCE_MASK) != NM_PRESENCE_VALUE) {
3f05f868 1547 if (! force_ac97) {
a3fe03f4
TI		 1548 dev_err(card->dev,
1549 "no ac97 is found!\n");
1550 dev_err(card->dev,
1551 "force the driver to load by passing in the module parameter\n");
1552 dev_err(card->dev,
1553 " force_ac97=1\n");
1554 dev_err(card->dev,
1555 "or try sb16, opl3sa2, or cs423x drivers instead.\n");
1da177e4
LT		 1556 err = -ENXIO;
1557 goto __error;
1558 }
1559 }
1560 chip->buffer_end = 2560 * 1024;
1561 chip->interrupt = snd_nm256_interrupt;
1562 chip->mixer_status_offset = NM_MIXER_STATUS_OFFSET;
1563 chip->mixer_status_mask = NM_MIXER_READY_MASK;
1564 } else {
1565 /* Not sure if there is any relevant detect for the ZX or not. */
1566 if (snd_nm256_readb(chip, 0xa0b) != 0)
1567 chip->buffer_end = 6144 * 1024;
1568 else
1569 chip->buffer_end = 4096 * 1024;
1570
1571 chip->interrupt = snd_nm256_interrupt_zx;
1572 chip->mixer_status_offset = NM2_MIXER_STATUS_OFFSET;
1573 chip->mixer_status_mask = NM2_MIXER_READY_MASK;
1574 }
1575
10754f53
TI		 1576 chip->buffer_size = chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize +
1577 chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize;
1da177e4
LT		 1578 if (chip->use_cache)
1579 chip->buffer_size += NM_TOTAL_COEFF_COUNT * 4;
1580 else
1581 chip->buffer_size += NM_MAX_PLAYBACK_COEF_SIZE + NM_MAX_RECORD_COEF_SIZE;
1582
3f05f868
TI		 1583 if (buffer_top >= chip->buffer_size && buffer_top < chip->buffer_end)
1584 chip->buffer_end = buffer_top;
1da177e4
LT		 1585 else {
1586 /* get buffer end pointer from signature */
1587 if ((err = snd_nm256_peek_for_sig(chip)) < 0)
1588 goto __error;
1589 }
1590
1591 chip->buffer_start = chip->buffer_end - chip->buffer_size;
1592 chip->buffer_addr += chip->buffer_start;
1593
a3fe03f4 1594 dev_info(card->dev, "Mapping port 1 from 0x%x - 0x%x\n",
1da177e4
LT		 1595 chip->buffer_start, chip->buffer_end);
1596
1597 chip->res_buffer = request_mem_region(chip->buffer_addr,
1598 chip->buffer_size,
1599 card->driver);
1600 if (chip->res_buffer == NULL) {
a3fe03f4 1601 dev_err(card->dev, "buffer 0x%lx (size 0x%x) busy\n",
1da177e4
LT		 1602 chip->buffer_addr, chip->buffer_size);
1603 err = -EBUSY;
1604 goto __error;
1605 }
1606 chip->buffer = ioremap_nocache(chip->buffer_addr, chip->buffer_size);
1607 if (chip->buffer == NULL) {
1608 err = -ENOMEM;
a3fe03f4
TI		 1609 dev_err(card->dev, "unable to map ring buffer at %lx\n",
1610 chip->buffer_addr);
1da177e4
LT		 1611 goto __error;
1612 }
1613
1614 /* set offsets */
1615 addr = chip->buffer_start;
1616 chip->streams[SNDRV_PCM_STREAM_PLAYBACK].buf = addr;
1617 addr += chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize;
1618 chip->streams[SNDRV_PCM_STREAM_CAPTURE].buf = addr;
1619 addr += chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize;
1620 if (chip->use_cache) {
1621 chip->all_coeff_buf = addr;
1622 } else {
1623 chip->coeff_buf[SNDRV_PCM_STREAM_PLAYBACK] = addr;
1624 addr += NM_MAX_PLAYBACK_COEF_SIZE;
1625 chip->coeff_buf[SNDRV_PCM_STREAM_CAPTURE] = addr;
1626 }
1627
1da177e4
LT		 1628 /* Fixed setting. */
1629 chip->mixer_base = NM_MIXER_OFFSET;
1630
1631 chip->coeffs_current = 0;
1632
1633 snd_nm256_init_chip(chip);
1634
1635 // pci_set_master(pci); /* needed? */
1636
1da177e4
LT		 1637 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0)
1638 goto __error;
1639
1da177e4
LT		 1640 *chip_ret = chip;
1641 return 0;
1642
1643__error:
1644 snd_nm256_free(chip);
1645 return err;
1646}
1647
1648
47530cf4 1649enum { NM_BLACKLISTED, NM_RESET_WORKAROUND, NM_RESET_WORKAROUND_2 };
1da177e4 1650
e23e7a14 1651static struct snd_pci_quirk nm256_quirks[] = {
1da177e4 1652 /* HP omnibook 4150 has cs4232 codec internally */
e2b6d13b
TI		 1653 SND_PCI_QUIRK(0x103c, 0x0007, "HP omnibook 4150", NM_BLACKLISTED),
1654 /* Reset workarounds to avoid lock-ups */
1655 SND_PCI_QUIRK(0x104d, 0x8041, "Sony PCG-F305", NM_RESET_WORKAROUND),
1656 SND_PCI_QUIRK(0x1028, 0x0080, "Dell Latitude LS", NM_RESET_WORKAROUND),
1657 SND_PCI_QUIRK(0x1028, 0x0091, "Dell Latitude CSx", NM_RESET_WORKAROUND_2),
1da177e4
LT		 1658 { } /* terminator */
1659};
1660
1661
e23e7a14
BP		 1662static int snd_nm256_probe(struct pci_dev *pci,
1663 const struct pci_device_id *pci_id)
1da177e4 1664{
10754f53
TI		 1665 struct snd_card *card;
1666 struct nm256 *chip;
1da177e4 1667 int err;
e2b6d13b
TI		 1668 const struct snd_pci_quirk *q;
1669
1670 q = snd_pci_quirk_lookup(pci, nm256_quirks);
1671 if (q) {
a3fe03f4 1672 dev_dbg(&pci->dev, "Enabled quirk for %s.\n",
86b27237 1673 snd_pci_quirk_name(q));
e2b6d13b
TI		 1674 switch (q->value) {
1675 case NM_BLACKLISTED:
a3fe03f4
TI		 1676 dev_info(&pci->dev,
1677 "The device is blacklisted. Loading stopped\n");
e2b6d13b
TI		 1678 return -ENODEV;
1679 case NM_RESET_WORKAROUND_2:
1680 reset_workaround_2 = 1;
1681 /* Fall-through */
1682 case NM_RESET_WORKAROUND:
1683 reset_workaround = 1;
1684 break;
1da177e4
LT		 1685 }
1686 }
1687
60c5772b 1688 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
e58de7ba
TI		 1689 if (err < 0)
1690 return err;
1da177e4
LT		 1691
1692 switch (pci->device) {
1693 case PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO:
1694 strcpy(card->driver, "NM256AV");
1695 break;
1696 case PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO:
1697 strcpy(card->driver, "NM256ZX");
1698 break;
1699 case PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO:
1700 strcpy(card->driver, "NM256XL+");
1701 break;
1702 default:
a3fe03f4 1703 dev_err(&pci->dev, "invalid device id 0x%x\n", pci->device);
1da177e4
LT		 1704 snd_card_free(card);
1705 return -EINVAL;
1706 }
1707
8a3fb4d0 1708 if (vaio_hack)
3f05f868 1709 buffer_top = 0x25a800; /* this avoids conflicts with XFree86 server */
8a3fb4d0
TI		 1710
1711 if (playback_bufsize < 4)
1712 playback_bufsize = 4;
1713 if (playback_bufsize > 128)
1714 playback_bufsize = 128;
1715 if (capture_bufsize < 4)
1716 capture_bufsize = 4;
1717 if (capture_bufsize > 128)
1718 capture_bufsize = 128;
3f05f868 1719 if ((err = snd_nm256_create(card, pci, &chip)) < 0) {
1da177e4
LT		 1720 snd_card_free(card);
1721 return err;
1722 }
3fcf7d2c 1723 card->private_data = chip;
1da177e4 1724
8a3fb4d0 1725 if (reset_workaround) {
a3fe03f4 1726 dev_dbg(&pci->dev, "reset_workaround activated\n");
1da177e4
LT		 1727 chip->reset_workaround = 1;
1728 }
1729
8a3fb4d0 1730 if (reset_workaround_2) {
a3fe03f4 1731 dev_dbg(&pci->dev, "reset_workaround_2 activated\n");
47530cf4
JL		 1732 chip->reset_workaround_2 = 1;
1733 }
1734
1da177e4
LT		 1735 if ((err = snd_nm256_pcm(chip, 0)) < 0 ||
1736 (err = snd_nm256_mixer(chip)) < 0) {
1737 snd_card_free(card);
1738 return err;
1739 }
1740
1741 sprintf(card->shortname, "NeoMagic %s", card->driver);
1742 sprintf(card->longname, "%s at 0x%lx & 0x%lx, irq %d",
1743 card->shortname,
1744 chip->buffer_addr, chip->cport_addr, chip->irq);
1745
1746 if ((err = snd_card_register(card)) < 0) {
1747 snd_card_free(card);
1748 return err;
1749 }
1750
1751 pci_set_drvdata(pci, card);
1da177e4
LT		 1752 return 0;
1753}
1754
e23e7a14 1755static void snd_nm256_remove(struct pci_dev *pci)
1da177e4
LT		 1756{
1757 snd_card_free(pci_get_drvdata(pci));
1da177e4
LT		 1758}
1759
1760
e9f66d9b 1761static struct pci_driver nm256_driver = {
3733e424 1762 .name = KBUILD_MODNAME,
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LT		 1763 .id_table = snd_nm256_ids,
1764 .probe = snd_nm256_probe,
e23e7a14 1765 .remove = snd_nm256_remove,
68cb2b55
TI		 1766 .driver = {
1767 .pm = NM256_PM_OPS,
1768 },
1da177e4
LT		 1769};
1770
e9f66d9b 1771module_pci_driver(nm256_driver);
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