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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Driver for NeoMagic 256AV and 256ZX chipsets. | |
3 | * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de> | |
4 | * | |
5 | * Based on nm256_audio.c OSS driver in linux kernel. | |
6 | * The original author of OSS nm256 driver wishes to remain anonymous, | |
7 | * so I just put my acknoledgment to him/her here. | |
8 | * The original author's web page is found at | |
9 | * http://www.uglx.org/sony.html | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | */ | |
26 | ||
6cbbfe1c | 27 | #include <linux/io.h> |
1da177e4 LT |
28 | #include <linux/delay.h> |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/pci.h> | |
32 | #include <linux/slab.h> | |
65a77217 | 33 | #include <linux/module.h> |
62932df8 IM |
34 | #include <linux/mutex.h> |
35 | ||
1da177e4 LT |
36 | #include <sound/core.h> |
37 | #include <sound/info.h> | |
38 | #include <sound/control.h> | |
39 | #include <sound/pcm.h> | |
40 | #include <sound/ac97_codec.h> | |
41 | #include <sound/initval.h> | |
42 | ||
43 | #define CARD_NAME "NeoMagic 256AV/ZX" | |
44 | #define DRIVER_NAME "NM256" | |
45 | ||
46 | MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); | |
47 | MODULE_DESCRIPTION("NeoMagic NM256AV/ZX"); | |
48 | MODULE_LICENSE("GPL"); | |
49 | MODULE_SUPPORTED_DEVICE("{{NeoMagic,NM256AV}," | |
50 | "{NeoMagic,NM256ZX}}"); | |
51 | ||
52 | /* | |
53 | * some compile conditions. | |
54 | */ | |
55 | ||
8a3fb4d0 TI |
56 | static int index = SNDRV_DEFAULT_IDX1; /* Index */ |
57 | static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ | |
58 | static int playback_bufsize = 16; | |
59 | static int capture_bufsize = 16; | |
a67ff6a5 | 60 | static bool force_ac97; /* disabled as default */ |
8a3fb4d0 | 61 | static int buffer_top; /* not specified */ |
a67ff6a5 RR |
62 | static bool use_cache; /* disabled */ |
63 | static bool vaio_hack; /* disabled */ | |
64 | static bool reset_workaround; | |
65 | static bool reset_workaround_2; | |
8a3fb4d0 TI |
66 | |
67 | module_param(index, int, 0444); | |
1da177e4 | 68 | MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); |
8a3fb4d0 | 69 | module_param(id, charp, 0444); |
1da177e4 | 70 | MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); |
8a3fb4d0 | 71 | module_param(playback_bufsize, int, 0444); |
1da177e4 | 72 | MODULE_PARM_DESC(playback_bufsize, "DAC frame size in kB for " CARD_NAME " soundcard."); |
8a3fb4d0 | 73 | module_param(capture_bufsize, int, 0444); |
1da177e4 | 74 | MODULE_PARM_DESC(capture_bufsize, "ADC frame size in kB for " CARD_NAME " soundcard."); |
8a3fb4d0 | 75 | module_param(force_ac97, bool, 0444); |
1da177e4 | 76 | MODULE_PARM_DESC(force_ac97, "Force to use AC97 codec for " CARD_NAME " soundcard."); |
8a3fb4d0 | 77 | module_param(buffer_top, int, 0444); |
1da177e4 | 78 | MODULE_PARM_DESC(buffer_top, "Set the top address of audio buffer for " CARD_NAME " soundcard."); |
8a3fb4d0 | 79 | module_param(use_cache, bool, 0444); |
1da177e4 | 80 | MODULE_PARM_DESC(use_cache, "Enable the cache for coefficient table access."); |
8a3fb4d0 | 81 | module_param(vaio_hack, bool, 0444); |
1da177e4 | 82 | MODULE_PARM_DESC(vaio_hack, "Enable workaround for Sony VAIO notebooks."); |
8a3fb4d0 | 83 | module_param(reset_workaround, bool, 0444); |
1da177e4 | 84 | MODULE_PARM_DESC(reset_workaround, "Enable AC97 RESET workaround for some laptops."); |
8a3fb4d0 | 85 | module_param(reset_workaround_2, bool, 0444); |
47530cf4 | 86 | MODULE_PARM_DESC(reset_workaround_2, "Enable extended AC97 RESET workaround for some other laptops."); |
1da177e4 | 87 | |
8a3fb4d0 | 88 | /* just for backward compatibility */ |
a67ff6a5 | 89 | static bool enable; |
8a3fb4d0 TI |
90 | module_param(enable, bool, 0444); |
91 | ||
92 | ||
93 | ||
1da177e4 LT |
94 | /* |
95 | * hw definitions | |
96 | */ | |
97 | ||
98 | /* The BIOS signature. */ | |
99 | #define NM_SIGNATURE 0x4e4d0000 | |
100 | /* Signature mask. */ | |
101 | #define NM_SIG_MASK 0xffff0000 | |
102 | ||
103 | /* Size of the second memory area. */ | |
104 | #define NM_PORT2_SIZE 4096 | |
105 | ||
106 | /* The base offset of the mixer in the second memory area. */ | |
107 | #define NM_MIXER_OFFSET 0x600 | |
108 | ||
109 | /* The maximum size of a coefficient entry. */ | |
110 | #define NM_MAX_PLAYBACK_COEF_SIZE 0x5000 | |
111 | #define NM_MAX_RECORD_COEF_SIZE 0x1260 | |
112 | ||
113 | /* The interrupt register. */ | |
114 | #define NM_INT_REG 0xa04 | |
115 | /* And its bits. */ | |
116 | #define NM_PLAYBACK_INT 0x40 | |
117 | #define NM_RECORD_INT 0x100 | |
118 | #define NM_MISC_INT_1 0x4000 | |
119 | #define NM_MISC_INT_2 0x1 | |
120 | #define NM_ACK_INT(chip, X) snd_nm256_writew(chip, NM_INT_REG, (X) << 1) | |
121 | ||
122 | /* The AV's "mixer ready" status bit and location. */ | |
123 | #define NM_MIXER_STATUS_OFFSET 0xa04 | |
124 | #define NM_MIXER_READY_MASK 0x0800 | |
125 | #define NM_MIXER_PRESENCE 0xa06 | |
126 | #define NM_PRESENCE_MASK 0x0050 | |
127 | #define NM_PRESENCE_VALUE 0x0040 | |
128 | ||
129 | /* | |
130 | * For the ZX. It uses the same interrupt register, but it holds 32 | |
131 | * bits instead of 16. | |
132 | */ | |
133 | #define NM2_PLAYBACK_INT 0x10000 | |
134 | #define NM2_RECORD_INT 0x80000 | |
135 | #define NM2_MISC_INT_1 0x8 | |
136 | #define NM2_MISC_INT_2 0x2 | |
137 | #define NM2_ACK_INT(chip, X) snd_nm256_writel(chip, NM_INT_REG, (X)) | |
138 | ||
139 | /* The ZX's "mixer ready" status bit and location. */ | |
140 | #define NM2_MIXER_STATUS_OFFSET 0xa06 | |
141 | #define NM2_MIXER_READY_MASK 0x0800 | |
142 | ||
143 | /* The playback registers start from here. */ | |
144 | #define NM_PLAYBACK_REG_OFFSET 0x0 | |
145 | /* The record registers start from here. */ | |
146 | #define NM_RECORD_REG_OFFSET 0x200 | |
147 | ||
148 | /* The rate register is located 2 bytes from the start of the register area. */ | |
149 | #define NM_RATE_REG_OFFSET 2 | |
150 | ||
151 | /* Mono/stereo flag, number of bits on playback, and rate mask. */ | |
152 | #define NM_RATE_STEREO 1 | |
153 | #define NM_RATE_BITS_16 2 | |
154 | #define NM_RATE_MASK 0xf0 | |
155 | ||
156 | /* Playback enable register. */ | |
157 | #define NM_PLAYBACK_ENABLE_REG (NM_PLAYBACK_REG_OFFSET + 0x1) | |
158 | #define NM_PLAYBACK_ENABLE_FLAG 1 | |
159 | #define NM_PLAYBACK_ONESHOT 2 | |
160 | #define NM_PLAYBACK_FREERUN 4 | |
161 | ||
162 | /* Mutes the audio output. */ | |
163 | #define NM_AUDIO_MUTE_REG (NM_PLAYBACK_REG_OFFSET + 0x18) | |
164 | #define NM_AUDIO_MUTE_LEFT 0x8000 | |
165 | #define NM_AUDIO_MUTE_RIGHT 0x0080 | |
166 | ||
167 | /* Recording enable register. */ | |
168 | #define NM_RECORD_ENABLE_REG (NM_RECORD_REG_OFFSET + 0) | |
169 | #define NM_RECORD_ENABLE_FLAG 1 | |
170 | #define NM_RECORD_FREERUN 2 | |
171 | ||
172 | /* coefficient buffer pointer */ | |
173 | #define NM_COEFF_START_OFFSET 0x1c | |
174 | #define NM_COEFF_END_OFFSET 0x20 | |
175 | ||
176 | /* DMA buffer offsets */ | |
177 | #define NM_RBUFFER_START (NM_RECORD_REG_OFFSET + 0x4) | |
178 | #define NM_RBUFFER_END (NM_RECORD_REG_OFFSET + 0x10) | |
179 | #define NM_RBUFFER_WMARK (NM_RECORD_REG_OFFSET + 0xc) | |
180 | #define NM_RBUFFER_CURRP (NM_RECORD_REG_OFFSET + 0x8) | |
181 | ||
182 | #define NM_PBUFFER_START (NM_PLAYBACK_REG_OFFSET + 0x4) | |
183 | #define NM_PBUFFER_END (NM_PLAYBACK_REG_OFFSET + 0x14) | |
184 | #define NM_PBUFFER_WMARK (NM_PLAYBACK_REG_OFFSET + 0xc) | |
185 | #define NM_PBUFFER_CURRP (NM_PLAYBACK_REG_OFFSET + 0x8) | |
186 | ||
10754f53 | 187 | struct nm256_stream { |
1da177e4 | 188 | |
10754f53 TI |
189 | struct nm256 *chip; |
190 | struct snd_pcm_substream *substream; | |
1da177e4 | 191 | int running; |
1204de32 | 192 | int suspended; |
1da177e4 LT |
193 | |
194 | u32 buf; /* offset from chip->buffer */ | |
195 | int bufsize; /* buffer size in bytes */ | |
196 | void __iomem *bufptr; /* mapped pointer */ | |
197 | unsigned long bufptr_addr; /* physical address of the mapped pointer */ | |
198 | ||
199 | int dma_size; /* buffer size of the substream in bytes */ | |
200 | int period_size; /* period size in bytes */ | |
201 | int periods; /* # of periods */ | |
202 | int shift; /* bit shifts */ | |
203 | int cur_period; /* current period # */ | |
204 | ||
205 | }; | |
206 | ||
10754f53 | 207 | struct nm256 { |
1da177e4 | 208 | |
10754f53 | 209 | struct snd_card *card; |
1da177e4 LT |
210 | |
211 | void __iomem *cport; /* control port */ | |
212 | struct resource *res_cport; /* its resource */ | |
213 | unsigned long cport_addr; /* physical address */ | |
214 | ||
215 | void __iomem *buffer; /* buffer */ | |
216 | struct resource *res_buffer; /* its resource */ | |
217 | unsigned long buffer_addr; /* buffer phyiscal address */ | |
218 | ||
219 | u32 buffer_start; /* start offset from pci resource 0 */ | |
220 | u32 buffer_end; /* end offset */ | |
221 | u32 buffer_size; /* total buffer size */ | |
222 | ||
223 | u32 all_coeff_buf; /* coefficient buffer */ | |
224 | u32 coeff_buf[2]; /* coefficient buffer for each stream */ | |
225 | ||
226 | unsigned int coeffs_current: 1; /* coeff. table is loaded? */ | |
227 | unsigned int use_cache: 1; /* use one big coef. table */ | |
228 | unsigned int reset_workaround: 1; /* Workaround for some laptops to avoid freeze */ | |
47530cf4 | 229 | unsigned int reset_workaround_2: 1; /* Extended workaround for some other laptops to avoid freeze */ |
a23446c0 | 230 | unsigned int in_resume: 1; |
1da177e4 LT |
231 | |
232 | int mixer_base; /* register offset of ac97 mixer */ | |
233 | int mixer_status_offset; /* offset of mixer status reg. */ | |
234 | int mixer_status_mask; /* bit mask to test the mixer status */ | |
235 | ||
236 | int irq; | |
1204de32 | 237 | int irq_acks; |
7d12e780 | 238 | irq_handler_t interrupt; |
1da177e4 | 239 | int badintrcount; /* counter to check bogus interrupts */ |
62932df8 | 240 | struct mutex irq_mutex; |
1da177e4 | 241 | |
10754f53 | 242 | struct nm256_stream streams[2]; |
1da177e4 | 243 | |
10754f53 | 244 | struct snd_ac97 *ac97; |
a23446c0 | 245 | unsigned short *ac97_regs; /* register caches, only for valid regs */ |
1da177e4 | 246 | |
10754f53 | 247 | struct snd_pcm *pcm; |
1da177e4 LT |
248 | |
249 | struct pci_dev *pci; | |
250 | ||
251 | spinlock_t reg_lock; | |
252 | ||
253 | }; | |
254 | ||
255 | ||
256 | /* | |
257 | * include coefficient table | |
258 | */ | |
259 | #include "nm256_coef.c" | |
260 | ||
261 | ||
262 | /* | |
263 | * PCI ids | |
264 | */ | |
9baa3c34 | 265 | static const struct pci_device_id snd_nm256_ids[] = { |
28d27aae JP |
266 | {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO), 0}, |
267 | {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO), 0}, | |
268 | {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO), 0}, | |
1da177e4 LT |
269 | {0,}, |
270 | }; | |
271 | ||
272 | MODULE_DEVICE_TABLE(pci, snd_nm256_ids); | |
273 | ||
274 | ||
275 | /* | |
276 | * lowlvel stuffs | |
277 | */ | |
278 | ||
77933d72 | 279 | static inline u8 |
10754f53 | 280 | snd_nm256_readb(struct nm256 *chip, int offset) |
1da177e4 LT |
281 | { |
282 | return readb(chip->cport + offset); | |
283 | } | |
284 | ||
77933d72 | 285 | static inline u16 |
10754f53 | 286 | snd_nm256_readw(struct nm256 *chip, int offset) |
1da177e4 LT |
287 | { |
288 | return readw(chip->cport + offset); | |
289 | } | |
290 | ||
77933d72 | 291 | static inline u32 |
10754f53 | 292 | snd_nm256_readl(struct nm256 *chip, int offset) |
1da177e4 LT |
293 | { |
294 | return readl(chip->cport + offset); | |
295 | } | |
296 | ||
77933d72 | 297 | static inline void |
10754f53 | 298 | snd_nm256_writeb(struct nm256 *chip, int offset, u8 val) |
1da177e4 LT |
299 | { |
300 | writeb(val, chip->cport + offset); | |
301 | } | |
302 | ||
77933d72 | 303 | static inline void |
10754f53 | 304 | snd_nm256_writew(struct nm256 *chip, int offset, u16 val) |
1da177e4 LT |
305 | { |
306 | writew(val, chip->cport + offset); | |
307 | } | |
308 | ||
77933d72 | 309 | static inline void |
10754f53 | 310 | snd_nm256_writel(struct nm256 *chip, int offset, u32 val) |
1da177e4 LT |
311 | { |
312 | writel(val, chip->cport + offset); | |
313 | } | |
314 | ||
77933d72 | 315 | static inline void |
10754f53 | 316 | snd_nm256_write_buffer(struct nm256 *chip, void *src, int offset, int size) |
1da177e4 LT |
317 | { |
318 | offset -= chip->buffer_start; | |
99b359ba | 319 | #ifdef CONFIG_SND_DEBUG |
1da177e4 | 320 | if (offset < 0 || offset >= chip->buffer_size) { |
a3fe03f4 TI |
321 | dev_err(chip->card->dev, |
322 | "write_buffer invalid offset = %d size = %d\n", | |
10754f53 | 323 | offset, size); |
1da177e4 LT |
324 | return; |
325 | } | |
326 | #endif | |
327 | memcpy_toio(chip->buffer + offset, src, size); | |
328 | } | |
329 | ||
330 | /* | |
331 | * coefficient handlers -- what a magic! | |
332 | */ | |
333 | ||
334 | static u16 | |
335 | snd_nm256_get_start_offset(int which) | |
336 | { | |
337 | u16 offset = 0; | |
338 | while (which-- > 0) | |
339 | offset += coefficient_sizes[which]; | |
340 | return offset; | |
341 | } | |
342 | ||
343 | static void | |
10754f53 | 344 | snd_nm256_load_one_coefficient(struct nm256 *chip, int stream, u32 port, int which) |
1da177e4 LT |
345 | { |
346 | u32 coeff_buf = chip->coeff_buf[stream]; | |
347 | u16 offset = snd_nm256_get_start_offset(which); | |
348 | u16 size = coefficient_sizes[which]; | |
349 | ||
350 | snd_nm256_write_buffer(chip, coefficients + offset, coeff_buf, size); | |
351 | snd_nm256_writel(chip, port, coeff_buf); | |
352 | /* ??? Record seems to behave differently than playback. */ | |
353 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) | |
354 | size--; | |
355 | snd_nm256_writel(chip, port + 4, coeff_buf + size); | |
356 | } | |
357 | ||
358 | static void | |
10754f53 | 359 | snd_nm256_load_coefficient(struct nm256 *chip, int stream, int number) |
1da177e4 LT |
360 | { |
361 | /* The enable register for the specified engine. */ | |
10754f53 TI |
362 | u32 poffset = (stream == SNDRV_PCM_STREAM_CAPTURE ? |
363 | NM_RECORD_ENABLE_REG : NM_PLAYBACK_ENABLE_REG); | |
1da177e4 LT |
364 | u32 addr = NM_COEFF_START_OFFSET; |
365 | ||
10754f53 TI |
366 | addr += (stream == SNDRV_PCM_STREAM_CAPTURE ? |
367 | NM_RECORD_REG_OFFSET : NM_PLAYBACK_REG_OFFSET); | |
1da177e4 LT |
368 | |
369 | if (snd_nm256_readb(chip, poffset) & 1) { | |
a3fe03f4 TI |
370 | dev_dbg(chip->card->dev, |
371 | "NM256: Engine was enabled while loading coefficients!\n"); | |
1da177e4 LT |
372 | return; |
373 | } | |
374 | ||
375 | /* The recording engine uses coefficient values 8-15. */ | |
376 | number &= 7; | |
377 | if (stream == SNDRV_PCM_STREAM_CAPTURE) | |
378 | number += 8; | |
379 | ||
380 | if (! chip->use_cache) { | |
381 | snd_nm256_load_one_coefficient(chip, stream, addr, number); | |
382 | return; | |
383 | } | |
384 | if (! chip->coeffs_current) { | |
385 | snd_nm256_write_buffer(chip, coefficients, chip->all_coeff_buf, | |
386 | NM_TOTAL_COEFF_COUNT * 4); | |
387 | chip->coeffs_current = 1; | |
388 | } else { | |
389 | u32 base = chip->all_coeff_buf; | |
390 | u32 offset = snd_nm256_get_start_offset(number); | |
391 | u32 end_offset = offset + coefficient_sizes[number]; | |
392 | snd_nm256_writel(chip, addr, base + offset); | |
393 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) | |
394 | end_offset--; | |
395 | snd_nm256_writel(chip, addr + 4, base + end_offset); | |
396 | } | |
397 | } | |
398 | ||
399 | ||
400 | /* The actual rates supported by the card. */ | |
3f2bdc45 | 401 | static const unsigned int samplerates[8] = { |
1da177e4 LT |
402 | 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000, |
403 | }; | |
3f2bdc45 | 404 | static const struct snd_pcm_hw_constraint_list constraints_rates = { |
1da177e4 LT |
405 | .count = ARRAY_SIZE(samplerates), |
406 | .list = samplerates, | |
407 | .mask = 0, | |
408 | }; | |
409 | ||
410 | /* | |
411 | * return the index of the target rate | |
412 | */ | |
413 | static int | |
414 | snd_nm256_fixed_rate(unsigned int rate) | |
415 | { | |
416 | unsigned int i; | |
417 | for (i = 0; i < ARRAY_SIZE(samplerates); i++) { | |
418 | if (rate == samplerates[i]) | |
419 | return i; | |
420 | } | |
421 | snd_BUG(); | |
422 | return 0; | |
423 | } | |
424 | ||
425 | /* | |
426 | * set sample rate and format | |
427 | */ | |
428 | static void | |
10754f53 TI |
429 | snd_nm256_set_format(struct nm256 *chip, struct nm256_stream *s, |
430 | struct snd_pcm_substream *substream) | |
1da177e4 | 431 | { |
10754f53 | 432 | struct snd_pcm_runtime *runtime = substream->runtime; |
1da177e4 LT |
433 | int rate_index = snd_nm256_fixed_rate(runtime->rate); |
434 | unsigned char ratebits = (rate_index << 4) & NM_RATE_MASK; | |
435 | ||
436 | s->shift = 0; | |
437 | if (snd_pcm_format_width(runtime->format) == 16) { | |
438 | ratebits |= NM_RATE_BITS_16; | |
439 | s->shift++; | |
440 | } | |
441 | if (runtime->channels > 1) { | |
442 | ratebits |= NM_RATE_STEREO; | |
443 | s->shift++; | |
444 | } | |
445 | ||
446 | runtime->rate = samplerates[rate_index]; | |
447 | ||
448 | switch (substream->stream) { | |
449 | case SNDRV_PCM_STREAM_PLAYBACK: | |
450 | snd_nm256_load_coefficient(chip, 0, rate_index); /* 0 = playback */ | |
451 | snd_nm256_writeb(chip, | |
452 | NM_PLAYBACK_REG_OFFSET + NM_RATE_REG_OFFSET, | |
453 | ratebits); | |
454 | break; | |
455 | case SNDRV_PCM_STREAM_CAPTURE: | |
456 | snd_nm256_load_coefficient(chip, 1, rate_index); /* 1 = record */ | |
457 | snd_nm256_writeb(chip, | |
458 | NM_RECORD_REG_OFFSET + NM_RATE_REG_OFFSET, | |
459 | ratebits); | |
460 | break; | |
461 | } | |
462 | } | |
463 | ||
1204de32 | 464 | /* acquire interrupt */ |
10754f53 | 465 | static int snd_nm256_acquire_irq(struct nm256 *chip) |
1204de32 | 466 | { |
62932df8 | 467 | mutex_lock(&chip->irq_mutex); |
1204de32 | 468 | if (chip->irq < 0) { |
437a5a46 | 469 | if (request_irq(chip->pci->irq, chip->interrupt, IRQF_SHARED, |
934c2b6d | 470 | KBUILD_MODNAME, chip)) { |
a3fe03f4 TI |
471 | dev_err(chip->card->dev, |
472 | "unable to grab IRQ %d\n", chip->pci->irq); | |
62932df8 | 473 | mutex_unlock(&chip->irq_mutex); |
1204de32 TI |
474 | return -EBUSY; |
475 | } | |
476 | chip->irq = chip->pci->irq; | |
477 | } | |
478 | chip->irq_acks++; | |
62932df8 | 479 | mutex_unlock(&chip->irq_mutex); |
1204de32 TI |
480 | return 0; |
481 | } | |
482 | ||
483 | /* release interrupt */ | |
10754f53 | 484 | static void snd_nm256_release_irq(struct nm256 *chip) |
1204de32 | 485 | { |
62932df8 | 486 | mutex_lock(&chip->irq_mutex); |
1204de32 TI |
487 | if (chip->irq_acks > 0) |
488 | chip->irq_acks--; | |
489 | if (chip->irq_acks == 0 && chip->irq >= 0) { | |
10754f53 | 490 | free_irq(chip->irq, chip); |
1204de32 TI |
491 | chip->irq = -1; |
492 | } | |
62932df8 | 493 | mutex_unlock(&chip->irq_mutex); |
1204de32 TI |
494 | } |
495 | ||
1da177e4 LT |
496 | /* |
497 | * start / stop | |
498 | */ | |
499 | ||
500 | /* update the watermark (current period) */ | |
10754f53 | 501 | static void snd_nm256_pcm_mark(struct nm256 *chip, struct nm256_stream *s, int reg) |
1da177e4 LT |
502 | { |
503 | s->cur_period++; | |
504 | s->cur_period %= s->periods; | |
505 | snd_nm256_writel(chip, reg, s->buf + s->cur_period * s->period_size); | |
506 | } | |
507 | ||
508 | #define snd_nm256_playback_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_PBUFFER_WMARK) | |
509 | #define snd_nm256_capture_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_RBUFFER_WMARK) | |
510 | ||
511 | static void | |
10754f53 TI |
512 | snd_nm256_playback_start(struct nm256 *chip, struct nm256_stream *s, |
513 | struct snd_pcm_substream *substream) | |
1da177e4 LT |
514 | { |
515 | /* program buffer pointers */ | |
516 | snd_nm256_writel(chip, NM_PBUFFER_START, s->buf); | |
517 | snd_nm256_writel(chip, NM_PBUFFER_END, s->buf + s->dma_size - (1 << s->shift)); | |
518 | snd_nm256_writel(chip, NM_PBUFFER_CURRP, s->buf); | |
519 | snd_nm256_playback_mark(chip, s); | |
520 | ||
521 | /* Enable playback engine and interrupts. */ | |
522 | snd_nm256_writeb(chip, NM_PLAYBACK_ENABLE_REG, | |
523 | NM_PLAYBACK_ENABLE_FLAG | NM_PLAYBACK_FREERUN); | |
524 | /* Enable both channels. */ | |
525 | snd_nm256_writew(chip, NM_AUDIO_MUTE_REG, 0x0); | |
526 | } | |
527 | ||
528 | static void | |
10754f53 TI |
529 | snd_nm256_capture_start(struct nm256 *chip, struct nm256_stream *s, |
530 | struct snd_pcm_substream *substream) | |
1da177e4 LT |
531 | { |
532 | /* program buffer pointers */ | |
533 | snd_nm256_writel(chip, NM_RBUFFER_START, s->buf); | |
534 | snd_nm256_writel(chip, NM_RBUFFER_END, s->buf + s->dma_size); | |
535 | snd_nm256_writel(chip, NM_RBUFFER_CURRP, s->buf); | |
536 | snd_nm256_capture_mark(chip, s); | |
537 | ||
538 | /* Enable playback engine and interrupts. */ | |
539 | snd_nm256_writeb(chip, NM_RECORD_ENABLE_REG, | |
540 | NM_RECORD_ENABLE_FLAG | NM_RECORD_FREERUN); | |
541 | } | |
542 | ||
543 | /* Stop the play engine. */ | |
544 | static void | |
10754f53 | 545 | snd_nm256_playback_stop(struct nm256 *chip) |
1da177e4 LT |
546 | { |
547 | /* Shut off sound from both channels. */ | |
548 | snd_nm256_writew(chip, NM_AUDIO_MUTE_REG, | |
549 | NM_AUDIO_MUTE_LEFT | NM_AUDIO_MUTE_RIGHT); | |
550 | /* Disable play engine. */ | |
551 | snd_nm256_writeb(chip, NM_PLAYBACK_ENABLE_REG, 0); | |
552 | } | |
553 | ||
554 | static void | |
10754f53 | 555 | snd_nm256_capture_stop(struct nm256 *chip) |
1da177e4 LT |
556 | { |
557 | /* Disable recording engine. */ | |
558 | snd_nm256_writeb(chip, NM_RECORD_ENABLE_REG, 0); | |
559 | } | |
560 | ||
561 | static int | |
10754f53 | 562 | snd_nm256_playback_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 | 563 | { |
10754f53 TI |
564 | struct nm256 *chip = snd_pcm_substream_chip(substream); |
565 | struct nm256_stream *s = substream->runtime->private_data; | |
1da177e4 LT |
566 | int err = 0; |
567 | ||
da3cec35 TI |
568 | if (snd_BUG_ON(!s)) |
569 | return -ENXIO; | |
1da177e4 LT |
570 | |
571 | spin_lock(&chip->reg_lock); | |
572 | switch (cmd) { | |
1da177e4 | 573 | case SNDRV_PCM_TRIGGER_RESUME: |
1204de32 TI |
574 | s->suspended = 0; |
575 | /* fallthru */ | |
576 | case SNDRV_PCM_TRIGGER_START: | |
1da177e4 LT |
577 | if (! s->running) { |
578 | snd_nm256_playback_start(chip, s, substream); | |
579 | s->running = 1; | |
580 | } | |
581 | break; | |
1da177e4 | 582 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1204de32 TI |
583 | s->suspended = 1; |
584 | /* fallthru */ | |
585 | case SNDRV_PCM_TRIGGER_STOP: | |
1da177e4 LT |
586 | if (s->running) { |
587 | snd_nm256_playback_stop(chip); | |
588 | s->running = 0; | |
589 | } | |
590 | break; | |
591 | default: | |
592 | err = -EINVAL; | |
593 | break; | |
594 | } | |
595 | spin_unlock(&chip->reg_lock); | |
596 | return err; | |
597 | } | |
598 | ||
599 | static int | |
10754f53 | 600 | snd_nm256_capture_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 | 601 | { |
10754f53 TI |
602 | struct nm256 *chip = snd_pcm_substream_chip(substream); |
603 | struct nm256_stream *s = substream->runtime->private_data; | |
1da177e4 LT |
604 | int err = 0; |
605 | ||
da3cec35 TI |
606 | if (snd_BUG_ON(!s)) |
607 | return -ENXIO; | |
1da177e4 LT |
608 | |
609 | spin_lock(&chip->reg_lock); | |
610 | switch (cmd) { | |
611 | case SNDRV_PCM_TRIGGER_START: | |
612 | case SNDRV_PCM_TRIGGER_RESUME: | |
613 | if (! s->running) { | |
614 | snd_nm256_capture_start(chip, s, substream); | |
615 | s->running = 1; | |
616 | } | |
617 | break; | |
618 | case SNDRV_PCM_TRIGGER_STOP: | |
619 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
620 | if (s->running) { | |
621 | snd_nm256_capture_stop(chip); | |
622 | s->running = 0; | |
623 | } | |
624 | break; | |
625 | default: | |
626 | err = -EINVAL; | |
627 | break; | |
628 | } | |
629 | spin_unlock(&chip->reg_lock); | |
630 | return err; | |
631 | } | |
632 | ||
633 | ||
634 | /* | |
635 | * prepare playback/capture channel | |
636 | */ | |
10754f53 | 637 | static int snd_nm256_pcm_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 638 | { |
10754f53 TI |
639 | struct nm256 *chip = snd_pcm_substream_chip(substream); |
640 | struct snd_pcm_runtime *runtime = substream->runtime; | |
641 | struct nm256_stream *s = runtime->private_data; | |
1da177e4 | 642 | |
da3cec35 TI |
643 | if (snd_BUG_ON(!s)) |
644 | return -ENXIO; | |
1da177e4 LT |
645 | s->dma_size = frames_to_bytes(runtime, substream->runtime->buffer_size); |
646 | s->period_size = frames_to_bytes(runtime, substream->runtime->period_size); | |
647 | s->periods = substream->runtime->periods; | |
648 | s->cur_period = 0; | |
649 | ||
650 | spin_lock_irq(&chip->reg_lock); | |
651 | s->running = 0; | |
652 | snd_nm256_set_format(chip, s, substream); | |
653 | spin_unlock_irq(&chip->reg_lock); | |
654 | ||
655 | return 0; | |
656 | } | |
657 | ||
658 | ||
659 | /* | |
660 | * get the current pointer | |
661 | */ | |
662 | static snd_pcm_uframes_t | |
10754f53 | 663 | snd_nm256_playback_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 664 | { |
10754f53 TI |
665 | struct nm256 *chip = snd_pcm_substream_chip(substream); |
666 | struct nm256_stream *s = substream->runtime->private_data; | |
1da177e4 LT |
667 | unsigned long curp; |
668 | ||
da3cec35 TI |
669 | if (snd_BUG_ON(!s)) |
670 | return 0; | |
1da177e4 LT |
671 | curp = snd_nm256_readl(chip, NM_PBUFFER_CURRP) - (unsigned long)s->buf; |
672 | curp %= s->dma_size; | |
673 | return bytes_to_frames(substream->runtime, curp); | |
674 | } | |
675 | ||
676 | static snd_pcm_uframes_t | |
10754f53 | 677 | snd_nm256_capture_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 678 | { |
10754f53 TI |
679 | struct nm256 *chip = snd_pcm_substream_chip(substream); |
680 | struct nm256_stream *s = substream->runtime->private_data; | |
1da177e4 LT |
681 | unsigned long curp; |
682 | ||
da3cec35 TI |
683 | if (snd_BUG_ON(!s)) |
684 | return 0; | |
1da177e4 LT |
685 | curp = snd_nm256_readl(chip, NM_RBUFFER_CURRP) - (unsigned long)s->buf; |
686 | curp %= s->dma_size; | |
687 | return bytes_to_frames(substream->runtime, curp); | |
688 | } | |
689 | ||
690 | /* Remapped I/O space can be accessible as pointer on i386 */ | |
691 | /* This might be changed in the future */ | |
692 | #ifndef __i386__ | |
693 | /* | |
694 | * silence / copy for playback | |
695 | */ | |
696 | static int | |
10754f53 | 697 | snd_nm256_playback_silence(struct snd_pcm_substream *substream, |
21de5673 | 698 | int channel, unsigned long pos, unsigned long count) |
1da177e4 | 699 | { |
10754f53 TI |
700 | struct snd_pcm_runtime *runtime = substream->runtime; |
701 | struct nm256_stream *s = runtime->private_data; | |
21de5673 | 702 | |
1da177e4 LT |
703 | memset_io(s->bufptr + pos, 0, count); |
704 | return 0; | |
705 | } | |
706 | ||
707 | static int | |
10754f53 | 708 | snd_nm256_playback_copy(struct snd_pcm_substream *substream, |
21de5673 TI |
709 | int channel, unsigned long pos, |
710 | void __user *src, unsigned long count) | |
1da177e4 | 711 | { |
10754f53 TI |
712 | struct snd_pcm_runtime *runtime = substream->runtime; |
713 | struct nm256_stream *s = runtime->private_data; | |
21de5673 | 714 | |
1da177e4 LT |
715 | if (copy_from_user_toio(s->bufptr + pos, src, count)) |
716 | return -EFAULT; | |
717 | return 0; | |
718 | } | |
719 | ||
21de5673 TI |
720 | static int |
721 | snd_nm256_playback_copy_kernel(struct snd_pcm_substream *substream, | |
722 | int channel, unsigned long pos, | |
723 | void *src, unsigned long count) | |
724 | { | |
725 | struct snd_pcm_runtime *runtime = substream->runtime; | |
726 | struct nm256_stream *s = runtime->private_data; | |
727 | ||
728 | memcpy_toio(s->bufptr + pos, src, count); | |
729 | return 0; | |
730 | } | |
731 | ||
1da177e4 LT |
732 | /* |
733 | * copy to user | |
734 | */ | |
735 | static int | |
10754f53 | 736 | snd_nm256_capture_copy(struct snd_pcm_substream *substream, |
21de5673 TI |
737 | int channel, unsigned long pos, |
738 | void __user *dst, unsigned long count) | |
1da177e4 | 739 | { |
10754f53 TI |
740 | struct snd_pcm_runtime *runtime = substream->runtime; |
741 | struct nm256_stream *s = runtime->private_data; | |
21de5673 | 742 | |
1da177e4 LT |
743 | if (copy_to_user_fromio(dst, s->bufptr + pos, count)) |
744 | return -EFAULT; | |
745 | return 0; | |
746 | } | |
747 | ||
21de5673 TI |
748 | static int |
749 | snd_nm256_capture_copy_kernel(struct snd_pcm_substream *substream, | |
750 | int channel, unsigned long pos, | |
751 | void *dst, unsigned long count) | |
752 | { | |
753 | struct snd_pcm_runtime *runtime = substream->runtime; | |
754 | struct nm256_stream *s = runtime->private_data; | |
755 | ||
756 | memcpy_fromio(dst, s->bufptr + pos, count); | |
757 | return 0; | |
758 | } | |
759 | ||
1da177e4 LT |
760 | #endif /* !__i386__ */ |
761 | ||
762 | ||
763 | /* | |
764 | * update playback/capture watermarks | |
765 | */ | |
766 | ||
767 | /* spinlock held! */ | |
768 | static void | |
10754f53 | 769 | snd_nm256_playback_update(struct nm256 *chip) |
1da177e4 | 770 | { |
10754f53 | 771 | struct nm256_stream *s; |
1da177e4 LT |
772 | |
773 | s = &chip->streams[SNDRV_PCM_STREAM_PLAYBACK]; | |
774 | if (s->running && s->substream) { | |
775 | spin_unlock(&chip->reg_lock); | |
776 | snd_pcm_period_elapsed(s->substream); | |
777 | spin_lock(&chip->reg_lock); | |
778 | snd_nm256_playback_mark(chip, s); | |
779 | } | |
780 | } | |
781 | ||
782 | /* spinlock held! */ | |
783 | static void | |
10754f53 | 784 | snd_nm256_capture_update(struct nm256 *chip) |
1da177e4 | 785 | { |
10754f53 | 786 | struct nm256_stream *s; |
1da177e4 LT |
787 | |
788 | s = &chip->streams[SNDRV_PCM_STREAM_CAPTURE]; | |
789 | if (s->running && s->substream) { | |
790 | spin_unlock(&chip->reg_lock); | |
791 | snd_pcm_period_elapsed(s->substream); | |
792 | spin_lock(&chip->reg_lock); | |
793 | snd_nm256_capture_mark(chip, s); | |
794 | } | |
795 | } | |
796 | ||
797 | /* | |
798 | * hardware info | |
799 | */ | |
10754f53 | 800 | static struct snd_pcm_hardware snd_nm256_playback = |
1da177e4 LT |
801 | { |
802 | .info = SNDRV_PCM_INFO_MMAP_IOMEM |SNDRV_PCM_INFO_MMAP_VALID | | |
803 | SNDRV_PCM_INFO_INTERLEAVED | | |
804 | /*SNDRV_PCM_INFO_PAUSE |*/ | |
805 | SNDRV_PCM_INFO_RESUME, | |
806 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, | |
807 | .rates = SNDRV_PCM_RATE_KNOT/*24k*/ | SNDRV_PCM_RATE_8000_48000, | |
808 | .rate_min = 8000, | |
809 | .rate_max = 48000, | |
810 | .channels_min = 1, | |
811 | .channels_max = 2, | |
812 | .periods_min = 2, | |
813 | .periods_max = 1024, | |
814 | .buffer_bytes_max = 128 * 1024, | |
815 | .period_bytes_min = 256, | |
816 | .period_bytes_max = 128 * 1024, | |
817 | }; | |
818 | ||
10754f53 | 819 | static struct snd_pcm_hardware snd_nm256_capture = |
1da177e4 LT |
820 | { |
821 | .info = SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID | | |
822 | SNDRV_PCM_INFO_INTERLEAVED | | |
823 | /*SNDRV_PCM_INFO_PAUSE |*/ | |
824 | SNDRV_PCM_INFO_RESUME, | |
825 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, | |
826 | .rates = SNDRV_PCM_RATE_KNOT/*24k*/ | SNDRV_PCM_RATE_8000_48000, | |
827 | .rate_min = 8000, | |
828 | .rate_max = 48000, | |
829 | .channels_min = 1, | |
830 | .channels_max = 2, | |
831 | .periods_min = 2, | |
832 | .periods_max = 1024, | |
833 | .buffer_bytes_max = 128 * 1024, | |
834 | .period_bytes_min = 256, | |
835 | .period_bytes_max = 128 * 1024, | |
836 | }; | |
837 | ||
838 | ||
839 | /* set dma transfer size */ | |
10754f53 TI |
840 | static int snd_nm256_pcm_hw_params(struct snd_pcm_substream *substream, |
841 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 LT |
842 | { |
843 | /* area and addr are already set and unchanged */ | |
844 | substream->runtime->dma_bytes = params_buffer_bytes(hw_params); | |
845 | return 0; | |
846 | } | |
847 | ||
848 | /* | |
849 | * open | |
850 | */ | |
10754f53 TI |
851 | static void snd_nm256_setup_stream(struct nm256 *chip, struct nm256_stream *s, |
852 | struct snd_pcm_substream *substream, | |
853 | struct snd_pcm_hardware *hw_ptr) | |
1da177e4 | 854 | { |
10754f53 | 855 | struct snd_pcm_runtime *runtime = substream->runtime; |
1da177e4 LT |
856 | |
857 | s->running = 0; | |
858 | runtime->hw = *hw_ptr; | |
859 | runtime->hw.buffer_bytes_max = s->bufsize; | |
860 | runtime->hw.period_bytes_max = s->bufsize / 2; | |
4d23359b | 861 | runtime->dma_area = (void __force *) s->bufptr; |
1da177e4 LT |
862 | runtime->dma_addr = s->bufptr_addr; |
863 | runtime->dma_bytes = s->bufsize; | |
864 | runtime->private_data = s; | |
865 | s->substream = substream; | |
866 | ||
1da177e4 LT |
867 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, |
868 | &constraints_rates); | |
869 | } | |
870 | ||
871 | static int | |
10754f53 | 872 | snd_nm256_playback_open(struct snd_pcm_substream *substream) |
1da177e4 | 873 | { |
10754f53 | 874 | struct nm256 *chip = snd_pcm_substream_chip(substream); |
1da177e4 | 875 | |
1204de32 TI |
876 | if (snd_nm256_acquire_irq(chip) < 0) |
877 | return -EBUSY; | |
1da177e4 LT |
878 | snd_nm256_setup_stream(chip, &chip->streams[SNDRV_PCM_STREAM_PLAYBACK], |
879 | substream, &snd_nm256_playback); | |
880 | return 0; | |
881 | } | |
882 | ||
883 | static int | |
10754f53 | 884 | snd_nm256_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 885 | { |
10754f53 | 886 | struct nm256 *chip = snd_pcm_substream_chip(substream); |
1da177e4 | 887 | |
1204de32 TI |
888 | if (snd_nm256_acquire_irq(chip) < 0) |
889 | return -EBUSY; | |
1da177e4 LT |
890 | snd_nm256_setup_stream(chip, &chip->streams[SNDRV_PCM_STREAM_CAPTURE], |
891 | substream, &snd_nm256_capture); | |
892 | return 0; | |
893 | } | |
894 | ||
895 | /* | |
896 | * close - we don't have to do special.. | |
897 | */ | |
898 | static int | |
10754f53 | 899 | snd_nm256_playback_close(struct snd_pcm_substream *substream) |
1da177e4 | 900 | { |
10754f53 | 901 | struct nm256 *chip = snd_pcm_substream_chip(substream); |
1204de32 TI |
902 | |
903 | snd_nm256_release_irq(chip); | |
1da177e4 LT |
904 | return 0; |
905 | } | |
906 | ||
907 | ||
908 | static int | |
10754f53 | 909 | snd_nm256_capture_close(struct snd_pcm_substream *substream) |
1da177e4 | 910 | { |
10754f53 | 911 | struct nm256 *chip = snd_pcm_substream_chip(substream); |
1204de32 TI |
912 | |
913 | snd_nm256_release_irq(chip); | |
1da177e4 LT |
914 | return 0; |
915 | } | |
916 | ||
917 | /* | |
918 | * create a pcm instance | |
919 | */ | |
6769e988 | 920 | static const struct snd_pcm_ops snd_nm256_playback_ops = { |
1da177e4 LT |
921 | .open = snd_nm256_playback_open, |
922 | .close = snd_nm256_playback_close, | |
923 | .ioctl = snd_pcm_lib_ioctl, | |
924 | .hw_params = snd_nm256_pcm_hw_params, | |
925 | .prepare = snd_nm256_pcm_prepare, | |
926 | .trigger = snd_nm256_playback_trigger, | |
927 | .pointer = snd_nm256_playback_pointer, | |
928 | #ifndef __i386__ | |
21de5673 TI |
929 | .copy_user = snd_nm256_playback_copy, |
930 | .copy_kernel = snd_nm256_playback_copy_kernel, | |
931 | .fill_silence = snd_nm256_playback_silence, | |
1da177e4 LT |
932 | #endif |
933 | .mmap = snd_pcm_lib_mmap_iomem, | |
934 | }; | |
935 | ||
6769e988 | 936 | static const struct snd_pcm_ops snd_nm256_capture_ops = { |
1da177e4 LT |
937 | .open = snd_nm256_capture_open, |
938 | .close = snd_nm256_capture_close, | |
939 | .ioctl = snd_pcm_lib_ioctl, | |
940 | .hw_params = snd_nm256_pcm_hw_params, | |
941 | .prepare = snd_nm256_pcm_prepare, | |
942 | .trigger = snd_nm256_capture_trigger, | |
943 | .pointer = snd_nm256_capture_pointer, | |
944 | #ifndef __i386__ | |
21de5673 TI |
945 | .copy_user = snd_nm256_capture_copy, |
946 | .copy_kernel = snd_nm256_capture_copy_kernel, | |
1da177e4 LT |
947 | #endif |
948 | .mmap = snd_pcm_lib_mmap_iomem, | |
949 | }; | |
950 | ||
e23e7a14 | 951 | static int |
10754f53 | 952 | snd_nm256_pcm(struct nm256 *chip, int device) |
1da177e4 | 953 | { |
10754f53 | 954 | struct snd_pcm *pcm; |
1da177e4 LT |
955 | int i, err; |
956 | ||
957 | for (i = 0; i < 2; i++) { | |
10754f53 | 958 | struct nm256_stream *s = &chip->streams[i]; |
1da177e4 LT |
959 | s->bufptr = chip->buffer + (s->buf - chip->buffer_start); |
960 | s->bufptr_addr = chip->buffer_addr + (s->buf - chip->buffer_start); | |
961 | } | |
962 | ||
963 | err = snd_pcm_new(chip->card, chip->card->driver, device, | |
964 | 1, 1, &pcm); | |
965 | if (err < 0) | |
966 | return err; | |
967 | ||
968 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_nm256_playback_ops); | |
969 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_nm256_capture_ops); | |
970 | ||
971 | pcm->private_data = chip; | |
972 | pcm->info_flags = 0; | |
973 | chip->pcm = pcm; | |
974 | ||
975 | return 0; | |
976 | } | |
977 | ||
978 | ||
979 | /* | |
980 | * Initialize the hardware. | |
981 | */ | |
982 | static void | |
10754f53 | 983 | snd_nm256_init_chip(struct nm256 *chip) |
1da177e4 | 984 | { |
1da177e4 LT |
985 | /* Reset everything. */ |
986 | snd_nm256_writeb(chip, 0x0, 0x11); | |
987 | snd_nm256_writew(chip, 0x214, 0); | |
988 | /* stop sounds.. */ | |
989 | //snd_nm256_playback_stop(chip); | |
990 | //snd_nm256_capture_stop(chip); | |
1da177e4 LT |
991 | } |
992 | ||
993 | ||
1204de32 | 994 | static irqreturn_t |
10754f53 | 995 | snd_nm256_intr_check(struct nm256 *chip) |
1da177e4 LT |
996 | { |
997 | if (chip->badintrcount++ > 1000) { | |
998 | /* | |
999 | * I'm not sure if the best thing is to stop the card from | |
1000 | * playing or just release the interrupt (after all, we're in | |
1001 | * a bad situation, so doing fancy stuff may not be such a good | |
1002 | * idea). | |
1003 | * | |
1004 | * I worry about the card engine continuing to play noise | |
1005 | * over and over, however--that could become a very | |
1006 | * obnoxious problem. And we know that when this usually | |
1007 | * happens things are fairly safe, it just means the user's | |
1008 | * inserted a PCMCIA card and someone's spamming us with IRQ 9s. | |
1009 | */ | |
1010 | if (chip->streams[SNDRV_PCM_STREAM_PLAYBACK].running) | |
1011 | snd_nm256_playback_stop(chip); | |
1012 | if (chip->streams[SNDRV_PCM_STREAM_CAPTURE].running) | |
1013 | snd_nm256_capture_stop(chip); | |
1014 | chip->badintrcount = 0; | |
1204de32 | 1015 | return IRQ_HANDLED; |
1da177e4 | 1016 | } |
1204de32 | 1017 | return IRQ_NONE; |
1da177e4 LT |
1018 | } |
1019 | ||
1020 | /* | |
1021 | * Handle a potential interrupt for the device referred to by DEV_ID. | |
1022 | * | |
1023 | * I don't like the cut-n-paste job here either between the two routines, | |
1024 | * but there are sufficient differences between the two interrupt handlers | |
1025 | * that parameterizing it isn't all that great either. (Could use a macro, | |
1026 | * I suppose...yucky bleah.) | |
1027 | */ | |
1028 | ||
1029 | static irqreturn_t | |
7d12e780 | 1030 | snd_nm256_interrupt(int irq, void *dev_id) |
1da177e4 | 1031 | { |
10754f53 | 1032 | struct nm256 *chip = dev_id; |
1da177e4 LT |
1033 | u16 status; |
1034 | u8 cbyte; | |
1035 | ||
1036 | status = snd_nm256_readw(chip, NM_INT_REG); | |
1037 | ||
1038 | /* Not ours. */ | |
1204de32 TI |
1039 | if (status == 0) |
1040 | return snd_nm256_intr_check(chip); | |
1da177e4 LT |
1041 | |
1042 | chip->badintrcount = 0; | |
1043 | ||
1044 | /* Rather boring; check for individual interrupts and process them. */ | |
1045 | ||
1046 | spin_lock(&chip->reg_lock); | |
1047 | if (status & NM_PLAYBACK_INT) { | |
1048 | status &= ~NM_PLAYBACK_INT; | |
1049 | NM_ACK_INT(chip, NM_PLAYBACK_INT); | |
1050 | snd_nm256_playback_update(chip); | |
1051 | } | |
1052 | ||
1053 | if (status & NM_RECORD_INT) { | |
1054 | status &= ~NM_RECORD_INT; | |
1055 | NM_ACK_INT(chip, NM_RECORD_INT); | |
1056 | snd_nm256_capture_update(chip); | |
1057 | } | |
1058 | ||
1059 | if (status & NM_MISC_INT_1) { | |
1060 | status &= ~NM_MISC_INT_1; | |
1061 | NM_ACK_INT(chip, NM_MISC_INT_1); | |
a3fe03f4 | 1062 | dev_dbg(chip->card->dev, "NM256: Got misc interrupt #1\n"); |
1da177e4 LT |
1063 | snd_nm256_writew(chip, NM_INT_REG, 0x8000); |
1064 | cbyte = snd_nm256_readb(chip, 0x400); | |
1065 | snd_nm256_writeb(chip, 0x400, cbyte | 2); | |
1066 | } | |
1067 | ||
1068 | if (status & NM_MISC_INT_2) { | |
1069 | status &= ~NM_MISC_INT_2; | |
1070 | NM_ACK_INT(chip, NM_MISC_INT_2); | |
a3fe03f4 | 1071 | dev_dbg(chip->card->dev, "NM256: Got misc interrupt #2\n"); |
1da177e4 LT |
1072 | cbyte = snd_nm256_readb(chip, 0x400); |
1073 | snd_nm256_writeb(chip, 0x400, cbyte & ~2); | |
1074 | } | |
1075 | ||
1076 | /* Unknown interrupt. */ | |
1077 | if (status) { | |
a3fe03f4 TI |
1078 | dev_dbg(chip->card->dev, |
1079 | "NM256: Fire in the hole! Unknown status 0x%x\n", | |
1da177e4 LT |
1080 | status); |
1081 | /* Pray. */ | |
1082 | NM_ACK_INT(chip, status); | |
1083 | } | |
1084 | ||
1085 | spin_unlock(&chip->reg_lock); | |
1086 | return IRQ_HANDLED; | |
1087 | } | |
1088 | ||
1089 | /* | |
1090 | * Handle a potential interrupt for the device referred to by DEV_ID. | |
1091 | * This handler is for the 256ZX, and is very similar to the non-ZX | |
1092 | * routine. | |
1093 | */ | |
1094 | ||
1095 | static irqreturn_t | |
7d12e780 | 1096 | snd_nm256_interrupt_zx(int irq, void *dev_id) |
1da177e4 | 1097 | { |
10754f53 | 1098 | struct nm256 *chip = dev_id; |
1da177e4 LT |
1099 | u32 status; |
1100 | u8 cbyte; | |
1101 | ||
1102 | status = snd_nm256_readl(chip, NM_INT_REG); | |
1103 | ||
1104 | /* Not ours. */ | |
1204de32 TI |
1105 | if (status == 0) |
1106 | return snd_nm256_intr_check(chip); | |
1da177e4 LT |
1107 | |
1108 | chip->badintrcount = 0; | |
1109 | ||
1110 | /* Rather boring; check for individual interrupts and process them. */ | |
1111 | ||
1112 | spin_lock(&chip->reg_lock); | |
1113 | if (status & NM2_PLAYBACK_INT) { | |
1114 | status &= ~NM2_PLAYBACK_INT; | |
1115 | NM2_ACK_INT(chip, NM2_PLAYBACK_INT); | |
1116 | snd_nm256_playback_update(chip); | |
1117 | } | |
1118 | ||
1119 | if (status & NM2_RECORD_INT) { | |
1120 | status &= ~NM2_RECORD_INT; | |
1121 | NM2_ACK_INT(chip, NM2_RECORD_INT); | |
1122 | snd_nm256_capture_update(chip); | |
1123 | } | |
1124 | ||
1125 | if (status & NM2_MISC_INT_1) { | |
1126 | status &= ~NM2_MISC_INT_1; | |
1127 | NM2_ACK_INT(chip, NM2_MISC_INT_1); | |
a3fe03f4 | 1128 | dev_dbg(chip->card->dev, "NM256: Got misc interrupt #1\n"); |
1da177e4 LT |
1129 | cbyte = snd_nm256_readb(chip, 0x400); |
1130 | snd_nm256_writeb(chip, 0x400, cbyte | 2); | |
1131 | } | |
1132 | ||
1133 | if (status & NM2_MISC_INT_2) { | |
1134 | status &= ~NM2_MISC_INT_2; | |
1135 | NM2_ACK_INT(chip, NM2_MISC_INT_2); | |
a3fe03f4 | 1136 | dev_dbg(chip->card->dev, "NM256: Got misc interrupt #2\n"); |
1da177e4 LT |
1137 | cbyte = snd_nm256_readb(chip, 0x400); |
1138 | snd_nm256_writeb(chip, 0x400, cbyte & ~2); | |
1139 | } | |
1140 | ||
1141 | /* Unknown interrupt. */ | |
1142 | if (status) { | |
a3fe03f4 TI |
1143 | dev_dbg(chip->card->dev, |
1144 | "NM256: Fire in the hole! Unknown status 0x%x\n", | |
1da177e4 LT |
1145 | status); |
1146 | /* Pray. */ | |
1147 | NM2_ACK_INT(chip, status); | |
1148 | } | |
1149 | ||
1150 | spin_unlock(&chip->reg_lock); | |
1151 | return IRQ_HANDLED; | |
1152 | } | |
1153 | ||
1154 | /* | |
1155 | * AC97 interface | |
1156 | */ | |
1157 | ||
1158 | /* | |
1159 | * Waits for the mixer to become ready to be written; returns a zero value | |
1160 | * if it timed out. | |
1161 | */ | |
1162 | static int | |
10754f53 | 1163 | snd_nm256_ac97_ready(struct nm256 *chip) |
1da177e4 LT |
1164 | { |
1165 | int timeout = 10; | |
1166 | u32 testaddr; | |
1167 | u16 testb; | |
1168 | ||
1169 | testaddr = chip->mixer_status_offset; | |
1170 | testb = chip->mixer_status_mask; | |
1171 | ||
1172 | /* | |
1173 | * Loop around waiting for the mixer to become ready. | |
1174 | */ | |
1175 | while (timeout-- > 0) { | |
1176 | if ((snd_nm256_readw(chip, testaddr) & testb) == 0) | |
1177 | return 1; | |
1178 | udelay(100); | |
1179 | } | |
1180 | return 0; | |
1181 | } | |
1182 | ||
a23446c0 FS |
1183 | /* |
1184 | * Initial register values to be written to the AC97 mixer. | |
1185 | * While most of these are identical to the reset values, we do this | |
1186 | * so that we have most of the register contents cached--this avoids | |
1187 | * reading from the mixer directly (which seems to be problematic, | |
1188 | * probably due to ignorance). | |
1189 | */ | |
1190 | ||
1191 | struct initialValues { | |
1192 | unsigned short reg; | |
1193 | unsigned short value; | |
1194 | }; | |
1195 | ||
1196 | static struct initialValues nm256_ac97_init_val[] = | |
1197 | { | |
1198 | { AC97_MASTER, 0x8000 }, | |
1199 | { AC97_HEADPHONE, 0x8000 }, | |
1200 | { AC97_MASTER_MONO, 0x8000 }, | |
1201 | { AC97_PC_BEEP, 0x8000 }, | |
1202 | { AC97_PHONE, 0x8008 }, | |
1203 | { AC97_MIC, 0x8000 }, | |
1204 | { AC97_LINE, 0x8808 }, | |
1205 | { AC97_CD, 0x8808 }, | |
1206 | { AC97_VIDEO, 0x8808 }, | |
1207 | { AC97_AUX, 0x8808 }, | |
1208 | { AC97_PCM, 0x8808 }, | |
1209 | { AC97_REC_SEL, 0x0000 }, | |
1210 | { AC97_REC_GAIN, 0x0B0B }, | |
1211 | { AC97_GENERAL_PURPOSE, 0x0000 }, | |
1212 | { AC97_3D_CONTROL, 0x8000 }, | |
1213 | { AC97_VENDOR_ID1, 0x8384 }, | |
1214 | { AC97_VENDOR_ID2, 0x7609 }, | |
1215 | }; | |
1216 | ||
1217 | static int nm256_ac97_idx(unsigned short reg) | |
1218 | { | |
1219 | int i; | |
1220 | for (i = 0; i < ARRAY_SIZE(nm256_ac97_init_val); i++) | |
1221 | if (nm256_ac97_init_val[i].reg == reg) | |
1222 | return i; | |
1223 | return -1; | |
1224 | } | |
1225 | ||
1da177e4 | 1226 | /* |
a23446c0 FS |
1227 | * some nm256 easily crash when reading from mixer registers |
1228 | * thus we're treating it as a write-only mixer and cache the | |
1229 | * written values | |
1da177e4 LT |
1230 | */ |
1231 | static unsigned short | |
10754f53 | 1232 | snd_nm256_ac97_read(struct snd_ac97 *ac97, unsigned short reg) |
1da177e4 | 1233 | { |
10754f53 | 1234 | struct nm256 *chip = ac97->private_data; |
a23446c0 | 1235 | int idx = nm256_ac97_idx(reg); |
1da177e4 | 1236 | |
a23446c0 | 1237 | if (idx < 0) |
1da177e4 | 1238 | return 0; |
a23446c0 | 1239 | return chip->ac97_regs[idx]; |
1da177e4 LT |
1240 | } |
1241 | ||
1242 | /* | |
1243 | */ | |
1244 | static void | |
10754f53 | 1245 | snd_nm256_ac97_write(struct snd_ac97 *ac97, |
1da177e4 LT |
1246 | unsigned short reg, unsigned short val) |
1247 | { | |
10754f53 | 1248 | struct nm256 *chip = ac97->private_data; |
1da177e4 | 1249 | int tries = 2; |
a23446c0 | 1250 | int idx = nm256_ac97_idx(reg); |
1da177e4 LT |
1251 | u32 base; |
1252 | ||
a23446c0 FS |
1253 | if (idx < 0) |
1254 | return; | |
1255 | ||
1da177e4 LT |
1256 | base = chip->mixer_base; |
1257 | ||
1258 | snd_nm256_ac97_ready(chip); | |
1259 | ||
1260 | /* Wait for the write to take, too. */ | |
1261 | while (tries-- > 0) { | |
1262 | snd_nm256_writew(chip, base + reg, val); | |
1263 | msleep(1); /* a little delay here seems better.. */ | |
a23446c0 FS |
1264 | if (snd_nm256_ac97_ready(chip)) { |
1265 | /* successful write: set cache */ | |
1266 | chip->ac97_regs[idx] = val; | |
1da177e4 | 1267 | return; |
a23446c0 | 1268 | } |
1da177e4 | 1269 | } |
a3fe03f4 | 1270 | dev_dbg(chip->card->dev, "nm256: ac97 codec not ready..\n"); |
1da177e4 LT |
1271 | } |
1272 | ||
a23446c0 FS |
1273 | /* static resolution table */ |
1274 | static struct snd_ac97_res_table nm256_res_table[] = { | |
1275 | { AC97_MASTER, 0x1f1f }, | |
1276 | { AC97_HEADPHONE, 0x1f1f }, | |
1277 | { AC97_MASTER_MONO, 0x001f }, | |
1278 | { AC97_PC_BEEP, 0x001f }, | |
1279 | { AC97_PHONE, 0x001f }, | |
1280 | { AC97_MIC, 0x001f }, | |
1281 | { AC97_LINE, 0x1f1f }, | |
1282 | { AC97_CD, 0x1f1f }, | |
1283 | { AC97_VIDEO, 0x1f1f }, | |
1284 | { AC97_AUX, 0x1f1f }, | |
1285 | { AC97_PCM, 0x1f1f }, | |
1286 | { AC97_REC_GAIN, 0x0f0f }, | |
1287 | { } /* terminator */ | |
1288 | }; | |
1289 | ||
1da177e4 LT |
1290 | /* initialize the ac97 into a known state */ |
1291 | static void | |
10754f53 | 1292 | snd_nm256_ac97_reset(struct snd_ac97 *ac97) |
1da177e4 | 1293 | { |
10754f53 | 1294 | struct nm256 *chip = ac97->private_data; |
1da177e4 LT |
1295 | |
1296 | /* Reset the mixer. 'Tis magic! */ | |
1297 | snd_nm256_writeb(chip, 0x6c0, 1); | |
1298 | if (! chip->reset_workaround) { | |
1299 | /* Dell latitude LS will lock up by this */ | |
1300 | snd_nm256_writeb(chip, 0x6cc, 0x87); | |
1301 | } | |
47530cf4 JL |
1302 | if (! chip->reset_workaround_2) { |
1303 | /* Dell latitude CSx will lock up by this */ | |
1304 | snd_nm256_writeb(chip, 0x6cc, 0x80); | |
1305 | snd_nm256_writeb(chip, 0x6cc, 0x0); | |
1306 | } | |
a23446c0 FS |
1307 | if (! chip->in_resume) { |
1308 | int i; | |
1309 | for (i = 0; i < ARRAY_SIZE(nm256_ac97_init_val); i++) { | |
1310 | /* preload the cache, so as to avoid even a single | |
1311 | * read of the mixer regs | |
1312 | */ | |
1313 | snd_nm256_ac97_write(ac97, nm256_ac97_init_val[i].reg, | |
1314 | nm256_ac97_init_val[i].value); | |
1315 | } | |
1316 | } | |
1da177e4 LT |
1317 | } |
1318 | ||
1319 | /* create an ac97 mixer interface */ | |
e23e7a14 | 1320 | static int |
10754f53 | 1321 | snd_nm256_mixer(struct nm256 *chip) |
1da177e4 | 1322 | { |
10754f53 TI |
1323 | struct snd_ac97_bus *pbus; |
1324 | struct snd_ac97_template ac97; | |
a23446c0 | 1325 | int err; |
10754f53 | 1326 | static struct snd_ac97_bus_ops ops = { |
1da177e4 LT |
1327 | .reset = snd_nm256_ac97_reset, |
1328 | .write = snd_nm256_ac97_write, | |
1329 | .read = snd_nm256_ac97_read, | |
1330 | }; | |
a23446c0 | 1331 | |
80ca9a70 MM |
1332 | chip->ac97_regs = kcalloc(ARRAY_SIZE(nm256_ac97_init_val), |
1333 | sizeof(short), GFP_KERNEL); | |
a23446c0 FS |
1334 | if (! chip->ac97_regs) |
1335 | return -ENOMEM; | |
1da177e4 LT |
1336 | |
1337 | if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0) | |
1338 | return err; | |
1339 | ||
1340 | memset(&ac97, 0, sizeof(ac97)); | |
1341 | ac97.scaps = AC97_SCAP_AUDIO; /* we support audio! */ | |
1da177e4 | 1342 | ac97.private_data = chip; |
a23446c0 | 1343 | ac97.res_table = nm256_res_table; |
1204de32 | 1344 | pbus->no_vra = 1; |
1da177e4 LT |
1345 | err = snd_ac97_mixer(pbus, &ac97, &chip->ac97); |
1346 | if (err < 0) | |
1347 | return err; | |
1348 | if (! (chip->ac97->id & (0xf0000000))) { | |
1349 | /* looks like an invalid id */ | |
1350 | sprintf(chip->card->mixername, "%s AC97", chip->card->driver); | |
1351 | } | |
1352 | return 0; | |
1353 | } | |
1354 | ||
1355 | /* | |
1356 | * See if the signature left by the NM256 BIOS is intact; if so, we use | |
1357 | * the associated address as the end of our audio buffer in the video | |
1358 | * RAM. | |
1359 | */ | |
1360 | ||
e23e7a14 | 1361 | static int |
10754f53 | 1362 | snd_nm256_peek_for_sig(struct nm256 *chip) |
1da177e4 LT |
1363 | { |
1364 | /* The signature is located 1K below the end of video RAM. */ | |
1365 | void __iomem *temp; | |
1366 | /* Default buffer end is 5120 bytes below the top of RAM. */ | |
1367 | unsigned long pointer_found = chip->buffer_end - 0x1400; | |
1368 | u32 sig; | |
1369 | ||
1370 | temp = ioremap_nocache(chip->buffer_addr + chip->buffer_end - 0x400, 16); | |
1371 | if (temp == NULL) { | |
a3fe03f4 TI |
1372 | dev_err(chip->card->dev, |
1373 | "Unable to scan for card signature in video RAM\n"); | |
1da177e4 LT |
1374 | return -EBUSY; |
1375 | } | |
1376 | ||
1377 | sig = readl(temp); | |
1378 | if ((sig & NM_SIG_MASK) == NM_SIGNATURE) { | |
1379 | u32 pointer = readl(temp + 4); | |
1380 | ||
1381 | /* | |
1382 | * If it's obviously invalid, don't use it | |
1383 | */ | |
1384 | if (pointer == 0xffffffff || | |
1385 | pointer < chip->buffer_size || | |
1386 | pointer > chip->buffer_end) { | |
a3fe03f4 TI |
1387 | dev_err(chip->card->dev, |
1388 | "invalid signature found: 0x%x\n", pointer); | |
1da177e4 LT |
1389 | iounmap(temp); |
1390 | return -ENODEV; | |
1391 | } else { | |
1392 | pointer_found = pointer; | |
a3fe03f4 TI |
1393 | dev_info(chip->card->dev, |
1394 | "found card signature in video RAM: 0x%x\n", | |
10754f53 | 1395 | pointer); |
1da177e4 LT |
1396 | } |
1397 | } | |
1398 | ||
1399 | iounmap(temp); | |
1400 | chip->buffer_end = pointer_found; | |
1401 | ||
1402 | return 0; | |
1403 | } | |
1404 | ||
c7561cd8 | 1405 | #ifdef CONFIG_PM_SLEEP |
1da177e4 LT |
1406 | /* |
1407 | * APM event handler, so the card is properly reinitialized after a power | |
1408 | * event. | |
1409 | */ | |
68cb2b55 | 1410 | static int nm256_suspend(struct device *dev) |
1da177e4 | 1411 | { |
68cb2b55 | 1412 | struct snd_card *card = dev_get_drvdata(dev); |
3fcf7d2c | 1413 | struct nm256 *chip = card->private_data; |
1da177e4 | 1414 | |
3fcf7d2c | 1415 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
1da177e4 LT |
1416 | snd_pcm_suspend_all(chip->pcm); |
1417 | snd_ac97_suspend(chip->ac97); | |
1418 | chip->coeffs_current = 0; | |
1da177e4 LT |
1419 | return 0; |
1420 | } | |
1421 | ||
68cb2b55 | 1422 | static int nm256_resume(struct device *dev) |
1da177e4 | 1423 | { |
68cb2b55 | 1424 | struct snd_card *card = dev_get_drvdata(dev); |
3fcf7d2c | 1425 | struct nm256 *chip = card->private_data; |
1204de32 | 1426 | int i; |
1da177e4 LT |
1427 | |
1428 | /* Perform a full reset on the hardware */ | |
a23446c0 | 1429 | chip->in_resume = 1; |
30b35399 | 1430 | |
1da177e4 LT |
1431 | snd_nm256_init_chip(chip); |
1432 | ||
1433 | /* restore ac97 */ | |
1434 | snd_ac97_resume(chip->ac97); | |
1435 | ||
1204de32 | 1436 | for (i = 0; i < 2; i++) { |
10754f53 | 1437 | struct nm256_stream *s = &chip->streams[i]; |
1204de32 TI |
1438 | if (s->substream && s->suspended) { |
1439 | spin_lock_irq(&chip->reg_lock); | |
1440 | snd_nm256_set_format(chip, s, s->substream); | |
1441 | spin_unlock_irq(&chip->reg_lock); | |
1442 | } | |
1443 | } | |
1444 | ||
3fcf7d2c | 1445 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
a23446c0 | 1446 | chip->in_resume = 0; |
1da177e4 LT |
1447 | return 0; |
1448 | } | |
68cb2b55 TI |
1449 | |
1450 | static SIMPLE_DEV_PM_OPS(nm256_pm, nm256_suspend, nm256_resume); | |
1451 | #define NM256_PM_OPS &nm256_pm | |
1452 | #else | |
1453 | #define NM256_PM_OPS NULL | |
c7561cd8 | 1454 | #endif /* CONFIG_PM_SLEEP */ |
1da177e4 | 1455 | |
10754f53 | 1456 | static int snd_nm256_free(struct nm256 *chip) |
1da177e4 LT |
1457 | { |
1458 | if (chip->streams[SNDRV_PCM_STREAM_PLAYBACK].running) | |
1459 | snd_nm256_playback_stop(chip); | |
1460 | if (chip->streams[SNDRV_PCM_STREAM_CAPTURE].running) | |
1461 | snd_nm256_capture_stop(chip); | |
1462 | ||
1463 | if (chip->irq >= 0) | |
ebf029da | 1464 | free_irq(chip->irq, chip); |
1da177e4 | 1465 | |
ff6defa6 ME |
1466 | iounmap(chip->cport); |
1467 | iounmap(chip->buffer); | |
b1d5776d TI |
1468 | release_and_free_resource(chip->res_cport); |
1469 | release_and_free_resource(chip->res_buffer); | |
1da177e4 LT |
1470 | |
1471 | pci_disable_device(chip->pci); | |
a23446c0 | 1472 | kfree(chip->ac97_regs); |
1da177e4 LT |
1473 | kfree(chip); |
1474 | return 0; | |
1475 | } | |
1476 | ||
10754f53 | 1477 | static int snd_nm256_dev_free(struct snd_device *device) |
1da177e4 | 1478 | { |
10754f53 | 1479 | struct nm256 *chip = device->device_data; |
1da177e4 LT |
1480 | return snd_nm256_free(chip); |
1481 | } | |
1482 | ||
e23e7a14 | 1483 | static int |
10754f53 TI |
1484 | snd_nm256_create(struct snd_card *card, struct pci_dev *pci, |
1485 | struct nm256 **chip_ret) | |
1da177e4 | 1486 | { |
10754f53 | 1487 | struct nm256 *chip; |
1da177e4 | 1488 | int err, pval; |
10754f53 | 1489 | static struct snd_device_ops ops = { |
1da177e4 LT |
1490 | .dev_free = snd_nm256_dev_free, |
1491 | }; | |
1492 | u32 addr; | |
1493 | ||
1494 | *chip_ret = NULL; | |
1495 | ||
1496 | if ((err = pci_enable_device(pci)) < 0) | |
1497 | return err; | |
1498 | ||
e560d8d8 | 1499 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
1da177e4 LT |
1500 | if (chip == NULL) { |
1501 | pci_disable_device(pci); | |
1502 | return -ENOMEM; | |
1503 | } | |
1504 | ||
1505 | chip->card = card; | |
1506 | chip->pci = pci; | |
3f05f868 | 1507 | chip->use_cache = use_cache; |
1da177e4 LT |
1508 | spin_lock_init(&chip->reg_lock); |
1509 | chip->irq = -1; | |
62932df8 | 1510 | mutex_init(&chip->irq_mutex); |
1da177e4 | 1511 | |
3f05f868 TI |
1512 | /* store buffer sizes in bytes */ |
1513 | chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize = playback_bufsize * 1024; | |
1514 | chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize = capture_bufsize * 1024; | |
1da177e4 LT |
1515 | |
1516 | /* | |
1517 | * The NM256 has two memory ports. The first port is nothing | |
1518 | * more than a chunk of video RAM, which is used as the I/O ring | |
1519 | * buffer. The second port has the actual juicy stuff (like the | |
1520 | * mixer and the playback engine control registers). | |
1521 | */ | |
1522 | ||
1523 | chip->buffer_addr = pci_resource_start(pci, 0); | |
1524 | chip->cport_addr = pci_resource_start(pci, 1); | |
1525 | ||
1526 | /* Init the memory port info. */ | |
1527 | /* remap control port (#2) */ | |
1528 | chip->res_cport = request_mem_region(chip->cport_addr, NM_PORT2_SIZE, | |
1529 | card->driver); | |
1530 | if (chip->res_cport == NULL) { | |
a3fe03f4 | 1531 | dev_err(card->dev, "memory region 0x%lx (size 0x%x) busy\n", |
1da177e4 LT |
1532 | chip->cport_addr, NM_PORT2_SIZE); |
1533 | err = -EBUSY; | |
1534 | goto __error; | |
1535 | } | |
1536 | chip->cport = ioremap_nocache(chip->cport_addr, NM_PORT2_SIZE); | |
1537 | if (chip->cport == NULL) { | |
a3fe03f4 TI |
1538 | dev_err(card->dev, "unable to map control port %lx\n", |
1539 | chip->cport_addr); | |
1da177e4 LT |
1540 | err = -ENOMEM; |
1541 | goto __error; | |
1542 | } | |
1543 | ||
1544 | if (!strcmp(card->driver, "NM256AV")) { | |
1545 | /* Ok, try to see if this is a non-AC97 version of the hardware. */ | |
1546 | pval = snd_nm256_readw(chip, NM_MIXER_PRESENCE); | |
1547 | if ((pval & NM_PRESENCE_MASK) != NM_PRESENCE_VALUE) { | |
3f05f868 | 1548 | if (! force_ac97) { |
a3fe03f4 TI |
1549 | dev_err(card->dev, |
1550 | "no ac97 is found!\n"); | |
1551 | dev_err(card->dev, | |
1552 | "force the driver to load by passing in the module parameter\n"); | |
1553 | dev_err(card->dev, | |
1554 | " force_ac97=1\n"); | |
1555 | dev_err(card->dev, | |
1556 | "or try sb16, opl3sa2, or cs423x drivers instead.\n"); | |
1da177e4 LT |
1557 | err = -ENXIO; |
1558 | goto __error; | |
1559 | } | |
1560 | } | |
1561 | chip->buffer_end = 2560 * 1024; | |
1562 | chip->interrupt = snd_nm256_interrupt; | |
1563 | chip->mixer_status_offset = NM_MIXER_STATUS_OFFSET; | |
1564 | chip->mixer_status_mask = NM_MIXER_READY_MASK; | |
1565 | } else { | |
1566 | /* Not sure if there is any relevant detect for the ZX or not. */ | |
1567 | if (snd_nm256_readb(chip, 0xa0b) != 0) | |
1568 | chip->buffer_end = 6144 * 1024; | |
1569 | else | |
1570 | chip->buffer_end = 4096 * 1024; | |
1571 | ||
1572 | chip->interrupt = snd_nm256_interrupt_zx; | |
1573 | chip->mixer_status_offset = NM2_MIXER_STATUS_OFFSET; | |
1574 | chip->mixer_status_mask = NM2_MIXER_READY_MASK; | |
1575 | } | |
1576 | ||
10754f53 TI |
1577 | chip->buffer_size = chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize + |
1578 | chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize; | |
1da177e4 LT |
1579 | if (chip->use_cache) |
1580 | chip->buffer_size += NM_TOTAL_COEFF_COUNT * 4; | |
1581 | else | |
1582 | chip->buffer_size += NM_MAX_PLAYBACK_COEF_SIZE + NM_MAX_RECORD_COEF_SIZE; | |
1583 | ||
3f05f868 TI |
1584 | if (buffer_top >= chip->buffer_size && buffer_top < chip->buffer_end) |
1585 | chip->buffer_end = buffer_top; | |
1da177e4 LT |
1586 | else { |
1587 | /* get buffer end pointer from signature */ | |
1588 | if ((err = snd_nm256_peek_for_sig(chip)) < 0) | |
1589 | goto __error; | |
1590 | } | |
1591 | ||
1592 | chip->buffer_start = chip->buffer_end - chip->buffer_size; | |
1593 | chip->buffer_addr += chip->buffer_start; | |
1594 | ||
a3fe03f4 | 1595 | dev_info(card->dev, "Mapping port 1 from 0x%x - 0x%x\n", |
1da177e4 LT |
1596 | chip->buffer_start, chip->buffer_end); |
1597 | ||
1598 | chip->res_buffer = request_mem_region(chip->buffer_addr, | |
1599 | chip->buffer_size, | |
1600 | card->driver); | |
1601 | if (chip->res_buffer == NULL) { | |
a3fe03f4 | 1602 | dev_err(card->dev, "buffer 0x%lx (size 0x%x) busy\n", |
1da177e4 LT |
1603 | chip->buffer_addr, chip->buffer_size); |
1604 | err = -EBUSY; | |
1605 | goto __error; | |
1606 | } | |
1607 | chip->buffer = ioremap_nocache(chip->buffer_addr, chip->buffer_size); | |
1608 | if (chip->buffer == NULL) { | |
1609 | err = -ENOMEM; | |
a3fe03f4 TI |
1610 | dev_err(card->dev, "unable to map ring buffer at %lx\n", |
1611 | chip->buffer_addr); | |
1da177e4 LT |
1612 | goto __error; |
1613 | } | |
1614 | ||
1615 | /* set offsets */ | |
1616 | addr = chip->buffer_start; | |
1617 | chip->streams[SNDRV_PCM_STREAM_PLAYBACK].buf = addr; | |
1618 | addr += chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize; | |
1619 | chip->streams[SNDRV_PCM_STREAM_CAPTURE].buf = addr; | |
1620 | addr += chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize; | |
1621 | if (chip->use_cache) { | |
1622 | chip->all_coeff_buf = addr; | |
1623 | } else { | |
1624 | chip->coeff_buf[SNDRV_PCM_STREAM_PLAYBACK] = addr; | |
1625 | addr += NM_MAX_PLAYBACK_COEF_SIZE; | |
1626 | chip->coeff_buf[SNDRV_PCM_STREAM_CAPTURE] = addr; | |
1627 | } | |
1628 | ||
1da177e4 LT |
1629 | /* Fixed setting. */ |
1630 | chip->mixer_base = NM_MIXER_OFFSET; | |
1631 | ||
1632 | chip->coeffs_current = 0; | |
1633 | ||
1634 | snd_nm256_init_chip(chip); | |
1635 | ||
1636 | // pci_set_master(pci); /* needed? */ | |
1637 | ||
1da177e4 LT |
1638 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) |
1639 | goto __error; | |
1640 | ||
1da177e4 LT |
1641 | *chip_ret = chip; |
1642 | return 0; | |
1643 | ||
1644 | __error: | |
1645 | snd_nm256_free(chip); | |
1646 | return err; | |
1647 | } | |
1648 | ||
1649 | ||
47530cf4 | 1650 | enum { NM_BLACKLISTED, NM_RESET_WORKAROUND, NM_RESET_WORKAROUND_2 }; |
1da177e4 | 1651 | |
e23e7a14 | 1652 | static struct snd_pci_quirk nm256_quirks[] = { |
1da177e4 | 1653 | /* HP omnibook 4150 has cs4232 codec internally */ |
e2b6d13b TI |
1654 | SND_PCI_QUIRK(0x103c, 0x0007, "HP omnibook 4150", NM_BLACKLISTED), |
1655 | /* Reset workarounds to avoid lock-ups */ | |
1656 | SND_PCI_QUIRK(0x104d, 0x8041, "Sony PCG-F305", NM_RESET_WORKAROUND), | |
1657 | SND_PCI_QUIRK(0x1028, 0x0080, "Dell Latitude LS", NM_RESET_WORKAROUND), | |
1658 | SND_PCI_QUIRK(0x1028, 0x0091, "Dell Latitude CSx", NM_RESET_WORKAROUND_2), | |
1da177e4 LT |
1659 | { } /* terminator */ |
1660 | }; | |
1661 | ||
1662 | ||
e23e7a14 BP |
1663 | static int snd_nm256_probe(struct pci_dev *pci, |
1664 | const struct pci_device_id *pci_id) | |
1da177e4 | 1665 | { |
10754f53 TI |
1666 | struct snd_card *card; |
1667 | struct nm256 *chip; | |
1da177e4 | 1668 | int err; |
e2b6d13b TI |
1669 | const struct snd_pci_quirk *q; |
1670 | ||
1671 | q = snd_pci_quirk_lookup(pci, nm256_quirks); | |
1672 | if (q) { | |
a3fe03f4 | 1673 | dev_dbg(&pci->dev, "Enabled quirk for %s.\n", |
86b27237 | 1674 | snd_pci_quirk_name(q)); |
e2b6d13b TI |
1675 | switch (q->value) { |
1676 | case NM_BLACKLISTED: | |
a3fe03f4 TI |
1677 | dev_info(&pci->dev, |
1678 | "The device is blacklisted. Loading stopped\n"); | |
e2b6d13b TI |
1679 | return -ENODEV; |
1680 | case NM_RESET_WORKAROUND_2: | |
1681 | reset_workaround_2 = 1; | |
1682 | /* Fall-through */ | |
1683 | case NM_RESET_WORKAROUND: | |
1684 | reset_workaround = 1; | |
1685 | break; | |
1da177e4 LT |
1686 | } |
1687 | } | |
1688 | ||
60c5772b | 1689 | err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card); |
e58de7ba TI |
1690 | if (err < 0) |
1691 | return err; | |
1da177e4 LT |
1692 | |
1693 | switch (pci->device) { | |
1694 | case PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO: | |
1695 | strcpy(card->driver, "NM256AV"); | |
1696 | break; | |
1697 | case PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO: | |
1698 | strcpy(card->driver, "NM256ZX"); | |
1699 | break; | |
1700 | case PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO: | |
1701 | strcpy(card->driver, "NM256XL+"); | |
1702 | break; | |
1703 | default: | |
a3fe03f4 | 1704 | dev_err(&pci->dev, "invalid device id 0x%x\n", pci->device); |
1da177e4 LT |
1705 | snd_card_free(card); |
1706 | return -EINVAL; | |
1707 | } | |
1708 | ||
8a3fb4d0 | 1709 | if (vaio_hack) |
3f05f868 | 1710 | buffer_top = 0x25a800; /* this avoids conflicts with XFree86 server */ |
8a3fb4d0 TI |
1711 | |
1712 | if (playback_bufsize < 4) | |
1713 | playback_bufsize = 4; | |
1714 | if (playback_bufsize > 128) | |
1715 | playback_bufsize = 128; | |
1716 | if (capture_bufsize < 4) | |
1717 | capture_bufsize = 4; | |
1718 | if (capture_bufsize > 128) | |
1719 | capture_bufsize = 128; | |
3f05f868 | 1720 | if ((err = snd_nm256_create(card, pci, &chip)) < 0) { |
1da177e4 LT |
1721 | snd_card_free(card); |
1722 | return err; | |
1723 | } | |
3fcf7d2c | 1724 | card->private_data = chip; |
1da177e4 | 1725 | |
8a3fb4d0 | 1726 | if (reset_workaround) { |
a3fe03f4 | 1727 | dev_dbg(&pci->dev, "reset_workaround activated\n"); |
1da177e4 LT |
1728 | chip->reset_workaround = 1; |
1729 | } | |
1730 | ||
8a3fb4d0 | 1731 | if (reset_workaround_2) { |
a3fe03f4 | 1732 | dev_dbg(&pci->dev, "reset_workaround_2 activated\n"); |
47530cf4 JL |
1733 | chip->reset_workaround_2 = 1; |
1734 | } | |
1735 | ||
1da177e4 LT |
1736 | if ((err = snd_nm256_pcm(chip, 0)) < 0 || |
1737 | (err = snd_nm256_mixer(chip)) < 0) { | |
1738 | snd_card_free(card); | |
1739 | return err; | |
1740 | } | |
1741 | ||
1742 | sprintf(card->shortname, "NeoMagic %s", card->driver); | |
1743 | sprintf(card->longname, "%s at 0x%lx & 0x%lx, irq %d", | |
1744 | card->shortname, | |
1745 | chip->buffer_addr, chip->cport_addr, chip->irq); | |
1746 | ||
1747 | if ((err = snd_card_register(card)) < 0) { | |
1748 | snd_card_free(card); | |
1749 | return err; | |
1750 | } | |
1751 | ||
1752 | pci_set_drvdata(pci, card); | |
1da177e4 LT |
1753 | return 0; |
1754 | } | |
1755 | ||
e23e7a14 | 1756 | static void snd_nm256_remove(struct pci_dev *pci) |
1da177e4 LT |
1757 | { |
1758 | snd_card_free(pci_get_drvdata(pci)); | |
1da177e4 LT |
1759 | } |
1760 | ||
1761 | ||
e9f66d9b | 1762 | static struct pci_driver nm256_driver = { |
3733e424 | 1763 | .name = KBUILD_MODNAME, |
1da177e4 LT |
1764 | .id_table = snd_nm256_ids, |
1765 | .probe = snd_nm256_probe, | |
e23e7a14 | 1766 | .remove = snd_nm256_remove, |
68cb2b55 TI |
1767 | .driver = { |
1768 | .pm = NM256_PM_OPS, | |
1769 | }, | |
1da177e4 LT |
1770 | }; |
1771 | ||
e9f66d9b | 1772 | module_pci_driver(nm256_driver); |