[mirror_ubuntu-eoan-kernel.git] / sound / pci / oxygen / oxygen_lib.c

/*
 * C-Media CMI8788 driver - main driver module
 *
 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
 *
 *
 *  This driver is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License, version 2.
 *
 *  This driver is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this driver; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/mutex.h>
#include <linux/pci.h>
#include <sound/ac97_codec.h>
#include <sound/asoundef.h>
#include <sound/core.h>
#include <sound/info.h>
#include <sound/mpu401.h>
#include <sound/pcm.h>
#include "oxygen.h"
#include "cm9780.h"

MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
MODULE_DESCRIPTION("C-Media CMI8788 helper library");
MODULE_LICENSE("GPL");


static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
{
	struct oxygen *chip = dev_id;
	unsigned int status, clear, elapsed_streams, i;

	status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
	if (!status)
		return IRQ_NONE;

	spin_lock(&chip->reg_lock);

	clear = status & (OXYGEN_CHANNEL_A |
			  OXYGEN_CHANNEL_B |
			  OXYGEN_CHANNEL_C |
			  OXYGEN_CHANNEL_SPDIF |
			  OXYGEN_CHANNEL_MULTICH |
			  OXYGEN_CHANNEL_AC97 |
			  OXYGEN_INT_SPDIF_IN_DETECT |
			  OXYGEN_INT_GPIO);
	if (clear) {
		if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
			chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
		oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
			       chip->interrupt_mask & ~clear);
		oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
			       chip->interrupt_mask);
	}

	elapsed_streams = status & chip->pcm_running;

	spin_unlock(&chip->reg_lock);

	for (i = 0; i < PCM_COUNT; ++i)
		if ((elapsed_streams & (1 << i)) && chip->streams[i])
			snd_pcm_period_elapsed(chip->streams[i]);

	if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
		spin_lock(&chip->reg_lock);
		i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
		if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
			 OXYGEN_SPDIF_RATE_INT)) {
			/* write the interrupt bit(s) to clear */
			oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
			schedule_work(&chip->spdif_input_bits_work);
		}
		spin_unlock(&chip->reg_lock);
	}

	if (status & OXYGEN_INT_GPIO)
		;

	if ((status & OXYGEN_INT_MIDI) && chip->midi)
		snd_mpu401_uart_interrupt(0, chip->midi->private_data);

	return IRQ_HANDLED;
}

static void oxygen_spdif_input_bits_changed(struct work_struct *work)
{
	struct oxygen *chip = container_of(work, struct oxygen,
					   spdif_input_bits_work);
	u32 reg;

	/*
	 * This function gets called when there is new activity on the SPDIF
	 * input, or when we lose lock on the input signal, or when the rate
	 * changes.
	 */
	msleep(1);
	spin_lock_irq(&chip->reg_lock);
	reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
	if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
		    OXYGEN_SPDIF_LOCK_STATUS))
	    == OXYGEN_SPDIF_SENSE_STATUS) {
		/*
		 * If we detect activity on the SPDIF input but cannot lock to
		 * a signal, the clock bit is likely to be wrong.
		 */
		reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
		oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
		spin_unlock_irq(&chip->reg_lock);
		msleep(1);
		spin_lock_irq(&chip->reg_lock);
		reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
		if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
			    OXYGEN_SPDIF_LOCK_STATUS))
		    == OXYGEN_SPDIF_SENSE_STATUS) {
			/* nothing detected with either clock; give up */
			if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
			    == OXYGEN_SPDIF_IN_CLOCK_192) {
				/*
				 * Reset clock to <= 96 kHz because this is
				 * more likely to be received next time.
				 */
				reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
				reg |= OXYGEN_SPDIF_IN_CLOCK_96;
				oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
			}
		}
	}
	spin_unlock_irq(&chip->reg_lock);

	if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
		spin_lock_irq(&chip->reg_lock);
		chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
		oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
			       chip->interrupt_mask);
		spin_unlock_irq(&chip->reg_lock);

		/*
		 * We don't actually know that any channel status bits have
		 * changed, but let's send a notification just to be sure.
		 */
		snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
			       &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
	}
}

#ifdef CONFIG_PROC_FS
static void oxygen_proc_read(struct snd_info_entry *entry,
			     struct snd_info_buffer *buffer)
{
	struct oxygen *chip = entry->private_data;
	int i, j;

	snd_iprintf(buffer, "CMI8788\n\n");
	for (i = 0; i < 0x100; i += 0x10) {
		snd_iprintf(buffer, "%02x:", i);
		for (j = 0; j < 0x10; ++j)
			snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
		snd_iprintf(buffer, "\n");
	}
	if (mutex_lock_interruptible(&chip->mutex) < 0)
		return;
	if (chip->has_ac97_0) {
		snd_iprintf(buffer, "\nAC97\n");
		for (i = 0; i < 0x80; i += 0x10) {
			snd_iprintf(buffer, "%02x:", i);
			for (j = 0; j < 0x10; j += 2)
				snd_iprintf(buffer, " %04x",
					    oxygen_read_ac97(chip, 0, i + j));
			snd_iprintf(buffer, "\n");
		}
	}
	if (chip->has_ac97_1) {
		snd_iprintf(buffer, "\nAC97 2\n");
		for (i = 0; i < 0x80; i += 0x10) {
			snd_iprintf(buffer, "%02x:", i);
			for (j = 0; j < 0x10; j += 2)
				snd_iprintf(buffer, " %04x",
					    oxygen_read_ac97(chip, 1, i + j));
			snd_iprintf(buffer, "\n");
		}
	}
	mutex_unlock(&chip->mutex);
}

static void __devinit oxygen_proc_init(struct oxygen *chip)
{
	struct snd_info_entry *entry;

	if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
		snd_info_set_text_ops(entry, chip, oxygen_proc_read);
}
#else
#define oxygen_proc_init(chip)
#endif

static void __devinit oxygen_init(struct oxygen *chip)
{
	unsigned int i;

	chip->dac_routing = 1;
	for (i = 0; i < 8; ++i)
		chip->dac_volume[i] = 0xff;
	chip->spdif_playback_enable = 1;
	chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
		(IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
	chip->spdif_pcm_bits = chip->spdif_bits;

	if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
		chip->revision = 2;
	else
		chip->revision = 1;

	if (chip->revision == 1)
		oxygen_set_bits8(chip, OXYGEN_MISC,
				 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);

	i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
	chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
	chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;

	oxygen_set_bits8(chip, OXYGEN_FUNCTION,
			 OXYGEN_FUNCTION_RESET_CODEC |
			 chip->model->function_flags);
	oxygen_write8_masked(chip, OXYGEN_FUNCTION,
			     OXYGEN_FUNCTION_SPI,
			     OXYGEN_FUNCTION_2WIRE_SPI_MASK);
	oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
	oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
	oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
		      OXYGEN_PLAY_CHANNELS_2 |
		      OXYGEN_DMA_A_BURST_8 |
		      OXYGEN_DMA_MULTICH_BURST_8);
	oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
	oxygen_write8_masked(chip, OXYGEN_MISC, 0,
			     OXYGEN_MISC_WRITE_PCI_SUBID |
			     OXYGEN_MISC_REC_C_FROM_SPDIF |
			     OXYGEN_MISC_REC_B_FROM_AC97 |
			     OXYGEN_MISC_REC_A_FROM_MULTICH);
	oxygen_write8(chip, OXYGEN_REC_FORMAT,
		      (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
		      (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
		      (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
	oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
		      (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
		      (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
	oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
	oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
		       OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
		       OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
		       OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
	oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
		       OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
		       OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
		       OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
	oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
		       OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
		       OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
		       OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
	oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
		       OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
		       OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
		       OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
	oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
			      OXYGEN_SPDIF_SENSE_MASK |
			      OXYGEN_SPDIF_LOCK_MASK |
			      OXYGEN_SPDIF_RATE_MASK |
			      OXYGEN_SPDIF_LOCK_PAR |
			      OXYGEN_SPDIF_IN_CLOCK_96,
			      OXYGEN_SPDIF_OUT_ENABLE |
			      OXYGEN_SPDIF_LOOPBACK |
			      OXYGEN_SPDIF_SENSE_MASK |
			      OXYGEN_SPDIF_LOCK_MASK |
			      OXYGEN_SPDIF_RATE_MASK |
			      OXYGEN_SPDIF_SENSE_PAR |
			      OXYGEN_SPDIF_LOCK_PAR |
			      OXYGEN_SPDIF_IN_CLOCK_MASK);
	oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
	oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
	oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
	oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
	oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
		       OXYGEN_PLAY_MULTICH_I2S_DAC |
		       OXYGEN_PLAY_SPDIF_SPDIF |
		       (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
		       (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
		       (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
		       (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
	oxygen_write8(chip, OXYGEN_REC_ROUTING,
		      OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
		      OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
		      OXYGEN_REC_C_ROUTE_SPDIF);
	oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
	oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
		      (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
		      (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
		      (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
		      (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));

	oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
	oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
	oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
	if (!(chip->has_ac97_0 | chip->has_ac97_1))
		oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
				  OXYGEN_AC97_CLOCK_DISABLE);
	if (!chip->has_ac97_0) {
		oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
				  OXYGEN_AC97_NO_CODEC_0);
	} else {
		oxygen_write_ac97(chip, 0, AC97_RESET, 0);
		msleep(1);
		oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
				     CM9780_GPIO0IO | CM9780_GPIO1IO);
		oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
				     CM9780_BSTSEL | CM9780_STRO_MIC |
				     CM9780_MIX2FR | CM9780_PCBSW);
		oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
				     CM9780_RSOE | CM9780_CBOE |
				     CM9780_SSOE | CM9780_FROE |
				     CM9780_MIC2MIC | CM9780_LI2LI);
		oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
		oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
		oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
		oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
		oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
		oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
		oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
		oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
		oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
		oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
		/* power down unused ADCs and DACs */
		oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
				     AC97_PD_PR0 | AC97_PD_PR1);
		oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
				     AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
	}
	if (chip->has_ac97_1) {
		oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
				  OXYGEN_AC97_CODEC1_SLOT3 |
				  OXYGEN_AC97_CODEC1_SLOT4);
		oxygen_write_ac97(chip, 1, AC97_RESET, 0);
		msleep(1);
		oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
		oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
		oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
		oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
		oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
		oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
		oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
		oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
		oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
		oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
		oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x8000);
		oxygen_ac97_clear_bits(chip, 1, AC97_REC_GAIN, 0x1c00);
		oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
	}
}

static void oxygen_card_free(struct snd_card *card)
{
	struct oxygen *chip = card->private_data;

	spin_lock_irq(&chip->reg_lock);
	chip->interrupt_mask = 0;
	chip->pcm_running = 0;
	oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
	oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
	spin_unlock_irq(&chip->reg_lock);
	if (chip->irq >= 0) {
		free_irq(chip->irq, chip);
		synchronize_irq(chip->irq);
	}
	flush_scheduled_work();
	chip->model->cleanup(chip);
	mutex_destroy(&chip->mutex);
	pci_release_regions(chip->pci);
	pci_disable_device(chip->pci);
}

int __devinit oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
			       int midi, const struct oxygen_model *model)
{
	struct snd_card *card;
	struct oxygen *chip;
	int err;

	card = snd_card_new(index, id, model->owner,
			    sizeof *chip + model->model_data_size);
	if (!card)
		return -ENOMEM;

	chip = card->private_data;
	chip->card = card;
	chip->pci = pci;
	chip->irq = -1;
	chip->model = model;
	chip->model_data = chip + 1;
	spin_lock_init(&chip->reg_lock);
	mutex_init(&chip->mutex);
	INIT_WORK(&chip->spdif_input_bits_work,
		  oxygen_spdif_input_bits_changed);

	err = pci_enable_device(pci);
	if (err < 0)
		goto err_card;

	err = pci_request_regions(pci, model->chip);
	if (err < 0) {
		snd_printk(KERN_ERR "cannot reserve PCI resources\n");
		goto err_pci_enable;
	}

	if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
	    pci_resource_len(pci, 0) < 0x100) {
		snd_printk(KERN_ERR "invalid PCI I/O range\n");
		err = -ENXIO;
		goto err_pci_regions;
	}
	chip->addr = pci_resource_start(pci, 0);

	pci_set_master(pci);
	snd_card_set_dev(card, &pci->dev);
	card->private_free = oxygen_card_free;

	oxygen_init(chip);
	model->init(chip);

	err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
			  model->chip, chip);
	if (err < 0) {
		snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
		goto err_card;
	}
	chip->irq = pci->irq;

	strcpy(card->driver, model->chip);
	strcpy(card->shortname, model->shortname);
	sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
		model->longname, chip->revision, chip->addr, chip->irq);
	strcpy(card->mixername, model->chip);
	snd_component_add(card, model->chip);

	err = oxygen_pcm_init(chip);
	if (err < 0)
		goto err_card;

	err = oxygen_mixer_init(chip);
	if (err < 0)
		goto err_card;

	oxygen_write8_masked(chip, OXYGEN_MISC,
			     midi ? OXYGEN_MISC_MIDI : 0, OXYGEN_MISC_MIDI);
	if (midi) {
		err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
					  chip->addr + OXYGEN_MPU401,
					  MPU401_INFO_INTEGRATED, 0, 0,
					  &chip->midi);
		if (err < 0)
			goto err_card;
	}

	oxygen_proc_init(chip);

	spin_lock_irq(&chip->reg_lock);
	chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
	oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
	spin_unlock_irq(&chip->reg_lock);

	err = snd_card_register(card);
	if (err < 0)
		goto err_card;

	pci_set_drvdata(pci, card);
	return 0;

err_pci_regions:
	pci_release_regions(pci);
err_pci_enable:
	pci_disable_device(pci);
err_card:
	snd_card_free(card);
	return err;
}
EXPORT_SYMBOL(oxygen_pci_probe);

void __devexit oxygen_pci_remove(struct pci_dev *pci)
{
	snd_card_free(pci_get_drvdata(pci));
	pci_set_drvdata(pci, NULL);
}
EXPORT_SYMBOL(oxygen_pci_remove);
Commit	Line	Data
d0ce9946 CL	1	/*
	2	* C-Media CMI8788 driver - main driver module
	3	*
	4	* Copyright (c) Clemens Ladisch <clemens@ladisch.de>
	5	*
	6	*
	7	* This driver is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License, version 2.
	9	*
	10	* This driver is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this driver; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
d0ce9946 CL	20	#include <linux/delay.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/mutex.h>
	23	#include <linux/pci.h>
	24	#include <sound/ac97_codec.h>
	25	#include <sound/asoundef.h>
	26	#include <sound/core.h>
	27	#include <sound/info.h>
	28	#include <sound/mpu401.h>
	29	#include <sound/pcm.h>
	30	#include "oxygen.h"
878ac3ee	31	#include "cm9780.h"
d0ce9946 CL	32
	33	MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
	34	MODULE_DESCRIPTION("C-Media CMI8788 helper library");
	35	MODULE_LICENSE("GPL");
	36
	37
	38	static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
	39	{
	40	struct oxygen *chip = dev_id;
	41	unsigned int status, clear, elapsed_streams, i;
	42
	43	status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
	44	if (!status)
	45	return IRQ_NONE;
	46
	47	spin_lock(&chip->reg_lock);
	48
	49	clear = status & (OXYGEN_CHANNEL_A \|
	50	OXYGEN_CHANNEL_B \|
	51	OXYGEN_CHANNEL_C \|
	52	OXYGEN_CHANNEL_SPDIF \|
	53	OXYGEN_CHANNEL_MULTICH \|
	54	OXYGEN_CHANNEL_AC97 \|
c2353a08	55	OXYGEN_INT_SPDIF_IN_DETECT \|
d0ce9946 CL	56	OXYGEN_INT_GPIO);
d0ce9946 CL	57	if (clear) {
c2353a08 CL	58	if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
c2353a08 CL	59	chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
d0ce9946 CL	60	oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
	61	chip->interrupt_mask & ~clear);
	62	oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
	63	chip->interrupt_mask);
	64	}
	65
	66	elapsed_streams = status & chip->pcm_running;
	67
	68	spin_unlock(&chip->reg_lock);
	69
	70	for (i = 0; i < PCM_COUNT; ++i)
	71	if ((elapsed_streams & (1 << i)) && chip->streams[i])
	72	snd_pcm_period_elapsed(chip->streams[i]);
	73
c2353a08	74	if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
d0ce9946 CL	75	spin_lock(&chip->reg_lock);
d0ce9946 CL	76	i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
7f0b8946 CL	77	if (i & (OXYGEN_SPDIF_SENSE_INT \| OXYGEN_SPDIF_LOCK_INT \|
	78	OXYGEN_SPDIF_RATE_INT)) {
	79	/* write the interrupt bit(s) to clear */
d0ce9946 CL	80	oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
	81	schedule_work(&chip->spdif_input_bits_work);
	82	}
	83	spin_unlock(&chip->reg_lock);
	84	}
	85
	86	if (status & OXYGEN_INT_GPIO)
	87	;
	88
	89	if ((status & OXYGEN_INT_MIDI) && chip->midi)
	90	snd_mpu401_uart_interrupt(0, chip->midi->private_data);
	91
	92	return IRQ_HANDLED;
	93	}
	94
	95	static void oxygen_spdif_input_bits_changed(struct work_struct *work)
	96	{
	97	struct oxygen *chip = container_of(work, struct oxygen,
	98	spdif_input_bits_work);
7f0b8946	99	u32 reg;
d0ce9946	100
7f0b8946 CL	101	/*
	102	* This function gets called when there is new activity on the SPDIF
	103	* input, or when we lose lock on the input signal, or when the rate
	104	* changes.
	105	*/
d0ce9946	106	msleep(1);
7f0b8946 CL	107	spin_lock_irq(&chip->reg_lock);
	108	reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
	109	if ((reg & (OXYGEN_SPDIF_SENSE_STATUS \|
	110	OXYGEN_SPDIF_LOCK_STATUS))
	111	== OXYGEN_SPDIF_SENSE_STATUS) {
	112	/*
	113	* If we detect activity on the SPDIF input but cannot lock to
	114	* a signal, the clock bit is likely to be wrong.
	115	*/
	116	reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
	117	oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
d0ce9946 CL	118	spin_unlock_irq(&chip->reg_lock);
d0ce9946 CL	119	msleep(1);
7f0b8946 CL	120	spin_lock_irq(&chip->reg_lock);
	121	reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
	122	if ((reg & (OXYGEN_SPDIF_SENSE_STATUS \|
	123	OXYGEN_SPDIF_LOCK_STATUS))
	124	== OXYGEN_SPDIF_SENSE_STATUS) {
	125	/* nothing detected with either clock; give up */
	126	if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
	127	== OXYGEN_SPDIF_IN_CLOCK_192) {
	128	/*
	129	* Reset clock to <= 96 kHz because this is
	130	* more likely to be received next time.
	131	*/
	132	reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
	133	reg \|= OXYGEN_SPDIF_IN_CLOCK_96;
	134	oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
	135	}
d0ce9946 CL	136	}
d0ce9946 CL	137	}
7f0b8946	138	spin_unlock_irq(&chip->reg_lock);
d0ce9946	139
01a3affb	140	if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
d0ce9946	141	spin_lock_irq(&chip->reg_lock);
c2353a08	142	chip->interrupt_mask \|= OXYGEN_INT_SPDIF_IN_DETECT;
d0ce9946 CL	143	oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
	144	chip->interrupt_mask);
	145	spin_unlock_irq(&chip->reg_lock);
	146
7f0b8946 CL	147	/*
	148	* We don't actually know that any channel status bits have
	149	* changed, but let's send a notification just to be sure.
	150	*/
d0ce9946	151	snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
01a3affb	152	&chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
d0ce9946 CL	153	}
	154	}
	155
	156	#ifdef CONFIG_PROC_FS
	157	static void oxygen_proc_read(struct snd_info_entry *entry,
	158	struct snd_info_buffer *buffer)
	159	{
	160	struct oxygen *chip = entry->private_data;
	161	int i, j;
	162
	163	snd_iprintf(buffer, "CMI8788\n\n");
	164	for (i = 0; i < 0x100; i += 0x10) {
	165	snd_iprintf(buffer, "%02x:", i);
	166	for (j = 0; j < 0x10; ++j)
	167	snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
	168	snd_iprintf(buffer, "\n");
	169	}
	170	if (mutex_lock_interruptible(&chip->mutex) < 0)
	171	return;
31c77643 CL	172	if (chip->has_ac97_0) {
	173	snd_iprintf(buffer, "\nAC97\n");
	174	for (i = 0; i < 0x80; i += 0x10) {
	175	snd_iprintf(buffer, "%02x:", i);
	176	for (j = 0; j < 0x10; j += 2)
	177	snd_iprintf(buffer, " %04x",
	178	oxygen_read_ac97(chip, 0, i + j));
	179	snd_iprintf(buffer, "\n");
	180	}
	181	}
	182	if (chip->has_ac97_1) {
	183	snd_iprintf(buffer, "\nAC97 2\n");
	184	for (i = 0; i < 0x80; i += 0x10) {
	185	snd_iprintf(buffer, "%02x:", i);
	186	for (j = 0; j < 0x10; j += 2)
	187	snd_iprintf(buffer, " %04x",
	188	oxygen_read_ac97(chip, 1, i + j));
	189	snd_iprintf(buffer, "\n");
	190	}
d0ce9946 CL	191	}
	192	mutex_unlock(&chip->mutex);
	193	}
	194
	195	static void __devinit oxygen_proc_init(struct oxygen *chip)
	196	{
	197	struct snd_info_entry *entry;
	198
	199	if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
	200	snd_info_set_text_ops(entry, chip, oxygen_proc_read);
	201	}
	202	#else
	203	#define oxygen_proc_init(chip)
	204	#endif
	205
	206	static void __devinit oxygen_init(struct oxygen *chip)
	207	{
	208	unsigned int i;
	209
	210	chip->dac_routing = 1;
	211	for (i = 0; i < 8; ++i)
	212	chip->dac_volume[i] = 0xff;
	213	chip->spdif_playback_enable = 1;
	214	chip->spdif_bits = OXYGEN_SPDIF_C \| OXYGEN_SPDIF_ORIGINAL \|
	215	(IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
	216	chip->spdif_pcm_bits = chip->spdif_bits;
	217
	218	if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
	219	chip->revision = 2;
	220	else
	221	chip->revision = 1;
	222
	223	if (chip->revision == 1)
c2353a08 CL	224	oxygen_set_bits8(chip, OXYGEN_MISC,
c2353a08 CL	225	OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
d0ce9946	226
31c77643 CL	227	i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
	228	chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
	229	chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
	230
d0ce9946 CL	231	oxygen_set_bits8(chip, OXYGEN_FUNCTION,
d0ce9946 CL	232	OXYGEN_FUNCTION_RESET_CODEC \|
84aa6b7b	233	chip->model->function_flags);
b78e3dbb CL	234	oxygen_write8_masked(chip, OXYGEN_FUNCTION,
	235	OXYGEN_FUNCTION_SPI,
	236	OXYGEN_FUNCTION_2WIRE_SPI_MASK);
	237	oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
	238	oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
	239	oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
	240	OXYGEN_PLAY_CHANNELS_2 \|
	241	OXYGEN_DMA_A_BURST_8 \|
	242	OXYGEN_DMA_MULTICH_BURST_8);
	243	oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
	244	oxygen_write8_masked(chip, OXYGEN_MISC, 0,
	245	OXYGEN_MISC_WRITE_PCI_SUBID \|
	246	OXYGEN_MISC_REC_C_FROM_SPDIF \|
	247	OXYGEN_MISC_REC_B_FROM_AC97 \|
	248	OXYGEN_MISC_REC_A_FROM_MULTICH);
	249	oxygen_write8(chip, OXYGEN_REC_FORMAT,
	250	(OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) \|
	251	(OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) \|
	252	(OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
	253	oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
	254	(OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) \|
	255	(OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
	256	oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
c9946b2c CL	257	oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
	258	OXYGEN_RATE_48000 \| OXYGEN_I2S_FORMAT_LJUST \|
	259	OXYGEN_I2S_MCLK_128 \| OXYGEN_I2S_BITS_16 \|
	260	OXYGEN_I2S_MASTER \| OXYGEN_I2S_BCLK_64);
	261	oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
	262	OXYGEN_RATE_48000 \| OXYGEN_I2S_FORMAT_LJUST \|
	263	OXYGEN_I2S_MCLK_128 \| OXYGEN_I2S_BITS_16 \|
	264	OXYGEN_I2S_MASTER \| OXYGEN_I2S_BCLK_64);
	265	oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
	266	OXYGEN_RATE_48000 \| OXYGEN_I2S_FORMAT_LJUST \|
	267	OXYGEN_I2S_MCLK_128 \| OXYGEN_I2S_BITS_16 \|
	268	OXYGEN_I2S_MASTER \| OXYGEN_I2S_BCLK_64);
	269	oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
	270	OXYGEN_RATE_48000 \| OXYGEN_I2S_FORMAT_LJUST \|
	271	OXYGEN_I2S_MCLK_128 \| OXYGEN_I2S_BITS_16 \|
	272	OXYGEN_I2S_MASTER \| OXYGEN_I2S_BCLK_64);
7f0b8946 CL	273	oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
	274	OXYGEN_SPDIF_SENSE_MASK \|
	275	OXYGEN_SPDIF_LOCK_MASK \|
	276	OXYGEN_SPDIF_RATE_MASK \|
	277	OXYGEN_SPDIF_LOCK_PAR \|
	278	OXYGEN_SPDIF_IN_CLOCK_96,
	279	OXYGEN_SPDIF_OUT_ENABLE \|
	280	OXYGEN_SPDIF_LOOPBACK \|
	281	OXYGEN_SPDIF_SENSE_MASK \|
	282	OXYGEN_SPDIF_LOCK_MASK \|
	283	OXYGEN_SPDIF_RATE_MASK \|
	284	OXYGEN_SPDIF_SENSE_PAR \|
	285	OXYGEN_SPDIF_LOCK_PAR \|
	286	OXYGEN_SPDIF_IN_CLOCK_MASK);
d0ce9946	287	oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
b78e3dbb CL	288	oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
	289	oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
	290	oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
c9946b2c	291	oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
b78e3dbb CL	292	OXYGEN_PLAY_MULTICH_I2S_DAC \|
b78e3dbb CL	293	OXYGEN_PLAY_SPDIF_SPDIF \|
c9946b2c CL	294	(0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) \|
	295	(1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) \|
	296	(2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) \|
	297	(3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
	298	oxygen_write8(chip, OXYGEN_REC_ROUTING,
	299	OXYGEN_REC_A_ROUTE_I2S_ADC_1 \|
b78e3dbb	300	OXYGEN_REC_B_ROUTE_I2S_ADC_2 \|
c9946b2c CL	301	OXYGEN_REC_C_ROUTE_SPDIF);
	302	oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
	303	oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
	304	(0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) \|
	305	(1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) \|
	306	(2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) \|
	307	(3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
d0ce9946	308
c9946b2c	309	oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
b78e3dbb CL	310	oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
	311	oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
	312	if (!(chip->has_ac97_0 \| chip->has_ac97_1))
	313	oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
	314	OXYGEN_AC97_CLOCK_DISABLE);
	315	if (!chip->has_ac97_0) {
	316	oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
	317	OXYGEN_AC97_NO_CODEC_0);
	318	} else {
31c77643 CL	319	oxygen_write_ac97(chip, 0, AC97_RESET, 0);
31c77643 CL	320	msleep(1);
878ac3ee CL	321	oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
	322	CM9780_GPIO0IO \| CM9780_GPIO1IO);
	323	oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
	324	CM9780_BSTSEL \| CM9780_STRO_MIC \|
	325	CM9780_MIX2FR \| CM9780_PCBSW);
	326	oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
	327	CM9780_RSOE \| CM9780_CBOE \|
	328	CM9780_SSOE \| CM9780_FROE \|
	329	CM9780_MIC2MIC \| CM9780_LI2LI);
31c77643 CL	330	oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
	331	oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
	332	oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
	333	oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
	334	oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
	335	oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
	336	oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
	337	oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
	338	oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
	339	oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
31c77643 CL	340	/* power down unused ADCs and DACs */
	341	oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
	342	AC97_PD_PR0 \| AC97_PD_PR1);
	343	oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
	344	AC97_EA_PRI \| AC97_EA_PRJ \| AC97_EA_PRK);
	345	}
b78e3dbb CL	346	if (chip->has_ac97_1) {
	347	oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
	348	OXYGEN_AC97_CODEC1_SLOT3 \|
	349	OXYGEN_AC97_CODEC1_SLOT4);
	350	oxygen_write_ac97(chip, 1, AC97_RESET, 0);
	351	msleep(1);
	352	oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
	353	oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
	354	oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
	355	oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
	356	oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
	357	oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
	358	oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
	359	oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
	360	oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
	361	oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
	362	oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x8000);
	363	oxygen_ac97_clear_bits(chip, 1, AC97_REC_GAIN, 0x1c00);
	364	oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
	365	}
d0ce9946 CL	366	}
	367
	368	static void oxygen_card_free(struct snd_card *card)
	369	{
	370	struct oxygen *chip = card->private_data;
	371
	372	spin_lock_irq(&chip->reg_lock);
	373	chip->interrupt_mask = 0;
	374	chip->pcm_running = 0;
	375	oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
	376	oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
	377	spin_unlock_irq(&chip->reg_lock);
	378	if (chip->irq >= 0) {
	379	free_irq(chip->irq, chip);
	380	synchronize_irq(chip->irq);
	381	}
	382	flush_scheduled_work();
	383	chip->model->cleanup(chip);
	384	mutex_destroy(&chip->mutex);
	385	pci_release_regions(chip->pci);
	386	pci_disable_device(chip->pci);
	387	}
	388
	389	int __devinit oxygen_pci_probe(struct pci_dev pci, int index, char id,
44fb7aae	390	int midi, const struct oxygen_model *model)
d0ce9946 CL	391	{
	392	struct snd_card *card;
	393	struct oxygen *chip;
	394	int err;
	395
7ef37cd9 CL	396	card = snd_card_new(index, id, model->owner,
7ef37cd9 CL	397	sizeof *chip + model->model_data_size);
d0ce9946 CL	398	if (!card)
	399	return -ENOMEM;
	400
	401	chip = card->private_data;
	402	chip->card = card;
	403	chip->pci = pci;
	404	chip->irq = -1;
	405	chip->model = model;
7ef37cd9	406	chip->model_data = chip + 1;
d0ce9946 CL	407	spin_lock_init(&chip->reg_lock);
	408	mutex_init(&chip->mutex);
	409	INIT_WORK(&chip->spdif_input_bits_work,
	410	oxygen_spdif_input_bits_changed);
	411
	412	err = pci_enable_device(pci);
	413	if (err < 0)
	414	goto err_card;
	415
	416	err = pci_request_regions(pci, model->chip);
	417	if (err < 0) {
	418	snd_printk(KERN_ERR "cannot reserve PCI resources\n");
	419	goto err_pci_enable;
	420	}
	421
	422	if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) \|\|
	423	pci_resource_len(pci, 0) < 0x100) {
	424	snd_printk(KERN_ERR "invalid PCI I/O range\n");
	425	err = -ENXIO;
	426	goto err_pci_regions;
	427	}
	428	chip->addr = pci_resource_start(pci, 0);
	429
	430	pci_set_master(pci);
	431	snd_card_set_dev(card, &pci->dev);
	432	card->private_free = oxygen_card_free;
	433
	434	oxygen_init(chip);
	435	model->init(chip);
	436
	437	err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
	438	model->chip, chip);
	439	if (err < 0) {
	440	snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
	441	goto err_card;
	442	}
	443	chip->irq = pci->irq;
	444
	445	strcpy(card->driver, model->chip);
	446	strcpy(card->shortname, model->shortname);
	447	sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
	448	model->longname, chip->revision, chip->addr, chip->irq);
	449	strcpy(card->mixername, model->chip);
	450	snd_component_add(card, model->chip);
	451
	452	err = oxygen_pcm_init(chip);
	453	if (err < 0)
	454	goto err_card;
	455
	456	err = oxygen_mixer_init(chip);
	457	if (err < 0)
	458	goto err_card;
	459
44fb7aae CL	460	oxygen_write8_masked(chip, OXYGEN_MISC,
	461	midi ? OXYGEN_MISC_MIDI : 0, OXYGEN_MISC_MIDI);
	462	if (midi) {
d0ce9946 CL	463	err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
	464	chip->addr + OXYGEN_MPU401,
	465	MPU401_INFO_INTEGRATED, 0, 0,
	466	&chip->midi);
	467	if (err < 0)
	468	goto err_card;
	469	}
	470
	471	oxygen_proc_init(chip);
	472
	473	spin_lock_irq(&chip->reg_lock);
c2353a08	474	chip->interrupt_mask \|= OXYGEN_INT_SPDIF_IN_DETECT;
d0ce9946 CL	475	oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
	476	spin_unlock_irq(&chip->reg_lock);
	477
	478	err = snd_card_register(card);
	479	if (err < 0)
	480	goto err_card;
	481
	482	pci_set_drvdata(pci, card);
	483	return 0;
	484
	485	err_pci_regions:
	486	pci_release_regions(pci);
	487	err_pci_enable:
	488	pci_disable_device(pci);
	489	err_card:
	490	snd_card_free(card);
	491	return err;
	492	}
	493	EXPORT_SYMBOL(oxygen_pci_probe);
	494
	495	void __devexit oxygen_pci_remove(struct pci_dev *pci)
	496	{
	497	snd_card_free(pci_get_drvdata(pci));
	498	pci_set_drvdata(pci, NULL);
	499	}
	500	EXPORT_SYMBOL(oxygen_pci_remove);