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d0ce9946 CL |
1 | /* |
2 | * C-Media CMI8788 driver - main driver module | |
3 | * | |
4 | * Copyright (c) Clemens Ladisch <clemens@ladisch.de> | |
5 | * | |
6 | * | |
7 | * This driver is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License, version 2. | |
9 | * | |
10 | * This driver is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this driver; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
d0ce9946 CL |
20 | #include <linux/delay.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/mutex.h> | |
23 | #include <linux/pci.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
da155d5b | 25 | #include <linux/module.h> |
d0ce9946 CL |
26 | #include <sound/ac97_codec.h> |
27 | #include <sound/asoundef.h> | |
28 | #include <sound/core.h> | |
29 | #include <sound/info.h> | |
30 | #include <sound/mpu401.h> | |
31 | #include <sound/pcm.h> | |
32 | #include "oxygen.h" | |
878ac3ee | 33 | #include "cm9780.h" |
d0ce9946 CL |
34 | |
35 | MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); | |
36 | MODULE_DESCRIPTION("C-Media CMI8788 helper library"); | |
d023dc0a | 37 | MODULE_LICENSE("GPL v2"); |
d0ce9946 | 38 | |
a69bb3c3 | 39 | #define DRIVER "oxygen" |
d0ce9946 | 40 | |
397b1dcc CL |
41 | static inline int oxygen_uart_input_ready(struct oxygen *chip) |
42 | { | |
43 | return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY); | |
44 | } | |
45 | ||
46 | static void oxygen_read_uart(struct oxygen *chip) | |
47 | { | |
48 | if (unlikely(!oxygen_uart_input_ready(chip))) { | |
49 | /* no data, but read it anyway to clear the interrupt */ | |
50 | oxygen_read8(chip, OXYGEN_MPU401); | |
51 | return; | |
52 | } | |
53 | do { | |
54 | u8 data = oxygen_read8(chip, OXYGEN_MPU401); | |
55 | if (data == MPU401_ACK) | |
56 | continue; | |
57 | if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input)) | |
58 | chip->uart_input_count = 0; | |
59 | chip->uart_input[chip->uart_input_count++] = data; | |
60 | } while (oxygen_uart_input_ready(chip)); | |
61 | if (chip->model.uart_input) | |
62 | chip->model.uart_input(chip); | |
63 | } | |
64 | ||
d0ce9946 CL |
65 | static irqreturn_t oxygen_interrupt(int dummy, void *dev_id) |
66 | { | |
67 | struct oxygen *chip = dev_id; | |
68 | unsigned int status, clear, elapsed_streams, i; | |
69 | ||
70 | status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS); | |
71 | if (!status) | |
72 | return IRQ_NONE; | |
73 | ||
74 | spin_lock(&chip->reg_lock); | |
75 | ||
76 | clear = status & (OXYGEN_CHANNEL_A | | |
77 | OXYGEN_CHANNEL_B | | |
78 | OXYGEN_CHANNEL_C | | |
79 | OXYGEN_CHANNEL_SPDIF | | |
80 | OXYGEN_CHANNEL_MULTICH | | |
81 | OXYGEN_CHANNEL_AC97 | | |
c2353a08 | 82 | OXYGEN_INT_SPDIF_IN_DETECT | |
1e821dd2 CL |
83 | OXYGEN_INT_GPIO | |
84 | OXYGEN_INT_AC97); | |
d0ce9946 | 85 | if (clear) { |
c2353a08 CL |
86 | if (clear & OXYGEN_INT_SPDIF_IN_DETECT) |
87 | chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT; | |
d0ce9946 CL |
88 | oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, |
89 | chip->interrupt_mask & ~clear); | |
90 | oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, | |
91 | chip->interrupt_mask); | |
92 | } | |
93 | ||
94 | elapsed_streams = status & chip->pcm_running; | |
95 | ||
96 | spin_unlock(&chip->reg_lock); | |
97 | ||
98 | for (i = 0; i < PCM_COUNT; ++i) | |
99 | if ((elapsed_streams & (1 << i)) && chip->streams[i]) | |
100 | snd_pcm_period_elapsed(chip->streams[i]); | |
101 | ||
c2353a08 | 102 | if (status & OXYGEN_INT_SPDIF_IN_DETECT) { |
d0ce9946 CL |
103 | spin_lock(&chip->reg_lock); |
104 | i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); | |
7f0b8946 CL |
105 | if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT | |
106 | OXYGEN_SPDIF_RATE_INT)) { | |
107 | /* write the interrupt bit(s) to clear */ | |
d0ce9946 CL |
108 | oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i); |
109 | schedule_work(&chip->spdif_input_bits_work); | |
110 | } | |
111 | spin_unlock(&chip->reg_lock); | |
112 | } | |
113 | ||
114 | if (status & OXYGEN_INT_GPIO) | |
7c014159 | 115 | schedule_work(&chip->gpio_work); |
d0ce9946 | 116 | |
397b1dcc CL |
117 | if (status & OXYGEN_INT_MIDI) { |
118 | if (chip->midi) | |
119 | snd_mpu401_uart_interrupt(0, chip->midi->private_data); | |
120 | else | |
121 | oxygen_read_uart(chip); | |
122 | } | |
d0ce9946 | 123 | |
1e821dd2 CL |
124 | if (status & OXYGEN_INT_AC97) |
125 | wake_up(&chip->ac97_waitqueue); | |
126 | ||
d0ce9946 CL |
127 | return IRQ_HANDLED; |
128 | } | |
129 | ||
130 | static void oxygen_spdif_input_bits_changed(struct work_struct *work) | |
131 | { | |
132 | struct oxygen *chip = container_of(work, struct oxygen, | |
133 | spdif_input_bits_work); | |
7f0b8946 | 134 | u32 reg; |
d0ce9946 | 135 | |
7f0b8946 CL |
136 | /* |
137 | * This function gets called when there is new activity on the SPDIF | |
138 | * input, or when we lose lock on the input signal, or when the rate | |
139 | * changes. | |
140 | */ | |
d0ce9946 | 141 | msleep(1); |
7f0b8946 CL |
142 | spin_lock_irq(&chip->reg_lock); |
143 | reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); | |
144 | if ((reg & (OXYGEN_SPDIF_SENSE_STATUS | | |
145 | OXYGEN_SPDIF_LOCK_STATUS)) | |
146 | == OXYGEN_SPDIF_SENSE_STATUS) { | |
147 | /* | |
148 | * If we detect activity on the SPDIF input but cannot lock to | |
149 | * a signal, the clock bit is likely to be wrong. | |
150 | */ | |
151 | reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK; | |
152 | oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg); | |
d0ce9946 CL |
153 | spin_unlock_irq(&chip->reg_lock); |
154 | msleep(1); | |
7f0b8946 CL |
155 | spin_lock_irq(&chip->reg_lock); |
156 | reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); | |
157 | if ((reg & (OXYGEN_SPDIF_SENSE_STATUS | | |
158 | OXYGEN_SPDIF_LOCK_STATUS)) | |
159 | == OXYGEN_SPDIF_SENSE_STATUS) { | |
160 | /* nothing detected with either clock; give up */ | |
161 | if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK) | |
162 | == OXYGEN_SPDIF_IN_CLOCK_192) { | |
163 | /* | |
164 | * Reset clock to <= 96 kHz because this is | |
165 | * more likely to be received next time. | |
166 | */ | |
167 | reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK; | |
168 | reg |= OXYGEN_SPDIF_IN_CLOCK_96; | |
169 | oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg); | |
170 | } | |
d0ce9946 CL |
171 | } |
172 | } | |
7f0b8946 | 173 | spin_unlock_irq(&chip->reg_lock); |
d0ce9946 | 174 | |
01a3affb | 175 | if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) { |
d0ce9946 | 176 | spin_lock_irq(&chip->reg_lock); |
c2353a08 | 177 | chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT; |
d0ce9946 CL |
178 | oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, |
179 | chip->interrupt_mask); | |
180 | spin_unlock_irq(&chip->reg_lock); | |
181 | ||
7f0b8946 CL |
182 | /* |
183 | * We don't actually know that any channel status bits have | |
184 | * changed, but let's send a notification just to be sure. | |
185 | */ | |
d0ce9946 | 186 | snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, |
01a3affb | 187 | &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id); |
d0ce9946 CL |
188 | } |
189 | } | |
190 | ||
7c014159 CL |
191 | static void oxygen_gpio_changed(struct work_struct *work) |
192 | { | |
193 | struct oxygen *chip = container_of(work, struct oxygen, gpio_work); | |
194 | ||
9bd6a73a CL |
195 | if (chip->model.gpio_changed) |
196 | chip->model.gpio_changed(chip); | |
7c014159 CL |
197 | } |
198 | ||
d0ce9946 CL |
199 | #ifdef CONFIG_PROC_FS |
200 | static void oxygen_proc_read(struct snd_info_entry *entry, | |
201 | struct snd_info_buffer *buffer) | |
202 | { | |
203 | struct oxygen *chip = entry->private_data; | |
204 | int i, j; | |
205 | ||
e2943efa CL |
206 | switch (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_PACKAGE_ID_MASK) { |
207 | case OXYGEN_PACKAGE_ID_8786: i = '6'; break; | |
208 | case OXYGEN_PACKAGE_ID_8787: i = '7'; break; | |
209 | case OXYGEN_PACKAGE_ID_8788: i = '8'; break; | |
210 | default: i = '?'; break; | |
211 | } | |
212 | snd_iprintf(buffer, "CMI878%c:\n", i); | |
c1365007 | 213 | for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) { |
d0ce9946 CL |
214 | snd_iprintf(buffer, "%02x:", i); |
215 | for (j = 0; j < 0x10; ++j) | |
216 | snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j)); | |
217 | snd_iprintf(buffer, "\n"); | |
218 | } | |
219 | if (mutex_lock_interruptible(&chip->mutex) < 0) | |
220 | return; | |
31c77643 | 221 | if (chip->has_ac97_0) { |
9719fcaa | 222 | snd_iprintf(buffer, "\nAC97:\n"); |
31c77643 CL |
223 | for (i = 0; i < 0x80; i += 0x10) { |
224 | snd_iprintf(buffer, "%02x:", i); | |
225 | for (j = 0; j < 0x10; j += 2) | |
226 | snd_iprintf(buffer, " %04x", | |
227 | oxygen_read_ac97(chip, 0, i + j)); | |
228 | snd_iprintf(buffer, "\n"); | |
229 | } | |
230 | } | |
231 | if (chip->has_ac97_1) { | |
9719fcaa | 232 | snd_iprintf(buffer, "\nAC97 2:\n"); |
31c77643 CL |
233 | for (i = 0; i < 0x80; i += 0x10) { |
234 | snd_iprintf(buffer, "%02x:", i); | |
235 | for (j = 0; j < 0x10; j += 2) | |
236 | snd_iprintf(buffer, " %04x", | |
237 | oxygen_read_ac97(chip, 1, i + j)); | |
238 | snd_iprintf(buffer, "\n"); | |
239 | } | |
d0ce9946 CL |
240 | } |
241 | mutex_unlock(&chip->mutex); | |
9719fcaa CL |
242 | if (chip->model.dump_registers) |
243 | chip->model.dump_registers(chip, buffer); | |
d0ce9946 CL |
244 | } |
245 | ||
f007dc04 | 246 | static void oxygen_proc_init(struct oxygen *chip) |
d0ce9946 CL |
247 | { |
248 | struct snd_info_entry *entry; | |
249 | ||
9719fcaa | 250 | if (!snd_card_proc_new(chip->card, "oxygen", &entry)) |
d0ce9946 CL |
251 | snd_info_set_text_ops(entry, chip, oxygen_proc_read); |
252 | } | |
253 | #else | |
254 | #define oxygen_proc_init(chip) | |
255 | #endif | |
256 | ||
30459d7b CL |
257 | static const struct pci_device_id * |
258 | oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[]) | |
259 | { | |
260 | u16 subdevice; | |
261 | ||
262 | /* | |
263 | * Make sure the EEPROM pins are available, i.e., not used for SPI. | |
264 | * (This function is called before we initialize or use SPI.) | |
265 | */ | |
266 | oxygen_clear_bits8(chip, OXYGEN_FUNCTION, | |
267 | OXYGEN_FUNCTION_ENABLE_SPI_4_5); | |
268 | /* | |
269 | * Read the subsystem device ID directly from the EEPROM, because the | |
270 | * chip didn't if the first EEPROM word was overwritten. | |
271 | */ | |
272 | subdevice = oxygen_read_eeprom(chip, 2); | |
92653453 | 273 | /* use default ID if EEPROM is missing */ |
31f86bac | 274 | if (subdevice == 0xffff && oxygen_read_eeprom(chip, 1) == 0xffff) |
92653453 | 275 | subdevice = 0x8788; |
30459d7b CL |
276 | /* |
277 | * We use only the subsystem device ID for searching because it is | |
278 | * unique even without the subsystem vendor ID, which may have been | |
279 | * overwritten in the EEPROM. | |
280 | */ | |
281 | for (; ids->vendor; ++ids) | |
282 | if (ids->subdevice == subdevice && | |
283 | ids->driver_data != BROKEN_EEPROM_DRIVER_DATA) | |
284 | return ids; | |
285 | return NULL; | |
286 | } | |
287 | ||
1275d6f6 CL |
288 | static void oxygen_restore_eeprom(struct oxygen *chip, |
289 | const struct pci_device_id *id) | |
290 | { | |
87b61902 CL |
291 | u16 eeprom_id; |
292 | ||
293 | eeprom_id = oxygen_read_eeprom(chip, 0); | |
294 | if (eeprom_id != OXYGEN_EEPROM_ID && | |
295 | (eeprom_id != 0xffff || id->subdevice != 0x8788)) { | |
1275d6f6 CL |
296 | /* |
297 | * This function gets called only when a known card model has | |
298 | * been detected, i.e., we know there is a valid subsystem | |
299 | * product ID at index 2 in the EEPROM. Therefore, we have | |
300 | * been able to deduce the correct subsystem vendor ID, and | |
301 | * this is enough information to restore the original EEPROM | |
302 | * contents. | |
303 | */ | |
304 | oxygen_write_eeprom(chip, 1, id->subvendor); | |
305 | oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID); | |
306 | ||
307 | oxygen_set_bits8(chip, OXYGEN_MISC, | |
308 | OXYGEN_MISC_WRITE_PCI_SUBID); | |
309 | pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, | |
310 | id->subvendor); | |
311 | pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID, | |
312 | id->subdevice); | |
313 | oxygen_clear_bits8(chip, OXYGEN_MISC, | |
314 | OXYGEN_MISC_WRITE_PCI_SUBID); | |
315 | ||
316 | snd_printk(KERN_INFO "EEPROM ID restored\n"); | |
317 | } | |
318 | } | |
319 | ||
7cb4ced5 | 320 | static void configure_pcie_bridge(struct pci_dev *pci) |
362bc24d | 321 | { |
ebebeece | 322 | enum { PEX811X, PI7C9X110 }; |
7cb4ced5 | 323 | static const struct pci_device_id bridge_ids[] = { |
ebebeece CL |
324 | { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X }, |
325 | { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X }, | |
7cb4ced5 CL |
326 | { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 }, |
327 | { } | |
328 | }; | |
329 | struct pci_dev *bridge; | |
330 | const struct pci_device_id *id; | |
362bc24d CL |
331 | u32 tmp; |
332 | ||
7cb4ced5 CL |
333 | if (!pci->bus || !pci->bus->self) |
334 | return; | |
335 | bridge = pci->bus->self; | |
336 | ||
337 | id = pci_match_id(bridge_ids, bridge); | |
338 | if (!id) | |
339 | return; | |
340 | ||
341 | switch (id->driver_data) { | |
ebebeece CL |
342 | case PEX811X: /* PLX PEX8111/PEX8112 PCIe/PCI bridge */ |
343 | pci_read_config_dword(bridge, 0x48, &tmp); | |
344 | tmp |= 1; /* enable blind prefetching */ | |
345 | tmp |= 1 << 11; /* enable beacon generation */ | |
346 | pci_write_config_dword(bridge, 0x48, tmp); | |
347 | ||
348 | pci_write_config_dword(bridge, 0x84, 0x0c); | |
349 | pci_read_config_dword(bridge, 0x88, &tmp); | |
350 | tmp &= ~(7 << 27); | |
351 | tmp |= 2 << 27; /* set prefetch size to 128 bytes */ | |
352 | pci_write_config_dword(bridge, 0x88, tmp); | |
353 | break; | |
354 | ||
7cb4ced5 CL |
355 | case PI7C9X110: /* Pericom PI7C9X110 PCIe/PCI bridge */ |
356 | pci_read_config_dword(bridge, 0x40, &tmp); | |
357 | tmp |= 1; /* park the PCI arbiter to the sound chip */ | |
358 | pci_write_config_dword(bridge, 0x40, tmp); | |
359 | break; | |
362bc24d CL |
360 | } |
361 | } | |
362 | ||
f007dc04 | 363 | static void oxygen_init(struct oxygen *chip) |
d0ce9946 CL |
364 | { |
365 | unsigned int i; | |
366 | ||
367 | chip->dac_routing = 1; | |
368 | for (i = 0; i < 8; ++i) | |
9bd6a73a | 369 | chip->dac_volume[i] = chip->model.dac_volume_min; |
e983532e | 370 | chip->dac_mute = 1; |
d0ce9946 CL |
371 | chip->spdif_playback_enable = 1; |
372 | chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL | | |
373 | (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT); | |
374 | chip->spdif_pcm_bits = chip->spdif_bits; | |
375 | ||
a1f80fcf | 376 | if (!(oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)) |
c2353a08 CL |
377 | oxygen_set_bits8(chip, OXYGEN_MISC, |
378 | OXYGEN_MISC_PCI_MEM_W_1_CLOCK); | |
d0ce9946 | 379 | |
31c77643 CL |
380 | i = oxygen_read16(chip, OXYGEN_AC97_CONTROL); |
381 | chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0; | |
382 | chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0; | |
383 | ||
b78e3dbb | 384 | oxygen_write8_masked(chip, OXYGEN_FUNCTION, |
87eedd2f | 385 | OXYGEN_FUNCTION_RESET_CODEC | |
9bd6a73a | 386 | chip->model.function_flags, |
87eedd2f CL |
387 | OXYGEN_FUNCTION_RESET_CODEC | |
388 | OXYGEN_FUNCTION_2WIRE_SPI_MASK | | |
389 | OXYGEN_FUNCTION_ENABLE_SPI_4_5); | |
b78e3dbb CL |
390 | oxygen_write8(chip, OXYGEN_DMA_STATUS, 0); |
391 | oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0); | |
392 | oxygen_write8(chip, OXYGEN_PLAY_CHANNELS, | |
393 | OXYGEN_PLAY_CHANNELS_2 | | |
394 | OXYGEN_DMA_A_BURST_8 | | |
395 | OXYGEN_DMA_MULTICH_BURST_8); | |
396 | oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); | |
db12b8e3 | 397 | oxygen_write8_masked(chip, OXYGEN_MISC, |
9bd6a73a | 398 | chip->model.misc_flags, |
b78e3dbb CL |
399 | OXYGEN_MISC_WRITE_PCI_SUBID | |
400 | OXYGEN_MISC_REC_C_FROM_SPDIF | | |
401 | OXYGEN_MISC_REC_B_FROM_AC97 | | |
db12b8e3 CL |
402 | OXYGEN_MISC_REC_A_FROM_MULTICH | |
403 | OXYGEN_MISC_MIDI); | |
b78e3dbb CL |
404 | oxygen_write8(chip, OXYGEN_REC_FORMAT, |
405 | (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) | | |
406 | (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) | | |
407 | (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT)); | |
408 | oxygen_write8(chip, OXYGEN_PLAY_FORMAT, | |
409 | (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) | | |
410 | (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT)); | |
411 | oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2); | |
c9946b2c | 412 | oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT, |
5b8bf2a5 CL |
413 | OXYGEN_RATE_48000 | |
414 | chip->model.dac_i2s_format | | |
415 | OXYGEN_I2S_MCLK(chip->model.dac_mclks) | | |
416 | OXYGEN_I2S_BITS_16 | | |
417 | OXYGEN_I2S_MASTER | | |
418 | OXYGEN_I2S_BCLK_64); | |
d76596b1 | 419 | if (chip->model.device_config & CAPTURE_0_FROM_I2S_1) |
43dd89c7 | 420 | oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, |
5b8bf2a5 CL |
421 | OXYGEN_RATE_48000 | |
422 | chip->model.adc_i2s_format | | |
423 | OXYGEN_I2S_MCLK(chip->model.adc_mclks) | | |
424 | OXYGEN_I2S_BITS_16 | | |
425 | OXYGEN_I2S_MASTER | | |
426 | OXYGEN_I2S_BCLK_64); | |
43dd89c7 CL |
427 | else |
428 | oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, | |
5b8bf2a5 CL |
429 | OXYGEN_I2S_MASTER | |
430 | OXYGEN_I2S_MUTE_MCLK); | |
d76596b1 CL |
431 | if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 | |
432 | CAPTURE_2_FROM_I2S_2)) | |
43dd89c7 | 433 | oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, |
5b8bf2a5 CL |
434 | OXYGEN_RATE_48000 | |
435 | chip->model.adc_i2s_format | | |
436 | OXYGEN_I2S_MCLK(chip->model.adc_mclks) | | |
437 | OXYGEN_I2S_BITS_16 | | |
438 | OXYGEN_I2S_MASTER | | |
439 | OXYGEN_I2S_BCLK_64); | |
43dd89c7 CL |
440 | else |
441 | oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, | |
5b8bf2a5 CL |
442 | OXYGEN_I2S_MASTER | |
443 | OXYGEN_I2S_MUTE_MCLK); | |
c9946b2c | 444 | oxygen_write16(chip, OXYGEN_I2S_C_FORMAT, |
5b8bf2a5 CL |
445 | OXYGEN_I2S_MASTER | |
446 | OXYGEN_I2S_MUTE_MCLK); | |
1d98c7d4 CL |
447 | oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, |
448 | OXYGEN_SPDIF_OUT_ENABLE | | |
449 | OXYGEN_SPDIF_LOOPBACK); | |
d76596b1 | 450 | if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) |
1d98c7d4 CL |
451 | oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL, |
452 | OXYGEN_SPDIF_SENSE_MASK | | |
453 | OXYGEN_SPDIF_LOCK_MASK | | |
454 | OXYGEN_SPDIF_RATE_MASK | | |
455 | OXYGEN_SPDIF_LOCK_PAR | | |
456 | OXYGEN_SPDIF_IN_CLOCK_96, | |
457 | OXYGEN_SPDIF_SENSE_MASK | | |
458 | OXYGEN_SPDIF_LOCK_MASK | | |
459 | OXYGEN_SPDIF_RATE_MASK | | |
460 | OXYGEN_SPDIF_SENSE_PAR | | |
461 | OXYGEN_SPDIF_LOCK_PAR | | |
462 | OXYGEN_SPDIF_IN_CLOCK_MASK); | |
463 | else | |
464 | oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, | |
465 | OXYGEN_SPDIF_SENSE_MASK | | |
466 | OXYGEN_SPDIF_LOCK_MASK | | |
467 | OXYGEN_SPDIF_RATE_MASK); | |
d0ce9946 | 468 | oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits); |
4a4bc53b CL |
469 | oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS, |
470 | OXYGEN_2WIRE_LENGTH_8 | | |
471 | OXYGEN_2WIRE_INTERRUPT_MASK | | |
472 | OXYGEN_2WIRE_SPEED_STANDARD); | |
b78e3dbb CL |
473 | oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK); |
474 | oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0); | |
475 | oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0); | |
c9946b2c | 476 | oxygen_write16(chip, OXYGEN_PLAY_ROUTING, |
b78e3dbb CL |
477 | OXYGEN_PLAY_MULTICH_I2S_DAC | |
478 | OXYGEN_PLAY_SPDIF_SPDIF | | |
c9946b2c CL |
479 | (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) | |
480 | (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) | | |
481 | (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) | | |
482 | (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT)); | |
483 | oxygen_write8(chip, OXYGEN_REC_ROUTING, | |
484 | OXYGEN_REC_A_ROUTE_I2S_ADC_1 | | |
b78e3dbb | 485 | OXYGEN_REC_B_ROUTE_I2S_ADC_2 | |
c9946b2c CL |
486 | OXYGEN_REC_C_ROUTE_SPDIF); |
487 | oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0); | |
488 | oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING, | |
489 | (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) | | |
490 | (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) | | |
491 | (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) | | |
492 | (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT)); | |
d0ce9946 | 493 | |
1d98c7d4 CL |
494 | if (chip->has_ac97_0 | chip->has_ac97_1) |
495 | oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, | |
496 | OXYGEN_AC97_INT_READ_DONE | | |
497 | OXYGEN_AC97_INT_WRITE_DONE); | |
498 | else | |
499 | oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0); | |
b78e3dbb CL |
500 | oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0); |
501 | oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0); | |
502 | if (!(chip->has_ac97_0 | chip->has_ac97_1)) | |
503 | oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL, | |
504 | OXYGEN_AC97_CLOCK_DISABLE); | |
505 | if (!chip->has_ac97_0) { | |
506 | oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL, | |
507 | OXYGEN_AC97_NO_CODEC_0); | |
508 | } else { | |
31c77643 CL |
509 | oxygen_write_ac97(chip, 0, AC97_RESET, 0); |
510 | msleep(1); | |
878ac3ee CL |
511 | oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP, |
512 | CM9780_GPIO0IO | CM9780_GPIO1IO); | |
513 | oxygen_ac97_set_bits(chip, 0, CM9780_MIXER, | |
514 | CM9780_BSTSEL | CM9780_STRO_MIC | | |
515 | CM9780_MIX2FR | CM9780_PCBSW); | |
516 | oxygen_ac97_set_bits(chip, 0, CM9780_JACK, | |
517 | CM9780_RSOE | CM9780_CBOE | | |
518 | CM9780_SSOE | CM9780_FROE | | |
519 | CM9780_MIC2MIC | CM9780_LI2LI); | |
31c77643 CL |
520 | oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000); |
521 | oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000); | |
522 | oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808); | |
523 | oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808); | |
524 | oxygen_write_ac97(chip, 0, AC97_CD, 0x8808); | |
525 | oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808); | |
526 | oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808); | |
527 | oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000); | |
528 | oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080); | |
529 | oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080); | |
e97f7999 CL |
530 | oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS, |
531 | CM9780_GPO0); | |
31c77643 CL |
532 | /* power down unused ADCs and DACs */ |
533 | oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN, | |
534 | AC97_PD_PR0 | AC97_PD_PR1); | |
535 | oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS, | |
536 | AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK); | |
537 | } | |
b78e3dbb CL |
538 | if (chip->has_ac97_1) { |
539 | oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG, | |
540 | OXYGEN_AC97_CODEC1_SLOT3 | | |
541 | OXYGEN_AC97_CODEC1_SLOT4); | |
542 | oxygen_write_ac97(chip, 1, AC97_RESET, 0); | |
543 | msleep(1); | |
544 | oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000); | |
545 | oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000); | |
546 | oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000); | |
547 | oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808); | |
548 | oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808); | |
549 | oxygen_write_ac97(chip, 1, AC97_CD, 0x8808); | |
550 | oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808); | |
551 | oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808); | |
552 | oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808); | |
553 | oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000); | |
a3601560 | 554 | oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000); |
b78e3dbb CL |
555 | oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040); |
556 | } | |
d0ce9946 CL |
557 | } |
558 | ||
4c25b932 | 559 | static void oxygen_shutdown(struct oxygen *chip) |
d0ce9946 | 560 | { |
d0ce9946 CL |
561 | spin_lock_irq(&chip->reg_lock); |
562 | chip->interrupt_mask = 0; | |
563 | chip->pcm_running = 0; | |
564 | oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); | |
565 | oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); | |
566 | spin_unlock_irq(&chip->reg_lock); | |
4c25b932 CL |
567 | } |
568 | ||
569 | static void oxygen_card_free(struct snd_card *card) | |
570 | { | |
571 | struct oxygen *chip = card->private_data; | |
572 | ||
573 | oxygen_shutdown(chip); | |
f000fd80 | 574 | if (chip->irq >= 0) |
d0ce9946 | 575 | free_irq(chip->irq, chip); |
5b84ba26 TH |
576 | flush_work_sync(&chip->spdif_input_bits_work); |
577 | flush_work_sync(&chip->gpio_work); | |
9bd6a73a | 578 | chip->model.cleanup(chip); |
6ed91157 | 579 | kfree(chip->model_data); |
d0ce9946 CL |
580 | mutex_destroy(&chip->mutex); |
581 | pci_release_regions(chip->pci); | |
582 | pci_disable_device(chip->pci); | |
583 | } | |
584 | ||
f007dc04 | 585 | int oxygen_pci_probe(struct pci_dev *pci, int index, char *id, |
bb718588 | 586 | struct module *owner, |
30459d7b CL |
587 | const struct pci_device_id *ids, |
588 | int (*get_model)(struct oxygen *chip, | |
589 | const struct pci_device_id *id | |
590 | ) | |
591 | ) | |
d0ce9946 CL |
592 | { |
593 | struct snd_card *card; | |
594 | struct oxygen *chip; | |
30459d7b | 595 | const struct pci_device_id *pci_id; |
d0ce9946 CL |
596 | int err; |
597 | ||
6ed91157 | 598 | err = snd_card_create(index, id, owner, sizeof(*chip), &card); |
e58de7ba TI |
599 | if (err < 0) |
600 | return err; | |
d0ce9946 CL |
601 | |
602 | chip = card->private_data; | |
603 | chip->card = card; | |
604 | chip->pci = pci; | |
605 | chip->irq = -1; | |
d0ce9946 CL |
606 | spin_lock_init(&chip->reg_lock); |
607 | mutex_init(&chip->mutex); | |
608 | INIT_WORK(&chip->spdif_input_bits_work, | |
609 | oxygen_spdif_input_bits_changed); | |
7c014159 | 610 | INIT_WORK(&chip->gpio_work, oxygen_gpio_changed); |
1e821dd2 | 611 | init_waitqueue_head(&chip->ac97_waitqueue); |
d0ce9946 CL |
612 | |
613 | err = pci_enable_device(pci); | |
614 | if (err < 0) | |
615 | goto err_card; | |
616 | ||
a69bb3c3 | 617 | err = pci_request_regions(pci, DRIVER); |
d0ce9946 CL |
618 | if (err < 0) { |
619 | snd_printk(KERN_ERR "cannot reserve PCI resources\n"); | |
620 | goto err_pci_enable; | |
621 | } | |
622 | ||
623 | if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) || | |
c1365007 | 624 | pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) { |
d0ce9946 CL |
625 | snd_printk(KERN_ERR "invalid PCI I/O range\n"); |
626 | err = -ENXIO; | |
627 | goto err_pci_regions; | |
628 | } | |
629 | chip->addr = pci_resource_start(pci, 0); | |
630 | ||
30459d7b CL |
631 | pci_id = oxygen_search_pci_id(chip, ids); |
632 | if (!pci_id) { | |
633 | err = -ENODEV; | |
634 | goto err_pci_regions; | |
635 | } | |
1275d6f6 | 636 | oxygen_restore_eeprom(chip, pci_id); |
30459d7b CL |
637 | err = get_model(chip, pci_id); |
638 | if (err < 0) | |
639 | goto err_pci_regions; | |
640 | ||
6ed91157 | 641 | if (chip->model.model_data_size) { |
82af308f | 642 | chip->model_data = kzalloc(chip->model.model_data_size, |
6ed91157 CL |
643 | GFP_KERNEL); |
644 | if (!chip->model_data) { | |
645 | err = -ENOMEM; | |
646 | goto err_pci_regions; | |
647 | } | |
648 | } | |
649 | ||
d0ce9946 CL |
650 | pci_set_master(pci); |
651 | snd_card_set_dev(card, &pci->dev); | |
652 | card->private_free = oxygen_card_free; | |
653 | ||
7cb4ced5 | 654 | configure_pcie_bridge(pci); |
d0ce9946 | 655 | oxygen_init(chip); |
9bd6a73a | 656 | chip->model.init(chip); |
d0ce9946 CL |
657 | |
658 | err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED, | |
934c2b6d | 659 | KBUILD_MODNAME, chip); |
d0ce9946 CL |
660 | if (err < 0) { |
661 | snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq); | |
662 | goto err_card; | |
663 | } | |
664 | chip->irq = pci->irq; | |
665 | ||
9bd6a73a CL |
666 | strcpy(card->driver, chip->model.chip); |
667 | strcpy(card->shortname, chip->model.shortname); | |
a1f80fcf CL |
668 | sprintf(card->longname, "%s at %#lx, irq %i", |
669 | chip->model.longname, chip->addr, chip->irq); | |
9bd6a73a CL |
670 | strcpy(card->mixername, chip->model.chip); |
671 | snd_component_add(card, chip->model.chip); | |
d0ce9946 CL |
672 | |
673 | err = oxygen_pcm_init(chip); | |
674 | if (err < 0) | |
675 | goto err_card; | |
676 | ||
677 | err = oxygen_mixer_init(chip); | |
678 | if (err < 0) | |
679 | goto err_card; | |
680 | ||
dbbbd674 | 681 | if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) { |
dba8b469 CL |
682 | unsigned int info_flags = |
683 | MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK; | |
dbbbd674 CL |
684 | if (chip->model.device_config & MIDI_OUTPUT) |
685 | info_flags |= MPU401_INFO_OUTPUT; | |
686 | if (chip->model.device_config & MIDI_INPUT) | |
687 | info_flags |= MPU401_INFO_INPUT; | |
d0ce9946 CL |
688 | err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, |
689 | chip->addr + OXYGEN_MPU401, | |
dba8b469 | 690 | info_flags, -1, &chip->midi); |
d0ce9946 CL |
691 | if (err < 0) |
692 | goto err_card; | |
693 | } | |
694 | ||
695 | oxygen_proc_init(chip); | |
696 | ||
697 | spin_lock_irq(&chip->reg_lock); | |
d76596b1 | 698 | if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) |
1d98c7d4 CL |
699 | chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT; |
700 | if (chip->has_ac97_0 | chip->has_ac97_1) | |
701 | chip->interrupt_mask |= OXYGEN_INT_AC97; | |
d0ce9946 CL |
702 | oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); |
703 | spin_unlock_irq(&chip->reg_lock); | |
704 | ||
705 | err = snd_card_register(card); | |
706 | if (err < 0) | |
707 | goto err_card; | |
708 | ||
709 | pci_set_drvdata(pci, card); | |
710 | return 0; | |
711 | ||
712 | err_pci_regions: | |
713 | pci_release_regions(pci); | |
714 | err_pci_enable: | |
715 | pci_disable_device(pci); | |
716 | err_card: | |
717 | snd_card_free(card); | |
718 | return err; | |
719 | } | |
720 | EXPORT_SYMBOL(oxygen_pci_probe); | |
721 | ||
f007dc04 | 722 | void oxygen_pci_remove(struct pci_dev *pci) |
d0ce9946 CL |
723 | { |
724 | snd_card_free(pci_get_drvdata(pci)); | |
725 | pci_set_drvdata(pci, NULL); | |
726 | } | |
727 | EXPORT_SYMBOL(oxygen_pci_remove); | |
4a4bc53b CL |
728 | |
729 | #ifdef CONFIG_PM | |
730 | int oxygen_pci_suspend(struct pci_dev *pci, pm_message_t state) | |
731 | { | |
732 | struct snd_card *card = pci_get_drvdata(pci); | |
733 | struct oxygen *chip = card->private_data; | |
734 | unsigned int i, saved_interrupt_mask; | |
735 | ||
736 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); | |
737 | ||
738 | for (i = 0; i < PCM_COUNT; ++i) | |
739 | if (chip->streams[i]) | |
740 | snd_pcm_suspend(chip->streams[i]); | |
741 | ||
9bd6a73a CL |
742 | if (chip->model.suspend) |
743 | chip->model.suspend(chip); | |
4a4bc53b CL |
744 | |
745 | spin_lock_irq(&chip->reg_lock); | |
746 | saved_interrupt_mask = chip->interrupt_mask; | |
747 | chip->interrupt_mask = 0; | |
748 | oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); | |
749 | oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); | |
750 | spin_unlock_irq(&chip->reg_lock); | |
751 | ||
752 | synchronize_irq(chip->irq); | |
5b84ba26 TH |
753 | flush_work_sync(&chip->spdif_input_bits_work); |
754 | flush_work_sync(&chip->gpio_work); | |
4a4bc53b CL |
755 | chip->interrupt_mask = saved_interrupt_mask; |
756 | ||
757 | pci_disable_device(pci); | |
758 | pci_save_state(pci); | |
759 | pci_set_power_state(pci, pci_choose_state(pci, state)); | |
760 | return 0; | |
761 | } | |
762 | EXPORT_SYMBOL(oxygen_pci_suspend); | |
763 | ||
764 | static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = { | |
765 | 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff, | |
766 | 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000 | |
767 | }; | |
768 | static const u32 ac97_registers_to_restore[2][0x40 / 32] = { | |
769 | { 0x18284fa2, 0x03060000 }, | |
770 | { 0x00007fa6, 0x00200000 } | |
771 | }; | |
772 | ||
773 | static inline int is_bit_set(const u32 *bitmap, unsigned int bit) | |
774 | { | |
775 | return bitmap[bit / 32] & (1 << (bit & 31)); | |
776 | } | |
777 | ||
778 | static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec) | |
779 | { | |
780 | unsigned int i; | |
781 | ||
782 | oxygen_write_ac97(chip, codec, AC97_RESET, 0); | |
783 | msleep(1); | |
784 | for (i = 1; i < 0x40; ++i) | |
785 | if (is_bit_set(ac97_registers_to_restore[codec], i)) | |
786 | oxygen_write_ac97(chip, codec, i * 2, | |
787 | chip->saved_ac97_registers[codec][i]); | |
788 | } | |
789 | ||
790 | int oxygen_pci_resume(struct pci_dev *pci) | |
791 | { | |
792 | struct snd_card *card = pci_get_drvdata(pci); | |
793 | struct oxygen *chip = card->private_data; | |
794 | unsigned int i; | |
795 | ||
796 | pci_set_power_state(pci, PCI_D0); | |
797 | pci_restore_state(pci); | |
798 | if (pci_enable_device(pci) < 0) { | |
799 | snd_printk(KERN_ERR "cannot reenable device"); | |
800 | snd_card_disconnect(card); | |
801 | return -EIO; | |
802 | } | |
803 | pci_set_master(pci); | |
804 | ||
805 | oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); | |
806 | oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); | |
807 | for (i = 0; i < OXYGEN_IO_SIZE; ++i) | |
808 | if (is_bit_set(registers_to_restore, i)) | |
809 | oxygen_write8(chip, i, chip->saved_registers._8[i]); | |
810 | if (chip->has_ac97_0) | |
811 | oxygen_restore_ac97(chip, 0); | |
812 | if (chip->has_ac97_1) | |
813 | oxygen_restore_ac97(chip, 1); | |
814 | ||
9bd6a73a CL |
815 | if (chip->model.resume) |
816 | chip->model.resume(chip); | |
4a4bc53b CL |
817 | |
818 | oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); | |
819 | ||
820 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); | |
821 | return 0; | |
822 | } | |
823 | EXPORT_SYMBOL(oxygen_pci_resume); | |
824 | #endif /* CONFIG_PM */ | |
4c25b932 CL |
825 | |
826 | void oxygen_pci_shutdown(struct pci_dev *pci) | |
827 | { | |
828 | struct snd_card *card = pci_get_drvdata(pci); | |
829 | struct oxygen *chip = card->private_data; | |
830 | ||
831 | oxygen_shutdown(chip); | |
832 | chip->model.cleanup(chip); | |
833 | } | |
834 | EXPORT_SYMBOL(oxygen_pci_shutdown); |