[mirror_ubuntu-bionic-kernel.git] / sound / pci / oxygen / xonar_dg.c

/*
 * card driver for the Xonar DG/DGX
 *
 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
 * Copyright (c) Roman Volkov <v1ron@mail.ru>
 *
 *  This driver is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License, version 2.
 *
 *  This driver is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this driver; if not, see <http://www.gnu.org/licenses/>.
 */

/*
 * Xonar DG/DGX
 * ------------
 *
 * CS4245 and CS4361 both will mute all outputs if any clock ratio
 * is invalid.
 *
 * CMI8788:
 *
 *   SPI 0 -> CS4245
 *
 *   Playback:
 *   I²S 1 -> CS4245
 *   I²S 2 -> CS4361 (center/LFE)
 *   I²S 3 -> CS4361 (surround)
 *   I²S 4 -> CS4361 (front)
 *   Capture:
 *   I²S ADC 1 <- CS4245
 *
 *   GPIO 3 <- ?
 *   GPIO 4 <- headphone detect
 *   GPIO 5 -> enable ADC analog circuit for the left channel
 *   GPIO 6 -> enable ADC analog circuit for the right channel
 *   GPIO 7 -> switch green rear output jack between CS4245 and and the first
 *             channel of CS4361 (mechanical relay)
 *   GPIO 8 -> enable output to speakers
 *
 * CS4245:
 *
 *   input 0 <- mic
 *   input 1 <- aux
 *   input 2 <- front mic
 *   input 4 <- line
 *   DAC out -> headphones
 *   aux out -> front panel headphones
 */

#include <linux/pci.h>
#include <linux/delay.h>
#include <sound/control.h>
#include <sound/core.h>
#include <sound/info.h>
#include <sound/pcm.h>
#include <sound/tlv.h>
#include "oxygen.h"
#include "xonar_dg.h"
#include "cs4245.h"

int cs4245_write_spi(struct oxygen *chip, u8 reg)
{
	struct dg *data = chip->model_data;
	unsigned int packet;

	packet = reg << 8;
	packet |= (CS4245_SPI_ADDRESS | CS4245_SPI_WRITE) << 16;
	packet |= data->cs4245_shadow[reg];

	return oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
				OXYGEN_SPI_DATA_LENGTH_3 |
				OXYGEN_SPI_CLOCK_1280 |
				(0 << OXYGEN_SPI_CODEC_SHIFT) |
				OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
				packet);
}

int cs4245_read_spi(struct oxygen *chip, u8 addr)
{
	struct dg *data = chip->model_data;
	int ret;

	ret = oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
		OXYGEN_SPI_DATA_LENGTH_2 |
		OXYGEN_SPI_CEN_LATCH_CLOCK_HI |
		OXYGEN_SPI_CLOCK_1280 | (0 << OXYGEN_SPI_CODEC_SHIFT),
		((CS4245_SPI_ADDRESS | CS4245_SPI_WRITE) << 8) | addr);
	if (ret < 0)
		return ret;

	ret = oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
		OXYGEN_SPI_DATA_LENGTH_2 |
		OXYGEN_SPI_CEN_LATCH_CLOCK_HI |
		OXYGEN_SPI_CLOCK_1280 | (0 << OXYGEN_SPI_CODEC_SHIFT),
		(CS4245_SPI_ADDRESS | CS4245_SPI_READ) << 8);
	if (ret < 0)
		return ret;

	data->cs4245_shadow[addr] = oxygen_read8(chip, OXYGEN_SPI_DATA1);

	return 0;
}

int cs4245_shadow_control(struct oxygen *chip, enum cs4245_shadow_operation op)
{
	struct dg *data = chip->model_data;
	unsigned char addr;
	int ret;

	for (addr = 1; addr < ARRAY_SIZE(data->cs4245_shadow); addr++) {
		ret = (op == CS4245_SAVE_TO_SHADOW ?
			cs4245_read_spi(chip, addr) :
			cs4245_write_spi(chip, addr));
		if (ret < 0)
			return ret;
	}
	return 0;
}

static void cs4245_init(struct oxygen *chip)
{
	struct dg *data = chip->model_data;

	/* save the initial state: codec version, registers */
	cs4245_shadow_control(chip, CS4245_SAVE_TO_SHADOW);

	/*
	 * Power up the CODEC internals, enable soft ramp & zero cross, work in
	 * async. mode, enable aux output from DAC. Invert DAC output as in the
	 * Windows driver.
	 */
	data->cs4245_shadow[CS4245_POWER_CTRL] = 0;
	data->cs4245_shadow[CS4245_SIGNAL_SEL] =
		CS4245_A_OUT_SEL_DAC | CS4245_ASYNCH;
	data->cs4245_shadow[CS4245_DAC_CTRL_1] =
		CS4245_DAC_FM_SINGLE | CS4245_DAC_DIF_LJUST;
	data->cs4245_shadow[CS4245_DAC_CTRL_2] =
		CS4245_DAC_SOFT | CS4245_DAC_ZERO | CS4245_INVERT_DAC;
	data->cs4245_shadow[CS4245_ADC_CTRL] =
		CS4245_ADC_FM_SINGLE | CS4245_ADC_DIF_LJUST;
	data->cs4245_shadow[CS4245_ANALOG_IN] =
		CS4245_PGA_SOFT | CS4245_PGA_ZERO;
	data->cs4245_shadow[CS4245_PGA_B_CTRL] = 0;
	data->cs4245_shadow[CS4245_PGA_A_CTRL] = 0;
	data->cs4245_shadow[CS4245_DAC_A_CTRL] = 8;
	data->cs4245_shadow[CS4245_DAC_B_CTRL] = 8;

	cs4245_shadow_control(chip, CS4245_LOAD_FROM_SHADOW);
	snd_component_add(chip->card, "CS4245");
}

void dg_init(struct oxygen *chip)
{
	struct dg *data = chip->model_data;

	data->output_sel = PLAYBACK_DST_HP_FP;
	data->input_sel = CAPTURE_SRC_MIC;

	cs4245_init(chip);
	oxygen_write16(chip, OXYGEN_GPIO_CONTROL,
		       GPIO_OUTPUT_ENABLE | GPIO_HP_REAR | GPIO_INPUT_ROUTE);
	/* anti-pop delay, wait some time before enabling the output */
	msleep(2500);
	oxygen_write16(chip, OXYGEN_GPIO_DATA,
		       GPIO_OUTPUT_ENABLE | GPIO_INPUT_ROUTE);
}

void dg_cleanup(struct oxygen *chip)
{
	oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_OUTPUT_ENABLE);
}

void dg_suspend(struct oxygen *chip)
{
	dg_cleanup(chip);
}

void dg_resume(struct oxygen *chip)
{
	cs4245_shadow_control(chip, CS4245_LOAD_FROM_SHADOW);
	msleep(2500);
	oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_OUTPUT_ENABLE);
}

void set_cs4245_dac_params(struct oxygen *chip,
				  struct snd_pcm_hw_params *params)
{
	struct dg *data = chip->model_data;
	unsigned char dac_ctrl;
	unsigned char mclk_freq;

	dac_ctrl = data->cs4245_shadow[CS4245_DAC_CTRL_1] & ~CS4245_DAC_FM_MASK;
	mclk_freq = data->cs4245_shadow[CS4245_MCLK_FREQ] & ~CS4245_MCLK1_MASK;
	if (params_rate(params) <= 50000) {
		dac_ctrl |= CS4245_DAC_FM_SINGLE;
		mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK1_SHIFT;
	} else if (params_rate(params) <= 100000) {
		dac_ctrl |= CS4245_DAC_FM_DOUBLE;
		mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK1_SHIFT;
	} else {
		dac_ctrl |= CS4245_DAC_FM_QUAD;
		mclk_freq |= CS4245_MCLK_2 << CS4245_MCLK1_SHIFT;
	}
	data->cs4245_shadow[CS4245_DAC_CTRL_1] = dac_ctrl;
	data->cs4245_shadow[CS4245_MCLK_FREQ] = mclk_freq;
	cs4245_write_spi(chip, CS4245_DAC_CTRL_1);
	cs4245_write_spi(chip, CS4245_MCLK_FREQ);
}

void set_cs4245_adc_params(struct oxygen *chip,
				  struct snd_pcm_hw_params *params)
{
	struct dg *data = chip->model_data;
	unsigned char adc_ctrl;
	unsigned char mclk_freq;

	adc_ctrl = data->cs4245_shadow[CS4245_ADC_CTRL] & ~CS4245_ADC_FM_MASK;
	mclk_freq = data->cs4245_shadow[CS4245_MCLK_FREQ] & ~CS4245_MCLK2_MASK;
	if (params_rate(params) <= 50000) {
		adc_ctrl |= CS4245_ADC_FM_SINGLE;
		mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK2_SHIFT;
	} else if (params_rate(params) <= 100000) {
		adc_ctrl |= CS4245_ADC_FM_DOUBLE;
		mclk_freq |= CS4245_MCLK_1 << CS4245_MCLK2_SHIFT;
	} else {
		adc_ctrl |= CS4245_ADC_FM_QUAD;
		mclk_freq |= CS4245_MCLK_2 << CS4245_MCLK2_SHIFT;
	}
	data->cs4245_shadow[CS4245_ADC_CTRL] = adc_ctrl;
	data->cs4245_shadow[CS4245_MCLK_FREQ] = mclk_freq;
	cs4245_write_spi(chip, CS4245_ADC_CTRL);
	cs4245_write_spi(chip, CS4245_MCLK_FREQ);
}

static inline unsigned int shift_bits(unsigned int value,
				      unsigned int shift_from,
				      unsigned int shift_to,
				      unsigned int mask)
{
	if (shift_from < shift_to)
		return (value << (shift_to - shift_from)) & mask;
	else
		return (value >> (shift_from - shift_to)) & mask;
}

unsigned int adjust_dg_dac_routing(struct oxygen *chip,
					  unsigned int play_routing)
{
	struct dg *data = chip->model_data;

	switch (data->output_sel) {
	case PLAYBACK_DST_HP:
	case PLAYBACK_DST_HP_FP:
		oxygen_write8_masked(chip, OXYGEN_PLAY_ROUTING,
			OXYGEN_PLAY_MUTE23 | OXYGEN_PLAY_MUTE45 |
			OXYGEN_PLAY_MUTE67, OXYGEN_PLAY_MUTE_MASK);
		break;
	case PLAYBACK_DST_MULTICH:
		oxygen_write8_masked(chip, OXYGEN_PLAY_ROUTING,
			OXYGEN_PLAY_MUTE01, OXYGEN_PLAY_MUTE_MASK);
		break;
	}
	return (play_routing & OXYGEN_PLAY_DAC0_SOURCE_MASK) |
	       shift_bits(play_routing,
			  OXYGEN_PLAY_DAC2_SOURCE_SHIFT,
			  OXYGEN_PLAY_DAC1_SOURCE_SHIFT,
			  OXYGEN_PLAY_DAC1_SOURCE_MASK) |
	       shift_bits(play_routing,
			  OXYGEN_PLAY_DAC1_SOURCE_SHIFT,
			  OXYGEN_PLAY_DAC2_SOURCE_SHIFT,
			  OXYGEN_PLAY_DAC2_SOURCE_MASK) |
	       shift_bits(play_routing,
			  OXYGEN_PLAY_DAC0_SOURCE_SHIFT,
			  OXYGEN_PLAY_DAC3_SOURCE_SHIFT,
			  OXYGEN_PLAY_DAC3_SOURCE_MASK);
}

void dump_cs4245_registers(struct oxygen *chip,
				  struct snd_info_buffer *buffer)
{
	struct dg *data = chip->model_data;
	unsigned int addr;

	snd_iprintf(buffer, "\nCS4245:");
	cs4245_read_spi(chip, CS4245_INT_STATUS);
	for (addr = 1; addr < ARRAY_SIZE(data->cs4245_shadow); addr++)
		snd_iprintf(buffer, " %02x", data->cs4245_shadow[addr]);
	snd_iprintf(buffer, "\n");
}
Commit	Line	Data
66410bfd	1	/*
76bc7a0d	2	* card driver for the Xonar DG/DGX
66410bfd CL	3	*
66410bfd CL	4	* Copyright (c) Clemens Ladisch <clemens@ladisch.de>
c4d4390c	5	* Copyright (c) Roman Volkov <v1ron@mail.ru>
66410bfd CL	6	*
	7	* This driver is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License, version 2.
	9	*
	10	* This driver is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this driver; if not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
	19	/*
76bc7a0d CL	20	* Xonar DG/DGX
76bc7a0d CL	21	* ------------
66410bfd	22	*
c4d4390c RV	23	* CS4245 and CS4361 both will mute all outputs if any clock ratio
	24	* is invalid.
	25	*
66410bfd CL	26	* CMI8788:
	27	*
	28	* SPI 0 -> CS4245
	29	*
c4d4390c	30	* Playback:
efbeb071 CL	31	* I²S 1 -> CS4245
	32	* I²S 2 -> CS4361 (center/LFE)
	33	* I²S 3 -> CS4361 (surround)
	34	* I²S 4 -> CS4361 (front)
c4d4390c RV	35	* Capture:
c4d4390c RV	36	* I²S ADC 1 <- CS4245
efbeb071	37	*
66410bfd CL	38	* GPIO 3 <- ?
66410bfd CL	39	* GPIO 4 <- headphone detect
c4d4390c RV	40	* GPIO 5 -> enable ADC analog circuit for the left channel
	41	* GPIO 6 -> enable ADC analog circuit for the right channel
	42	* GPIO 7 -> switch green rear output jack between CS4245 and and the first
	43	* channel of CS4361 (mechanical relay)
66410bfd CL	44	* GPIO 8 -> enable output to speakers
	45	*
	46	* CS4245:
	47	*
c4d4390c	48	* input 0 <- mic
66410bfd CL	49	* input 1 <- aux
66410bfd CL	50	* input 2 <- front mic
c4d4390c	51	* input 4 <- line
efbeb071	52	* DAC out -> headphones
66410bfd CL	53	* aux out -> front panel headphones
	54	*/
	55
	56	#include <linux/pci.h>
e92d4575	57	#include <linux/delay.h>
66410bfd CL	58	#include <sound/control.h>
	59	#include <sound/core.h>
	60	#include <sound/info.h>
	61	#include <sound/pcm.h>
	62	#include <sound/tlv.h>
	63	#include "oxygen.h"
	64	#include "xonar_dg.h"
	65	#include "cs4245.h"
	66
bed61935 RV	67	int cs4245_write_spi(struct oxygen *chip, u8 reg)
	68	{
	69	struct dg *data = chip->model_data;
	70	unsigned int packet;
	71
	72	packet = reg << 8;
	73	packet \|= (CS4245_SPI_ADDRESS \| CS4245_SPI_WRITE) << 16;
	74	packet \|= data->cs4245_shadow[reg];
	75
	76	return oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER \|
	77	OXYGEN_SPI_DATA_LENGTH_3 \|
	78	OXYGEN_SPI_CLOCK_1280 \|
	79	(0 << OXYGEN_SPI_CODEC_SHIFT) \|
	80	OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
	81	packet);
	82	}
	83
	84	int cs4245_read_spi(struct oxygen *chip, u8 addr)
	85	{
	86	struct dg *data = chip->model_data;
	87	int ret;
	88
	89	ret = oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER \|
	90	OXYGEN_SPI_DATA_LENGTH_2 \|
	91	OXYGEN_SPI_CEN_LATCH_CLOCK_HI \|
	92	OXYGEN_SPI_CLOCK_1280 \| (0 << OXYGEN_SPI_CODEC_SHIFT),
	93	((CS4245_SPI_ADDRESS \| CS4245_SPI_WRITE) << 8) \| addr);
	94	if (ret < 0)
	95	return ret;
	96
	97	ret = oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER \|
	98	OXYGEN_SPI_DATA_LENGTH_2 \|
	99	OXYGEN_SPI_CEN_LATCH_CLOCK_HI \|
	100	OXYGEN_SPI_CLOCK_1280 \| (0 << OXYGEN_SPI_CODEC_SHIFT),
	101	(CS4245_SPI_ADDRESS \| CS4245_SPI_READ) << 8);
	102	if (ret < 0)
	103	return ret;
	104
	105	data->cs4245_shadow[addr] = oxygen_read8(chip, OXYGEN_SPI_DATA1);
	106
	107	return 0;
	108	}
	109
	110	int cs4245_shadow_control(struct oxygen *chip, enum cs4245_shadow_operation op)
	111	{
	112	struct dg *data = chip->model_data;
	113	unsigned char addr;
	114	int ret;
	115
	116	for (addr = 1; addr < ARRAY_SIZE(data->cs4245_shadow); addr++) {
	117	ret = (op == CS4245_SAVE_TO_SHADOW ?
	118	cs4245_read_spi(chip, addr) :
	119	cs4245_write_spi(chip, addr));
	120	if (ret < 0)
	121	return ret;
	122	}
	123	return 0;
	124	}
	125
66410bfd CL	126	static void cs4245_init(struct oxygen *chip)
	127	{
	128	struct dg *data = chip->model_data;
	129
3c1611dd RV	130	/* save the initial state: codec version, registers */
	131	cs4245_shadow_control(chip, CS4245_SAVE_TO_SHADOW);
	132
	133	/*
	134	* Power up the CODEC internals, enable soft ramp & zero cross, work in
	135	* async. mode, enable aux output from DAC. Invert DAC output as in the
	136	* Windows driver.
	137	*/
	138	data->cs4245_shadow[CS4245_POWER_CTRL] = 0;
	139	data->cs4245_shadow[CS4245_SIGNAL_SEL] =
	140	CS4245_A_OUT_SEL_DAC \| CS4245_ASYNCH;
	141	data->cs4245_shadow[CS4245_DAC_CTRL_1] =
66410bfd	142	CS4245_DAC_FM_SINGLE \| CS4245_DAC_DIF_LJUST;
3c1611dd RV	143	data->cs4245_shadow[CS4245_DAC_CTRL_2] =
	144	CS4245_DAC_SOFT \| CS4245_DAC_ZERO \| CS4245_INVERT_DAC;
	145	data->cs4245_shadow[CS4245_ADC_CTRL] =
66410bfd	146	CS4245_ADC_FM_SINGLE \| CS4245_ADC_DIF_LJUST;
3c1611dd RV	147	data->cs4245_shadow[CS4245_ANALOG_IN] =
	148	CS4245_PGA_SOFT \| CS4245_PGA_ZERO;
	149	data->cs4245_shadow[CS4245_PGA_B_CTRL] = 0;
	150	data->cs4245_shadow[CS4245_PGA_A_CTRL] = 0;
3f49a66f RV	151	data->cs4245_shadow[CS4245_DAC_A_CTRL] = 8;
3f49a66f RV	152	data->cs4245_shadow[CS4245_DAC_B_CTRL] = 8;
3c1611dd RV	153
3c1611dd RV	154	cs4245_shadow_control(chip, CS4245_LOAD_FROM_SHADOW);
66410bfd CL	155	snd_component_add(chip->card, "CS4245");
	156	}
	157
041f26b6	158	void dg_init(struct oxygen *chip)
66410bfd CL	159	{
	160	struct dg *data = chip->model_data;
	161
3f49a66f RV	162	data->output_sel = PLAYBACK_DST_HP_FP;
3f49a66f RV	163	data->input_sel = CAPTURE_SRC_MIC;
66410bfd CL	164
66410bfd CL	165	cs4245_init(chip);
3c1611dd RV	166	oxygen_write16(chip, OXYGEN_GPIO_CONTROL,
3c1611dd RV	167	GPIO_OUTPUT_ENABLE \| GPIO_HP_REAR \| GPIO_INPUT_ROUTE);
3f49a66f RV	168	/* anti-pop delay, wait some time before enabling the output */
3f49a66f RV	169	msleep(2500);
3c1611dd RV	170	oxygen_write16(chip, OXYGEN_GPIO_DATA,
3c1611dd RV	171	GPIO_OUTPUT_ENABLE \| GPIO_INPUT_ROUTE);
66410bfd CL	172	}
66410bfd CL	173
041f26b6	174	void dg_cleanup(struct oxygen *chip)
66410bfd CL	175	{
	176	oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_OUTPUT_ENABLE);
	177	}
	178
041f26b6	179	void dg_suspend(struct oxygen *chip)
66410bfd CL	180	{
	181	dg_cleanup(chip);
	182	}
	183
041f26b6	184	void dg_resume(struct oxygen *chip)
66410bfd	185	{
3c1611dd RV	186	cs4245_shadow_control(chip, CS4245_LOAD_FROM_SHADOW);
	187	msleep(2500);
	188	oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_OUTPUT_ENABLE);
66410bfd CL	189	}
66410bfd CL	190
041f26b6	191	void set_cs4245_dac_params(struct oxygen *chip,
66410bfd CL	192	struct snd_pcm_hw_params *params)
	193	{
	194	struct dg *data = chip->model_data;
fddc106b RV	195	unsigned char dac_ctrl;
	196	unsigned char mclk_freq;
	197
	198	dac_ctrl = data->cs4245_shadow[CS4245_DAC_CTRL_1] & ~CS4245_DAC_FM_MASK;
	199	mclk_freq = data->cs4245_shadow[CS4245_MCLK_FREQ] & ~CS4245_MCLK1_MASK;
	200	if (params_rate(params) <= 50000) {
	201	dac_ctrl \|= CS4245_DAC_FM_SINGLE;
	202	mclk_freq \|= CS4245_MCLK_1 << CS4245_MCLK1_SHIFT;
	203	} else if (params_rate(params) <= 100000) {
	204	dac_ctrl \|= CS4245_DAC_FM_DOUBLE;
	205	mclk_freq \|= CS4245_MCLK_1 << CS4245_MCLK1_SHIFT;
	206	} else {
	207	dac_ctrl \|= CS4245_DAC_FM_QUAD;
	208	mclk_freq \|= CS4245_MCLK_2 << CS4245_MCLK1_SHIFT;
	209	}
	210	data->cs4245_shadow[CS4245_DAC_CTRL_1] = dac_ctrl;
	211	data->cs4245_shadow[CS4245_MCLK_FREQ] = mclk_freq;
	212	cs4245_write_spi(chip, CS4245_DAC_CTRL_1);
	213	cs4245_write_spi(chip, CS4245_MCLK_FREQ);
66410bfd CL	214	}
66410bfd CL	215
041f26b6	216	void set_cs4245_adc_params(struct oxygen *chip,
66410bfd CL	217	struct snd_pcm_hw_params *params)
	218	{
	219	struct dg *data = chip->model_data;
fddc106b RV	220	unsigned char adc_ctrl;
	221	unsigned char mclk_freq;
	222
	223	adc_ctrl = data->cs4245_shadow[CS4245_ADC_CTRL] & ~CS4245_ADC_FM_MASK;
	224	mclk_freq = data->cs4245_shadow[CS4245_MCLK_FREQ] & ~CS4245_MCLK2_MASK;
	225	if (params_rate(params) <= 50000) {
	226	adc_ctrl \|= CS4245_ADC_FM_SINGLE;
	227	mclk_freq \|= CS4245_MCLK_1 << CS4245_MCLK2_SHIFT;
	228	} else if (params_rate(params) <= 100000) {
	229	adc_ctrl \|= CS4245_ADC_FM_DOUBLE;
	230	mclk_freq \|= CS4245_MCLK_1 << CS4245_MCLK2_SHIFT;
	231	} else {
	232	adc_ctrl \|= CS4245_ADC_FM_QUAD;
	233	mclk_freq \|= CS4245_MCLK_2 << CS4245_MCLK2_SHIFT;
	234	}
	235	data->cs4245_shadow[CS4245_ADC_CTRL] = adc_ctrl;
	236	data->cs4245_shadow[CS4245_MCLK_FREQ] = mclk_freq;
	237	cs4245_write_spi(chip, CS4245_ADC_CTRL);
	238	cs4245_write_spi(chip, CS4245_MCLK_FREQ);
66410bfd CL	239	}
66410bfd CL	240
30556441 CL	241	static inline unsigned int shift_bits(unsigned int value,
	242	unsigned int shift_from,
	243	unsigned int shift_to,
	244	unsigned int mask)
	245	{
	246	if (shift_from < shift_to)
	247	return (value << (shift_to - shift_from)) & mask;
	248	else
	249	return (value >> (shift_from - shift_to)) & mask;
	250	}
	251
041f26b6	252	unsigned int adjust_dg_dac_routing(struct oxygen *chip,
efbeb071 CL	253	unsigned int play_routing)
efbeb071 CL	254	{
1f91ecc1	255	struct dg *data = chip->model_data;
1f91ecc1	256
2809cb84	257	switch (data->output_sel) {
1f91ecc1 RV	258	case PLAYBACK_DST_HP:
	259	case PLAYBACK_DST_HP_FP:
	260	oxygen_write8_masked(chip, OXYGEN_PLAY_ROUTING,
	261	OXYGEN_PLAY_MUTE23 \| OXYGEN_PLAY_MUTE45 \|
	262	OXYGEN_PLAY_MUTE67, OXYGEN_PLAY_MUTE_MASK);
	263	break;
	264	case PLAYBACK_DST_MULTICH:
1f91ecc1 RV	265	oxygen_write8_masked(chip, OXYGEN_PLAY_ROUTING,
	266	OXYGEN_PLAY_MUTE01, OXYGEN_PLAY_MUTE_MASK);
	267	break;
	268	}
30556441 CL	269	return (play_routing & OXYGEN_PLAY_DAC0_SOURCE_MASK) \|
	270	shift_bits(play_routing,
	271	OXYGEN_PLAY_DAC2_SOURCE_SHIFT,
	272	OXYGEN_PLAY_DAC1_SOURCE_SHIFT,
	273	OXYGEN_PLAY_DAC1_SOURCE_MASK) \|
	274	shift_bits(play_routing,
	275	OXYGEN_PLAY_DAC1_SOURCE_SHIFT,
	276	OXYGEN_PLAY_DAC2_SOURCE_SHIFT,
	277	OXYGEN_PLAY_DAC2_SOURCE_MASK) \|
	278	shift_bits(play_routing,
	279	OXYGEN_PLAY_DAC0_SOURCE_SHIFT,
	280	OXYGEN_PLAY_DAC3_SOURCE_SHIFT,
	281	OXYGEN_PLAY_DAC3_SOURCE_MASK);
efbeb071 CL	282	}
efbeb071 CL	283
041f26b6	284	void dump_cs4245_registers(struct oxygen *chip,
66410bfd CL	285	struct snd_info_buffer *buffer)
	286	{
	287	struct dg *data = chip->model_data;
06f70d0d	288	unsigned int addr;
66410bfd CL	289
66410bfd CL	290	snd_iprintf(buffer, "\nCS4245:");
06f70d0d RV	291	cs4245_read_spi(chip, CS4245_INT_STATUS);
	292	for (addr = 1; addr < ARRAY_SIZE(data->cs4245_shadow); addr++)
	293	snd_iprintf(buffer, " %02x", data->cs4245_shadow[addr]);
66410bfd CL	294	snd_iprintf(buffer, "\n");
66410bfd CL	295	}