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1da177e4 LT |
1 | /* |
2 | * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces | |
3 | * | |
4 | * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>, | |
5 | * Pilo Chambert <pilo.c@wanadoo.fr> | |
6 | * | |
7 | * Thanks to : Anders Torger <torger@ludd.luth.se>, | |
8 | * Henk Hesselink <henk@anda.nl> | |
9 | * for writing the digi96-driver | |
10 | * and RME for all informations. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * **************************************************************************** | |
28 | * | |
29 | * Note #1 "Sek'd models" ................................... martin 2002-12-07 | |
30 | * | |
31 | * Identical soundcards by Sek'd were labeled: | |
32 | * RME Digi 32 = Sek'd Prodif 32 | |
33 | * RME Digi 32 Pro = Sek'd Prodif 96 | |
34 | * RME Digi 32/8 = Sek'd Prodif Gold | |
35 | * | |
36 | * **************************************************************************** | |
37 | * | |
38 | * Note #2 "full duplex mode" ............................... martin 2002-12-07 | |
39 | * | |
40 | * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical | |
41 | * in this mode. Rec data and play data are using the same buffer therefore. At | |
42 | * first you have got the playing bits in the buffer and then (after playing | |
43 | * them) they were overwitten by the captured sound of the CS8412/14. Both | |
44 | * modes (play/record) are running harmonically hand in hand in the same buffer | |
45 | * and you have only one start bit plus one interrupt bit to control this | |
46 | * paired action. | |
47 | * This is opposite to the latter rme96 where playing and capturing is totally | |
48 | * separated and so their full duplex mode is supported by alsa (using two | |
49 | * start bits and two interrupts for two different buffers). | |
50 | * But due to the wrong sequence of playing and capturing ALSA shows no solved | |
51 | * full duplex support for the rme32 at the moment. That's bad, but I'm not | |
52 | * able to solve it. Are you motivated enough to solve this problem now? Your | |
53 | * patch would be welcome! | |
54 | * | |
55 | * **************************************************************************** | |
56 | * | |
57 | * "The story after the long seeking" -- tiwai | |
58 | * | |
59 | * Ok, the situation regarding the full duplex is now improved a bit. | |
60 | * In the fullduplex mode (given by the module parameter), the hardware buffer | |
61 | * is split to halves for read and write directions at the DMA pointer. | |
62 | * That is, the half above the current DMA pointer is used for write, and | |
63 | * the half below is used for read. To mangle this strange behavior, an | |
64 | * software intermediate buffer is introduced. This is, of course, not good | |
65 | * from the viewpoint of the data transfer efficiency. However, this allows | |
66 | * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size. | |
67 | * | |
68 | * **************************************************************************** | |
69 | */ | |
70 | ||
71 | ||
1da177e4 LT |
72 | #include <linux/delay.h> |
73 | #include <linux/init.h> | |
74 | #include <linux/interrupt.h> | |
75 | #include <linux/pci.h> | |
76 | #include <linux/slab.h> | |
77 | #include <linux/moduleparam.h> | |
78 | ||
79 | #include <sound/core.h> | |
80 | #include <sound/info.h> | |
81 | #include <sound/control.h> | |
82 | #include <sound/pcm.h> | |
83 | #include <sound/pcm_params.h> | |
84 | #include <sound/pcm-indirect.h> | |
85 | #include <sound/asoundef.h> | |
86 | #include <sound/initval.h> | |
87 | ||
88 | #include <asm/io.h> | |
89 | ||
90 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
91 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
92 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ | |
93 | static int fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1}; | |
94 | ||
95 | module_param_array(index, int, NULL, 0444); | |
96 | MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard."); | |
97 | module_param_array(id, charp, NULL, 0444); | |
98 | MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard."); | |
99 | module_param_array(enable, bool, NULL, 0444); | |
100 | MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard."); | |
101 | module_param_array(fullduplex, bool, NULL, 0444); | |
102 | MODULE_PARM_DESC(fullduplex, "Support full-duplex mode."); | |
103 | MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>"); | |
104 | MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO"); | |
105 | MODULE_LICENSE("GPL"); | |
106 | MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}"); | |
107 | ||
108 | /* Defines for RME Digi32 series */ | |
109 | #define RME32_SPDIF_NCHANNELS 2 | |
110 | ||
111 | /* Playback and capture buffer size */ | |
112 | #define RME32_BUFFER_SIZE 0x20000 | |
113 | ||
114 | /* IO area size */ | |
115 | #define RME32_IO_SIZE 0x30000 | |
116 | ||
117 | /* IO area offsets */ | |
118 | #define RME32_IO_DATA_BUFFER 0x0 | |
119 | #define RME32_IO_CONTROL_REGISTER 0x20000 | |
120 | #define RME32_IO_GET_POS 0x20000 | |
121 | #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004 | |
122 | #define RME32_IO_RESET_POS 0x20100 | |
123 | ||
124 | /* Write control register bits */ | |
125 | #define RME32_WCR_START (1 << 0) /* startbit */ | |
126 | #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono | |
127 | Setting the whole card to mono | |
128 | doesn't seem to be very useful. | |
129 | A software-solution can handle | |
130 | full-duplex with one direction in | |
131 | stereo and the other way in mono. | |
132 | So, the hardware should work all | |
133 | the time in stereo! */ | |
134 | #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */ | |
135 | #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */ | |
136 | #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */ | |
137 | #define RME32_WCR_FREQ_1 (1 << 5) | |
138 | #define RME32_WCR_INP_0 (1 << 6) /* input switch */ | |
139 | #define RME32_WCR_INP_1 (1 << 7) | |
140 | #define RME32_WCR_RESET (1 << 8) /* Reset address */ | |
141 | #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */ | |
142 | #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */ | |
143 | #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */ | |
144 | #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */ | |
145 | #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */ | |
146 | #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */ | |
147 | #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */ | |
148 | ||
149 | #define RME32_WCR_BITPOS_FREQ_0 4 | |
150 | #define RME32_WCR_BITPOS_FREQ_1 5 | |
151 | #define RME32_WCR_BITPOS_INP_0 6 | |
152 | #define RME32_WCR_BITPOS_INP_1 7 | |
153 | ||
154 | /* Read control register bits */ | |
155 | #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff | |
156 | #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */ | |
157 | #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */ | |
158 | #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */ | |
159 | #define RME32_RCR_FREQ_1 (1 << 28) | |
160 | #define RME32_RCR_FREQ_2 (1 << 29) | |
161 | #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */ | |
162 | #define RME32_RCR_IRQ (1 << 31) /* interrupt */ | |
163 | ||
164 | #define RME32_RCR_BITPOS_F0 27 | |
165 | #define RME32_RCR_BITPOS_F1 28 | |
166 | #define RME32_RCR_BITPOS_F2 29 | |
167 | ||
168 | /* Input types */ | |
169 | #define RME32_INPUT_OPTICAL 0 | |
170 | #define RME32_INPUT_COAXIAL 1 | |
171 | #define RME32_INPUT_INTERNAL 2 | |
172 | #define RME32_INPUT_XLR 3 | |
173 | ||
174 | /* Clock modes */ | |
175 | #define RME32_CLOCKMODE_SLAVE 0 | |
176 | #define RME32_CLOCKMODE_MASTER_32 1 | |
177 | #define RME32_CLOCKMODE_MASTER_44 2 | |
178 | #define RME32_CLOCKMODE_MASTER_48 3 | |
179 | ||
180 | /* Block sizes in bytes */ | |
181 | #define RME32_BLOCK_SIZE 8192 | |
182 | ||
183 | /* Software intermediate buffer (max) size */ | |
184 | #define RME32_MID_BUFFER_SIZE (1024*1024) | |
185 | ||
186 | /* Hardware revisions */ | |
187 | #define RME32_32_REVISION 192 | |
188 | #define RME32_328_REVISION_OLD 100 | |
189 | #define RME32_328_REVISION_NEW 101 | |
190 | #define RME32_PRO_REVISION_WITH_8412 192 | |
191 | #define RME32_PRO_REVISION_WITH_8414 150 | |
192 | ||
193 | ||
017ce802 | 194 | struct rme32 { |
1da177e4 LT |
195 | spinlock_t lock; |
196 | int irq; | |
197 | unsigned long port; | |
198 | void __iomem *iobase; | |
199 | ||
200 | u32 wcreg; /* cached write control register value */ | |
201 | u32 wcreg_spdif; /* S/PDIF setup */ | |
202 | u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ | |
203 | u32 rcreg; /* cached read control register value */ | |
204 | ||
205 | u8 rev; /* card revision number */ | |
206 | ||
017ce802 TI |
207 | struct snd_pcm_substream *playback_substream; |
208 | struct snd_pcm_substream *capture_substream; | |
1da177e4 LT |
209 | |
210 | int playback_frlog; /* log2 of framesize */ | |
211 | int capture_frlog; | |
212 | ||
213 | size_t playback_periodsize; /* in bytes, zero if not used */ | |
214 | size_t capture_periodsize; /* in bytes, zero if not used */ | |
215 | ||
216 | unsigned int fullduplex_mode; | |
217 | int running; | |
218 | ||
017ce802 TI |
219 | struct snd_pcm_indirect playback_pcm; |
220 | struct snd_pcm_indirect capture_pcm; | |
1da177e4 | 221 | |
017ce802 TI |
222 | struct snd_card *card; |
223 | struct snd_pcm *spdif_pcm; | |
224 | struct snd_pcm *adat_pcm; | |
1da177e4 | 225 | struct pci_dev *pci; |
017ce802 TI |
226 | struct snd_kcontrol *spdif_ctl; |
227 | }; | |
1da177e4 | 228 | |
f40b6890 | 229 | static struct pci_device_id snd_rme32_ids[] = { |
8b7fc421 | 230 | {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32, |
1da177e4 | 231 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,}, |
8b7fc421 | 232 | {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8, |
1da177e4 | 233 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,}, |
8b7fc421 | 234 | {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO, |
1da177e4 LT |
235 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,}, |
236 | {0,} | |
237 | }; | |
238 | ||
239 | MODULE_DEVICE_TABLE(pci, snd_rme32_ids); | |
240 | ||
241 | #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START) | |
8b7fc421 | 242 | #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414) |
1da177e4 | 243 | |
017ce802 | 244 | static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream); |
1da177e4 | 245 | |
017ce802 | 246 | static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream); |
1da177e4 | 247 | |
017ce802 | 248 | static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd); |
1da177e4 | 249 | |
017ce802 | 250 | static void snd_rme32_proc_init(struct rme32 * rme32); |
1da177e4 | 251 | |
017ce802 | 252 | static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32); |
1da177e4 | 253 | |
017ce802 | 254 | static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32) |
1da177e4 LT |
255 | { |
256 | return (readl(rme32->iobase + RME32_IO_GET_POS) | |
257 | & RME32_RCR_AUDIO_ADDR_MASK); | |
258 | } | |
259 | ||
1da177e4 | 260 | /* silence callback for halfduplex mode */ |
017ce802 | 261 | static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */ |
1da177e4 LT |
262 | snd_pcm_uframes_t pos, |
263 | snd_pcm_uframes_t count) | |
264 | { | |
017ce802 | 265 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
266 | count <<= rme32->playback_frlog; |
267 | pos <<= rme32->playback_frlog; | |
268 | memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count); | |
269 | return 0; | |
270 | } | |
271 | ||
272 | /* copy callback for halfduplex mode */ | |
017ce802 | 273 | static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */ |
1da177e4 LT |
274 | snd_pcm_uframes_t pos, |
275 | void __user *src, snd_pcm_uframes_t count) | |
276 | { | |
017ce802 | 277 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
278 | count <<= rme32->playback_frlog; |
279 | pos <<= rme32->playback_frlog; | |
280 | if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, | |
281 | src, count)) | |
282 | return -EFAULT; | |
283 | return 0; | |
284 | } | |
285 | ||
286 | /* copy callback for halfduplex mode */ | |
017ce802 | 287 | static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */ |
1da177e4 LT |
288 | snd_pcm_uframes_t pos, |
289 | void __user *dst, snd_pcm_uframes_t count) | |
290 | { | |
017ce802 | 291 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
292 | count <<= rme32->capture_frlog; |
293 | pos <<= rme32->capture_frlog; | |
294 | if (copy_to_user_fromio(dst, | |
295 | rme32->iobase + RME32_IO_DATA_BUFFER + pos, | |
296 | count)) | |
297 | return -EFAULT; | |
298 | return 0; | |
299 | } | |
300 | ||
301 | /* | |
7f927fcc | 302 | * SPDIF I/O capabilities (half-duplex mode) |
1da177e4 | 303 | */ |
017ce802 | 304 | static struct snd_pcm_hardware snd_rme32_spdif_info = { |
1da177e4 LT |
305 | .info = (SNDRV_PCM_INFO_MMAP_IOMEM | |
306 | SNDRV_PCM_INFO_MMAP_VALID | | |
307 | SNDRV_PCM_INFO_INTERLEAVED | | |
308 | SNDRV_PCM_INFO_PAUSE | | |
309 | SNDRV_PCM_INFO_SYNC_START), | |
310 | .formats = (SNDRV_PCM_FMTBIT_S16_LE | | |
311 | SNDRV_PCM_FMTBIT_S32_LE), | |
312 | .rates = (SNDRV_PCM_RATE_32000 | | |
313 | SNDRV_PCM_RATE_44100 | | |
314 | SNDRV_PCM_RATE_48000), | |
315 | .rate_min = 32000, | |
316 | .rate_max = 48000, | |
317 | .channels_min = 2, | |
318 | .channels_max = 2, | |
319 | .buffer_bytes_max = RME32_BUFFER_SIZE, | |
320 | .period_bytes_min = RME32_BLOCK_SIZE, | |
321 | .period_bytes_max = RME32_BLOCK_SIZE, | |
322 | .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, | |
323 | .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, | |
324 | .fifo_size = 0, | |
325 | }; | |
326 | ||
327 | /* | |
7f927fcc | 328 | * ADAT I/O capabilities (half-duplex mode) |
1da177e4 | 329 | */ |
017ce802 | 330 | static struct snd_pcm_hardware snd_rme32_adat_info = |
1da177e4 LT |
331 | { |
332 | .info = (SNDRV_PCM_INFO_MMAP_IOMEM | | |
333 | SNDRV_PCM_INFO_MMAP_VALID | | |
334 | SNDRV_PCM_INFO_INTERLEAVED | | |
335 | SNDRV_PCM_INFO_PAUSE | | |
336 | SNDRV_PCM_INFO_SYNC_START), | |
337 | .formats= SNDRV_PCM_FMTBIT_S16_LE, | |
338 | .rates = (SNDRV_PCM_RATE_44100 | | |
339 | SNDRV_PCM_RATE_48000), | |
340 | .rate_min = 44100, | |
341 | .rate_max = 48000, | |
342 | .channels_min = 8, | |
343 | .channels_max = 8, | |
344 | .buffer_bytes_max = RME32_BUFFER_SIZE, | |
345 | .period_bytes_min = RME32_BLOCK_SIZE, | |
346 | .period_bytes_max = RME32_BLOCK_SIZE, | |
347 | .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, | |
348 | .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, | |
349 | .fifo_size = 0, | |
350 | }; | |
351 | ||
352 | /* | |
7f927fcc | 353 | * SPDIF I/O capabilities (full-duplex mode) |
1da177e4 | 354 | */ |
017ce802 | 355 | static struct snd_pcm_hardware snd_rme32_spdif_fd_info = { |
1da177e4 LT |
356 | .info = (SNDRV_PCM_INFO_MMAP | |
357 | SNDRV_PCM_INFO_MMAP_VALID | | |
358 | SNDRV_PCM_INFO_INTERLEAVED | | |
359 | SNDRV_PCM_INFO_PAUSE | | |
360 | SNDRV_PCM_INFO_SYNC_START), | |
361 | .formats = (SNDRV_PCM_FMTBIT_S16_LE | | |
362 | SNDRV_PCM_FMTBIT_S32_LE), | |
363 | .rates = (SNDRV_PCM_RATE_32000 | | |
364 | SNDRV_PCM_RATE_44100 | | |
365 | SNDRV_PCM_RATE_48000), | |
366 | .rate_min = 32000, | |
367 | .rate_max = 48000, | |
368 | .channels_min = 2, | |
369 | .channels_max = 2, | |
370 | .buffer_bytes_max = RME32_MID_BUFFER_SIZE, | |
371 | .period_bytes_min = RME32_BLOCK_SIZE, | |
372 | .period_bytes_max = RME32_BLOCK_SIZE, | |
373 | .periods_min = 2, | |
374 | .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE, | |
375 | .fifo_size = 0, | |
376 | }; | |
377 | ||
378 | /* | |
7f927fcc | 379 | * ADAT I/O capabilities (full-duplex mode) |
1da177e4 | 380 | */ |
017ce802 | 381 | static struct snd_pcm_hardware snd_rme32_adat_fd_info = |
1da177e4 LT |
382 | { |
383 | .info = (SNDRV_PCM_INFO_MMAP | | |
384 | SNDRV_PCM_INFO_MMAP_VALID | | |
385 | SNDRV_PCM_INFO_INTERLEAVED | | |
386 | SNDRV_PCM_INFO_PAUSE | | |
387 | SNDRV_PCM_INFO_SYNC_START), | |
388 | .formats= SNDRV_PCM_FMTBIT_S16_LE, | |
389 | .rates = (SNDRV_PCM_RATE_44100 | | |
390 | SNDRV_PCM_RATE_48000), | |
391 | .rate_min = 44100, | |
392 | .rate_max = 48000, | |
393 | .channels_min = 8, | |
394 | .channels_max = 8, | |
395 | .buffer_bytes_max = RME32_MID_BUFFER_SIZE, | |
396 | .period_bytes_min = RME32_BLOCK_SIZE, | |
397 | .period_bytes_max = RME32_BLOCK_SIZE, | |
398 | .periods_min = 2, | |
399 | .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE, | |
400 | .fifo_size = 0, | |
401 | }; | |
402 | ||
017ce802 | 403 | static void snd_rme32_reset_dac(struct rme32 *rme32) |
1da177e4 LT |
404 | { |
405 | writel(rme32->wcreg | RME32_WCR_PD, | |
406 | rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
407 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
408 | } | |
409 | ||
017ce802 | 410 | static int snd_rme32_playback_getrate(struct rme32 * rme32) |
1da177e4 LT |
411 | { |
412 | int rate; | |
413 | ||
414 | rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + | |
415 | (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); | |
416 | switch (rate) { | |
417 | case 1: | |
418 | rate = 32000; | |
419 | break; | |
420 | case 2: | |
421 | rate = 44100; | |
422 | break; | |
423 | case 3: | |
424 | rate = 48000; | |
425 | break; | |
426 | default: | |
427 | return -1; | |
428 | } | |
429 | return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate; | |
430 | } | |
431 | ||
017ce802 | 432 | static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat) |
1da177e4 LT |
433 | { |
434 | int n; | |
435 | ||
436 | *is_adat = 0; | |
437 | if (rme32->rcreg & RME32_RCR_LOCK) { | |
438 | /* ADAT rate */ | |
439 | *is_adat = 1; | |
440 | } | |
441 | if (rme32->rcreg & RME32_RCR_ERF) { | |
442 | return -1; | |
443 | } | |
444 | ||
445 | /* S/PDIF rate */ | |
446 | n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) + | |
447 | (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) + | |
448 | (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2); | |
449 | ||
450 | if (RME32_PRO_WITH_8414(rme32)) | |
451 | switch (n) { /* supporting the CS8414 */ | |
452 | case 0: | |
453 | case 1: | |
454 | case 2: | |
455 | return -1; | |
456 | case 3: | |
457 | return 96000; | |
458 | case 4: | |
459 | return 88200; | |
460 | case 5: | |
461 | return 48000; | |
462 | case 6: | |
463 | return 44100; | |
464 | case 7: | |
465 | return 32000; | |
466 | default: | |
467 | return -1; | |
468 | break; | |
469 | } | |
470 | else | |
471 | switch (n) { /* supporting the CS8412 */ | |
472 | case 0: | |
473 | return -1; | |
474 | case 1: | |
475 | return 48000; | |
476 | case 2: | |
477 | return 44100; | |
478 | case 3: | |
479 | return 32000; | |
480 | case 4: | |
481 | return 48000; | |
482 | case 5: | |
483 | return 44100; | |
484 | case 6: | |
485 | return 44056; | |
486 | case 7: | |
487 | return 32000; | |
488 | default: | |
489 | break; | |
490 | } | |
491 | return -1; | |
492 | } | |
493 | ||
017ce802 | 494 | static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate) |
1da177e4 LT |
495 | { |
496 | int ds; | |
497 | ||
498 | ds = rme32->wcreg & RME32_WCR_DS_BM; | |
499 | switch (rate) { | |
500 | case 32000: | |
501 | rme32->wcreg &= ~RME32_WCR_DS_BM; | |
502 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & | |
503 | ~RME32_WCR_FREQ_1; | |
504 | break; | |
505 | case 44100: | |
506 | rme32->wcreg &= ~RME32_WCR_DS_BM; | |
507 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & | |
508 | ~RME32_WCR_FREQ_0; | |
509 | break; | |
510 | case 48000: | |
511 | rme32->wcreg &= ~RME32_WCR_DS_BM; | |
512 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | | |
513 | RME32_WCR_FREQ_1; | |
514 | break; | |
515 | case 64000: | |
8b7fc421 | 516 | if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) |
1da177e4 LT |
517 | return -EINVAL; |
518 | rme32->wcreg |= RME32_WCR_DS_BM; | |
519 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & | |
520 | ~RME32_WCR_FREQ_1; | |
521 | break; | |
522 | case 88200: | |
8b7fc421 | 523 | if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) |
1da177e4 LT |
524 | return -EINVAL; |
525 | rme32->wcreg |= RME32_WCR_DS_BM; | |
526 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & | |
527 | ~RME32_WCR_FREQ_0; | |
528 | break; | |
529 | case 96000: | |
8b7fc421 | 530 | if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) |
1da177e4 LT |
531 | return -EINVAL; |
532 | rme32->wcreg |= RME32_WCR_DS_BM; | |
533 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | | |
534 | RME32_WCR_FREQ_1; | |
535 | break; | |
536 | default: | |
537 | return -EINVAL; | |
538 | } | |
539 | if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) || | |
540 | (ds && !(rme32->wcreg & RME32_WCR_DS_BM))) | |
541 | { | |
542 | /* change to/from double-speed: reset the DAC (if available) */ | |
543 | snd_rme32_reset_dac(rme32); | |
544 | } else { | |
545 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
546 | } | |
547 | return 0; | |
548 | } | |
549 | ||
017ce802 | 550 | static int snd_rme32_setclockmode(struct rme32 * rme32, int mode) |
1da177e4 LT |
551 | { |
552 | switch (mode) { | |
553 | case RME32_CLOCKMODE_SLAVE: | |
554 | /* AutoSync */ | |
555 | rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) & | |
556 | ~RME32_WCR_FREQ_1; | |
557 | break; | |
558 | case RME32_CLOCKMODE_MASTER_32: | |
559 | /* Internal 32.0kHz */ | |
560 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & | |
561 | ~RME32_WCR_FREQ_1; | |
562 | break; | |
563 | case RME32_CLOCKMODE_MASTER_44: | |
564 | /* Internal 44.1kHz */ | |
565 | rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) | | |
566 | RME32_WCR_FREQ_1; | |
567 | break; | |
568 | case RME32_CLOCKMODE_MASTER_48: | |
569 | /* Internal 48.0kHz */ | |
570 | rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | | |
571 | RME32_WCR_FREQ_1; | |
572 | break; | |
573 | default: | |
574 | return -EINVAL; | |
575 | } | |
576 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
577 | return 0; | |
578 | } | |
579 | ||
017ce802 | 580 | static int snd_rme32_getclockmode(struct rme32 * rme32) |
1da177e4 LT |
581 | { |
582 | return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + | |
583 | (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); | |
584 | } | |
585 | ||
017ce802 | 586 | static int snd_rme32_setinputtype(struct rme32 * rme32, int type) |
1da177e4 LT |
587 | { |
588 | switch (type) { | |
589 | case RME32_INPUT_OPTICAL: | |
590 | rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) & | |
591 | ~RME32_WCR_INP_1; | |
592 | break; | |
593 | case RME32_INPUT_COAXIAL: | |
594 | rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) & | |
595 | ~RME32_WCR_INP_1; | |
596 | break; | |
597 | case RME32_INPUT_INTERNAL: | |
598 | rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) | | |
599 | RME32_WCR_INP_1; | |
600 | break; | |
601 | case RME32_INPUT_XLR: | |
602 | rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) | | |
603 | RME32_WCR_INP_1; | |
604 | break; | |
605 | default: | |
606 | return -EINVAL; | |
607 | } | |
608 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
609 | return 0; | |
610 | } | |
611 | ||
017ce802 | 612 | static int snd_rme32_getinputtype(struct rme32 * rme32) |
1da177e4 LT |
613 | { |
614 | return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) + | |
615 | (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1); | |
616 | } | |
617 | ||
618 | static void | |
017ce802 | 619 | snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback) |
1da177e4 LT |
620 | { |
621 | int frlog; | |
622 | ||
623 | if (n_channels == 2) { | |
624 | frlog = 1; | |
625 | } else { | |
626 | /* assume 8 channels */ | |
627 | frlog = 3; | |
628 | } | |
629 | if (is_playback) { | |
630 | frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; | |
631 | rme32->playback_frlog = frlog; | |
632 | } else { | |
633 | frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; | |
634 | rme32->capture_frlog = frlog; | |
635 | } | |
636 | } | |
637 | ||
017ce802 | 638 | static int snd_rme32_setformat(struct rme32 * rme32, int format) |
1da177e4 LT |
639 | { |
640 | switch (format) { | |
641 | case SNDRV_PCM_FORMAT_S16_LE: | |
642 | rme32->wcreg &= ~RME32_WCR_MODE24; | |
643 | break; | |
644 | case SNDRV_PCM_FORMAT_S32_LE: | |
645 | rme32->wcreg |= RME32_WCR_MODE24; | |
646 | break; | |
647 | default: | |
648 | return -EINVAL; | |
649 | } | |
650 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
651 | return 0; | |
652 | } | |
653 | ||
654 | static int | |
017ce802 TI |
655 | snd_rme32_playback_hw_params(struct snd_pcm_substream *substream, |
656 | struct snd_pcm_hw_params *params) | |
1da177e4 LT |
657 | { |
658 | int err, rate, dummy; | |
017ce802 TI |
659 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
660 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
661 | |
662 | if (rme32->fullduplex_mode) { | |
663 | err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params)); | |
664 | if (err < 0) | |
665 | return err; | |
666 | } else { | |
4d23359b CL |
667 | runtime->dma_area = (void __force *)(rme32->iobase + |
668 | RME32_IO_DATA_BUFFER); | |
1da177e4 LT |
669 | runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER; |
670 | runtime->dma_bytes = RME32_BUFFER_SIZE; | |
671 | } | |
672 | ||
673 | spin_lock_irq(&rme32->lock); | |
674 | if ((rme32->rcreg & RME32_RCR_KMODE) && | |
675 | (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) { | |
676 | /* AutoSync */ | |
677 | if ((int)params_rate(params) != rate) { | |
678 | spin_unlock_irq(&rme32->lock); | |
679 | return -EIO; | |
680 | } | |
681 | } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) { | |
682 | spin_unlock_irq(&rme32->lock); | |
683 | return err; | |
684 | } | |
685 | if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) { | |
686 | spin_unlock_irq(&rme32->lock); | |
687 | return err; | |
688 | } | |
689 | ||
690 | snd_rme32_setframelog(rme32, params_channels(params), 1); | |
691 | if (rme32->capture_periodsize != 0) { | |
692 | if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) { | |
693 | spin_unlock_irq(&rme32->lock); | |
694 | return -EBUSY; | |
695 | } | |
696 | } | |
697 | rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog; | |
698 | /* S/PDIF setup */ | |
699 | if ((rme32->wcreg & RME32_WCR_ADAT) == 0) { | |
700 | rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); | |
701 | rme32->wcreg |= rme32->wcreg_spdif_stream; | |
702 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
703 | } | |
704 | spin_unlock_irq(&rme32->lock); | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | static int | |
017ce802 TI |
710 | snd_rme32_capture_hw_params(struct snd_pcm_substream *substream, |
711 | struct snd_pcm_hw_params *params) | |
1da177e4 LT |
712 | { |
713 | int err, isadat, rate; | |
017ce802 TI |
714 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
715 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
716 | |
717 | if (rme32->fullduplex_mode) { | |
718 | err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params)); | |
719 | if (err < 0) | |
720 | return err; | |
721 | } else { | |
4d23359b CL |
722 | runtime->dma_area = (void __force *)rme32->iobase + |
723 | RME32_IO_DATA_BUFFER; | |
1da177e4 LT |
724 | runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER; |
725 | runtime->dma_bytes = RME32_BUFFER_SIZE; | |
726 | } | |
727 | ||
728 | spin_lock_irq(&rme32->lock); | |
729 | /* enable AutoSync for record-preparing */ | |
730 | rme32->wcreg |= RME32_WCR_AUTOSYNC; | |
731 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
732 | ||
733 | if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) { | |
734 | spin_unlock_irq(&rme32->lock); | |
735 | return err; | |
736 | } | |
737 | if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) { | |
738 | spin_unlock_irq(&rme32->lock); | |
739 | return err; | |
740 | } | |
741 | if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) { | |
742 | if ((int)params_rate(params) != rate) { | |
743 | spin_unlock_irq(&rme32->lock); | |
744 | return -EIO; | |
745 | } | |
746 | if ((isadat && runtime->hw.channels_min == 2) || | |
747 | (!isadat && runtime->hw.channels_min == 8)) { | |
748 | spin_unlock_irq(&rme32->lock); | |
749 | return -EIO; | |
750 | } | |
751 | } | |
752 | /* AutoSync off for recording */ | |
753 | rme32->wcreg &= ~RME32_WCR_AUTOSYNC; | |
754 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
755 | ||
756 | snd_rme32_setframelog(rme32, params_channels(params), 0); | |
757 | if (rme32->playback_periodsize != 0) { | |
758 | if (params_period_size(params) << rme32->capture_frlog != | |
759 | rme32->playback_periodsize) { | |
760 | spin_unlock_irq(&rme32->lock); | |
761 | return -EBUSY; | |
762 | } | |
763 | } | |
764 | rme32->capture_periodsize = | |
765 | params_period_size(params) << rme32->capture_frlog; | |
766 | spin_unlock_irq(&rme32->lock); | |
767 | ||
768 | return 0; | |
769 | } | |
770 | ||
017ce802 | 771 | static int snd_rme32_pcm_hw_free(struct snd_pcm_substream *substream) |
1da177e4 | 772 | { |
017ce802 | 773 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
774 | if (! rme32->fullduplex_mode) |
775 | return 0; | |
776 | return snd_pcm_lib_free_pages(substream); | |
777 | } | |
778 | ||
017ce802 | 779 | static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause) |
1da177e4 LT |
780 | { |
781 | if (!from_pause) { | |
782 | writel(0, rme32->iobase + RME32_IO_RESET_POS); | |
783 | } | |
784 | ||
785 | rme32->wcreg |= RME32_WCR_START; | |
786 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
787 | } | |
788 | ||
017ce802 | 789 | static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause) |
1da177e4 LT |
790 | { |
791 | /* | |
792 | * Check if there is an unconfirmed IRQ, if so confirm it, or else | |
793 | * the hardware will not stop generating interrupts | |
794 | */ | |
795 | rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
796 | if (rme32->rcreg & RME32_RCR_IRQ) { | |
797 | writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ); | |
798 | } | |
799 | rme32->wcreg &= ~RME32_WCR_START; | |
800 | if (rme32->wcreg & RME32_WCR_SEL) | |
801 | rme32->wcreg |= RME32_WCR_MUTE; | |
802 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
803 | if (! to_pause) | |
804 | writel(0, rme32->iobase + RME32_IO_RESET_POS); | |
805 | } | |
806 | ||
7d12e780 | 807 | static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id) |
1da177e4 | 808 | { |
017ce802 | 809 | struct rme32 *rme32 = (struct rme32 *) dev_id; |
1da177e4 LT |
810 | |
811 | rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
812 | if (!(rme32->rcreg & RME32_RCR_IRQ)) { | |
813 | return IRQ_NONE; | |
814 | } else { | |
815 | if (rme32->capture_substream) { | |
816 | snd_pcm_period_elapsed(rme32->capture_substream); | |
817 | } | |
818 | if (rme32->playback_substream) { | |
819 | snd_pcm_period_elapsed(rme32->playback_substream); | |
820 | } | |
821 | writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ); | |
822 | } | |
823 | return IRQ_HANDLED; | |
824 | } | |
825 | ||
826 | static unsigned int period_bytes[] = { RME32_BLOCK_SIZE }; | |
827 | ||
828 | ||
017ce802 | 829 | static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { |
1da177e4 LT |
830 | .count = ARRAY_SIZE(period_bytes), |
831 | .list = period_bytes, | |
832 | .mask = 0 | |
833 | }; | |
834 | ||
017ce802 | 835 | static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime) |
1da177e4 LT |
836 | { |
837 | if (! rme32->fullduplex_mode) { | |
838 | snd_pcm_hw_constraint_minmax(runtime, | |
839 | SNDRV_PCM_HW_PARAM_BUFFER_BYTES, | |
840 | RME32_BUFFER_SIZE, RME32_BUFFER_SIZE); | |
841 | snd_pcm_hw_constraint_list(runtime, 0, | |
842 | SNDRV_PCM_HW_PARAM_PERIOD_BYTES, | |
843 | &hw_constraints_period_bytes); | |
844 | } | |
845 | } | |
846 | ||
017ce802 | 847 | static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
848 | { |
849 | int rate, dummy; | |
017ce802 TI |
850 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
851 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
852 | |
853 | snd_pcm_set_sync(substream); | |
854 | ||
855 | spin_lock_irq(&rme32->lock); | |
856 | if (rme32->playback_substream != NULL) { | |
857 | spin_unlock_irq(&rme32->lock); | |
858 | return -EBUSY; | |
859 | } | |
860 | rme32->wcreg &= ~RME32_WCR_ADAT; | |
861 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
862 | rme32->playback_substream = substream; | |
863 | spin_unlock_irq(&rme32->lock); | |
864 | ||
865 | if (rme32->fullduplex_mode) | |
866 | runtime->hw = snd_rme32_spdif_fd_info; | |
867 | else | |
868 | runtime->hw = snd_rme32_spdif_info; | |
8b7fc421 | 869 | if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) { |
1da177e4 LT |
870 | runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; |
871 | runtime->hw.rate_max = 96000; | |
872 | } | |
873 | if ((rme32->rcreg & RME32_RCR_KMODE) && | |
874 | (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) { | |
875 | /* AutoSync */ | |
918f3a0e | 876 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); |
1da177e4 LT |
877 | runtime->hw.rate_min = rate; |
878 | runtime->hw.rate_max = rate; | |
879 | } | |
880 | ||
881 | snd_rme32_set_buffer_constraint(rme32, runtime); | |
882 | ||
883 | rme32->wcreg_spdif_stream = rme32->wcreg_spdif; | |
884 | rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
885 | snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE | | |
886 | SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id); | |
887 | return 0; | |
888 | } | |
889 | ||
017ce802 | 890 | static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
891 | { |
892 | int isadat, rate; | |
017ce802 TI |
893 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
894 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
895 | |
896 | snd_pcm_set_sync(substream); | |
897 | ||
898 | spin_lock_irq(&rme32->lock); | |
899 | if (rme32->capture_substream != NULL) { | |
900 | spin_unlock_irq(&rme32->lock); | |
901 | return -EBUSY; | |
902 | } | |
903 | rme32->capture_substream = substream; | |
904 | spin_unlock_irq(&rme32->lock); | |
905 | ||
906 | if (rme32->fullduplex_mode) | |
907 | runtime->hw = snd_rme32_spdif_fd_info; | |
908 | else | |
909 | runtime->hw = snd_rme32_spdif_info; | |
910 | if (RME32_PRO_WITH_8414(rme32)) { | |
911 | runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; | |
912 | runtime->hw.rate_max = 96000; | |
913 | } | |
914 | if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) { | |
915 | if (isadat) { | |
916 | return -EIO; | |
917 | } | |
918f3a0e | 918 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); |
1da177e4 LT |
919 | runtime->hw.rate_min = rate; |
920 | runtime->hw.rate_max = rate; | |
921 | } | |
922 | ||
923 | snd_rme32_set_buffer_constraint(rme32, runtime); | |
924 | ||
925 | return 0; | |
926 | } | |
927 | ||
928 | static int | |
017ce802 | 929 | snd_rme32_playback_adat_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
930 | { |
931 | int rate, dummy; | |
017ce802 TI |
932 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
933 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
934 | |
935 | snd_pcm_set_sync(substream); | |
936 | ||
937 | spin_lock_irq(&rme32->lock); | |
938 | if (rme32->playback_substream != NULL) { | |
939 | spin_unlock_irq(&rme32->lock); | |
940 | return -EBUSY; | |
941 | } | |
942 | rme32->wcreg |= RME32_WCR_ADAT; | |
943 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
944 | rme32->playback_substream = substream; | |
945 | spin_unlock_irq(&rme32->lock); | |
946 | ||
947 | if (rme32->fullduplex_mode) | |
948 | runtime->hw = snd_rme32_adat_fd_info; | |
949 | else | |
950 | runtime->hw = snd_rme32_adat_info; | |
951 | if ((rme32->rcreg & RME32_RCR_KMODE) && | |
952 | (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) { | |
953 | /* AutoSync */ | |
918f3a0e | 954 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); |
1da177e4 LT |
955 | runtime->hw.rate_min = rate; |
956 | runtime->hw.rate_max = rate; | |
957 | } | |
958 | ||
959 | snd_rme32_set_buffer_constraint(rme32, runtime); | |
960 | return 0; | |
961 | } | |
962 | ||
963 | static int | |
017ce802 | 964 | snd_rme32_capture_adat_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
965 | { |
966 | int isadat, rate; | |
017ce802 TI |
967 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
968 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
969 | |
970 | if (rme32->fullduplex_mode) | |
971 | runtime->hw = snd_rme32_adat_fd_info; | |
972 | else | |
973 | runtime->hw = snd_rme32_adat_info; | |
974 | if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) { | |
975 | if (!isadat) { | |
976 | return -EIO; | |
977 | } | |
918f3a0e | 978 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); |
1da177e4 LT |
979 | runtime->hw.rate_min = rate; |
980 | runtime->hw.rate_max = rate; | |
981 | } | |
982 | ||
983 | snd_pcm_set_sync(substream); | |
984 | ||
985 | spin_lock_irq(&rme32->lock); | |
986 | if (rme32->capture_substream != NULL) { | |
987 | spin_unlock_irq(&rme32->lock); | |
988 | return -EBUSY; | |
989 | } | |
990 | rme32->capture_substream = substream; | |
991 | spin_unlock_irq(&rme32->lock); | |
992 | ||
993 | snd_rme32_set_buffer_constraint(rme32, runtime); | |
994 | return 0; | |
995 | } | |
996 | ||
017ce802 | 997 | static int snd_rme32_playback_close(struct snd_pcm_substream *substream) |
1da177e4 | 998 | { |
017ce802 | 999 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1000 | int spdif = 0; |
1001 | ||
1002 | spin_lock_irq(&rme32->lock); | |
1003 | rme32->playback_substream = NULL; | |
1004 | rme32->playback_periodsize = 0; | |
1005 | spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0; | |
1006 | spin_unlock_irq(&rme32->lock); | |
1007 | if (spdif) { | |
1008 | rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
1009 | snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE | | |
1010 | SNDRV_CTL_EVENT_MASK_INFO, | |
1011 | &rme32->spdif_ctl->id); | |
1012 | } | |
1013 | return 0; | |
1014 | } | |
1015 | ||
017ce802 | 1016 | static int snd_rme32_capture_close(struct snd_pcm_substream *substream) |
1da177e4 | 1017 | { |
017ce802 | 1018 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1019 | |
1020 | spin_lock_irq(&rme32->lock); | |
1021 | rme32->capture_substream = NULL; | |
1022 | rme32->capture_periodsize = 0; | |
1023 | spin_unlock(&rme32->lock); | |
1024 | return 0; | |
1025 | } | |
1026 | ||
017ce802 | 1027 | static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1028 | { |
017ce802 | 1029 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1030 | |
1031 | spin_lock_irq(&rme32->lock); | |
1032 | if (rme32->fullduplex_mode) { | |
1033 | memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm)); | |
1034 | rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE; | |
1035 | rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); | |
1036 | } else { | |
1037 | writel(0, rme32->iobase + RME32_IO_RESET_POS); | |
1038 | } | |
1039 | if (rme32->wcreg & RME32_WCR_SEL) | |
1040 | rme32->wcreg &= ~RME32_WCR_MUTE; | |
1041 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
1042 | spin_unlock_irq(&rme32->lock); | |
1043 | return 0; | |
1044 | } | |
1045 | ||
017ce802 | 1046 | static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1047 | { |
017ce802 | 1048 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1049 | |
1050 | spin_lock_irq(&rme32->lock); | |
1051 | if (rme32->fullduplex_mode) { | |
1052 | memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm)); | |
1053 | rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE; | |
1054 | rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2; | |
1055 | rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); | |
1056 | } else { | |
1057 | writel(0, rme32->iobase + RME32_IO_RESET_POS); | |
1058 | } | |
1059 | spin_unlock_irq(&rme32->lock); | |
1060 | return 0; | |
1061 | } | |
1062 | ||
1063 | static int | |
017ce802 | 1064 | snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 | 1065 | { |
017ce802 | 1066 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
017ce802 | 1067 | struct snd_pcm_substream *s; |
1da177e4 LT |
1068 | |
1069 | spin_lock(&rme32->lock); | |
ef991b95 | 1070 | snd_pcm_group_for_each_entry(s, substream) { |
1da177e4 LT |
1071 | if (s != rme32->playback_substream && |
1072 | s != rme32->capture_substream) | |
1073 | continue; | |
1074 | switch (cmd) { | |
1075 | case SNDRV_PCM_TRIGGER_START: | |
1076 | rme32->running |= (1 << s->stream); | |
1077 | if (rme32->fullduplex_mode) { | |
1078 | /* remember the current DMA position */ | |
1079 | if (s == rme32->playback_substream) { | |
1080 | rme32->playback_pcm.hw_io = | |
1081 | rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); | |
1082 | } else { | |
1083 | rme32->capture_pcm.hw_io = | |
1084 | rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); | |
1085 | } | |
1086 | } | |
1087 | break; | |
1088 | case SNDRV_PCM_TRIGGER_STOP: | |
1089 | rme32->running &= ~(1 << s->stream); | |
1090 | break; | |
1091 | } | |
1092 | snd_pcm_trigger_done(s, substream); | |
1093 | } | |
1094 | ||
1095 | /* prefill playback buffer */ | |
1096 | if (cmd == SNDRV_PCM_TRIGGER_START && rme32->fullduplex_mode) { | |
ef991b95 | 1097 | snd_pcm_group_for_each_entry(s, substream) { |
1da177e4 LT |
1098 | if (s == rme32->playback_substream) { |
1099 | s->ops->ack(s); | |
1100 | break; | |
1101 | } | |
1102 | } | |
1103 | } | |
1104 | ||
1105 | switch (cmd) { | |
1106 | case SNDRV_PCM_TRIGGER_START: | |
1107 | if (rme32->running && ! RME32_ISWORKING(rme32)) | |
1108 | snd_rme32_pcm_start(rme32, 0); | |
1109 | break; | |
1110 | case SNDRV_PCM_TRIGGER_STOP: | |
1111 | if (! rme32->running && RME32_ISWORKING(rme32)) | |
1112 | snd_rme32_pcm_stop(rme32, 0); | |
1113 | break; | |
1114 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
1115 | if (rme32->running && RME32_ISWORKING(rme32)) | |
1116 | snd_rme32_pcm_stop(rme32, 1); | |
1117 | break; | |
1118 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
1119 | if (rme32->running && ! RME32_ISWORKING(rme32)) | |
1120 | snd_rme32_pcm_start(rme32, 1); | |
1121 | break; | |
1122 | } | |
1123 | spin_unlock(&rme32->lock); | |
1124 | return 0; | |
1125 | } | |
1126 | ||
1127 | /* pointer callback for halfduplex mode */ | |
1128 | static snd_pcm_uframes_t | |
017ce802 | 1129 | snd_rme32_playback_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 1130 | { |
017ce802 | 1131 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1132 | return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog; |
1133 | } | |
1134 | ||
1135 | static snd_pcm_uframes_t | |
017ce802 | 1136 | snd_rme32_capture_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 1137 | { |
017ce802 | 1138 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1139 | return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog; |
1140 | } | |
1141 | ||
1142 | ||
1143 | /* ack and pointer callbacks for fullduplex mode */ | |
017ce802 TI |
1144 | static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream, |
1145 | struct snd_pcm_indirect *rec, size_t bytes) | |
1da177e4 | 1146 | { |
017ce802 | 1147 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1148 | memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, |
1149 | substream->runtime->dma_area + rec->sw_data, bytes); | |
1150 | } | |
1151 | ||
017ce802 | 1152 | static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream) |
1da177e4 | 1153 | { |
017ce802 TI |
1154 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1155 | struct snd_pcm_indirect *rec, *cprec; | |
1da177e4 LT |
1156 | |
1157 | rec = &rme32->playback_pcm; | |
1158 | cprec = &rme32->capture_pcm; | |
1159 | spin_lock(&rme32->lock); | |
1160 | rec->hw_queue_size = RME32_BUFFER_SIZE; | |
1161 | if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE)) | |
1162 | rec->hw_queue_size -= cprec->hw_ready; | |
1163 | spin_unlock(&rme32->lock); | |
1164 | snd_pcm_indirect_playback_transfer(substream, rec, | |
1165 | snd_rme32_pb_trans_copy); | |
1166 | return 0; | |
1167 | } | |
1168 | ||
017ce802 TI |
1169 | static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream, |
1170 | struct snd_pcm_indirect *rec, size_t bytes) | |
1da177e4 | 1171 | { |
017ce802 | 1172 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1173 | memcpy_fromio(substream->runtime->dma_area + rec->sw_data, |
1174 | rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, | |
1175 | bytes); | |
1176 | } | |
1177 | ||
017ce802 | 1178 | static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream) |
1da177e4 | 1179 | { |
017ce802 | 1180 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1181 | snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm, |
1182 | snd_rme32_cp_trans_copy); | |
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | static snd_pcm_uframes_t | |
017ce802 | 1187 | snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 1188 | { |
017ce802 | 1189 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1190 | return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm, |
1191 | snd_rme32_pcm_byteptr(rme32)); | |
1192 | } | |
1193 | ||
1194 | static snd_pcm_uframes_t | |
017ce802 | 1195 | snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 1196 | { |
017ce802 | 1197 | struct rme32 *rme32 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1198 | return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm, |
1199 | snd_rme32_pcm_byteptr(rme32)); | |
1200 | } | |
1201 | ||
1202 | /* for halfduplex mode */ | |
017ce802 | 1203 | static struct snd_pcm_ops snd_rme32_playback_spdif_ops = { |
1da177e4 LT |
1204 | .open = snd_rme32_playback_spdif_open, |
1205 | .close = snd_rme32_playback_close, | |
1206 | .ioctl = snd_pcm_lib_ioctl, | |
1207 | .hw_params = snd_rme32_playback_hw_params, | |
1208 | .hw_free = snd_rme32_pcm_hw_free, | |
1209 | .prepare = snd_rme32_playback_prepare, | |
1210 | .trigger = snd_rme32_pcm_trigger, | |
1211 | .pointer = snd_rme32_playback_pointer, | |
1212 | .copy = snd_rme32_playback_copy, | |
1213 | .silence = snd_rme32_playback_silence, | |
1214 | .mmap = snd_pcm_lib_mmap_iomem, | |
1215 | }; | |
1216 | ||
017ce802 | 1217 | static struct snd_pcm_ops snd_rme32_capture_spdif_ops = { |
1da177e4 LT |
1218 | .open = snd_rme32_capture_spdif_open, |
1219 | .close = snd_rme32_capture_close, | |
1220 | .ioctl = snd_pcm_lib_ioctl, | |
1221 | .hw_params = snd_rme32_capture_hw_params, | |
1222 | .hw_free = snd_rme32_pcm_hw_free, | |
1223 | .prepare = snd_rme32_capture_prepare, | |
1224 | .trigger = snd_rme32_pcm_trigger, | |
1225 | .pointer = snd_rme32_capture_pointer, | |
1226 | .copy = snd_rme32_capture_copy, | |
1227 | .mmap = snd_pcm_lib_mmap_iomem, | |
1228 | }; | |
1229 | ||
017ce802 | 1230 | static struct snd_pcm_ops snd_rme32_playback_adat_ops = { |
1da177e4 LT |
1231 | .open = snd_rme32_playback_adat_open, |
1232 | .close = snd_rme32_playback_close, | |
1233 | .ioctl = snd_pcm_lib_ioctl, | |
1234 | .hw_params = snd_rme32_playback_hw_params, | |
1235 | .prepare = snd_rme32_playback_prepare, | |
1236 | .trigger = snd_rme32_pcm_trigger, | |
1237 | .pointer = snd_rme32_playback_pointer, | |
1238 | .copy = snd_rme32_playback_copy, | |
1239 | .silence = snd_rme32_playback_silence, | |
1240 | .mmap = snd_pcm_lib_mmap_iomem, | |
1241 | }; | |
1242 | ||
017ce802 | 1243 | static struct snd_pcm_ops snd_rme32_capture_adat_ops = { |
1da177e4 LT |
1244 | .open = snd_rme32_capture_adat_open, |
1245 | .close = snd_rme32_capture_close, | |
1246 | .ioctl = snd_pcm_lib_ioctl, | |
1247 | .hw_params = snd_rme32_capture_hw_params, | |
1248 | .prepare = snd_rme32_capture_prepare, | |
1249 | .trigger = snd_rme32_pcm_trigger, | |
1250 | .pointer = snd_rme32_capture_pointer, | |
1251 | .copy = snd_rme32_capture_copy, | |
1252 | .mmap = snd_pcm_lib_mmap_iomem, | |
1253 | }; | |
1254 | ||
1255 | /* for fullduplex mode */ | |
017ce802 | 1256 | static struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = { |
1da177e4 LT |
1257 | .open = snd_rme32_playback_spdif_open, |
1258 | .close = snd_rme32_playback_close, | |
1259 | .ioctl = snd_pcm_lib_ioctl, | |
1260 | .hw_params = snd_rme32_playback_hw_params, | |
1261 | .hw_free = snd_rme32_pcm_hw_free, | |
1262 | .prepare = snd_rme32_playback_prepare, | |
1263 | .trigger = snd_rme32_pcm_trigger, | |
1264 | .pointer = snd_rme32_playback_fd_pointer, | |
1265 | .ack = snd_rme32_playback_fd_ack, | |
1266 | }; | |
1267 | ||
017ce802 | 1268 | static struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = { |
1da177e4 LT |
1269 | .open = snd_rme32_capture_spdif_open, |
1270 | .close = snd_rme32_capture_close, | |
1271 | .ioctl = snd_pcm_lib_ioctl, | |
1272 | .hw_params = snd_rme32_capture_hw_params, | |
1273 | .hw_free = snd_rme32_pcm_hw_free, | |
1274 | .prepare = snd_rme32_capture_prepare, | |
1275 | .trigger = snd_rme32_pcm_trigger, | |
1276 | .pointer = snd_rme32_capture_fd_pointer, | |
1277 | .ack = snd_rme32_capture_fd_ack, | |
1278 | }; | |
1279 | ||
017ce802 | 1280 | static struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = { |
1da177e4 LT |
1281 | .open = snd_rme32_playback_adat_open, |
1282 | .close = snd_rme32_playback_close, | |
1283 | .ioctl = snd_pcm_lib_ioctl, | |
1284 | .hw_params = snd_rme32_playback_hw_params, | |
1285 | .prepare = snd_rme32_playback_prepare, | |
1286 | .trigger = snd_rme32_pcm_trigger, | |
1287 | .pointer = snd_rme32_playback_fd_pointer, | |
1288 | .ack = snd_rme32_playback_fd_ack, | |
1289 | }; | |
1290 | ||
017ce802 | 1291 | static struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = { |
1da177e4 LT |
1292 | .open = snd_rme32_capture_adat_open, |
1293 | .close = snd_rme32_capture_close, | |
1294 | .ioctl = snd_pcm_lib_ioctl, | |
1295 | .hw_params = snd_rme32_capture_hw_params, | |
1296 | .prepare = snd_rme32_capture_prepare, | |
1297 | .trigger = snd_rme32_pcm_trigger, | |
1298 | .pointer = snd_rme32_capture_fd_pointer, | |
1299 | .ack = snd_rme32_capture_fd_ack, | |
1300 | }; | |
1301 | ||
1302 | static void snd_rme32_free(void *private_data) | |
1303 | { | |
017ce802 | 1304 | struct rme32 *rme32 = (struct rme32 *) private_data; |
1da177e4 LT |
1305 | |
1306 | if (rme32 == NULL) { | |
1307 | return; | |
1308 | } | |
1309 | if (rme32->irq >= 0) { | |
1310 | snd_rme32_pcm_stop(rme32, 0); | |
1311 | free_irq(rme32->irq, (void *) rme32); | |
1312 | rme32->irq = -1; | |
1313 | } | |
1314 | if (rme32->iobase) { | |
1315 | iounmap(rme32->iobase); | |
1316 | rme32->iobase = NULL; | |
1317 | } | |
1318 | if (rme32->port) { | |
1319 | pci_release_regions(rme32->pci); | |
1320 | rme32->port = 0; | |
1321 | } | |
1322 | pci_disable_device(rme32->pci); | |
1323 | } | |
1324 | ||
017ce802 | 1325 | static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm) |
1da177e4 | 1326 | { |
017ce802 | 1327 | struct rme32 *rme32 = (struct rme32 *) pcm->private_data; |
1da177e4 LT |
1328 | rme32->spdif_pcm = NULL; |
1329 | } | |
1330 | ||
1331 | static void | |
017ce802 | 1332 | snd_rme32_free_adat_pcm(struct snd_pcm *pcm) |
1da177e4 | 1333 | { |
017ce802 | 1334 | struct rme32 *rme32 = (struct rme32 *) pcm->private_data; |
1da177e4 LT |
1335 | rme32->adat_pcm = NULL; |
1336 | } | |
1337 | ||
017ce802 | 1338 | static int __devinit snd_rme32_create(struct rme32 * rme32) |
1da177e4 LT |
1339 | { |
1340 | struct pci_dev *pci = rme32->pci; | |
1341 | int err; | |
1342 | ||
1343 | rme32->irq = -1; | |
1344 | spin_lock_init(&rme32->lock); | |
1345 | ||
1346 | if ((err = pci_enable_device(pci)) < 0) | |
1347 | return err; | |
1348 | ||
1349 | if ((err = pci_request_regions(pci, "RME32")) < 0) | |
1350 | return err; | |
1351 | rme32->port = pci_resource_start(rme32->pci, 0); | |
1352 | ||
4db9e4f2 HH |
1353 | rme32->iobase = ioremap_nocache(rme32->port, RME32_IO_SIZE); |
1354 | if (!rme32->iobase) { | |
99b359ba | 1355 | snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", |
1da177e4 LT |
1356 | rme32->port, rme32->port + RME32_IO_SIZE - 1); |
1357 | return -ENOMEM; | |
1358 | } | |
1359 | ||
437a5a46 TI |
1360 | if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_SHARED, |
1361 | "RME32", rme32)) { | |
688956f2 TI |
1362 | snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); |
1363 | return -EBUSY; | |
1364 | } | |
1365 | rme32->irq = pci->irq; | |
1366 | ||
1da177e4 LT |
1367 | /* read the card's revision number */ |
1368 | pci_read_config_byte(pci, 8, &rme32->rev); | |
1369 | ||
1370 | /* set up ALSA pcm device for S/PDIF */ | |
1371 | if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) { | |
1372 | return err; | |
1373 | } | |
1374 | rme32->spdif_pcm->private_data = rme32; | |
1375 | rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm; | |
1376 | strcpy(rme32->spdif_pcm->name, "Digi32 IEC958"); | |
1377 | if (rme32->fullduplex_mode) { | |
1378 | snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
1379 | &snd_rme32_playback_spdif_fd_ops); | |
1380 | snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, | |
1381 | &snd_rme32_capture_spdif_fd_ops); | |
1382 | snd_pcm_lib_preallocate_pages_for_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS, | |
1383 | snd_dma_continuous_data(GFP_KERNEL), | |
1384 | 0, RME32_MID_BUFFER_SIZE); | |
1385 | rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; | |
1386 | } else { | |
1387 | snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
1388 | &snd_rme32_playback_spdif_ops); | |
1389 | snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, | |
1390 | &snd_rme32_capture_spdif_ops); | |
1391 | rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX; | |
1392 | } | |
1393 | ||
1394 | /* set up ALSA pcm device for ADAT */ | |
8b7fc421 RD |
1395 | if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) || |
1396 | (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) { | |
1da177e4 LT |
1397 | /* ADAT is not available on DIGI32 and DIGI32 Pro */ |
1398 | rme32->adat_pcm = NULL; | |
1399 | } | |
1400 | else { | |
1401 | if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1, | |
1402 | 1, 1, &rme32->adat_pcm)) < 0) | |
1403 | { | |
1404 | return err; | |
1405 | } | |
1406 | rme32->adat_pcm->private_data = rme32; | |
1407 | rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm; | |
1408 | strcpy(rme32->adat_pcm->name, "Digi32 ADAT"); | |
1409 | if (rme32->fullduplex_mode) { | |
1410 | snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
1411 | &snd_rme32_playback_adat_fd_ops); | |
1412 | snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, | |
1413 | &snd_rme32_capture_adat_fd_ops); | |
1414 | snd_pcm_lib_preallocate_pages_for_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS, | |
1415 | snd_dma_continuous_data(GFP_KERNEL), | |
1416 | 0, RME32_MID_BUFFER_SIZE); | |
1417 | rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; | |
1418 | } else { | |
1419 | snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
1420 | &snd_rme32_playback_adat_ops); | |
1421 | snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, | |
1422 | &snd_rme32_capture_adat_ops); | |
1423 | rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX; | |
1424 | } | |
1425 | } | |
1426 | ||
1427 | ||
1428 | rme32->playback_periodsize = 0; | |
1429 | rme32->capture_periodsize = 0; | |
1430 | ||
1431 | /* make sure playback/capture is stopped, if by some reason active */ | |
1432 | snd_rme32_pcm_stop(rme32, 0); | |
1433 | ||
1434 | /* reset DAC */ | |
1435 | snd_rme32_reset_dac(rme32); | |
1436 | ||
1437 | /* reset buffer pointer */ | |
1438 | writel(0, rme32->iobase + RME32_IO_RESET_POS); | |
1439 | ||
1440 | /* set default values in registers */ | |
1441 | rme32->wcreg = RME32_WCR_SEL | /* normal playback */ | |
1442 | RME32_WCR_INP_0 | /* input select */ | |
1443 | RME32_WCR_MUTE; /* muting on */ | |
1444 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
1445 | ||
1446 | ||
1447 | /* init switch interface */ | |
1448 | if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) { | |
1449 | return err; | |
1450 | } | |
1451 | ||
1452 | /* init proc interface */ | |
1453 | snd_rme32_proc_init(rme32); | |
1454 | ||
1455 | rme32->capture_substream = NULL; | |
1456 | rme32->playback_substream = NULL; | |
1457 | ||
1458 | return 0; | |
1459 | } | |
1460 | ||
1461 | /* | |
1462 | * proc interface | |
1463 | */ | |
1464 | ||
1465 | static void | |
017ce802 | 1466 | snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer) |
1da177e4 LT |
1467 | { |
1468 | int n; | |
017ce802 | 1469 | struct rme32 *rme32 = (struct rme32 *) entry->private_data; |
1da177e4 LT |
1470 | |
1471 | rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
1472 | ||
1473 | snd_iprintf(buffer, rme32->card->longname); | |
1474 | snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1); | |
1475 | ||
1476 | snd_iprintf(buffer, "\nGeneral settings\n"); | |
1477 | if (rme32->fullduplex_mode) | |
1478 | snd_iprintf(buffer, " Full-duplex mode\n"); | |
1479 | else | |
1480 | snd_iprintf(buffer, " Half-duplex mode\n"); | |
1481 | if (RME32_PRO_WITH_8414(rme32)) { | |
1482 | snd_iprintf(buffer, " receiver: CS8414\n"); | |
1483 | } else { | |
1484 | snd_iprintf(buffer, " receiver: CS8412\n"); | |
1485 | } | |
1486 | if (rme32->wcreg & RME32_WCR_MODE24) { | |
1487 | snd_iprintf(buffer, " format: 24 bit"); | |
1488 | } else { | |
1489 | snd_iprintf(buffer, " format: 16 bit"); | |
1490 | } | |
1491 | if (rme32->wcreg & RME32_WCR_MONO) { | |
1492 | snd_iprintf(buffer, ", Mono\n"); | |
1493 | } else { | |
1494 | snd_iprintf(buffer, ", Stereo\n"); | |
1495 | } | |
1496 | ||
1497 | snd_iprintf(buffer, "\nInput settings\n"); | |
1498 | switch (snd_rme32_getinputtype(rme32)) { | |
1499 | case RME32_INPUT_OPTICAL: | |
1500 | snd_iprintf(buffer, " input: optical"); | |
1501 | break; | |
1502 | case RME32_INPUT_COAXIAL: | |
1503 | snd_iprintf(buffer, " input: coaxial"); | |
1504 | break; | |
1505 | case RME32_INPUT_INTERNAL: | |
1506 | snd_iprintf(buffer, " input: internal"); | |
1507 | break; | |
1508 | case RME32_INPUT_XLR: | |
1509 | snd_iprintf(buffer, " input: XLR"); | |
1510 | break; | |
1511 | } | |
1512 | if (snd_rme32_capture_getrate(rme32, &n) < 0) { | |
1513 | snd_iprintf(buffer, "\n sample rate: no valid signal\n"); | |
1514 | } else { | |
1515 | if (n) { | |
1516 | snd_iprintf(buffer, " (8 channels)\n"); | |
1517 | } else { | |
1518 | snd_iprintf(buffer, " (2 channels)\n"); | |
1519 | } | |
1520 | snd_iprintf(buffer, " sample rate: %d Hz\n", | |
1521 | snd_rme32_capture_getrate(rme32, &n)); | |
1522 | } | |
1523 | ||
1524 | snd_iprintf(buffer, "\nOutput settings\n"); | |
1525 | if (rme32->wcreg & RME32_WCR_SEL) { | |
1526 | snd_iprintf(buffer, " output signal: normal playback"); | |
1527 | } else { | |
1528 | snd_iprintf(buffer, " output signal: same as input"); | |
1529 | } | |
1530 | if (rme32->wcreg & RME32_WCR_MUTE) { | |
1531 | snd_iprintf(buffer, " (muted)\n"); | |
1532 | } else { | |
1533 | snd_iprintf(buffer, "\n"); | |
1534 | } | |
1535 | ||
1536 | /* master output frequency */ | |
1537 | if (! | |
1538 | ((!(rme32->wcreg & RME32_WCR_FREQ_0)) | |
1539 | && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) { | |
1540 | snd_iprintf(buffer, " sample rate: %d Hz\n", | |
1541 | snd_rme32_playback_getrate(rme32)); | |
1542 | } | |
1543 | if (rme32->rcreg & RME32_RCR_KMODE) { | |
1544 | snd_iprintf(buffer, " sample clock source: AutoSync\n"); | |
1545 | } else { | |
1546 | snd_iprintf(buffer, " sample clock source: Internal\n"); | |
1547 | } | |
1548 | if (rme32->wcreg & RME32_WCR_PRO) { | |
1549 | snd_iprintf(buffer, " format: AES/EBU (professional)\n"); | |
1550 | } else { | |
1551 | snd_iprintf(buffer, " format: IEC958 (consumer)\n"); | |
1552 | } | |
1553 | if (rme32->wcreg & RME32_WCR_EMP) { | |
1554 | snd_iprintf(buffer, " emphasis: on\n"); | |
1555 | } else { | |
1556 | snd_iprintf(buffer, " emphasis: off\n"); | |
1557 | } | |
1558 | } | |
1559 | ||
017ce802 | 1560 | static void __devinit snd_rme32_proc_init(struct rme32 * rme32) |
1da177e4 | 1561 | { |
017ce802 | 1562 | struct snd_info_entry *entry; |
1da177e4 LT |
1563 | |
1564 | if (! snd_card_proc_new(rme32->card, "rme32", &entry)) | |
bf850204 | 1565 | snd_info_set_text_ops(entry, rme32, snd_rme32_proc_read); |
1da177e4 LT |
1566 | } |
1567 | ||
1568 | /* | |
1569 | * control interface | |
1570 | */ | |
1571 | ||
a5ce8890 TI |
1572 | #define snd_rme32_info_loopback_control snd_ctl_boolean_mono_info |
1573 | ||
1da177e4 | 1574 | static int |
017ce802 TI |
1575 | snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol, |
1576 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1577 | { |
017ce802 | 1578 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1579 | |
1580 | spin_lock_irq(&rme32->lock); | |
1581 | ucontrol->value.integer.value[0] = | |
1582 | rme32->wcreg & RME32_WCR_SEL ? 0 : 1; | |
1583 | spin_unlock_irq(&rme32->lock); | |
1584 | return 0; | |
1585 | } | |
1586 | static int | |
017ce802 TI |
1587 | snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol, |
1588 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1589 | { |
017ce802 | 1590 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1591 | unsigned int val; |
1592 | int change; | |
1593 | ||
1594 | val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL; | |
1595 | spin_lock_irq(&rme32->lock); | |
1596 | val = (rme32->wcreg & ~RME32_WCR_SEL) | val; | |
1597 | change = val != rme32->wcreg; | |
1598 | if (ucontrol->value.integer.value[0]) | |
1599 | val &= ~RME32_WCR_MUTE; | |
1600 | else | |
1601 | val |= RME32_WCR_MUTE; | |
1602 | rme32->wcreg = val; | |
1603 | writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
1604 | spin_unlock_irq(&rme32->lock); | |
1605 | return change; | |
1606 | } | |
1607 | ||
1608 | static int | |
017ce802 TI |
1609 | snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol, |
1610 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 | 1611 | { |
017ce802 | 1612 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1613 | static char *texts[4] = { "Optical", "Coaxial", "Internal", "XLR" }; |
1614 | ||
1615 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1616 | uinfo->count = 1; | |
1617 | switch (rme32->pci->device) { | |
8b7fc421 RD |
1618 | case PCI_DEVICE_ID_RME_DIGI32: |
1619 | case PCI_DEVICE_ID_RME_DIGI32_8: | |
1da177e4 LT |
1620 | uinfo->value.enumerated.items = 3; |
1621 | break; | |
8b7fc421 | 1622 | case PCI_DEVICE_ID_RME_DIGI32_PRO: |
1da177e4 LT |
1623 | uinfo->value.enumerated.items = 4; |
1624 | break; | |
1625 | default: | |
1626 | snd_BUG(); | |
1627 | break; | |
1628 | } | |
1629 | if (uinfo->value.enumerated.item > | |
1630 | uinfo->value.enumerated.items - 1) { | |
1631 | uinfo->value.enumerated.item = | |
1632 | uinfo->value.enumerated.items - 1; | |
1633 | } | |
1634 | strcpy(uinfo->value.enumerated.name, | |
1635 | texts[uinfo->value.enumerated.item]); | |
1636 | return 0; | |
1637 | } | |
1638 | static int | |
017ce802 TI |
1639 | snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol, |
1640 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1641 | { |
017ce802 | 1642 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1643 | unsigned int items = 3; |
1644 | ||
1645 | spin_lock_irq(&rme32->lock); | |
1646 | ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32); | |
1647 | ||
1648 | switch (rme32->pci->device) { | |
8b7fc421 RD |
1649 | case PCI_DEVICE_ID_RME_DIGI32: |
1650 | case PCI_DEVICE_ID_RME_DIGI32_8: | |
1da177e4 LT |
1651 | items = 3; |
1652 | break; | |
8b7fc421 | 1653 | case PCI_DEVICE_ID_RME_DIGI32_PRO: |
1da177e4 LT |
1654 | items = 4; |
1655 | break; | |
1656 | default: | |
1657 | snd_BUG(); | |
1658 | break; | |
1659 | } | |
1660 | if (ucontrol->value.enumerated.item[0] >= items) { | |
1661 | ucontrol->value.enumerated.item[0] = items - 1; | |
1662 | } | |
1663 | ||
1664 | spin_unlock_irq(&rme32->lock); | |
1665 | return 0; | |
1666 | } | |
1667 | static int | |
017ce802 TI |
1668 | snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol, |
1669 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1670 | { |
017ce802 | 1671 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1672 | unsigned int val; |
1673 | int change, items = 3; | |
1674 | ||
1675 | switch (rme32->pci->device) { | |
8b7fc421 RD |
1676 | case PCI_DEVICE_ID_RME_DIGI32: |
1677 | case PCI_DEVICE_ID_RME_DIGI32_8: | |
1da177e4 LT |
1678 | items = 3; |
1679 | break; | |
8b7fc421 | 1680 | case PCI_DEVICE_ID_RME_DIGI32_PRO: |
1da177e4 LT |
1681 | items = 4; |
1682 | break; | |
1683 | default: | |
1684 | snd_BUG(); | |
1685 | break; | |
1686 | } | |
1687 | val = ucontrol->value.enumerated.item[0] % items; | |
1688 | ||
1689 | spin_lock_irq(&rme32->lock); | |
1690 | change = val != (unsigned int)snd_rme32_getinputtype(rme32); | |
1691 | snd_rme32_setinputtype(rme32, val); | |
1692 | spin_unlock_irq(&rme32->lock); | |
1693 | return change; | |
1694 | } | |
1695 | ||
1696 | static int | |
017ce802 TI |
1697 | snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol, |
1698 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1699 | { |
1700 | static char *texts[4] = { "AutoSync", | |
1701 | "Internal 32.0kHz", | |
1702 | "Internal 44.1kHz", | |
1703 | "Internal 48.0kHz" }; | |
1704 | ||
1705 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1706 | uinfo->count = 1; | |
1707 | uinfo->value.enumerated.items = 4; | |
1708 | if (uinfo->value.enumerated.item > 3) { | |
1709 | uinfo->value.enumerated.item = 3; | |
1710 | } | |
1711 | strcpy(uinfo->value.enumerated.name, | |
1712 | texts[uinfo->value.enumerated.item]); | |
1713 | return 0; | |
1714 | } | |
1715 | static int | |
017ce802 TI |
1716 | snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol, |
1717 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1718 | { |
017ce802 | 1719 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1720 | |
1721 | spin_lock_irq(&rme32->lock); | |
1722 | ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32); | |
1723 | spin_unlock_irq(&rme32->lock); | |
1724 | return 0; | |
1725 | } | |
1726 | static int | |
017ce802 TI |
1727 | snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol, |
1728 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1729 | { |
017ce802 | 1730 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1731 | unsigned int val; |
1732 | int change; | |
1733 | ||
1734 | val = ucontrol->value.enumerated.item[0] % 3; | |
1735 | spin_lock_irq(&rme32->lock); | |
1736 | change = val != (unsigned int)snd_rme32_getclockmode(rme32); | |
1737 | snd_rme32_setclockmode(rme32, val); | |
1738 | spin_unlock_irq(&rme32->lock); | |
1739 | return change; | |
1740 | } | |
1741 | ||
017ce802 | 1742 | static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes) |
1da177e4 LT |
1743 | { |
1744 | u32 val = 0; | |
1745 | val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0; | |
1746 | if (val & RME32_WCR_PRO) | |
1747 | val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0; | |
1748 | else | |
1749 | val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0; | |
1750 | return val; | |
1751 | } | |
1752 | ||
017ce802 | 1753 | static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val) |
1da177e4 LT |
1754 | { |
1755 | aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0); | |
1756 | if (val & RME32_WCR_PRO) | |
1757 | aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; | |
1758 | else | |
1759 | aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; | |
1760 | } | |
1761 | ||
017ce802 TI |
1762 | static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol, |
1763 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1764 | { |
1765 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1766 | uinfo->count = 1; | |
1767 | return 0; | |
1768 | } | |
1769 | ||
017ce802 TI |
1770 | static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol, |
1771 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1772 | { |
017ce802 | 1773 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1774 | |
1775 | snd_rme32_convert_to_aes(&ucontrol->value.iec958, | |
1776 | rme32->wcreg_spdif); | |
1777 | return 0; | |
1778 | } | |
1779 | ||
017ce802 TI |
1780 | static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol, |
1781 | struct snd_ctl_elem_value *ucontrol) | |
1da177e4 | 1782 | { |
017ce802 | 1783 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1784 | int change; |
1785 | u32 val; | |
1786 | ||
1787 | val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); | |
1788 | spin_lock_irq(&rme32->lock); | |
1789 | change = val != rme32->wcreg_spdif; | |
1790 | rme32->wcreg_spdif = val; | |
1791 | spin_unlock_irq(&rme32->lock); | |
1792 | return change; | |
1793 | } | |
1794 | ||
017ce802 TI |
1795 | static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol, |
1796 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1797 | { |
1798 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1799 | uinfo->count = 1; | |
1800 | return 0; | |
1801 | } | |
1802 | ||
017ce802 TI |
1803 | static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol, |
1804 | struct snd_ctl_elem_value * | |
1da177e4 LT |
1805 | ucontrol) |
1806 | { | |
017ce802 | 1807 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1808 | |
1809 | snd_rme32_convert_to_aes(&ucontrol->value.iec958, | |
1810 | rme32->wcreg_spdif_stream); | |
1811 | return 0; | |
1812 | } | |
1813 | ||
017ce802 TI |
1814 | static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol, |
1815 | struct snd_ctl_elem_value * | |
1da177e4 LT |
1816 | ucontrol) |
1817 | { | |
017ce802 | 1818 | struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1819 | int change; |
1820 | u32 val; | |
1821 | ||
1822 | val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); | |
1823 | spin_lock_irq(&rme32->lock); | |
1824 | change = val != rme32->wcreg_spdif_stream; | |
1825 | rme32->wcreg_spdif_stream = val; | |
1826 | rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); | |
1827 | rme32->wcreg |= val; | |
1828 | writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); | |
1829 | spin_unlock_irq(&rme32->lock); | |
1830 | return change; | |
1831 | } | |
1832 | ||
017ce802 TI |
1833 | static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol, |
1834 | struct snd_ctl_elem_info *uinfo) | |
1da177e4 LT |
1835 | { |
1836 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
1837 | uinfo->count = 1; | |
1838 | return 0; | |
1839 | } | |
1840 | ||
017ce802 TI |
1841 | static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol, |
1842 | struct snd_ctl_elem_value * | |
1da177e4 LT |
1843 | ucontrol) |
1844 | { | |
1845 | ucontrol->value.iec958.status[0] = kcontrol->private_value; | |
1846 | return 0; | |
1847 | } | |
1848 | ||
017ce802 | 1849 | static struct snd_kcontrol_new snd_rme32_controls[] = { |
1da177e4 LT |
1850 | { |
1851 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1852 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), | |
1853 | .info = snd_rme32_control_spdif_info, | |
1854 | .get = snd_rme32_control_spdif_get, | |
1855 | .put = snd_rme32_control_spdif_put | |
1856 | }, | |
1857 | { | |
1858 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, | |
1859 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
1860 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM), | |
1861 | .info = snd_rme32_control_spdif_stream_info, | |
1862 | .get = snd_rme32_control_spdif_stream_get, | |
1863 | .put = snd_rme32_control_spdif_stream_put | |
1864 | }, | |
1865 | { | |
1866 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
67ed4161 | 1867 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
1868 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), |
1869 | .info = snd_rme32_control_spdif_mask_info, | |
1870 | .get = snd_rme32_control_spdif_mask_get, | |
1871 | .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS | |
1872 | }, | |
1873 | { | |
1874 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
67ed4161 | 1875 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
1876 | .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK), |
1877 | .info = snd_rme32_control_spdif_mask_info, | |
1878 | .get = snd_rme32_control_spdif_mask_get, | |
1879 | .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS | |
1880 | }, | |
1881 | { | |
1882 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
1883 | .name = "Input Connector", | |
1884 | .info = snd_rme32_info_inputtype_control, | |
1885 | .get = snd_rme32_get_inputtype_control, | |
1886 | .put = snd_rme32_put_inputtype_control | |
1887 | }, | |
1888 | { | |
1889 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
1890 | .name = "Loopback Input", | |
1891 | .info = snd_rme32_info_loopback_control, | |
1892 | .get = snd_rme32_get_loopback_control, | |
1893 | .put = snd_rme32_put_loopback_control | |
1894 | }, | |
1895 | { | |
1896 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
1897 | .name = "Sample Clock Source", | |
1898 | .info = snd_rme32_info_clockmode_control, | |
1899 | .get = snd_rme32_get_clockmode_control, | |
1900 | .put = snd_rme32_put_clockmode_control | |
1901 | } | |
1902 | }; | |
1903 | ||
017ce802 | 1904 | static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32) |
1da177e4 LT |
1905 | { |
1906 | int idx, err; | |
017ce802 | 1907 | struct snd_kcontrol *kctl; |
1da177e4 LT |
1908 | |
1909 | for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) { | |
1910 | if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0) | |
1911 | return err; | |
1912 | if (idx == 1) /* IEC958 (S/PDIF) Stream */ | |
1913 | rme32->spdif_ctl = kctl; | |
1914 | } | |
1915 | ||
1916 | return 0; | |
1917 | } | |
1918 | ||
1919 | /* | |
1920 | * Card initialisation | |
1921 | */ | |
1922 | ||
017ce802 | 1923 | static void snd_rme32_card_free(struct snd_card *card) |
1da177e4 LT |
1924 | { |
1925 | snd_rme32_free(card->private_data); | |
1926 | } | |
1927 | ||
1928 | static int __devinit | |
1929 | snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) | |
1930 | { | |
1931 | static int dev; | |
017ce802 TI |
1932 | struct rme32 *rme32; |
1933 | struct snd_card *card; | |
1da177e4 LT |
1934 | int err; |
1935 | ||
1936 | if (dev >= SNDRV_CARDS) { | |
1937 | return -ENODEV; | |
1938 | } | |
1939 | if (!enable[dev]) { | |
1940 | dev++; | |
1941 | return -ENOENT; | |
1942 | } | |
1943 | ||
1944 | if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE, | |
017ce802 | 1945 | sizeof(struct rme32))) == NULL) |
1da177e4 LT |
1946 | return -ENOMEM; |
1947 | card->private_free = snd_rme32_card_free; | |
017ce802 | 1948 | rme32 = (struct rme32 *) card->private_data; |
1da177e4 LT |
1949 | rme32->card = card; |
1950 | rme32->pci = pci; | |
1951 | snd_card_set_dev(card, &pci->dev); | |
1952 | if (fullduplex[dev]) | |
1953 | rme32->fullduplex_mode = 1; | |
1954 | if ((err = snd_rme32_create(rme32)) < 0) { | |
1955 | snd_card_free(card); | |
1956 | return err; | |
1957 | } | |
1958 | ||
1959 | strcpy(card->driver, "Digi32"); | |
1960 | switch (rme32->pci->device) { | |
8b7fc421 | 1961 | case PCI_DEVICE_ID_RME_DIGI32: |
1da177e4 LT |
1962 | strcpy(card->shortname, "RME Digi32"); |
1963 | break; | |
8b7fc421 | 1964 | case PCI_DEVICE_ID_RME_DIGI32_8: |
1da177e4 LT |
1965 | strcpy(card->shortname, "RME Digi32/8"); |
1966 | break; | |
8b7fc421 | 1967 | case PCI_DEVICE_ID_RME_DIGI32_PRO: |
1da177e4 LT |
1968 | strcpy(card->shortname, "RME Digi32 PRO"); |
1969 | break; | |
1970 | } | |
1971 | sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d", | |
1972 | card->shortname, rme32->rev, rme32->port, rme32->irq); | |
1973 | ||
1974 | if ((err = snd_card_register(card)) < 0) { | |
1975 | snd_card_free(card); | |
1976 | return err; | |
1977 | } | |
1978 | pci_set_drvdata(pci, card); | |
1979 | dev++; | |
1980 | return 0; | |
1981 | } | |
1982 | ||
1983 | static void __devexit snd_rme32_remove(struct pci_dev *pci) | |
1984 | { | |
1985 | snd_card_free(pci_get_drvdata(pci)); | |
1986 | pci_set_drvdata(pci, NULL); | |
1987 | } | |
1988 | ||
1989 | static struct pci_driver driver = { | |
1990 | .name = "RME Digi32", | |
1991 | .id_table = snd_rme32_ids, | |
1992 | .probe = snd_rme32_probe, | |
1993 | .remove = __devexit_p(snd_rme32_remove), | |
1994 | }; | |
1995 | ||
1996 | static int __init alsa_card_rme32_init(void) | |
1997 | { | |
01d25d46 | 1998 | return pci_register_driver(&driver); |
1da177e4 LT |
1999 | } |
2000 | ||
2001 | static void __exit alsa_card_rme32_exit(void) | |
2002 | { | |
2003 | pci_unregister_driver(&driver); | |
2004 | } | |
2005 | ||
2006 | module_init(alsa_card_rme32_init) | |
2007 | module_exit(alsa_card_rme32_exit) |