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Merge branch 'efi-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-eoan-kernel.git] / sound / pci / rme96.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
3 * interfaces
4 *
5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
6 *
7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
8 * code.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
1da177e4
LT		 26#include <linux/delay.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/pci.h>
65a77217 30#include <linux/module.h>
a8cc2099 31#include <linux/vmalloc.h>
6cbbfe1c 32#include <linux/io.h>
1da177e4
LT		 33
34#include <sound/core.h>
35#include <sound/info.h>
36#include <sound/control.h>
37#include <sound/pcm.h>
38#include <sound/pcm_params.h>
39#include <sound/asoundef.h>
40#include <sound/initval.h>
41
1da177e4
LT		 42/* note, two last pcis should be equal, it is not a bug */
43
44MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
45MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
46 "Digi96/8 PAD");
47MODULE_LICENSE("GPL");
48MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
49 "{RME,Digi96/8},"
50 "{RME,Digi96/8 PRO},"
51 "{RME,Digi96/8 PST},"
52 "{RME,Digi96/8 PAD}}");
53
54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
a67ff6a5 56static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
1da177e4
LT		 57
58module_param_array(index, int, NULL, 0444);
59MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
60module_param_array(id, charp, NULL, 0444);
61MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
62module_param_array(enable, bool, NULL, 0444);
63MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
64
65/*
66 * Defines for RME Digi96 series, from internal RME reference documents
67 * dated 12.01.00
68 */
69
70#define RME96_SPDIF_NCHANNELS 2
71
72/* Playback and capture buffer size */
73#define RME96_BUFFER_SIZE 0x10000
74
75/* IO area size */
76#define RME96_IO_SIZE 0x60000
77
78/* IO area offsets */
79#define RME96_IO_PLAY_BUFFER 0x0
80#define RME96_IO_REC_BUFFER 0x10000
81#define RME96_IO_CONTROL_REGISTER 0x20000
82#define RME96_IO_ADDITIONAL_REG 0x20004
83#define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
84#define RME96_IO_CONFIRM_REC_IRQ 0x2000C
85#define RME96_IO_SET_PLAY_POS 0x40000
86#define RME96_IO_RESET_PLAY_POS 0x4FFFC
87#define RME96_IO_SET_REC_POS 0x50000
88#define RME96_IO_RESET_REC_POS 0x5FFFC
89#define RME96_IO_GET_PLAY_POS 0x20000
90#define RME96_IO_GET_REC_POS 0x30000
91
92/* Write control register bits */
93#define RME96_WCR_START (1 << 0)
94#define RME96_WCR_START_2 (1 << 1)
95#define RME96_WCR_GAIN_0 (1 << 2)
96#define RME96_WCR_GAIN_1 (1 << 3)
97#define RME96_WCR_MODE24 (1 << 4)
98#define RME96_WCR_MODE24_2 (1 << 5)
99#define RME96_WCR_BM (1 << 6)
100#define RME96_WCR_BM_2 (1 << 7)
101#define RME96_WCR_ADAT (1 << 8)
102#define RME96_WCR_FREQ_0 (1 << 9)
103#define RME96_WCR_FREQ_1 (1 << 10)
104#define RME96_WCR_DS (1 << 11)
105#define RME96_WCR_PRO (1 << 12)
106#define RME96_WCR_EMP (1 << 13)
107#define RME96_WCR_SEL (1 << 14)
108#define RME96_WCR_MASTER (1 << 15)
109#define RME96_WCR_PD (1 << 16)
110#define RME96_WCR_INP_0 (1 << 17)
111#define RME96_WCR_INP_1 (1 << 18)
112#define RME96_WCR_THRU_0 (1 << 19)
113#define RME96_WCR_THRU_1 (1 << 20)
114#define RME96_WCR_THRU_2 (1 << 21)
115#define RME96_WCR_THRU_3 (1 << 22)
116#define RME96_WCR_THRU_4 (1 << 23)
117#define RME96_WCR_THRU_5 (1 << 24)
118#define RME96_WCR_THRU_6 (1 << 25)
119#define RME96_WCR_THRU_7 (1 << 26)
120#define RME96_WCR_DOLBY (1 << 27)
121#define RME96_WCR_MONITOR_0 (1 << 28)
122#define RME96_WCR_MONITOR_1 (1 << 29)
123#define RME96_WCR_ISEL (1 << 30)
124#define RME96_WCR_IDIS (1 << 31)
125
126#define RME96_WCR_BITPOS_GAIN_0 2
127#define RME96_WCR_BITPOS_GAIN_1 3
128#define RME96_WCR_BITPOS_FREQ_0 9
129#define RME96_WCR_BITPOS_FREQ_1 10
130#define RME96_WCR_BITPOS_INP_0 17
131#define RME96_WCR_BITPOS_INP_1 18
132#define RME96_WCR_BITPOS_MONITOR_0 28
133#define RME96_WCR_BITPOS_MONITOR_1 29
134
135/* Read control register bits */
136#define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
137#define RME96_RCR_IRQ_2 (1 << 16)
138#define RME96_RCR_T_OUT (1 << 17)
139#define RME96_RCR_DEV_ID_0 (1 << 21)
140#define RME96_RCR_DEV_ID_1 (1 << 22)
141#define RME96_RCR_LOCK (1 << 23)
142#define RME96_RCR_VERF (1 << 26)
143#define RME96_RCR_F0 (1 << 27)
144#define RME96_RCR_F1 (1 << 28)
145#define RME96_RCR_F2 (1 << 29)
146#define RME96_RCR_AUTOSYNC (1 << 30)
147#define RME96_RCR_IRQ (1 << 31)
148
149#define RME96_RCR_BITPOS_F0 27
150#define RME96_RCR_BITPOS_F1 28
151#define RME96_RCR_BITPOS_F2 29
152
25985edc 153/* Additional register bits */
1da177e4
LT		 154#define RME96_AR_WSEL (1 << 0)
155#define RME96_AR_ANALOG (1 << 1)
156#define RME96_AR_FREQPAD_0 (1 << 2)
157#define RME96_AR_FREQPAD_1 (1 << 3)
158#define RME96_AR_FREQPAD_2 (1 << 4)
159#define RME96_AR_PD2 (1 << 5)
160#define RME96_AR_DAC_EN (1 << 6)
161#define RME96_AR_CLATCH (1 << 7)
162#define RME96_AR_CCLK (1 << 8)
163#define RME96_AR_CDATA (1 << 9)
164
165#define RME96_AR_BITPOS_F0 2
166#define RME96_AR_BITPOS_F1 3
167#define RME96_AR_BITPOS_F2 4
168
169/* Monitor tracks */
170#define RME96_MONITOR_TRACKS_1_2 0
171#define RME96_MONITOR_TRACKS_3_4 1
172#define RME96_MONITOR_TRACKS_5_6 2
173#define RME96_MONITOR_TRACKS_7_8 3
174
175/* Attenuation */
176#define RME96_ATTENUATION_0 0
177#define RME96_ATTENUATION_6 1
178#define RME96_ATTENUATION_12 2
179#define RME96_ATTENUATION_18 3
180
181/* Input types */
182#define RME96_INPUT_OPTICAL 0
183#define RME96_INPUT_COAXIAL 1
184#define RME96_INPUT_INTERNAL 2
185#define RME96_INPUT_XLR 3
186#define RME96_INPUT_ANALOG 4
187
188/* Clock modes */
189#define RME96_CLOCKMODE_SLAVE 0
190#define RME96_CLOCKMODE_MASTER 1
191#define RME96_CLOCKMODE_WORDCLOCK 2
192
193/* Block sizes in bytes */
194#define RME96_SMALL_BLOCK_SIZE 2048
195#define RME96_LARGE_BLOCK_SIZE 8192
196
197/* Volume control */
198#define RME96_AD1852_VOL_BITS 14
199#define RME96_AD1855_VOL_BITS 10
200
b892ca1c
KP		 201/* Defines for snd_rme96_trigger */
202#define RME96_TB_START_PLAYBACK 1
203#define RME96_TB_START_CAPTURE 2
204#define RME96_TB_STOP_PLAYBACK 4
205#define RME96_TB_STOP_CAPTURE 8
206#define RME96_TB_RESET_PLAYPOS 16
207#define RME96_TB_RESET_CAPTUREPOS 32
208#define RME96_TB_CLEAR_PLAYBACK_IRQ 64
209#define RME96_TB_CLEAR_CAPTURE_IRQ 128
210#define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK)
211#define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE)
212#define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \
213 | RME96_RESUME_CAPTURE)
214#define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \
215 | RME96_TB_RESET_PLAYPOS)
216#define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \
217 | RME96_TB_RESET_CAPTUREPOS)
218#define RME96_START_BOTH (RME96_START_PLAYBACK \
219 | RME96_START_CAPTURE)
220#define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \
221 | RME96_TB_CLEAR_PLAYBACK_IRQ)
222#define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \
223 | RME96_TB_CLEAR_CAPTURE_IRQ)
224#define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \
225 | RME96_STOP_CAPTURE)
1da177e4 226
a3aefd88 227struct rme96 {
1da177e4
LT		 228 spinlock_t lock;
229 int irq;
230 unsigned long port;
231 void __iomem *iobase;
232
233 u32 wcreg; /* cached write control register value */
234 u32 wcreg_spdif; /* S/PDIF setup */
235 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
236 u32 rcreg; /* cached read control register value */
237 u32 areg; /* cached additional register value */
238 u16 vol[2]; /* cached volume of analog output */
239
240 u8 rev; /* card revision number */
241
a932be91 242#ifdef CONFIG_PM_SLEEP
528ba522
KP		 243 u32 playback_pointer;
244 u32 capture_pointer;
245 void *playback_suspend_buffer;
246 void *capture_suspend_buffer;
247#endif
248
a3aefd88
TI		 249 struct snd_pcm_substream *playback_substream;
250 struct snd_pcm_substream *capture_substream;
1da177e4
LT		 251
252 int playback_frlog; /* log2 of framesize */
253 int capture_frlog;
254
255 size_t playback_periodsize; /* in bytes, zero if not used */
256 size_t capture_periodsize; /* in bytes, zero if not used */
257
a3aefd88
TI		 258 struct snd_card *card;
259 struct snd_pcm *spdif_pcm;
260 struct snd_pcm *adat_pcm;
1da177e4 261 struct pci_dev *pci;
a3aefd88
TI		 262 struct snd_kcontrol *spdif_ctl;
263};
1da177e4 264
9baa3c34 265static const struct pci_device_id snd_rme96_ids[] = {
28d27aae
JP		 266 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
267 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
268 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
269 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
1da177e4
LT		 270 { 0, }
271};
272
273MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
274
275#define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
276#define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
8b7fc421
RD		 277#define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
278#define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
279 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
1da177e4 280#define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
8b7fc421
RD		 281#define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
282 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
1da177e4
LT		 283#define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
284
285static int
a3aefd88 286snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
1da177e4
LT		 287
288static int
a3aefd88 289snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
1da177e4
LT		 290
291static int
a3aefd88 292snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 293 int cmd);
294
295static int
a3aefd88 296snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 297 int cmd);
298
299static snd_pcm_uframes_t
a3aefd88 300snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
1da177e4
LT		 301
302static snd_pcm_uframes_t
a3aefd88 303snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
1da177e4 304
e23e7a14 305static void snd_rme96_proc_init(struct rme96 *rme96);
1da177e4
LT		 306
307static int
a3aefd88
TI		 308snd_rme96_create_switches(struct snd_card *card,
309 struct rme96 *rme96);
1da177e4
LT		 310
311static int
a3aefd88 312snd_rme96_getinputtype(struct rme96 *rme96);
1da177e4
LT		 313
314static inline unsigned int
a3aefd88 315snd_rme96_playback_ptr(struct rme96 *rme96)
1da177e4
LT		 316{
317 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
318 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
319}
320
321static inline unsigned int
a3aefd88 322snd_rme96_capture_ptr(struct rme96 *rme96)
1da177e4
LT		 323{
324 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
325 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
326}
327
1da177e4 328static int
a3aefd88 329snd_rme96_playback_silence(struct snd_pcm_substream *substream,
53945f5b 330 int channel, unsigned long pos, unsigned long count)
1da177e4 331{
a3aefd88 332 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
53945f5b 333
1da177e4
LT		 334 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
335 0, count);
336 return 0;
337}
338
339static int
a3aefd88 340snd_rme96_playback_copy(struct snd_pcm_substream *substream,
53945f5b
TI		 341 int channel, unsigned long pos,
342 void __user *src, unsigned long count)
1da177e4 343{
a3aefd88 344 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
53945f5b
TI		 345
346 return copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
347 src, count);
348}
349
350static int
351snd_rme96_playback_copy_kernel(struct snd_pcm_substream *substream,
352 int channel, unsigned long pos,
353 void *src, unsigned long count)
354{
355 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
356
357 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src, count);
358 return 0;
1da177e4
LT		 359}
360
361static int
a3aefd88 362snd_rme96_capture_copy(struct snd_pcm_substream *substream,
53945f5b
TI		 363 int channel, unsigned long pos,
364 void __user *dst, unsigned long count)
1da177e4 365{
a3aefd88 366 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
53945f5b
TI		 367
368 return copy_to_user_fromio(dst,
369 rme96->iobase + RME96_IO_REC_BUFFER + pos,
2026d24e 370 count);
1da177e4
LT		 371}
372
53945f5b
TI		 373static int
374snd_rme96_capture_copy_kernel(struct snd_pcm_substream *substream,
375 int channel, unsigned long pos,
376 void *dst, unsigned long count)
377{
378 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
379
380 memcpy_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos, count);
381 return 0;
382}
383
1da177e4 384/*
7f927fcc 385 * Digital output capabilities (S/PDIF)
1da177e4 386 */
dee49895 387static const struct snd_pcm_hardware snd_rme96_playback_spdif_info =
1da177e4
LT		 388{
389 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
390 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 391 SNDRV_PCM_INFO_SYNC_START |
528ba522 392 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 393 SNDRV_PCM_INFO_INTERLEAVED |
394 SNDRV_PCM_INFO_PAUSE),
395 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
396 SNDRV_PCM_FMTBIT_S32_LE),
397 .rates = (SNDRV_PCM_RATE_32000 |
398 SNDRV_PCM_RATE_44100 |
399 SNDRV_PCM_RATE_48000 |
400 SNDRV_PCM_RATE_64000 |
401 SNDRV_PCM_RATE_88200 |
402 SNDRV_PCM_RATE_96000),
403 .rate_min = 32000,
404 .rate_max = 96000,
405 .channels_min = 2,
406 .channels_max = 2,
407 .buffer_bytes_max = RME96_BUFFER_SIZE,
408 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
409 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
410 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
411 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
412 .fifo_size = 0,
413};
414
415/*
7f927fcc 416 * Digital input capabilities (S/PDIF)
1da177e4 417 */
dee49895 418static const struct snd_pcm_hardware snd_rme96_capture_spdif_info =
1da177e4
LT		 419{
420 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
421 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 422 SNDRV_PCM_INFO_SYNC_START |
528ba522 423 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 424 SNDRV_PCM_INFO_INTERLEAVED |
425 SNDRV_PCM_INFO_PAUSE),
426 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
427 SNDRV_PCM_FMTBIT_S32_LE),
428 .rates = (SNDRV_PCM_RATE_32000 |
429 SNDRV_PCM_RATE_44100 |
430 SNDRV_PCM_RATE_48000 |
431 SNDRV_PCM_RATE_64000 |
432 SNDRV_PCM_RATE_88200 |
433 SNDRV_PCM_RATE_96000),
434 .rate_min = 32000,
435 .rate_max = 96000,
436 .channels_min = 2,
437 .channels_max = 2,
438 .buffer_bytes_max = RME96_BUFFER_SIZE,
439 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
440 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
441 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
442 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
443 .fifo_size = 0,
444};
445
446/*
7f927fcc 447 * Digital output capabilities (ADAT)
1da177e4 448 */
dee49895 449static const struct snd_pcm_hardware snd_rme96_playback_adat_info =
1da177e4
LT		 450{
451 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
452 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 453 SNDRV_PCM_INFO_SYNC_START |
528ba522 454 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 455 SNDRV_PCM_INFO_INTERLEAVED |
456 SNDRV_PCM_INFO_PAUSE),
457 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
458 SNDRV_PCM_FMTBIT_S32_LE),
459 .rates = (SNDRV_PCM_RATE_44100 |
460 SNDRV_PCM_RATE_48000),
461 .rate_min = 44100,
462 .rate_max = 48000,
463 .channels_min = 8,
464 .channels_max = 8,
465 .buffer_bytes_max = RME96_BUFFER_SIZE,
466 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
467 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
468 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
469 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
470 .fifo_size = 0,
471};
472
473/*
7f927fcc 474 * Digital input capabilities (ADAT)
1da177e4 475 */
dee49895 476static const struct snd_pcm_hardware snd_rme96_capture_adat_info =
1da177e4
LT		 477{
478 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
479 SNDRV_PCM_INFO_MMAP_VALID |
b892ca1c 480 SNDRV_PCM_INFO_SYNC_START |
528ba522 481 SNDRV_PCM_INFO_RESUME |
1da177e4
LT		 482 SNDRV_PCM_INFO_INTERLEAVED |
483 SNDRV_PCM_INFO_PAUSE),
484 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
485 SNDRV_PCM_FMTBIT_S32_LE),
486 .rates = (SNDRV_PCM_RATE_44100 |
487 SNDRV_PCM_RATE_48000),
488 .rate_min = 44100,
489 .rate_max = 48000,
490 .channels_min = 8,
491 .channels_max = 8,
492 .buffer_bytes_max = RME96_BUFFER_SIZE,
493 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
494 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
495 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
496 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
497 .fifo_size = 0,
498};
499
500/*
501 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
502 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
503 * on the falling edge of CCLK and be stable on the rising edge. The rising
504 * edge of CLATCH after the last data bit clocks in the whole data word.
505 * A fast processor could probably drive the SPI interface faster than the
506 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
507 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
508 *
509 * NOTE: increased delay from 1 to 10, since there where problems setting
510 * the volume.
511 */
512static void
a3aefd88 513snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
1da177e4
LT		 514{
515 int i;
516
517 for (i = 0; i < 16; i++) {
518 if (val & 0x8000) {
519 rme96->areg |= RME96_AR_CDATA;
520 } else {
521 rme96->areg &= ~RME96_AR_CDATA;
522 }
523 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
524 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
525 udelay(10);
526 rme96->areg |= RME96_AR_CCLK;
527 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
528 udelay(10);
529 val <<= 1;
530 }
531 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
532 rme96->areg |= RME96_AR_CLATCH;
533 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
534 udelay(10);
535 rme96->areg &= ~RME96_AR_CLATCH;
536 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
537}
538
539static void
a3aefd88 540snd_rme96_apply_dac_volume(struct rme96 *rme96)
1da177e4
LT		 541{
542 if (RME96_DAC_IS_1852(rme96)) {
543 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
544 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
545 } else if (RME96_DAC_IS_1855(rme96)) {
546 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
547 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
548 }
549}
550
551static void
a3aefd88 552snd_rme96_reset_dac(struct rme96 *rme96)
1da177e4
LT		 553{
554 writel(rme96->wcreg | RME96_WCR_PD,
555 rme96->iobase + RME96_IO_CONTROL_REGISTER);
556 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
557}
558
559static int
a3aefd88 560snd_rme96_getmontracks(struct rme96 *rme96)
1da177e4
LT		 561{
562 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
563 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
564}
565
566static int
a3aefd88 567snd_rme96_setmontracks(struct rme96 *rme96,
1da177e4
LT		 568 int montracks)
569{
570 if (montracks & 1) {
571 rme96->wcreg |= RME96_WCR_MONITOR_0;
572 } else {
573 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
574 }
575 if (montracks & 2) {
576 rme96->wcreg |= RME96_WCR_MONITOR_1;
577 } else {
578 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
579 }
580 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
581 return 0;
582}
583
584static int
a3aefd88 585snd_rme96_getattenuation(struct rme96 *rme96)
1da177e4
LT		 586{
587 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
588 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
589}
590
591static int
a3aefd88 592snd_rme96_setattenuation(struct rme96 *rme96,
1da177e4
LT		 593 int attenuation)
594{
595 switch (attenuation) {
596 case 0:
597 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
598 ~RME96_WCR_GAIN_1;
599 break;
600 case 1:
601 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
602 ~RME96_WCR_GAIN_1;
603 break;
604 case 2:
605 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
606 RME96_WCR_GAIN_1;
607 break;
608 case 3:
609 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
610 RME96_WCR_GAIN_1;
611 break;
612 default:
613 return -EINVAL;
614 }
615 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
616 return 0;
617}
618
619static int
a3aefd88 620snd_rme96_capture_getrate(struct rme96 *rme96,
1da177e4
LT		 621 int *is_adat)
622{
623 int n, rate;
624
625 *is_adat = 0;
626 if (rme96->areg & RME96_AR_ANALOG) {
627 /* Analog input, overrides S/PDIF setting */
628 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
629 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
630 switch (n) {
631 case 1:
632 rate = 32000;
633 break;
634 case 2:
635 rate = 44100;
636 break;
637 case 3:
638 rate = 48000;
639 break;
640 default:
641 return -1;
642 }
643 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
644 }
645
646 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
647 if (rme96->rcreg & RME96_RCR_LOCK) {
648 /* ADAT rate */
649 *is_adat = 1;
650 if (rme96->rcreg & RME96_RCR_T_OUT) {
651 return 48000;
652 }
653 return 44100;
654 }
655
656 if (rme96->rcreg & RME96_RCR_VERF) {
657 return -1;
658 }
659
660 /* S/PDIF rate */
661 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
662 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
663 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
664
665 switch (n) {
666 case 0:
667 if (rme96->rcreg & RME96_RCR_T_OUT) {
668 return 64000;
669 }
670 return -1;
671 case 3: return 96000;
672 case 4: return 88200;
673 case 5: return 48000;
674 case 6: return 44100;
675 case 7: return 32000;
676 default:
677 break;
678 }
679 return -1;
680}
681
682static int
a3aefd88 683snd_rme96_playback_getrate(struct rme96 *rme96)
1da177e4
LT		 684{
685 int rate, dummy;
686
687 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
688 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
689 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
690 {
691 /* slave clock */
692 return rate;
693 }
694 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
695 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
696 switch (rate) {
697 case 1:
698 rate = 32000;
699 break;
700 case 2:
701 rate = 44100;
702 break;
703 case 3:
704 rate = 48000;
705 break;
706 default:
707 return -1;
708 }
709 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
710}
711
712static int
a3aefd88 713snd_rme96_playback_setrate(struct rme96 *rme96,
1da177e4
LT		 714 int rate)
715{
716 int ds;
717
718 ds = rme96->wcreg & RME96_WCR_DS;
719 switch (rate) {
720 case 32000:
721 rme96->wcreg &= ~RME96_WCR_DS;
722 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
723 ~RME96_WCR_FREQ_1;
724 break;
725 case 44100:
726 rme96->wcreg &= ~RME96_WCR_DS;
727 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
728 ~RME96_WCR_FREQ_0;
729 break;
730 case 48000:
731 rme96->wcreg &= ~RME96_WCR_DS;
732 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
733 RME96_WCR_FREQ_1;
734 break;
735 case 64000:
736 rme96->wcreg |= RME96_WCR_DS;
737 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
738 ~RME96_WCR_FREQ_1;
739 break;
740 case 88200:
741 rme96->wcreg |= RME96_WCR_DS;
742 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
743 ~RME96_WCR_FREQ_0;
744 break;
745 case 96000:
746 rme96->wcreg |= RME96_WCR_DS;
747 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
748 RME96_WCR_FREQ_1;
749 break;
750 default:
751 return -EINVAL;
752 }
753 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
754 (ds && !(rme96->wcreg & RME96_WCR_DS)))
755 {
756 /* change to/from double-speed: reset the DAC (if available) */
757 snd_rme96_reset_dac(rme96);
a74a8216 758 return 1; /* need to restore volume */
1da177e4
LT		 759 } else {
760 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
a74a8216 761 return 0;
1da177e4 762 }
1da177e4
LT		 763}
764
765static int
a3aefd88 766snd_rme96_capture_analog_setrate(struct rme96 *rme96,
1da177e4
LT		 767 int rate)
768{
769 switch (rate) {
770 case 32000:
771 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
772 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
773 break;
774 case 44100:
775 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
776 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
777 break;
778 case 48000:
779 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
780 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
781 break;
782 case 64000:
783 if (rme96->rev < 4) {
784 return -EINVAL;
785 }
786 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
787 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
788 break;
789 case 88200:
790 if (rme96->rev < 4) {
791 return -EINVAL;
792 }
793 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
794 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
795 break;
796 case 96000:
797 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
798 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
799 break;
800 default:
801 return -EINVAL;
802 }
803 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
804 return 0;
805}
806
807static int
a3aefd88 808snd_rme96_setclockmode(struct rme96 *rme96,
1da177e4
LT		 809 int mode)
810{
811 switch (mode) {
812 case RME96_CLOCKMODE_SLAVE:
813 /* AutoSync */
814 rme96->wcreg &= ~RME96_WCR_MASTER;
815 rme96->areg &= ~RME96_AR_WSEL;
816 break;
817 case RME96_CLOCKMODE_MASTER:
818 /* Internal */
819 rme96->wcreg |= RME96_WCR_MASTER;
820 rme96->areg &= ~RME96_AR_WSEL;
821 break;
822 case RME96_CLOCKMODE_WORDCLOCK:
823 /* Word clock is a master mode */
824 rme96->wcreg |= RME96_WCR_MASTER;
825 rme96->areg |= RME96_AR_WSEL;
826 break;
827 default:
828 return -EINVAL;
829 }
830 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
831 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
832 return 0;
833}
834
835static int
a3aefd88 836snd_rme96_getclockmode(struct rme96 *rme96)
1da177e4
LT		 837{
838 if (rme96->areg & RME96_AR_WSEL) {
839 return RME96_CLOCKMODE_WORDCLOCK;
840 }
841 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
842 RME96_CLOCKMODE_SLAVE;
843}
844
845static int
a3aefd88 846snd_rme96_setinputtype(struct rme96 *rme96,
1da177e4
LT		 847 int type)
848{
849 int n;
850
851 switch (type) {
852 case RME96_INPUT_OPTICAL:
853 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
854 ~RME96_WCR_INP_1;
855 break;
856 case RME96_INPUT_COAXIAL:
857 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
858 ~RME96_WCR_INP_1;
859 break;
860 case RME96_INPUT_INTERNAL:
861 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
862 RME96_WCR_INP_1;
863 break;
864 case RME96_INPUT_XLR:
8b7fc421
RD		 865 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
866 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
867 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
1da177e4
LT		 868 rme96->rev > 4))
869 {
870 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
871 return -EINVAL;
872 }
873 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
874 RME96_WCR_INP_1;
875 break;
876 case RME96_INPUT_ANALOG:
877 if (!RME96_HAS_ANALOG_IN(rme96)) {
878 return -EINVAL;
879 }
880 rme96->areg |= RME96_AR_ANALOG;
881 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
882 if (rme96->rev < 4) {
883 /*
884 * Revision less than 004 does not support 64 and
885 * 88.2 kHz
886 */
887 if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
888 snd_rme96_capture_analog_setrate(rme96, 44100);
889 }
890 if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
891 snd_rme96_capture_analog_setrate(rme96, 32000);
892 }
893 }
894 return 0;
895 default:
896 return -EINVAL;
897 }
898 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
899 rme96->areg &= ~RME96_AR_ANALOG;
900 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
901 }
902 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
903 return 0;
904}
905
906static int
a3aefd88 907snd_rme96_getinputtype(struct rme96 *rme96)
1da177e4
LT		 908{
909 if (rme96->areg & RME96_AR_ANALOG) {
910 return RME96_INPUT_ANALOG;
911 }
912 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
913 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
914}
915
916static void
a3aefd88 917snd_rme96_setframelog(struct rme96 *rme96,
1da177e4
LT		 918 int n_channels,
919 int is_playback)
920{
921 int frlog;
922
923 if (n_channels == 2) {
924 frlog = 1;
925 } else {
926 /* assume 8 channels */
927 frlog = 3;
928 }
929 if (is_playback) {
930 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
931 rme96->playback_frlog = frlog;
932 } else {
933 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
934 rme96->capture_frlog = frlog;
935 }
936}
937
938static int
6c869d30 939snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format)
1da177e4
LT		 940{
941 switch (format) {
942 case SNDRV_PCM_FORMAT_S16_LE:
943 rme96->wcreg &= ~RME96_WCR_MODE24;
944 break;
945 case SNDRV_PCM_FORMAT_S32_LE:
946 rme96->wcreg |= RME96_WCR_MODE24;
947 break;
948 default:
949 return -EINVAL;
950 }
951 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
952 return 0;
953}
954
955static int
6c869d30 956snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format)
1da177e4
LT		 957{
958 switch (format) {
959 case SNDRV_PCM_FORMAT_S16_LE:
960 rme96->wcreg &= ~RME96_WCR_MODE24_2;
961 break;
962 case SNDRV_PCM_FORMAT_S32_LE:
963 rme96->wcreg |= RME96_WCR_MODE24_2;
964 break;
965 default:
966 return -EINVAL;
967 }
968 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
969 return 0;
970}
971
972static void
a3aefd88 973snd_rme96_set_period_properties(struct rme96 *rme96,
1da177e4
LT		 974 size_t period_bytes)
975{
976 switch (period_bytes) {
977 case RME96_LARGE_BLOCK_SIZE:
978 rme96->wcreg &= ~RME96_WCR_ISEL;
979 break;
980 case RME96_SMALL_BLOCK_SIZE:
981 rme96->wcreg |= RME96_WCR_ISEL;
982 break;
983 default:
984 snd_BUG();
985 break;
986 }
987 rme96->wcreg &= ~RME96_WCR_IDIS;
988 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
989}
990
991static int
a3aefd88
TI		 992snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
993 struct snd_pcm_hw_params *params)
1da177e4 994{
a3aefd88
TI		 995 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
996 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 997 int err, rate, dummy;
a74a8216 998 bool apply_dac_volume = false;
1da177e4 999
4d23359b
CL		 1000 runtime->dma_area = (void __force *)(rme96->iobase +
1001 RME96_IO_PLAY_BUFFER);
1da177e4
LT		 1002 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
1003 runtime->dma_bytes = RME96_BUFFER_SIZE;
1004
1005 spin_lock_irq(&rme96->lock);
1006 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1007 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1008 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1009 {
1010 /* slave clock */
1011 if ((int)params_rate(params) != rate) {
a74a8216
TI		 1012 err = -EIO;
1013 goto error;
1014 }
1015 } else {
1016 err = snd_rme96_playback_setrate(rme96, params_rate(params));
1017 if (err < 0)
1018 goto error;
1019 apply_dac_volume = err > 0; /* need to restore volume later? */
1da177e4 1020 }
a74a8216
TI		 1021
1022 err = snd_rme96_playback_setformat(rme96, params_format(params));
1023 if (err < 0)
1024 goto error;
1da177e4
LT		 1025 snd_rme96_setframelog(rme96, params_channels(params), 1);
1026 if (rme96->capture_periodsize != 0) {
1027 if (params_period_size(params) << rme96->playback_frlog !=
1028 rme96->capture_periodsize)
1029 {
a74a8216
TI		 1030 err = -EBUSY;
1031 goto error;
1da177e4
LT		 1032 }
1033 }
1034 rme96->playback_periodsize =
1035 params_period_size(params) << rme96->playback_frlog;
1036 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1037 /* S/PDIF setup */
1038 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1039 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1040 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1041 }
a74a8216
TI		 1042
1043 err = 0;
1044 error:
1da177e4 1045 spin_unlock_irq(&rme96->lock);
a74a8216
TI		 1046 if (apply_dac_volume) {
1047 usleep_range(3000, 10000);
1048 snd_rme96_apply_dac_volume(rme96);
1049 }
1050
1051 return err;
1da177e4
LT		 1052}
1053
1054static int
a3aefd88
TI		 1055snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1056 struct snd_pcm_hw_params *params)
1da177e4 1057{
a3aefd88
TI		 1058 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1059 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1060 int err, isadat, rate;
1061
4d23359b
CL		 1062 runtime->dma_area = (void __force *)(rme96->iobase +
1063 RME96_IO_REC_BUFFER);
1da177e4
LT		 1064 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1065 runtime->dma_bytes = RME96_BUFFER_SIZE;
1066
1067 spin_lock_irq(&rme96->lock);
1068 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1069 spin_unlock_irq(&rme96->lock);
1070 return err;
1071 }
1072 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1073 if ((err = snd_rme96_capture_analog_setrate(rme96,
1074 params_rate(params))) < 0)
1075 {
1076 spin_unlock_irq(&rme96->lock);
1077 return err;
1078 }
1079 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1080 if ((int)params_rate(params) != rate) {
1081 spin_unlock_irq(&rme96->lock);
1082 return -EIO;
1083 }
1084 if ((isadat && runtime->hw.channels_min == 2) ||
1085 (!isadat && runtime->hw.channels_min == 8))
1086 {
1087 spin_unlock_irq(&rme96->lock);
1088 return -EIO;
1089 }
1090 }
1091 snd_rme96_setframelog(rme96, params_channels(params), 0);
1092 if (rme96->playback_periodsize != 0) {
1093 if (params_period_size(params) << rme96->capture_frlog !=
1094 rme96->playback_periodsize)
1095 {
1096 spin_unlock_irq(&rme96->lock);
1097 return -EBUSY;
1098 }
1099 }
1100 rme96->capture_periodsize =
1101 params_period_size(params) << rme96->capture_frlog;
1102 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1103 spin_unlock_irq(&rme96->lock);
1104
1105 return 0;
1106}
1107
1108static void
b892ca1c
KP		 1109snd_rme96_trigger(struct rme96 *rme96,
1110 int op)
1da177e4 1111{
b892ca1c 1112 if (op & RME96_TB_RESET_PLAYPOS)
1da177e4 1113 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
b892ca1c 1114 if (op & RME96_TB_RESET_CAPTUREPOS)
1da177e4 1115 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
b892ca1c
KP		 1116 if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) {
1117 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1118 if (rme96->rcreg & RME96_RCR_IRQ)
1119 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1da177e4 1120 }
b892ca1c
KP		 1121 if (op & RME96_TB_CLEAR_CAPTURE_IRQ) {
1122 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1123 if (rme96->rcreg & RME96_RCR_IRQ_2)
1124 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1125 }
1126 if (op & RME96_TB_START_PLAYBACK)
1127 rme96->wcreg |= RME96_WCR_START;
1128 if (op & RME96_TB_STOP_PLAYBACK)
1129 rme96->wcreg &= ~RME96_WCR_START;
1130 if (op & RME96_TB_START_CAPTURE)
1131 rme96->wcreg |= RME96_WCR_START_2;
1132 if (op & RME96_TB_STOP_CAPTURE)
1133 rme96->wcreg &= ~RME96_WCR_START_2;
1da177e4
LT		 1134 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1135}
1136
1da177e4 1137
1da177e4
LT		 1138
1139static irqreturn_t
1140snd_rme96_interrupt(int irq,
7d12e780 1141 void *dev_id)
1da177e4 1142{
a3aefd88 1143 struct rme96 *rme96 = (struct rme96 *)dev_id;
1da177e4
LT		 1144
1145 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1146 /* fastpath out, to ease interrupt sharing */
1147 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1148 (rme96->rcreg & RME96_RCR_IRQ_2)))
1149 {
1150 return IRQ_NONE;
1151 }
1152
1153 if (rme96->rcreg & RME96_RCR_IRQ) {
1154 /* playback */
1155 snd_pcm_period_elapsed(rme96->playback_substream);
1156 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1157 }
1158 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1159 /* capture */
1160 snd_pcm_period_elapsed(rme96->capture_substream);
1161 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1162 }
1163 return IRQ_HANDLED;
1164}
1165
84e7b998 1166static const unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1da177e4 1167
84e7b998 1168static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1da177e4
LT		 1169 .count = ARRAY_SIZE(period_bytes),
1170 .list = period_bytes,
1171 .mask = 0
1172};
1173
2ce7fb57
TI		 1174static void
1175rme96_set_buffer_size_constraint(struct rme96 *rme96,
1176 struct snd_pcm_runtime *runtime)
1177{
1178 unsigned int size;
1179
1a8e41ef
LPC		 1180 snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1181 RME96_BUFFER_SIZE);
2ce7fb57
TI		 1182 if ((size = rme96->playback_periodsize) != 0 ||
1183 (size = rme96->capture_periodsize) != 0)
1a8e41ef 1184 snd_pcm_hw_constraint_single(runtime,
2ce7fb57 1185 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1a8e41ef 1186 size);
2ce7fb57
TI		 1187 else
1188 snd_pcm_hw_constraint_list(runtime, 0,
1189 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1190 &hw_constraints_period_bytes);
1191}
1192
1da177e4 1193static int
a3aefd88 1194snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1195{
1196 int rate, dummy;
a3aefd88
TI		 1197 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1198 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1199
b892ca1c 1200 snd_pcm_set_sync(substream);
1da177e4 1201 spin_lock_irq(&rme96->lock);
2cb98d01 1202 if (rme96->playback_substream) {
1da177e4
LT		 1203 spin_unlock_irq(&rme96->lock);
1204 return -EBUSY;
1205 }
1206 rme96->wcreg &= ~RME96_WCR_ADAT;
1207 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1208 rme96->playback_substream = substream;
1209 spin_unlock_irq(&rme96->lock);
1210
1211 runtime->hw = snd_rme96_playback_spdif_info;
1212 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1213 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1214 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1215 {
1216 /* slave clock */
918f3a0e 1217 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1218 runtime->hw.rate_min = rate;
1219 runtime->hw.rate_max = rate;
1220 }
2ce7fb57 1221 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1222
1223 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1224 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1225 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1226 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1227 return 0;
1228}
1229
1230static int
a3aefd88 1231snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1232{
1233 int isadat, rate;
a3aefd88
TI		 1234 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1235 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1236
b892ca1c 1237 snd_pcm_set_sync(substream);
1da177e4
LT		 1238 runtime->hw = snd_rme96_capture_spdif_info;
1239 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1240 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1241 {
1242 if (isadat) {
1243 return -EIO;
1244 }
918f3a0e 1245 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1246 runtime->hw.rate_min = rate;
1247 runtime->hw.rate_max = rate;
1248 }
1249
1250 spin_lock_irq(&rme96->lock);
2cb98d01 1251 if (rme96->capture_substream) {
1da177e4
LT		 1252 spin_unlock_irq(&rme96->lock);
1253 return -EBUSY;
1254 }
1255 rme96->capture_substream = substream;
1256 spin_unlock_irq(&rme96->lock);
1257
2ce7fb57 1258 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1259 return 0;
1260}
1261
1262static int
a3aefd88 1263snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1264{
1265 int rate, dummy;
a3aefd88
TI		 1266 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1267 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1268
b892ca1c 1269 snd_pcm_set_sync(substream);
1da177e4 1270 spin_lock_irq(&rme96->lock);
2cb98d01 1271 if (rme96->playback_substream) {
1da177e4
LT		 1272 spin_unlock_irq(&rme96->lock);
1273 return -EBUSY;
1274 }
1275 rme96->wcreg |= RME96_WCR_ADAT;
1276 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1277 rme96->playback_substream = substream;
1278 spin_unlock_irq(&rme96->lock);
1279
1280 runtime->hw = snd_rme96_playback_adat_info;
1281 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1282 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1283 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1284 {
1285 /* slave clock */
918f3a0e 1286 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1287 runtime->hw.rate_min = rate;
1288 runtime->hw.rate_max = rate;
1289 }
2ce7fb57 1290 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1291 return 0;
1292}
1293
1294static int
a3aefd88 1295snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1296{
1297 int isadat, rate;
a3aefd88
TI		 1298 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1299 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1300
b892ca1c 1301 snd_pcm_set_sync(substream);
1da177e4
LT		 1302 runtime->hw = snd_rme96_capture_adat_info;
1303 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1304 /* makes no sense to use analog input. Note that analog
1305 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1306 return -EIO;
1307 }
1308 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1309 if (!isadat) {
1310 return -EIO;
1311 }
918f3a0e 1312 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1313 runtime->hw.rate_min = rate;
1314 runtime->hw.rate_max = rate;
1315 }
1316
1317 spin_lock_irq(&rme96->lock);
2cb98d01 1318 if (rme96->capture_substream) {
1da177e4
LT		 1319 spin_unlock_irq(&rme96->lock);
1320 return -EBUSY;
1321 }
1322 rme96->capture_substream = substream;
1323 spin_unlock_irq(&rme96->lock);
1324
2ce7fb57 1325 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1326 return 0;
1327}
1328
1329static int
a3aefd88 1330snd_rme96_playback_close(struct snd_pcm_substream *substream)
1da177e4 1331{
a3aefd88 1332 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1333 int spdif = 0;
1334
1335 spin_lock_irq(&rme96->lock);
1336 if (RME96_ISPLAYING(rme96)) {
b892ca1c 1337 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1da177e4
LT		 1338 }
1339 rme96->playback_substream = NULL;
1340 rme96->playback_periodsize = 0;
1341 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1342 spin_unlock_irq(&rme96->lock);
1343 if (spdif) {
1344 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1345 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1346 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1347 }
1348 return 0;
1349}
1350
1351static int
a3aefd88 1352snd_rme96_capture_close(struct snd_pcm_substream *substream)
1da177e4 1353{
a3aefd88 1354 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1355
1356 spin_lock_irq(&rme96->lock);
1357 if (RME96_ISRECORDING(rme96)) {
b892ca1c 1358 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1da177e4
LT		 1359 }
1360 rme96->capture_substream = NULL;
1361 rme96->capture_periodsize = 0;
1362 spin_unlock_irq(&rme96->lock);
1363 return 0;
1364}
1365
1366static int
a3aefd88 1367snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 1368{
a3aefd88 1369 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1370
1371 spin_lock_irq(&rme96->lock);
1372 if (RME96_ISPLAYING(rme96)) {
b892ca1c 1373 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1da177e4
LT		 1374 }
1375 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1376 spin_unlock_irq(&rme96->lock);
1377 return 0;
1378}
1379
1380static int
a3aefd88 1381snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 1382{
a3aefd88 1383 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1384
1385 spin_lock_irq(&rme96->lock);
1386 if (RME96_ISRECORDING(rme96)) {
b892ca1c 1387 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1da177e4
LT		 1388 }
1389 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1390 spin_unlock_irq(&rme96->lock);
1391 return 0;
1392}
1393
1394static int
a3aefd88 1395snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 1396 int cmd)
1397{
a3aefd88 1398 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
b892ca1c
KP		 1399 struct snd_pcm_substream *s;
1400 bool sync;
1401
1402 snd_pcm_group_for_each_entry(s, substream) {
1403 if (snd_pcm_substream_chip(s) == rme96)
1404 snd_pcm_trigger_done(s, substream);
1405 }
1406
1407 sync = (rme96->playback_substream && rme96->capture_substream) &&
1408 (rme96->playback_substream->group ==
1409 rme96->capture_substream->group);
1da177e4
LT		 1410
1411 switch (cmd) {
1412 case SNDRV_PCM_TRIGGER_START:
1413 if (!RME96_ISPLAYING(rme96)) {
b892ca1c 1414 if (substream != rme96->playback_substream)
1da177e4 1415 return -EBUSY;
b892ca1c
KP		 1416 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1417 : RME96_START_PLAYBACK);
1da177e4
LT		 1418 }
1419 break;
1420
528ba522 1421 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 1422 case SNDRV_PCM_TRIGGER_STOP:
1423 if (RME96_ISPLAYING(rme96)) {
b892ca1c 1424 if (substream != rme96->playback_substream)
1da177e4 1425 return -EBUSY;
b892ca1c
KP		 1426 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1427 : RME96_STOP_PLAYBACK);
1da177e4
LT		 1428 }
1429 break;
1430
1431 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
b892ca1c
KP		 1432 if (RME96_ISPLAYING(rme96))
1433 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1434 : RME96_STOP_PLAYBACK);
1da177e4
LT		 1435 break;
1436
528ba522 1437 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4 1438 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
b892ca1c
KP		 1439 if (!RME96_ISPLAYING(rme96))
1440 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1441 : RME96_RESUME_PLAYBACK);
1da177e4 1442 break;
b892ca1c 1443
1da177e4
LT		 1444 default:
1445 return -EINVAL;
1446 }
b892ca1c 1447
1da177e4
LT		 1448 return 0;
1449}
1450
1451static int
a3aefd88 1452snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 1453 int cmd)
1454{
a3aefd88 1455 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
b892ca1c
KP		 1456 struct snd_pcm_substream *s;
1457 bool sync;
1458
1459 snd_pcm_group_for_each_entry(s, substream) {
1460 if (snd_pcm_substream_chip(s) == rme96)
1461 snd_pcm_trigger_done(s, substream);
1462 }
1463
1464 sync = (rme96->playback_substream && rme96->capture_substream) &&
1465 (rme96->playback_substream->group ==
1466 rme96->capture_substream->group);
1da177e4
LT		 1467
1468 switch (cmd) {
1469 case SNDRV_PCM_TRIGGER_START:
1470 if (!RME96_ISRECORDING(rme96)) {
b892ca1c 1471 if (substream != rme96->capture_substream)
1da177e4 1472 return -EBUSY;
b892ca1c
KP		 1473 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1474 : RME96_START_CAPTURE);
1da177e4
LT		 1475 }
1476 break;
1477
528ba522 1478 case SNDRV_PCM_TRIGGER_SUSPEND:
1da177e4
LT		 1479 case SNDRV_PCM_TRIGGER_STOP:
1480 if (RME96_ISRECORDING(rme96)) {
b892ca1c 1481 if (substream != rme96->capture_substream)
1da177e4 1482 return -EBUSY;
b892ca1c
KP		 1483 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1484 : RME96_STOP_CAPTURE);
1da177e4
LT		 1485 }
1486 break;
1487
1488 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
b892ca1c
KP		 1489 if (RME96_ISRECORDING(rme96))
1490 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1491 : RME96_STOP_CAPTURE);
1da177e4
LT		 1492 break;
1493
528ba522 1494 case SNDRV_PCM_TRIGGER_RESUME:
1da177e4 1495 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
b892ca1c
KP		 1496 if (!RME96_ISRECORDING(rme96))
1497 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1498 : RME96_RESUME_CAPTURE);
1da177e4 1499 break;
b892ca1c 1500
1da177e4
LT		 1501 default:
1502 return -EINVAL;
1503 }
1504
1505 return 0;
1506}
1507
1508static snd_pcm_uframes_t
a3aefd88 1509snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 1510{
a3aefd88 1511 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1512 return snd_rme96_playback_ptr(rme96);
1513}
1514
1515static snd_pcm_uframes_t
a3aefd88 1516snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 1517{
a3aefd88 1518 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1519 return snd_rme96_capture_ptr(rme96);
1520}
1521
6769e988 1522static const struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1da177e4
LT		 1523 .open = snd_rme96_playback_spdif_open,
1524 .close = snd_rme96_playback_close,
1525 .ioctl = snd_pcm_lib_ioctl,
1526 .hw_params = snd_rme96_playback_hw_params,
1527 .prepare = snd_rme96_playback_prepare,
1528 .trigger = snd_rme96_playback_trigger,
1529 .pointer = snd_rme96_playback_pointer,
53945f5b
TI		 1530 .copy_user = snd_rme96_playback_copy,
1531 .copy_kernel = snd_rme96_playback_copy_kernel,
1532 .fill_silence = snd_rme96_playback_silence,
1da177e4
LT		 1533 .mmap = snd_pcm_lib_mmap_iomem,
1534};
1535
6769e988 1536static const struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1da177e4
LT		 1537 .open = snd_rme96_capture_spdif_open,
1538 .close = snd_rme96_capture_close,
1539 .ioctl = snd_pcm_lib_ioctl,
1540 .hw_params = snd_rme96_capture_hw_params,
1541 .prepare = snd_rme96_capture_prepare,
1542 .trigger = snd_rme96_capture_trigger,
1543 .pointer = snd_rme96_capture_pointer,
53945f5b
TI		 1544 .copy_user = snd_rme96_capture_copy,
1545 .copy_kernel = snd_rme96_capture_copy_kernel,
1da177e4
LT		 1546 .mmap = snd_pcm_lib_mmap_iomem,
1547};
1548
6769e988 1549static const struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1da177e4
LT		 1550 .open = snd_rme96_playback_adat_open,
1551 .close = snd_rme96_playback_close,
1552 .ioctl = snd_pcm_lib_ioctl,
1553 .hw_params = snd_rme96_playback_hw_params,
1554 .prepare = snd_rme96_playback_prepare,
1555 .trigger = snd_rme96_playback_trigger,
1556 .pointer = snd_rme96_playback_pointer,
53945f5b
TI		 1557 .copy_user = snd_rme96_playback_copy,
1558 .copy_kernel = snd_rme96_playback_copy_kernel,
1559 .fill_silence = snd_rme96_playback_silence,
1da177e4
LT		 1560 .mmap = snd_pcm_lib_mmap_iomem,
1561};
1562
6769e988 1563static const struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1da177e4
LT		 1564 .open = snd_rme96_capture_adat_open,
1565 .close = snd_rme96_capture_close,
1566 .ioctl = snd_pcm_lib_ioctl,
1567 .hw_params = snd_rme96_capture_hw_params,
1568 .prepare = snd_rme96_capture_prepare,
1569 .trigger = snd_rme96_capture_trigger,
1570 .pointer = snd_rme96_capture_pointer,
53945f5b
TI		 1571 .copy_user = snd_rme96_capture_copy,
1572 .copy_kernel = snd_rme96_capture_copy_kernel,
1da177e4
LT		 1573 .mmap = snd_pcm_lib_mmap_iomem,
1574};
1575
1576static void
1577snd_rme96_free(void *private_data)
1578{
a3aefd88 1579 struct rme96 *rme96 = (struct rme96 *)private_data;
1da177e4 1580
2cb98d01 1581 if (!rme96)
1da177e4 1582 return;
2cb98d01 1583
1da177e4 1584 if (rme96->irq >= 0) {
b892ca1c 1585 snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1da177e4
LT		 1586 rme96->areg &= ~RME96_AR_DAC_EN;
1587 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1588 free_irq(rme96->irq, (void *)rme96);
1589 rme96->irq = -1;
1590 }
1591 if (rme96->iobase) {
1592 iounmap(rme96->iobase);
1593 rme96->iobase = NULL;
1594 }
1595 if (rme96->port) {
1596 pci_release_regions(rme96->pci);
1597 rme96->port = 0;
1598 }
a932be91 1599#ifdef CONFIG_PM_SLEEP
528ba522
KP		 1600 vfree(rme96->playback_suspend_buffer);
1601 vfree(rme96->capture_suspend_buffer);
1602#endif
1da177e4
LT		 1603 pci_disable_device(rme96->pci);
1604}
1605
1606static void
a3aefd88 1607snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1da177e4 1608{
9fe856e4 1609 struct rme96 *rme96 = pcm->private_data;
1da177e4
LT		 1610 rme96->spdif_pcm = NULL;
1611}
1612
1613static void
a3aefd88 1614snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1da177e4 1615{
9fe856e4 1616 struct rme96 *rme96 = pcm->private_data;
1da177e4
LT		 1617 rme96->adat_pcm = NULL;
1618}
1619
e23e7a14 1620static int
a3aefd88 1621snd_rme96_create(struct rme96 *rme96)
1da177e4
LT		 1622{
1623 struct pci_dev *pci = rme96->pci;
1624 int err;
1625
1626 rme96->irq = -1;
1627 spin_lock_init(&rme96->lock);
1628
1629 if ((err = pci_enable_device(pci)) < 0)
1630 return err;
1631
1632 if ((err = pci_request_regions(pci, "RME96")) < 0)
1633 return err;
1634 rme96->port = pci_resource_start(rme96->pci, 0);
1635
44977b71
HH		 1636 rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE);
1637 if (!rme96->iobase) {
342cd934
TI		 1638 dev_err(rme96->card->dev,
1639 "unable to remap memory region 0x%lx-0x%lx\n",
1640 rme96->port, rme96->port + RME96_IO_SIZE - 1);
688956f2
TI		 1641 return -ENOMEM;
1642 }
1643
437a5a46 1644 if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
934c2b6d 1645 KBUILD_MODNAME, rme96)) {
342cd934 1646 dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 1647 return -EBUSY;
1648 }
1649 rme96->irq = pci->irq;
1650
1da177e4
LT		 1651 /* read the card's revision number */
1652 pci_read_config_byte(pci, 8, &rme96->rev);
1653
1654 /* set up ALSA pcm device for S/PDIF */
1655 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1656 1, 1, &rme96->spdif_pcm)) < 0)
1657 {
1658 return err;
1659 }
1660 rme96->spdif_pcm->private_data = rme96;
1661 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1662 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1663 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1664 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1665
1666 rme96->spdif_pcm->info_flags = 0;
1667
1668 /* set up ALSA pcm device for ADAT */
8b7fc421 1669 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1da177e4
LT		 1670 /* ADAT is not available on the base model */
1671 rme96->adat_pcm = NULL;
1672 } else {
1673 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1674 1, 1, &rme96->adat_pcm)) < 0)
1675 {
1676 return err;
1677 }
1678 rme96->adat_pcm->private_data = rme96;
1679 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1680 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1681 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1682 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1683
1684 rme96->adat_pcm->info_flags = 0;
1685 }
1686
1687 rme96->playback_periodsize = 0;
1688 rme96->capture_periodsize = 0;
1689
1690 /* make sure playback/capture is stopped, if by some reason active */
b892ca1c 1691 snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1da177e4
LT		 1692
1693 /* set default values in registers */
1694 rme96->wcreg =
1695 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1696 RME96_WCR_SEL | /* normal playback */
1697 RME96_WCR_MASTER | /* set to master clock mode */
1698 RME96_WCR_INP_0; /* set coaxial input */
1699
1700 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1701
1702 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1703 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1704
1705 /* reset the ADC */
1706 writel(rme96->areg | RME96_AR_PD2,
1707 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1708 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1709
1710 /* reset and enable the DAC (order is important). */
1711 snd_rme96_reset_dac(rme96);
1712 rme96->areg |= RME96_AR_DAC_EN;
1713 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1714
1715 /* reset playback and record buffer pointers */
1716 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1717 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1718
1719 /* reset volume */
1720 rme96->vol[0] = rme96->vol[1] = 0;
1721 if (RME96_HAS_ANALOG_OUT(rme96)) {
1722 snd_rme96_apply_dac_volume(rme96);
1723 }
1724
1725 /* init switch interface */
1726 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1727 return err;
1728 }
1729
1730 /* init proc interface */
1731 snd_rme96_proc_init(rme96);
1732
1733 return 0;
1734}
1735
1736/*
1737 * proc interface
1738 */
1739
1740static void
a3aefd88 1741snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1da177e4
LT		 1742{
1743 int n;
9fe856e4 1744 struct rme96 *rme96 = entry->private_data;
1da177e4
LT		 1745
1746 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1747
1748 snd_iprintf(buffer, rme96->card->longname);
1749 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1750
1751 snd_iprintf(buffer, "\nGeneral settings\n");
1752 if (rme96->wcreg & RME96_WCR_IDIS) {
1753 snd_iprintf(buffer, " period size: N/A (interrupts "
1754 "disabled)\n");
1755 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1756 snd_iprintf(buffer, " period size: 2048 bytes\n");
1757 } else {
1758 snd_iprintf(buffer, " period size: 8192 bytes\n");
1759 }
1760 snd_iprintf(buffer, "\nInput settings\n");
1761 switch (snd_rme96_getinputtype(rme96)) {
1762 case RME96_INPUT_OPTICAL:
1763 snd_iprintf(buffer, " input: optical");
1764 break;
1765 case RME96_INPUT_COAXIAL:
1766 snd_iprintf(buffer, " input: coaxial");
1767 break;
1768 case RME96_INPUT_INTERNAL:
1769 snd_iprintf(buffer, " input: internal");
1770 break;
1771 case RME96_INPUT_XLR:
1772 snd_iprintf(buffer, " input: XLR");
1773 break;
1774 case RME96_INPUT_ANALOG:
1775 snd_iprintf(buffer, " input: analog");
1776 break;
1777 }
1778 if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1779 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1780 } else {
1781 if (n) {
1782 snd_iprintf(buffer, " (8 channels)\n");
1783 } else {
1784 snd_iprintf(buffer, " (2 channels)\n");
1785 }
1786 snd_iprintf(buffer, " sample rate: %d Hz\n",
1787 snd_rme96_capture_getrate(rme96, &n));
1788 }
1789 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1790 snd_iprintf(buffer, " sample format: 24 bit\n");
1791 } else {
1792 snd_iprintf(buffer, " sample format: 16 bit\n");
1793 }
1794
1795 snd_iprintf(buffer, "\nOutput settings\n");
1796 if (rme96->wcreg & RME96_WCR_SEL) {
1797 snd_iprintf(buffer, " output signal: normal playback\n");
1798 } else {
1799 snd_iprintf(buffer, " output signal: same as input\n");
1800 }
1801 snd_iprintf(buffer, " sample rate: %d Hz\n",
1802 snd_rme96_playback_getrate(rme96));
1803 if (rme96->wcreg & RME96_WCR_MODE24) {
1804 snd_iprintf(buffer, " sample format: 24 bit\n");
1805 } else {
1806 snd_iprintf(buffer, " sample format: 16 bit\n");
1807 }
1808 if (rme96->areg & RME96_AR_WSEL) {
1809 snd_iprintf(buffer, " sample clock source: word clock\n");
1810 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1811 snd_iprintf(buffer, " sample clock source: internal\n");
1812 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1813 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1814 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1815 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1816 } else {
1817 snd_iprintf(buffer, " sample clock source: autosync\n");
1818 }
1819 if (rme96->wcreg & RME96_WCR_PRO) {
1820 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1821 } else {
1822 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1823 }
1824 if (rme96->wcreg & RME96_WCR_EMP) {
1825 snd_iprintf(buffer, " emphasis: on\n");
1826 } else {
1827 snd_iprintf(buffer, " emphasis: off\n");
1828 }
1829 if (rme96->wcreg & RME96_WCR_DOLBY) {
1830 snd_iprintf(buffer, " non-audio (dolby): on\n");
1831 } else {
1832 snd_iprintf(buffer, " non-audio (dolby): off\n");
1833 }
1834 if (RME96_HAS_ANALOG_IN(rme96)) {
1835 snd_iprintf(buffer, "\nAnalog output settings\n");
1836 switch (snd_rme96_getmontracks(rme96)) {
1837 case RME96_MONITOR_TRACKS_1_2:
1838 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1839 break;
1840 case RME96_MONITOR_TRACKS_3_4:
1841 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1842 break;
1843 case RME96_MONITOR_TRACKS_5_6:
1844 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1845 break;
1846 case RME96_MONITOR_TRACKS_7_8:
1847 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1848 break;
1849 }
1850 switch (snd_rme96_getattenuation(rme96)) {
1851 case RME96_ATTENUATION_0:
1852 snd_iprintf(buffer, " attenuation: 0 dB\n");
1853 break;
1854 case RME96_ATTENUATION_6:
1855 snd_iprintf(buffer, " attenuation: -6 dB\n");
1856 break;
1857 case RME96_ATTENUATION_12:
1858 snd_iprintf(buffer, " attenuation: -12 dB\n");
1859 break;
1860 case RME96_ATTENUATION_18:
1861 snd_iprintf(buffer, " attenuation: -18 dB\n");
1862 break;
1863 }
1864 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1865 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1866 }
1867}
1868
e23e7a14 1869static void snd_rme96_proc_init(struct rme96 *rme96)
1da177e4 1870{
a3aefd88 1871 struct snd_info_entry *entry;
1da177e4
LT		 1872
1873 if (! snd_card_proc_new(rme96->card, "rme96", &entry))
bf850204 1874 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
1da177e4
LT		 1875}
1876
1877/*
1878 * control interface
1879 */
1880
a5ce8890
TI		 1881#define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info
1882
1da177e4 1883static int
a3aefd88 1884snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1885{
a3aefd88 1886 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1887
1888 spin_lock_irq(&rme96->lock);
1889 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1890 spin_unlock_irq(&rme96->lock);
1891 return 0;
1892}
1893static int
a3aefd88 1894snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1895{
a3aefd88 1896 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1897 unsigned int val;
1898 int change;
1899
1900 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1901 spin_lock_irq(&rme96->lock);
1902 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1903 change = val != rme96->wcreg;
1904 rme96->wcreg = val;
1905 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1906 spin_unlock_irq(&rme96->lock);
1907 return change;
1908}
1909
1910static int
a3aefd88 1911snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 1912{
9c30d46a
TI		 1913 static const char * const _texts[5] = {
1914 "Optical", "Coaxial", "Internal", "XLR", "Analog"
1915 };
a3aefd88 1916 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
9c30d46a
TI		 1917 const char *texts[5] = {
1918 _texts[0], _texts[1], _texts[2], _texts[3], _texts[4]
1919 };
1920 int num_items;
1da177e4 1921
1da177e4 1922 switch (rme96->pci->device) {
8b7fc421
RD		 1923 case PCI_DEVICE_ID_RME_DIGI96:
1924 case PCI_DEVICE_ID_RME_DIGI96_8:
9c30d46a 1925 num_items = 3;
1da177e4 1926 break;
8b7fc421 1927 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
9c30d46a 1928 num_items = 4;
1da177e4 1929 break;
8b7fc421 1930 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1931 if (rme96->rev > 4) {
1932 /* PST */
9c30d46a 1933 num_items = 4;
1da177e4
LT		 1934 texts[3] = _texts[4]; /* Analog instead of XLR */
1935 } else {
1936 /* PAD */
9c30d46a 1937 num_items = 5;
1da177e4
LT		 1938 }
1939 break;
1940 default:
1941 snd_BUG();
9c30d46a 1942 return -EINVAL;
1da177e4 1943 }
9c30d46a 1944 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1da177e4
LT		 1945}
1946static int
a3aefd88 1947snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1948{
a3aefd88 1949 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1950 unsigned int items = 3;
1951
1952 spin_lock_irq(&rme96->lock);
1953 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1954
1955 switch (rme96->pci->device) {
8b7fc421
RD		 1956 case PCI_DEVICE_ID_RME_DIGI96:
1957 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1958 items = 3;
1959 break;
8b7fc421 1960 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1961 items = 4;
1962 break;
8b7fc421 1963 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1964 if (rme96->rev > 4) {
1965 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1966 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1967 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1968 }
1969 items = 4;
1970 } else {
1971 items = 5;
1972 }
1973 break;
1974 default:
1975 snd_BUG();
1976 break;
1977 }
1978 if (ucontrol->value.enumerated.item[0] >= items) {
1979 ucontrol->value.enumerated.item[0] = items - 1;
1980 }
1981
1982 spin_unlock_irq(&rme96->lock);
1983 return 0;
1984}
1985static int
a3aefd88 1986snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1987{
a3aefd88 1988 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1989 unsigned int val;
1990 int change, items = 3;
1991
1992 switch (rme96->pci->device) {
8b7fc421
RD		 1993 case PCI_DEVICE_ID_RME_DIGI96:
1994 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1995 items = 3;
1996 break;
8b7fc421 1997 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1998 items = 4;
1999 break;
8b7fc421 2000 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 2001 if (rme96->rev > 4) {
2002 items = 4;
2003 } else {
2004 items = 5;
2005 }
2006 break;
2007 default:
2008 snd_BUG();
2009 break;
2010 }
2011 val = ucontrol->value.enumerated.item[0] % items;
2012
2013 /* special case for PST */
8b7fc421 2014 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1da177e4
LT		 2015 if (val == RME96_INPUT_XLR) {
2016 val = RME96_INPUT_ANALOG;
2017 }
2018 }
2019
2020 spin_lock_irq(&rme96->lock);
2021 change = (int)val != snd_rme96_getinputtype(rme96);
2022 snd_rme96_setinputtype(rme96, val);
2023 spin_unlock_irq(&rme96->lock);
2024 return change;
2025}
2026
2027static int
a3aefd88 2028snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 2029{
9c30d46a 2030 static const char * const texts[3] = { "AutoSync", "Internal", "Word" };
1da177e4 2031
9c30d46a 2032 return snd_ctl_enum_info(uinfo, 1, 3, texts);
1da177e4
LT		 2033}
2034static int
a3aefd88 2035snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2036{
a3aefd88 2037 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2038
2039 spin_lock_irq(&rme96->lock);
2040 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2041 spin_unlock_irq(&rme96->lock);
2042 return 0;
2043}
2044static int
a3aefd88 2045snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2046{
a3aefd88 2047 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2048 unsigned int val;
2049 int change;
2050
2051 val = ucontrol->value.enumerated.item[0] % 3;
2052 spin_lock_irq(&rme96->lock);
2053 change = (int)val != snd_rme96_getclockmode(rme96);
2054 snd_rme96_setclockmode(rme96, val);
2055 spin_unlock_irq(&rme96->lock);
2056 return change;
2057}
2058
2059static int
a3aefd88 2060snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 2061{
9c30d46a
TI		 2062 static const char * const texts[4] = {
2063 "0 dB", "-6 dB", "-12 dB", "-18 dB"
2064 };
1da177e4 2065
9c30d46a 2066 return snd_ctl_enum_info(uinfo, 1, 4, texts);
1da177e4
LT		 2067}
2068static int
a3aefd88 2069snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2070{
a3aefd88 2071 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2072
2073 spin_lock_irq(&rme96->lock);
2074 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2075 spin_unlock_irq(&rme96->lock);
2076 return 0;
2077}
2078static int
a3aefd88 2079snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2080{
a3aefd88 2081 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2082 unsigned int val;
2083 int change;
2084
2085 val = ucontrol->value.enumerated.item[0] % 4;
2086 spin_lock_irq(&rme96->lock);
2087
2088 change = (int)val != snd_rme96_getattenuation(rme96);
2089 snd_rme96_setattenuation(rme96, val);
2090 spin_unlock_irq(&rme96->lock);
2091 return change;
2092}
2093
2094static int
a3aefd88 2095snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 2096{
9c30d46a 2097 static const char * const texts[4] = { "1+2", "3+4", "5+6", "7+8" };
1da177e4 2098
9c30d46a 2099 return snd_ctl_enum_info(uinfo, 1, 4, texts);
1da177e4
LT		 2100}
2101static int
a3aefd88 2102snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2103{
a3aefd88 2104 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2105
2106 spin_lock_irq(&rme96->lock);
2107 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2108 spin_unlock_irq(&rme96->lock);
2109 return 0;
2110}
2111static int
a3aefd88 2112snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2113{
a3aefd88 2114 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2115 unsigned int val;
2116 int change;
2117
2118 val = ucontrol->value.enumerated.item[0] % 4;
2119 spin_lock_irq(&rme96->lock);
2120 change = (int)val != snd_rme96_getmontracks(rme96);
2121 snd_rme96_setmontracks(rme96, val);
2122 spin_unlock_irq(&rme96->lock);
2123 return change;
2124}
2125
a3aefd88 2126static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
1da177e4
LT		 2127{
2128 u32 val = 0;
2129 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2130 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2131 if (val & RME96_WCR_PRO)
2132 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2133 else
2134 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2135 return val;
2136}
2137
a3aefd88 2138static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1da177e4
LT		 2139{
2140 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2141 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2142 if (val & RME96_WCR_PRO)
2143 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2144 else
2145 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2146}
2147
a3aefd88 2148static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2149{
2150 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2151 uinfo->count = 1;
2152 return 0;
2153}
2154
a3aefd88 2155static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2156{
a3aefd88 2157 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2158
2159 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2160 return 0;
2161}
2162
a3aefd88 2163static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2164{
a3aefd88 2165 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2166 int change;
2167 u32 val;
2168
2169 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2170 spin_lock_irq(&rme96->lock);
2171 change = val != rme96->wcreg_spdif;
2172 rme96->wcreg_spdif = val;
2173 spin_unlock_irq(&rme96->lock);
2174 return change;
2175}
2176
a3aefd88 2177static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2178{
2179 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2180 uinfo->count = 1;
2181 return 0;
2182}
2183
a3aefd88 2184static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2185{
a3aefd88 2186 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2187
2188 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2189 return 0;
2190}
2191
a3aefd88 2192static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2193{
a3aefd88 2194 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2195 int change;
2196 u32 val;
2197
2198 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2199 spin_lock_irq(&rme96->lock);
2200 change = val != rme96->wcreg_spdif_stream;
2201 rme96->wcreg_spdif_stream = val;
2202 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2203 rme96->wcreg |= val;
2204 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2205 spin_unlock_irq(&rme96->lock);
2206 return change;
2207}
2208
a3aefd88 2209static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2210{
2211 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2212 uinfo->count = 1;
2213 return 0;
2214}
2215
a3aefd88 2216static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 2217{
2218 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2219 return 0;
2220}
2221
2222static int
a3aefd88 2223snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 2224{
a3aefd88 2225 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2226
2227 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2228 uinfo->count = 2;
2229 uinfo->value.integer.min = 0;
2230 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2231 return 0;
2232}
2233
2234static int
a3aefd88 2235snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
1da177e4 2236{
a3aefd88 2237 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2238
2239 spin_lock_irq(&rme96->lock);
2240 u->value.integer.value[0] = rme96->vol[0];
2241 u->value.integer.value[1] = rme96->vol[1];
2242 spin_unlock_irq(&rme96->lock);
2243
2244 return 0;
2245}
2246
2247static int
a3aefd88 2248snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
1da177e4 2249{
a3aefd88 2250 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4 2251 int change = 0;
4e98d6a7 2252 unsigned int vol, maxvol;
1da177e4 2253
4e98d6a7
TI		 2254
2255 if (!RME96_HAS_ANALOG_OUT(rme96))
1da177e4 2256 return -EINVAL;
4e98d6a7 2257 maxvol = RME96_185X_MAX_OUT(rme96);
1da177e4 2258 spin_lock_irq(&rme96->lock);
4e98d6a7
TI		 2259 vol = u->value.integer.value[0];
2260 if (vol != rme96->vol[0] && vol <= maxvol) {
2261 rme96->vol[0] = vol;
2262 change = 1;
2263 }
2264 vol = u->value.integer.value[1];
2265 if (vol != rme96->vol[1] && vol <= maxvol) {
2266 rme96->vol[1] = vol;
2267 change = 1;
1da177e4 2268 }
4e98d6a7
TI		 2269 if (change)
2270 snd_rme96_apply_dac_volume(rme96);
1da177e4
LT		 2271 spin_unlock_irq(&rme96->lock);
2272
2273 return change;
2274}
2275
a3aefd88 2276static struct snd_kcontrol_new snd_rme96_controls[] = {
1da177e4
LT		 2277{
2278 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2279 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2280 .info = snd_rme96_control_spdif_info,
2281 .get = snd_rme96_control_spdif_get,
2282 .put = snd_rme96_control_spdif_put
2283},
2284{
2285 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2286 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2287 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2288 .info = snd_rme96_control_spdif_stream_info,
2289 .get = snd_rme96_control_spdif_stream_get,
2290 .put = snd_rme96_control_spdif_stream_put
2291},
2292{
2293 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 2294 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2295 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2296 .info = snd_rme96_control_spdif_mask_info,
2297 .get = snd_rme96_control_spdif_mask_get,
2298 .private_value = IEC958_AES0_NONAUDIO |
2299 IEC958_AES0_PROFESSIONAL |
2300 IEC958_AES0_CON_EMPHASIS
2301},
2302{
2303 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 2304 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2305 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2306 .info = snd_rme96_control_spdif_mask_info,
2307 .get = snd_rme96_control_spdif_mask_get,
2308 .private_value = IEC958_AES0_NONAUDIO |
2309 IEC958_AES0_PROFESSIONAL |
2310 IEC958_AES0_PRO_EMPHASIS
2311},
2312{
2313 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2314 .name = "Input Connector",
2315 .info = snd_rme96_info_inputtype_control,
2316 .get = snd_rme96_get_inputtype_control,
2317 .put = snd_rme96_put_inputtype_control
2318},
2319{
2320 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2321 .name = "Loopback Input",
2322 .info = snd_rme96_info_loopback_control,
2323 .get = snd_rme96_get_loopback_control,
2324 .put = snd_rme96_put_loopback_control
2325},
2326{
2327 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2328 .name = "Sample Clock Source",
2329 .info = snd_rme96_info_clockmode_control,
2330 .get = snd_rme96_get_clockmode_control,
2331 .put = snd_rme96_put_clockmode_control
2332},
2333{
2334 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2335 .name = "Monitor Tracks",
2336 .info = snd_rme96_info_montracks_control,
2337 .get = snd_rme96_get_montracks_control,
2338 .put = snd_rme96_put_montracks_control
2339},
2340{
2341 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2342 .name = "Attenuation",
2343 .info = snd_rme96_info_attenuation_control,
2344 .get = snd_rme96_get_attenuation_control,
2345 .put = snd_rme96_put_attenuation_control
2346},
2347{
2348 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2349 .name = "DAC Playback Volume",
2350 .info = snd_rme96_dac_volume_info,
2351 .get = snd_rme96_dac_volume_get,
2352 .put = snd_rme96_dac_volume_put
2353}
2354};
2355
2356static int
a3aefd88
TI		 2357snd_rme96_create_switches(struct snd_card *card,
2358 struct rme96 *rme96)
1da177e4
LT		 2359{
2360 int idx, err;
a3aefd88 2361 struct snd_kcontrol *kctl;
1da177e4
LT		 2362
2363 for (idx = 0; idx < 7; idx++) {
2364 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2365 return err;
2366 if (idx == 1) /* IEC958 (S/PDIF) Stream */
2367 rme96->spdif_ctl = kctl;
2368 }
2369
2370 if (RME96_HAS_ANALOG_OUT(rme96)) {
2371 for (idx = 7; idx < 10; idx++)
2372 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2373 return err;
2374 }
2375
2376 return 0;
2377}
2378
2379/*
2380 * Card initialisation
2381 */
2382
a932be91 2383#ifdef CONFIG_PM_SLEEP
528ba522 2384
a932be91 2385static int rme96_suspend(struct device *dev)
528ba522 2386{
a932be91 2387 struct snd_card *card = dev_get_drvdata(dev);
528ba522
KP		 2388 struct rme96 *rme96 = card->private_data;
2389
2390 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2391 snd_pcm_suspend(rme96->playback_substream);
2392 snd_pcm_suspend(rme96->capture_substream);
2393
2394 /* save capture & playback pointers */
2395 rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
2396 & RME96_RCR_AUDIO_ADDR_MASK;
2397 rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS)
2398 & RME96_RCR_AUDIO_ADDR_MASK;
2399
2400 /* save playback and capture buffers */
2401 memcpy_fromio(rme96->playback_suspend_buffer,
2402 rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE);
2403 memcpy_fromio(rme96->capture_suspend_buffer,
2404 rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE);
2405
2406 /* disable the DAC */
2407 rme96->areg &= ~RME96_AR_DAC_EN;
2408 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
528ba522
KP		 2409 return 0;
2410}
2411
a932be91 2412static int rme96_resume(struct device *dev)
528ba522 2413{
a932be91 2414 struct snd_card *card = dev_get_drvdata(dev);
528ba522
KP		 2415 struct rme96 *rme96 = card->private_data;
2416
528ba522
KP		 2417 /* reset playback and record buffer pointers */
2418 writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS
2419 + rme96->playback_pointer);
2420 writel(0, rme96->iobase + RME96_IO_SET_REC_POS
2421 + rme96->capture_pointer);
2422
2423 /* restore playback and capture buffers */
2424 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER,
2425 rme96->playback_suspend_buffer, RME96_BUFFER_SIZE);
2426 memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER,
2427 rme96->capture_suspend_buffer, RME96_BUFFER_SIZE);
2428
2429 /* reset the ADC */
2430 writel(rme96->areg | RME96_AR_PD2,
2431 rme96->iobase + RME96_IO_ADDITIONAL_REG);
2432 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2433
2434 /* reset and enable DAC, restore analog volume */
2435 snd_rme96_reset_dac(rme96);
2436 rme96->areg |= RME96_AR_DAC_EN;
2437 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2438 if (RME96_HAS_ANALOG_OUT(rme96)) {
2439 usleep_range(3000, 10000);
2440 snd_rme96_apply_dac_volume(rme96);
2441 }
2442
2443 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2444
2445 return 0;
2446}
2447
a932be91
TI		 2448static SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume);
2449#define RME96_PM_OPS &rme96_pm
2450#else
2451#define RME96_PM_OPS NULL
2452#endif /* CONFIG_PM_SLEEP */
528ba522 2453
a3aefd88 2454static void snd_rme96_card_free(struct snd_card *card)
1da177e4
LT		 2455{
2456 snd_rme96_free(card->private_data);
2457}
2458
e23e7a14 2459static int
1da177e4
LT		 2460snd_rme96_probe(struct pci_dev *pci,
2461 const struct pci_device_id *pci_id)
2462{
2463 static int dev;
a3aefd88
TI		 2464 struct rme96 *rme96;
2465 struct snd_card *card;
1da177e4
LT		 2466 int err;
2467 u8 val;
2468
2469 if (dev >= SNDRV_CARDS) {
2470 return -ENODEV;
2471 }
2472 if (!enable[dev]) {
2473 dev++;
2474 return -ENOENT;
2475 }
60c5772b
TI		 2476 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2477 sizeof(struct rme96), &card);
e58de7ba
TI		 2478 if (err < 0)
2479 return err;
1da177e4 2480 card->private_free = snd_rme96_card_free;
9fe856e4 2481 rme96 = card->private_data;
1da177e4
LT		 2482 rme96->card = card;
2483 rme96->pci = pci;
d72a8010
ME		 2484 err = snd_rme96_create(rme96);
2485 if (err)
2486 goto free_card;
1da177e4 2487
a932be91 2488#ifdef CONFIG_PM_SLEEP
528ba522
KP		 2489 rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2490 if (!rme96->playback_suspend_buffer) {
d72a8010
ME		 2491 err = -ENOMEM;
2492 goto free_card;
528ba522
KP		 2493 }
2494 rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2495 if (!rme96->capture_suspend_buffer) {
d72a8010
ME		 2496 err = -ENOMEM;
2497 goto free_card;
528ba522
KP		 2498 }
2499#endif
2500
1da177e4
LT		 2501 strcpy(card->driver, "Digi96");
2502 switch (rme96->pci->device) {
8b7fc421 2503 case PCI_DEVICE_ID_RME_DIGI96:
1da177e4
LT		 2504 strcpy(card->shortname, "RME Digi96");
2505 break;
8b7fc421 2506 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 2507 strcpy(card->shortname, "RME Digi96/8");
2508 break;
8b7fc421 2509 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 2510 strcpy(card->shortname, "RME Digi96/8 PRO");
2511 break;
8b7fc421 2512 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 2513 pci_read_config_byte(rme96->pci, 8, &val);
2514 if (val < 5) {
2515 strcpy(card->shortname, "RME Digi96/8 PAD");
2516 } else {
2517 strcpy(card->shortname, "RME Digi96/8 PST");
2518 }
2519 break;
2520 }
2521 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2522 rme96->port, rme96->irq);
d72a8010
ME		 2523 err = snd_card_register(card);
2524 if (err)
2525 goto free_card;
2526
1da177e4
LT		 2527 pci_set_drvdata(pci, card);
2528 dev++;
2529 return 0;
d72a8010
ME		 2530free_card:
2531 snd_card_free(card);
2532 return err;
1da177e4
LT		 2533}
2534
e23e7a14 2535static void snd_rme96_remove(struct pci_dev *pci)
1da177e4
LT		 2536{
2537 snd_card_free(pci_get_drvdata(pci));
1da177e4
LT		 2538}
2539
e9f66d9b 2540static struct pci_driver rme96_driver = {
3733e424 2541 .name = KBUILD_MODNAME,
1da177e4
LT		 2542 .id_table = snd_rme96_ids,
2543 .probe = snd_rme96_probe,
e23e7a14 2544 .remove = snd_rme96_remove,
a932be91
TI		 2545 .driver = {
2546 .pm = RME96_PM_OPS,
2547 },
1da177e4
LT		 2548};
2549
e9f66d9b 2550module_pci_driver(rme96_driver);
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