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7614a55e | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
175859bf DD |
2 | #ifndef __sis7019_h__ |
3 | #define __sis7019_h__ | |
4 | ||
5 | /* | |
6 | * Definitions for SiS7019 Audio Accelerator | |
7 | * | |
8 | * Copyright (C) 2004-2007, David Dillow | |
9 | * Written by David Dillow <dave@thedillows.org> | |
10 | * Inspired by the Trident 4D-WaveDX/NX driver. | |
11 | * | |
12 | * All rights reserved. | |
175859bf DD |
13 | */ |
14 | ||
15 | ||
16 | /* General Control Register */ | |
17 | #define SIS_GCR 0x00 | |
18 | #define SIS_GCR_MACRO_POWER_DOWN 0x80000000 | |
19 | #define SIS_GCR_MODEM_ENABLE 0x00010000 | |
20 | #define SIS_GCR_SOFTWARE_RESET 0x00000001 | |
21 | ||
22 | /* General Interrupt Enable Register */ | |
23 | #define SIS_GIER 0x04 | |
24 | #define SIS_GIER_MODEM_TIMER_IRQ_ENABLE 0x00100000 | |
25 | #define SIS_GIER_MODEM_RX_DMA_IRQ_ENABLE 0x00080000 | |
26 | #define SIS_GIER_MODEM_TX_DMA_IRQ_ENABLE 0x00040000 | |
27 | #define SIS_GIER_AC97_GPIO1_IRQ_ENABLE 0x00020000 | |
28 | #define SIS_GIER_AC97_GPIO0_IRQ_ENABLE 0x00010000 | |
29 | #define SIS_GIER_AC97_SAMPLE_TIMER_IRQ_ENABLE 0x00000010 | |
30 | #define SIS_GIER_AUDIO_GLOBAL_TIMER_IRQ_ENABLE 0x00000008 | |
31 | #define SIS_GIER_AUDIO_RECORD_DMA_IRQ_ENABLE 0x00000004 | |
32 | #define SIS_GIER_AUDIO_PLAY_DMA_IRQ_ENABLE 0x00000002 | |
33 | #define SIS_GIER_AUDIO_WAVE_ENGINE_IRQ_ENABLE 0x00000001 | |
34 | ||
35 | /* General Interrupt Status Register */ | |
36 | #define SIS_GISR 0x08 | |
37 | #define SIS_GISR_MODEM_TIMER_IRQ_STATUS 0x00100000 | |
38 | #define SIS_GISR_MODEM_RX_DMA_IRQ_STATUS 0x00080000 | |
39 | #define SIS_GISR_MODEM_TX_DMA_IRQ_STATUS 0x00040000 | |
40 | #define SIS_GISR_AC97_GPIO1_IRQ_STATUS 0x00020000 | |
41 | #define SIS_GISR_AC97_GPIO0_IRQ_STATUS 0x00010000 | |
42 | #define SIS_GISR_AC97_SAMPLE_TIMER_IRQ_STATUS 0x00000010 | |
43 | #define SIS_GISR_AUDIO_GLOBAL_TIMER_IRQ_STATUS 0x00000008 | |
44 | #define SIS_GISR_AUDIO_RECORD_DMA_IRQ_STATUS 0x00000004 | |
45 | #define SIS_GISR_AUDIO_PLAY_DMA_IRQ_STATUS 0x00000002 | |
46 | #define SIS_GISR_AUDIO_WAVE_ENGINE_IRQ_STATUS 0x00000001 | |
47 | ||
48 | /* DMA Control Register */ | |
49 | #define SIS_DMA_CSR 0x10 | |
50 | #define SIS_DMA_CSR_PCI_SETTINGS 0x0000001d | |
51 | #define SIS_DMA_CSR_CONCURRENT_ENABLE 0x00000200 | |
52 | #define SIS_DMA_CSR_PIPELINE_ENABLE 0x00000100 | |
53 | #define SIS_DMA_CSR_RX_DRAIN_ENABLE 0x00000010 | |
54 | #define SIS_DMA_CSR_RX_FILL_ENABLE 0x00000008 | |
55 | #define SIS_DMA_CSR_TX_DRAIN_ENABLE 0x00000004 | |
56 | #define SIS_DMA_CSR_TX_LOWPRI_FILL_ENABLE 0x00000002 | |
57 | #define SIS_DMA_CSR_TX_HIPRI_FILL_ENABLE 0x00000001 | |
58 | ||
59 | /* Playback Channel Start Registers */ | |
60 | #define SIS_PLAY_START_A_REG 0x14 | |
61 | #define SIS_PLAY_START_B_REG 0x18 | |
62 | ||
63 | /* Playback Channel Stop Registers */ | |
64 | #define SIS_PLAY_STOP_A_REG 0x1c | |
65 | #define SIS_PLAY_STOP_B_REG 0x20 | |
66 | ||
67 | /* Recording Channel Start Register */ | |
68 | #define SIS_RECORD_START_REG 0x24 | |
69 | ||
70 | /* Recording Channel Stop Register */ | |
71 | #define SIS_RECORD_STOP_REG 0x28 | |
72 | ||
73 | /* Playback Interrupt Status Registers */ | |
74 | #define SIS_PISR_A 0x2c | |
75 | #define SIS_PISR_B 0x30 | |
76 | ||
77 | /* Recording Interrupt Status Register */ | |
78 | #define SIS_RISR 0x34 | |
79 | ||
80 | /* AC97 AC-link Playback Source Register */ | |
81 | #define SIS_AC97_PSR 0x40 | |
82 | #define SIS_AC97_PSR_MODEM_HEADSET_SRC_MIXER 0x0f000000 | |
83 | #define SIS_AC97_PSR_MODEM_LINE2_SRC_MIXER 0x00f00000 | |
84 | #define SIS_AC97_PSR_MODEM_LINE1_SRC_MIXER 0x000f0000 | |
85 | #define SIS_AC97_PSR_PCM_LFR_SRC_MIXER 0x0000f000 | |
86 | #define SIS_AC97_PSR_PCM_SURROUND_SRC_MIXER 0x00000f00 | |
87 | #define SIS_AC97_PSR_PCM_CENTER_SRC_MIXER 0x000000f0 | |
88 | #define SIS_AC97_PSR_PCM_LR_SRC_MIXER 0x0000000f | |
89 | ||
90 | /* AC97 AC-link Command Register */ | |
91 | #define SIS_AC97_CMD 0x50 | |
92 | #define SIS_AC97_CMD_DATA_MASK 0xffff0000 | |
93 | #define SIS_AC97_CMD_REG_MASK 0x0000ff00 | |
94 | #define SIS_AC97_CMD_CODEC3_READ 0x0000000d | |
95 | #define SIS_AC97_CMD_CODEC3_WRITE 0x0000000c | |
96 | #define SIS_AC97_CMD_CODEC2_READ 0x0000000b | |
97 | #define SIS_AC97_CMD_CODEC2_WRITE 0x0000000a | |
98 | #define SIS_AC97_CMD_CODEC_READ 0x00000009 | |
99 | #define SIS_AC97_CMD_CODEC_WRITE 0x00000008 | |
100 | #define SIS_AC97_CMD_CODEC_WARM_RESET 0x00000005 | |
101 | #define SIS_AC97_CMD_CODEC_COLD_RESET 0x00000004 | |
102 | #define SIS_AC97_CMD_DONE 0x00000000 | |
103 | ||
104 | /* AC97 AC-link Semaphore Register */ | |
105 | #define SIS_AC97_SEMA 0x54 | |
106 | #define SIS_AC97_SEMA_BUSY 0x00000001 | |
107 | #define SIS_AC97_SEMA_RELEASE 0x00000000 | |
108 | ||
109 | /* AC97 AC-link Status Register */ | |
110 | #define SIS_AC97_STATUS 0x58 | |
111 | #define SIS_AC97_STATUS_AUDIO_D2_INACT_SECS 0x03f00000 | |
112 | #define SIS_AC97_STATUS_MODEM_ALIVE 0x00002000 | |
113 | #define SIS_AC97_STATUS_AUDIO_ALIVE 0x00001000 | |
114 | #define SIS_AC97_STATUS_CODEC3_READY 0x00000400 | |
115 | #define SIS_AC97_STATUS_CODEC2_READY 0x00000200 | |
116 | #define SIS_AC97_STATUS_CODEC_READY 0x00000100 | |
117 | #define SIS_AC97_STATUS_WARM_RESET 0x00000080 | |
118 | #define SIS_AC97_STATUS_COLD_RESET 0x00000040 | |
119 | #define SIS_AC97_STATUS_POWERED_DOWN 0x00000020 | |
120 | #define SIS_AC97_STATUS_NORMAL 0x00000010 | |
121 | #define SIS_AC97_STATUS_READ_EXPIRED 0x00000004 | |
122 | #define SIS_AC97_STATUS_SEMAPHORE 0x00000002 | |
123 | #define SIS_AC97_STATUS_BUSY 0x00000001 | |
124 | ||
125 | /* AC97 AC-link Audio Configuration Register */ | |
126 | #define SIS_AC97_CONF 0x5c | |
127 | #define SIS_AC97_CONF_AUDIO_ALIVE 0x80000000 | |
128 | #define SIS_AC97_CONF_WARM_RESET_ENABLE 0x40000000 | |
129 | #define SIS_AC97_CONF_PR6_ENABLE 0x20000000 | |
130 | #define SIS_AC97_CONF_PR5_ENABLE 0x10000000 | |
131 | #define SIS_AC97_CONF_PR4_ENABLE 0x08000000 | |
132 | #define SIS_AC97_CONF_PR3_ENABLE 0x04000000 | |
133 | #define SIS_AC97_CONF_PR2_PR7_ENABLE 0x02000000 | |
134 | #define SIS_AC97_CONF_PR0_PR1_ENABLE 0x01000000 | |
135 | #define SIS_AC97_CONF_AUTO_PM_ENABLE 0x00800000 | |
136 | #define SIS_AC97_CONF_PCM_LFE_ENABLE 0x00080000 | |
137 | #define SIS_AC97_CONF_PCM_SURROUND_ENABLE 0x00040000 | |
138 | #define SIS_AC97_CONF_PCM_CENTER_ENABLE 0x00020000 | |
139 | #define SIS_AC97_CONF_PCM_LR_ENABLE 0x00010000 | |
140 | #define SIS_AC97_CONF_PCM_CAP_MIC_ENABLE 0x00002000 | |
141 | #define SIS_AC97_CONF_PCM_CAP_LR_ENABLE 0x00001000 | |
142 | #define SIS_AC97_CONF_PCM_CAP_MIC_FROM_CODEC3 0x00000200 | |
143 | #define SIS_AC97_CONF_PCM_CAP_LR_FROM_CODEC3 0x00000100 | |
144 | #define SIS_AC97_CONF_CODEC3_PM_VRM 0x00000080 | |
145 | #define SIS_AC97_CONF_CODEC_PM_VRM 0x00000040 | |
146 | #define SIS_AC97_CONF_CODEC3_VRA_ENABLE 0x00000020 | |
147 | #define SIS_AC97_CONF_CODEC_VRA_ENABLE 0x00000010 | |
148 | #define SIS_AC97_CONF_CODEC3_PM_EAC 0x00000008 | |
149 | #define SIS_AC97_CONF_CODEC_PM_EAC 0x00000004 | |
150 | #define SIS_AC97_CONF_CODEC3_EXISTS 0x00000002 | |
151 | #define SIS_AC97_CONF_CODEC_EXISTS 0x00000001 | |
152 | ||
153 | /* Playback Channel Sync Group registers */ | |
154 | #define SIS_PLAY_SYNC_GROUP_A 0x80 | |
155 | #define SIS_PLAY_SYNC_GROUP_B 0x84 | |
156 | #define SIS_PLAY_SYNC_GROUP_C 0x88 | |
157 | #define SIS_PLAY_SYNC_GROUP_D 0x8c | |
158 | #define SIS_MIXER_SYNC_GROUP 0x90 | |
159 | ||
160 | /* Wave Engine Config and Control Register */ | |
161 | #define SIS_WECCR 0xa0 | |
162 | #define SIS_WECCR_TESTMODE_MASK 0x00300000 | |
163 | #define SIS_WECCR_TESTMODE_NORMAL 0x00000000 | |
164 | #define SIS_WECCR_TESTMODE_BYPASS_NSO_ALPHA 0x00100000 | |
165 | #define SIS_WECCR_TESTMODE_BYPASS_FC 0x00200000 | |
166 | #define SIS_WECCR_TESTMODE_BYPASS_WOL 0x00300000 | |
167 | #define SIS_WECCR_RESONANCE_DELAY_MASK 0x00060000 | |
168 | #define SIS_WECCR_RESONANCE_DELAY_NONE 0x00000000 | |
169 | #define SIS_WECCR_RESONANCE_DELAY_FC_1F00 0x00020000 | |
170 | #define SIS_WECCR_RESONANCE_DELAY_FC_1E00 0x00040000 | |
171 | #define SIS_WECCR_RESONANCE_DELAY_FC_1C00 0x00060000 | |
172 | #define SIS_WECCR_IGNORE_CHANNEL_PARMS 0x00010000 | |
173 | #define SIS_WECCR_COMMAND_CHANNEL_ID_MASK 0x0003ff00 | |
174 | #define SIS_WECCR_COMMAND_MASK 0x00000007 | |
175 | #define SIS_WECCR_COMMAND_NONE 0x00000000 | |
176 | #define SIS_WECCR_COMMAND_DONE 0x00000000 | |
177 | #define SIS_WECCR_COMMAND_PAUSE 0x00000001 | |
178 | #define SIS_WECCR_COMMAND_TOGGLE_VEG 0x00000002 | |
179 | #define SIS_WECCR_COMMAND_TOGGLE_MEG 0x00000003 | |
180 | #define SIS_WECCR_COMMAND_TOGGLE_VEG_MEG 0x00000004 | |
181 | ||
182 | /* Wave Engine Volume Control Register */ | |
183 | #define SIS_WEVCR 0xa4 | |
184 | #define SIS_WEVCR_LEFT_MUSIC_ATTENUATION_MASK 0xff000000 | |
185 | #define SIS_WEVCR_RIGHT_MUSIC_ATTENUATION_MASK 0x00ff0000 | |
186 | #define SIS_WEVCR_LEFT_WAVE_ATTENUATION_MASK 0x0000ff00 | |
187 | #define SIS_WEVCR_RIGHT_WAVE_ATTENUATION_MASK 0x000000ff | |
188 | ||
189 | /* Wave Engine Interrupt Status Registers */ | |
190 | #define SIS_WEISR_A 0xa8 | |
191 | #define SIS_WEISR_B 0xac | |
192 | ||
193 | ||
98a1708d | 194 | /* Playback DMA parameters (parameter RAM) */ |
175859bf DD |
195 | #define SIS_PLAY_DMA_OFFSET 0x0000 |
196 | #define SIS_PLAY_DMA_SIZE 0x10 | |
197 | #define SIS_PLAY_DMA_ADDR(addr, num) \ | |
198 | ((num * SIS_PLAY_DMA_SIZE) + (addr) + SIS_PLAY_DMA_OFFSET) | |
199 | ||
200 | #define SIS_PLAY_DMA_FORMAT_CSO 0x00 | |
201 | #define SIS_PLAY_DMA_FORMAT_UNSIGNED 0x00080000 | |
202 | #define SIS_PLAY_DMA_FORMAT_8BIT 0x00040000 | |
203 | #define SIS_PLAY_DMA_FORMAT_MONO 0x00020000 | |
204 | #define SIS_PLAY_DMA_CSO_MASK 0x0000ffff | |
205 | #define SIS_PLAY_DMA_BASE 0x04 | |
206 | #define SIS_PLAY_DMA_CONTROL 0x08 | |
207 | #define SIS_PLAY_DMA_STOP_AT_SSO 0x04000000 | |
208 | #define SIS_PLAY_DMA_RELEASE 0x02000000 | |
209 | #define SIS_PLAY_DMA_LOOP 0x01000000 | |
210 | #define SIS_PLAY_DMA_INTR_AT_SSO 0x00080000 | |
211 | #define SIS_PLAY_DMA_INTR_AT_ESO 0x00040000 | |
212 | #define SIS_PLAY_DMA_INTR_AT_LEO 0x00020000 | |
213 | #define SIS_PLAY_DMA_INTR_AT_MLP 0x00010000 | |
214 | #define SIS_PLAY_DMA_LEO_MASK 0x0000ffff | |
215 | #define SIS_PLAY_DMA_SSO_ESO 0x0c | |
216 | #define SIS_PLAY_DMA_SSO_MASK 0xffff0000 | |
217 | #define SIS_PLAY_DMA_ESO_MASK 0x0000ffff | |
218 | ||
98a1708d | 219 | /* Capture DMA parameters (parameter RAM) */ |
175859bf DD |
220 | #define SIS_CAPTURE_DMA_OFFSET 0x0800 |
221 | #define SIS_CAPTURE_DMA_SIZE 0x10 | |
222 | #define SIS_CAPTURE_DMA_ADDR(addr, num) \ | |
223 | ((num * SIS_CAPTURE_DMA_SIZE) + (addr) + SIS_CAPTURE_DMA_OFFSET) | |
224 | ||
225 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_0 0 | |
226 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_1 1 | |
227 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_2 2 | |
228 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_3 3 | |
229 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_4 4 | |
230 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_5 5 | |
231 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_6 6 | |
232 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_7 7 | |
233 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_8 8 | |
234 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_9 9 | |
235 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_10 10 | |
236 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_11 11 | |
237 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_12 12 | |
238 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_13 13 | |
239 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_14 14 | |
240 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_15 15 | |
241 | #define SIS_CAPTURE_CHAN_AC97_PCM_IN 16 | |
242 | #define SIS_CAPTURE_CHAN_AC97_MIC_IN 17 | |
243 | #define SIS_CAPTURE_CHAN_AC97_LINE1_IN 18 | |
244 | #define SIS_CAPTURE_CHAN_AC97_LINE2_IN 19 | |
245 | #define SIS_CAPTURE_CHAN_AC97_HANDSE_IN 20 | |
246 | ||
247 | #define SIS_CAPTURE_DMA_FORMAT_CSO 0x00 | |
248 | #define SIS_CAPTURE_DMA_MONO_MODE_MASK 0xc0000000 | |
249 | #define SIS_CAPTURE_DMA_MONO_MODE_AVG 0x00000000 | |
250 | #define SIS_CAPTURE_DMA_MONO_MODE_LEFT 0x40000000 | |
251 | #define SIS_CAPTURE_DMA_MONO_MODE_RIGHT 0x80000000 | |
252 | #define SIS_CAPTURE_DMA_FORMAT_UNSIGNED 0x00080000 | |
253 | #define SIS_CAPTURE_DMA_FORMAT_8BIT 0x00040000 | |
254 | #define SIS_CAPTURE_DMA_FORMAT_MONO 0x00020000 | |
255 | #define SIS_CAPTURE_DMA_CSO_MASK 0x0000ffff | |
256 | #define SIS_CAPTURE_DMA_BASE 0x04 | |
257 | #define SIS_CAPTURE_DMA_CONTROL 0x08 | |
258 | #define SIS_CAPTURE_DMA_STOP_AT_SSO 0x04000000 | |
259 | #define SIS_CAPTURE_DMA_RELEASE 0x02000000 | |
260 | #define SIS_CAPTURE_DMA_LOOP 0x01000000 | |
261 | #define SIS_CAPTURE_DMA_INTR_AT_LEO 0x00020000 | |
262 | #define SIS_CAPTURE_DMA_INTR_AT_MLP 0x00010000 | |
263 | #define SIS_CAPTURE_DMA_LEO_MASK 0x0000ffff | |
264 | #define SIS_CAPTURE_DMA_RESERVED 0x0c | |
265 | ||
266 | ||
267 | /* Mixer routing list start pointer (parameter RAM) */ | |
268 | #define SIS_MIXER_START_OFFSET 0x1000 | |
269 | #define SIS_MIXER_START_SIZE 0x04 | |
270 | #define SIS_MIXER_START_ADDR(addr, num) \ | |
271 | ((num * SIS_MIXER_START_SIZE) + (addr) + SIS_MIXER_START_OFFSET) | |
272 | ||
273 | #define SIS_MIXER_START_MASK 0x0000007f | |
274 | ||
275 | /* Mixer routing table (parameter RAM) */ | |
276 | #define SIS_MIXER_OFFSET 0x1400 | |
277 | #define SIS_MIXER_SIZE 0x04 | |
278 | #define SIS_MIXER_ADDR(addr, num) \ | |
279 | ((num * SIS_MIXER_SIZE) + (addr) + SIS_MIXER_OFFSET) | |
280 | ||
281 | #define SIS_MIXER_RIGHT_ATTENUTATION_MASK 0xff000000 | |
282 | #define SIS_MIXER_RIGHT_NO_ATTEN 0xff000000 | |
283 | #define SIS_MIXER_LEFT_ATTENUTATION_MASK 0x00ff0000 | |
284 | #define SIS_MIXER_LEFT_NO_ATTEN 0x00ff0000 | |
285 | #define SIS_MIXER_NEXT_ENTRY_MASK 0x00007f00 | |
286 | #define SIS_MIXER_NEXT_ENTRY_NONE 0x00000000 | |
287 | #define SIS_MIXER_DEST_MASK 0x0000007f | |
288 | #define SIS_MIXER_DEST_0 0x00000020 | |
289 | #define SIS_MIXER_DEST_1 0x00000021 | |
290 | #define SIS_MIXER_DEST_2 0x00000022 | |
291 | #define SIS_MIXER_DEST_3 0x00000023 | |
292 | #define SIS_MIXER_DEST_4 0x00000024 | |
293 | #define SIS_MIXER_DEST_5 0x00000025 | |
294 | #define SIS_MIXER_DEST_6 0x00000026 | |
295 | #define SIS_MIXER_DEST_7 0x00000027 | |
296 | #define SIS_MIXER_DEST_8 0x00000028 | |
297 | #define SIS_MIXER_DEST_9 0x00000029 | |
298 | #define SIS_MIXER_DEST_10 0x0000002a | |
299 | #define SIS_MIXER_DEST_11 0x0000002b | |
300 | #define SIS_MIXER_DEST_12 0x0000002c | |
301 | #define SIS_MIXER_DEST_13 0x0000002d | |
302 | #define SIS_MIXER_DEST_14 0x0000002e | |
303 | #define SIS_MIXER_DEST_15 0x0000002f | |
304 | ||
305 | /* Wave Engine Control Parameters (parameter RAM) */ | |
306 | #define SIS_WAVE_OFFSET 0x2000 | |
307 | #define SIS_WAVE_SIZE 0x40 | |
308 | #define SIS_WAVE_ADDR(addr, num) \ | |
309 | ((num * SIS_WAVE_SIZE) + (addr) + SIS_WAVE_OFFSET) | |
310 | ||
311 | #define SIS_WAVE_GENERAL 0x00 | |
312 | #define SIS_WAVE_GENERAL_WAVE_VOLUME 0x80000000 | |
313 | #define SIS_WAVE_GENERAL_MUSIC_VOLUME 0x00000000 | |
314 | #define SIS_WAVE_GENERAL_VOLUME_MASK 0x7f000000 | |
315 | #define SIS_WAVE_GENERAL_ARTICULATION 0x04 | |
316 | #define SIS_WAVE_GENERAL_ARTICULATION_DELTA_MASK 0x3fff0000 | |
317 | #define SIS_WAVE_ARTICULATION 0x08 | |
318 | #define SIS_WAVE_TIMER 0x0c | |
319 | #define SIS_WAVE_GENERATOR 0x10 | |
320 | #define SIS_WAVE_CHANNEL_CONTROL 0x14 | |
321 | #define SIS_WAVE_CHANNEL_CONTROL_FIRST_SAMPLE 0x80000000 | |
322 | #define SIS_WAVE_CHANNEL_CONTROL_AMP_ENABLE 0x40000000 | |
323 | #define SIS_WAVE_CHANNEL_CONTROL_FILTER_ENABLE 0x20000000 | |
324 | #define SIS_WAVE_CHANNEL_CONTROL_INTERPOLATE_ENABLE 0x10000000 | |
325 | #define SIS_WAVE_LFO_EG_CONTROL 0x18 | |
326 | #define SIS_WAVE_LFO_EG_CONTROL_2 0x1c | |
327 | #define SIS_WAVE_LFO_EG_CONTROL_3 0x20 | |
328 | #define SIS_WAVE_LFO_EG_CONTROL_4 0x24 | |
329 | ||
330 | #endif /* __sis7019_h__ */ |