[mirror_ubuntu-bionic-kernel.git] / sound / soc / at32 / playpaq_wm8510.c

/* sound/soc/at32/playpaq_wm8510.c
 * ASoC machine driver for PlayPaq using WM8510 codec
 *
 * Copyright (C) 2008 Long Range Systems
 *    Geoffrey Wossum <gwossum@acm.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This code is largely inspired by sound/soc/at91/eti_b1_wm8731.c
 *
 * NOTE: If you don't have the AT32 enhanced portmux configured (which
 * isn't currently in the mainline or Atmel patched kernel), you will
 * need to set the MCLK pin (PA30) to peripheral A in your board initialization
 * code.  Something like:
 *	at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
 *
 */

/* #define DEBUG */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>

#include <mach/at32ap700x.h>
#include <mach/portmux.h>

#include "../codecs/wm8510.h"
#include "at32-pcm.h"
#include "at32-ssc.h"


/*-------------------------------------------------------------------------*\
 * constants
\*-------------------------------------------------------------------------*/
#define MCLK_PIN		GPIO_PIN_PA(30)
#define MCLK_PERIPH		GPIO_PERIPH_A


/*-------------------------------------------------------------------------*\
 * data types
\*-------------------------------------------------------------------------*/
/* SSC clocking data */
struct ssc_clock_data {
	/* CMR div */
	unsigned int cmr_div;

	/* Frame period (as needed by xCMR.PERIOD) */
	unsigned int period;

	/* The SSC clock rate these settings where calculated for */
	unsigned long ssc_rate;
};


/*-------------------------------------------------------------------------*\
 * module data
\*-------------------------------------------------------------------------*/
static struct clk *_gclk0;
static struct clk *_pll0;

#define CODEC_CLK (_gclk0)


/*-------------------------------------------------------------------------*\
 * Sound SOC operations
\*-------------------------------------------------------------------------*/
#if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
static struct ssc_clock_data playpaq_wm8510_calc_ssc_clock(
	struct snd_pcm_hw_params *params,
	struct snd_soc_dai *cpu_dai)
{
	struct at32_ssc_info *ssc_p = cpu_dai->private_data;
	struct ssc_device *ssc = ssc_p->ssc;
	struct ssc_clock_data cd;
	unsigned int rate, width_bits, channels;
	unsigned int bitrate, ssc_div;
	unsigned actual_rate;


	/*
	 * Figure out required bitrate
	 */
	rate = params_rate(params);
	channels = params_channels(params);
	width_bits = snd_pcm_format_physical_width(params_format(params));
	bitrate = rate * width_bits * channels;


	/*
	 * Figure out required SSC divider and period for required bitrate
	 */
	cd.ssc_rate = clk_get_rate(ssc->clk);
	ssc_div = cd.ssc_rate / bitrate;
	cd.cmr_div = ssc_div / 2;
	if (ssc_div & 1) {
		/* round cmr_div up */
		cd.cmr_div++;
	}
	cd.period = width_bits - 1;


	/*
	 * Find actual rate, compare to requested rate
	 */
	actual_rate = (cd.ssc_rate / (cd.cmr_div * 2)) / (2 * (cd.period + 1));
	pr_debug("playpaq_wm8510: Request rate = %d, actual rate = %d\n",
		 rate, actual_rate);


	return cd;
}
#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */


static int playpaq_wm8510_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
	struct at32_ssc_info *ssc_p = cpu_dai->private_data;
	struct ssc_device *ssc = ssc_p->ssc;
	unsigned int pll_out = 0, bclk = 0, mclk_div = 0;
	int ret;


	/* Due to difficulties with getting the correct clocks from the AT32's
	 * PLL0, we're going to let the CODEC be in charge of all the clocks
	 */
#if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	const unsigned int fmt = (SND_SOC_DAIFMT_I2S |
				  SND_SOC_DAIFMT_NB_NF |
				  SND_SOC_DAIFMT_CBM_CFM);
#else
	struct ssc_clock_data cd;
	const unsigned int fmt = (SND_SOC_DAIFMT_I2S |
				  SND_SOC_DAIFMT_NB_NF |
				  SND_SOC_DAIFMT_CBS_CFS);
#endif

	if (ssc == NULL) {
		pr_warning("playpaq_wm8510_hw_params: ssc is NULL!\n");
		return -EINVAL;
	}


	/*
	 * Figure out PLL and BCLK dividers for WM8510
	 */
	switch (params_rate(params)) {
	case 48000:
		pll_out = 12288000;
		mclk_div = WM8510_MCLKDIV_1;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 44100:
		pll_out = 11289600;
		mclk_div = WM8510_MCLKDIV_1;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 22050:
		pll_out = 11289600;
		mclk_div = WM8510_MCLKDIV_2;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 16000:
		pll_out = 12288000;
		mclk_div = WM8510_MCLKDIV_3;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 11025:
		pll_out = 11289600;
		mclk_div = WM8510_MCLKDIV_4;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 8000:
		pll_out = 12288000;
		mclk_div = WM8510_MCLKDIV_6;
		bclk = WM8510_BCLKDIV_8;
		break;

	default:
		pr_warning("playpaq_wm8510: Unsupported sample rate %d\n",
			   params_rate(params));
		return -EINVAL;
	}


	/*
	 * set CPU and CODEC DAI configuration
	 */
	ret = snd_soc_dai_set_fmt(codec_dai, fmt);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: "
			   "Failed to set CODEC DAI format (%d)\n",
			   ret);
		return ret;
	}
	ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: "
			   "Failed to set CPU DAI format (%d)\n",
			   ret);
		return ret;
	}


	/*
	 * Set CPU clock configuration
	 */
#if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	cd = playpaq_wm8510_calc_ssc_clock(params, cpu_dai);
	pr_debug("playpaq_wm8510: cmr_div = %d, period = %d\n",
		 cd.cmr_div, cd.period);
	ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_CMR_DIV, cd.cmr_div);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: Failed to set CPU CMR_DIV (%d)\n",
			   ret);
		return ret;
	}
	ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_TCMR_PERIOD,
					  cd.period);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: "
			   "Failed to set CPU transmit period (%d)\n",
			   ret);
		return ret;
	}
#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */


	/*
	 * Set CODEC clock configuration
	 */
	pr_debug("playpaq_wm8510: "
		 "pll_in = %ld, pll_out = %u, bclk = %x, mclk = %x\n",
		 clk_get_rate(CODEC_CLK), pll_out, bclk, mclk_div);


#if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_BCLKDIV, bclk);
	if (ret < 0) {
		pr_warning
		    ("playpaq_wm8510: Failed to set CODEC DAI BCLKDIV (%d)\n",
		     ret);
		return ret;
	}
#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */


	ret = snd_soc_dai_set_pll(codec_dai, 0,
					 clk_get_rate(CODEC_CLK), pll_out);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: Failed to set CODEC DAI PLL (%d)\n",
			   ret);
		return ret;
	}


	ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_MCLKDIV, mclk_div);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: Failed to set CODEC MCLKDIV (%d)\n",
			   ret);
		return ret;
	}


	return 0;
}


static struct snd_soc_ops playpaq_wm8510_ops = {
	.hw_params = playpaq_wm8510_hw_params,
};


static const struct snd_soc_dapm_widget playpaq_dapm_widgets[] = {
	SND_SOC_DAPM_MIC("Int Mic", NULL),
	SND_SOC_DAPM_SPK("Ext Spk", NULL),
};


static const char *intercon[][3] = {
	/* speaker connected to SPKOUT */
	{"Ext Spk", NULL, "SPKOUTP"},
	{"Ext Spk", NULL, "SPKOUTN"},

	{"Mic Bias", NULL, "Int Mic"},
	{"MICN", NULL, "Mic Bias"},
	{"MICP", NULL, "Mic Bias"},

	/* Terminator */
	{NULL, NULL, NULL},
};


static int playpaq_wm8510_init(struct snd_soc_codec *codec)
{
	int i;

	/*
	 * Add DAPM widgets
	 */
	for (i = 0; i < ARRAY_SIZE(playpaq_dapm_widgets); i++)
		snd_soc_dapm_new_control(codec, &playpaq_dapm_widgets[i]);


	/*
	 * Setup audio path interconnects
	 */
	for (i = 0; intercon[i][0] != NULL; i++) {
		snd_soc_dapm_connect_input(codec,
					   intercon[i][0],
					   intercon[i][1], intercon[i][2]);
	}


	/* always connected pins */
	snd_soc_dapm_enable_pin(codec, "Int Mic");
	snd_soc_dapm_enable_pin(codec, "Ext Spk");
	snd_soc_dapm_sync(codec);


	/* Make CSB show PLL rate */
	snd_soc_dai_set_clkdiv(codec->dai, WM8510_OPCLKDIV,
				       WM8510_OPCLKDIV_1 | 4);

	return 0;
}


static struct snd_soc_dai_link playpaq_wm8510_dai = {
	.name = "WM8510",
	.stream_name = "WM8510 PCM",
	.cpu_dai = &at32_ssc_dai[0],
	.codec_dai = &wm8510_dai,
	.init = playpaq_wm8510_init,
	.ops = &playpaq_wm8510_ops,
};


static struct snd_soc_machine snd_soc_machine_playpaq = {
	.name = "LRS_PlayPaq_WM8510",
	.dai_link = &playpaq_wm8510_dai,
	.num_links = 1,
};


static struct wm8510_setup_data playpaq_wm8510_setup = {
	.i2c_bus = 0,
	.i2c_address = 0x1a,
};


static struct snd_soc_device playpaq_wm8510_snd_devdata = {
	.machine = &snd_soc_machine_playpaq,
	.platform = &at32_soc_platform,
	.codec_dev = &soc_codec_dev_wm8510,
	.codec_data = &playpaq_wm8510_setup,
};

static struct platform_device *playpaq_snd_device;


static int __init playpaq_asoc_init(void)
{
	int ret = 0;
	struct at32_ssc_info *ssc_p = playpaq_wm8510_dai.cpu_dai->private_data;
	struct ssc_device *ssc = NULL;


	/*
	 * Request SSC device
	 */
	ssc = ssc_request(0);
	if (IS_ERR(ssc)) {
		ret = PTR_ERR(ssc);
		ssc = NULL;
		goto err_ssc;
	}
	ssc_p->ssc = ssc;


	/*
	 * Configure MCLK for WM8510
	 */
	_gclk0 = clk_get(NULL, "gclk0");
	if (IS_ERR(_gclk0)) {
		_gclk0 = NULL;
		goto err_gclk0;
	}
	_pll0 = clk_get(NULL, "pll0");
	if (IS_ERR(_pll0)) {
		_pll0 = NULL;
		goto err_pll0;
	}
	if (clk_set_parent(_gclk0, _pll0)) {
		pr_warning("snd-soc-playpaq: "
			   "Failed to set PLL0 as parent for DAC clock\n");
		goto err_set_clk;
	}
	clk_set_rate(CODEC_CLK, 12000000);
	clk_enable(CODEC_CLK);

#if defined CONFIG_AT32_ENHANCED_PORTMUX
	at32_select_periph(MCLK_PIN, MCLK_PERIPH, 0);
#endif


	/*
	 * Create and register platform device
	 */
	playpaq_snd_device = platform_device_alloc("soc-audio", 0);
	if (playpaq_snd_device == NULL) {
		ret = -ENOMEM;
		goto err_device_alloc;
	}

	platform_set_drvdata(playpaq_snd_device, &playpaq_wm8510_snd_devdata);
	playpaq_wm8510_snd_devdata.dev = &playpaq_snd_device->dev;

	ret = platform_device_add(playpaq_snd_device);
	if (ret) {
		pr_warning("playpaq_wm8510: platform_device_add failed (%d)\n",
			   ret);
		goto err_device_add;
	}

	return 0;


err_device_add:
	if (playpaq_snd_device != NULL) {
		platform_device_put(playpaq_snd_device);
		playpaq_snd_device = NULL;
	}
err_device_alloc:
err_set_clk:
	if (_pll0 != NULL) {
		clk_put(_pll0);
		_pll0 = NULL;
	}
err_pll0:
	if (_gclk0 != NULL) {
		clk_put(_gclk0);
		_gclk0 = NULL;
	}
err_gclk0:
	if (ssc != NULL) {
		ssc_free(ssc);
		ssc = NULL;
	}
err_ssc:
	return ret;
}


static void __exit playpaq_asoc_exit(void)
{
	struct at32_ssc_info *ssc_p = playpaq_wm8510_dai.cpu_dai->private_data;
	struct ssc_device *ssc;

	if (ssc_p != NULL) {
		ssc = ssc_p->ssc;
		if (ssc != NULL)
			ssc_free(ssc);
		ssc_p->ssc = NULL;
	}

	if (_gclk0 != NULL) {
		clk_put(_gclk0);
		_gclk0 = NULL;
	}
	if (_pll0 != NULL) {
		clk_put(_pll0);
		_pll0 = NULL;
	}

#if defined CONFIG_AT32_ENHANCED_PORTMUX
	at32_free_pin(MCLK_PIN);
#endif

	platform_device_unregister(playpaq_snd_device);
	playpaq_snd_device = NULL;
}

module_init(playpaq_asoc_init);
module_exit(playpaq_asoc_exit);

MODULE_AUTHOR("Geoffrey Wossum <gwossum@acm.org>");
MODULE_DESCRIPTION("ASoC machine driver for LRS PlayPaq");
MODULE_LICENSE("GPL");
Commit	Line	Data
9aaca968 GW	1	/* sound/soc/at32/playpaq_wm8510.c
	2	* ASoC machine driver for PlayPaq using WM8510 codec
	3	*
	4	* Copyright (C) 2008 Long Range Systems
	5	* Geoffrey Wossum <gwossum@acm.org>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This code is largely inspired by sound/soc/at91/eti_b1_wm8731.c
	12	*
	13	* NOTE: If you don't have the AT32 enhanced portmux configured (which
	14	* isn't currently in the mainline or Atmel patched kernel), you will
	15	* need to set the MCLK pin (PA30) to peripheral A in your board initialization
	16	* code. Something like:
	17	* at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
	18	*
	19	*/
	20
	21	/* #define DEBUG */
	22
	23	#include <linux/module.h>
	24	#include <linux/moduleparam.h>
	25	#include <linux/version.h>
	26	#include <linux/kernel.h>
	27	#include <linux/errno.h>
	28	#include <linux/clk.h>
	29	#include <linux/timer.h>
	30	#include <linux/interrupt.h>
	31	#include <linux/platform_device.h>
	32
	33	#include <sound/core.h>
	34	#include <sound/pcm.h>
	35	#include <sound/pcm_params.h>
	36	#include <sound/soc.h>
	37	#include <sound/soc-dapm.h>
	38
a09e64fb RK	39	#include <mach/at32ap700x.h>
a09e64fb RK	40	#include <mach/portmux.h>
9aaca968 GW	41
	42	#include "../codecs/wm8510.h"
	43	#include "at32-pcm.h"
	44	#include "at32-ssc.h"
	45
	46
	47	/-------------------------------------------------------------------------\
	48	* constants
	49	\-------------------------------------------------------------------------/
	50	#define MCLK_PIN GPIO_PIN_PA(30)
	51	#define MCLK_PERIPH GPIO_PERIPH_A
	52
	53
	54	/-------------------------------------------------------------------------\
	55	* data types
	56	\-------------------------------------------------------------------------/
	57	/* SSC clocking data */
	58	struct ssc_clock_data {
	59	/* CMR div */
	60	unsigned int cmr_div;
	61
	62	/* Frame period (as needed by xCMR.PERIOD) */
	63	unsigned int period;
	64
	65	/* The SSC clock rate these settings where calculated for */
	66	unsigned long ssc_rate;
	67	};
	68
	69
	70	/-------------------------------------------------------------------------\
	71	* module data
	72	\-------------------------------------------------------------------------/
	73	static struct clk *_gclk0;
	74	static struct clk *_pll0;
	75
	76	#define CODEC_CLK (_gclk0)
	77
	78
	79	/-------------------------------------------------------------------------\
	80	* Sound SOC operations
	81	\-------------------------------------------------------------------------/
	82	#if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	83	static struct ssc_clock_data playpaq_wm8510_calc_ssc_clock(
	84	struct snd_pcm_hw_params *params,
453ba20b	85	struct snd_soc_dai *cpu_dai)
9aaca968 GW	86	{
	87	struct at32_ssc_info *ssc_p = cpu_dai->private_data;
	88	struct ssc_device *ssc = ssc_p->ssc;
	89	struct ssc_clock_data cd;
	90	unsigned int rate, width_bits, channels;
	91	unsigned int bitrate, ssc_div;
	92	unsigned actual_rate;
	93
	94
	95	/*
	96	* Figure out required bitrate
	97	*/
	98	rate = params_rate(params);
	99	channels = params_channels(params);
	100	width_bits = snd_pcm_format_physical_width(params_format(params));
	101	bitrate = rate * width_bits * channels;
	102
	103
	104	/*
	105	* Figure out required SSC divider and period for required bitrate
	106	*/
	107	cd.ssc_rate = clk_get_rate(ssc->clk);
	108	ssc_div = cd.ssc_rate / bitrate;
	109	cd.cmr_div = ssc_div / 2;
	110	if (ssc_div & 1) {
	111	/* round cmr_div up */
	112	cd.cmr_div++;
	113	}
	114	cd.period = width_bits - 1;
	115
	116
	117	/*
	118	* Find actual rate, compare to requested rate
	119	*/
	120	actual_rate = (cd.ssc_rate / (cd.cmr_div * 2)) / (2 * (cd.period + 1));
	121	pr_debug("playpaq_wm8510: Request rate = %d, actual rate = %d\n",
	122	rate, actual_rate);
	123
	124
	125	return cd;
	126	}
	127	#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
	128
	129
	130
	131	static int playpaq_wm8510_hw_params(struct snd_pcm_substream *substream,
	132	struct snd_pcm_hw_params *params)
	133	{
	134	struct snd_soc_pcm_runtime *rtd = substream->private_data;
453ba20b LG	135	struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
453ba20b LG	136	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
9aaca968 GW	137	struct at32_ssc_info *ssc_p = cpu_dai->private_data;
	138	struct ssc_device *ssc = ssc_p->ssc;
	139	unsigned int pll_out = 0, bclk = 0, mclk_div = 0;
	140	int ret;
	141
	142
	143	/* Due to difficulties with getting the correct clocks from the AT32's
	144	* PLL0, we're going to let the CODEC be in charge of all the clocks
	145	*/
	146	#if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	147	const unsigned int fmt = (SND_SOC_DAIFMT_I2S \|
	148	SND_SOC_DAIFMT_NB_NF \|
	149	SND_SOC_DAIFMT_CBM_CFM);
	150	#else
	151	struct ssc_clock_data cd;
	152	const unsigned int fmt = (SND_SOC_DAIFMT_I2S \|
	153	SND_SOC_DAIFMT_NB_NF \|
	154	SND_SOC_DAIFMT_CBS_CFS);
	155	#endif
	156
	157	if (ssc == NULL) {
	158	pr_warning("playpaq_wm8510_hw_params: ssc is NULL!\n");
	159	return -EINVAL;
	160	}
	161
	162
	163	/*
	164	* Figure out PLL and BCLK dividers for WM8510
	165	*/
	166	switch (params_rate(params)) {
	167	case 48000:
	168	pll_out = 12288000;
	169	mclk_div = WM8510_MCLKDIV_1;
	170	bclk = WM8510_BCLKDIV_8;
	171	break;
	172
	173	case 44100:
	174	pll_out = 11289600;
	175	mclk_div = WM8510_MCLKDIV_1;
	176	bclk = WM8510_BCLKDIV_8;
	177	break;
	178
	179	case 22050:
	180	pll_out = 11289600;
	181	mclk_div = WM8510_MCLKDIV_2;
	182	bclk = WM8510_BCLKDIV_8;
	183	break;
	184
	185	case 16000:
	186	pll_out = 12288000;
	187	mclk_div = WM8510_MCLKDIV_3;
	188	bclk = WM8510_BCLKDIV_8;
	189	break;
	190
	191	case 11025:
	192	pll_out = 11289600;
	193	mclk_div = WM8510_MCLKDIV_4;
	194	bclk = WM8510_BCLKDIV_8;
	195	break;
	196
	197	case 8000:
	198	pll_out = 12288000;
	199	mclk_div = WM8510_MCLKDIV_6;
	200	bclk = WM8510_BCLKDIV_8;
201	break;
202
203	default:
204	pr_warning("playpaq_wm8510: Unsupported sample rate %d\n",
205	params_rate(params));
206	return -EINVAL;
207	}
208
209
210	/*
211	* set CPU and CODEC DAI configuration
212	*/
64105cfd	213	ret = snd_soc_dai_set_fmt(codec_dai, fmt);
9aaca968 GW	214	if (ret < 0) {
	215	pr_warning("playpaq_wm8510: "
	216	"Failed to set CODEC DAI format (%d)\n",
	217	ret);
	218	return ret;
	219	}
64105cfd	220	ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
9aaca968 GW	221	if (ret < 0) {
	222	pr_warning("playpaq_wm8510: "
	223	"Failed to set CPU DAI format (%d)\n",
	224	ret);
	225	return ret;
	226	}
	227
	228
	229	/*
	230	* Set CPU clock configuration
	231	*/
	232	#if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	233	cd = playpaq_wm8510_calc_ssc_clock(params, cpu_dai);
	234	pr_debug("playpaq_wm8510: cmr_div = %d, period = %d\n",
	235	cd.cmr_div, cd.period);
64105cfd	236	ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_CMR_DIV, cd.cmr_div);
9aaca968 GW	237	if (ret < 0) {
	238	pr_warning("playpaq_wm8510: Failed to set CPU CMR_DIV (%d)\n",
	239	ret);
	240	return ret;
	241	}
64105cfd	242	ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_TCMR_PERIOD,
9aaca968 GW	243	cd.period);
	244	if (ret < 0) {
	245	pr_warning("playpaq_wm8510: "
	246	"Failed to set CPU transmit period (%d)\n",
	247	ret);
	248	return ret;
	249	}
	250	#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
	251
	252
	253	/*
	254	* Set CODEC clock configuration
	255	*/
	256	pr_debug("playpaq_wm8510: "
	257	"pll_in = %ld, pll_out = %u, bclk = %x, mclk = %x\n",
	258	clk_get_rate(CODEC_CLK), pll_out, bclk, mclk_div);
	259
	260
	261	#if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
64105cfd	262	ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_BCLKDIV, bclk);
9aaca968 GW	263	if (ret < 0) {
	264	pr_warning
	265	("playpaq_wm8510: Failed to set CODEC DAI BCLKDIV (%d)\n",
	266	ret);
	267	return ret;
	268	}
	269	#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
	270
	271
64105cfd	272	ret = snd_soc_dai_set_pll(codec_dai, 0,
9aaca968 GW	273	clk_get_rate(CODEC_CLK), pll_out);
	274	if (ret < 0) {
	275	pr_warning("playpaq_wm8510: Failed to set CODEC DAI PLL (%d)\n",
	276	ret);
	277	return ret;
	278	}
	279
	280
64105cfd	281	ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_MCLKDIV, mclk_div);
9aaca968 GW	282	if (ret < 0) {
	283	pr_warning("playpaq_wm8510: Failed to set CODEC MCLKDIV (%d)\n",
	284	ret);
	285	return ret;
	286	}
	287
	288
	289	return 0;
	290	}
	291
	292
	293
	294	static struct snd_soc_ops playpaq_wm8510_ops = {
	295	.hw_params = playpaq_wm8510_hw_params,
	296	};
	297
	298
	299
	300	static const struct snd_soc_dapm_widget playpaq_dapm_widgets[] = {
	301	SND_SOC_DAPM_MIC("Int Mic", NULL),
	302	SND_SOC_DAPM_SPK("Ext Spk", NULL),
	303	};
	304
	305
	306
	307	static const char *intercon[][3] = {
	308	/* speaker connected to SPKOUT */
	309	{"Ext Spk", NULL, "SPKOUTP"},
	310	{"Ext Spk", NULL, "SPKOUTN"},
	311
	312	{"Mic Bias", NULL, "Int Mic"},
	313	{"MICN", NULL, "Mic Bias"},
	314	{"MICP", NULL, "Mic Bias"},
	315
	316	/* Terminator */
	317	{NULL, NULL, NULL},
	318	};
	319
	320
	321
	322	static int playpaq_wm8510_init(struct snd_soc_codec *codec)
	323	{
	324	int i;
	325
	326	/*
	327	* Add DAPM widgets
	328	*/
	329	for (i = 0; i < ARRAY_SIZE(playpaq_dapm_widgets); i++)
	330	snd_soc_dapm_new_control(codec, &playpaq_dapm_widgets[i]);
	331
	332
	333
	334	/*
	335	* Setup audio path interconnects
	336	*/
	337	for (i = 0; intercon[i][0] != NULL; i++) {
	338	snd_soc_dapm_connect_input(codec,
	339	intercon[i][0],
	340	intercon[i][1], intercon[i][2]);
	341	}
	342
	343
6f48413d LG	344	/* always connected pins */
	345	snd_soc_dapm_enable_pin(codec, "Int Mic");
	346	snd_soc_dapm_enable_pin(codec, "Ext Spk");
	347	snd_soc_dapm_sync(codec);
9aaca968 GW	348
	349
	350
	351	/* Make CSB show PLL rate */
6f48413d	352	snd_soc_dai_set_clkdiv(codec->dai, WM8510_OPCLKDIV,
9aaca968 GW	353	WM8510_OPCLKDIV_1 \| 4);
	354
	355	return 0;
	356	}
	357
	358
	359
	360	static struct snd_soc_dai_link playpaq_wm8510_dai = {
	361	.name = "WM8510",
	362	.stream_name = "WM8510 PCM",
	363	.cpu_dai = &at32_ssc_dai[0],
	364	.codec_dai = &wm8510_dai,
	365	.init = playpaq_wm8510_init,
	366	.ops = &playpaq_wm8510_ops,
	367	};
	368
	369
	370
	371	static struct snd_soc_machine snd_soc_machine_playpaq = {
	372	.name = "LRS_PlayPaq_WM8510",
	373	.dai_link = &playpaq_wm8510_dai,
	374	.num_links = 1,
	375	};
	376
	377
	378
	379	static struct wm8510_setup_data playpaq_wm8510_setup = {
41759c2e	380	.i2c_bus = 0,
9aaca968 GW	381	.i2c_address = 0x1a,
	382	};
	383
	384
	385
	386	static struct snd_soc_device playpaq_wm8510_snd_devdata = {
	387	.machine = &snd_soc_machine_playpaq,
	388	.platform = &at32_soc_platform,
	389	.codec_dev = &soc_codec_dev_wm8510,
	390	.codec_data = &playpaq_wm8510_setup,
	391	};
	392
	393	static struct platform_device *playpaq_snd_device;
	394
	395
	396	static int __init playpaq_asoc_init(void)
	397	{
	398	int ret = 0;
	399	struct at32_ssc_info *ssc_p = playpaq_wm8510_dai.cpu_dai->private_data;
	400	struct ssc_device *ssc = NULL;
	401
	402
	403	/*
	404	* Request SSC device
	405	*/
	406	ssc = ssc_request(0);
	407	if (IS_ERR(ssc)) {
	408	ret = PTR_ERR(ssc);
	409	ssc = NULL;
	410	goto err_ssc;
	411	}
	412	ssc_p->ssc = ssc;
	413
	414
	415	/*
	416	* Configure MCLK for WM8510
	417	*/
	418	_gclk0 = clk_get(NULL, "gclk0");
	419	if (IS_ERR(_gclk0)) {
	420	_gclk0 = NULL;
	421	goto err_gclk0;
	422	}
	423	_pll0 = clk_get(NULL, "pll0");
	424	if (IS_ERR(_pll0)) {
	425	_pll0 = NULL;
	426	goto err_pll0;
	427	}
	428	if (clk_set_parent(_gclk0, _pll0)) {
	429	pr_warning("snd-soc-playpaq: "
	430	"Failed to set PLL0 as parent for DAC clock\n");
	431	goto err_set_clk;
	432	}
	433	clk_set_rate(CODEC_CLK, 12000000);
	434	clk_enable(CODEC_CLK);
	435
	436	#if defined CONFIG_AT32_ENHANCED_PORTMUX
	437	at32_select_periph(MCLK_PIN, MCLK_PERIPH, 0);
	438	#endif
	439
	440
	441	/*
	442	* Create and register platform device
	443	*/
	444	playpaq_snd_device = platform_device_alloc("soc-audio", 0);
445	if (playpaq_snd_device == NULL) {
446	ret = -ENOMEM;
447	goto err_device_alloc;
448	}
449
450	platform_set_drvdata(playpaq_snd_device, &playpaq_wm8510_snd_devdata);
451	playpaq_wm8510_snd_devdata.dev = &playpaq_snd_device->dev;
452
453	ret = platform_device_add(playpaq_snd_device);
454	if (ret) {
455	pr_warning("playpaq_wm8510: platform_device_add failed (%d)\n",
456	ret);
457	goto err_device_add;
458	}
459
460	return 0;
461
462
463	err_device_add:
464	if (playpaq_snd_device != NULL) {
465	platform_device_put(playpaq_snd_device);
466	playpaq_snd_device = NULL;
467	}
468	err_device_alloc:
469	err_set_clk:
470	if (_pll0 != NULL) {
471	clk_put(_pll0);
472	_pll0 = NULL;
473	}
474	err_pll0:
475	if (_gclk0 != NULL) {
476	clk_put(_gclk0);
477	_gclk0 = NULL;
478	}
479	err_gclk0:
480	if (ssc != NULL) {
481	ssc_free(ssc);
482	ssc = NULL;
483	}
484	err_ssc:
485	return ret;
486	}
487
488
489	static void __exit playpaq_asoc_exit(void)
490	{
491	struct at32_ssc_info *ssc_p = playpaq_wm8510_dai.cpu_dai->private_data;
492	struct ssc_device *ssc;
493
494	if (ssc_p != NULL) {
495	ssc = ssc_p->ssc;
496	if (ssc != NULL)
497	ssc_free(ssc);
498	ssc_p->ssc = NULL;
499	}
500
501	if (_gclk0 != NULL) {
502	clk_put(_gclk0);
503	_gclk0 = NULL;
504	}
505	if (_pll0 != NULL) {
506	clk_put(_pll0);
507	_pll0 = NULL;
508	}
509
510	#if defined CONFIG_AT32_ENHANCED_PORTMUX
511	at32_free_pin(MCLK_PIN);
512	#endif
513
514	platform_device_unregister(playpaq_snd_device);
515	playpaq_snd_device = NULL;
516	}
517
518	module_init(playpaq_asoc_init);
519	module_exit(playpaq_asoc_exit);
520
521	MODULE_AUTHOR("Geoffrey Wossum <gwossum@acm.org>");
522	MODULE_DESCRIPTION("ASoC machine driver for LRS PlayPaq");
523	MODULE_LICENSE("GPL");