[mirror_ubuntu-eoan-kernel.git] / sound / soc / atmel / playpaq_wm8510.c

/* sound/soc/at32/playpaq_wm8510.c
 * ASoC machine driver for PlayPaq using WM8510 codec
 *
 * Copyright (C) 2008 Long Range Systems
 *    Geoffrey Wossum <gwossum@acm.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This code is largely inspired by sound/soc/at91/eti_b1_wm8731.c
 *
 * NOTE: If you don't have the AT32 enhanced portmux configured (which
 * isn't currently in the mainline or Atmel patched kernel), you will
 * need to set the MCLK pin (PA30) to peripheral A in your board initialization
 * code.  Something like:
 *	at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
 *
 */

/* #define DEBUG */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

#include <mach/at32ap700x.h>
#include <mach/portmux.h>

#include "../codecs/wm8510.h"
#include "atmel-pcm.h"
#include "atmel_ssc_dai.h"


/*-------------------------------------------------------------------------*\
 * constants
\*-------------------------------------------------------------------------*/
#define MCLK_PIN		GPIO_PIN_PA(30)
#define MCLK_PERIPH		GPIO_PERIPH_A


/*-------------------------------------------------------------------------*\
 * data types
\*-------------------------------------------------------------------------*/
/* SSC clocking data */
struct ssc_clock_data {
	/* CMR div */
	unsigned int cmr_div;

	/* Frame period (as needed by xCMR.PERIOD) */
	unsigned int period;

	/* The SSC clock rate these settings where calculated for */
	unsigned long ssc_rate;
};


/*-------------------------------------------------------------------------*\
 * module data
\*-------------------------------------------------------------------------*/
static struct clk *_gclk0;
static struct clk *_pll0;

#define CODEC_CLK (_gclk0)


/*-------------------------------------------------------------------------*\
 * Sound SOC operations
\*-------------------------------------------------------------------------*/
#if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
static struct ssc_clock_data playpaq_wm8510_calc_ssc_clock(
	struct snd_pcm_hw_params *params,
	struct snd_soc_dai *cpu_dai)
{
	struct at32_ssc_info *ssc_p = snd_soc_dai_get_drvdata(cpu_dai);
	struct ssc_device *ssc = ssc_p->ssc;
	struct ssc_clock_data cd;
	unsigned int rate, width_bits, channels;
	unsigned int bitrate, ssc_div;
	unsigned actual_rate;


	/*
	 * Figure out required bitrate
	 */
	rate = params_rate(params);
	channels = params_channels(params);
	width_bits = snd_pcm_format_physical_width(params_format(params));
	bitrate = rate * width_bits * channels;


	/*
	 * Figure out required SSC divider and period for required bitrate
	 */
	cd.ssc_rate = clk_get_rate(ssc->clk);
	ssc_div = cd.ssc_rate / bitrate;
	cd.cmr_div = ssc_div / 2;
	if (ssc_div & 1) {
		/* round cmr_div up */
		cd.cmr_div++;
	}
	cd.period = width_bits - 1;


	/*
	 * Find actual rate, compare to requested rate
	 */
	actual_rate = (cd.ssc_rate / (cd.cmr_div * 2)) / (2 * (cd.period + 1));
	pr_debug("playpaq_wm8510: Request rate = %u, actual rate = %u\n",
		 rate, actual_rate);


	return cd;
}
#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */


static int playpaq_wm8510_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *codec_dai = rtd->codec_dai;
	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
	struct at32_ssc_info *ssc_p = snd_soc_dai_get_drvdata(cpu_dai);
	struct ssc_device *ssc = ssc_p->ssc;
	unsigned int pll_out = 0, bclk = 0, mclk_div = 0;
	int ret;


	/* Due to difficulties with getting the correct clocks from the AT32's
	 * PLL0, we're going to let the CODEC be in charge of all the clocks
	 */
#if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	const unsigned int fmt = (SND_SOC_DAIFMT_I2S |
				  SND_SOC_DAIFMT_NB_NF |
				  SND_SOC_DAIFMT_CBM_CFM);
#else
	struct ssc_clock_data cd;
	const unsigned int fmt = (SND_SOC_DAIFMT_I2S |
				  SND_SOC_DAIFMT_NB_NF |
				  SND_SOC_DAIFMT_CBS_CFS);
#endif

	if (ssc == NULL) {
		pr_warning("playpaq_wm8510_hw_params: ssc is NULL!\n");
		return -EINVAL;
	}


	/*
	 * Figure out PLL and BCLK dividers for WM8510
	 */
	switch (params_rate(params)) {
	case 48000:
		pll_out = 24576000;
		mclk_div = WM8510_MCLKDIV_2;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 44100:
		pll_out = 22579200;
		mclk_div = WM8510_MCLKDIV_2;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 22050:
		pll_out = 22579200;
		mclk_div = WM8510_MCLKDIV_4;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 16000:
		pll_out = 24576000;
		mclk_div = WM8510_MCLKDIV_6;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 11025:
		pll_out = 22579200;
		mclk_div = WM8510_MCLKDIV_8;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 8000:
		pll_out = 24576000;
		mclk_div = WM8510_MCLKDIV_12;
		bclk = WM8510_BCLKDIV_8;
		break;

	default:
		pr_warning("playpaq_wm8510: Unsupported sample rate %d\n",
			   params_rate(params));
		return -EINVAL;
	}


	/*
	 * set CPU and CODEC DAI configuration
	 */
	ret = snd_soc_dai_set_fmt(codec_dai, fmt);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: "
			   "Failed to set CODEC DAI format (%d)\n",
			   ret);
		return ret;
	}
	ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: "
			   "Failed to set CPU DAI format (%d)\n",
			   ret);
		return ret;
	}


	/*
	 * Set CPU clock configuration
	 */
#if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	cd = playpaq_wm8510_calc_ssc_clock(params, cpu_dai);
	pr_debug("playpaq_wm8510: cmr_div = %d, period = %d\n",
		 cd.cmr_div, cd.period);
	ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_CMR_DIV, cd.cmr_div);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: Failed to set CPU CMR_DIV (%d)\n",
			   ret);
		return ret;
	}
	ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_TCMR_PERIOD,
					  cd.period);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: "
			   "Failed to set CPU transmit period (%d)\n",
			   ret);
		return ret;
	}
#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */


	/*
	 * Set CODEC clock configuration
	 */
	pr_debug("playpaq_wm8510: "
		 "pll_in = %ld, pll_out = %u, bclk = %x, mclk = %x\n",
		 clk_get_rate(CODEC_CLK), pll_out, bclk, mclk_div);


#if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_BCLKDIV, bclk);
	if (ret < 0) {
		pr_warning
		    ("playpaq_wm8510: Failed to set CODEC DAI BCLKDIV (%d)\n",
		     ret);
		return ret;
	}
#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */


	ret = snd_soc_dai_set_pll(codec_dai, 0, 0,
					 clk_get_rate(CODEC_CLK), pll_out);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: Failed to set CODEC DAI PLL (%d)\n",
			   ret);
		return ret;
	}


	ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_MCLKDIV, mclk_div);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: Failed to set CODEC MCLKDIV (%d)\n",
			   ret);
		return ret;
	}


	return 0;
}


static struct snd_soc_ops playpaq_wm8510_ops = {
	.hw_params = playpaq_wm8510_hw_params,
};


static const struct snd_soc_dapm_widget playpaq_dapm_widgets[] = {
	SND_SOC_DAPM_MIC("Int Mic", NULL),
	SND_SOC_DAPM_SPK("Ext Spk", NULL),
};


static const struct snd_soc_dapm_route intercon[] = {
	/* speaker connected to SPKOUT */
	{"Ext Spk", NULL, "SPKOUTP"},
	{"Ext Spk", NULL, "SPKOUTN"},

	{"Mic Bias", NULL, "Int Mic"},
	{"MICN", NULL, "Mic Bias"},
	{"MICP", NULL, "Mic Bias"},
};


static int playpaq_wm8510_init(struct snd_soc_pcm_runtime *rtd)
{
	struct snd_soc_codec *codec = rtd->codec;
	struct snd_soc_dapm_context *dapm = &codec->dapm;
	int i;

	/*
	 * Add DAPM widgets
	 */
	for (i = 0; i < ARRAY_SIZE(playpaq_dapm_widgets); i++)
		snd_soc_dapm_new_control(dapm, &playpaq_dapm_widgets[i]);


	/*
	 * Setup audio path interconnects
	 */
	snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));


	/* always connected pins */
	snd_soc_dapm_enable_pin(dapm, "Int Mic");
	snd_soc_dapm_enable_pin(dapm, "Ext Spk");


	/* Make CSB show PLL rate */
	snd_soc_dai_set_clkdiv(rtd->codec_dai, WM8510_OPCLKDIV,
				       WM8510_OPCLKDIV_1 | 4);

	return 0;
}


static struct snd_soc_dai_link playpaq_wm8510_dai = {
	.name = "WM8510",
	.stream_name = "WM8510 PCM",
	.cpu_dai_name= "atmel-ssc-dai.0",
	.platform_name = "atmel-pcm-audio",
	.codec_name = "wm8510-codec.0-0x1a",
	.codec_dai_name = "wm8510-hifi",
	.init = playpaq_wm8510_init,
	.ops = &playpaq_wm8510_ops,
};


static struct snd_soc_card snd_soc_playpaq = {
	.name = "LRS_PlayPaq_WM8510",
	.dai_link = &playpaq_wm8510_dai,
	.num_links = 1,
};

static struct platform_device *playpaq_snd_device;


static int __init playpaq_asoc_init(void)
{
	int ret = 0;

	/*
	 * Configure MCLK for WM8510
	 */
	_gclk0 = clk_get(NULL, "gclk0");
	if (IS_ERR(_gclk0)) {
		_gclk0 = NULL;
		ret = PTR_ERR(_gclk0);
		goto err_gclk0;
	}
	_pll0 = clk_get(NULL, "pll0");
	if (IS_ERR(_pll0)) {
		_pll0 = NULL;
		ret = PTR_ERR(_pll0);
		goto err_pll0;
	}
	ret = clk_set_parent(_gclk0, _pll0);
	if (ret) {
		pr_warning("snd-soc-playpaq: "
			   "Failed to set PLL0 as parent for DAC clock\n");
		goto err_set_clk;
	}
	clk_set_rate(CODEC_CLK, 12000000);
	clk_enable(CODEC_CLK);

#if defined CONFIG_AT32_ENHANCED_PORTMUX
	at32_select_periph(MCLK_PIN, MCLK_PERIPH, 0);
#endif


	/*
	 * Create and register platform device
	 */
	playpaq_snd_device = platform_device_alloc("soc-audio", 0);
	if (playpaq_snd_device == NULL) {
		ret = -ENOMEM;
		goto err_device_alloc;
	}

	platform_set_drvdata(playpaq_snd_device, &snd_soc_playpaq);

	ret = platform_device_add(playpaq_snd_device);
	if (ret) {
		pr_warning("playpaq_wm8510: platform_device_add failed (%d)\n",
			   ret);
		goto err_device_add;
	}

	return 0;


err_device_add:
	if (playpaq_snd_device != NULL) {
		platform_device_put(playpaq_snd_device);
		playpaq_snd_device = NULL;
	}
err_device_alloc:
err_set_clk:
	if (_pll0 != NULL) {
		clk_put(_pll0);
		_pll0 = NULL;
	}
err_pll0:
	if (_gclk0 != NULL) {
		clk_put(_gclk0);
		_gclk0 = NULL;
	}
	return ret;
}


static void __exit playpaq_asoc_exit(void)
{
	if (_gclk0 != NULL) {
		clk_put(_gclk0);
		_gclk0 = NULL;
	}
	if (_pll0 != NULL) {
		clk_put(_pll0);
		_pll0 = NULL;
	}

#if defined CONFIG_AT32_ENHANCED_PORTMUX
	at32_free_pin(MCLK_PIN);
#endif

	platform_device_unregister(playpaq_snd_device);
	playpaq_snd_device = NULL;
}

module_init(playpaq_asoc_init);
module_exit(playpaq_asoc_exit);

MODULE_AUTHOR("Geoffrey Wossum <gwossum@acm.org>");
MODULE_DESCRIPTION("ASoC machine driver for LRS PlayPaq");
MODULE_LICENSE("GPL");
Commit	Line	Data
9aaca968 GW	1	/* sound/soc/at32/playpaq_wm8510.c
	2	* ASoC machine driver for PlayPaq using WM8510 codec
	3	*
	4	* Copyright (C) 2008 Long Range Systems
	5	* Geoffrey Wossum <gwossum@acm.org>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This code is largely inspired by sound/soc/at91/eti_b1_wm8731.c
	12	*
	13	* NOTE: If you don't have the AT32 enhanced portmux configured (which
	14	* isn't currently in the mainline or Atmel patched kernel), you will
	15	* need to set the MCLK pin (PA30) to peripheral A in your board initialization
	16	* code. Something like:
	17	* at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
	18	*
	19	*/
	20
	21	/* #define DEBUG */
	22
	23	#include <linux/module.h>
	24	#include <linux/moduleparam.h>
9aaca968 GW	25	#include <linux/kernel.h>
	26	#include <linux/errno.h>
	27	#include <linux/clk.h>
	28	#include <linux/timer.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/platform_device.h>
	31
	32	#include <sound/core.h>
	33	#include <sound/pcm.h>
	34	#include <sound/pcm_params.h>
	35	#include <sound/soc.h>
9aaca968	36
a09e64fb RK	37	#include <mach/at32ap700x.h>
a09e64fb RK	38	#include <mach/portmux.h>
9aaca968 GW	39
9aaca968 GW	40	#include "../codecs/wm8510.h"
6c742509 SG	41	#include "atmel-pcm.h"
6c742509 SG	42	#include "atmel_ssc_dai.h"
9aaca968 GW	43
	44
	45	/-------------------------------------------------------------------------\
	46	* constants
	47	\-------------------------------------------------------------------------/
	48	#define MCLK_PIN GPIO_PIN_PA(30)
	49	#define MCLK_PERIPH GPIO_PERIPH_A
	50
	51
	52	/-------------------------------------------------------------------------\
	53	* data types
	54	\-------------------------------------------------------------------------/
	55	/* SSC clocking data */
	56	struct ssc_clock_data {
	57	/* CMR div */
	58	unsigned int cmr_div;
	59
	60	/* Frame period (as needed by xCMR.PERIOD) */
	61	unsigned int period;
	62
	63	/* The SSC clock rate these settings where calculated for */
	64	unsigned long ssc_rate;
	65	};
	66
	67
	68	/-------------------------------------------------------------------------\
	69	* module data
	70	\-------------------------------------------------------------------------/
	71	static struct clk *_gclk0;
	72	static struct clk *_pll0;
	73
	74	#define CODEC_CLK (_gclk0)
	75
	76
	77	/-------------------------------------------------------------------------\
	78	* Sound SOC operations
	79	\-------------------------------------------------------------------------/
	80	#if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	81	static struct ssc_clock_data playpaq_wm8510_calc_ssc_clock(
	82	struct snd_pcm_hw_params *params,
453ba20b	83	struct snd_soc_dai *cpu_dai)
9aaca968	84	{
f0fba2ad	85	struct at32_ssc_info *ssc_p = snd_soc_dai_get_drvdata(cpu_dai);
9aaca968 GW	86	struct ssc_device *ssc = ssc_p->ssc;
	87	struct ssc_clock_data cd;
	88	unsigned int rate, width_bits, channels;
	89	unsigned int bitrate, ssc_div;
	90	unsigned actual_rate;
	91
	92
	93	/*
	94	* Figure out required bitrate
	95	*/
	96	rate = params_rate(params);
	97	channels = params_channels(params);
	98	width_bits = snd_pcm_format_physical_width(params_format(params));
	99	bitrate = rate * width_bits * channels;
	100
	101
	102	/*
	103	* Figure out required SSC divider and period for required bitrate
	104	*/
	105	cd.ssc_rate = clk_get_rate(ssc->clk);
	106	ssc_div = cd.ssc_rate / bitrate;
	107	cd.cmr_div = ssc_div / 2;
	108	if (ssc_div & 1) {
	109	/* round cmr_div up */
	110	cd.cmr_div++;
	111	}
	112	cd.period = width_bits - 1;
	113
	114
	115	/*
	116	* Find actual rate, compare to requested rate
	117	*/
	118	actual_rate = (cd.ssc_rate / (cd.cmr_div * 2)) / (2 * (cd.period + 1));
449bd54d	119	pr_debug("playpaq_wm8510: Request rate = %u, actual rate = %u\n",
9aaca968 GW	120	rate, actual_rate);
	121
	122
	123	return cd;
	124	}
	125	#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
	126
	127
	128
	129	static int playpaq_wm8510_hw_params(struct snd_pcm_substream *substream,
	130	struct snd_pcm_hw_params *params)
	131	{
	132	struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad LG	133	struct snd_soc_dai *codec_dai = rtd->codec_dai;
	134	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
	135	struct at32_ssc_info *ssc_p = snd_soc_dai_get_drvdata(cpu_dai);
9aaca968 GW	136	struct ssc_device *ssc = ssc_p->ssc;
	137	unsigned int pll_out = 0, bclk = 0, mclk_div = 0;
	138	int ret;
	139
	140
	141	/* Due to difficulties with getting the correct clocks from the AT32's
	142	* PLL0, we're going to let the CODEC be in charge of all the clocks
	143	*/
	144	#if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	145	const unsigned int fmt = (SND_SOC_DAIFMT_I2S \|
	146	SND_SOC_DAIFMT_NB_NF \|
	147	SND_SOC_DAIFMT_CBM_CFM);
	148	#else
	149	struct ssc_clock_data cd;
	150	const unsigned int fmt = (SND_SOC_DAIFMT_I2S \|
	151	SND_SOC_DAIFMT_NB_NF \|
	152	SND_SOC_DAIFMT_CBS_CFS);
	153	#endif
	154
	155	if (ssc == NULL) {
	156	pr_warning("playpaq_wm8510_hw_params: ssc is NULL!\n");
	157	return -EINVAL;
	158	}
	159
	160
	161	/*
	162	* Figure out PLL and BCLK dividers for WM8510
	163	*/
	164	switch (params_rate(params)) {
	165	case 48000:
86027ae7 JA	166	pll_out = 24576000;
86027ae7 JA	167	mclk_div = WM8510_MCLKDIV_2;
9aaca968 GW	168	bclk = WM8510_BCLKDIV_8;
	169	break;
	170
	171	case 44100:
86027ae7 JA	172	pll_out = 22579200;
86027ae7 JA	173	mclk_div = WM8510_MCLKDIV_2;
9aaca968 GW	174	bclk = WM8510_BCLKDIV_8;
	175	break;
	176
	177	case 22050:
86027ae7 JA	178	pll_out = 22579200;
86027ae7 JA	179	mclk_div = WM8510_MCLKDIV_4;
9aaca968 GW	180	bclk = WM8510_BCLKDIV_8;
	181	break;
	182
	183	case 16000:
86027ae7 JA	184	pll_out = 24576000;
86027ae7 JA	185	mclk_div = WM8510_MCLKDIV_6;
9aaca968 GW	186	bclk = WM8510_BCLKDIV_8;
	187	break;
	188
	189	case 11025:
86027ae7 JA	190	pll_out = 22579200;
86027ae7 JA	191	mclk_div = WM8510_MCLKDIV_8;
9aaca968 GW	192	bclk = WM8510_BCLKDIV_8;
	193	break;
	194
	195	case 8000:
86027ae7 JA	196	pll_out = 24576000;
86027ae7 JA	197	mclk_div = WM8510_MCLKDIV_12;
9aaca968 GW	198	bclk = WM8510_BCLKDIV_8;
	199	break;
	200
	201	default:
	202	pr_warning("playpaq_wm8510: Unsupported sample rate %d\n",
	203	params_rate(params));
	204	return -EINVAL;
	205	}
	206
	207
	208	/*
	209	* set CPU and CODEC DAI configuration
	210	*/
64105cfd	211	ret = snd_soc_dai_set_fmt(codec_dai, fmt);
9aaca968 GW	212	if (ret < 0) {
	213	pr_warning("playpaq_wm8510: "
	214	"Failed to set CODEC DAI format (%d)\n",
	215	ret);
	216	return ret;
	217	}
64105cfd	218	ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
9aaca968 GW	219	if (ret < 0) {
	220	pr_warning("playpaq_wm8510: "
	221	"Failed to set CPU DAI format (%d)\n",
	222	ret);
	223	return ret;
	224	}
	225
	226
	227	/*
	228	* Set CPU clock configuration
	229	*/
	230	#if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	231	cd = playpaq_wm8510_calc_ssc_clock(params, cpu_dai);
	232	pr_debug("playpaq_wm8510: cmr_div = %d, period = %d\n",
	233	cd.cmr_div, cd.period);
64105cfd	234	ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_CMR_DIV, cd.cmr_div);
9aaca968 GW	235	if (ret < 0) {
	236	pr_warning("playpaq_wm8510: Failed to set CPU CMR_DIV (%d)\n",
	237	ret);
	238	return ret;
	239	}
64105cfd	240	ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_TCMR_PERIOD,
9aaca968 GW	241	cd.period);
	242	if (ret < 0) {
	243	pr_warning("playpaq_wm8510: "
	244	"Failed to set CPU transmit period (%d)\n",
	245	ret);
	246	return ret;
	247	}
	248	#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
	249
	250
	251	/*
	252	* Set CODEC clock configuration
	253	*/
	254	pr_debug("playpaq_wm8510: "
	255	"pll_in = %ld, pll_out = %u, bclk = %x, mclk = %x\n",
	256	clk_get_rate(CODEC_CLK), pll_out, bclk, mclk_div);
	257
	258
	259	#if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
64105cfd	260	ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_BCLKDIV, bclk);
9aaca968 GW	261	if (ret < 0) {
	262	pr_warning
	263	("playpaq_wm8510: Failed to set CODEC DAI BCLKDIV (%d)\n",
	264	ret);
	265	return ret;
	266	}
	267	#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
	268
	269
85488037	270	ret = snd_soc_dai_set_pll(codec_dai, 0, 0,
9aaca968 GW	271	clk_get_rate(CODEC_CLK), pll_out);
	272	if (ret < 0) {
	273	pr_warning("playpaq_wm8510: Failed to set CODEC DAI PLL (%d)\n",
	274	ret);
	275	return ret;
	276	}
	277
	278
64105cfd	279	ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_MCLKDIV, mclk_div);
9aaca968 GW	280	if (ret < 0) {
	281	pr_warning("playpaq_wm8510: Failed to set CODEC MCLKDIV (%d)\n",
	282	ret);
	283	return ret;
	284	}
	285
	286
	287	return 0;
	288	}
	289
	290
	291
	292	static struct snd_soc_ops playpaq_wm8510_ops = {
	293	.hw_params = playpaq_wm8510_hw_params,
	294	};
	295
	296
	297
	298	static const struct snd_soc_dapm_widget playpaq_dapm_widgets[] = {
	299	SND_SOC_DAPM_MIC("Int Mic", NULL),
	300	SND_SOC_DAPM_SPK("Ext Spk", NULL),
	301	};
	302
	303
	304
cdbdd167	305	static const struct snd_soc_dapm_route intercon[] = {
9aaca968 GW	306	/* speaker connected to SPKOUT */
	307	{"Ext Spk", NULL, "SPKOUTP"},
	308	{"Ext Spk", NULL, "SPKOUTN"},
	309
	310	{"Mic Bias", NULL, "Int Mic"},
	311	{"MICN", NULL, "Mic Bias"},
	312	{"MICP", NULL, "Mic Bias"},
9aaca968 GW	313	};
	314
	315
	316
f0fba2ad	317	static int playpaq_wm8510_init(struct snd_soc_pcm_runtime *rtd)
9aaca968	318	{
f0fba2ad	319	struct snd_soc_codec *codec = rtd->codec;
ce6120cc	320	struct snd_soc_dapm_context *dapm = &codec->dapm;
9aaca968 GW	321	int i;
	322
	323	/*
	324	* Add DAPM widgets
	325	*/
	326	for (i = 0; i < ARRAY_SIZE(playpaq_dapm_widgets); i++)
ce6120cc	327	snd_soc_dapm_new_control(dapm, &playpaq_dapm_widgets[i]);
9aaca968 GW	328
	329
	330
	331	/*
	332	* Setup audio path interconnects
	333	*/
ce6120cc	334	snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
cdbdd167	335
9aaca968 GW	336
9aaca968 GW	337
6f48413d	338	/* always connected pins */
ce6120cc LG	339	snd_soc_dapm_enable_pin(dapm, "Int Mic");
ce6120cc LG	340	snd_soc_dapm_enable_pin(dapm, "Ext Spk");
9aaca968 GW	341
	342
	343
	344	/* Make CSB show PLL rate */
f0fba2ad	345	snd_soc_dai_set_clkdiv(rtd->codec_dai, WM8510_OPCLKDIV,
9aaca968 GW	346	WM8510_OPCLKDIV_1 \| 4);
	347
	348	return 0;
	349	}
	350
	351
	352
	353	static struct snd_soc_dai_link playpaq_wm8510_dai = {
	354	.name = "WM8510",
	355	.stream_name = "WM8510 PCM",
f0fba2ad LG	356	.cpu_dai_name= "atmel-ssc-dai.0",
	357	.platform_name = "atmel-pcm-audio",
	358	.codec_name = "wm8510-codec.0-0x1a",
	359	.codec_dai_name = "wm8510-hifi",
9aaca968 GW	360	.init = playpaq_wm8510_init,
	361	.ops = &playpaq_wm8510_ops,
	362	};
	363
	364
	365
87506549	366	static struct snd_soc_card snd_soc_playpaq = {
9aaca968 GW	367	.name = "LRS_PlayPaq_WM8510",
	368	.dai_link = &playpaq_wm8510_dai,
	369	.num_links = 1,
	370	};
	371
9aaca968 GW	372	static struct platform_device *playpaq_snd_device;
	373
	374
	375	static int __init playpaq_asoc_init(void)
	376	{
	377	int ret = 0;
9aaca968 GW	378
	379	/*
	380	* Configure MCLK for WM8510
	381	*/
	382	_gclk0 = clk_get(NULL, "gclk0");
	383	if (IS_ERR(_gclk0)) {
	384	_gclk0 = NULL;
69474147	385	ret = PTR_ERR(_gclk0);
9aaca968 GW	386	goto err_gclk0;
	387	}
	388	_pll0 = clk_get(NULL, "pll0");
	389	if (IS_ERR(_pll0)) {
	390	_pll0 = NULL;
69474147	391	ret = PTR_ERR(_pll0);
9aaca968 GW	392	goto err_pll0;
9aaca968 GW	393	}
69474147 AL	394	ret = clk_set_parent(_gclk0, _pll0);
69474147 AL	395	if (ret) {
9aaca968 GW	396	pr_warning("snd-soc-playpaq: "
	397	"Failed to set PLL0 as parent for DAC clock\n");
	398	goto err_set_clk;
	399	}
	400	clk_set_rate(CODEC_CLK, 12000000);
	401	clk_enable(CODEC_CLK);
	402
	403	#if defined CONFIG_AT32_ENHANCED_PORTMUX
	404	at32_select_periph(MCLK_PIN, MCLK_PERIPH, 0);
	405	#endif
	406
	407
	408	/*
	409	* Create and register platform device
	410	*/
	411	playpaq_snd_device = platform_device_alloc("soc-audio", 0);
	412	if (playpaq_snd_device == NULL) {
	413	ret = -ENOMEM;
	414	goto err_device_alloc;
	415	}
	416
f0fba2ad	417	platform_set_drvdata(playpaq_snd_device, &snd_soc_playpaq);
9aaca968 GW	418
	419	ret = platform_device_add(playpaq_snd_device);
	420	if (ret) {
	421	pr_warning("playpaq_wm8510: platform_device_add failed (%d)\n",
	422	ret);
	423	goto err_device_add;
	424	}
	425
	426	return 0;
	427
	428
	429	err_device_add:
	430	if (playpaq_snd_device != NULL) {
	431	platform_device_put(playpaq_snd_device);
	432	playpaq_snd_device = NULL;
	433	}
	434	err_device_alloc:
	435	err_set_clk:
	436	if (_pll0 != NULL) {
	437	clk_put(_pll0);
	438	_pll0 = NULL;
	439	}
	440	err_pll0:
	441	if (_gclk0 != NULL) {
	442	clk_put(_gclk0);
	443	_gclk0 = NULL;
	444	}
9aaca968 GW	445	return ret;
	446	}
	447
	448
	449	static void __exit playpaq_asoc_exit(void)
	450	{
9aaca968 GW	451	if (_gclk0 != NULL) {
	452	clk_put(_gclk0);
	453	_gclk0 = NULL;
	454	}
	455	if (_pll0 != NULL) {
	456	clk_put(_pll0);
	457	_pll0 = NULL;
	458	}
	459
	460	#if defined CONFIG_AT32_ENHANCED_PORTMUX
	461	at32_free_pin(MCLK_PIN);
	462	#endif
	463
	464	platform_device_unregister(playpaq_snd_device);
	465	playpaq_snd_device = NULL;
	466	}
	467
	468	module_init(playpaq_asoc_init);
	469	module_exit(playpaq_asoc_exit);
	470
	471	MODULE_AUTHOR("Geoffrey Wossum <gwossum@acm.org>");
	472	MODULE_DESCRIPTION("ASoC machine driver for LRS PlayPaq");
	473	MODULE_LICENSE("GPL");