[mirror_ubuntu-bionic-kernel.git] / sound / soc / atmel / playpaq_wm8510.c

/* sound/soc/at32/playpaq_wm8510.c
 * ASoC machine driver for PlayPaq using WM8510 codec
 *
 * Copyright (C) 2008 Long Range Systems
 *    Geoffrey Wossum <gwossum@acm.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This code is largely inspired by sound/soc/at91/eti_b1_wm8731.c
 *
 * NOTE: If you don't have the AT32 enhanced portmux configured (which
 * isn't currently in the mainline or Atmel patched kernel), you will
 * need to set the MCLK pin (PA30) to peripheral A in your board initialization
 * code.  Something like:
 *	at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
 *
 */

/* #define DEBUG */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>

#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>

#include <mach/at32ap700x.h>
#include <mach/portmux.h>

#include "../codecs/wm8510.h"
#include "atmel-pcm.h"
#include "atmel_ssc_dai.h"


/*-------------------------------------------------------------------------*\
 * constants
\*-------------------------------------------------------------------------*/
#define MCLK_PIN		GPIO_PIN_PA(30)
#define MCLK_PERIPH		GPIO_PERIPH_A


/*-------------------------------------------------------------------------*\
 * data types
\*-------------------------------------------------------------------------*/
/* SSC clocking data */
struct ssc_clock_data {
	/* CMR div */
	unsigned int cmr_div;

	/* Frame period (as needed by xCMR.PERIOD) */
	unsigned int period;

	/* The SSC clock rate these settings where calculated for */
	unsigned long ssc_rate;
};


/*-------------------------------------------------------------------------*\
 * module data
\*-------------------------------------------------------------------------*/
static struct clk *_gclk0;
static struct clk *_pll0;

#define CODEC_CLK (_gclk0)


/*-------------------------------------------------------------------------*\
 * Sound SOC operations
\*-------------------------------------------------------------------------*/
#if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
static struct ssc_clock_data playpaq_wm8510_calc_ssc_clock(
	struct snd_pcm_hw_params *params,
	struct snd_soc_dai *cpu_dai)
{
	struct at32_ssc_info *ssc_p = snd_soc_dai_get_drvdata(cpu_dai);
	struct ssc_device *ssc = ssc_p->ssc;
	struct ssc_clock_data cd;
	unsigned int rate, width_bits, channels;
	unsigned int bitrate, ssc_div;
	unsigned actual_rate;


	/*
	 * Figure out required bitrate
	 */
	rate = params_rate(params);
	channels = params_channels(params);
	width_bits = snd_pcm_format_physical_width(params_format(params));
	bitrate = rate * width_bits * channels;


	/*
	 * Figure out required SSC divider and period for required bitrate
	 */
	cd.ssc_rate = clk_get_rate(ssc->clk);
	ssc_div = cd.ssc_rate / bitrate;
	cd.cmr_div = ssc_div / 2;
	if (ssc_div & 1) {
		/* round cmr_div up */
		cd.cmr_div++;
	}
	cd.period = width_bits - 1;


	/*
	 * Find actual rate, compare to requested rate
	 */
	actual_rate = (cd.ssc_rate / (cd.cmr_div * 2)) / (2 * (cd.period + 1));
	pr_debug("playpaq_wm8510: Request rate = %u, actual rate = %u\n",
		 rate, actual_rate);


	return cd;
}
#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */


static int playpaq_wm8510_hw_params(struct snd_pcm_substream *substream,
				    struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *codec_dai = rtd->codec_dai;
	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
	struct at32_ssc_info *ssc_p = snd_soc_dai_get_drvdata(cpu_dai);
	struct ssc_device *ssc = ssc_p->ssc;
	unsigned int pll_out = 0, bclk = 0, mclk_div = 0;
	int ret;


	/* Due to difficulties with getting the correct clocks from the AT32's
	 * PLL0, we're going to let the CODEC be in charge of all the clocks
	 */
#if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	const unsigned int fmt = (SND_SOC_DAIFMT_I2S |
				  SND_SOC_DAIFMT_NB_NF |
				  SND_SOC_DAIFMT_CBM_CFM);
#else
	struct ssc_clock_data cd;
	const unsigned int fmt = (SND_SOC_DAIFMT_I2S |
				  SND_SOC_DAIFMT_NB_NF |
				  SND_SOC_DAIFMT_CBS_CFS);
#endif

	if (ssc == NULL) {
		pr_warning("playpaq_wm8510_hw_params: ssc is NULL!\n");
		return -EINVAL;
	}


	/*
	 * Figure out PLL and BCLK dividers for WM8510
	 */
	switch (params_rate(params)) {
	case 48000:
		pll_out = 24576000;
		mclk_div = WM8510_MCLKDIV_2;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 44100:
		pll_out = 22579200;
		mclk_div = WM8510_MCLKDIV_2;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 22050:
		pll_out = 22579200;
		mclk_div = WM8510_MCLKDIV_4;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 16000:
		pll_out = 24576000;
		mclk_div = WM8510_MCLKDIV_6;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 11025:
		pll_out = 22579200;
		mclk_div = WM8510_MCLKDIV_8;
		bclk = WM8510_BCLKDIV_8;
		break;

	case 8000:
		pll_out = 24576000;
		mclk_div = WM8510_MCLKDIV_12;
		bclk = WM8510_BCLKDIV_8;
		break;

	default:
		pr_warning("playpaq_wm8510: Unsupported sample rate %d\n",
			   params_rate(params));
		return -EINVAL;
	}


	/*
	 * set CPU and CODEC DAI configuration
	 */
	ret = snd_soc_dai_set_fmt(codec_dai, fmt);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: "
			   "Failed to set CODEC DAI format (%d)\n",
			   ret);
		return ret;
	}
	ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: "
			   "Failed to set CPU DAI format (%d)\n",
			   ret);
		return ret;
	}


	/*
	 * Set CPU clock configuration
	 */
#if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	cd = playpaq_wm8510_calc_ssc_clock(params, cpu_dai);
	pr_debug("playpaq_wm8510: cmr_div = %d, period = %d\n",
		 cd.cmr_div, cd.period);
	ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_CMR_DIV, cd.cmr_div);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: Failed to set CPU CMR_DIV (%d)\n",
			   ret);
		return ret;
	}
	ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_TCMR_PERIOD,
					  cd.period);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: "
			   "Failed to set CPU transmit period (%d)\n",
			   ret);
		return ret;
	}
#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */


	/*
	 * Set CODEC clock configuration
	 */
	pr_debug("playpaq_wm8510: "
		 "pll_in = %ld, pll_out = %u, bclk = %x, mclk = %x\n",
		 clk_get_rate(CODEC_CLK), pll_out, bclk, mclk_div);


#if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_BCLKDIV, bclk);
	if (ret < 0) {
		pr_warning
		    ("playpaq_wm8510: Failed to set CODEC DAI BCLKDIV (%d)\n",
		     ret);
		return ret;
	}
#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */


	ret = snd_soc_dai_set_pll(codec_dai, 0, 0,
					 clk_get_rate(CODEC_CLK), pll_out);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: Failed to set CODEC DAI PLL (%d)\n",
			   ret);
		return ret;
	}


	ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_MCLKDIV, mclk_div);
	if (ret < 0) {
		pr_warning("playpaq_wm8510: Failed to set CODEC MCLKDIV (%d)\n",
			   ret);
		return ret;
	}


	return 0;
}


static struct snd_soc_ops playpaq_wm8510_ops = {
	.hw_params = playpaq_wm8510_hw_params,
};


static const struct snd_soc_dapm_widget playpaq_dapm_widgets[] = {
	SND_SOC_DAPM_MIC("Int Mic", NULL),
	SND_SOC_DAPM_SPK("Ext Spk", NULL),
};


static const struct snd_soc_dapm_route intercon[] = {
	/* speaker connected to SPKOUT */
	{"Ext Spk", NULL, "SPKOUTP"},
	{"Ext Spk", NULL, "SPKOUTN"},

	{"Mic Bias", NULL, "Int Mic"},
	{"MICN", NULL, "Mic Bias"},
	{"MICP", NULL, "Mic Bias"},
};


static int playpaq_wm8510_init(struct snd_soc_pcm_runtime *rtd)
{
	struct snd_soc_codec *codec = rtd->codec;
	struct snd_soc_dapm_context *dapm = &codec->dapm;
	int i;

	/*
	 * Add DAPM widgets
	 */
	for (i = 0; i < ARRAY_SIZE(playpaq_dapm_widgets); i++)
		snd_soc_dapm_new_control(dapm, &playpaq_dapm_widgets[i]);


	/*
	 * Setup audio path interconnects
	 */
	snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));


	/* always connected pins */
	snd_soc_dapm_enable_pin(dapm, "Int Mic");
	snd_soc_dapm_enable_pin(dapm, "Ext Spk");
	snd_soc_dapm_sync(dapm);


	/* Make CSB show PLL rate */
	snd_soc_dai_set_clkdiv(rtd->codec_dai, WM8510_OPCLKDIV,
				       WM8510_OPCLKDIV_1 | 4);

	return 0;
}


static struct snd_soc_dai_link playpaq_wm8510_dai = {
	.name = "WM8510",
	.stream_name = "WM8510 PCM",
	.cpu_dai_name= "atmel-ssc-dai.0",
	.platform_name = "atmel-pcm-audio",
	.codec_name = "wm8510-codec.0-0x1a",
	.codec_dai_name = "wm8510-hifi",
	.init = playpaq_wm8510_init,
	.ops = &playpaq_wm8510_ops,
};


static struct snd_soc_card snd_soc_playpaq = {
	.name = "LRS_PlayPaq_WM8510",
	.dai_link = &playpaq_wm8510_dai,
	.num_links = 1,
};

static struct platform_device *playpaq_snd_device;


static int __init playpaq_asoc_init(void)
{
	int ret = 0;

	/*
	 * Configure MCLK for WM8510
	 */
	_gclk0 = clk_get(NULL, "gclk0");
	if (IS_ERR(_gclk0)) {
		_gclk0 = NULL;
		goto err_gclk0;
	}
	_pll0 = clk_get(NULL, "pll0");
	if (IS_ERR(_pll0)) {
		_pll0 = NULL;
		goto err_pll0;
	}
	if (clk_set_parent(_gclk0, _pll0)) {
		pr_warning("snd-soc-playpaq: "
			   "Failed to set PLL0 as parent for DAC clock\n");
		goto err_set_clk;
	}
	clk_set_rate(CODEC_CLK, 12000000);
	clk_enable(CODEC_CLK);

#if defined CONFIG_AT32_ENHANCED_PORTMUX
	at32_select_periph(MCLK_PIN, MCLK_PERIPH, 0);
#endif


	/*
	 * Create and register platform device
	 */
	playpaq_snd_device = platform_device_alloc("soc-audio", 0);
	if (playpaq_snd_device == NULL) {
		ret = -ENOMEM;
		goto err_device_alloc;
	}

	platform_set_drvdata(playpaq_snd_device, &snd_soc_playpaq);

	ret = platform_device_add(playpaq_snd_device);
	if (ret) {
		pr_warning("playpaq_wm8510: platform_device_add failed (%d)\n",
			   ret);
		goto err_device_add;
	}

	return 0;


err_device_add:
	if (playpaq_snd_device != NULL) {
		platform_device_put(playpaq_snd_device);
		playpaq_snd_device = NULL;
	}
err_device_alloc:
err_set_clk:
	if (_pll0 != NULL) {
		clk_put(_pll0);
		_pll0 = NULL;
	}
err_pll0:
	if (_gclk0 != NULL) {
		clk_put(_gclk0);
		_gclk0 = NULL;
	}
	return ret;
}


static void __exit playpaq_asoc_exit(void)
{
	if (_gclk0 != NULL) {
		clk_put(_gclk0);
		_gclk0 = NULL;
	}
	if (_pll0 != NULL) {
		clk_put(_pll0);
		_pll0 = NULL;
	}

#if defined CONFIG_AT32_ENHANCED_PORTMUX
	at32_free_pin(MCLK_PIN);
#endif

	platform_device_unregister(playpaq_snd_device);
	playpaq_snd_device = NULL;
}

module_init(playpaq_asoc_init);
module_exit(playpaq_asoc_exit);

MODULE_AUTHOR("Geoffrey Wossum <gwossum@acm.org>");
MODULE_DESCRIPTION("ASoC machine driver for LRS PlayPaq");
MODULE_LICENSE("GPL");
Commit	Line	Data
9aaca968 GW	1	/* sound/soc/at32/playpaq_wm8510.c
	2	* ASoC machine driver for PlayPaq using WM8510 codec
	3	*
	4	* Copyright (C) 2008 Long Range Systems
	5	* Geoffrey Wossum <gwossum@acm.org>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This code is largely inspired by sound/soc/at91/eti_b1_wm8731.c
	12	*
	13	* NOTE: If you don't have the AT32 enhanced portmux configured (which
	14	* isn't currently in the mainline or Atmel patched kernel), you will
	15	* need to set the MCLK pin (PA30) to peripheral A in your board initialization
	16	* code. Something like:
	17	* at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
	18	*
	19	*/
	20
	21	/* #define DEBUG */
	22
	23	#include <linux/module.h>
	24	#include <linux/moduleparam.h>
9aaca968 GW	25	#include <linux/kernel.h>
	26	#include <linux/errno.h>
	27	#include <linux/clk.h>
	28	#include <linux/timer.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/platform_device.h>
	31
	32	#include <sound/core.h>
	33	#include <sound/pcm.h>
	34	#include <sound/pcm_params.h>
	35	#include <sound/soc.h>
	36	#include <sound/soc-dapm.h>
	37
a09e64fb RK	38	#include <mach/at32ap700x.h>
a09e64fb RK	39	#include <mach/portmux.h>
9aaca968 GW	40
9aaca968 GW	41	#include "../codecs/wm8510.h"
6c742509 SG	42	#include "atmel-pcm.h"
6c742509 SG	43	#include "atmel_ssc_dai.h"
9aaca968 GW	44
	45
	46	/-------------------------------------------------------------------------\
	47	* constants
	48	\-------------------------------------------------------------------------/
	49	#define MCLK_PIN GPIO_PIN_PA(30)
	50	#define MCLK_PERIPH GPIO_PERIPH_A
	51
	52
	53	/-------------------------------------------------------------------------\
	54	* data types
	55	\-------------------------------------------------------------------------/
	56	/* SSC clocking data */
	57	struct ssc_clock_data {
	58	/* CMR div */
	59	unsigned int cmr_div;
	60
	61	/* Frame period (as needed by xCMR.PERIOD) */
	62	unsigned int period;
	63
	64	/* The SSC clock rate these settings where calculated for */
	65	unsigned long ssc_rate;
	66	};
	67
	68
	69	/-------------------------------------------------------------------------\
	70	* module data
	71	\-------------------------------------------------------------------------/
	72	static struct clk *_gclk0;
	73	static struct clk *_pll0;
	74
	75	#define CODEC_CLK (_gclk0)
	76
	77
	78	/-------------------------------------------------------------------------\
	79	* Sound SOC operations
	80	\-------------------------------------------------------------------------/
	81	#if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	82	static struct ssc_clock_data playpaq_wm8510_calc_ssc_clock(
	83	struct snd_pcm_hw_params *params,
453ba20b	84	struct snd_soc_dai *cpu_dai)
9aaca968	85	{
f0fba2ad	86	struct at32_ssc_info *ssc_p = snd_soc_dai_get_drvdata(cpu_dai);
9aaca968 GW	87	struct ssc_device *ssc = ssc_p->ssc;
	88	struct ssc_clock_data cd;
	89	unsigned int rate, width_bits, channels;
	90	unsigned int bitrate, ssc_div;
	91	unsigned actual_rate;
	92
	93
	94	/*
	95	* Figure out required bitrate
	96	*/
	97	rate = params_rate(params);
	98	channels = params_channels(params);
	99	width_bits = snd_pcm_format_physical_width(params_format(params));
	100	bitrate = rate * width_bits * channels;
	101
	102
	103	/*
	104	* Figure out required SSC divider and period for required bitrate
	105	*/
	106	cd.ssc_rate = clk_get_rate(ssc->clk);
	107	ssc_div = cd.ssc_rate / bitrate;
	108	cd.cmr_div = ssc_div / 2;
	109	if (ssc_div & 1) {
	110	/* round cmr_div up */
	111	cd.cmr_div++;
	112	}
	113	cd.period = width_bits - 1;
	114
	115
	116	/*
	117	* Find actual rate, compare to requested rate
	118	*/
	119	actual_rate = (cd.ssc_rate / (cd.cmr_div * 2)) / (2 * (cd.period + 1));
449bd54d	120	pr_debug("playpaq_wm8510: Request rate = %u, actual rate = %u\n",
9aaca968 GW	121	rate, actual_rate);
	122
	123
	124	return cd;
	125	}
	126	#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
	127
	128
	129
	130	static int playpaq_wm8510_hw_params(struct snd_pcm_substream *substream,
	131	struct snd_pcm_hw_params *params)
	132	{
	133	struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad LG	134	struct snd_soc_dai *codec_dai = rtd->codec_dai;
	135	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
	136	struct at32_ssc_info *ssc_p = snd_soc_dai_get_drvdata(cpu_dai);
9aaca968 GW	137	struct ssc_device *ssc = ssc_p->ssc;
	138	unsigned int pll_out = 0, bclk = 0, mclk_div = 0;
	139	int ret;
	140
	141
	142	/* Due to difficulties with getting the correct clocks from the AT32's
	143	* PLL0, we're going to let the CODEC be in charge of all the clocks
	144	*/
	145	#if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	146	const unsigned int fmt = (SND_SOC_DAIFMT_I2S \|
	147	SND_SOC_DAIFMT_NB_NF \|
	148	SND_SOC_DAIFMT_CBM_CFM);
	149	#else
	150	struct ssc_clock_data cd;
	151	const unsigned int fmt = (SND_SOC_DAIFMT_I2S \|
	152	SND_SOC_DAIFMT_NB_NF \|
	153	SND_SOC_DAIFMT_CBS_CFS);
	154	#endif
	155
	156	if (ssc == NULL) {
	157	pr_warning("playpaq_wm8510_hw_params: ssc is NULL!\n");
	158	return -EINVAL;
	159	}
	160
	161
	162	/*
	163	* Figure out PLL and BCLK dividers for WM8510
	164	*/
	165	switch (params_rate(params)) {
	166	case 48000:
86027ae7 JA	167	pll_out = 24576000;
86027ae7 JA	168	mclk_div = WM8510_MCLKDIV_2;
9aaca968 GW	169	bclk = WM8510_BCLKDIV_8;
	170	break;
	171
	172	case 44100:
86027ae7 JA	173	pll_out = 22579200;
86027ae7 JA	174	mclk_div = WM8510_MCLKDIV_2;
9aaca968 GW	175	bclk = WM8510_BCLKDIV_8;
	176	break;
	177
	178	case 22050:
86027ae7 JA	179	pll_out = 22579200;
86027ae7 JA	180	mclk_div = WM8510_MCLKDIV_4;
9aaca968 GW	181	bclk = WM8510_BCLKDIV_8;
	182	break;
	183
	184	case 16000:
86027ae7 JA	185	pll_out = 24576000;
86027ae7 JA	186	mclk_div = WM8510_MCLKDIV_6;
9aaca968 GW	187	bclk = WM8510_BCLKDIV_8;
	188	break;
	189
	190	case 11025:
86027ae7 JA	191	pll_out = 22579200;
86027ae7 JA	192	mclk_div = WM8510_MCLKDIV_8;
9aaca968 GW	193	bclk = WM8510_BCLKDIV_8;
	194	break;
	195
	196	case 8000:
86027ae7 JA	197	pll_out = 24576000;
86027ae7 JA	198	mclk_div = WM8510_MCLKDIV_12;
9aaca968 GW	199	bclk = WM8510_BCLKDIV_8;
	200	break;
	201
	202	default:
	203	pr_warning("playpaq_wm8510: Unsupported sample rate %d\n",
	204	params_rate(params));
	205	return -EINVAL;
	206	}
	207
	208
	209	/*
	210	* set CPU and CODEC DAI configuration
	211	*/
64105cfd	212	ret = snd_soc_dai_set_fmt(codec_dai, fmt);
9aaca968 GW	213	if (ret < 0) {
	214	pr_warning("playpaq_wm8510: "
	215	"Failed to set CODEC DAI format (%d)\n",
	216	ret);
	217	return ret;
	218	}
64105cfd	219	ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
9aaca968 GW	220	if (ret < 0) {
	221	pr_warning("playpaq_wm8510: "
	222	"Failed to set CPU DAI format (%d)\n",
	223	ret);
	224	return ret;
	225	}
	226
	227
	228	/*
	229	* Set CPU clock configuration
	230	*/
	231	#if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
	232	cd = playpaq_wm8510_calc_ssc_clock(params, cpu_dai);
	233	pr_debug("playpaq_wm8510: cmr_div = %d, period = %d\n",
	234	cd.cmr_div, cd.period);
64105cfd	235	ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_CMR_DIV, cd.cmr_div);
9aaca968 GW	236	if (ret < 0) {
	237	pr_warning("playpaq_wm8510: Failed to set CPU CMR_DIV (%d)\n",
	238	ret);
	239	return ret;
	240	}
64105cfd	241	ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_TCMR_PERIOD,
9aaca968 GW	242	cd.period);
	243	if (ret < 0) {
	244	pr_warning("playpaq_wm8510: "
	245	"Failed to set CPU transmit period (%d)\n",
	246	ret);
	247	return ret;
	248	}
	249	#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
	250
	251
	252	/*
	253	* Set CODEC clock configuration
	254	*/
	255	pr_debug("playpaq_wm8510: "
	256	"pll_in = %ld, pll_out = %u, bclk = %x, mclk = %x\n",
	257	clk_get_rate(CODEC_CLK), pll_out, bclk, mclk_div);
	258
	259
	260	#if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
64105cfd	261	ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_BCLKDIV, bclk);
9aaca968 GW	262	if (ret < 0) {
	263	pr_warning
	264	("playpaq_wm8510: Failed to set CODEC DAI BCLKDIV (%d)\n",
	265	ret);
	266	return ret;
	267	}
	268	#endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
	269
	270
85488037	271	ret = snd_soc_dai_set_pll(codec_dai, 0, 0,
9aaca968 GW	272	clk_get_rate(CODEC_CLK), pll_out);
	273	if (ret < 0) {
	274	pr_warning("playpaq_wm8510: Failed to set CODEC DAI PLL (%d)\n",
	275	ret);
	276	return ret;
	277	}
	278
	279
64105cfd	280	ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_MCLKDIV, mclk_div);
9aaca968 GW	281	if (ret < 0) {
	282	pr_warning("playpaq_wm8510: Failed to set CODEC MCLKDIV (%d)\n",
	283	ret);
	284	return ret;
	285	}
	286
	287
	288	return 0;
	289	}
	290
	291
	292
	293	static struct snd_soc_ops playpaq_wm8510_ops = {
	294	.hw_params = playpaq_wm8510_hw_params,
	295	};
	296
	297
	298
	299	static const struct snd_soc_dapm_widget playpaq_dapm_widgets[] = {
	300	SND_SOC_DAPM_MIC("Int Mic", NULL),
	301	SND_SOC_DAPM_SPK("Ext Spk", NULL),
	302	};
	303
	304
	305
cdbdd167	306	static const struct snd_soc_dapm_route intercon[] = {
9aaca968 GW	307	/* speaker connected to SPKOUT */
	308	{"Ext Spk", NULL, "SPKOUTP"},
	309	{"Ext Spk", NULL, "SPKOUTN"},
	310
	311	{"Mic Bias", NULL, "Int Mic"},
	312	{"MICN", NULL, "Mic Bias"},
	313	{"MICP", NULL, "Mic Bias"},
9aaca968 GW	314	};
	315
	316
	317
f0fba2ad	318	static int playpaq_wm8510_init(struct snd_soc_pcm_runtime *rtd)
9aaca968	319	{
f0fba2ad	320	struct snd_soc_codec *codec = rtd->codec;
ce6120cc	321	struct snd_soc_dapm_context *dapm = &codec->dapm;
9aaca968 GW	322	int i;
	323
	324	/*
	325	* Add DAPM widgets
	326	*/
	327	for (i = 0; i < ARRAY_SIZE(playpaq_dapm_widgets); i++)
ce6120cc	328	snd_soc_dapm_new_control(dapm, &playpaq_dapm_widgets[i]);
9aaca968 GW	329
	330
	331
	332	/*
	333	* Setup audio path interconnects
	334	*/
ce6120cc	335	snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
cdbdd167	336
9aaca968 GW	337
9aaca968 GW	338
6f48413d	339	/* always connected pins */
ce6120cc LG	340	snd_soc_dapm_enable_pin(dapm, "Int Mic");
	341	snd_soc_dapm_enable_pin(dapm, "Ext Spk");
	342	snd_soc_dapm_sync(dapm);
9aaca968 GW	343
	344
	345
	346	/* Make CSB show PLL rate */
f0fba2ad	347	snd_soc_dai_set_clkdiv(rtd->codec_dai, WM8510_OPCLKDIV,
9aaca968 GW	348	WM8510_OPCLKDIV_1 \| 4);
	349
	350	return 0;
	351	}
	352
	353
	354
	355	static struct snd_soc_dai_link playpaq_wm8510_dai = {
	356	.name = "WM8510",
	357	.stream_name = "WM8510 PCM",
f0fba2ad LG	358	.cpu_dai_name= "atmel-ssc-dai.0",
	359	.platform_name = "atmel-pcm-audio",
	360	.codec_name = "wm8510-codec.0-0x1a",
	361	.codec_dai_name = "wm8510-hifi",
9aaca968 GW	362	.init = playpaq_wm8510_init,
	363	.ops = &playpaq_wm8510_ops,
	364	};
	365
	366
	367
87506549	368	static struct snd_soc_card snd_soc_playpaq = {
9aaca968 GW	369	.name = "LRS_PlayPaq_WM8510",
	370	.dai_link = &playpaq_wm8510_dai,
	371	.num_links = 1,
	372	};
	373
9aaca968 GW	374	static struct platform_device *playpaq_snd_device;
	375
	376
	377	static int __init playpaq_asoc_init(void)
	378	{
	379	int ret = 0;
9aaca968 GW	380
	381	/*
	382	* Configure MCLK for WM8510
	383	*/
	384	_gclk0 = clk_get(NULL, "gclk0");
	385	if (IS_ERR(_gclk0)) {
	386	_gclk0 = NULL;
	387	goto err_gclk0;
	388	}
	389	_pll0 = clk_get(NULL, "pll0");
	390	if (IS_ERR(_pll0)) {
	391	_pll0 = NULL;
	392	goto err_pll0;
	393	}
	394	if (clk_set_parent(_gclk0, _pll0)) {
	395	pr_warning("snd-soc-playpaq: "
	396	"Failed to set PLL0 as parent for DAC clock\n");
	397	goto err_set_clk;
	398	}
	399	clk_set_rate(CODEC_CLK, 12000000);
	400	clk_enable(CODEC_CLK);
	401
	402	#if defined CONFIG_AT32_ENHANCED_PORTMUX
	403	at32_select_periph(MCLK_PIN, MCLK_PERIPH, 0);
	404	#endif
	405
	406
	407	/*
	408	* Create and register platform device
	409	*/
	410	playpaq_snd_device = platform_device_alloc("soc-audio", 0);
	411	if (playpaq_snd_device == NULL) {
	412	ret = -ENOMEM;
	413	goto err_device_alloc;
	414	}
	415
f0fba2ad	416	platform_set_drvdata(playpaq_snd_device, &snd_soc_playpaq);
9aaca968 GW	417
	418	ret = platform_device_add(playpaq_snd_device);
	419	if (ret) {
	420	pr_warning("playpaq_wm8510: platform_device_add failed (%d)\n",
	421	ret);
	422	goto err_device_add;
	423	}
	424
	425	return 0;
	426
	427
	428	err_device_add:
	429	if (playpaq_snd_device != NULL) {
	430	platform_device_put(playpaq_snd_device);
	431	playpaq_snd_device = NULL;
	432	}
	433	err_device_alloc:
	434	err_set_clk:
	435	if (_pll0 != NULL) {
	436	clk_put(_pll0);
	437	_pll0 = NULL;
	438	}
	439	err_pll0:
	440	if (_gclk0 != NULL) {
	441	clk_put(_gclk0);
	442	_gclk0 = NULL;
	443	}
9aaca968 GW	444	return ret;
	445	}
	446
	447
	448	static void __exit playpaq_asoc_exit(void)
	449	{
9aaca968 GW	450	if (_gclk0 != NULL) {
	451	clk_put(_gclk0);
	452	_gclk0 = NULL;
	453	}
	454	if (_pll0 != NULL) {
	455	clk_put(_pll0);
	456	_pll0 = NULL;
	457	}
	458
	459	#if defined CONFIG_AT32_ENHANCED_PORTMUX
	460	at32_free_pin(MCLK_PIN);
	461	#endif
	462
	463	platform_device_unregister(playpaq_snd_device);
	464	playpaq_snd_device = NULL;
	465	}
	466
	467	module_init(playpaq_asoc_init);
	468	module_exit(playpaq_asoc_exit);
	469
	470	MODULE_AUTHOR("Geoffrey Wossum <gwossum@acm.org>");
	471	MODULE_DESCRIPTION("ASoC machine driver for LRS PlayPaq");
	472	MODULE_LICENSE("GPL");