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5b99e6cc SG |
1 | /* |
2 | * sam9g20_wm8731 -- SoC audio for AT91SAM9G20-based | |
3 | * ATMEL AT91SAM9G20ek board. | |
4 | * | |
5 | * Copyright (C) 2005 SAN People | |
6 | * Copyright (C) 2008 Atmel | |
7 | * | |
8 | * Authors: Sedji Gaouaou <sedji.gaouaou@atmel.com> | |
9 | * | |
10 | * Based on ati_b1_wm8731.c by: | |
11 | * Frank Mandarino <fmandarino@endrelia.com> | |
12 | * Copyright 2006 Endrelia Technologies Inc. | |
13 | * Based on corgi.c by: | |
14 | * Copyright 2005 Wolfson Microelectronics PLC. | |
15 | * Copyright 2005 Openedhand Ltd. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License as published by | |
19 | * the Free Software Foundation; either version 2 of the License, or | |
20 | * (at your option) any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software | |
29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
30 | */ | |
31 | ||
32 | #include <linux/module.h> | |
33 | #include <linux/moduleparam.h> | |
5b99e6cc SG |
34 | #include <linux/kernel.h> |
35 | #include <linux/clk.h> | |
36 | #include <linux/timer.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/platform_device.h> | |
39 | ||
40 | #include <linux/atmel-ssc.h> | |
41 | ||
42 | #include <sound/core.h> | |
43 | #include <sound/pcm.h> | |
44 | #include <sound/pcm_params.h> | |
45 | #include <sound/soc.h> | |
46 | #include <sound/soc-dapm.h> | |
47 | ||
40135ea0 | 48 | #include <asm/mach-types.h> |
5b99e6cc SG |
49 | #include <mach/hardware.h> |
50 | #include <mach/gpio.h> | |
51 | ||
52 | #include "../codecs/wm8731.h" | |
53 | #include "atmel-pcm.h" | |
54 | #include "atmel_ssc_dai.h" | |
55 | ||
5de7f9b2 MB |
56 | #define MCLK_RATE 12000000 |
57 | ||
58 | static struct clk *mclk; | |
5b99e6cc SG |
59 | |
60 | static int at91sam9g20ek_startup(struct snd_pcm_substream *substream) | |
61 | { | |
62 | struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); | |
63 | struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; | |
64 | int ret; | |
65 | ||
5b99e6cc | 66 | ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK, |
5de7f9b2 MB |
67 | MCLK_RATE, SND_SOC_CLOCK_IN); |
68 | if (ret < 0) { | |
69 | clk_disable(mclk); | |
5b99e6cc | 70 | return ret; |
5de7f9b2 | 71 | } |
5b99e6cc SG |
72 | |
73 | return 0; | |
74 | } | |
75 | ||
76 | static void at91sam9g20ek_shutdown(struct snd_pcm_substream *substream) | |
77 | { | |
78 | struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream); | |
79 | ||
80 | dev_dbg(rtd->socdev->dev, "shutdown"); | |
81 | } | |
82 | ||
83 | static int at91sam9g20ek_hw_params(struct snd_pcm_substream *substream, | |
84 | struct snd_pcm_hw_params *params) | |
85 | { | |
86 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
87 | struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; | |
88 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | |
89 | struct atmel_ssc_info *ssc_p = cpu_dai->private_data; | |
90 | struct ssc_device *ssc = ssc_p->ssc; | |
91 | int ret; | |
92 | ||
93 | unsigned int rate; | |
94 | int cmr_div, period; | |
95 | ||
96 | if (ssc == NULL) { | |
97 | printk(KERN_INFO "at91sam9g20ek_hw_params: ssc is NULL!\n"); | |
98 | return -EINVAL; | |
99 | } | |
100 | ||
101 | /* set codec DAI configuration */ | |
102 | ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | | |
103 | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); | |
104 | if (ret < 0) | |
105 | return ret; | |
106 | ||
107 | /* set cpu DAI configuration */ | |
108 | ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | | |
109 | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); | |
110 | if (ret < 0) | |
111 | return ret; | |
112 | ||
113 | /* | |
114 | * The SSC clock dividers depend on the sample rate. The CMR.DIV | |
115 | * field divides the system master clock MCK to drive the SSC TK | |
116 | * signal which provides the codec BCLK. The TCMR.PERIOD and | |
117 | * RCMR.PERIOD fields further divide the BCLK signal to drive | |
118 | * the SSC TF and RF signals which provide the codec DACLRC and | |
119 | * ADCLRC clocks. | |
120 | * | |
121 | * The dividers were determined through trial and error, where a | |
122 | * CMR.DIV value is chosen such that the resulting BCLK value is | |
123 | * divisible, or almost divisible, by (2 * sample rate), and then | |
124 | * the TCMR.PERIOD or RCMR.PERIOD is BCLK / (2 * sample rate) - 1. | |
125 | */ | |
126 | rate = params_rate(params); | |
127 | ||
128 | switch (rate) { | |
129 | case 8000: | |
130 | cmr_div = 55; /* BCLK = 133MHz/(2*55) = 1.209MHz */ | |
131 | period = 74; /* LRC = BCLK/(2*(74+1)) ~= 8060,6Hz */ | |
132 | break; | |
133 | case 11025: | |
134 | cmr_div = 67; /* BCLK = 133MHz/(2*60) = 1.108MHz */ | |
135 | period = 45; /* LRC = BCLK/(2*(49+1)) = 11083,3Hz */ | |
136 | break; | |
137 | case 16000: | |
138 | cmr_div = 63; /* BCLK = 133MHz/(2*63) = 1.055MHz */ | |
139 | period = 32; /* LRC = BCLK/(2*(32+1)) = 15993,2Hz */ | |
140 | break; | |
141 | case 22050: | |
142 | cmr_div = 52; /* BCLK = 133MHz/(2*52) = 1.278MHz */ | |
143 | period = 28; /* LRC = BCLK/(2*(28+1)) = 22049Hz */ | |
144 | break; | |
145 | case 32000: | |
146 | cmr_div = 66; /* BCLK = 133MHz/(2*66) = 1.007MHz */ | |
147 | period = 15; /* LRC = BCLK/(2*(15+1)) = 31486,742Hz */ | |
148 | break; | |
149 | case 44100: | |
150 | cmr_div = 29; /* BCLK = 133MHz/(2*29) = 2.293MHz */ | |
151 | period = 25; /* LRC = BCLK/(2*(25+1)) = 44098Hz */ | |
152 | break; | |
153 | case 48000: | |
154 | cmr_div = 33; /* BCLK = 133MHz/(2*33) = 2.015MHz */ | |
155 | period = 20; /* LRC = BCLK/(2*(20+1)) = 47979,79Hz */ | |
156 | break; | |
157 | case 88200: | |
158 | cmr_div = 29; /* BCLK = 133MHz/(2*29) = 2.293MHz */ | |
159 | period = 12; /* LRC = BCLK/(2*(12+1)) = 88196Hz */ | |
160 | break; | |
161 | case 96000: | |
162 | cmr_div = 23; /* BCLK = 133MHz/(2*23) = 2.891MHz */ | |
163 | period = 14; /* LRC = BCLK/(2*(14+1)) = 96376Hz */ | |
164 | break; | |
165 | default: | |
166 | printk(KERN_WARNING "unsupported rate %d" | |
167 | " on at91sam9g20ek board\n", rate); | |
168 | return -EINVAL; | |
169 | } | |
170 | ||
171 | /* set the MCK divider for BCLK */ | |
172 | ret = snd_soc_dai_set_clkdiv(cpu_dai, ATMEL_SSC_CMR_DIV, cmr_div); | |
173 | if (ret < 0) | |
174 | return ret; | |
175 | ||
176 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
177 | /* set the BCLK divider for DACLRC */ | |
178 | ret = snd_soc_dai_set_clkdiv(cpu_dai, | |
179 | ATMEL_SSC_TCMR_PERIOD, period); | |
180 | } else { | |
181 | /* set the BCLK divider for ADCLRC */ | |
182 | ret = snd_soc_dai_set_clkdiv(cpu_dai, | |
183 | ATMEL_SSC_RCMR_PERIOD, period); | |
184 | } | |
185 | if (ret < 0) | |
186 | return ret; | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | static struct snd_soc_ops at91sam9g20ek_ops = { | |
192 | .startup = at91sam9g20ek_startup, | |
193 | .hw_params = at91sam9g20ek_hw_params, | |
194 | .shutdown = at91sam9g20ek_shutdown, | |
195 | }; | |
196 | ||
5de7f9b2 MB |
197 | static int at91sam9g20ek_set_bias_level(struct snd_soc_card *card, |
198 | enum snd_soc_bias_level level) | |
199 | { | |
200 | static int mclk_on; | |
201 | int ret = 0; | |
202 | ||
203 | switch (level) { | |
204 | case SND_SOC_BIAS_ON: | |
205 | case SND_SOC_BIAS_PREPARE: | |
206 | if (!mclk_on) | |
207 | ret = clk_enable(mclk); | |
208 | if (ret == 0) | |
209 | mclk_on = 1; | |
210 | break; | |
211 | ||
212 | case SND_SOC_BIAS_OFF: | |
213 | case SND_SOC_BIAS_STANDBY: | |
214 | if (mclk_on) | |
215 | clk_disable(mclk); | |
216 | mclk_on = 0; | |
217 | break; | |
218 | } | |
219 | ||
220 | return ret; | |
221 | } | |
5b99e6cc SG |
222 | |
223 | static const struct snd_soc_dapm_widget at91sam9g20ek_dapm_widgets[] = { | |
224 | SND_SOC_DAPM_MIC("Int Mic", NULL), | |
225 | SND_SOC_DAPM_SPK("Ext Spk", NULL), | |
226 | }; | |
227 | ||
228 | static const struct snd_soc_dapm_route intercon[] = { | |
229 | ||
230 | /* speaker connected to LHPOUT */ | |
231 | {"Ext Spk", NULL, "LHPOUT"}, | |
232 | ||
233 | /* mic is connected to Mic Jack, with WM8731 Mic Bias */ | |
234 | {"MICIN", NULL, "Mic Bias"}, | |
235 | {"Mic Bias", NULL, "Int Mic"}, | |
236 | }; | |
237 | ||
238 | /* | |
239 | * Logic for a wm8731 as connected on a at91sam9g20ek board. | |
240 | */ | |
241 | static int at91sam9g20ek_wm8731_init(struct snd_soc_codec *codec) | |
242 | { | |
243 | printk(KERN_DEBUG | |
244 | "at91sam9g20ek_wm8731 " | |
245 | ": at91sam9g20ek_wm8731_init() called\n"); | |
246 | ||
247 | /* Add specific widgets */ | |
248 | snd_soc_dapm_new_controls(codec, at91sam9g20ek_dapm_widgets, | |
249 | ARRAY_SIZE(at91sam9g20ek_dapm_widgets)); | |
250 | /* Set up specific audio path interconnects */ | |
251 | snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); | |
252 | ||
253 | /* not connected */ | |
8c0bad7f MB |
254 | snd_soc_dapm_nc_pin(codec, "RLINEIN"); |
255 | snd_soc_dapm_nc_pin(codec, "LLINEIN"); | |
5b99e6cc SG |
256 | |
257 | /* always connected */ | |
258 | snd_soc_dapm_enable_pin(codec, "Int Mic"); | |
259 | snd_soc_dapm_enable_pin(codec, "Ext Spk"); | |
260 | ||
261 | snd_soc_dapm_sync(codec); | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
266 | static struct snd_soc_dai_link at91sam9g20ek_dai = { | |
267 | .name = "WM8731", | |
268 | .stream_name = "WM8731 PCM", | |
269 | .cpu_dai = &atmel_ssc_dai[0], | |
270 | .codec_dai = &wm8731_dai, | |
271 | .init = at91sam9g20ek_wm8731_init, | |
272 | .ops = &at91sam9g20ek_ops, | |
273 | }; | |
274 | ||
87506549 | 275 | static struct snd_soc_card snd_soc_at91sam9g20ek = { |
7ee75380 | 276 | .name = "AT91SAMG20-EK", |
87689d56 | 277 | .platform = &atmel_soc_platform, |
5b99e6cc SG |
278 | .dai_link = &at91sam9g20ek_dai, |
279 | .num_links = 1, | |
5de7f9b2 | 280 | .set_bias_level = at91sam9g20ek_set_bias_level, |
5b99e6cc SG |
281 | }; |
282 | ||
283 | static struct wm8731_setup_data at91sam9g20ek_wm8731_setup = { | |
284 | .i2c_bus = 0, | |
285 | .i2c_address = 0x1b, | |
286 | }; | |
287 | ||
288 | static struct snd_soc_device at91sam9g20ek_snd_devdata = { | |
87506549 | 289 | .card = &snd_soc_at91sam9g20ek, |
5b99e6cc SG |
290 | .codec_dev = &soc_codec_dev_wm8731, |
291 | .codec_data = &at91sam9g20ek_wm8731_setup, | |
292 | }; | |
293 | ||
294 | static struct platform_device *at91sam9g20ek_snd_device; | |
295 | ||
296 | static int __init at91sam9g20ek_init(void) | |
297 | { | |
298 | struct atmel_ssc_info *ssc_p = at91sam9g20ek_dai.cpu_dai->private_data; | |
299 | struct ssc_device *ssc = NULL; | |
5de7f9b2 | 300 | struct clk *pllb; |
5b99e6cc SG |
301 | int ret; |
302 | ||
40135ea0 MB |
303 | if (!machine_is_at91sam9g20ek()) |
304 | return -ENODEV; | |
305 | ||
5de7f9b2 MB |
306 | /* |
307 | * Codec MCLK is supplied by PCK0 - set it up. | |
308 | */ | |
309 | mclk = clk_get(NULL, "pck0"); | |
310 | if (IS_ERR(mclk)) { | |
311 | printk(KERN_ERR "ASoC: Failed to get MCLK\n"); | |
312 | ret = PTR_ERR(mclk); | |
313 | goto err; | |
314 | } | |
315 | ||
316 | pllb = clk_get(NULL, "pllb"); | |
317 | if (IS_ERR(mclk)) { | |
318 | printk(KERN_ERR "ASoC: Failed to get PLLB\n"); | |
319 | ret = PTR_ERR(mclk); | |
320 | goto err_mclk; | |
321 | } | |
322 | ret = clk_set_parent(mclk, pllb); | |
323 | clk_put(pllb); | |
324 | if (ret != 0) { | |
325 | printk(KERN_ERR "ASoC: Failed to set MCLK parent\n"); | |
326 | goto err_mclk; | |
327 | } | |
328 | ||
329 | clk_set_rate(mclk, MCLK_RATE); | |
330 | ||
5b99e6cc SG |
331 | /* |
332 | * Request SSC device | |
333 | */ | |
334 | ssc = ssc_request(0); | |
335 | if (IS_ERR(ssc)) { | |
d6943541 | 336 | printk(KERN_ERR "ASoC: Failed to request SSC 0\n"); |
5b99e6cc SG |
337 | ret = PTR_ERR(ssc); |
338 | ssc = NULL; | |
339 | goto err_ssc; | |
340 | } | |
341 | ssc_p->ssc = ssc; | |
342 | ||
343 | at91sam9g20ek_snd_device = platform_device_alloc("soc-audio", -1); | |
344 | if (!at91sam9g20ek_snd_device) { | |
d6943541 | 345 | printk(KERN_ERR "ASoC: Platform device allocation failed\n"); |
5b99e6cc SG |
346 | ret = -ENOMEM; |
347 | } | |
348 | ||
349 | platform_set_drvdata(at91sam9g20ek_snd_device, | |
350 | &at91sam9g20ek_snd_devdata); | |
351 | at91sam9g20ek_snd_devdata.dev = &at91sam9g20ek_snd_device->dev; | |
352 | ||
353 | ret = platform_device_add(at91sam9g20ek_snd_device); | |
354 | if (ret) { | |
d6943541 | 355 | printk(KERN_ERR "ASoC: Platform device allocation failed\n"); |
5b99e6cc SG |
356 | platform_device_put(at91sam9g20ek_snd_device); |
357 | } | |
358 | ||
359 | return ret; | |
360 | ||
361 | err_ssc: | |
5de7f9b2 MB |
362 | err_mclk: |
363 | clk_put(mclk); | |
364 | mclk = NULL; | |
365 | err: | |
5b99e6cc SG |
366 | return ret; |
367 | } | |
368 | ||
369 | static void __exit at91sam9g20ek_exit(void) | |
370 | { | |
371 | struct atmel_ssc_info *ssc_p = at91sam9g20ek_dai.cpu_dai->private_data; | |
372 | struct ssc_device *ssc; | |
373 | ||
374 | if (ssc_p != NULL) { | |
375 | ssc = ssc_p->ssc; | |
376 | if (ssc != NULL) | |
377 | ssc_free(ssc); | |
378 | ssc_p->ssc = NULL; | |
379 | } | |
380 | ||
381 | platform_device_unregister(at91sam9g20ek_snd_device); | |
382 | at91sam9g20ek_snd_device = NULL; | |
5de7f9b2 MB |
383 | clk_put(mclk); |
384 | mclk = NULL; | |
5b99e6cc SG |
385 | } |
386 | ||
387 | module_init(at91sam9g20ek_init); | |
388 | module_exit(at91sam9g20ek_exit); | |
389 | ||
390 | /* Module information */ | |
391 | MODULE_AUTHOR("Sedji Gaouaou <sedji.gaouaou@atmel.com>"); | |
392 | MODULE_DESCRIPTION("ALSA SoC AT91SAM9G20EK_WM8731"); | |
393 | MODULE_LICENSE("GPL"); |