[mirror_ubuntu-zesty-kernel.git] / sound / soc / bcm / bcm2835-i2s.c

/*
 * ALSA SoC I2S Audio Layer for Broadcom BCM2835 SoC
 *
 * Author:	Florian Meier <florian.meier@koalo.de>
 *		Copyright 2013
 *
 * Based on
 *	Raspberry Pi PCM I2S ALSA Driver
 *	Copyright (c) by Phil Poole 2013
 *
 *	ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
 *      Vladimir Barinov, <vbarinov@embeddedalley.com>
 *	Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
 *
 *	OMAP ALSA SoC DAI driver using McBSP port
 *	Copyright (C) 2008 Nokia Corporation
 *	Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
 *		 Peter Ujfalusi <peter.ujfalusi@ti.com>
 *
 *	Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
 *	Author: Timur Tabi <timur@freescale.com>
 *	Copyright 2007-2010 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/slab.h>

#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/initval.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>

/* I2S registers */
#define BCM2835_I2S_CS_A_REG		0x00
#define BCM2835_I2S_FIFO_A_REG		0x04
#define BCM2835_I2S_MODE_A_REG		0x08
#define BCM2835_I2S_RXC_A_REG		0x0c
#define BCM2835_I2S_TXC_A_REG		0x10
#define BCM2835_I2S_DREQ_A_REG		0x14
#define BCM2835_I2S_INTEN_A_REG	0x18
#define BCM2835_I2S_INTSTC_A_REG	0x1c
#define BCM2835_I2S_GRAY_REG		0x20

/* I2S register settings */
#define BCM2835_I2S_STBY		BIT(25)
#define BCM2835_I2S_SYNC		BIT(24)
#define BCM2835_I2S_RXSEX		BIT(23)
#define BCM2835_I2S_RXF		BIT(22)
#define BCM2835_I2S_TXE		BIT(21)
#define BCM2835_I2S_RXD		BIT(20)
#define BCM2835_I2S_TXD		BIT(19)
#define BCM2835_I2S_RXR		BIT(18)
#define BCM2835_I2S_TXW		BIT(17)
#define BCM2835_I2S_CS_RXERR		BIT(16)
#define BCM2835_I2S_CS_TXERR		BIT(15)
#define BCM2835_I2S_RXSYNC		BIT(14)
#define BCM2835_I2S_TXSYNC		BIT(13)
#define BCM2835_I2S_DMAEN		BIT(9)
#define BCM2835_I2S_RXTHR(v)		((v) << 7)
#define BCM2835_I2S_TXTHR(v)		((v) << 5)
#define BCM2835_I2S_RXCLR		BIT(4)
#define BCM2835_I2S_TXCLR		BIT(3)
#define BCM2835_I2S_TXON		BIT(2)
#define BCM2835_I2S_RXON		BIT(1)
#define BCM2835_I2S_EN			(1)

#define BCM2835_I2S_CLKDIS		BIT(28)
#define BCM2835_I2S_PDMN		BIT(27)
#define BCM2835_I2S_PDME		BIT(26)
#define BCM2835_I2S_FRXP		BIT(25)
#define BCM2835_I2S_FTXP		BIT(24)
#define BCM2835_I2S_CLKM		BIT(23)
#define BCM2835_I2S_CLKI		BIT(22)
#define BCM2835_I2S_FSM		BIT(21)
#define BCM2835_I2S_FSI		BIT(20)
#define BCM2835_I2S_FLEN(v)		((v) << 10)
#define BCM2835_I2S_FSLEN(v)		(v)

#define BCM2835_I2S_CHWEX		BIT(15)
#define BCM2835_I2S_CHEN		BIT(14)
#define BCM2835_I2S_CHPOS(v)		((v) << 4)
#define BCM2835_I2S_CHWID(v)		(v)
#define BCM2835_I2S_CH1(v)		((v) << 16)
#define BCM2835_I2S_CH2(v)		(v)

#define BCM2835_I2S_TX_PANIC(v)	((v) << 24)
#define BCM2835_I2S_RX_PANIC(v)	((v) << 16)
#define BCM2835_I2S_TX(v)		((v) << 8)
#define BCM2835_I2S_RX(v)		(v)

#define BCM2835_I2S_INT_RXERR		BIT(3)
#define BCM2835_I2S_INT_TXERR		BIT(2)
#define BCM2835_I2S_INT_RXR		BIT(1)
#define BCM2835_I2S_INT_TXW		BIT(0)

/* General device struct */
struct bcm2835_i2s_dev {
	struct device				*dev;
	struct snd_dmaengine_dai_dma_data	dma_data[2];
	unsigned int				fmt;
	unsigned int				bclk_ratio;

	struct regmap				*i2s_regmap;
	struct clk				*clk;
	bool					clk_prepared;
};

static void bcm2835_i2s_start_clock(struct bcm2835_i2s_dev *dev)
{
	unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;

	if (dev->clk_prepared)
		return;

	switch (master) {
	case SND_SOC_DAIFMT_CBS_CFS:
	case SND_SOC_DAIFMT_CBS_CFM:
		clk_prepare_enable(dev->clk);
		dev->clk_prepared = true;
		break;
	default:
		break;
	}
}

static void bcm2835_i2s_stop_clock(struct bcm2835_i2s_dev *dev)
{
	if (dev->clk_prepared)
		clk_disable_unprepare(dev->clk);
	dev->clk_prepared = false;
}

static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev,
				    bool tx, bool rx)
{
	int timeout = 1000;
	uint32_t syncval;
	uint32_t csreg;
	uint32_t i2s_active_state;
	bool clk_was_prepared;
	uint32_t off;
	uint32_t clr;

	off =  tx ? BCM2835_I2S_TXON : 0;
	off |= rx ? BCM2835_I2S_RXON : 0;

	clr =  tx ? BCM2835_I2S_TXCLR : 0;
	clr |= rx ? BCM2835_I2S_RXCLR : 0;

	/* Backup the current state */
	regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
	i2s_active_state = csreg & (BCM2835_I2S_RXON | BCM2835_I2S_TXON);

	/* Start clock if not running */
	clk_was_prepared = dev->clk_prepared;
	if (!clk_was_prepared)
		bcm2835_i2s_start_clock(dev);

	/* Stop I2S module */
	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, off, 0);

	/*
	 * Clear the FIFOs
	 * Requires at least 2 PCM clock cycles to take effect
	 */
	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, clr, clr);

	/* Wait for 2 PCM clock cycles */

	/*
	 * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
	 * FIXME: This does not seem to work for slave mode!
	 */
	regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &syncval);
	syncval &= BCM2835_I2S_SYNC;

	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
			BCM2835_I2S_SYNC, ~syncval);

	/* Wait for the SYNC flag changing it's state */
	while (--timeout) {
		regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
		if ((csreg & BCM2835_I2S_SYNC) != syncval)
			break;
	}

	if (!timeout)
		dev_err(dev->dev, "I2S SYNC error!\n");

	/* Stop clock if it was not running before */
	if (!clk_was_prepared)
		bcm2835_i2s_stop_clock(dev);

	/* Restore I2S state */
	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
			BCM2835_I2S_RXON | BCM2835_I2S_TXON, i2s_active_state);
}

static int bcm2835_i2s_set_dai_fmt(struct snd_soc_dai *dai,
				      unsigned int fmt)
{
	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	dev->fmt = fmt;
	return 0;
}

static int bcm2835_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
				      unsigned int ratio)
{
	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	dev->bclk_ratio = ratio;
	return 0;
}

static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
				 struct snd_pcm_hw_params *params,
				 struct snd_soc_dai *dai)
{
	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	unsigned int sampling_rate = params_rate(params);
	unsigned int data_length, data_delay, bclk_ratio;
	unsigned int ch1pos, ch2pos, mode, format;
	uint32_t csreg;

	/*
	 * If a stream is already enabled,
	 * the registers are already set properly.
	 */
	regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);

	if (csreg & (BCM2835_I2S_TXON | BCM2835_I2S_RXON))
		return 0;

	/*
	 * Adjust the data length according to the format.
	 * We prefill the half frame length with an integer
	 * divider of 2400 as explained at the clock settings.
	 * Maybe it is overwritten there, if the Integer mode
	 * does not apply.
	 */
	switch (params_format(params)) {
	case SNDRV_PCM_FORMAT_S16_LE:
		data_length = 16;
		break;
	case SNDRV_PCM_FORMAT_S32_LE:
		data_length = 32;
		break;
	default:
		return -EINVAL;
	}

	/* If bclk_ratio already set, use that one. */
	if (dev->bclk_ratio)
		bclk_ratio = dev->bclk_ratio;
	else
		/* otherwise calculate a fitting block ratio */
		bclk_ratio = 2 * data_length;

	/* set target clock rate*/
	clk_set_rate(dev->clk, sampling_rate * bclk_ratio);

	/* Setup the frame format */
	format = BCM2835_I2S_CHEN;

	if (data_length > 24)
		format |= BCM2835_I2S_CHWEX;

	format |= BCM2835_I2S_CHWID((data_length-8)&0xf);

	switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		data_delay = 1;
		break;
	default:
		/*
		 * TODO
		 * Others are possible but are not implemented at the moment.
		 */
		dev_err(dev->dev, "%s:bad format\n", __func__);
		return -EINVAL;
	}

	ch1pos = data_delay;
	ch2pos = bclk_ratio / 2 + data_delay;

	switch (params_channels(params)) {
	case 2:
		format = BCM2835_I2S_CH1(format) | BCM2835_I2S_CH2(format);
		format |= BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(ch1pos));
		format |= BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(ch2pos));
		break;
	default:
		return -EINVAL;
	}

	/*
	 * Set format for both streams.
	 * We cannot set another frame length
	 * (and therefore word length) anyway,
	 * so the format will be the same.
	 */
	regmap_write(dev->i2s_regmap, BCM2835_I2S_RXC_A_REG, format);
	regmap_write(dev->i2s_regmap, BCM2835_I2S_TXC_A_REG, format);

	/* Setup the I2S mode */
	mode = 0;

	if (data_length <= 16) {
		/*
		 * Use frame packed mode (2 channels per 32 bit word)
		 * We cannot set another frame length in the second stream
		 * (and therefore word length) anyway,
		 * so the format will be the same.
		 */
		mode |= BCM2835_I2S_FTXP | BCM2835_I2S_FRXP;
	}

	mode |= BCM2835_I2S_FLEN(bclk_ratio - 1);
	mode |= BCM2835_I2S_FSLEN(bclk_ratio / 2);

	/* Master or slave? */
	switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		/* CPU is master */
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		/*
		 * CODEC is bit clock master
		 * CPU is frame master
		 */
		mode |= BCM2835_I2S_CLKM;
		break;
	case SND_SOC_DAIFMT_CBS_CFM:
		/*
		 * CODEC is frame master
		 * CPU is bit clock master
		 */
		mode |= BCM2835_I2S_FSM;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		/* CODEC is master */
		mode |= BCM2835_I2S_CLKM;
		mode |= BCM2835_I2S_FSM;
		break;
	default:
		dev_err(dev->dev, "%s:bad master\n", __func__);
		return -EINVAL;
	}

	/*
	 * Invert clocks?
	 *
	 * The BCM approach seems to be inverted to the classical I2S approach.
	 */
	switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_NB_NF:
		/* None. Therefore, both for BCM */
		mode |= BCM2835_I2S_CLKI;
		mode |= BCM2835_I2S_FSI;
		break;
	case SND_SOC_DAIFMT_IB_IF:
		/* Both. Therefore, none for BCM */
		break;
	case SND_SOC_DAIFMT_NB_IF:
		/*
		 * Invert only frame sync. Therefore,
		 * invert only bit clock for BCM
		 */
		mode |= BCM2835_I2S_CLKI;
		break;
	case SND_SOC_DAIFMT_IB_NF:
		/*
		 * Invert only bit clock. Therefore,
		 * invert only frame sync for BCM
		 */
		mode |= BCM2835_I2S_FSI;
		break;
	default:
		return -EINVAL;
	}

	regmap_write(dev->i2s_regmap, BCM2835_I2S_MODE_A_REG, mode);

	/* Setup the DMA parameters */
	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
			BCM2835_I2S_RXTHR(1)
			| BCM2835_I2S_TXTHR(1)
			| BCM2835_I2S_DMAEN, 0xffffffff);

	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_DREQ_A_REG,
			  BCM2835_I2S_TX_PANIC(0x10)
			| BCM2835_I2S_RX_PANIC(0x30)
			| BCM2835_I2S_TX(0x30)
			| BCM2835_I2S_RX(0x20), 0xffffffff);

	/* Clear FIFOs */
	bcm2835_i2s_clear_fifos(dev, true, true);

	return 0;
}

static int bcm2835_i2s_prepare(struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
{
	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	uint32_t cs_reg;

	bcm2835_i2s_start_clock(dev);

	/*
	 * Clear both FIFOs if the one that should be started
	 * is not empty at the moment. This should only happen
	 * after overrun. Otherwise, hw_params would have cleared
	 * the FIFO.
	 */
	regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &cs_reg);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
			&& !(cs_reg & BCM2835_I2S_TXE))
		bcm2835_i2s_clear_fifos(dev, true, false);
	else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
			&& (cs_reg & BCM2835_I2S_RXD))
		bcm2835_i2s_clear_fifos(dev, false, true);

	return 0;
}

static void bcm2835_i2s_stop(struct bcm2835_i2s_dev *dev,
		struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
{
	uint32_t mask;

	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
		mask = BCM2835_I2S_RXON;
	else
		mask = BCM2835_I2S_TXON;

	regmap_update_bits(dev->i2s_regmap,
			BCM2835_I2S_CS_A_REG, mask, 0);

	/* Stop also the clock when not SND_SOC_DAIFMT_CONT */
	if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT))
		bcm2835_i2s_stop_clock(dev);
}

static int bcm2835_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
			       struct snd_soc_dai *dai)
{
	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	uint32_t mask;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		bcm2835_i2s_start_clock(dev);

		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
			mask = BCM2835_I2S_RXON;
		else
			mask = BCM2835_I2S_TXON;

		regmap_update_bits(dev->i2s_regmap,
				BCM2835_I2S_CS_A_REG, mask, mask);
		break;

	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		bcm2835_i2s_stop(dev, substream, dai);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int bcm2835_i2s_startup(struct snd_pcm_substream *substream,
			       struct snd_soc_dai *dai)
{
	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);

	if (dai->active)
		return 0;

	/* Should this still be running stop it */
	bcm2835_i2s_stop_clock(dev);

	/* Enable PCM block */
	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
			BCM2835_I2S_EN, BCM2835_I2S_EN);

	/*
	 * Disable STBY.
	 * Requires at least 4 PCM clock cycles to take effect.
	 */
	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
			BCM2835_I2S_STBY, BCM2835_I2S_STBY);

	return 0;
}

static void bcm2835_i2s_shutdown(struct snd_pcm_substream *substream,
		struct snd_soc_dai *dai)
{
	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);

	bcm2835_i2s_stop(dev, substream, dai);

	/* If both streams are stopped, disable module and clock */
	if (dai->active)
		return;

	/* Disable the module */
	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
			BCM2835_I2S_EN, 0);

	/*
	 * Stopping clock is necessary, because stop does
	 * not stop the clock when SND_SOC_DAIFMT_CONT
	 */
	bcm2835_i2s_stop_clock(dev);
}

static const struct snd_soc_dai_ops bcm2835_i2s_dai_ops = {
	.startup	= bcm2835_i2s_startup,
	.shutdown	= bcm2835_i2s_shutdown,
	.prepare	= bcm2835_i2s_prepare,
	.trigger	= bcm2835_i2s_trigger,
	.hw_params	= bcm2835_i2s_hw_params,
	.set_fmt	= bcm2835_i2s_set_dai_fmt,
	.set_bclk_ratio	= bcm2835_i2s_set_dai_bclk_ratio,
};

static int bcm2835_i2s_dai_probe(struct snd_soc_dai *dai)
{
	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);

	snd_soc_dai_init_dma_data(dai,
			&dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
			&dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]);

	return 0;
}

static struct snd_soc_dai_driver bcm2835_i2s_dai = {
	.name	= "bcm2835-i2s",
	.probe	= bcm2835_i2s_dai_probe,
	.playback = {
		.channels_min = 2,
		.channels_max = 2,
		.rates =	SNDRV_PCM_RATE_8000_192000,
		.formats =	SNDRV_PCM_FMTBIT_S16_LE
				| SNDRV_PCM_FMTBIT_S32_LE
		},
	.capture = {
		.channels_min = 2,
		.channels_max = 2,
		.rates =	SNDRV_PCM_RATE_8000_192000,
		.formats =	SNDRV_PCM_FMTBIT_S16_LE
				| SNDRV_PCM_FMTBIT_S32_LE
		},
	.ops = &bcm2835_i2s_dai_ops,
	.symmetric_rates = 1
};

static bool bcm2835_i2s_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case BCM2835_I2S_CS_A_REG:
	case BCM2835_I2S_FIFO_A_REG:
	case BCM2835_I2S_INTSTC_A_REG:
	case BCM2835_I2S_GRAY_REG:
		return true;
	default:
		return false;
	};
}

static bool bcm2835_i2s_precious_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case BCM2835_I2S_FIFO_A_REG:
		return true;
	default:
		return false;
	};
}

static const struct regmap_config bcm2835_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = BCM2835_I2S_GRAY_REG,
	.precious_reg = bcm2835_i2s_precious_reg,
	.volatile_reg = bcm2835_i2s_volatile_reg,
	.cache_type = REGCACHE_RBTREE,
};

static const struct snd_soc_component_driver bcm2835_i2s_component = {
	.name		= "bcm2835-i2s-comp",
};

static int bcm2835_i2s_probe(struct platform_device *pdev)
{
	struct bcm2835_i2s_dev *dev;
	int ret;
	struct resource *mem;
	void __iomem *base;
	const __be32 *addr;
	dma_addr_t dma_base;

	dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
			   GFP_KERNEL);
	if (!dev)
		return -ENOMEM;

	/* get the clock */
	dev->clk_prepared = false;
	dev->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(dev->clk)) {
		dev_err(&pdev->dev, "could not get clk: %ld\n",
			PTR_ERR(dev->clk));
		return PTR_ERR(dev->clk);
	}

	/* Request ioarea */
	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(base))
		return PTR_ERR(base);

	dev->i2s_regmap = devm_regmap_init_mmio(&pdev->dev, base,
				&bcm2835_regmap_config);
	if (IS_ERR(dev->i2s_regmap))
		return PTR_ERR(dev->i2s_regmap);

	/* Set the DMA address - we have to parse DT ourselves */
	addr = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
	if (!addr) {
		dev_err(&pdev->dev, "could not get DMA-register address\n");
		return -EINVAL;
	}
	dma_base = be32_to_cpup(addr);

	dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
		dma_base + BCM2835_I2S_FIFO_A_REG;

	dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
		dma_base + BCM2835_I2S_FIFO_A_REG;

	/* Set the bus width */
	dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
		DMA_SLAVE_BUSWIDTH_4_BYTES;
	dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
		DMA_SLAVE_BUSWIDTH_4_BYTES;

	/* Set burst */
	dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
	dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;

	/* BCLK ratio - use default */
	dev->bclk_ratio = 0;

	/* Store the pdev */
	dev->dev = &pdev->dev;
	dev_set_drvdata(&pdev->dev, dev);

	ret = devm_snd_soc_register_component(&pdev->dev,
			&bcm2835_i2s_component, &bcm2835_i2s_dai, 1);
	if (ret) {
		dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
		return ret;
	}

	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
	if (ret) {
		dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
		return ret;
	}

	return 0;
}

static const struct of_device_id bcm2835_i2s_of_match[] = {
	{ .compatible = "brcm,bcm2835-i2s", },
	{},
};

MODULE_DEVICE_TABLE(of, bcm2835_i2s_of_match);

static struct platform_driver bcm2835_i2s_driver = {
	.probe		= bcm2835_i2s_probe,
	.driver		= {
		.name	= "bcm2835-i2s",
		.of_match_table = bcm2835_i2s_of_match,
	},
};

module_platform_driver(bcm2835_i2s_driver);

MODULE_ALIAS("platform:bcm2835-i2s");
MODULE_DESCRIPTION("BCM2835 I2S interface");
MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
c6aeb7de FM	1	/*
	2	* ALSA SoC I2S Audio Layer for Broadcom BCM2835 SoC
	3	*
	4	* Author: Florian Meier <florian.meier@koalo.de>
	5	* Copyright 2013
	6	*
	7	* Based on
	8	* Raspberry Pi PCM I2S ALSA Driver
	9	* Copyright (c) by Phil Poole 2013
	10	*
	11	* ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
	12	* Vladimir Barinov, <vbarinov@embeddedalley.com>
	13	* Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
	14	*
	15	* OMAP ALSA SoC DAI driver using McBSP port
	16	* Copyright (C) 2008 Nokia Corporation
	17	* Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
	18	* Peter Ujfalusi <peter.ujfalusi@ti.com>
	19	*
	20	* Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
	21	* Author: Timur Tabi <timur@freescale.com>
	22	* Copyright 2007-2010 Freescale Semiconductor, Inc.
	23	*
	24	* This program is free software; you can redistribute it and/or
	25	* modify it under the terms of the GNU General Public License
	26	* version 2 as published by the Free Software Foundation.
	27	*
	28	* This program is distributed in the hope that it will be useful, but
	29	* WITHOUT ANY WARRANTY; without even the implied warranty of
	30	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	31	* General Public License for more details.
	32	*/
	33
7905f082 MS	34	#include <linux/clk.h>
	35	#include <linux/delay.h>
	36	#include <linux/device.h>
c6aeb7de	37	#include <linux/init.h>
7905f082	38	#include <linux/io.h>
c6aeb7de	39	#include <linux/module.h>
201bd3c6	40	#include <linux/of_address.h>
c6aeb7de	41	#include <linux/slab.h>
c6aeb7de FM	42
c6aeb7de FM	43	#include <sound/core.h>
7905f082 MS	44	#include <sound/dmaengine_pcm.h>
7905f082 MS	45	#include <sound/initval.h>
c6aeb7de FM	46	#include <sound/pcm.h>
c6aeb7de FM	47	#include <sound/pcm_params.h>
c6aeb7de	48	#include <sound/soc.h>
c6aeb7de	49
c6aeb7de FM	50	/* I2S registers */
	51	#define BCM2835_I2S_CS_A_REG 0x00
	52	#define BCM2835_I2S_FIFO_A_REG 0x04
	53	#define BCM2835_I2S_MODE_A_REG 0x08
	54	#define BCM2835_I2S_RXC_A_REG 0x0c
	55	#define BCM2835_I2S_TXC_A_REG 0x10
	56	#define BCM2835_I2S_DREQ_A_REG 0x14
	57	#define BCM2835_I2S_INTEN_A_REG 0x18
	58	#define BCM2835_I2S_INTSTC_A_REG 0x1c
	59	#define BCM2835_I2S_GRAY_REG 0x20
	60
	61	/* I2S register settings */
	62	#define BCM2835_I2S_STBY BIT(25)
	63	#define BCM2835_I2S_SYNC BIT(24)
	64	#define BCM2835_I2S_RXSEX BIT(23)
	65	#define BCM2835_I2S_RXF BIT(22)
	66	#define BCM2835_I2S_TXE BIT(21)
	67	#define BCM2835_I2S_RXD BIT(20)
	68	#define BCM2835_I2S_TXD BIT(19)
	69	#define BCM2835_I2S_RXR BIT(18)
	70	#define BCM2835_I2S_TXW BIT(17)
	71	#define BCM2835_I2S_CS_RXERR BIT(16)
	72	#define BCM2835_I2S_CS_TXERR BIT(15)
	73	#define BCM2835_I2S_RXSYNC BIT(14)
	74	#define BCM2835_I2S_TXSYNC BIT(13)
	75	#define BCM2835_I2S_DMAEN BIT(9)
	76	#define BCM2835_I2S_RXTHR(v) ((v) << 7)
	77	#define BCM2835_I2S_TXTHR(v) ((v) << 5)
	78	#define BCM2835_I2S_RXCLR BIT(4)
	79	#define BCM2835_I2S_TXCLR BIT(3)
	80	#define BCM2835_I2S_TXON BIT(2)
	81	#define BCM2835_I2S_RXON BIT(1)
	82	#define BCM2835_I2S_EN (1)
	83
	84	#define BCM2835_I2S_CLKDIS BIT(28)
	85	#define BCM2835_I2S_PDMN BIT(27)
	86	#define BCM2835_I2S_PDME BIT(26)
	87	#define BCM2835_I2S_FRXP BIT(25)
	88	#define BCM2835_I2S_FTXP BIT(24)
	89	#define BCM2835_I2S_CLKM BIT(23)
	90	#define BCM2835_I2S_CLKI BIT(22)
	91	#define BCM2835_I2S_FSM BIT(21)
	92	#define BCM2835_I2S_FSI BIT(20)
	93	#define BCM2835_I2S_FLEN(v) ((v) << 10)
	94	#define BCM2835_I2S_FSLEN(v) (v)
	95
	96	#define BCM2835_I2S_CHWEX BIT(15)
	97	#define BCM2835_I2S_CHEN BIT(14)
	98	#define BCM2835_I2S_CHPOS(v) ((v) << 4)
	99	#define BCM2835_I2S_CHWID(v) (v)
	100	#define BCM2835_I2S_CH1(v) ((v) << 16)
	101	#define BCM2835_I2S_CH2(v) (v)
	102
	103	#define BCM2835_I2S_TX_PANIC(v) ((v) << 24)
	104	#define BCM2835_I2S_RX_PANIC(v) ((v) << 16)
	105	#define BCM2835_I2S_TX(v) ((v) << 8)
	106	#define BCM2835_I2S_RX(v) (v)
	107
	108	#define BCM2835_I2S_INT_RXERR BIT(3)
	109	#define BCM2835_I2S_INT_TXERR BIT(2)
	110	#define BCM2835_I2S_INT_RXR BIT(1)
	111	#define BCM2835_I2S_INT_TXW BIT(0)
	112
c6aeb7de FM	113	/* General device struct */
	114	struct bcm2835_i2s_dev {
	115	struct device *dev;
	116	struct snd_dmaengine_dai_dma_data dma_data[2];
	117	unsigned int fmt;
	118	unsigned int bclk_ratio;
	119
201bd3c6 MS	120	struct regmap *i2s_regmap;
	121	struct clk *clk;
	122	bool clk_prepared;
c6aeb7de FM	123	};
	124
	125	static void bcm2835_i2s_start_clock(struct bcm2835_i2s_dev *dev)
	126	{
c6aeb7de FM	127	unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
c6aeb7de FM	128
201bd3c6 MS	129	if (dev->clk_prepared)
	130	return;
	131
c6aeb7de FM	132	switch (master) {
	133	case SND_SOC_DAIFMT_CBS_CFS:
	134	case SND_SOC_DAIFMT_CBS_CFM:
201bd3c6 MS	135	clk_prepare_enable(dev->clk);
201bd3c6 MS	136	dev->clk_prepared = true;
c6aeb7de FM	137	break;
	138	default:
	139	break;
	140	}
	141	}
	142
	143	static void bcm2835_i2s_stop_clock(struct bcm2835_i2s_dev *dev)
	144	{
201bd3c6 MS	145	if (dev->clk_prepared)
	146	clk_disable_unprepare(dev->clk);
	147	dev->clk_prepared = false;
c6aeb7de FM	148	}
	149
	150	static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev,
	151	bool tx, bool rx)
	152	{
	153	int timeout = 1000;
	154	uint32_t syncval;
	155	uint32_t csreg;
	156	uint32_t i2s_active_state;
201bd3c6	157	bool clk_was_prepared;
c6aeb7de FM	158	uint32_t off;
	159	uint32_t clr;
	160
	161	off = tx ? BCM2835_I2S_TXON : 0;
	162	off \|= rx ? BCM2835_I2S_RXON : 0;
	163
	164	clr = tx ? BCM2835_I2S_TXCLR : 0;
	165	clr \|= rx ? BCM2835_I2S_RXCLR : 0;
	166
	167	/* Backup the current state */
	168	regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
	169	i2s_active_state = csreg & (BCM2835_I2S_RXON \| BCM2835_I2S_TXON);
	170
c6aeb7de	171	/* Start clock if not running */
201bd3c6 MS	172	clk_was_prepared = dev->clk_prepared;
	173	if (!clk_was_prepared)
	174	bcm2835_i2s_start_clock(dev);
c6aeb7de FM	175
	176	/* Stop I2S module */
	177	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, off, 0);
	178
	179	/*
	180	* Clear the FIFOs
	181	* Requires at least 2 PCM clock cycles to take effect
	182	*/
	183	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, clr, clr);
	184
	185	/* Wait for 2 PCM clock cycles */
	186
	187	/*
	188	* Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
	189	* FIXME: This does not seem to work for slave mode!
	190	*/
	191	regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &syncval);
	192	syncval &= BCM2835_I2S_SYNC;
	193
	194	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
	195	BCM2835_I2S_SYNC, ~syncval);
	196
	197	/* Wait for the SYNC flag changing it's state */
	198	while (--timeout) {
	199	regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
	200	if ((csreg & BCM2835_I2S_SYNC) != syncval)
	201	break;
	202	}
	203
	204	if (!timeout)
	205	dev_err(dev->dev, "I2S SYNC error!\n");
	206
	207	/* Stop clock if it was not running before */
201bd3c6	208	if (!clk_was_prepared)
c6aeb7de FM	209	bcm2835_i2s_stop_clock(dev);
	210
	211	/* Restore I2S state */
	212	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
	213	BCM2835_I2S_RXON \| BCM2835_I2S_TXON, i2s_active_state);
	214	}
	215
	216	static int bcm2835_i2s_set_dai_fmt(struct snd_soc_dai *dai,
	217	unsigned int fmt)
	218	{
	219	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	220	dev->fmt = fmt;
	221	return 0;
	222	}
	223
	224	static int bcm2835_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
	225	unsigned int ratio)
	226	{
	227	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	228	dev->bclk_ratio = ratio;
	229	return 0;
	230	}
	231
	232	static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
	233	struct snd_pcm_hw_params *params,
	234	struct snd_soc_dai *dai)
	235	{
	236	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
c6aeb7de FM	237	unsigned int sampling_rate = params_rate(params);
	238	unsigned int data_length, data_delay, bclk_ratio;
	239	unsigned int ch1pos, ch2pos, mode, format;
c6aeb7de FM	240	uint32_t csreg;
	241
	242	/*
	243	* If a stream is already enabled,
	244	* the registers are already set properly.
	245	*/
	246	regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg);
	247
	248	if (csreg & (BCM2835_I2S_TXON \| BCM2835_I2S_RXON))
	249	return 0;
	250
	251	/*
	252	* Adjust the data length according to the format.
	253	* We prefill the half frame length with an integer
	254	* divider of 2400 as explained at the clock settings.
	255	* Maybe it is overwritten there, if the Integer mode
	256	* does not apply.
	257	*/
	258	switch (params_format(params)) {
	259	case SNDRV_PCM_FORMAT_S16_LE:
	260	data_length = 16;
c6aeb7de FM	261	break;
	262	case SNDRV_PCM_FORMAT_S32_LE:
	263	data_length = 32;
c6aeb7de FM	264	break;
	265	default:
	266	return -EINVAL;
	267	}
	268
	269	/* If bclk_ratio already set, use that one. */
	270	if (dev->bclk_ratio)
	271	bclk_ratio = dev->bclk_ratio;
201bd3c6 MS	272	else
	273	/* otherwise calculate a fitting block ratio */
	274	bclk_ratio = 2 * data_length;
c6aeb7de	275
201bd3c6 MS	276	/* set target clock rate*/
201bd3c6 MS	277	clk_set_rate(dev->clk, sampling_rate * bclk_ratio);
c6aeb7de FM	278
	279	/* Setup the frame format */
	280	format = BCM2835_I2S_CHEN;
	281
c5430fe8	282	if (data_length > 24)
c6aeb7de FM	283	format \|= BCM2835_I2S_CHWEX;
	284
	285	format \|= BCM2835_I2S_CHWID((data_length-8)&0xf);
	286
	287	switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	288	case SND_SOC_DAIFMT_I2S:
	289	data_delay = 1;
	290	break;
	291	default:
	292	/*
	293	* TODO
	294	* Others are possible but are not implemented at the moment.
	295	*/
	296	dev_err(dev->dev, "%s:bad format\n", __func__);
	297	return -EINVAL;
	298	}
	299
	300	ch1pos = data_delay;
	301	ch2pos = bclk_ratio / 2 + data_delay;
	302
	303	switch (params_channels(params)) {
	304	case 2:
	305	format = BCM2835_I2S_CH1(format) \| BCM2835_I2S_CH2(format);
	306	format \|= BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(ch1pos));
	307	format \|= BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(ch2pos));
	308	break;
	309	default:
	310	return -EINVAL;
	311	}
	312
	313	/*
	314	* Set format for both streams.
	315	* We cannot set another frame length
	316	* (and therefore word length) anyway,
	317	* so the format will be the same.
	318	*/
	319	regmap_write(dev->i2s_regmap, BCM2835_I2S_RXC_A_REG, format);
	320	regmap_write(dev->i2s_regmap, BCM2835_I2S_TXC_A_REG, format);
	321
	322	/* Setup the I2S mode */
	323	mode = 0;
	324
	325	if (data_length <= 16) {
	326	/*
	327	* Use frame packed mode (2 channels per 32 bit word)
	328	* We cannot set another frame length in the second stream
	329	* (and therefore word length) anyway,
	330	* so the format will be the same.
	331	*/
	332	mode \|= BCM2835_I2S_FTXP \| BCM2835_I2S_FRXP;
	333	}
	334
	335	mode \|= BCM2835_I2S_FLEN(bclk_ratio - 1);
	336	mode \|= BCM2835_I2S_FSLEN(bclk_ratio / 2);
	337
	338	/* Master or slave? */
	339	switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	340	case SND_SOC_DAIFMT_CBS_CFS:
	341	/* CPU is master */
	342	break;
	343	case SND_SOC_DAIFMT_CBM_CFS:
	344	/*
	345	* CODEC is bit clock master
	346	* CPU is frame master
347	*/
348	mode \|= BCM2835_I2S_CLKM;
349	break;
350	case SND_SOC_DAIFMT_CBS_CFM:
351	/*
352	* CODEC is frame master
353	* CPU is bit clock master
354	*/
355	mode \|= BCM2835_I2S_FSM;
356	break;
357	case SND_SOC_DAIFMT_CBM_CFM:
358	/* CODEC is master */
359	mode \|= BCM2835_I2S_CLKM;
360	mode \|= BCM2835_I2S_FSM;
361	break;
362	default:
363	dev_err(dev->dev, "%s:bad master\n", __func__);
364	return -EINVAL;
365	}
366
367	/*
368	* Invert clocks?
369	*
370	* The BCM approach seems to be inverted to the classical I2S approach.
371	*/
372	switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
373	case SND_SOC_DAIFMT_NB_NF:
374	/* None. Therefore, both for BCM */
375	mode \|= BCM2835_I2S_CLKI;
376	mode \|= BCM2835_I2S_FSI;
377	break;
378	case SND_SOC_DAIFMT_IB_IF:
379	/* Both. Therefore, none for BCM */
380	break;
381	case SND_SOC_DAIFMT_NB_IF:
382	/*
383	* Invert only frame sync. Therefore,
384	* invert only bit clock for BCM
385	*/
386	mode \|= BCM2835_I2S_CLKI;
387	break;
388	case SND_SOC_DAIFMT_IB_NF:
389	/*
390	* Invert only bit clock. Therefore,
391	* invert only frame sync for BCM
392	*/
393	mode \|= BCM2835_I2S_FSI;
394	break;
395	default:
396	return -EINVAL;
397	}
398
399	regmap_write(dev->i2s_regmap, BCM2835_I2S_MODE_A_REG, mode);
400
401	/* Setup the DMA parameters */
402	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
0880fc3e MS	403	BCM2835_I2S_RXTHR(1)
	404	\| BCM2835_I2S_TXTHR(1)
	405	\| BCM2835_I2S_DMAEN, 0xffffffff);
c6aeb7de FM	406
c6aeb7de FM	407	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_DREQ_A_REG,
0880fc3e MS	408	BCM2835_I2S_TX_PANIC(0x10)
	409	\| BCM2835_I2S_RX_PANIC(0x30)
	410	\| BCM2835_I2S_TX(0x30)
	411	\| BCM2835_I2S_RX(0x20), 0xffffffff);
c6aeb7de FM	412
	413	/* Clear FIFOs */
	414	bcm2835_i2s_clear_fifos(dev, true, true);
	415
	416	return 0;
	417	}
	418
	419	static int bcm2835_i2s_prepare(struct snd_pcm_substream *substream,
	420	struct snd_soc_dai *dai)
	421	{
	422	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	423	uint32_t cs_reg;
	424
	425	bcm2835_i2s_start_clock(dev);
	426
	427	/*
	428	* Clear both FIFOs if the one that should be started
	429	* is not empty at the moment. This should only happen
	430	* after overrun. Otherwise, hw_params would have cleared
	431	* the FIFO.
	432	*/
	433	regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &cs_reg);
	434
	435	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
	436	&& !(cs_reg & BCM2835_I2S_TXE))
	437	bcm2835_i2s_clear_fifos(dev, true, false);
	438	else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
	439	&& (cs_reg & BCM2835_I2S_RXD))
	440	bcm2835_i2s_clear_fifos(dev, false, true);
	441
	442	return 0;
	443	}
	444
	445	static void bcm2835_i2s_stop(struct bcm2835_i2s_dev *dev,
	446	struct snd_pcm_substream *substream,
	447	struct snd_soc_dai *dai)
	448	{
	449	uint32_t mask;
	450
	451	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
	452	mask = BCM2835_I2S_RXON;
	453	else
	454	mask = BCM2835_I2S_TXON;
	455
	456	regmap_update_bits(dev->i2s_regmap,
	457	BCM2835_I2S_CS_A_REG, mask, 0);
	458
	459	/* Stop also the clock when not SND_SOC_DAIFMT_CONT */
	460	if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT))
	461	bcm2835_i2s_stop_clock(dev);
	462	}
	463
	464	static int bcm2835_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
	465	struct snd_soc_dai *dai)
	466	{
	467	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	468	uint32_t mask;
	469
	470	switch (cmd) {
	471	case SNDRV_PCM_TRIGGER_START:
	472	case SNDRV_PCM_TRIGGER_RESUME:
	473	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	474	bcm2835_i2s_start_clock(dev);
	475
476	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
477	mask = BCM2835_I2S_RXON;
478	else
479	mask = BCM2835_I2S_TXON;
480
481	regmap_update_bits(dev->i2s_regmap,
482	BCM2835_I2S_CS_A_REG, mask, mask);
483	break;
484
485	case SNDRV_PCM_TRIGGER_STOP:
486	case SNDRV_PCM_TRIGGER_SUSPEND:
487	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
488	bcm2835_i2s_stop(dev, substream, dai);
489	break;
490	default:
491	return -EINVAL;
492	}
493
494	return 0;
495	}
496
497	static int bcm2835_i2s_startup(struct snd_pcm_substream *substream,
498	struct snd_soc_dai *dai)
499	{
500	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
501
502	if (dai->active)
503	return 0;
504
505	/* Should this still be running stop it */
506	bcm2835_i2s_stop_clock(dev);
507
508	/* Enable PCM block */
509	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
510	BCM2835_I2S_EN, BCM2835_I2S_EN);
511
512	/*
513	* Disable STBY.
514	* Requires at least 4 PCM clock cycles to take effect.
515	*/
516	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
517	BCM2835_I2S_STBY, BCM2835_I2S_STBY);
518
519	return 0;
520	}
521
522	static void bcm2835_i2s_shutdown(struct snd_pcm_substream *substream,
523	struct snd_soc_dai *dai)
524	{
525	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
526
527	bcm2835_i2s_stop(dev, substream, dai);
528
529	/* If both streams are stopped, disable module and clock */
530	if (dai->active)
531	return;
532
533	/* Disable the module */
534	regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG,
535	BCM2835_I2S_EN, 0);
536
537	/*
538	* Stopping clock is necessary, because stop does
539	* not stop the clock when SND_SOC_DAIFMT_CONT
540	*/
541	bcm2835_i2s_stop_clock(dev);
542	}
543
544	static const struct snd_soc_dai_ops bcm2835_i2s_dai_ops = {
545	.startup = bcm2835_i2s_startup,
546	.shutdown = bcm2835_i2s_shutdown,
547	.prepare = bcm2835_i2s_prepare,
548	.trigger = bcm2835_i2s_trigger,
549	.hw_params = bcm2835_i2s_hw_params,
550	.set_fmt = bcm2835_i2s_set_dai_fmt,
201bd3c6	551	.set_bclk_ratio = bcm2835_i2s_set_dai_bclk_ratio,
c6aeb7de FM	552	};
	553
	554	static int bcm2835_i2s_dai_probe(struct snd_soc_dai *dai)
	555	{
	556	struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
	557
	558	snd_soc_dai_init_dma_data(dai,
	559	&dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
	560	&dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
	561
	562	return 0;
	563	}
	564
	565	static struct snd_soc_dai_driver bcm2835_i2s_dai = {
	566	.name = "bcm2835-i2s",
	567	.probe = bcm2835_i2s_dai_probe,
	568	.playback = {
	569	.channels_min = 2,
	570	.channels_max = 2,
	571	.rates = SNDRV_PCM_RATE_8000_192000,
	572	.formats = SNDRV_PCM_FMTBIT_S16_LE
	573	\| SNDRV_PCM_FMTBIT_S32_LE
	574	},
	575	.capture = {
	576	.channels_min = 2,
	577	.channels_max = 2,
	578	.rates = SNDRV_PCM_RATE_8000_192000,
	579	.formats = SNDRV_PCM_FMTBIT_S16_LE
	580	\| SNDRV_PCM_FMTBIT_S32_LE
	581	},
	582	.ops = &bcm2835_i2s_dai_ops,
	583	.symmetric_rates = 1
	584	};
	585
	586	static bool bcm2835_i2s_volatile_reg(struct device *dev, unsigned int reg)
	587	{
	588	switch (reg) {
	589	case BCM2835_I2S_CS_A_REG:
	590	case BCM2835_I2S_FIFO_A_REG:
	591	case BCM2835_I2S_INTSTC_A_REG:
	592	case BCM2835_I2S_GRAY_REG:
	593	return true;
	594	default:
	595	return false;
	596	};
	597	}
	598
	599	static bool bcm2835_i2s_precious_reg(struct device *dev, unsigned int reg)
	600	{
	601	switch (reg) {
	602	case BCM2835_I2S_FIFO_A_REG:
	603	return true;
	604	default:
	605	return false;
	606	};
	607	}
	608
201bd3c6 MS	609	static const struct regmap_config bcm2835_regmap_config = {
	610	.reg_bits = 32,
	611	.reg_stride = 4,
	612	.val_bits = 32,
	613	.max_register = BCM2835_I2S_GRAY_REG,
	614	.precious_reg = bcm2835_i2s_precious_reg,
	615	.volatile_reg = bcm2835_i2s_volatile_reg,
	616	.cache_type = REGCACHE_RBTREE,
c6aeb7de FM	617	};
	618
	619	static const struct snd_soc_component_driver bcm2835_i2s_component = {
	620	.name = "bcm2835-i2s-comp",
	621	};
	622
	623	static int bcm2835_i2s_probe(struct platform_device *pdev)
	624	{
	625	struct bcm2835_i2s_dev *dev;
c6aeb7de	626	int ret;
201bd3c6 MS	627	struct resource *mem;
	628	void __iomem *base;
	629	const __be32 *addr;
	630	dma_addr_t dma_base;
c6aeb7de FM	631
	632	dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
	633	GFP_KERNEL);
	634	if (!dev)
	635	return -ENOMEM;
	636
201bd3c6 MS	637	/* get the clock */
	638	dev->clk_prepared = false;
	639	dev->clk = devm_clk_get(&pdev->dev, NULL);
	640	if (IS_ERR(dev->clk)) {
	641	dev_err(&pdev->dev, "could not get clk: %ld\n",
	642	PTR_ERR(dev->clk));
	643	return PTR_ERR(dev->clk);
	644	}
	645
	646	/* Request ioarea */
	647	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	648	base = devm_ioremap_resource(&pdev->dev, mem);
	649	if (IS_ERR(base))
	650	return PTR_ERR(base);
	651
	652	dev->i2s_regmap = devm_regmap_init_mmio(&pdev->dev, base,
	653	&bcm2835_regmap_config);
	654	if (IS_ERR(dev->i2s_regmap))
	655	return PTR_ERR(dev->i2s_regmap);
	656
	657	/* Set the DMA address - we have to parse DT ourselves */
	658	addr = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
	659	if (!addr) {
	660	dev_err(&pdev->dev, "could not get DMA-register address\n");
	661	return -EINVAL;
	662	}
	663	dma_base = be32_to_cpup(addr);
c6aeb7de	664
c6aeb7de	665	dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
201bd3c6	666	dma_base + BCM2835_I2S_FIFO_A_REG;
c6aeb7de FM	667
c6aeb7de FM	668	dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
201bd3c6	669	dma_base + BCM2835_I2S_FIFO_A_REG;
c6aeb7de FM	670
	671	/* Set the bus width */
	672	dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
	673	DMA_SLAVE_BUSWIDTH_4_BYTES;
	674	dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
	675	DMA_SLAVE_BUSWIDTH_4_BYTES;
	676
	677	/* Set burst */
	678	dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
	679	dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;
	680
	681	/* BCLK ratio - use default */
	682	dev->bclk_ratio = 0;
	683
	684	/* Store the pdev */
	685	dev->dev = &pdev->dev;
	686	dev_set_drvdata(&pdev->dev, dev);
	687
	688	ret = devm_snd_soc_register_component(&pdev->dev,
	689	&bcm2835_i2s_component, &bcm2835_i2s_dai, 1);
	690	if (ret) {
	691	dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
	692	return ret;
	693	}
	694
c3b19131	695	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
c6aeb7de FM	696	if (ret) {
	697	dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
	698	return ret;
	699	}
	700
	701	return 0;
	702	}
	703
	704	static const struct of_device_id bcm2835_i2s_of_match[] = {
	705	{ .compatible = "brcm,bcm2835-i2s", },
	706	{},
	707	};
	708
054bc835 LB	709	MODULE_DEVICE_TABLE(of, bcm2835_i2s_of_match);
054bc835 LB	710
c6aeb7de FM	711	static struct platform_driver bcm2835_i2s_driver = {
c6aeb7de FM	712	.probe = bcm2835_i2s_probe,
c6aeb7de FM	713	.driver = {
c6aeb7de FM	714	.name = "bcm2835-i2s",
c6aeb7de FM	715	.of_match_table = bcm2835_i2s_of_match,
	716	},
	717	};
	718
	719	module_platform_driver(bcm2835_i2s_driver);
	720
	721	MODULE_ALIAS("platform:bcm2835-i2s");
	722	MODULE_DESCRIPTION("BCM2835 I2S interface");
	723	MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
	724	MODULE_LICENSE("GPL v2");