[mirror_ubuntu-artful-kernel.git] / sound / soc / codecs / ab8500-codec.h

/*
 * Copyright (C) ST-Ericsson SA 2012
 *
 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
 *         Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>,
 *         Roger Nilsson <roger.xr.nilsson@stericsson.com>,
 *         for ST-Ericsson.
 *
 *         Based on the early work done by:
 *         Mikko J. Lehto <mikko.lehto@symbio.com>,
 *         Mikko Sarmanne <mikko.sarmanne@symbio.com>,
 *         for ST-Ericsson.
 *
 * License terms:
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#ifndef AB8500_CODEC_REGISTERS_H
#define AB8500_CODEC_REGISTERS_H

#define AB8500_SUPPORTED_RATE			(SNDRV_PCM_RATE_48000)
#define AB8500_SUPPORTED_FMT			(SNDRV_PCM_FMTBIT_S16_LE)

/* AB8500 interface slot offset definitions */

#define AB8500_AD_DATA0_OFFSET	0
#define AB8500_DA_DATA0_OFFSET	8
#define AB8500_AD_DATA1_OFFSET	16
#define AB8500_DA_DATA1_OFFSET	24

/* AB8500 audio bank (0x0d) register definitions */

#define AB8500_POWERUP				0x00
#define AB8500_AUDSWRESET			0x01
#define AB8500_ADPATHENA			0x02
#define AB8500_DAPATHENA			0x03
#define AB8500_ANACONF1				0x04
#define AB8500_ANACONF2				0x05
#define AB8500_DIGMICCONF			0x06
#define AB8500_ANACONF3				0x07
#define AB8500_ANACONF4				0x08
#define AB8500_DAPATHCONF			0x09
#define AB8500_MUTECONF				0x0A
#define AB8500_SHORTCIRCONF			0x0B
#define AB8500_ANACONF5				0x0C
#define AB8500_ENVCPCONF			0x0D
#define AB8500_SIGENVCONF			0x0E
#define AB8500_PWMGENCONF1			0x0F
#define AB8500_PWMGENCONF2			0x10
#define AB8500_PWMGENCONF3			0x11
#define AB8500_PWMGENCONF4			0x12
#define AB8500_PWMGENCONF5			0x13
#define AB8500_ANAGAIN1				0x14
#define AB8500_ANAGAIN2				0x15
#define AB8500_ANAGAIN3				0x16
#define AB8500_ANAGAIN4				0x17
#define AB8500_DIGLINHSLGAIN			0x18
#define AB8500_DIGLINHSRGAIN			0x19
#define AB8500_ADFILTCONF			0x1A
#define AB8500_DIGIFCONF1			0x1B
#define AB8500_DIGIFCONF2			0x1C
#define AB8500_DIGIFCONF3			0x1D
#define AB8500_DIGIFCONF4			0x1E
#define AB8500_ADSLOTSEL1			0x1F
#define AB8500_ADSLOTSEL2			0x20
#define AB8500_ADSLOTSEL3			0x21
#define AB8500_ADSLOTSEL4			0x22
#define AB8500_ADSLOTSEL5			0x23
#define AB8500_ADSLOTSEL6			0x24
#define AB8500_ADSLOTSEL7			0x25
#define AB8500_ADSLOTSEL8			0x26
#define AB8500_ADSLOTSEL9			0x27
#define AB8500_ADSLOTSEL10			0x28
#define AB8500_ADSLOTSEL11			0x29
#define AB8500_ADSLOTSEL12			0x2A
#define AB8500_ADSLOTSEL13			0x2B
#define AB8500_ADSLOTSEL14			0x2C
#define AB8500_ADSLOTSEL15			0x2D
#define AB8500_ADSLOTSEL16			0x2E
#define AB8500_ADSLOTSEL(slot)			(AB8500_ADSLOTSEL1 + (slot >> 1))
#define AB8500_ADSLOTHIZCTRL1			0x2F
#define AB8500_ADSLOTHIZCTRL2			0x30
#define AB8500_ADSLOTHIZCTRL3			0x31
#define AB8500_ADSLOTHIZCTRL4			0x32
#define AB8500_DASLOTCONF1			0x33
#define AB8500_DASLOTCONF2			0x34
#define AB8500_DASLOTCONF3			0x35
#define AB8500_DASLOTCONF4			0x36
#define AB8500_DASLOTCONF5			0x37
#define AB8500_DASLOTCONF6			0x38
#define AB8500_DASLOTCONF7			0x39
#define AB8500_DASLOTCONF8			0x3A
#define AB8500_CLASSDCONF1			0x3B
#define AB8500_CLASSDCONF2			0x3C
#define AB8500_CLASSDCONF3			0x3D
#define AB8500_DMICFILTCONF			0x3E
#define AB8500_DIGMULTCONF1			0x3F
#define AB8500_DIGMULTCONF2			0x40
#define AB8500_ADDIGGAIN1			0x41
#define AB8500_ADDIGGAIN2			0x42
#define AB8500_ADDIGGAIN3			0x43
#define AB8500_ADDIGGAIN4			0x44
#define AB8500_ADDIGGAIN5			0x45
#define AB8500_ADDIGGAIN6			0x46
#define AB8500_DADIGGAIN1			0x47
#define AB8500_DADIGGAIN2			0x48
#define AB8500_DADIGGAIN3			0x49
#define AB8500_DADIGGAIN4			0x4A
#define AB8500_DADIGGAIN5			0x4B
#define AB8500_DADIGGAIN6			0x4C
#define AB8500_ADDIGLOOPGAIN1			0x4D
#define AB8500_ADDIGLOOPGAIN2			0x4E
#define AB8500_HSLEARDIGGAIN			0x4F
#define AB8500_HSRDIGGAIN			0x50
#define AB8500_SIDFIRGAIN1			0x51
#define AB8500_SIDFIRGAIN2			0x52
#define AB8500_ANCCONF1				0x53
#define AB8500_ANCCONF2				0x54
#define AB8500_ANCCONF3				0x55
#define AB8500_ANCCONF4				0x56
#define AB8500_ANCCONF5				0x57
#define AB8500_ANCCONF6				0x58
#define AB8500_ANCCONF7				0x59
#define AB8500_ANCCONF8				0x5A
#define AB8500_ANCCONF9				0x5B
#define AB8500_ANCCONF10			0x5C
#define AB8500_ANCCONF11			0x5D
#define AB8500_ANCCONF12			0x5E
#define AB8500_ANCCONF13			0x5F
#define AB8500_ANCCONF14			0x60
#define AB8500_SIDFIRADR			0x61
#define AB8500_SIDFIRCOEF1			0x62
#define AB8500_SIDFIRCOEF2			0x63
#define AB8500_SIDFIRCONF			0x64
#define AB8500_AUDINTMASK1			0x65
#define AB8500_AUDINTSOURCE1			0x66
#define AB8500_AUDINTMASK2			0x67
#define AB8500_AUDINTSOURCE2			0x68
#define AB8500_FIFOCONF1			0x69
#define AB8500_FIFOCONF2			0x6A
#define AB8500_FIFOCONF3			0x6B
#define AB8500_FIFOCONF4			0x6C
#define AB8500_FIFOCONF5			0x6D
#define AB8500_FIFOCONF6			0x6E
#define AB8500_AUDREV				0x6F

#define AB8500_FIRST_REG			AB8500_POWERUP
#define AB8500_LAST_REG				AB8500_AUDREV
#define AB8500_CACHEREGNUM			(AB8500_LAST_REG + 1)

#define AB8500_MASK_ALL				0xFF
#define AB8500_MASK_SLOT(slot)			((slot & 1) ? 0xF0 : 0x0F)
#define AB8500_MASK_NONE			0x00

/* AB8500_POWERUP */
#define AB8500_POWERUP_POWERUP			7
#define AB8500_POWERUP_ENANA			3

/* AB8500_AUDSWRESET */
#define AB8500_AUDSWRESET_SWRESET		7

/* AB8500_ADPATHENA */
#define AB8500_ADPATHENA_ENAD12			7
#define AB8500_ADPATHENA_ENAD34			5
#define AB8500_ADPATHENA_ENAD5768		3

/* AB8500_DAPATHENA */
#define AB8500_DAPATHENA_ENDA1			7
#define AB8500_DAPATHENA_ENDA2			6
#define AB8500_DAPATHENA_ENDA3			5
#define AB8500_DAPATHENA_ENDA4			4
#define AB8500_DAPATHENA_ENDA5			3
#define AB8500_DAPATHENA_ENDA6			2

/* AB8500_ANACONF1 */
#define AB8500_ANACONF1_HSLOWPOW		7
#define AB8500_ANACONF1_DACLOWPOW1		6
#define AB8500_ANACONF1_DACLOWPOW0		5
#define AB8500_ANACONF1_EARDACLOWPOW		4
#define AB8500_ANACONF1_EARSELCM		2
#define AB8500_ANACONF1_HSHPEN			1
#define AB8500_ANACONF1_EARDRVLOWPOW		0

/* AB8500_ANACONF2 */
#define AB8500_ANACONF2_ENMIC1			7
#define AB8500_ANACONF2_ENMIC2			6
#define AB8500_ANACONF2_ENLINL			5
#define AB8500_ANACONF2_ENLINR			4
#define AB8500_ANACONF2_MUTMIC1			3
#define AB8500_ANACONF2_MUTMIC2			2
#define AB8500_ANACONF2_MUTLINL			1
#define AB8500_ANACONF2_MUTLINR			0

/* AB8500_DIGMICCONF */
#define AB8500_DIGMICCONF_ENDMIC1		7
#define AB8500_DIGMICCONF_ENDMIC2		6
#define AB8500_DIGMICCONF_ENDMIC3		5
#define AB8500_DIGMICCONF_ENDMIC4		4
#define AB8500_DIGMICCONF_ENDMIC5		3
#define AB8500_DIGMICCONF_ENDMIC6		2
#define AB8500_DIGMICCONF_HSFADSPEED		0

/* AB8500_ANACONF3 */
#define AB8500_ANACONF3_MIC1SEL			7
#define AB8500_ANACONF3_LINRSEL			6
#define AB8500_ANACONF3_ENDRVHSL		5
#define AB8500_ANACONF3_ENDRVHSR		4
#define AB8500_ANACONF3_ENADCMIC		2
#define AB8500_ANACONF3_ENADCLINL		1
#define AB8500_ANACONF3_ENADCLINR		0

/* AB8500_ANACONF4 */
#define AB8500_ANACONF4_DISPDVSS		7
#define AB8500_ANACONF4_ENEAR			6
#define AB8500_ANACONF4_ENHSL			5
#define AB8500_ANACONF4_ENHSR			4
#define AB8500_ANACONF4_ENHFL			3
#define AB8500_ANACONF4_ENHFR			2
#define AB8500_ANACONF4_ENVIB1			1
#define AB8500_ANACONF4_ENVIB2			0

/* AB8500_DAPATHCONF */
#define AB8500_DAPATHCONF_ENDACEAR		6
#define AB8500_DAPATHCONF_ENDACHSL		5
#define AB8500_DAPATHCONF_ENDACHSR		4
#define AB8500_DAPATHCONF_ENDACHFL		3
#define AB8500_DAPATHCONF_ENDACHFR		2
#define AB8500_DAPATHCONF_ENDACVIB1		1
#define AB8500_DAPATHCONF_ENDACVIB2		0

/* AB8500_MUTECONF */
#define AB8500_MUTECONF_MUTEAR			6
#define AB8500_MUTECONF_MUTHSL			5
#define AB8500_MUTECONF_MUTHSR			4
#define AB8500_MUTECONF_MUTDACEAR		2
#define AB8500_MUTECONF_MUTDACHSL		1
#define AB8500_MUTECONF_MUTDACHSR		0

/* AB8500_SHORTCIRCONF */
#define AB8500_SHORTCIRCONF_ENSHORTPWD		7
#define AB8500_SHORTCIRCONF_EARSHORTDIS		6
#define AB8500_SHORTCIRCONF_HSSHORTDIS		5
#define AB8500_SHORTCIRCONF_HSPULLDEN		4
#define AB8500_SHORTCIRCONF_HSOSCEN		2
#define AB8500_SHORTCIRCONF_HSFADDIS		1
#define AB8500_SHORTCIRCONF_HSZCDDIS		0
/* Zero cross should be disabled */

/* AB8500_ANACONF5 */
#define AB8500_ANACONF5_ENCPHS			7
#define AB8500_ANACONF5_HSLDACTOLOL		5
#define AB8500_ANACONF5_HSRDACTOLOR		4
#define AB8500_ANACONF5_ENLOL			3
#define AB8500_ANACONF5_ENLOR			2
#define AB8500_ANACONF5_HSAUTOEN		0

/* AB8500_ENVCPCONF */
#define AB8500_ENVCPCONF_ENVDETHTHRE		4
#define AB8500_ENVCPCONF_ENVDETLTHRE		0
#define AB8500_ENVCPCONF_ENVDETHTHRE_MAX	0x0F
#define AB8500_ENVCPCONF_ENVDETLTHRE_MAX	0x0F

/* AB8500_SIGENVCONF */
#define AB8500_SIGENVCONF_CPLVEN		5
#define AB8500_SIGENVCONF_ENVDETCPEN		4
#define AB8500_SIGENVCONF_ENVDETTIME		0
#define AB8500_SIGENVCONF_ENVDETTIME_MAX	0x0F

/* AB8500_PWMGENCONF1 */
#define AB8500_PWMGENCONF1_PWMTOVIB1		7
#define AB8500_PWMGENCONF1_PWMTOVIB2		6
#define AB8500_PWMGENCONF1_PWM1CTRL		5
#define AB8500_PWMGENCONF1_PWM2CTRL		4
#define AB8500_PWMGENCONF1_PWM1NCTRL		3
#define AB8500_PWMGENCONF1_PWM1PCTRL		2
#define AB8500_PWMGENCONF1_PWM2NCTRL		1
#define AB8500_PWMGENCONF1_PWM2PCTRL		0

/* AB8500_PWMGENCONF2 */
/* AB8500_PWMGENCONF3 */
/* AB8500_PWMGENCONF4 */
/* AB8500_PWMGENCONF5 */
#define AB8500_PWMGENCONFX_PWMVIBXPOL		7
#define AB8500_PWMGENCONFX_PWMVIBXDUTCYC	0
#define AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX	0x64

/* AB8500_ANAGAIN1 */
/* AB8500_ANAGAIN2 */
#define AB8500_ANAGAINX_ENSEMICX		7
#define AB8500_ANAGAINX_LOWPOWMICX		6
#define AB8500_ANAGAINX_MICXGAIN		0
#define AB8500_ANAGAINX_MICXGAIN_MAX		0x1F

/* AB8500_ANAGAIN3 */
#define AB8500_ANAGAIN3_HSLGAIN			4
#define AB8500_ANAGAIN3_HSRGAIN			0
#define AB8500_ANAGAIN3_HSXGAIN_MAX		0x0F

/* AB8500_ANAGAIN4 */
#define AB8500_ANAGAIN4_LINLGAIN		4
#define AB8500_ANAGAIN4_LINRGAIN		0
#define AB8500_ANAGAIN4_LINXGAIN_MAX		0x0F

/* AB8500_DIGLINHSLGAIN */
/* AB8500_DIGLINHSRGAIN */
#define AB8500_DIGLINHSXGAIN_LINTOHSXGAIN	0
#define AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX	0x13

/* AB8500_ADFILTCONF */
#define AB8500_ADFILTCONF_AD1NH			7
#define AB8500_ADFILTCONF_AD2NH			6
#define AB8500_ADFILTCONF_AD3NH			5
#define AB8500_ADFILTCONF_AD4NH			4
#define AB8500_ADFILTCONF_AD1VOICE		3
#define AB8500_ADFILTCONF_AD2VOICE		2
#define AB8500_ADFILTCONF_AD3VOICE		1
#define AB8500_ADFILTCONF_AD4VOICE		0

/* AB8500_DIGIFCONF1 */
#define AB8500_DIGIFCONF1_ENMASTGEN		7
#define AB8500_DIGIFCONF1_IF1BITCLKOS1		6
#define AB8500_DIGIFCONF1_IF1BITCLKOS0		5
#define AB8500_DIGIFCONF1_ENFSBITCLK1		4
#define AB8500_DIGIFCONF1_IF0BITCLKOS1		2
#define AB8500_DIGIFCONF1_IF0BITCLKOS0		1
#define AB8500_DIGIFCONF1_ENFSBITCLK0		0

/* AB8500_DIGIFCONF2 */
#define AB8500_DIGIFCONF2_FSYNC0P		6
#define AB8500_DIGIFCONF2_BITCLK0P		5
#define AB8500_DIGIFCONF2_IF0DEL		4
#define AB8500_DIGIFCONF2_IF0FORMAT1		3
#define AB8500_DIGIFCONF2_IF0FORMAT0		2
#define AB8500_DIGIFCONF2_IF0WL1		1
#define AB8500_DIGIFCONF2_IF0WL0		0

/* AB8500_DIGIFCONF3 */
#define AB8500_DIGIFCONF3_IF0DATOIF1AD		7
#define AB8500_DIGIFCONF3_IF0CLKTOIF1CLK	6
#define AB8500_DIGIFCONF3_IF1MASTER		5
#define AB8500_DIGIFCONF3_IF1DATOIF0AD		3
#define AB8500_DIGIFCONF3_IF1CLKTOIF0CLK	2
#define AB8500_DIGIFCONF3_IF0MASTER		1
#define AB8500_DIGIFCONF3_IF0BFIFOEN		0

/* AB8500_DIGIFCONF4 */
#define AB8500_DIGIFCONF4_FSYNC1P		6
#define AB8500_DIGIFCONF4_BITCLK1P		5
#define AB8500_DIGIFCONF4_IF1DEL		4
#define AB8500_DIGIFCONF4_IF1FORMAT1		3
#define AB8500_DIGIFCONF4_IF1FORMAT0		2
#define AB8500_DIGIFCONF4_IF1WL1		1
#define AB8500_DIGIFCONF4_IF1WL0		0

/* AB8500_ADSLOTSELX */
#define AB8500_AD_OUT1	0x0
#define AB8500_AD_OUT2	0x1
#define AB8500_AD_OUT3	0x2
#define AB8500_AD_OUT4	0x3
#define AB8500_AD_OUT5	0x4
#define AB8500_AD_OUT6	0x5
#define AB8500_AD_OUT7	0x6
#define AB8500_AD_OUT8	0x7
#define AB8500_ZEROES	0x8
#define AB8500_TRISTATE	0xF
#define AB8500_ADSLOTSELX_EVEN_SHIFT		0
#define AB8500_ADSLOTSELX_ODD_SHIFT		4
#define AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(out, slot)	\
	((out) << (((slot) & 1) ? \
	 AB8500_ADSLOTSELX_ODD_SHIFT : AB8500_ADSLOTSELX_EVEN_SHIFT))

/* AB8500_ADSLOTHIZCTRL1 */
/* AB8500_ADSLOTHIZCTRL2 */
/* AB8500_ADSLOTHIZCTRL3 */
/* AB8500_ADSLOTHIZCTRL4 */
/* AB8500_DASLOTCONF1 */
#define AB8500_DASLOTCONF1_DA12VOICE		7
#define AB8500_DASLOTCONF1_SWAPDA12_34		6
#define AB8500_DASLOTCONF1_DAI7TOADO1		5

/* AB8500_DASLOTCONF2 */
#define AB8500_DASLOTCONF2_DAI8TOADO2		5

/* AB8500_DASLOTCONF3 */
#define AB8500_DASLOTCONF3_DA34VOICE		7
#define AB8500_DASLOTCONF3_DAI7TOADO3		5

/* AB8500_DASLOTCONF4 */
#define AB8500_DASLOTCONF4_DAI8TOADO4		5

/* AB8500_DASLOTCONF5 */
#define AB8500_DASLOTCONF5_DA56VOICE		7
#define AB8500_DASLOTCONF5_DAI7TOADO5		5

/* AB8500_DASLOTCONF6 */
#define AB8500_DASLOTCONF6_DAI8TOADO6		5

/* AB8500_DASLOTCONF7 */
#define AB8500_DASLOTCONF7_DAI8TOADO7		5

/* AB8500_DASLOTCONF8 */
#define AB8500_DASLOTCONF8_DAI7TOADO8		5

#define AB8500_DASLOTCONFX_SLTODAX_SHIFT	0
#define AB8500_DASLOTCONFX_SLTODAX_MASK		0x1F

/* AB8500_CLASSDCONF1 */
#define AB8500_CLASSDCONF1_PARLHF		7
#define AB8500_CLASSDCONF1_PARLVIB		6
#define AB8500_CLASSDCONF1_VIB1SWAPEN		3
#define AB8500_CLASSDCONF1_VIB2SWAPEN		2
#define AB8500_CLASSDCONF1_HFLSWAPEN		1
#define AB8500_CLASSDCONF1_HFRSWAPEN		0

/* AB8500_CLASSDCONF2 */
#define AB8500_CLASSDCONF2_FIRBYP3		7
#define AB8500_CLASSDCONF2_FIRBYP2		6
#define AB8500_CLASSDCONF2_FIRBYP1		5
#define AB8500_CLASSDCONF2_FIRBYP0		4
#define AB8500_CLASSDCONF2_HIGHVOLEN3		3
#define AB8500_CLASSDCONF2_HIGHVOLEN2		2
#define AB8500_CLASSDCONF2_HIGHVOLEN1		1
#define AB8500_CLASSDCONF2_HIGHVOLEN0		0

/* AB8500_CLASSDCONF3 */
#define AB8500_CLASSDCONF3_DITHHPGAIN		4
#define AB8500_CLASSDCONF3_DITHHPGAIN_MAX	0x0A
#define AB8500_CLASSDCONF3_DITHWGAIN		0
#define AB8500_CLASSDCONF3_DITHWGAIN_MAX	0x0A

/* AB8500_DMICFILTCONF */
#define AB8500_DMICFILTCONF_ANCINSEL		7
#define AB8500_DMICFILTCONF_DA3TOEAR		6
#define AB8500_DMICFILTCONF_DMIC1SINC3		5
#define AB8500_DMICFILTCONF_DMIC2SINC3		4
#define AB8500_DMICFILTCONF_DMIC3SINC3		3
#define AB8500_DMICFILTCONF_DMIC4SINC3		2
#define AB8500_DMICFILTCONF_DMIC5SINC3		1
#define AB8500_DMICFILTCONF_DMIC6SINC3		0

/* AB8500_DIGMULTCONF1 */
#define AB8500_DIGMULTCONF1_DATOHSLEN		7
#define AB8500_DIGMULTCONF1_DATOHSREN		6
#define AB8500_DIGMULTCONF1_AD1SEL		5
#define AB8500_DIGMULTCONF1_AD2SEL		4
#define AB8500_DIGMULTCONF1_AD3SEL		3
#define AB8500_DIGMULTCONF1_AD5SEL		2
#define AB8500_DIGMULTCONF1_AD6SEL		1
#define AB8500_DIGMULTCONF1_ANCSEL		0

/* AB8500_DIGMULTCONF2 */
#define AB8500_DIGMULTCONF2_DATOHFREN		7
#define AB8500_DIGMULTCONF2_DATOHFLEN		6
#define AB8500_DIGMULTCONF2_HFRSEL		5
#define AB8500_DIGMULTCONF2_HFLSEL		4
#define AB8500_DIGMULTCONF2_FIRSID1SEL		2
#define AB8500_DIGMULTCONF2_FIRSID2SEL		0

/* AB8500_ADDIGGAIN1 */
/* AB8500_ADDIGGAIN2 */
/* AB8500_ADDIGGAIN3 */
/* AB8500_ADDIGGAIN4 */
/* AB8500_ADDIGGAIN5 */
/* AB8500_ADDIGGAIN6 */
#define AB8500_ADDIGGAINX_FADEDISADX		6
#define AB8500_ADDIGGAINX_ADXGAIN_MAX		0x3F

/* AB8500_DADIGGAIN1 */
/* AB8500_DADIGGAIN2 */
/* AB8500_DADIGGAIN3 */
/* AB8500_DADIGGAIN4 */
/* AB8500_DADIGGAIN5 */
/* AB8500_DADIGGAIN6 */
#define AB8500_DADIGGAINX_FADEDISDAX		6
#define AB8500_DADIGGAINX_DAXGAIN_MAX		0x3F

/* AB8500_ADDIGLOOPGAIN1 */
/* AB8500_ADDIGLOOPGAIN2 */
#define AB8500_ADDIGLOOPGAINX_FADEDISADXL	6
#define AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX	0x3F

/* AB8500_HSLEARDIGGAIN */
#define AB8500_HSLEARDIGGAIN_HSSINC1		7
#define AB8500_HSLEARDIGGAIN_FADEDISHSL		4
#define AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX	0x09

/* AB8500_HSRDIGGAIN */
#define AB8500_HSRDIGGAIN_FADESPEED		6
#define AB8500_HSRDIGGAIN_FADEDISHSR		4
#define AB8500_HSRDIGGAIN_HSRDGAIN_MAX		0x09

/* AB8500_SIDFIRGAIN1 */
/* AB8500_SIDFIRGAIN2 */
#define AB8500_SIDFIRGAINX_FIRSIDXGAIN_MAX	0x1F

/* AB8500_ANCCONF1 */
#define AB8500_ANCCONF1_ANCIIRUPDATE		3
#define AB8500_ANCCONF1_ENANC			2
#define AB8500_ANCCONF1_ANCIIRINIT		1
#define AB8500_ANCCONF1_ANCFIRUPDATE		0

/* AB8500_ANCCONF2 */
#define AB8500_ANCCONF2_SHIFT			5
#define AB8500_ANCCONF2_MIN			-0x10
#define AB8500_ANCCONF2_MAX			0xF

/* AB8500_ANCCONF3 */
#define AB8500_ANCCONF3_SHIFT			5
#define AB8500_ANCCONF3_MIN			-0x10
#define AB8500_ANCCONF3_MAX			0xF

/* AB8500_ANCCONF4 */
#define AB8500_ANCCONF4_SHIFT			5
#define AB8500_ANCCONF4_MIN			-0x10
#define AB8500_ANCCONF4_MAX			0xF

/* AB8500_ANC_FIR_COEFFS */
#define AB8500_ANC_FIR_COEFF_MIN		-0x8000
#define AB8500_ANC_FIR_COEFF_MAX		0x7FFF
#define AB8500_ANC_FIR_COEFFS			15

/* AB8500_ANC_IIR_COEFFS */
#define AB8500_ANC_IIR_COEFF_MIN		-0x800000
#define AB8500_ANC_IIR_COEFF_MAX		0x7FFFFF
#define AB8500_ANC_IIR_COEFFS			24
/* AB8500_ANC_WARP_DELAY */
#define AB8500_ANC_WARP_DELAY_SHIFT		16
#define AB8500_ANC_WARP_DELAY_MIN		0x0000
#define AB8500_ANC_WARP_DELAY_MAX		0xFFFF

/* AB8500_ANCCONF11 */
/* AB8500_ANCCONF12 */
/* AB8500_ANCCONF13 */
/* AB8500_ANCCONF14 */

/* AB8500_SIDFIRADR */
#define AB8500_SIDFIRADR_FIRSIDSET		7
#define AB8500_SIDFIRADR_ADDRESS_SHIFT		0
#define AB8500_SIDFIRADR_ADDRESS_MAX		0x7F

/* AB8500_SIDFIRCOEF1 */
/* AB8500_SIDFIRCOEF2 */
#define AB8500_SID_FIR_COEFF_MIN		0
#define AB8500_SID_FIR_COEFF_MAX		0xFFFF
#define AB8500_SID_FIR_COEFFS			128

/* AB8500_SIDFIRCONF */
#define AB8500_SIDFIRCONF_ENFIRSIDS		2
#define AB8500_SIDFIRCONF_FIRSIDSTOIF1		1
#define AB8500_SIDFIRCONF_FIRSIDBUSY		0

/* AB8500_AUDINTMASK1 */
/* AB8500_AUDINTSOURCE1 */
/* AB8500_AUDINTMASK2 */
/* AB8500_AUDINTSOURCE2 */

/* AB8500_FIFOCONF1 */
#define AB8500_FIFOCONF1_BFIFOMASK		0x80
#define AB8500_FIFOCONF1_BFIFO19M2		0x40
#define AB8500_FIFOCONF1_BFIFOINT_SHIFT		0
#define AB8500_FIFOCONF1_BFIFOINT_MAX		0x3F

/* AB8500_FIFOCONF2 */
#define AB8500_FIFOCONF2_BFIFOTX_SHIFT		0
#define AB8500_FIFOCONF2_BFIFOTX_MAX		0xFF

/* AB8500_FIFOCONF3 */
#define AB8500_FIFOCONF3_BFIFOEXSL_SHIFT	5
#define AB8500_FIFOCONF3_BFIFOEXSL_MAX		0x5
#define AB8500_FIFOCONF3_PREBITCLK0_SHIFT	2
#define AB8500_FIFOCONF3_PREBITCLK0_MAX		0x7
#define AB8500_FIFOCONF3_BFIFOMAST_SHIFT	1
#define AB8500_FIFOCONF3_BFIFORUN_SHIFT		0

/* AB8500_FIFOCONF4 */
#define AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT	0
#define AB8500_FIFOCONF4_BFIFOFRAMSW_MAX	0xFF

/* AB8500_FIFOCONF5 */
#define AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT	0
#define AB8500_FIFOCONF5_BFIFOWAKEUP_MAX	0xFF

/* AB8500_FIFOCONF6 */
#define AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT	0
#define AB8500_FIFOCONF6_BFIFOSAMPLE_MAX	0xFF

/* AB8500_AUDREV */

#endif
Commit	Line	Data
679d7abd OL	1	/*
	2	* Copyright (C) ST-Ericsson SA 2012
	3	*
	4	* Author: Ola Lilja <ola.o.lilja@stericsson.com>,
	5	* Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>,
	6	* Roger Nilsson <roger.xr.nilsson@stericsson.com>,
	7	* for ST-Ericsson.
	8	*
	9	* Based on the early work done by:
	10	* Mikko J. Lehto <mikko.lehto@symbio.com>,
	11	* Mikko Sarmanne <mikko.sarmanne@symbio.com>,
	12	* for ST-Ericsson.
	13	*
	14	* License terms:
	15	*
	16	* This program is free software; you can redistribute it and/or modify it
	17	* under the terms of the GNU General Public License version 2 as published
	18	* by the Free Software Foundation.
	19	*/
	20
	21	#ifndef AB8500_CODEC_REGISTERS_H
	22	#define AB8500_CODEC_REGISTERS_H
	23
	24	#define AB8500_SUPPORTED_RATE (SNDRV_PCM_RATE_48000)
	25	#define AB8500_SUPPORTED_FMT (SNDRV_PCM_FMTBIT_S16_LE)
	26
b2962633 FB	27	/* AB8500 interface slot offset definitions */
	28
	29	#define AB8500_AD_DATA0_OFFSET 0
	30	#define AB8500_DA_DATA0_OFFSET 8
	31	#define AB8500_AD_DATA1_OFFSET 16
	32	#define AB8500_DA_DATA1_OFFSET 24
	33
679d7abd OL	34	/* AB8500 audio bank (0x0d) register definitions */
	35
	36	#define AB8500_POWERUP 0x00
	37	#define AB8500_AUDSWRESET 0x01
	38	#define AB8500_ADPATHENA 0x02
	39	#define AB8500_DAPATHENA 0x03
	40	#define AB8500_ANACONF1 0x04
	41	#define AB8500_ANACONF2 0x05
	42	#define AB8500_DIGMICCONF 0x06
	43	#define AB8500_ANACONF3 0x07
	44	#define AB8500_ANACONF4 0x08
	45	#define AB8500_DAPATHCONF 0x09
	46	#define AB8500_MUTECONF 0x0A
	47	#define AB8500_SHORTCIRCONF 0x0B
	48	#define AB8500_ANACONF5 0x0C
	49	#define AB8500_ENVCPCONF 0x0D
	50	#define AB8500_SIGENVCONF 0x0E
	51	#define AB8500_PWMGENCONF1 0x0F
	52	#define AB8500_PWMGENCONF2 0x10
	53	#define AB8500_PWMGENCONF3 0x11
	54	#define AB8500_PWMGENCONF4 0x12
	55	#define AB8500_PWMGENCONF5 0x13
	56	#define AB8500_ANAGAIN1 0x14
	57	#define AB8500_ANAGAIN2 0x15
	58	#define AB8500_ANAGAIN3 0x16
	59	#define AB8500_ANAGAIN4 0x17
	60	#define AB8500_DIGLINHSLGAIN 0x18
	61	#define AB8500_DIGLINHSRGAIN 0x19
	62	#define AB8500_ADFILTCONF 0x1A
	63	#define AB8500_DIGIFCONF1 0x1B
	64	#define AB8500_DIGIFCONF2 0x1C
	65	#define AB8500_DIGIFCONF3 0x1D
	66	#define AB8500_DIGIFCONF4 0x1E
	67	#define AB8500_ADSLOTSEL1 0x1F
	68	#define AB8500_ADSLOTSEL2 0x20
	69	#define AB8500_ADSLOTSEL3 0x21
	70	#define AB8500_ADSLOTSEL4 0x22
	71	#define AB8500_ADSLOTSEL5 0x23
	72	#define AB8500_ADSLOTSEL6 0x24
	73	#define AB8500_ADSLOTSEL7 0x25
	74	#define AB8500_ADSLOTSEL8 0x26
	75	#define AB8500_ADSLOTSEL9 0x27
	76	#define AB8500_ADSLOTSEL10 0x28
	77	#define AB8500_ADSLOTSEL11 0x29
	78	#define AB8500_ADSLOTSEL12 0x2A
	79	#define AB8500_ADSLOTSEL13 0x2B
	80	#define AB8500_ADSLOTSEL14 0x2C
	81	#define AB8500_ADSLOTSEL15 0x2D
	82	#define AB8500_ADSLOTSEL16 0x2E
da33d723	83	#define AB8500_ADSLOTSEL(slot) (AB8500_ADSLOTSEL1 + (slot >> 1))
679d7abd OL	84	#define AB8500_ADSLOTHIZCTRL1 0x2F
	85	#define AB8500_ADSLOTHIZCTRL2 0x30
	86	#define AB8500_ADSLOTHIZCTRL3 0x31
	87	#define AB8500_ADSLOTHIZCTRL4 0x32
	88	#define AB8500_DASLOTCONF1 0x33
	89	#define AB8500_DASLOTCONF2 0x34
	90	#define AB8500_DASLOTCONF3 0x35
	91	#define AB8500_DASLOTCONF4 0x36
	92	#define AB8500_DASLOTCONF5 0x37
	93	#define AB8500_DASLOTCONF6 0x38
	94	#define AB8500_DASLOTCONF7 0x39
	95	#define AB8500_DASLOTCONF8 0x3A
	96	#define AB8500_CLASSDCONF1 0x3B
	97	#define AB8500_CLASSDCONF2 0x3C
	98	#define AB8500_CLASSDCONF3 0x3D
	99	#define AB8500_DMICFILTCONF 0x3E
	100	#define AB8500_DIGMULTCONF1 0x3F
	101	#define AB8500_DIGMULTCONF2 0x40
	102	#define AB8500_ADDIGGAIN1 0x41
	103	#define AB8500_ADDIGGAIN2 0x42
	104	#define AB8500_ADDIGGAIN3 0x43
	105	#define AB8500_ADDIGGAIN4 0x44
	106	#define AB8500_ADDIGGAIN5 0x45
	107	#define AB8500_ADDIGGAIN6 0x46
	108	#define AB8500_DADIGGAIN1 0x47
	109	#define AB8500_DADIGGAIN2 0x48
	110	#define AB8500_DADIGGAIN3 0x49
	111	#define AB8500_DADIGGAIN4 0x4A
	112	#define AB8500_DADIGGAIN5 0x4B
	113	#define AB8500_DADIGGAIN6 0x4C
	114	#define AB8500_ADDIGLOOPGAIN1 0x4D
	115	#define AB8500_ADDIGLOOPGAIN2 0x4E
	116	#define AB8500_HSLEARDIGGAIN 0x4F
	117	#define AB8500_HSRDIGGAIN 0x50
	118	#define AB8500_SIDFIRGAIN1 0x51
	119	#define AB8500_SIDFIRGAIN2 0x52
	120	#define AB8500_ANCCONF1 0x53
	121	#define AB8500_ANCCONF2 0x54
	122	#define AB8500_ANCCONF3 0x55
	123	#define AB8500_ANCCONF4 0x56
	124	#define AB8500_ANCCONF5 0x57
	125	#define AB8500_ANCCONF6 0x58
	126	#define AB8500_ANCCONF7 0x59
	127	#define AB8500_ANCCONF8 0x5A
	128	#define AB8500_ANCCONF9 0x5B
	129	#define AB8500_ANCCONF10 0x5C
	130	#define AB8500_ANCCONF11 0x5D
	131	#define AB8500_ANCCONF12 0x5E
	132	#define AB8500_ANCCONF13 0x5F
	133	#define AB8500_ANCCONF14 0x60
	134	#define AB8500_SIDFIRADR 0x61
	135	#define AB8500_SIDFIRCOEF1 0x62
	136	#define AB8500_SIDFIRCOEF2 0x63
	137	#define AB8500_SIDFIRCONF 0x64
	138	#define AB8500_AUDINTMASK1 0x65
	139	#define AB8500_AUDINTSOURCE1 0x66
	140	#define AB8500_AUDINTMASK2 0x67
	141	#define AB8500_AUDINTSOURCE2 0x68
	142	#define AB8500_FIFOCONF1 0x69
	143	#define AB8500_FIFOCONF2 0x6A
	144	#define AB8500_FIFOCONF3 0x6B
	145	#define AB8500_FIFOCONF4 0x6C
	146	#define AB8500_FIFOCONF5 0x6D
	147	#define AB8500_FIFOCONF6 0x6E
148	#define AB8500_AUDREV 0x6F
149
150	#define AB8500_FIRST_REG AB8500_POWERUP
151	#define AB8500_LAST_REG AB8500_AUDREV
152	#define AB8500_CACHEREGNUM (AB8500_LAST_REG + 1)
153
154	#define AB8500_MASK_ALL 0xFF
da33d723	155	#define AB8500_MASK_SLOT(slot) ((slot & 1) ? 0xF0 : 0x0F)
679d7abd OL	156	#define AB8500_MASK_NONE 0x00
	157
	158	/* AB8500_POWERUP */
	159	#define AB8500_POWERUP_POWERUP 7
	160	#define AB8500_POWERUP_ENANA 3
	161
	162	/* AB8500_AUDSWRESET */
	163	#define AB8500_AUDSWRESET_SWRESET 7
	164
	165	/* AB8500_ADPATHENA */
	166	#define AB8500_ADPATHENA_ENAD12 7
	167	#define AB8500_ADPATHENA_ENAD34 5
	168	#define AB8500_ADPATHENA_ENAD5768 3
	169
	170	/* AB8500_DAPATHENA */
	171	#define AB8500_DAPATHENA_ENDA1 7
	172	#define AB8500_DAPATHENA_ENDA2 6
	173	#define AB8500_DAPATHENA_ENDA3 5
	174	#define AB8500_DAPATHENA_ENDA4 4
	175	#define AB8500_DAPATHENA_ENDA5 3
	176	#define AB8500_DAPATHENA_ENDA6 2
	177
	178	/* AB8500_ANACONF1 */
	179	#define AB8500_ANACONF1_HSLOWPOW 7
	180	#define AB8500_ANACONF1_DACLOWPOW1 6
	181	#define AB8500_ANACONF1_DACLOWPOW0 5
	182	#define AB8500_ANACONF1_EARDACLOWPOW 4
	183	#define AB8500_ANACONF1_EARSELCM 2
	184	#define AB8500_ANACONF1_HSHPEN 1
	185	#define AB8500_ANACONF1_EARDRVLOWPOW 0
	186
	187	/* AB8500_ANACONF2 */
	188	#define AB8500_ANACONF2_ENMIC1 7
	189	#define AB8500_ANACONF2_ENMIC2 6
	190	#define AB8500_ANACONF2_ENLINL 5
	191	#define AB8500_ANACONF2_ENLINR 4
	192	#define AB8500_ANACONF2_MUTMIC1 3
	193	#define AB8500_ANACONF2_MUTMIC2 2
	194	#define AB8500_ANACONF2_MUTLINL 1
	195	#define AB8500_ANACONF2_MUTLINR 0
	196
	197	/* AB8500_DIGMICCONF */
	198	#define AB8500_DIGMICCONF_ENDMIC1 7
	199	#define AB8500_DIGMICCONF_ENDMIC2 6
	200	#define AB8500_DIGMICCONF_ENDMIC3 5
	201	#define AB8500_DIGMICCONF_ENDMIC4 4
	202	#define AB8500_DIGMICCONF_ENDMIC5 3
	203	#define AB8500_DIGMICCONF_ENDMIC6 2
	204	#define AB8500_DIGMICCONF_HSFADSPEED 0
	205
	206	/* AB8500_ANACONF3 */
	207	#define AB8500_ANACONF3_MIC1SEL 7
	208	#define AB8500_ANACONF3_LINRSEL 6
	209	#define AB8500_ANACONF3_ENDRVHSL 5
	210	#define AB8500_ANACONF3_ENDRVHSR 4
	211	#define AB8500_ANACONF3_ENADCMIC 2
	212	#define AB8500_ANACONF3_ENADCLINL 1
	213	#define AB8500_ANACONF3_ENADCLINR 0
	214
	215	/* AB8500_ANACONF4 */
	216	#define AB8500_ANACONF4_DISPDVSS 7
	217	#define AB8500_ANACONF4_ENEAR 6
	218	#define AB8500_ANACONF4_ENHSL 5
	219	#define AB8500_ANACONF4_ENHSR 4
220	#define AB8500_ANACONF4_ENHFL 3
221	#define AB8500_ANACONF4_ENHFR 2
222	#define AB8500_ANACONF4_ENVIB1 1
223	#define AB8500_ANACONF4_ENVIB2 0
224
225	/* AB8500_DAPATHCONF */
226	#define AB8500_DAPATHCONF_ENDACEAR 6
227	#define AB8500_DAPATHCONF_ENDACHSL 5
228	#define AB8500_DAPATHCONF_ENDACHSR 4
229	#define AB8500_DAPATHCONF_ENDACHFL 3
230	#define AB8500_DAPATHCONF_ENDACHFR 2
231	#define AB8500_DAPATHCONF_ENDACVIB1 1
232	#define AB8500_DAPATHCONF_ENDACVIB2 0
233
234	/* AB8500_MUTECONF */
235	#define AB8500_MUTECONF_MUTEAR 6
236	#define AB8500_MUTECONF_MUTHSL 5
237	#define AB8500_MUTECONF_MUTHSR 4
238	#define AB8500_MUTECONF_MUTDACEAR 2
239	#define AB8500_MUTECONF_MUTDACHSL 1
240	#define AB8500_MUTECONF_MUTDACHSR 0
241
242	/* AB8500_SHORTCIRCONF */
243	#define AB8500_SHORTCIRCONF_ENSHORTPWD 7
244	#define AB8500_SHORTCIRCONF_EARSHORTDIS 6
245	#define AB8500_SHORTCIRCONF_HSSHORTDIS 5
246	#define AB8500_SHORTCIRCONF_HSPULLDEN 4
247	#define AB8500_SHORTCIRCONF_HSOSCEN 2
248	#define AB8500_SHORTCIRCONF_HSFADDIS 1
249	#define AB8500_SHORTCIRCONF_HSZCDDIS 0
250	/* Zero cross should be disabled */
251
252	/* AB8500_ANACONF5 */
253	#define AB8500_ANACONF5_ENCPHS 7
254	#define AB8500_ANACONF5_HSLDACTOLOL 5
255	#define AB8500_ANACONF5_HSRDACTOLOR 4
256	#define AB8500_ANACONF5_ENLOL 3
257	#define AB8500_ANACONF5_ENLOR 2
258	#define AB8500_ANACONF5_HSAUTOEN 0
259
260	/* AB8500_ENVCPCONF */
261	#define AB8500_ENVCPCONF_ENVDETHTHRE 4
262	#define AB8500_ENVCPCONF_ENVDETLTHRE 0
263	#define AB8500_ENVCPCONF_ENVDETHTHRE_MAX 0x0F
264	#define AB8500_ENVCPCONF_ENVDETLTHRE_MAX 0x0F
265
266	/* AB8500_SIGENVCONF */
267	#define AB8500_SIGENVCONF_CPLVEN 5
268	#define AB8500_SIGENVCONF_ENVDETCPEN 4
269	#define AB8500_SIGENVCONF_ENVDETTIME 0
270	#define AB8500_SIGENVCONF_ENVDETTIME_MAX 0x0F
271
272	/* AB8500_PWMGENCONF1 */
273	#define AB8500_PWMGENCONF1_PWMTOVIB1 7
274	#define AB8500_PWMGENCONF1_PWMTOVIB2 6
275	#define AB8500_PWMGENCONF1_PWM1CTRL 5
276	#define AB8500_PWMGENCONF1_PWM2CTRL 4
277	#define AB8500_PWMGENCONF1_PWM1NCTRL 3
278	#define AB8500_PWMGENCONF1_PWM1PCTRL 2
279	#define AB8500_PWMGENCONF1_PWM2NCTRL 1
280	#define AB8500_PWMGENCONF1_PWM2PCTRL 0
281
282	/* AB8500_PWMGENCONF2 */
283	/* AB8500_PWMGENCONF3 */
284	/* AB8500_PWMGENCONF4 */
285	/* AB8500_PWMGENCONF5 */
286	#define AB8500_PWMGENCONFX_PWMVIBXPOL 7
287	#define AB8500_PWMGENCONFX_PWMVIBXDUTCYC 0
288	#define AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX 0x64
289
290	/* AB8500_ANAGAIN1 */
291	/* AB8500_ANAGAIN2 */
292	#define AB8500_ANAGAINX_ENSEMICX 7
293	#define AB8500_ANAGAINX_LOWPOWMICX 6
294	#define AB8500_ANAGAINX_MICXGAIN 0
295	#define AB8500_ANAGAINX_MICXGAIN_MAX 0x1F
296
297	/* AB8500_ANAGAIN3 */
298	#define AB8500_ANAGAIN3_HSLGAIN 4
299	#define AB8500_ANAGAIN3_HSRGAIN 0
300	#define AB8500_ANAGAIN3_HSXGAIN_MAX 0x0F
301
302	/* AB8500_ANAGAIN4 */
303	#define AB8500_ANAGAIN4_LINLGAIN 4
304	#define AB8500_ANAGAIN4_LINRGAIN 0
305	#define AB8500_ANAGAIN4_LINXGAIN_MAX 0x0F
306
307	/* AB8500_DIGLINHSLGAIN */
308	/* AB8500_DIGLINHSRGAIN */
309	#define AB8500_DIGLINHSXGAIN_LINTOHSXGAIN 0
310	#define AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX 0x13
311
312	/* AB8500_ADFILTCONF */
313	#define AB8500_ADFILTCONF_AD1NH 7
314	#define AB8500_ADFILTCONF_AD2NH 6
315	#define AB8500_ADFILTCONF_AD3NH 5
316	#define AB8500_ADFILTCONF_AD4NH 4
317	#define AB8500_ADFILTCONF_AD1VOICE 3
318	#define AB8500_ADFILTCONF_AD2VOICE 2
319	#define AB8500_ADFILTCONF_AD3VOICE 1
320	#define AB8500_ADFILTCONF_AD4VOICE 0
321
322	/* AB8500_DIGIFCONF1 */
323	#define AB8500_DIGIFCONF1_ENMASTGEN 7
324	#define AB8500_DIGIFCONF1_IF1BITCLKOS1 6
325	#define AB8500_DIGIFCONF1_IF1BITCLKOS0 5
326	#define AB8500_DIGIFCONF1_ENFSBITCLK1 4
327	#define AB8500_DIGIFCONF1_IF0BITCLKOS1 2
328	#define AB8500_DIGIFCONF1_IF0BITCLKOS0 1
329	#define AB8500_DIGIFCONF1_ENFSBITCLK0 0
330
331	/* AB8500_DIGIFCONF2 */
332	#define AB8500_DIGIFCONF2_FSYNC0P 6
333	#define AB8500_DIGIFCONF2_BITCLK0P 5
334	#define AB8500_DIGIFCONF2_IF0DEL 4
335	#define AB8500_DIGIFCONF2_IF0FORMAT1 3
336	#define AB8500_DIGIFCONF2_IF0FORMAT0 2
337	#define AB8500_DIGIFCONF2_IF0WL1 1
338	#define AB8500_DIGIFCONF2_IF0WL0 0
339
340	/* AB8500_DIGIFCONF3 */
341	#define AB8500_DIGIFCONF3_IF0DATOIF1AD 7
342	#define AB8500_DIGIFCONF3_IF0CLKTOIF1CLK 6
343	#define AB8500_DIGIFCONF3_IF1MASTER 5
344	#define AB8500_DIGIFCONF3_IF1DATOIF0AD 3
345	#define AB8500_DIGIFCONF3_IF1CLKTOIF0CLK 2
346	#define AB8500_DIGIFCONF3_IF0MASTER 1
347	#define AB8500_DIGIFCONF3_IF0BFIFOEN 0
348
349	/* AB8500_DIGIFCONF4 */
350	#define AB8500_DIGIFCONF4_FSYNC1P 6
351	#define AB8500_DIGIFCONF4_BITCLK1P 5
352	#define AB8500_DIGIFCONF4_IF1DEL 4
353	#define AB8500_DIGIFCONF4_IF1FORMAT1 3
354	#define AB8500_DIGIFCONF4_IF1FORMAT0 2
355	#define AB8500_DIGIFCONF4_IF1WL1 1
356	#define AB8500_DIGIFCONF4_IF1WL0 0
357
358	/* AB8500_ADSLOTSELX */
da33d723 FB	359	#define AB8500_AD_OUT1 0x0
	360	#define AB8500_AD_OUT2 0x1
	361	#define AB8500_AD_OUT3 0x2
	362	#define AB8500_AD_OUT4 0x3
	363	#define AB8500_AD_OUT5 0x4
	364	#define AB8500_AD_OUT6 0x5
	365	#define AB8500_AD_OUT7 0x6
	366	#define AB8500_AD_OUT8 0x7
	367	#define AB8500_ZEROES 0x8
	368	#define AB8500_TRISTATE 0xF
679d7abd OL	369	#define AB8500_ADSLOTSELX_EVEN_SHIFT 0
679d7abd OL	370	#define AB8500_ADSLOTSELX_ODD_SHIFT 4
da33d723 FB	371	#define AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(out, slot) \
	372	((out) << (((slot) & 1) ? \
	373	AB8500_ADSLOTSELX_ODD_SHIFT : AB8500_ADSLOTSELX_EVEN_SHIFT))
679d7abd OL	374
	375	/* AB8500_ADSLOTHIZCTRL1 */
	376	/* AB8500_ADSLOTHIZCTRL2 */
	377	/* AB8500_ADSLOTHIZCTRL3 */
	378	/* AB8500_ADSLOTHIZCTRL4 */
	379	/* AB8500_DASLOTCONF1 */
	380	#define AB8500_DASLOTCONF1_DA12VOICE 7
	381	#define AB8500_DASLOTCONF1_SWAPDA12_34 6
	382	#define AB8500_DASLOTCONF1_DAI7TOADO1 5
	383
	384	/* AB8500_DASLOTCONF2 */
	385	#define AB8500_DASLOTCONF2_DAI8TOADO2 5
	386
	387	/* AB8500_DASLOTCONF3 */
	388	#define AB8500_DASLOTCONF3_DA34VOICE 7
	389	#define AB8500_DASLOTCONF3_DAI7TOADO3 5
	390
	391	/* AB8500_DASLOTCONF4 */
	392	#define AB8500_DASLOTCONF4_DAI8TOADO4 5
	393
	394	/* AB8500_DASLOTCONF5 */
	395	#define AB8500_DASLOTCONF5_DA56VOICE 7
	396	#define AB8500_DASLOTCONF5_DAI7TOADO5 5
	397
	398	/* AB8500_DASLOTCONF6 */
	399	#define AB8500_DASLOTCONF6_DAI8TOADO6 5
	400
	401	/* AB8500_DASLOTCONF7 */
	402	#define AB8500_DASLOTCONF7_DAI8TOADO7 5
	403
	404	/* AB8500_DASLOTCONF8 */
	405	#define AB8500_DASLOTCONF8_DAI7TOADO8 5
	406
	407	#define AB8500_DASLOTCONFX_SLTODAX_SHIFT 0
	408	#define AB8500_DASLOTCONFX_SLTODAX_MASK 0x1F
	409
	410	/* AB8500_CLASSDCONF1 */
	411	#define AB8500_CLASSDCONF1_PARLHF 7
	412	#define AB8500_CLASSDCONF1_PARLVIB 6
	413	#define AB8500_CLASSDCONF1_VIB1SWAPEN 3
	414	#define AB8500_CLASSDCONF1_VIB2SWAPEN 2
	415	#define AB8500_CLASSDCONF1_HFLSWAPEN 1
	416	#define AB8500_CLASSDCONF1_HFRSWAPEN 0
	417
	418	/* AB8500_CLASSDCONF2 */
	419	#define AB8500_CLASSDCONF2_FIRBYP3 7
	420	#define AB8500_CLASSDCONF2_FIRBYP2 6
	421	#define AB8500_CLASSDCONF2_FIRBYP1 5
	422	#define AB8500_CLASSDCONF2_FIRBYP0 4
	423	#define AB8500_CLASSDCONF2_HIGHVOLEN3 3
	424	#define AB8500_CLASSDCONF2_HIGHVOLEN2 2
	425	#define AB8500_CLASSDCONF2_HIGHVOLEN1 1
	426	#define AB8500_CLASSDCONF2_HIGHVOLEN0 0
	427
	428	/* AB8500_CLASSDCONF3 */
	429	#define AB8500_CLASSDCONF3_DITHHPGAIN 4
	430	#define AB8500_CLASSDCONF3_DITHHPGAIN_MAX 0x0A
	431	#define AB8500_CLASSDCONF3_DITHWGAIN 0
	432	#define AB8500_CLASSDCONF3_DITHWGAIN_MAX 0x0A
	433
	434	/* AB8500_DMICFILTCONF */
	435	#define AB8500_DMICFILTCONF_ANCINSEL 7
	436	#define AB8500_DMICFILTCONF_DA3TOEAR 6
	437	#define AB8500_DMICFILTCONF_DMIC1SINC3 5
438	#define AB8500_DMICFILTCONF_DMIC2SINC3 4
439	#define AB8500_DMICFILTCONF_DMIC3SINC3 3
440	#define AB8500_DMICFILTCONF_DMIC4SINC3 2
441	#define AB8500_DMICFILTCONF_DMIC5SINC3 1
442	#define AB8500_DMICFILTCONF_DMIC6SINC3 0
443
444	/* AB8500_DIGMULTCONF1 */
445	#define AB8500_DIGMULTCONF1_DATOHSLEN 7
446	#define AB8500_DIGMULTCONF1_DATOHSREN 6
447	#define AB8500_DIGMULTCONF1_AD1SEL 5
448	#define AB8500_DIGMULTCONF1_AD2SEL 4
449	#define AB8500_DIGMULTCONF1_AD3SEL 3
450	#define AB8500_DIGMULTCONF1_AD5SEL 2
451	#define AB8500_DIGMULTCONF1_AD6SEL 1
452	#define AB8500_DIGMULTCONF1_ANCSEL 0
453
454	/* AB8500_DIGMULTCONF2 */
455	#define AB8500_DIGMULTCONF2_DATOHFREN 7
456	#define AB8500_DIGMULTCONF2_DATOHFLEN 6
457	#define AB8500_DIGMULTCONF2_HFRSEL 5
458	#define AB8500_DIGMULTCONF2_HFLSEL 4
459	#define AB8500_DIGMULTCONF2_FIRSID1SEL 2
460	#define AB8500_DIGMULTCONF2_FIRSID2SEL 0
461
462	/* AB8500_ADDIGGAIN1 */
463	/* AB8500_ADDIGGAIN2 */
464	/* AB8500_ADDIGGAIN3 */
465	/* AB8500_ADDIGGAIN4 */
466	/* AB8500_ADDIGGAIN5 */
467	/* AB8500_ADDIGGAIN6 */
468	#define AB8500_ADDIGGAINX_FADEDISADX 6
469	#define AB8500_ADDIGGAINX_ADXGAIN_MAX 0x3F
470
471	/* AB8500_DADIGGAIN1 */
472	/* AB8500_DADIGGAIN2 */
473	/* AB8500_DADIGGAIN3 */
474	/* AB8500_DADIGGAIN4 */
475	/* AB8500_DADIGGAIN5 */
476	/* AB8500_DADIGGAIN6 */
477	#define AB8500_DADIGGAINX_FADEDISDAX 6
478	#define AB8500_DADIGGAINX_DAXGAIN_MAX 0x3F
479
480	/* AB8500_ADDIGLOOPGAIN1 */
481	/* AB8500_ADDIGLOOPGAIN2 */
482	#define AB8500_ADDIGLOOPGAINX_FADEDISADXL 6
483	#define AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX 0x3F
484
485	/* AB8500_HSLEARDIGGAIN */
486	#define AB8500_HSLEARDIGGAIN_HSSINC1 7
487	#define AB8500_HSLEARDIGGAIN_FADEDISHSL 4
488	#define AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX 0x09
489
490	/* AB8500_HSRDIGGAIN */
491	#define AB8500_HSRDIGGAIN_FADESPEED 6
492	#define AB8500_HSRDIGGAIN_FADEDISHSR 4
493	#define AB8500_HSRDIGGAIN_HSRDGAIN_MAX 0x09
494
495	/* AB8500_SIDFIRGAIN1 */
496	/* AB8500_SIDFIRGAIN2 */
497	#define AB8500_SIDFIRGAINX_FIRSIDXGAIN_MAX 0x1F
498
499	/* AB8500_ANCCONF1 */
500	#define AB8500_ANCCONF1_ANCIIRUPDATE 3
501	#define AB8500_ANCCONF1_ENANC 2
502	#define AB8500_ANCCONF1_ANCIIRINIT 1
503	#define AB8500_ANCCONF1_ANCFIRUPDATE 0
504
505	/* AB8500_ANCCONF2 */
506	#define AB8500_ANCCONF2_SHIFT 5
507	#define AB8500_ANCCONF2_MIN -0x10
508	#define AB8500_ANCCONF2_MAX 0xF
509
510	/* AB8500_ANCCONF3 */
511	#define AB8500_ANCCONF3_SHIFT 5
512	#define AB8500_ANCCONF3_MIN -0x10
513	#define AB8500_ANCCONF3_MAX 0xF
514
515	/* AB8500_ANCCONF4 */
516	#define AB8500_ANCCONF4_SHIFT 5
517	#define AB8500_ANCCONF4_MIN -0x10
518	#define AB8500_ANCCONF4_MAX 0xF
519
520	/* AB8500_ANC_FIR_COEFFS */
521	#define AB8500_ANC_FIR_COEFF_MIN -0x8000
522	#define AB8500_ANC_FIR_COEFF_MAX 0x7FFF
523	#define AB8500_ANC_FIR_COEFFS 15
524
525	/* AB8500_ANC_IIR_COEFFS */
526	#define AB8500_ANC_IIR_COEFF_MIN -0x800000
527	#define AB8500_ANC_IIR_COEFF_MAX 0x7FFFFF
528	#define AB8500_ANC_IIR_COEFFS 24
529	/* AB8500_ANC_WARP_DELAY */
530	#define AB8500_ANC_WARP_DELAY_SHIFT 16
531	#define AB8500_ANC_WARP_DELAY_MIN 0x0000
532	#define AB8500_ANC_WARP_DELAY_MAX 0xFFFF
533
534	/* AB8500_ANCCONF11 */
535	/* AB8500_ANCCONF12 */
536	/* AB8500_ANCCONF13 */
537	/* AB8500_ANCCONF14 */
538
539	/* AB8500_SIDFIRADR */
540	#define AB8500_SIDFIRADR_FIRSIDSET 7
541	#define AB8500_SIDFIRADR_ADDRESS_SHIFT 0
542	#define AB8500_SIDFIRADR_ADDRESS_MAX 0x7F
543
544	/* AB8500_SIDFIRCOEF1 */
545	/* AB8500_SIDFIRCOEF2 */
546	#define AB8500_SID_FIR_COEFF_MIN 0
547	#define AB8500_SID_FIR_COEFF_MAX 0xFFFF
548	#define AB8500_SID_FIR_COEFFS 128
549
550	/* AB8500_SIDFIRCONF */
551	#define AB8500_SIDFIRCONF_ENFIRSIDS 2
552	#define AB8500_SIDFIRCONF_FIRSIDSTOIF1 1
553	#define AB8500_SIDFIRCONF_FIRSIDBUSY 0
554
555	/* AB8500_AUDINTMASK1 */
556	/* AB8500_AUDINTSOURCE1 */
557	/* AB8500_AUDINTMASK2 */
558	/* AB8500_AUDINTSOURCE2 */
559
560	/* AB8500_FIFOCONF1 */
561	#define AB8500_FIFOCONF1_BFIFOMASK 0x80
562	#define AB8500_FIFOCONF1_BFIFO19M2 0x40
563	#define AB8500_FIFOCONF1_BFIFOINT_SHIFT 0
564	#define AB8500_FIFOCONF1_BFIFOINT_MAX 0x3F
565
566	/* AB8500_FIFOCONF2 */
567	#define AB8500_FIFOCONF2_BFIFOTX_SHIFT 0
568	#define AB8500_FIFOCONF2_BFIFOTX_MAX 0xFF
569
570	/* AB8500_FIFOCONF3 */
571	#define AB8500_FIFOCONF3_BFIFOEXSL_SHIFT 5
572	#define AB8500_FIFOCONF3_BFIFOEXSL_MAX 0x5
573	#define AB8500_FIFOCONF3_PREBITCLK0_SHIFT 2
574	#define AB8500_FIFOCONF3_PREBITCLK0_MAX 0x7
575	#define AB8500_FIFOCONF3_BFIFOMAST_SHIFT 1
576	#define AB8500_FIFOCONF3_BFIFORUN_SHIFT 0
577
578	/* AB8500_FIFOCONF4 */
579	#define AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT 0
580	#define AB8500_FIFOCONF4_BFIFOFRAMSW_MAX 0xFF
581
582	/* AB8500_FIFOCONF5 */
583	#define AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT 0
584	#define AB8500_FIFOCONF5_BFIFOWAKEUP_MAX 0xFF
585
586	/* AB8500_FIFOCONF6 */
587	#define AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT 0
588	#define AB8500_FIFOCONF6_BFIFOSAMPLE_MAX 0xFF
589
590	/* AB8500_AUDREV */
591
592	#endif