projects / mirror_ubuntu-jammy-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 80503b23 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| a1533d94 BS |
2 | /* |
| 3 | * AD193X Audio Codec driver | |
| 4 | * | |
| 5 | * Copyright 2010 Analog Devices Inc. | |
| a1533d94 BS |
6 | */ |
| 7 | ||
| 8 | #ifndef __AD193X_H__ | |
| 9 | #define __AD193X_H__ | |
| 10 | ||
| 6c3d713e LPC |
11 | #include <linux/regmap.h> |
| 12 | ||
| 13 | struct device; | |
| 14 | ||
| e5224f58 CP |
15 | enum ad193x_type { |
| 16 | AD193X, | |
| 17 | AD1933, | |
| 18 | AD1934, | |
| 19 | }; | |
| 20 | ||
| 6c3d713e | 21 | extern const struct regmap_config ad193x_regmap_config; |
| e5224f58 CP |
22 | int ad193x_probe(struct device *dev, struct regmap *regmap, |
| 23 | enum ad193x_type type); | |
| 6c3d713e | 24 | |
| 30ab1e78 | 25 | #define AD193X_PLL_CLK_CTRL0 0x00 |
| a1533d94 | 26 | #define AD193X_PLL_POWERDOWN 0x01 |
| f3aa7219 | 27 | #define AD193X_PLL_INPUT_MASK 0x6 |
| fab90aa4 BS |
28 | #define AD193X_PLL_INPUT_256 (0 << 1) |
| 29 | #define AD193X_PLL_INPUT_384 (1 << 1) | |
| 30 | #define AD193X_PLL_INPUT_512 (2 << 1) | |
| 31 | #define AD193X_PLL_INPUT_768 (3 << 1) | |
| 30ab1e78 | 32 | #define AD193X_PLL_CLK_CTRL1 0x01 |
| 59529473 CC |
33 | #define AD193X_PLL_SRC_MASK 0x03 |
| 34 | #define AD193X_PLL_DAC_SRC_PLL 0 | |
| 35 | #define AD193X_PLL_DAC_SRC_MCLK 1 | |
| 36 | #define AD193X_PLL_CLK_SRC_PLL (0 << 1) | |
| 37 | #define AD193X_PLL_CLK_SRC_MCLK (1 << 1) | |
| 30ab1e78 | 38 | #define AD193X_DAC_CTRL0 0x02 |
| a1533d94 BS |
39 | #define AD193X_DAC_POWERDOWN 0x01 |
| 40 | #define AD193X_DAC_SERFMT_MASK 0xC0 | |
| 41 | #define AD193X_DAC_SERFMT_STEREO (0 << 6) | |
| 42 | #define AD193X_DAC_SERFMT_TDM (1 << 6) | |
| 30ab1e78 | 43 | #define AD193X_DAC_CTRL1 0x03 |
| a1533d94 BS |
44 | #define AD193X_DAC_CHAN_SHFT 1 |
| 45 | #define AD193X_DAC_CHAN_MASK (3 << AD193X_DAC_CHAN_SHFT) | |
| 46 | #define AD193X_DAC_LCR_MASTER (1 << 4) | |
| 47 | #define AD193X_DAC_BCLK_MASTER (1 << 5) | |
| 48 | #define AD193X_DAC_LEFT_HIGH (1 << 3) | |
| 49 | #define AD193X_DAC_BCLK_INV (1 << 7) | |
| b82ca578 LPC |
50 | #define AD193X_DAC_FMT_MASK (AD193X_DAC_LCR_MASTER | \ |
| 51 | AD193X_DAC_BCLK_MASTER | AD193X_DAC_LEFT_HIGH | AD193X_DAC_BCLK_INV) | |
| 30ab1e78 | 52 | #define AD193X_DAC_CTRL2 0x04 |
| 95c93d85 | 53 | #define AD193X_DAC_WORD_LEN_SHFT 3 |
| bf545ed7 | 54 | #define AD193X_DAC_WORD_LEN_MASK 0x18 |
| a1533d94 | 55 | #define AD193X_DAC_MASTER_MUTE 1 |
| 30ab1e78 | 56 | #define AD193X_DAC_CHNL_MUTE 0x05 |
| a1533d94 BS |
57 | #define AD193X_DACL1_MUTE 0 |
| 58 | #define AD193X_DACR1_MUTE 1 | |
| 59 | #define AD193X_DACL2_MUTE 2 | |
| 60 | #define AD193X_DACR2_MUTE 3 | |
| 61 | #define AD193X_DACL3_MUTE 4 | |
| 62 | #define AD193X_DACR3_MUTE 5 | |
| 63 | #define AD193X_DACL4_MUTE 6 | |
| 64 | #define AD193X_DACR4_MUTE 7 | |
| 30ab1e78 LPC |
65 | #define AD193X_DAC_L1_VOL 0x06 |
| 66 | #define AD193X_DAC_R1_VOL 0x07 | |
| 67 | #define AD193X_DAC_L2_VOL 0x08 | |
| 68 | #define AD193X_DAC_R2_VOL 0x09 | |
| 69 | #define AD193X_DAC_L3_VOL 0x0a | |
| 70 | #define AD193X_DAC_R3_VOL 0x0b | |
| 71 | #define AD193X_DAC_L4_VOL 0x0c | |
| 72 | #define AD193X_DAC_R4_VOL 0x0d | |
| 73 | #define AD193X_ADC_CTRL0 0x0e | |
| a1533d94 BS |
74 | #define AD193X_ADC_POWERDOWN 0x01 |
| 75 | #define AD193X_ADC_HIGHPASS_FILTER 1 | |
| 76 | #define AD193X_ADCL1_MUTE 2 | |
| 77 | #define AD193X_ADCR1_MUTE 3 | |
| 78 | #define AD193X_ADCL2_MUTE 4 | |
| 79 | #define AD193X_ADCR2_MUTE 5 | |
| 30ab1e78 | 80 | #define AD193X_ADC_CTRL1 0x0f |
| a1533d94 BS |
81 | #define AD193X_ADC_SERFMT_MASK 0x60 |
| 82 | #define AD193X_ADC_SERFMT_STEREO (0 << 5) | |
| bf545ed7 | 83 | #define AD193X_ADC_SERFMT_TDM (1 << 5) |
| a1533d94 BS |
84 | #define AD193X_ADC_SERFMT_AUX (2 << 5) |
| 85 | #define AD193X_ADC_WORD_LEN_MASK 0x3 | |
| 30ab1e78 | 86 | #define AD193X_ADC_CTRL2 0x10 |
| a1533d94 BS |
87 | #define AD193X_ADC_CHAN_SHFT 4 |
| 88 | #define AD193X_ADC_CHAN_MASK (3 << AD193X_ADC_CHAN_SHFT) | |
| 89 | #define AD193X_ADC_LCR_MASTER (1 << 3) | |
| 90 | #define AD193X_ADC_BCLK_MASTER (1 << 6) | |
| 91 | #define AD193X_ADC_LEFT_HIGH (1 << 2) | |
| 92 | #define AD193X_ADC_BCLK_INV (1 << 1) | |
| b82ca578 LPC |
93 | #define AD193X_ADC_FMT_MASK (AD193X_ADC_LCR_MASTER | \ |
| 94 | AD193X_ADC_BCLK_MASTER | AD193X_ADC_LEFT_HIGH | AD193X_ADC_BCLK_INV) | |
| 95 | ||
| 96 | #define AD193X_2_CHANNELS 0 | |
| 97 | #define AD193X_4_CHANNELS 1 | |
| 98 | #define AD193X_8_CHANNELS 2 | |
| 99 | #define AD193X_16_CHANNELS 3 | |
| a1533d94 BS |
100 | |
| 101 | #define AD193X_NUM_REGS 17 | |
| 102 | ||
| 59529473 CC |
103 | #define AD193X_SYSCLK_PLL 0 |
| 104 | #define AD193X_SYSCLK_MCLK 1 | |
| 105 | ||
| a1533d94 | 106 | #endif |