[mirror_ubuntu-artful-kernel.git] / sound / soc / codecs / ak4642.c

/*
 * ak4642.c  --  AK4642/AK4643 ALSA Soc Audio driver
 *
 * Copyright (C) 2009 Renesas Solutions Corp.
 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
 *
 * Based on wm8731.c by Richard Purdie
 * Based on ak4535.c by Richard Purdie
 * Based on wm8753.c by Liam Girdwood
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/* ** CAUTION **
 *
 * This is very simple driver.
 * It can use headphone output / stereo input only
 *
 * AK4642 is tested.
 * AK4643 is tested.
 * AK4648 is tested.
 */

#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>

#define PW_MGMT1	0x00
#define PW_MGMT2	0x01
#define SG_SL1		0x02
#define SG_SL2		0x03
#define MD_CTL1		0x04
#define MD_CTL2		0x05
#define TIMER		0x06
#define ALC_CTL1	0x07
#define ALC_CTL2	0x08
#define L_IVC		0x09
#define L_DVC		0x0a
#define ALC_CTL3	0x0b
#define R_IVC		0x0c
#define R_DVC		0x0d
#define MD_CTL3		0x0e
#define MD_CTL4		0x0f
#define PW_MGMT3	0x10
#define DF_S		0x11
#define FIL3_0		0x12
#define FIL3_1		0x13
#define FIL3_2		0x14
#define FIL3_3		0x15
#define EQ_0		0x16
#define EQ_1		0x17
#define EQ_2		0x18
#define EQ_3		0x19
#define EQ_4		0x1a
#define EQ_5		0x1b
#define FIL1_0		0x1c
#define FIL1_1		0x1d
#define FIL1_2		0x1e
#define FIL1_3		0x1f
#define PW_MGMT4	0x20
#define MD_CTL5		0x21
#define LO_MS		0x22
#define HP_MS		0x23
#define SPK_MS		0x24

/* PW_MGMT1*/
#define PMVCM		(1 << 6) /* VCOM Power Management */
#define PMMIN		(1 << 5) /* MIN Input Power Management */
#define PMDAC		(1 << 2) /* DAC Power Management */
#define PMADL		(1 << 0) /* MIC Amp Lch and ADC Lch Power Management */

/* PW_MGMT2 */
#define HPMTN		(1 << 6)
#define PMHPL		(1 << 5)
#define PMHPR		(1 << 4)
#define MS		(1 << 3) /* master/slave select */
#define MCKO		(1 << 1)
#define PMPLL		(1 << 0)

#define PMHP_MASK	(PMHPL | PMHPR)
#define PMHP		PMHP_MASK

/* PW_MGMT3 */
#define PMADR		(1 << 0) /* MIC L / ADC R Power Management */

/* SG_SL1 */
#define MINS		(1 << 6) /* Switch from MIN to Speaker */
#define DACL		(1 << 4) /* Switch from DAC to Stereo or Receiver */
#define PMMP		(1 << 2) /* MPWR pin Power Management */
#define MGAIN0		(1 << 0) /* MIC amp gain*/

/* TIMER */
#define ZTM(param)	((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
#define WTM(param)	(((param & 0x4) << 4) | ((param & 0x3) << 2))

/* ALC_CTL1 */
#define ALC		(1 << 5) /* ALC Enable */
#define LMTH0		(1 << 0) /* ALC Limiter / Recovery Level */

/* MD_CTL1 */
#define PLL3		(1 << 7)
#define PLL2		(1 << 6)
#define PLL1		(1 << 5)
#define PLL0		(1 << 4)
#define PLL_MASK	(PLL3 | PLL2 | PLL1 | PLL0)

#define BCKO_MASK	(1 << 3)
#define BCKO_64		BCKO_MASK

#define DIF_MASK	(3 << 0)
#define DSP		(0 << 0)
#define RIGHT_J		(1 << 0)
#define LEFT_J		(2 << 0)
#define I2S		(3 << 0)

/* MD_CTL2 */
#define FS0		(1 << 0)
#define FS1		(1 << 1)
#define FS2		(1 << 2)
#define FS3		(1 << 5)
#define FS_MASK		(FS0 | FS1 | FS2 | FS3)

/* MD_CTL3 */
#define BST1		(1 << 3)

/* MD_CTL4 */
#define DACH		(1 << 0)

/*
 * Playback Volume (table 39)
 *
 * max : 0x00 : +12.0 dB
 *       ( 0.5 dB step )
 * min : 0xFE : -115.0 dB
 * mute: 0xFF
 */
static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);

static const struct snd_kcontrol_new ak4642_snd_controls[] = {

	SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
			 0, 0xFF, 1, out_tlv),
};

static const struct snd_kcontrol_new ak4642_headphone_control =
	SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);

static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
	SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
};

static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {

	/* Outputs */
	SND_SOC_DAPM_OUTPUT("HPOUTL"),
	SND_SOC_DAPM_OUTPUT("HPOUTR"),
	SND_SOC_DAPM_OUTPUT("LINEOUT"),

	SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
	SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
	SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
			    &ak4642_headphone_control),

	SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),

	SND_SOC_DAPM_MIXER("LINEOUT Mixer", PW_MGMT1, 3, 0,
			   &ak4642_lout_mixer_controls[0],
			   ARRAY_SIZE(ak4642_lout_mixer_controls)),

	/* DAC */
	SND_SOC_DAPM_DAC("DAC", "HiFi Playback", PW_MGMT1, 2, 0),
};

static const struct snd_soc_dapm_route ak4642_intercon[] = {

	/* Outputs */
	{"HPOUTL", NULL, "HPL Out"},
	{"HPOUTR", NULL, "HPR Out"},
	{"LINEOUT", NULL, "LINEOUT Mixer"},

	{"HPL Out", NULL, "Headphone Enable"},
	{"HPR Out", NULL, "Headphone Enable"},

	{"Headphone Enable", "Switch", "DACH"},

	{"DACH", NULL, "DAC"},

	{"LINEOUT Mixer", "DACL", "DAC"},
};

/*
 * ak4642 register cache
 */
static const struct reg_default ak4642_reg[] = {
	{  0, 0x00 }, {  1, 0x00 }, {  2, 0x01 }, {  3, 0x00 },
	{  4, 0x02 }, {  5, 0x00 }, {  6, 0x00 }, {  7, 0x00 },
	{  8, 0xe1 }, {  9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
	{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0x08 },
	{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
	{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
	{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
	{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
	{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
	{ 36, 0x00 },
};

static const struct reg_default ak4648_reg[] = {
	{  0, 0x00 }, {  1, 0x00 }, {  2, 0x01 }, {  3, 0x00 },
	{  4, 0x02 }, {  5, 0x00 }, {  6, 0x00 }, {  7, 0x00 },
	{  8, 0xe1 }, {  9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
	{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0xb8 },
	{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
	{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
	{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
	{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
	{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
	{ 36, 0x00 }, { 37, 0x88 }, { 38, 0x88 }, { 39, 0x08 },
};

static int ak4642_dai_startup(struct snd_pcm_substream *substream,
			      struct snd_soc_dai *dai)
{
	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	struct snd_soc_codec *codec = dai->codec;

	if (is_play) {
		/*
		 * start headphone output
		 *
		 * PLL, Master Mode
		 * Audio I/F Format :MSB justified (ADC & DAC)
		 * Bass Boost Level : Middle
		 *
		 * This operation came from example code of
		 * "ASAHI KASEI AK4642" (japanese) manual p97.
		 */
		snd_soc_write(codec, L_IVC, 0x91); /* volume */
		snd_soc_write(codec, R_IVC, 0x91); /* volume */
	} else {
		/*
		 * start stereo input
		 *
		 * PLL Master Mode
		 * Audio I/F Format:MSB justified (ADC & DAC)
		 * Pre MIC AMP:+20dB
		 * MIC Power On
		 * ALC setting:Refer to Table 35
		 * ALC bit=“1”
		 *
		 * This operation came from example code of
		 * "ASAHI KASEI AK4642" (japanese) manual p94.
		 */
		snd_soc_update_bits(codec, SG_SL1, PMMP | MGAIN0, PMMP | MGAIN0);
		snd_soc_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
		snd_soc_write(codec, ALC_CTL1, ALC | LMTH0);
		snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL);
		snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
	}

	return 0;
}

static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
			       struct snd_soc_dai *dai)
{
	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	struct snd_soc_codec *codec = dai->codec;

	if (is_play) {
	} else {
		/* stop stereo input */
		snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
		snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
		snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
	}
}

static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
	int clk_id, unsigned int freq, int dir)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	u8 pll;

	switch (freq) {
	case 11289600:
		pll = PLL2;
		break;
	case 12288000:
		pll = PLL2 | PLL0;
		break;
	case 12000000:
		pll = PLL2 | PLL1;
		break;
	case 24000000:
		pll = PLL2 | PLL1 | PLL0;
		break;
	case 13500000:
		pll = PLL3 | PLL2;
		break;
	case 27000000:
		pll = PLL3 | PLL2 | PLL0;
		break;
	default:
		return -EINVAL;
	}
	snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);

	return 0;
}

static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
	struct snd_soc_codec *codec = dai->codec;
	u8 data;
	u8 bcko;

	data = MCKO | PMPLL; /* use MCKO */
	bcko = 0;

	/* set master/slave audio interface */
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		data |= MS;
		bcko = BCKO_64;
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		break;
	default:
		return -EINVAL;
	}
	snd_soc_update_bits(codec, PW_MGMT2, MS | MCKO | PMPLL, data);
	snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);

	/* format type */
	data = 0;
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_LEFT_J:
		data = LEFT_J;
		break;
	case SND_SOC_DAIFMT_I2S:
		data = I2S;
		break;
	/* FIXME
	 * Please add RIGHT_J / DSP support here
	 */
	default:
		return -EINVAL;
	}
	snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);

	return 0;
}

static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
				struct snd_pcm_hw_params *params,
				struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	u8 rate;

	switch (params_rate(params)) {
	case 7350:
		rate = FS2;
		break;
	case 8000:
		rate = 0;
		break;
	case 11025:
		rate = FS2 | FS0;
		break;
	case 12000:
		rate = FS0;
		break;
	case 14700:
		rate = FS2 | FS1;
		break;
	case 16000:
		rate = FS1;
		break;
	case 22050:
		rate = FS2 | FS1 | FS0;
		break;
	case 24000:
		rate = FS1 | FS0;
		break;
	case 29400:
		rate = FS3 | FS2 | FS1;
		break;
	case 32000:
		rate = FS3 | FS1;
		break;
	case 44100:
		rate = FS3 | FS2 | FS1 | FS0;
		break;
	case 48000:
		rate = FS3 | FS1 | FS0;
		break;
	default:
		return -EINVAL;
	}
	snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);

	return 0;
}

static int ak4642_set_bias_level(struct snd_soc_codec *codec,
				 enum snd_soc_bias_level level)
{
	switch (level) {
	case SND_SOC_BIAS_OFF:
		snd_soc_write(codec, PW_MGMT1, 0x00);
		break;
	default:
		snd_soc_update_bits(codec, PW_MGMT1, PMVCM, PMVCM);
		break;
	}
	codec->dapm.bias_level = level;

	return 0;
}

static const struct snd_soc_dai_ops ak4642_dai_ops = {
	.startup	= ak4642_dai_startup,
	.shutdown	= ak4642_dai_shutdown,
	.set_sysclk	= ak4642_dai_set_sysclk,
	.set_fmt	= ak4642_dai_set_fmt,
	.hw_params	= ak4642_dai_hw_params,
};

static struct snd_soc_dai_driver ak4642_dai = {
	.name = "ak4642-hifi",
	.playback = {
		.stream_name = "Playback",
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE },
	.capture = {
		.stream_name = "Capture",
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_48000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE },
	.ops = &ak4642_dai_ops,
	.symmetric_rates = 1,
};

static int ak4642_resume(struct snd_soc_codec *codec)
{
	struct regmap *regmap = dev_get_regmap(codec->dev, NULL);

	regcache_mark_dirty(regmap);
	regcache_sync(regmap);
	return 0;
}


static int ak4642_probe(struct snd_soc_codec *codec)
{
	int ret;

	ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
	if (ret < 0) {
		dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
		return ret;
	}

	ak4642_set_bias_level(codec, SND_SOC_BIAS_STANDBY);

	return 0;
}

static int ak4642_remove(struct snd_soc_codec *codec)
{
	ak4642_set_bias_level(codec, SND_SOC_BIAS_OFF);
	return 0;
}

static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
	.probe			= ak4642_probe,
	.remove			= ak4642_remove,
	.resume			= ak4642_resume,
	.set_bias_level		= ak4642_set_bias_level,
	.controls		= ak4642_snd_controls,
	.num_controls		= ARRAY_SIZE(ak4642_snd_controls),
	.dapm_widgets		= ak4642_dapm_widgets,
	.num_dapm_widgets	= ARRAY_SIZE(ak4642_dapm_widgets),
	.dapm_routes		= ak4642_intercon,
	.num_dapm_routes	= ARRAY_SIZE(ak4642_intercon),
};

static const struct regmap_config ak4642_regmap = {
	.reg_bits		= 8,
	.val_bits		= 8,
	.max_register		= ARRAY_SIZE(ak4642_reg) + 1,
	.reg_defaults		= ak4642_reg,
	.num_reg_defaults	= ARRAY_SIZE(ak4642_reg),
};

static const struct regmap_config ak4648_regmap = {
	.reg_bits		= 8,
	.val_bits		= 8,
	.max_register		= ARRAY_SIZE(ak4648_reg) + 1,
	.reg_defaults		= ak4648_reg,
	.num_reg_defaults	= ARRAY_SIZE(ak4648_reg),
};

static struct of_device_id ak4642_of_match[];
static int ak4642_i2c_probe(struct i2c_client *i2c,
			    const struct i2c_device_id *id)
{
	struct device_node *np = i2c->dev.of_node;
	const struct regmap_config *regmap_config = NULL;
	struct regmap *regmap;

	if (np) {
		const struct of_device_id *of_id;

		of_id = of_match_device(ak4642_of_match, &i2c->dev);
		if (of_id)
			regmap_config = of_id->data;
	} else {
		regmap_config = (const struct regmap_config *)id->driver_data;
	}

	if (!regmap_config) {
		dev_err(&i2c->dev, "Unknown device type\n");
		return -EINVAL;
	}

	regmap = devm_regmap_init_i2c(i2c, regmap_config);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	return snd_soc_register_codec(&i2c->dev,
				      &soc_codec_dev_ak4642, &ak4642_dai, 1);
}

static int ak4642_i2c_remove(struct i2c_client *client)
{
	snd_soc_unregister_codec(&client->dev);
	return 0;
}

static struct of_device_id ak4642_of_match[] = {
	{ .compatible = "asahi-kasei,ak4642",	.data = &ak4642_regmap},
	{ .compatible = "asahi-kasei,ak4643",	.data = &ak4642_regmap},
	{ .compatible = "asahi-kasei,ak4648",	.data = &ak4648_regmap},
	{},
};
MODULE_DEVICE_TABLE(of, ak4642_of_match);

static const struct i2c_device_id ak4642_i2c_id[] = {
	{ "ak4642", (kernel_ulong_t)&ak4642_regmap },
	{ "ak4643", (kernel_ulong_t)&ak4642_regmap },
	{ "ak4648", (kernel_ulong_t)&ak4648_regmap },
	{ }
};
MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);

static struct i2c_driver ak4642_i2c_driver = {
	.driver = {
		.name = "ak4642-codec",
		.owner = THIS_MODULE,
		.of_match_table = ak4642_of_match,
	},
	.probe		= ak4642_i2c_probe,
	.remove		= ak4642_i2c_remove,
	.id_table	= ak4642_i2c_id,
};

module_i2c_driver(ak4642_i2c_driver);

MODULE_DESCRIPTION("Soc AK4642 driver");
MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
a3a83d9a KM	1	/*
	2	* ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
	3	*
	4	* Copyright (C) 2009 Renesas Solutions Corp.
	5	* Kuninori Morimoto <morimoto.kuninori@renesas.com>
	6	*
	7	* Based on wm8731.c by Richard Purdie
	8	* Based on ak4535.c by Richard Purdie
	9	* Based on wm8753.c by Liam Girdwood
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	/* CAUTION
	17	*
	18	* This is very simple driver.
	19	* It can use headphone output / stereo input only
	20	*
20211391	21	* AK4642 is tested.
a3a83d9a	22	* AK4643 is tested.
a9317e8b	23	* AK4648 is tested.
a3a83d9a KM	24	*/
a3a83d9a KM	25
a3a83d9a	26	#include <linux/delay.h>
a3a83d9a	27	#include <linux/i2c.h>
5a0e3ad6	28	#include <linux/slab.h>
bbf1453e	29	#include <linux/of_device.h>
da155d5b	30	#include <linux/module.h>
4574cd94	31	#include <linux/regmap.h>
ce6120cc	32	#include <sound/soc.h>
a3a83d9a	33	#include <sound/initval.h>
a300de3c	34	#include <sound/tlv.h>
a3a83d9a	35
a3a83d9a KM	36	#define PW_MGMT1 0x00
	37	#define PW_MGMT2 0x01
	38	#define SG_SL1 0x02
	39	#define SG_SL2 0x03
	40	#define MD_CTL1 0x04
	41	#define MD_CTL2 0x05
	42	#define TIMER 0x06
	43	#define ALC_CTL1 0x07
	44	#define ALC_CTL2 0x08
	45	#define L_IVC 0x09
	46	#define L_DVC 0x0a
	47	#define ALC_CTL3 0x0b
	48	#define R_IVC 0x0c
	49	#define R_DVC 0x0d
	50	#define MD_CTL3 0x0e
	51	#define MD_CTL4 0x0f
	52	#define PW_MGMT3 0x10
	53	#define DF_S 0x11
	54	#define FIL3_0 0x12
	55	#define FIL3_1 0x13
	56	#define FIL3_2 0x14
	57	#define FIL3_3 0x15
	58	#define EQ_0 0x16
	59	#define EQ_1 0x17
	60	#define EQ_2 0x18
	61	#define EQ_3 0x19
	62	#define EQ_4 0x1a
	63	#define EQ_5 0x1b
	64	#define FIL1_0 0x1c
	65	#define FIL1_1 0x1d
	66	#define FIL1_2 0x1e
	67	#define FIL1_3 0x1f
	68	#define PW_MGMT4 0x20
	69	#define MD_CTL5 0x21
	70	#define LO_MS 0x22
	71	#define HP_MS 0x23
	72	#define SPK_MS 0x24
	73
a3471239 KM	74	/* PW_MGMT1*/
	75	#define PMVCM (1 << 6) /* VCOM Power Management */
	76	#define PMMIN (1 << 5) /* MIN Input Power Management */
	77	#define PMDAC (1 << 2) /* DAC Power Management */
	78	#define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
	79
0643ce8f KM	80	/* PW_MGMT2 */
	81	#define HPMTN (1 << 6)
	82	#define PMHPL (1 << 5)
	83	#define PMHPR (1 << 4)
	84	#define MS (1 << 3) /* master/slave select */
	85	#define MCKO (1 << 1)
	86	#define PMPLL (1 << 0)
	87
	88	#define PMHP_MASK (PMHPL \| PMHPR)
	89	#define PMHP PMHP_MASK
	90
a3471239 KM	91	/* PW_MGMT3 */
	92	#define PMADR (1 << 0) /* MIC L / ADC R Power Management */
	93
	94	/* SG_SL1 */
	95	#define MINS (1 << 6) /* Switch from MIN to Speaker */
	96	#define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
	97	#define PMMP (1 << 2) /* MPWR pin Power Management */
	98	#define MGAIN0 (1 << 0) /* MIC amp gain*/
	99
	100	/* TIMER */
	101	#define ZTM(param) ((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
	102	#define WTM(param) (((param & 0x4) << 4) \| ((param & 0x3) << 2))
	103
	104	/* ALC_CTL1 */
	105	#define ALC (1 << 5) /* ALC Enable */
	106	#define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
	107
4b6316b4 KM	108	/* MD_CTL1 */
	109	#define PLL3 (1 << 7)
	110	#define PLL2 (1 << 6)
	111	#define PLL1 (1 << 5)
	112	#define PLL0 (1 << 4)
	113	#define PLL_MASK (PLL3 \| PLL2 \| PLL1 \| PLL0)
	114
0643ce8f KM	115	#define BCKO_MASK (1 << 3)
	116	#define BCKO_64 BCKO_MASK
	117
cb9c130a KM	118	#define DIF_MASK (3 << 0)
	119	#define DSP (0 << 0)
	120	#define RIGHT_J (1 << 0)
	121	#define LEFT_J (2 << 0)
	122	#define I2S (3 << 0)
	123
1ad747ca KM	124	/* MD_CTL2 */
	125	#define FS0 (1 << 0)
	126	#define FS1 (1 << 1)
	127	#define FS2 (1 << 2)
	128	#define FS3 (1 << 5)
	129	#define FS_MASK (FS0 \| FS1 \| FS2 \| FS3)
	130
a3471239 KM	131	/* MD_CTL3 */
	132	#define BST1 (1 << 3)
	133
	134	/* MD_CTL4 */
	135	#define DACH (1 << 0)
a3a83d9a	136
a300de3c KM	137	/*
	138	* Playback Volume (table 39)
	139	*
	140	* max : 0x00 : +12.0 dB
	141	* ( 0.5 dB step )
	142	* min : 0xFE : -115.0 dB
	143	* mute: 0xFF
	144	*/
1f99e44c	145	static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);
a300de3c KM	146
	147	static const struct snd_kcontrol_new ak4642_snd_controls[] = {
	148
	149	SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
	150	0, 0xFF, 1, out_tlv),
	151	};
	152
e555cf36 KM	153	static const struct snd_kcontrol_new ak4642_headphone_control =
e555cf36 KM	154	SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);
24747dae	155
e8c83dbf KM	156	static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
	157	SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
	158	};
	159
24747dae KM	160	static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {
	161
	162	/* Outputs */
	163	SND_SOC_DAPM_OUTPUT("HPOUTL"),
	164	SND_SOC_DAPM_OUTPUT("HPOUTR"),
e8c83dbf	165	SND_SOC_DAPM_OUTPUT("LINEOUT"),
24747dae	166
e555cf36 KM	167	SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
	168	SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
	169	SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
	170	&ak4642_headphone_control),
24747dae	171
e555cf36	172	SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),
24747dae	173
e8c83dbf KM	174	SND_SOC_DAPM_MIXER("LINEOUT Mixer", PW_MGMT1, 3, 0,
	175	&ak4642_lout_mixer_controls[0],
	176	ARRAY_SIZE(ak4642_lout_mixer_controls)),
	177
24747dae KM	178	/* DAC */
	179	SND_SOC_DAPM_DAC("DAC", "HiFi Playback", PW_MGMT1, 2, 0),
	180	};
	181
	182	static const struct snd_soc_dapm_route ak4642_intercon[] = {
	183
	184	/* Outputs */
e555cf36 KM	185	{"HPOUTL", NULL, "HPL Out"},
e555cf36 KM	186	{"HPOUTR", NULL, "HPR Out"},
e8c83dbf	187	{"LINEOUT", NULL, "LINEOUT Mixer"},
24747dae	188
e555cf36 KM	189	{"HPL Out", NULL, "Headphone Enable"},
	190	{"HPR Out", NULL, "Headphone Enable"},
	191
	192	{"Headphone Enable", "Switch", "DACH"},
	193
	194	{"DACH", NULL, "DAC"},
	195
e8c83dbf	196	{"LINEOUT Mixer", "DACL", "DAC"},
24747dae	197	};
a300de3c	198
a3a83d9a KM	199	/*
	200	* ak4642 register cache
	201	*/
4574cd94 MB	202	static const struct reg_default ak4642_reg[] = {
	203	{ 0, 0x00 }, { 1, 0x00 }, { 2, 0x01 }, { 3, 0x00 },
	204	{ 4, 0x02 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
	205	{ 8, 0xe1 }, { 9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
	206	{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0x08 },
	207	{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
	208	{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
	209	{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
	210	{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
	211	{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
	212	{ 36, 0x00 },
a3a83d9a KM	213	};
a3a83d9a KM	214
4574cd94 MB	215	static const struct reg_default ak4648_reg[] = {
	216	{ 0, 0x00 }, { 1, 0x00 }, { 2, 0x01 }, { 3, 0x00 },
	217	{ 4, 0x02 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
	218	{ 8, 0xe1 }, { 9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
	219	{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0xb8 },
	220	{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
	221	{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
	222	{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
	223	{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
	224	{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
	225	{ 36, 0x00 }, { 37, 0x88 }, { 38, 0x88 }, { 39, 0x08 },
a9317e8b KM	226	};
a9317e8b KM	227
a3a83d9a KM	228	static int ak4642_dai_startup(struct snd_pcm_substream *substream,
	229	struct snd_soc_dai *dai)
	230	{
	231	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	232	struct snd_soc_codec *codec = dai->codec;
	233
	234	if (is_play) {
	235	/*
	236	* start headphone output
	237	*
	238	* PLL, Master Mode
	239	* Audio I/F Format :MSB justified (ADC & DAC)
a3a83d9a KM	240	* Bass Boost Level : Middle
	241	*
	242	* This operation came from example code of
	243	* "ASAHI KASEI AK4642" (japanese) manual p97.
a3a83d9a	244	*/
b91470bb AL	245	snd_soc_write(codec, L_IVC, 0x91); /* volume */
b91470bb AL	246	snd_soc_write(codec, R_IVC, 0x91); /* volume */
a3a83d9a KM	247	} else {
	248	/*
	249	* start stereo input
	250	*
	251	* PLL Master Mode
	252	* Audio I/F Format:MSB justified (ADC & DAC)
a3a83d9a KM	253	* Pre MIC AMP:+20dB
	254	* MIC Power On
	255	* ALC setting:Refer to Table 35
	256	* ALC bit=“1”
	257	*
	258	* This operation came from example code of
	259	* "ASAHI KASEI AK4642" (japanese) manual p94.
	260	*/
7b5bfb82	261	snd_soc_update_bits(codec, SG_SL1, PMMP \| MGAIN0, PMMP \| MGAIN0);
b91470bb AL	262	snd_soc_write(codec, TIMER, ZTM(0x3) \| WTM(0x3));
b91470bb AL	263	snd_soc_write(codec, ALC_CTL1, ALC \| LMTH0);
ed2dd7da	264	snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL);
a3471239	265	snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
a3a83d9a KM	266	}
	267
	268	return 0;
	269	}
	270
	271	static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
	272	struct snd_soc_dai *dai)
	273	{
	274	int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	275	struct snd_soc_codec *codec = dai->codec;
	276
	277	if (is_play) {
a3a83d9a KM	278	} else {
a3a83d9a KM	279	/* stop stereo input */
a3471239 KM	280	snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
	281	snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
	282	snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
a3a83d9a KM	283	}
	284	}
	285
	286	static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
	287	int clk_id, unsigned int freq, int dir)
	288	{
	289	struct snd_soc_codec *codec = codec_dai->codec;
4b6316b4 KM	290	u8 pll;
	291
	292	switch (freq) {
	293	case 11289600:
	294	pll = PLL2;
	295	break;
	296	case 12288000:
	297	pll = PLL2 \| PLL0;
	298	break;
	299	case 12000000:
	300	pll = PLL2 \| PLL1;
	301	break;
	302	case 24000000:
	303	pll = PLL2 \| PLL1 \| PLL0;
	304	break;
	305	case 13500000:
	306	pll = PLL3 \| PLL2;
	307	break;
	308	case 27000000:
	309	pll = PLL3 \| PLL2 \| PLL0;
	310	break;
	311	default:
	312	return -EINVAL;
	313	}
	314	snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
a3a83d9a	315
a3a83d9a KM	316	return 0;
	317	}
	318
0643ce8f KM	319	static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
	320	{
	321	struct snd_soc_codec *codec = dai->codec;
	322	u8 data;
	323	u8 bcko;
	324
	325	data = MCKO \| PMPLL; /* use MCKO */
	326	bcko = 0;
	327
	328	/* set master/slave audio interface */
	329	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	330	case SND_SOC_DAIFMT_CBM_CFM:
	331	data \|= MS;
	332	bcko = BCKO_64;
	333	break;
	334	case SND_SOC_DAIFMT_CBS_CFS:
	335	break;
	336	default:
	337	return -EINVAL;
	338	}
bd7fdbca	339	snd_soc_update_bits(codec, PW_MGMT2, MS \| MCKO \| PMPLL, data);
0643ce8f KM	340	snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);
0643ce8f KM	341
cb9c130a KM	342	/* format type */
	343	data = 0;
	344	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	345	case SND_SOC_DAIFMT_LEFT_J:
	346	data = LEFT_J;
	347	break;
	348	case SND_SOC_DAIFMT_I2S:
	349	data = I2S;
	350	break;
	351	/* FIXME
	352	* Please add RIGHT_J / DSP support here
	353	*/
	354	default:
	355	return -EINVAL;
cb9c130a KM	356	}
	357	snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);
	358
0643ce8f KM	359	return 0;
	360	}
	361
1ad747ca KM	362	static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
	363	struct snd_pcm_hw_params *params,
	364	struct snd_soc_dai *dai)
	365	{
	366	struct snd_soc_codec *codec = dai->codec;
	367	u8 rate;
	368
	369	switch (params_rate(params)) {
	370	case 7350:
	371	rate = FS2;
	372	break;
	373	case 8000:
	374	rate = 0;
	375	break;
	376	case 11025:
	377	rate = FS2 \| FS0;
	378	break;
	379	case 12000:
	380	rate = FS0;
	381	break;
	382	case 14700:
	383	rate = FS2 \| FS1;
	384	break;
	385	case 16000:
	386	rate = FS1;
	387	break;
	388	case 22050:
	389	rate = FS2 \| FS1 \| FS0;
	390	break;
	391	case 24000:
	392	rate = FS1 \| FS0;
	393	break;
	394	case 29400:
	395	rate = FS3 \| FS2 \| FS1;
	396	break;
	397	case 32000:
	398	rate = FS3 \| FS1;
	399	break;
	400	case 44100:
	401	rate = FS3 \| FS2 \| FS1 \| FS0;
	402	break;
	403	case 48000:
	404	rate = FS3 \| FS1 \| FS0;
	405	break;
	406	default:
	407	return -EINVAL;
1ad747ca KM	408	}
1ad747ca KM	409	snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);
a3a83d9a	410
a3a83d9a KM	411	return 0;
	412	}
	413
ed2dd7da KM	414	static int ak4642_set_bias_level(struct snd_soc_codec *codec,
	415	enum snd_soc_bias_level level)
	416	{
	417	switch (level) {
	418	case SND_SOC_BIAS_OFF:
	419	snd_soc_write(codec, PW_MGMT1, 0x00);
	420	break;
	421	default:
	422	snd_soc_update_bits(codec, PW_MGMT1, PMVCM, PMVCM);
	423	break;
	424	}
	425	codec->dapm.bias_level = level;
	426
	427	return 0;
	428	}
	429
85e7652d	430	static const struct snd_soc_dai_ops ak4642_dai_ops = {
a3a83d9a KM	431	.startup = ak4642_dai_startup,
	432	.shutdown = ak4642_dai_shutdown,
	433	.set_sysclk = ak4642_dai_set_sysclk,
0643ce8f	434	.set_fmt = ak4642_dai_set_fmt,
1ad747ca	435	.hw_params = ak4642_dai_hw_params,
a3a83d9a KM	436	};
a3a83d9a KM	437
f0fba2ad LG	438	static struct snd_soc_dai_driver ak4642_dai = {
f0fba2ad LG	439	.name = "ak4642-hifi",
a3a83d9a KM	440	.playback = {
	441	.stream_name = "Playback",
	442	.channels_min = 1,
	443	.channels_max = 2,
	444	.rates = SNDRV_PCM_RATE_8000_48000,
	445	.formats = SNDRV_PCM_FMTBIT_S16_LE },
	446	.capture = {
	447	.stream_name = "Capture",
	448	.channels_min = 1,
	449	.channels_max = 2,
	450	.rates = SNDRV_PCM_RATE_8000_48000,
	451	.formats = SNDRV_PCM_FMTBIT_S16_LE },
	452	.ops = &ak4642_dai_ops,
1ad747ca	453	.symmetric_rates = 1,
a3a83d9a	454	};
a3a83d9a	455
f0fba2ad	456	static int ak4642_resume(struct snd_soc_codec *codec)
a3a83d9a	457	{
4574cd94 MB	458	struct regmap *regmap = dev_get_regmap(codec->dev, NULL);
	459
	460	regcache_mark_dirty(regmap);
	461	regcache_sync(regmap);
a3a83d9a KM	462	return 0;
	463	}
	464
f0fba2ad LG	465
f0fba2ad LG	466	static int ak4642_probe(struct snd_soc_codec *codec)
a3a83d9a	467	{
b91470bb	468	int ret;
a3a83d9a	469
4574cd94	470	ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
b91470bb AL	471	if (ret < 0) {
	472	dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
	473	return ret;
	474	}
a3a83d9a	475
ed2dd7da KM	476	ak4642_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	477
	478	return 0;
	479	}
	480
	481	static int ak4642_remove(struct snd_soc_codec *codec)
	482	{
	483	ak4642_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad	484	return 0;
a3a83d9a KM	485	}
a3a83d9a KM	486
f0fba2ad	487	static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
0ce75aa4	488	.probe = ak4642_probe,
ed2dd7da	489	.remove = ak4642_remove,
0ce75aa4	490	.resume = ak4642_resume,
ed2dd7da	491	.set_bias_level = ak4642_set_bias_level,
a8ca52b7 MB	492	.controls = ak4642_snd_controls,
a8ca52b7 MB	493	.num_controls = ARRAY_SIZE(ak4642_snd_controls),
a9317e8b KM	494	.dapm_widgets = ak4642_dapm_widgets,
	495	.num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets),
	496	.dapm_routes = ak4642_intercon,
	497	.num_dapm_routes = ARRAY_SIZE(ak4642_intercon),
	498	};
	499
4574cd94 MB	500	static const struct regmap_config ak4642_regmap = {
	501	.reg_bits = 8,
	502	.val_bits = 8,
	503	.max_register = ARRAY_SIZE(ak4642_reg) + 1,
	504	.reg_defaults = ak4642_reg,
	505	.num_reg_defaults = ARRAY_SIZE(ak4642_reg),
	506	};
	507
	508	static const struct regmap_config ak4648_regmap = {
	509	.reg_bits = 8,
	510	.val_bits = 8,
	511	.max_register = ARRAY_SIZE(ak4648_reg) + 1,
	512	.reg_defaults = ak4648_reg,
	513	.num_reg_defaults = ARRAY_SIZE(ak4648_reg),
f0fba2ad LG	514	};
f0fba2ad LG	515
bbf1453e	516	static struct of_device_id ak4642_of_match[];
7a79e94e BP	517	static int ak4642_i2c_probe(struct i2c_client *i2c,
7a79e94e BP	518	const struct i2c_device_id *id)
a3a83d9a	519	{
bbf1453e	520	struct device_node *np = i2c->dev.of_node;
4574cd94 MB	521	const struct regmap_config *regmap_config = NULL;
4574cd94 MB	522	struct regmap *regmap;
bbf1453e	523
bbf1453e KM	524	if (np) {
	525	const struct of_device_id *of_id;
	526
	527	of_id = of_match_device(ak4642_of_match, &i2c->dev);
	528	if (of_id)
4574cd94	529	regmap_config = of_id->data;
bbf1453e	530	} else {
4574cd94	531	regmap_config = (const struct regmap_config *)id->driver_data;
bbf1453e KM	532	}
bbf1453e KM	533
4574cd94 MB	534	if (!regmap_config) {
4574cd94 MB	535	dev_err(&i2c->dev, "Unknown device type\n");
bbf1453e KM	536	return -EINVAL;
	537	}
	538
4574cd94 MB	539	regmap = devm_regmap_init_i2c(i2c, regmap_config);
	540	if (IS_ERR(regmap))
	541	return PTR_ERR(regmap);
	542
2f391251	543	return snd_soc_register_codec(&i2c->dev,
4574cd94	544	&soc_codec_dev_ak4642, &ak4642_dai, 1);
a3a83d9a KM	545	}
a3a83d9a KM	546
7a79e94e	547	static int ak4642_i2c_remove(struct i2c_client *client)
a3a83d9a	548	{
f0fba2ad	549	snd_soc_unregister_codec(&client->dev);
a3a83d9a KM	550	return 0;
	551	}
	552
c890caee	553	static struct of_device_id ak4642_of_match[] = {
4574cd94 MB	554	{ .compatible = "asahi-kasei,ak4642", .data = &ak4642_regmap},
	555	{ .compatible = "asahi-kasei,ak4643", .data = &ak4642_regmap},
	556	{ .compatible = "asahi-kasei,ak4648", .data = &ak4648_regmap},
bbf1453e KM	557	{},
	558	};
	559	MODULE_DEVICE_TABLE(of, ak4642_of_match);
	560
a3a83d9a	561	static const struct i2c_device_id ak4642_i2c_id[] = {
4574cd94 MB	562	{ "ak4642", (kernel_ulong_t)&ak4642_regmap },
	563	{ "ak4643", (kernel_ulong_t)&ak4642_regmap },
	564	{ "ak4648", (kernel_ulong_t)&ak4648_regmap },
a3a83d9a KM	565	{ }
	566	};
	567	MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
	568
	569	static struct i2c_driver ak4642_i2c_driver = {
	570	.driver = {
f0fba2ad	571	.name = "ak4642-codec",
a3a83d9a	572	.owner = THIS_MODULE,
bbf1453e	573	.of_match_table = ak4642_of_match,
a3a83d9a	574	},
0ce75aa4	575	.probe = ak4642_i2c_probe,
7a79e94e	576	.remove = ak4642_i2c_remove,
0ce75aa4	577	.id_table = ak4642_i2c_id,
a3a83d9a	578	};
a3a83d9a	579
2f54d2a1	580	module_i2c_driver(ak4642_i2c_driver);
a3a83d9a KM	581
	582	MODULE_DESCRIPTION("Soc AK4642 driver");
	583	MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
	584	MODULE_LICENSE("GPL");