]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - sound/soc/codecs/cs35l35.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: cs35l35: Improve power down time
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / cs35l35.c
CommitLineData
6387f866
BA		 1/*
2 * cs35l35.c -- CS35L35 ALSA SoC audio driver
3 *
4 * Copyright 2017 Cirrus Logic, Inc.
5 *
6 * Author: Brian Austin <brian.austin@cirrus.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/version.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/i2c.h>
21#include <linux/slab.h>
22#include <linux/platform_device.h>
23#include <linux/regulator/consumer.h>
24#include <linux/gpio/consumer.h>
25#include <linux/of_device.h>
26#include <linux/of_gpio.h>
27#include <linux/regmap.h>
28#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/soc.h>
32#include <sound/soc-dapm.h>
33#include <linux/gpio.h>
34#include <sound/initval.h>
35#include <sound/tlv.h>
36#include <sound/cs35l35.h>
37#include <linux/of_irq.h>
38#include <linux/completion.h>
39
40#include "cs35l35.h"
41
42/*
43 * Some fields take zero as a valid value so use a high bit flag that won't
44 * get written to the device to mark those.
45 */
46#define CS35L35_VALID_PDATA 0x80000000
47
48static const struct reg_default cs35l35_reg[] = {
49 {CS35L35_PWRCTL1, 0x01},
50 {CS35L35_PWRCTL2, 0x11},
51 {CS35L35_PWRCTL3, 0x00},
52 {CS35L35_CLK_CTL1, 0x04},
53 {CS35L35_CLK_CTL2, 0x10},
54 {CS35L35_CLK_CTL3, 0xCF},
55 {CS35L35_SP_FMT_CTL1, 0x20},
56 {CS35L35_SP_FMT_CTL2, 0x00},
57 {CS35L35_SP_FMT_CTL3, 0x02},
58 {CS35L35_MAG_COMP_CTL, 0x00},
59 {CS35L35_AMP_INP_DRV_CTL, 0x01},
60 {CS35L35_AMP_DIG_VOL_CTL, 0x12},
61 {CS35L35_AMP_DIG_VOL, 0x00},
62 {CS35L35_ADV_DIG_VOL, 0x00},
63 {CS35L35_PROTECT_CTL, 0x06},
64 {CS35L35_AMP_GAIN_AUD_CTL, 0x13},
65 {CS35L35_AMP_GAIN_PDM_CTL, 0x00},
66 {CS35L35_AMP_GAIN_ADV_CTL, 0x00},
67 {CS35L35_GPI_CTL, 0x00},
68 {CS35L35_BST_CVTR_V_CTL, 0x00},
69 {CS35L35_BST_PEAK_I, 0x07},
70 {CS35L35_BST_RAMP_CTL, 0x85},
71 {CS35L35_BST_CONV_COEF_1, 0x24},
72 {CS35L35_BST_CONV_COEF_2, 0x24},
73 {CS35L35_BST_CONV_SLOPE_COMP, 0x47},
74 {CS35L35_BST_CONV_SW_FREQ, 0x04},
75 {CS35L35_CLASS_H_CTL, 0x0B},
76 {CS35L35_CLASS_H_HEADRM_CTL, 0x0B},
77 {CS35L35_CLASS_H_RELEASE_RATE, 0x08},
78 {CS35L35_CLASS_H_FET_DRIVE_CTL, 0x41},
79 {CS35L35_CLASS_H_VP_CTL, 0xC5},
80 {CS35L35_VPBR_CTL, 0x0A},
81 {CS35L35_VPBR_VOL_CTL, 0x09},
82 {CS35L35_VPBR_TIMING_CTL, 0x6A},
83 {CS35L35_VPBR_MODE_VOL_CTL, 0x40},
84 {CS35L35_SPKR_MON_CTL, 0xC0},
85 {CS35L35_IMON_SCALE_CTL, 0x30},
86 {CS35L35_AUDIN_RXLOC_CTL, 0x00},
87 {CS35L35_ADVIN_RXLOC_CTL, 0x80},
88 {CS35L35_VMON_TXLOC_CTL, 0x00},
89 {CS35L35_IMON_TXLOC_CTL, 0x80},
90 {CS35L35_VPMON_TXLOC_CTL, 0x04},
91 {CS35L35_VBSTMON_TXLOC_CTL, 0x84},
92 {CS35L35_VPBR_STATUS_TXLOC_CTL, 0x04},
93 {CS35L35_ZERO_FILL_LOC_CTL, 0x00},
94 {CS35L35_AUDIN_DEPTH_CTL, 0x0F},
95 {CS35L35_SPKMON_DEPTH_CTL, 0x0F},
96 {CS35L35_SUPMON_DEPTH_CTL, 0x0F},
97 {CS35L35_ZEROFILL_DEPTH_CTL, 0x00},
98 {CS35L35_MULT_DEV_SYNCH1, 0x02},
99 {CS35L35_MULT_DEV_SYNCH2, 0x80},
100 {CS35L35_PROT_RELEASE_CTL, 0x00},
101 {CS35L35_DIAG_MODE_REG_LOCK, 0x00},
102 {CS35L35_DIAG_MODE_CTL_1, 0x40},
103 {CS35L35_DIAG_MODE_CTL_2, 0x00},
104 {CS35L35_INT_MASK_1, 0xFF},
105 {CS35L35_INT_MASK_2, 0xFF},
106 {CS35L35_INT_MASK_3, 0xFF},
107 {CS35L35_INT_MASK_4, 0xFF},
108
109};
110
111static bool cs35l35_volatile_register(struct device *dev, unsigned int reg)
112{
113 switch (reg) {
114 case CS35L35_INT_STATUS_1:
115 case CS35L35_INT_STATUS_2:
116 case CS35L35_INT_STATUS_3:
117 case CS35L35_INT_STATUS_4:
118 case CS35L35_PLL_STATUS:
119 case CS35L35_OTP_TRIM_STATUS:
120 return true;
121 default:
122 return false;
123 }
124}
125
126static bool cs35l35_readable_register(struct device *dev, unsigned int reg)
127{
128 switch (reg) {
129 case CS35L35_DEVID_AB ... CS35L35_PWRCTL3:
130 case CS35L35_CLK_CTL1 ... CS35L35_SP_FMT_CTL3:
131 case CS35L35_MAG_COMP_CTL ... CS35L35_AMP_GAIN_AUD_CTL:
132 case CS35L35_AMP_GAIN_PDM_CTL ... CS35L35_BST_PEAK_I:
133 case CS35L35_BST_RAMP_CTL ... CS35L35_BST_CONV_SW_FREQ:
134 case CS35L35_CLASS_H_CTL ... CS35L35_CLASS_H_VP_CTL:
135 case CS35L35_CLASS_H_STATUS:
136 case CS35L35_VPBR_CTL ... CS35L35_VPBR_MODE_VOL_CTL:
137 case CS35L35_VPBR_ATTEN_STATUS:
138 case CS35L35_SPKR_MON_CTL:
139 case CS35L35_IMON_SCALE_CTL ... CS35L35_ZEROFILL_DEPTH_CTL:
140 case CS35L35_MULT_DEV_SYNCH1 ... CS35L35_PROT_RELEASE_CTL:
141 case CS35L35_DIAG_MODE_REG_LOCK ... CS35L35_DIAG_MODE_CTL_2:
142 case CS35L35_INT_MASK_1 ... CS35L35_PLL_STATUS:
143 case CS35L35_OTP_TRIM_STATUS:
144 return true;
145 default:
146 return false;
147 }
148}
149
150static bool cs35l35_precious_register(struct device *dev, unsigned int reg)
151{
152 switch (reg) {
153 case CS35L35_INT_STATUS_1:
154 case CS35L35_INT_STATUS_2:
155 case CS35L35_INT_STATUS_3:
156 case CS35L35_INT_STATUS_4:
157 case CS35L35_PLL_STATUS:
158 case CS35L35_OTP_TRIM_STATUS:
159 return true;
160 default:
161 return false;
162 }
163}
164
165static int cs35l35_sdin_event(struct snd_soc_dapm_widget *w,
166 struct snd_kcontrol *kcontrol, int event)
167{
168 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
169 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
170 int ret = 0;
171
172 switch (event) {
173 case SND_SOC_DAPM_PRE_PMU:
174 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
175 CS35L35_MCLK_DIS_MASK,
176 0 << CS35L35_MCLK_DIS_SHIFT);
177 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
178 CS35L35_DISCHG_FILT_MASK,
179 0 << CS35L35_DISCHG_FILT_SHIFT);
180 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
181 CS35L35_PDN_ALL_MASK, 0);
182 break;
183 case SND_SOC_DAPM_POST_PMD:
184 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
185 CS35L35_DISCHG_FILT_MASK,
186 1 << CS35L35_DISCHG_FILT_SHIFT);
187 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
188 CS35L35_PDN_ALL_MASK, 1);
189
2c84afb5
CK		 190 /* Already muted, so disable volume ramp for faster shutdown */
191 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_DIG_VOL_CTL,
192 CS35L35_AMP_DIGSFT_MASK, 0);
193
6387f866
BA		 194 reinit_completion(&cs35l35->pdn_done);
195
196 ret = wait_for_completion_timeout(&cs35l35->pdn_done,
197 msecs_to_jiffies(100));
198 if (ret == 0) {
199 dev_err(codec->dev, "TIMEOUT PDN_DONE did not complete in 100ms\n");
200 ret = -ETIMEDOUT;
201 }
202
203 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
204 CS35L35_MCLK_DIS_MASK,
205 1 << CS35L35_MCLK_DIS_SHIFT);
2c84afb5
CK		 206
207 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_DIG_VOL_CTL,
208 CS35L35_AMP_DIGSFT_MASK,
209 1 << CS35L35_AMP_DIGSFT_SHIFT);
6387f866
BA		 210 break;
211 default:
212 dev_err(codec->dev, "Invalid event = 0x%x\n", event);
213 ret = -EINVAL;
214 }
215 return ret;
216}
217
218static int cs35l35_main_amp_event(struct snd_soc_dapm_widget *w,
219 struct snd_kcontrol *kcontrol, int event)
220{
221 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
222 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
223 unsigned int reg[4];
224 int i;
225
226 switch (event) {
227 case SND_SOC_DAPM_PRE_PMU:
228 if (cs35l35->pdata.bst_pdn_fet_on)
229 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
230 CS35L35_PDN_BST_MASK,
231 0 << CS35L35_PDN_BST_FETON_SHIFT);
232 else
233 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
234 CS35L35_PDN_BST_MASK,
235 0 << CS35L35_PDN_BST_FETOFF_SHIFT);
236 break;
237 case SND_SOC_DAPM_POST_PMU:
238 usleep_range(5000, 5100);
239 /* If in PDM mode we must use VP for Voltage control */
240 if (cs35l35->pdm_mode)
241 regmap_update_bits(cs35l35->regmap,
242 CS35L35_BST_CVTR_V_CTL,
243 CS35L35_BST_CTL_MASK,
244 0 << CS35L35_BST_CTL_SHIFT);
245
246 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
247 CS35L35_AMP_MUTE_MASK, 0);
248
249 for (i = 0; i < 2; i++)
250 regmap_bulk_read(cs35l35->regmap, CS35L35_INT_STATUS_1,
251 &reg, ARRAY_SIZE(reg));
252
253 break;
254 case SND_SOC_DAPM_PRE_PMD:
255 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
256 CS35L35_AMP_MUTE_MASK,
257 1 << CS35L35_AMP_MUTE_SHIFT);
258 if (cs35l35->pdata.bst_pdn_fet_on)
259 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
260 CS35L35_PDN_BST_MASK,
261 1 << CS35L35_PDN_BST_FETON_SHIFT);
262 else
263 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
264 CS35L35_PDN_BST_MASK,
265 1 << CS35L35_PDN_BST_FETOFF_SHIFT);
266 break;
267 case SND_SOC_DAPM_POST_PMD:
268 usleep_range(5000, 5100);
269 /*
270 * If PDM mode we should switch back to pdata value
271 * for Voltage control when we go down
272 */
273 if (cs35l35->pdm_mode)
274 regmap_update_bits(cs35l35->regmap,
275 CS35L35_BST_CVTR_V_CTL,
276 CS35L35_BST_CTL_MASK,
277 cs35l35->pdata.bst_vctl
278 << CS35L35_BST_CTL_SHIFT);
279
280 break;
281 default:
282 dev_err(codec->dev, "Invalid event = 0x%x\n", event);
283 }
284 return 0;
285}
286
287static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1);
288static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 50, 0);
289
290static const struct snd_kcontrol_new cs35l35_aud_controls[] = {
291 SOC_SINGLE_SX_TLV("Digital Audio Volume", CS35L35_AMP_DIG_VOL,
292 0, 0x34, 0xE4, dig_vol_tlv),
293 SOC_SINGLE_TLV("Analog Audio Volume", CS35L35_AMP_GAIN_AUD_CTL, 0, 19, 0,
294 amp_gain_tlv),
295 SOC_SINGLE_TLV("PDM Volume", CS35L35_AMP_GAIN_PDM_CTL, 0, 19, 0,
296 amp_gain_tlv),
297};
298
299static const struct snd_kcontrol_new cs35l35_adv_controls[] = {
300 SOC_SINGLE_SX_TLV("Digital Advisory Volume", CS35L35_ADV_DIG_VOL,
301 0, 0x34, 0xE4, dig_vol_tlv),
302 SOC_SINGLE_TLV("Analog Advisory Volume", CS35L35_AMP_GAIN_ADV_CTL, 0, 19, 0,
303 amp_gain_tlv),
304};
305
306static const struct snd_soc_dapm_widget cs35l35_dapm_widgets[] = {
307 SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L35_PWRCTL3, 1, 1,
308 cs35l35_sdin_event, SND_SOC_DAPM_PRE_PMU |
309 SND_SOC_DAPM_POST_PMD),
310 SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L35_PWRCTL3, 2, 1),
311
312 SND_SOC_DAPM_OUTPUT("SPK"),
313
314 SND_SOC_DAPM_INPUT("VP"),
315 SND_SOC_DAPM_INPUT("VBST"),
316 SND_SOC_DAPM_INPUT("ISENSE"),
317 SND_SOC_DAPM_INPUT("VSENSE"),
318
319 SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L35_PWRCTL2, 7, 1),
320 SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L35_PWRCTL2, 6, 1),
321 SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L35_PWRCTL3, 3, 1),
322 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L35_PWRCTL3, 4, 1),
323 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L35_PWRCTL2, 5, 1),
324
325 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L35_PWRCTL2, 0, 1, NULL, 0,
326 cs35l35_main_amp_event, SND_SOC_DAPM_PRE_PMU |
327 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU |
328 SND_SOC_DAPM_PRE_PMD),
329};
330
331static const struct snd_soc_dapm_route cs35l35_audio_map[] = {
332 {"VPMON ADC", NULL, "VP"},
333 {"VBSTMON ADC", NULL, "VBST"},
334 {"IMON ADC", NULL, "ISENSE"},
335 {"VMON ADC", NULL, "VSENSE"},
336 {"SDOUT", NULL, "IMON ADC"},
337 {"SDOUT", NULL, "VMON ADC"},
338 {"SDOUT", NULL, "VBSTMON ADC"},
339 {"SDOUT", NULL, "VPMON ADC"},
340 {"AMP Capture", NULL, "SDOUT"},
341
342 {"SDIN", NULL, "AMP Playback"},
343 {"CLASS H", NULL, "SDIN"},
344 {"Main AMP", NULL, "CLASS H"},
345 {"SPK", NULL, "Main AMP"},
346};
347
348static int cs35l35_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
349{
350 struct snd_soc_codec *codec = codec_dai->codec;
351 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
352
353 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
354 case SND_SOC_DAIFMT_CBM_CFM:
355 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
356 CS35L35_MS_MASK, 1 << CS35L35_MS_SHIFT);
357 cs35l35->slave_mode = false;
358 break;
359 case SND_SOC_DAIFMT_CBS_CFS:
360 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
361 CS35L35_MS_MASK, 0 << CS35L35_MS_SHIFT);
362 cs35l35->slave_mode = true;
363 break;
364 default:
365 return -EINVAL;
366 }
367
368 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
369 case SND_SOC_DAIFMT_I2S:
370 cs35l35->i2s_mode = true;
371 cs35l35->pdm_mode = false;
372 break;
373 case SND_SOC_DAIFMT_PDM:
374 cs35l35->pdm_mode = true;
375 cs35l35->i2s_mode = false;
376 break;
377 default:
378 return -EINVAL;
379 }
380
381 return 0;
382}
383
384struct cs35l35_sysclk_config {
385 int sysclk;
386 int srate;
387 u8 clk_cfg;
388};
389
390static struct cs35l35_sysclk_config cs35l35_clk_ctl[] = {
391
392 /* SYSCLK, Sample Rate, Serial Port Cfg */
393 {5644800, 44100, 0x00},
394 {5644800, 88200, 0x40},
395 {6144000, 48000, 0x10},
396 {6144000, 96000, 0x50},
397 {11289600, 44100, 0x01},
398 {11289600, 88200, 0x41},
399 {11289600, 176400, 0x81},
400 {12000000, 44100, 0x03},
401 {12000000, 48000, 0x13},
402 {12000000, 88200, 0x43},
403 {12000000, 96000, 0x53},
404 {12000000, 176400, 0x83},
405 {12000000, 192000, 0x93},
406 {12288000, 48000, 0x11},
407 {12288000, 96000, 0x51},
408 {12288000, 192000, 0x91},
409 {13000000, 44100, 0x07},
410 {13000000, 48000, 0x17},
411 {13000000, 88200, 0x47},
412 {13000000, 96000, 0x57},
413 {13000000, 176400, 0x87},
414 {13000000, 192000, 0x97},
415 {22579200, 44100, 0x02},
416 {22579200, 88200, 0x42},
417 {22579200, 176400, 0x82},
418 {24000000, 44100, 0x0B},
419 {24000000, 48000, 0x1B},
420 {24000000, 88200, 0x4B},
421 {24000000, 96000, 0x5B},
422 {24000000, 176400, 0x8B},
423 {24000000, 192000, 0x9B},
424 {24576000, 48000, 0x12},
425 {24576000, 96000, 0x52},
426 {24576000, 192000, 0x92},
427 {26000000, 44100, 0x0F},
428 {26000000, 48000, 0x1F},
429 {26000000, 88200, 0x4F},
430 {26000000, 96000, 0x5F},
431 {26000000, 176400, 0x8F},
432 {26000000, 192000, 0x9F},
433};
434
435static int cs35l35_get_clk_config(int sysclk, int srate)
436{
437 int i;
438
439 for (i = 0; i < ARRAY_SIZE(cs35l35_clk_ctl); i++) {
440 if (cs35l35_clk_ctl[i].sysclk == sysclk &&
441 cs35l35_clk_ctl[i].srate == srate)
442 return cs35l35_clk_ctl[i].clk_cfg;
443 }
444 return -EINVAL;
445}
446
447static int cs35l35_hw_params(struct snd_pcm_substream *substream,
448 struct snd_pcm_hw_params *params,
449 struct snd_soc_dai *dai)
450{
451 struct snd_soc_codec *codec = dai->codec;
452 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
453 struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
454 int srate = params_rate(params);
455 int ret = 0;
456 u8 sp_sclks;
457 int audin_format;
458 int errata_chk;
459
460 int clk_ctl = cs35l35_get_clk_config(cs35l35->sysclk, srate);
461
462 if (clk_ctl < 0) {
463 dev_err(codec->dev, "Invalid CLK:Rate %d:%d\n",
464 cs35l35->sysclk, srate);
465 return -EINVAL;
466 }
467
468 ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL2,
469 CS35L35_CLK_CTL2_MASK, clk_ctl);
470 if (ret != 0) {
471 dev_err(codec->dev, "Failed to set port config %d\n", ret);
472 return ret;
473 }
474
475 /*
476 * Rev A0 Errata
477 * When configured for the weak-drive detection path (CH_WKFET_DIS = 0)
478 * the Class H algorithm does not enable weak-drive operation for
479 * nonzero values of CH_WKFET_DELAY if SP_RATE = 01 or 10
480 */
481 errata_chk = clk_ctl & CS35L35_SP_RATE_MASK;
482
483 if (classh->classh_wk_fet_disable == 0x00 &&
484 (errata_chk == 0x01 || errata_chk == 0x03)) {
485 ret = regmap_update_bits(cs35l35->regmap,
486 CS35L35_CLASS_H_FET_DRIVE_CTL,
487 CS35L35_CH_WKFET_DEL_MASK,
488 0 << CS35L35_CH_WKFET_DEL_SHIFT);
489 if (ret != 0) {
490 dev_err(codec->dev, "Failed to set fet config %d\n",
491 ret);
492 return ret;
493 }
494 }
495
496 /*
497 * You can pull more Monitor data from the SDOUT pin than going to SDIN
498 * Just make sure your SCLK is fast enough to fill the frame
499 */
500 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
501 switch (params_width(params)) {
502 case 8:
503 audin_format = CS35L35_SDIN_DEPTH_8;
504 break;
505 case 16:
506 audin_format = CS35L35_SDIN_DEPTH_16;
507 break;
508 case 24:
509 audin_format = CS35L35_SDIN_DEPTH_24;
510 break;
511 default:
512 dev_err(codec->dev, "Unsupported Width %d\n",
513 params_width(params));
514 return -EINVAL;
515 }
516 regmap_update_bits(cs35l35->regmap,
517 CS35L35_AUDIN_DEPTH_CTL,
518 CS35L35_AUDIN_DEPTH_MASK,
519 audin_format <<
520 CS35L35_AUDIN_DEPTH_SHIFT);
521 if (cs35l35->pdata.stereo) {
522 regmap_update_bits(cs35l35->regmap,
523 CS35L35_AUDIN_DEPTH_CTL,
524 CS35L35_ADVIN_DEPTH_MASK,
525 audin_format <<
526 CS35L35_ADVIN_DEPTH_SHIFT);
527 }
528 }
529
530 if (cs35l35->i2s_mode) {
531 /* We have to take the SCLK to derive num sclks
532 * to configure the CLOCK_CTL3 register correctly
533 */
534 if ((cs35l35->sclk / srate) % 4) {
535 dev_err(codec->dev, "Unsupported sclk/fs ratio %d:%d\n",
536 cs35l35->sclk, srate);
537 return -EINVAL;
538 }
539 sp_sclks = ((cs35l35->sclk / srate) / 4) - 1;
540
541 /* Only certain ratios are supported in I2S Slave Mode */
542 if (cs35l35->slave_mode) {
543 switch (sp_sclks) {
544 case CS35L35_SP_SCLKS_32FS:
545 case CS35L35_SP_SCLKS_48FS:
546 case CS35L35_SP_SCLKS_64FS:
547 break;
548 default:
549 dev_err(codec->dev, "ratio not supported\n");
550 return -EINVAL;
f3a612a6 551 }
6387f866
BA		 552 } else {
553 /* Only certain ratios supported in I2S MASTER Mode */
554 switch (sp_sclks) {
555 case CS35L35_SP_SCLKS_32FS:
556 case CS35L35_SP_SCLKS_64FS:
557 break;
558 default:
559 dev_err(codec->dev, "ratio not supported\n");
560 return -EINVAL;
f3a612a6 561 }
6387f866
BA		 562 }
563 ret = regmap_update_bits(cs35l35->regmap,
564 CS35L35_CLK_CTL3,
565 CS35L35_SP_SCLKS_MASK, sp_sclks <<
566 CS35L35_SP_SCLKS_SHIFT);
567 if (ret != 0) {
568 dev_err(codec->dev, "Failed to set fsclk %d\n", ret);
569 return ret;
570 }
571 }
572
573 return ret;
574}
575
576static const unsigned int cs35l35_src_rates[] = {
577 44100, 48000, 88200, 96000, 176400, 192000
578};
579
580static const struct snd_pcm_hw_constraint_list cs35l35_constraints = {
581 .count = ARRAY_SIZE(cs35l35_src_rates),
582 .list = cs35l35_src_rates,
583};
584
585static int cs35l35_pcm_startup(struct snd_pcm_substream *substream,
586 struct snd_soc_dai *dai)
587{
588 struct snd_soc_codec *codec = dai->codec;
589 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
590
591 if (!substream->runtime)
592 return 0;
593
594 snd_pcm_hw_constraint_list(substream->runtime, 0,
595 SNDRV_PCM_HW_PARAM_RATE, &cs35l35_constraints);
596
597 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
598 CS35L35_PDM_MODE_MASK,
599 0 << CS35L35_PDM_MODE_SHIFT);
600
601 return 0;
602}
603
604static const unsigned int cs35l35_pdm_rates[] = {
605 44100, 48000, 88200, 96000
606};
607
608static const struct snd_pcm_hw_constraint_list cs35l35_pdm_constraints = {
609 .count = ARRAY_SIZE(cs35l35_pdm_rates),
610 .list = cs35l35_pdm_rates,
611};
612
613static int cs35l35_pdm_startup(struct snd_pcm_substream *substream,
614 struct snd_soc_dai *dai)
615{
616 struct snd_soc_codec *codec = dai->codec;
617 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
618
619 if (!substream->runtime)
620 return 0;
621
622 snd_pcm_hw_constraint_list(substream->runtime, 0,
623 SNDRV_PCM_HW_PARAM_RATE,
624 &cs35l35_pdm_constraints);
625
626 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
627 CS35L35_PDM_MODE_MASK,
628 1 << CS35L35_PDM_MODE_SHIFT);
629
630 return 0;
631}
632
633static int cs35l35_dai_set_sysclk(struct snd_soc_dai *dai,
634 int clk_id, unsigned int freq, int dir)
635{
636 struct snd_soc_codec *codec = dai->codec;
637 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
638
639 /* Need the SCLK Frequency regardless of sysclk source for I2S */
640 cs35l35->sclk = freq;
641
642 return 0;
643}
644
645static const struct snd_soc_dai_ops cs35l35_ops = {
646 .startup = cs35l35_pcm_startup,
647 .set_fmt = cs35l35_set_dai_fmt,
648 .hw_params = cs35l35_hw_params,
649 .set_sysclk = cs35l35_dai_set_sysclk,
650};
651
652static const struct snd_soc_dai_ops cs35l35_pdm_ops = {
653 .startup = cs35l35_pdm_startup,
654 .set_fmt = cs35l35_set_dai_fmt,
655 .hw_params = cs35l35_hw_params,
656};
657
658static struct snd_soc_dai_driver cs35l35_dai[] = {
659 {
660 .name = "cs35l35-pcm",
661 .id = 0,
662 .playback = {
663 .stream_name = "AMP Playback",
664 .channels_min = 1,
665 .channels_max = 8,
666 .rates = SNDRV_PCM_RATE_KNOT,
667 .formats = CS35L35_FORMATS,
668 },
669 .capture = {
670 .stream_name = "AMP Capture",
671 .channels_min = 1,
672 .channels_max = 8,
673 .rates = SNDRV_PCM_RATE_KNOT,
674 .formats = CS35L35_FORMATS,
675 },
676 .ops = &cs35l35_ops,
677 .symmetric_rates = 1,
678 },
679 {
680 .name = "cs35l35-pdm",
681 .id = 1,
682 .playback = {
683 .stream_name = "PDM Playback",
684 .channels_min = 1,
685 .channels_max = 2,
686 .rates = SNDRV_PCM_RATE_KNOT,
687 .formats = CS35L35_FORMATS,
688 },
689 .ops = &cs35l35_pdm_ops,
690 },
691};
692
693static int cs35l35_codec_set_sysclk(struct snd_soc_codec *codec,
694 int clk_id, int source, unsigned int freq,
695 int dir)
696{
697 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
698 int clksrc;
699 int ret = 0;
700
701 switch (clk_id) {
702 case 0:
703 clksrc = CS35L35_CLK_SOURCE_MCLK;
704 break;
705 case 1:
706 clksrc = CS35L35_CLK_SOURCE_SCLK;
707 break;
708 case 2:
709 clksrc = CS35L35_CLK_SOURCE_PDM;
710 break;
711 default:
712 dev_err(codec->dev, "Invalid CLK Source\n");
713 return -EINVAL;
f3a612a6 714 }
6387f866
BA		 715
716 switch (freq) {
717 case 5644800:
718 case 6144000:
719 case 11289600:
720 case 12000000:
721 case 12288000:
722 case 13000000:
723 case 22579200:
724 case 24000000:
725 case 24576000:
726 case 26000000:
727 cs35l35->sysclk = freq;
728 break;
729 default:
730 dev_err(codec->dev, "Invalid CLK Frequency Input : %d\n", freq);
731 return -EINVAL;
732 }
733
734 ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
735 CS35L35_CLK_SOURCE_MASK,
736 clksrc << CS35L35_CLK_SOURCE_SHIFT);
737 if (ret != 0) {
738 dev_err(codec->dev, "Failed to set sysclk %d\n", ret);
739 return ret;
740 }
741
742 return ret;
743}
744
745static int cs35l35_codec_probe(struct snd_soc_codec *codec)
746{
747 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
748 struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
749 struct monitor_cfg *monitor_config = &cs35l35->pdata.mon_cfg;
750 int ret;
751
6387f866
BA		 752 /* Set Platform Data */
753 if (cs35l35->pdata.bst_vctl)
754 regmap_update_bits(cs35l35->regmap, CS35L35_BST_CVTR_V_CTL,
755 CS35L35_BST_CTL_MASK,
756 cs35l35->pdata.bst_vctl);
757
758 if (cs35l35->pdata.bst_ipk)
759 regmap_update_bits(cs35l35->regmap, CS35L35_BST_PEAK_I,
760 CS35L35_BST_IPK_MASK,
761 cs35l35->pdata.bst_ipk <<
762 CS35L35_BST_IPK_SHIFT);
763
764 if (cs35l35->pdata.gain_zc)
765 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
766 CS35L35_AMP_GAIN_ZC_MASK,
767 cs35l35->pdata.gain_zc <<
768 CS35L35_AMP_GAIN_ZC_SHIFT);
769
770 if (cs35l35->pdata.aud_channel)
771 regmap_update_bits(cs35l35->regmap,
772 CS35L35_AUDIN_RXLOC_CTL,
773 CS35L35_AUD_IN_LR_MASK,
774 cs35l35->pdata.aud_channel <<
775 CS35L35_AUD_IN_LR_SHIFT);
776
777 if (cs35l35->pdata.stereo) {
778 regmap_update_bits(cs35l35->regmap,
779 CS35L35_ADVIN_RXLOC_CTL,
780 CS35L35_ADV_IN_LR_MASK,
781 cs35l35->pdata.adv_channel <<
782 CS35L35_ADV_IN_LR_SHIFT);
783 if (cs35l35->pdata.shared_bst)
784 regmap_update_bits(cs35l35->regmap, CS35L35_CLASS_H_CTL,
785 CS35L35_CH_STEREO_MASK,
786 1 << CS35L35_CH_STEREO_SHIFT);
787 ret = snd_soc_add_codec_controls(codec, cs35l35_adv_controls,
788 ARRAY_SIZE(cs35l35_adv_controls));
789 if (ret)
790 return ret;
791 }
792
793 if (cs35l35->pdata.sp_drv_str)
794 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
795 CS35L35_SP_DRV_MASK,
796 cs35l35->pdata.sp_drv_str <<
797 CS35L35_SP_DRV_SHIFT);
8d45f2d2
CK		 798 if (cs35l35->pdata.sp_drv_unused)
799 regmap_update_bits(cs35l35->regmap, CS35L35_SP_FMT_CTL3,
800 CS35L35_SP_I2S_DRV_MASK,
801 cs35l35->pdata.sp_drv_unused <<
802 CS35L35_SP_I2S_DRV_SHIFT);
6387f866
BA		 803
804 if (classh->classh_algo_enable) {
805 if (classh->classh_bst_override)
806 regmap_update_bits(cs35l35->regmap,
807 CS35L35_CLASS_H_CTL,
808 CS35L35_CH_BST_OVR_MASK,
809 classh->classh_bst_override <<
810 CS35L35_CH_BST_OVR_SHIFT);
811 if (classh->classh_bst_max_limit)
812 regmap_update_bits(cs35l35->regmap,
813 CS35L35_CLASS_H_CTL,
814 CS35L35_CH_BST_LIM_MASK,
815 classh->classh_bst_max_limit <<
816 CS35L35_CH_BST_LIM_SHIFT);
817 if (classh->classh_mem_depth)
818 regmap_update_bits(cs35l35->regmap,
819 CS35L35_CLASS_H_CTL,
820 CS35L35_CH_MEM_DEPTH_MASK,
821 classh->classh_mem_depth <<
822 CS35L35_CH_MEM_DEPTH_SHIFT);
823 if (classh->classh_headroom)
824 regmap_update_bits(cs35l35->regmap,
825 CS35L35_CLASS_H_HEADRM_CTL,
826 CS35L35_CH_HDRM_CTL_MASK,
827 classh->classh_headroom <<
828 CS35L35_CH_HDRM_CTL_SHIFT);
829 if (classh->classh_release_rate)
830 regmap_update_bits(cs35l35->regmap,
831 CS35L35_CLASS_H_RELEASE_RATE,
832 CS35L35_CH_REL_RATE_MASK,
833 classh->classh_release_rate <<
834 CS35L35_CH_REL_RATE_SHIFT);
835 if (classh->classh_wk_fet_disable)
836 regmap_update_bits(cs35l35->regmap,
837 CS35L35_CLASS_H_FET_DRIVE_CTL,
838 CS35L35_CH_WKFET_DIS_MASK,
839 classh->classh_wk_fet_disable <<
840 CS35L35_CH_WKFET_DIS_SHIFT);
841 if (classh->classh_wk_fet_delay)
842 regmap_update_bits(cs35l35->regmap,
843 CS35L35_CLASS_H_FET_DRIVE_CTL,
844 CS35L35_CH_WKFET_DEL_MASK,
845 classh->classh_wk_fet_delay <<
846 CS35L35_CH_WKFET_DEL_SHIFT);
847 if (classh->classh_wk_fet_thld)
848 regmap_update_bits(cs35l35->regmap,
849 CS35L35_CLASS_H_FET_DRIVE_CTL,
850 CS35L35_CH_WKFET_THLD_MASK,
851 classh->classh_wk_fet_thld <<
852 CS35L35_CH_WKFET_THLD_SHIFT);
853 if (classh->classh_vpch_auto)
854 regmap_update_bits(cs35l35->regmap,
855 CS35L35_CLASS_H_VP_CTL,
856 CS35L35_CH_VP_AUTO_MASK,
857 classh->classh_vpch_auto <<
858 CS35L35_CH_VP_AUTO_SHIFT);
859 if (classh->classh_vpch_rate)
860 regmap_update_bits(cs35l35->regmap,
861 CS35L35_CLASS_H_VP_CTL,
862 CS35L35_CH_VP_RATE_MASK,
863 classh->classh_vpch_rate <<
864 CS35L35_CH_VP_RATE_SHIFT);
865 if (classh->classh_vpch_man)
866 regmap_update_bits(cs35l35->regmap,
867 CS35L35_CLASS_H_VP_CTL,
868 CS35L35_CH_VP_MAN_MASK,
869 classh->classh_vpch_man <<
870 CS35L35_CH_VP_MAN_SHIFT);
871 }
872
873 if (monitor_config->is_present) {
874 if (monitor_config->vmon_specs) {
875 regmap_update_bits(cs35l35->regmap,
876 CS35L35_SPKMON_DEPTH_CTL,
877 CS35L35_VMON_DEPTH_MASK,
878 monitor_config->vmon_dpth <<
879 CS35L35_VMON_DEPTH_SHIFT);
880 regmap_update_bits(cs35l35->regmap,
881 CS35L35_VMON_TXLOC_CTL,
882 CS35L35_MON_TXLOC_MASK,
883 monitor_config->vmon_loc <<
884 CS35L35_MON_TXLOC_SHIFT);
885 regmap_update_bits(cs35l35->regmap,
886 CS35L35_VMON_TXLOC_CTL,
887 CS35L35_MON_FRM_MASK,
888 monitor_config->vmon_frm <<
889 CS35L35_MON_FRM_SHIFT);
890 }
891 if (monitor_config->imon_specs) {
892 regmap_update_bits(cs35l35->regmap,
893 CS35L35_SPKMON_DEPTH_CTL,
894 CS35L35_IMON_DEPTH_MASK,
895 monitor_config->imon_dpth <<
896 CS35L35_IMON_DEPTH_SHIFT);
897 regmap_update_bits(cs35l35->regmap,
898 CS35L35_IMON_TXLOC_CTL,
899 CS35L35_MON_TXLOC_MASK,
900 monitor_config->imon_loc <<
901 CS35L35_MON_TXLOC_SHIFT);
902 regmap_update_bits(cs35l35->regmap,
903 CS35L35_IMON_TXLOC_CTL,
904 CS35L35_MON_FRM_MASK,
905 monitor_config->imon_frm <<
906 CS35L35_MON_FRM_SHIFT);
907 }
908 if (monitor_config->vpmon_specs) {
909 regmap_update_bits(cs35l35->regmap,
910 CS35L35_SUPMON_DEPTH_CTL,
911 CS35L35_VPMON_DEPTH_MASK,
912 monitor_config->vpmon_dpth <<
913 CS35L35_VPMON_DEPTH_SHIFT);
914 regmap_update_bits(cs35l35->regmap,
915 CS35L35_VPMON_TXLOC_CTL,
916 CS35L35_MON_TXLOC_MASK,
917 monitor_config->vpmon_loc <<
918 CS35L35_MON_TXLOC_SHIFT);
919 regmap_update_bits(cs35l35->regmap,
920 CS35L35_VPMON_TXLOC_CTL,
921 CS35L35_MON_FRM_MASK,
922 monitor_config->vpmon_frm <<
923 CS35L35_MON_FRM_SHIFT);
924 }
925 if (monitor_config->vbstmon_specs) {
926 regmap_update_bits(cs35l35->regmap,
927 CS35L35_SUPMON_DEPTH_CTL,
928 CS35L35_VBSTMON_DEPTH_MASK,
929 monitor_config->vpmon_dpth <<
930 CS35L35_VBSTMON_DEPTH_SHIFT);
931 regmap_update_bits(cs35l35->regmap,
932 CS35L35_VBSTMON_TXLOC_CTL,
933 CS35L35_MON_TXLOC_MASK,
934 monitor_config->vbstmon_loc <<
935 CS35L35_MON_TXLOC_SHIFT);
936 regmap_update_bits(cs35l35->regmap,
937 CS35L35_VBSTMON_TXLOC_CTL,
938 CS35L35_MON_FRM_MASK,
939 monitor_config->vbstmon_frm <<
940 CS35L35_MON_FRM_SHIFT);
941 }
942 if (monitor_config->vpbrstat_specs) {
943 regmap_update_bits(cs35l35->regmap,
944 CS35L35_SUPMON_DEPTH_CTL,
945 CS35L35_VPBRSTAT_DEPTH_MASK,
946 monitor_config->vpbrstat_dpth <<
947 CS35L35_VPBRSTAT_DEPTH_SHIFT);
948 regmap_update_bits(cs35l35->regmap,
949 CS35L35_VPBR_STATUS_TXLOC_CTL,
950 CS35L35_MON_TXLOC_MASK,
951 monitor_config->vpbrstat_loc <<
952 CS35L35_MON_TXLOC_SHIFT);
953 regmap_update_bits(cs35l35->regmap,
954 CS35L35_VPBR_STATUS_TXLOC_CTL,
955 CS35L35_MON_FRM_MASK,
956 monitor_config->vpbrstat_frm <<
957 CS35L35_MON_FRM_SHIFT);
958 }
959 if (monitor_config->zerofill_specs) {
960 regmap_update_bits(cs35l35->regmap,
961 CS35L35_SUPMON_DEPTH_CTL,
962 CS35L35_ZEROFILL_DEPTH_MASK,
963 monitor_config->zerofill_dpth <<
964 CS35L35_ZEROFILL_DEPTH_SHIFT);
965 regmap_update_bits(cs35l35->regmap,
966 CS35L35_ZERO_FILL_LOC_CTL,
967 CS35L35_MON_TXLOC_MASK,
968 monitor_config->zerofill_loc <<
969 CS35L35_MON_TXLOC_SHIFT);
970 regmap_update_bits(cs35l35->regmap,
971 CS35L35_ZERO_FILL_LOC_CTL,
972 CS35L35_MON_FRM_MASK,
973 monitor_config->zerofill_frm <<
974 CS35L35_MON_FRM_SHIFT);
975 }
976 }
977
bfe41c67 978 return 0;
6387f866
BA		 979}
980
981static struct snd_soc_codec_driver soc_codec_dev_cs35l35 = {
982 .probe = cs35l35_codec_probe,
983 .set_sysclk = cs35l35_codec_set_sysclk,
984 .component_driver = {
985 .dapm_widgets = cs35l35_dapm_widgets,
986 .num_dapm_widgets = ARRAY_SIZE(cs35l35_dapm_widgets),
987
988 .dapm_routes = cs35l35_audio_map,
989 .num_dapm_routes = ARRAY_SIZE(cs35l35_audio_map),
990
991 .controls = cs35l35_aud_controls,
992 .num_controls = ARRAY_SIZE(cs35l35_aud_controls),
993 },
994
995};
996
997static struct regmap_config cs35l35_regmap = {
998 .reg_bits = 8,
999 .val_bits = 8,
1000
1001 .max_register = CS35L35_MAX_REGISTER,
1002 .reg_defaults = cs35l35_reg,
1003 .num_reg_defaults = ARRAY_SIZE(cs35l35_reg),
1004 .volatile_reg = cs35l35_volatile_register,
1005 .readable_reg = cs35l35_readable_register,
1006 .precious_reg = cs35l35_precious_register,
1007 .cache_type = REGCACHE_RBTREE,
1008};
1009
1010static irqreturn_t cs35l35_irq(int irq, void *data)
1011{
1012 struct cs35l35_private *cs35l35 = data;
6387f866
BA		 1013 unsigned int sticky1, sticky2, sticky3, sticky4;
1014 unsigned int mask1, mask2, mask3, mask4, current1;
1015
1016 /* ack the irq by reading all status registers */
1017 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_4, &sticky4);
1018 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_3, &sticky3);
1019 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_2, &sticky2);
1020 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_1, &sticky1);
1021
1022 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_4, &mask4);
1023 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_3, &mask3);
1024 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_2, &mask2);
1025 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_1, &mask1);
1026
1027 /* Check to see if unmasked bits are active */
1028 if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3)
1029 && !(sticky4 & ~mask4))
1030 return IRQ_NONE;
1031
1032 if (sticky2 & CS35L35_PDN_DONE)
1033 complete(&cs35l35->pdn_done);
1034
1035 /* read the current values */
1036 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_1, &current1);
1037
1038 /* handle the interrupts */
1039 if (sticky1 & CS35L35_CAL_ERR) {
5d3d0ad6 1040 dev_crit(cs35l35->dev, "Calibration Error\n");
6387f866
BA		 1041
1042 /* error is no longer asserted; safe to reset */
1043 if (!(current1 & CS35L35_CAL_ERR)) {
1044 pr_debug("%s : Cal error release\n", __func__);
1045 regmap_update_bits(cs35l35->regmap,
1046 CS35L35_PROT_RELEASE_CTL,
1047 CS35L35_CAL_ERR_RLS, 0);
1048 regmap_update_bits(cs35l35->regmap,
1049 CS35L35_PROT_RELEASE_CTL,
1050 CS35L35_CAL_ERR_RLS,
1051 CS35L35_CAL_ERR_RLS);
1052 regmap_update_bits(cs35l35->regmap,
1053 CS35L35_PROT_RELEASE_CTL,
1054 CS35L35_CAL_ERR_RLS, 0);
1055 }
1056 }
1057
1058 if (sticky1 & CS35L35_AMP_SHORT) {
5d3d0ad6 1059 dev_crit(cs35l35->dev, "AMP Short Error\n");
6387f866
BA		 1060 /* error is no longer asserted; safe to reset */
1061 if (!(current1 & CS35L35_AMP_SHORT)) {
5d3d0ad6 1062 dev_dbg(cs35l35->dev, "Amp short error release\n");
6387f866
BA		 1063 regmap_update_bits(cs35l35->regmap,
1064 CS35L35_PROT_RELEASE_CTL,
1065 CS35L35_SHORT_RLS, 0);
1066 regmap_update_bits(cs35l35->regmap,
1067 CS35L35_PROT_RELEASE_CTL,
1068 CS35L35_SHORT_RLS,
1069 CS35L35_SHORT_RLS);
1070 regmap_update_bits(cs35l35->regmap,
1071 CS35L35_PROT_RELEASE_CTL,
1072 CS35L35_SHORT_RLS, 0);
1073 }
1074 }
1075
1076 if (sticky1 & CS35L35_OTW) {
5d3d0ad6 1077 dev_warn(cs35l35->dev, "Over temperature warning\n");
6387f866
BA		 1078
1079 /* error is no longer asserted; safe to reset */
1080 if (!(current1 & CS35L35_OTW)) {
5d3d0ad6 1081 dev_dbg(cs35l35->dev, "Over temperature warn release\n");
6387f866
BA		 1082 regmap_update_bits(cs35l35->regmap,
1083 CS35L35_PROT_RELEASE_CTL,
1084 CS35L35_OTW_RLS, 0);
1085 regmap_update_bits(cs35l35->regmap,
1086 CS35L35_PROT_RELEASE_CTL,
1087 CS35L35_OTW_RLS,
1088 CS35L35_OTW_RLS);
1089 regmap_update_bits(cs35l35->regmap,
1090 CS35L35_PROT_RELEASE_CTL,
1091 CS35L35_OTW_RLS, 0);
1092 }
1093 }
1094
1095 if (sticky1 & CS35L35_OTE) {
5d3d0ad6 1096 dev_crit(cs35l35->dev, "Over temperature error\n");
6387f866
BA		 1097 /* error is no longer asserted; safe to reset */
1098 if (!(current1 & CS35L35_OTE)) {
5d3d0ad6 1099 dev_dbg(cs35l35->dev, "Over temperature error release\n");
6387f866
BA		 1100 regmap_update_bits(cs35l35->regmap,
1101 CS35L35_PROT_RELEASE_CTL,
1102 CS35L35_OTE_RLS, 0);
1103 regmap_update_bits(cs35l35->regmap,
1104 CS35L35_PROT_RELEASE_CTL,
1105 CS35L35_OTE_RLS,
1106 CS35L35_OTE_RLS);
1107 regmap_update_bits(cs35l35->regmap,
1108 CS35L35_PROT_RELEASE_CTL,
1109 CS35L35_OTE_RLS, 0);
1110 }
1111 }
1112
1113 if (sticky3 & CS35L35_BST_HIGH) {
5d3d0ad6 1114 dev_crit(cs35l35->dev, "VBST error: powering off!\n");
6387f866
BA		 1115 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1116 CS35L35_PDN_AMP, CS35L35_PDN_AMP);
1117 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
1118 CS35L35_PDN_ALL, CS35L35_PDN_ALL);
1119 }
1120
1121 if (sticky3 & CS35L35_LBST_SHORT) {
5d3d0ad6 1122 dev_crit(cs35l35->dev, "LBST error: powering off!\n");
6387f866
BA		 1123 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1124 CS35L35_PDN_AMP, CS35L35_PDN_AMP);
1125 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
1126 CS35L35_PDN_ALL, CS35L35_PDN_ALL);
1127 }
1128
1129 if (sticky2 & CS35L35_VPBR_ERR)
5d3d0ad6 1130 dev_dbg(cs35l35->dev, "Error: Reactive Brownout\n");
6387f866
BA		 1131
1132 if (sticky4 & CS35L35_VMON_OVFL)
5d3d0ad6 1133 dev_dbg(cs35l35->dev, "Error: VMON overflow\n");
6387f866
BA		 1134
1135 if (sticky4 & CS35L35_IMON_OVFL)
5d3d0ad6 1136 dev_dbg(cs35l35->dev, "Error: IMON overflow\n");
6387f866
BA		 1137
1138 return IRQ_HANDLED;
1139}
1140
1141
1142static int cs35l35_handle_of_data(struct i2c_client *i2c_client,
1143 struct cs35l35_platform_data *pdata)
1144{
1145 struct device_node *np = i2c_client->dev.of_node;
1146 struct device_node *classh, *signal_format;
1147 struct classh_cfg *classh_config = &pdata->classh_algo;
1148 struct monitor_cfg *monitor_config = &pdata->mon_cfg;
1149 unsigned int val32 = 0;
1150 u8 monitor_array[3];
1151 int ret = 0;
1152
1153 if (!np)
1154 return 0;
1155
1156 pdata->bst_pdn_fet_on = of_property_read_bool(np,
1157 "cirrus,boost-pdn-fet-on");
1158
1159 ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val32);
1160 if (ret >= 0) {
1161 if (val32 < 2600 || val32 > 9000) {
1162 dev_err(&i2c_client->dev,
1163 "Invalid Boost Voltage %d mV\n", val32);
1164 return -EINVAL;
1165 }
1166 pdata->bst_vctl = ((val32 - 2600) / 100) + 1;
1167 }
1168
1169 ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val32);
1170 if (ret >= 0) {
1171 if (val32 < 1680 || val32 > 4480) {
1172 dev_err(&i2c_client->dev,
1173 "Invalid Boost Peak Current %u mA\n", val32);
1174 return -EINVAL;
1175 }
1176
1177 pdata->bst_ipk = (val32 - 1680) / 110;
1178 }
1179
1180 if (of_property_read_u32(np, "cirrus,sp-drv-strength", &val32) >= 0)
1181 pdata->sp_drv_str = val32;
8d45f2d2
CK		 1182 if (of_property_read_u32(np, "cirrus,sp-drv-unused", &val32) >= 0)
1183 pdata->sp_drv_unused = val32 | CS35L35_VALID_PDATA;
6387f866
BA		 1184
1185 pdata->stereo = of_property_read_bool(np, "cirrus,stereo-config");
1186
1187 if (pdata->stereo) {
1188 ret = of_property_read_u32(np, "cirrus,audio-channel", &val32);
1189 if (ret >= 0)
1190 pdata->aud_channel = val32;
1191
1192 ret = of_property_read_u32(np, "cirrus,advisory-channel",
1193 &val32);
1194 if (ret >= 0)
1195 pdata->adv_channel = val32;
1196
1197 pdata->shared_bst = of_property_read_bool(np,
1198 "cirrus,shared-boost");
1199 }
1200
1201 pdata->gain_zc = of_property_read_bool(np, "cirrus,amp-gain-zc");
1202
1203 classh = of_get_child_by_name(np, "cirrus,classh-internal-algo");
1204 classh_config->classh_algo_enable = classh ? true : false;
1205
1206 if (classh_config->classh_algo_enable) {
1207 classh_config->classh_bst_override =
1208 of_property_read_bool(np, "cirrus,classh-bst-overide");
1209
1210 ret = of_property_read_u32(classh,
1211 "cirrus,classh-bst-max-limit",
1212 &val32);
1213 if (ret >= 0) {
1214 val32 |= CS35L35_VALID_PDATA;
1215 classh_config->classh_bst_max_limit = val32;
1216 }
1217
1218 ret = of_property_read_u32(classh,
1219 "cirrus,classh-bst-max-limit",
1220 &val32);
1221 if (ret >= 0) {
1222 val32 |= CS35L35_VALID_PDATA;
1223 classh_config->classh_bst_max_limit = val32;
1224 }
1225
1226 ret = of_property_read_u32(classh, "cirrus,classh-mem-depth",
1227 &val32);
1228 if (ret >= 0) {
1229 val32 |= CS35L35_VALID_PDATA;
1230 classh_config->classh_mem_depth = val32;
1231 }
1232
1233 ret = of_property_read_u32(classh, "cirrus,classh-release-rate",
1234 &val32);
1235 if (ret >= 0)
1236 classh_config->classh_release_rate = val32;
1237
1238 ret = of_property_read_u32(classh, "cirrus,classh-headroom",
1239 &val32);
1240 if (ret >= 0) {
1241 val32 |= CS35L35_VALID_PDATA;
1242 classh_config->classh_headroom = val32;
1243 }
1244
1245 ret = of_property_read_u32(classh,
1246 "cirrus,classh-wk-fet-disable",
1247 &val32);
1248 if (ret >= 0)
1249 classh_config->classh_wk_fet_disable = val32;
1250
1251 ret = of_property_read_u32(classh, "cirrus,classh-wk-fet-delay",
1252 &val32);
1253 if (ret >= 0) {
1254 val32 |= CS35L35_VALID_PDATA;
1255 classh_config->classh_wk_fet_delay = val32;
1256 }
1257
1258 ret = of_property_read_u32(classh, "cirrus,classh-wk-fet-thld",
1259 &val32);
1260 if (ret >= 0)
1261 classh_config->classh_wk_fet_thld = val32;
1262
1263 ret = of_property_read_u32(classh, "cirrus,classh-vpch-auto",
1264 &val32);
1265 if (ret >= 0) {
1266 val32 |= CS35L35_VALID_PDATA;
1267 classh_config->classh_vpch_auto = val32;
1268 }
1269
1270 ret = of_property_read_u32(classh, "cirrus,classh-vpch-rate",
1271 &val32);
1272 if (ret >= 0) {
1273 val32 |= CS35L35_VALID_PDATA;
1274 classh_config->classh_vpch_rate = val32;
1275 }
1276
1277 ret = of_property_read_u32(classh, "cirrus,classh-vpch-man",
1278 &val32);
1279 if (ret >= 0)
1280 classh_config->classh_vpch_man = val32;
1281 }
1282 of_node_put(classh);
1283
1284 /* frame depth location */
1285 signal_format = of_get_child_by_name(np, "cirrus,monitor-signal-format");
1286 monitor_config->is_present = signal_format ? true : false;
1287 if (monitor_config->is_present) {
1288 ret = of_property_read_u8_array(signal_format, "cirrus,imon",
1289 monitor_array, ARRAY_SIZE(monitor_array));
1290 if (!ret) {
1291 monitor_config->imon_specs = true;
1292 monitor_config->imon_dpth = monitor_array[0];
1293 monitor_config->imon_loc = monitor_array[1];
1294 monitor_config->imon_frm = monitor_array[2];
1295 }
1296 ret = of_property_read_u8_array(signal_format, "cirrus,vmon",
1297 monitor_array, ARRAY_SIZE(monitor_array));
1298 if (!ret) {
1299 monitor_config->vmon_specs = true;
1300 monitor_config->vmon_dpth = monitor_array[0];
1301 monitor_config->vmon_loc = monitor_array[1];
1302 monitor_config->vmon_frm = monitor_array[2];
1303 }
1304 ret = of_property_read_u8_array(signal_format, "cirrus,vpmon",
1305 monitor_array, ARRAY_SIZE(monitor_array));
1306 if (!ret) {
1307 monitor_config->vpmon_specs = true;
1308 monitor_config->vpmon_dpth = monitor_array[0];
1309 monitor_config->vpmon_loc = monitor_array[1];
1310 monitor_config->vpmon_frm = monitor_array[2];
1311 }
1312 ret = of_property_read_u8_array(signal_format, "cirrus,vbstmon",
1313 monitor_array, ARRAY_SIZE(monitor_array));
1314 if (!ret) {
1315 monitor_config->vbstmon_specs = true;
1316 monitor_config->vbstmon_dpth = monitor_array[0];
1317 monitor_config->vbstmon_loc = monitor_array[1];
1318 monitor_config->vbstmon_frm = monitor_array[2];
1319 }
1320 ret = of_property_read_u8_array(signal_format, "cirrus,vpbrstat",
1321 monitor_array, ARRAY_SIZE(monitor_array));
1322 if (!ret) {
1323 monitor_config->vpbrstat_specs = true;
1324 monitor_config->vpbrstat_dpth = monitor_array[0];
1325 monitor_config->vpbrstat_loc = monitor_array[1];
1326 monitor_config->vpbrstat_frm = monitor_array[2];
1327 }
1328 ret = of_property_read_u8_array(signal_format, "cirrus,zerofill",
1329 monitor_array, ARRAY_SIZE(monitor_array));
1330 if (!ret) {
1331 monitor_config->zerofill_specs = true;
1332 monitor_config->zerofill_dpth = monitor_array[0];
1333 monitor_config->zerofill_loc = monitor_array[1];
1334 monitor_config->zerofill_frm = monitor_array[2];
1335 }
1336 }
1337 of_node_put(signal_format);
1338
1339 return 0;
1340}
1341
1342/* Errata Rev A0 */
1343static const struct reg_sequence cs35l35_errata_patch[] = {
1344
1345 { 0x7F, 0x99 },
1346 { 0x00, 0x99 },
1347 { 0x52, 0x22 },
1348 { 0x04, 0x14 },
1349 { 0x6D, 0x44 },
1350 { 0x24, 0x10 },
1351 { 0x58, 0xC4 },
1352 { 0x00, 0x98 },
1353 { 0x18, 0x08 },
1354 { 0x00, 0x00 },
1355 { 0x7F, 0x00 },
1356};
1357
1358static int cs35l35_i2c_probe(struct i2c_client *i2c_client,
1359 const struct i2c_device_id *id)
1360{
1361 struct cs35l35_private *cs35l35;
1f758cd9
CK		 1362 struct device *dev = &i2c_client->dev;
1363 struct cs35l35_platform_data *pdata = dev_get_platdata(dev);
6387f866
BA		 1364 int i;
1365 int ret;
1366 unsigned int devid = 0;
1367 unsigned int reg;
1368
1f758cd9 1369 cs35l35 = devm_kzalloc(dev, sizeof(struct cs35l35_private), GFP_KERNEL);
6387f866
BA		 1370 if (!cs35l35)
1371 return -ENOMEM;
1372
5d3d0ad6
CK		 1373 cs35l35->dev = dev;
1374
6387f866
BA		 1375 i2c_set_clientdata(i2c_client, cs35l35);
1376 cs35l35->regmap = devm_regmap_init_i2c(i2c_client, &cs35l35_regmap);
1377 if (IS_ERR(cs35l35->regmap)) {
1378 ret = PTR_ERR(cs35l35->regmap);
1f758cd9 1379 dev_err(dev, "regmap_init() failed: %d\n", ret);
6387f866
BA		 1380 goto err;
1381 }
1382
1383 for (i = 0; i < ARRAY_SIZE(cs35l35_supplies); i++)
1384 cs35l35->supplies[i].supply = cs35l35_supplies[i];
03ff570c
CIK		 1385
1386 cs35l35->num_supplies = ARRAY_SIZE(cs35l35_supplies);
6387f866 1387
1f758cd9
CK		 1388 ret = devm_regulator_bulk_get(dev, cs35l35->num_supplies,
1389 cs35l35->supplies);
6387f866 1390 if (ret != 0) {
1f758cd9 1391 dev_err(dev, "Failed to request core supplies: %d\n", ret);
6387f866
BA		 1392 return ret;
1393 }
1394
1395 if (pdata) {
1396 cs35l35->pdata = *pdata;
1397 } else {
1f758cd9
CK		 1398 pdata = devm_kzalloc(dev, sizeof(struct cs35l35_platform_data),
1399 GFP_KERNEL);
6387f866
BA		 1400 if (!pdata)
1401 return -ENOMEM;
1402 if (i2c_client->dev.of_node) {
1403 ret = cs35l35_handle_of_data(i2c_client, pdata);
1404 if (ret != 0)
1405 return ret;
1406
1407 }
1408 cs35l35->pdata = *pdata;
1409 }
1410
1411 ret = regulator_bulk_enable(cs35l35->num_supplies,
1412 cs35l35->supplies);
1413 if (ret != 0) {
1f758cd9 1414 dev_err(dev, "Failed to enable core supplies: %d\n", ret);
6387f866
BA		 1415 return ret;
1416 }
1417
1418 /* returning NULL can be valid if in stereo mode */
1f758cd9
CK		 1419 cs35l35->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1420 GPIOD_OUT_LOW);
6387f866
BA		 1421 if (IS_ERR(cs35l35->reset_gpio)) {
1422 ret = PTR_ERR(cs35l35->reset_gpio);
8e71321d 1423 cs35l35->reset_gpio = NULL;
6387f866 1424 if (ret == -EBUSY) {
1f758cd9 1425 dev_info(dev,
6387f866 1426 "Reset line busy, assuming shared reset\n");
6387f866 1427 } else {
1f758cd9 1428 dev_err(dev, "Failed to get reset GPIO: %d\n", ret);
6387f866
BA		 1429 goto err;
1430 }
1431 }
1432
1433 gpiod_set_value_cansleep(cs35l35->reset_gpio, 1);
1434
1435 init_completion(&cs35l35->pdn_done);
1436
1f758cd9 1437 ret = devm_request_threaded_irq(dev, i2c_client->irq, NULL, cs35l35_irq,
bf5043d6
CK		 1438 IRQF_ONESHOT | IRQF_TRIGGER_LOW |
1439 IRQF_SHARED, "cs35l35", cs35l35);
6387f866 1440 if (ret != 0) {
1f758cd9 1441 dev_err(dev, "Failed to request IRQ: %d\n", ret);
6387f866
BA		 1442 goto err;
1443 }
1444 /* initialize codec */
1445 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_AB, &reg);
1446
1447 devid = (reg & 0xFF) << 12;
1448 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_CD, &reg);
1449 devid |= (reg & 0xFF) << 4;
1450 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_E, &reg);
1451 devid |= (reg & 0xF0) >> 4;
1452
1453 if (devid != CS35L35_CHIP_ID) {
1f758cd9 1454 dev_err(dev, "CS35L35 Device ID (%X). Expected ID %X\n",
6387f866
BA		 1455 devid, CS35L35_CHIP_ID);
1456 ret = -ENODEV;
1457 goto err;
1458 }
1459
1460 ret = regmap_read(cs35l35->regmap, CS35L35_REV_ID, &reg);
1461 if (ret < 0) {
1f758cd9 1462 dev_err(dev, "Get Revision ID failed: %d\n", ret);
6387f866
BA		 1463 goto err;
1464 }
1465
1466 ret = regmap_register_patch(cs35l35->regmap, cs35l35_errata_patch,
1467 ARRAY_SIZE(cs35l35_errata_patch));
1468 if (ret < 0) {
1f758cd9 1469 dev_err(dev, "Failed to apply errata patch: %d\n", ret);
6387f866
BA		 1470 goto err;
1471 }
1472
1f758cd9 1473 dev_info(dev, "Cirrus Logic CS35L35 (%x), Revision: %02X\n",
82875163 1474 devid, reg & 0xFF);
6387f866
BA		 1475
1476 /* Set the INT Masks for critical errors */
1477 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_1,
1478 CS35L35_INT1_CRIT_MASK);
1479 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_2,
1480 CS35L35_INT2_CRIT_MASK);
1481 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_3,
1482 CS35L35_INT3_CRIT_MASK);
1483 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_4,
1484 CS35L35_INT4_CRIT_MASK);
1485
1486 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1487 CS35L35_PWR2_PDN_MASK,
1488 CS35L35_PWR2_PDN_MASK);
1489
1490 if (cs35l35->pdata.bst_pdn_fet_on)
1491 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1492 CS35L35_PDN_BST_MASK,
1493 1 << CS35L35_PDN_BST_FETON_SHIFT);
1494 else
1495 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1496 CS35L35_PDN_BST_MASK,
1497 1 << CS35L35_PDN_BST_FETOFF_SHIFT);
1498
1499 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL3,
1500 CS35L35_PWR3_PDN_MASK,
1501 CS35L35_PWR3_PDN_MASK);
1502
1503 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
1504 CS35L35_AMP_MUTE_MASK, 1 << CS35L35_AMP_MUTE_SHIFT);
1505
1f758cd9
CK		 1506 ret = snd_soc_register_codec(dev, &soc_codec_dev_cs35l35, cs35l35_dai,
1507 ARRAY_SIZE(cs35l35_dai));
6387f866 1508 if (ret < 0) {
1f758cd9 1509 dev_err(dev, "Failed to register codec: %d\n", ret);
6387f866
BA		 1510 goto err;
1511 }
1512
1bb06ada
CK		 1513 return 0;
1514
6387f866
BA		 1515err:
1516 regulator_bulk_disable(cs35l35->num_supplies,
1517 cs35l35->supplies);
1518 gpiod_set_value_cansleep(cs35l35->reset_gpio, 0);
1519
1520 return ret;
1521}
1522
1523static int cs35l35_i2c_remove(struct i2c_client *client)
1524{
1525 snd_soc_unregister_codec(&client->dev);
1526 return 0;
1527}
1528
1529static const struct of_device_id cs35l35_of_match[] = {
1530 {.compatible = "cirrus,cs35l35"},
1531 {},
1532};
1533MODULE_DEVICE_TABLE(of, cs35l35_of_match);
1534
1535static const struct i2c_device_id cs35l35_id[] = {
1536 {"cs35l35", 0},
1537 {}
1538};
1539
1540MODULE_DEVICE_TABLE(i2c, cs35l35_id);
1541
1542static struct i2c_driver cs35l35_i2c_driver = {
1543 .driver = {
1544 .name = "cs35l35",
1545 .of_match_table = cs35l35_of_match,
1546 },
1547 .id_table = cs35l35_id,
1548 .probe = cs35l35_i2c_probe,
1549 .remove = cs35l35_i2c_remove,
1550};
1551
1552module_i2c_driver(cs35l35_i2c_driver);
1553
1554MODULE_DESCRIPTION("ASoC CS35L35 driver");
1555MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1556MODULE_LICENSE("GPL");
Ubuntu Hirsute Linux kernel mirror