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ASoC: cs35l35: returning uninitialized in probe()
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / cs35l35.c
CommitLineData
6387f866
BA		 1/*
2 * cs35l35.c -- CS35L35 ALSA SoC audio driver
3 *
4 * Copyright 2017 Cirrus Logic, Inc.
5 *
6 * Author: Brian Austin <brian.austin@cirrus.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/version.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/i2c.h>
21#include <linux/slab.h>
22#include <linux/platform_device.h>
23#include <linux/regulator/consumer.h>
24#include <linux/gpio/consumer.h>
25#include <linux/of_device.h>
26#include <linux/of_gpio.h>
27#include <linux/regmap.h>
28#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/soc.h>
32#include <sound/soc-dapm.h>
33#include <linux/gpio.h>
34#include <sound/initval.h>
35#include <sound/tlv.h>
36#include <sound/cs35l35.h>
37#include <linux/of_irq.h>
38#include <linux/completion.h>
39
40#include "cs35l35.h"
41
42/*
43 * Some fields take zero as a valid value so use a high bit flag that won't
44 * get written to the device to mark those.
45 */
46#define CS35L35_VALID_PDATA 0x80000000
47
48static const struct reg_default cs35l35_reg[] = {
49 {CS35L35_PWRCTL1, 0x01},
50 {CS35L35_PWRCTL2, 0x11},
51 {CS35L35_PWRCTL3, 0x00},
52 {CS35L35_CLK_CTL1, 0x04},
53 {CS35L35_CLK_CTL2, 0x10},
54 {CS35L35_CLK_CTL3, 0xCF},
55 {CS35L35_SP_FMT_CTL1, 0x20},
56 {CS35L35_SP_FMT_CTL2, 0x00},
57 {CS35L35_SP_FMT_CTL3, 0x02},
58 {CS35L35_MAG_COMP_CTL, 0x00},
59 {CS35L35_AMP_INP_DRV_CTL, 0x01},
60 {CS35L35_AMP_DIG_VOL_CTL, 0x12},
61 {CS35L35_AMP_DIG_VOL, 0x00},
62 {CS35L35_ADV_DIG_VOL, 0x00},
63 {CS35L35_PROTECT_CTL, 0x06},
64 {CS35L35_AMP_GAIN_AUD_CTL, 0x13},
65 {CS35L35_AMP_GAIN_PDM_CTL, 0x00},
66 {CS35L35_AMP_GAIN_ADV_CTL, 0x00},
67 {CS35L35_GPI_CTL, 0x00},
68 {CS35L35_BST_CVTR_V_CTL, 0x00},
69 {CS35L35_BST_PEAK_I, 0x07},
70 {CS35L35_BST_RAMP_CTL, 0x85},
71 {CS35L35_BST_CONV_COEF_1, 0x24},
72 {CS35L35_BST_CONV_COEF_2, 0x24},
73 {CS35L35_BST_CONV_SLOPE_COMP, 0x47},
74 {CS35L35_BST_CONV_SW_FREQ, 0x04},
75 {CS35L35_CLASS_H_CTL, 0x0B},
76 {CS35L35_CLASS_H_HEADRM_CTL, 0x0B},
77 {CS35L35_CLASS_H_RELEASE_RATE, 0x08},
78 {CS35L35_CLASS_H_FET_DRIVE_CTL, 0x41},
79 {CS35L35_CLASS_H_VP_CTL, 0xC5},
80 {CS35L35_VPBR_CTL, 0x0A},
81 {CS35L35_VPBR_VOL_CTL, 0x09},
82 {CS35L35_VPBR_TIMING_CTL, 0x6A},
83 {CS35L35_VPBR_MODE_VOL_CTL, 0x40},
84 {CS35L35_SPKR_MON_CTL, 0xC0},
85 {CS35L35_IMON_SCALE_CTL, 0x30},
86 {CS35L35_AUDIN_RXLOC_CTL, 0x00},
87 {CS35L35_ADVIN_RXLOC_CTL, 0x80},
88 {CS35L35_VMON_TXLOC_CTL, 0x00},
89 {CS35L35_IMON_TXLOC_CTL, 0x80},
90 {CS35L35_VPMON_TXLOC_CTL, 0x04},
91 {CS35L35_VBSTMON_TXLOC_CTL, 0x84},
92 {CS35L35_VPBR_STATUS_TXLOC_CTL, 0x04},
93 {CS35L35_ZERO_FILL_LOC_CTL, 0x00},
94 {CS35L35_AUDIN_DEPTH_CTL, 0x0F},
95 {CS35L35_SPKMON_DEPTH_CTL, 0x0F},
96 {CS35L35_SUPMON_DEPTH_CTL, 0x0F},
97 {CS35L35_ZEROFILL_DEPTH_CTL, 0x00},
98 {CS35L35_MULT_DEV_SYNCH1, 0x02},
99 {CS35L35_MULT_DEV_SYNCH2, 0x80},
100 {CS35L35_PROT_RELEASE_CTL, 0x00},
101 {CS35L35_DIAG_MODE_REG_LOCK, 0x00},
102 {CS35L35_DIAG_MODE_CTL_1, 0x40},
103 {CS35L35_DIAG_MODE_CTL_2, 0x00},
104 {CS35L35_INT_MASK_1, 0xFF},
105 {CS35L35_INT_MASK_2, 0xFF},
106 {CS35L35_INT_MASK_3, 0xFF},
107 {CS35L35_INT_MASK_4, 0xFF},
108
109};
110
111static bool cs35l35_volatile_register(struct device *dev, unsigned int reg)
112{
113 switch (reg) {
114 case CS35L35_INT_STATUS_1:
115 case CS35L35_INT_STATUS_2:
116 case CS35L35_INT_STATUS_3:
117 case CS35L35_INT_STATUS_4:
118 case CS35L35_PLL_STATUS:
119 case CS35L35_OTP_TRIM_STATUS:
120 return true;
121 default:
122 return false;
123 }
124}
125
126static bool cs35l35_readable_register(struct device *dev, unsigned int reg)
127{
128 switch (reg) {
129 case CS35L35_DEVID_AB ... CS35L35_PWRCTL3:
130 case CS35L35_CLK_CTL1 ... CS35L35_SP_FMT_CTL3:
131 case CS35L35_MAG_COMP_CTL ... CS35L35_AMP_GAIN_AUD_CTL:
132 case CS35L35_AMP_GAIN_PDM_CTL ... CS35L35_BST_PEAK_I:
133 case CS35L35_BST_RAMP_CTL ... CS35L35_BST_CONV_SW_FREQ:
134 case CS35L35_CLASS_H_CTL ... CS35L35_CLASS_H_VP_CTL:
135 case CS35L35_CLASS_H_STATUS:
136 case CS35L35_VPBR_CTL ... CS35L35_VPBR_MODE_VOL_CTL:
137 case CS35L35_VPBR_ATTEN_STATUS:
138 case CS35L35_SPKR_MON_CTL:
139 case CS35L35_IMON_SCALE_CTL ... CS35L35_ZEROFILL_DEPTH_CTL:
140 case CS35L35_MULT_DEV_SYNCH1 ... CS35L35_PROT_RELEASE_CTL:
141 case CS35L35_DIAG_MODE_REG_LOCK ... CS35L35_DIAG_MODE_CTL_2:
142 case CS35L35_INT_MASK_1 ... CS35L35_PLL_STATUS:
143 case CS35L35_OTP_TRIM_STATUS:
144 return true;
145 default:
146 return false;
147 }
148}
149
150static bool cs35l35_precious_register(struct device *dev, unsigned int reg)
151{
152 switch (reg) {
153 case CS35L35_INT_STATUS_1:
154 case CS35L35_INT_STATUS_2:
155 case CS35L35_INT_STATUS_3:
156 case CS35L35_INT_STATUS_4:
157 case CS35L35_PLL_STATUS:
158 case CS35L35_OTP_TRIM_STATUS:
159 return true;
160 default:
161 return false;
162 }
163}
164
165static int cs35l35_sdin_event(struct snd_soc_dapm_widget *w,
166 struct snd_kcontrol *kcontrol, int event)
167{
168 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
169 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
170 int ret = 0;
171
172 switch (event) {
173 case SND_SOC_DAPM_PRE_PMU:
174 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
175 CS35L35_MCLK_DIS_MASK,
176 0 << CS35L35_MCLK_DIS_SHIFT);
177 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
178 CS35L35_DISCHG_FILT_MASK,
179 0 << CS35L35_DISCHG_FILT_SHIFT);
180 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
181 CS35L35_PDN_ALL_MASK, 0);
182 break;
183 case SND_SOC_DAPM_POST_PMD:
184 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
185 CS35L35_DISCHG_FILT_MASK,
186 1 << CS35L35_DISCHG_FILT_SHIFT);
187 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
188 CS35L35_PDN_ALL_MASK, 1);
189
190 reinit_completion(&cs35l35->pdn_done);
191
192 ret = wait_for_completion_timeout(&cs35l35->pdn_done,
193 msecs_to_jiffies(100));
194 if (ret == 0) {
195 dev_err(codec->dev, "TIMEOUT PDN_DONE did not complete in 100ms\n");
196 ret = -ETIMEDOUT;
197 }
198
199 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
200 CS35L35_MCLK_DIS_MASK,
201 1 << CS35L35_MCLK_DIS_SHIFT);
202 break;
203 default:
204 dev_err(codec->dev, "Invalid event = 0x%x\n", event);
205 ret = -EINVAL;
206 }
207 return ret;
208}
209
210static int cs35l35_main_amp_event(struct snd_soc_dapm_widget *w,
211 struct snd_kcontrol *kcontrol, int event)
212{
213 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
214 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
215 unsigned int reg[4];
216 int i;
217
218 switch (event) {
219 case SND_SOC_DAPM_PRE_PMU:
220 if (cs35l35->pdata.bst_pdn_fet_on)
221 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
222 CS35L35_PDN_BST_MASK,
223 0 << CS35L35_PDN_BST_FETON_SHIFT);
224 else
225 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
226 CS35L35_PDN_BST_MASK,
227 0 << CS35L35_PDN_BST_FETOFF_SHIFT);
228 break;
229 case SND_SOC_DAPM_POST_PMU:
230 usleep_range(5000, 5100);
231 /* If in PDM mode we must use VP for Voltage control */
232 if (cs35l35->pdm_mode)
233 regmap_update_bits(cs35l35->regmap,
234 CS35L35_BST_CVTR_V_CTL,
235 CS35L35_BST_CTL_MASK,
236 0 << CS35L35_BST_CTL_SHIFT);
237
238 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
239 CS35L35_AMP_MUTE_MASK, 0);
240
241 for (i = 0; i < 2; i++)
242 regmap_bulk_read(cs35l35->regmap, CS35L35_INT_STATUS_1,
243 &reg, ARRAY_SIZE(reg));
244
245 break;
246 case SND_SOC_DAPM_PRE_PMD:
247 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
248 CS35L35_AMP_MUTE_MASK,
249 1 << CS35L35_AMP_MUTE_SHIFT);
250 if (cs35l35->pdata.bst_pdn_fet_on)
251 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
252 CS35L35_PDN_BST_MASK,
253 1 << CS35L35_PDN_BST_FETON_SHIFT);
254 else
255 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
256 CS35L35_PDN_BST_MASK,
257 1 << CS35L35_PDN_BST_FETOFF_SHIFT);
258 break;
259 case SND_SOC_DAPM_POST_PMD:
260 usleep_range(5000, 5100);
261 /*
262 * If PDM mode we should switch back to pdata value
263 * for Voltage control when we go down
264 */
265 if (cs35l35->pdm_mode)
266 regmap_update_bits(cs35l35->regmap,
267 CS35L35_BST_CVTR_V_CTL,
268 CS35L35_BST_CTL_MASK,
269 cs35l35->pdata.bst_vctl
270 << CS35L35_BST_CTL_SHIFT);
271
272 break;
273 default:
274 dev_err(codec->dev, "Invalid event = 0x%x\n", event);
275 }
276 return 0;
277}
278
279static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1);
280static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 50, 0);
281
282static const struct snd_kcontrol_new cs35l35_aud_controls[] = {
283 SOC_SINGLE_SX_TLV("Digital Audio Volume", CS35L35_AMP_DIG_VOL,
284 0, 0x34, 0xE4, dig_vol_tlv),
285 SOC_SINGLE_TLV("Analog Audio Volume", CS35L35_AMP_GAIN_AUD_CTL, 0, 19, 0,
286 amp_gain_tlv),
287 SOC_SINGLE_TLV("PDM Volume", CS35L35_AMP_GAIN_PDM_CTL, 0, 19, 0,
288 amp_gain_tlv),
289};
290
291static const struct snd_kcontrol_new cs35l35_adv_controls[] = {
292 SOC_SINGLE_SX_TLV("Digital Advisory Volume", CS35L35_ADV_DIG_VOL,
293 0, 0x34, 0xE4, dig_vol_tlv),
294 SOC_SINGLE_TLV("Analog Advisory Volume", CS35L35_AMP_GAIN_ADV_CTL, 0, 19, 0,
295 amp_gain_tlv),
296};
297
298static const struct snd_soc_dapm_widget cs35l35_dapm_widgets[] = {
299 SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L35_PWRCTL3, 1, 1,
300 cs35l35_sdin_event, SND_SOC_DAPM_PRE_PMU |
301 SND_SOC_DAPM_POST_PMD),
302 SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L35_PWRCTL3, 2, 1),
303
304 SND_SOC_DAPM_OUTPUT("SPK"),
305
306 SND_SOC_DAPM_INPUT("VP"),
307 SND_SOC_DAPM_INPUT("VBST"),
308 SND_SOC_DAPM_INPUT("ISENSE"),
309 SND_SOC_DAPM_INPUT("VSENSE"),
310
311 SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L35_PWRCTL2, 7, 1),
312 SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L35_PWRCTL2, 6, 1),
313 SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L35_PWRCTL3, 3, 1),
314 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L35_PWRCTL3, 4, 1),
315 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L35_PWRCTL2, 5, 1),
316
317 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L35_PWRCTL2, 0, 1, NULL, 0,
318 cs35l35_main_amp_event, SND_SOC_DAPM_PRE_PMU |
319 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU |
320 SND_SOC_DAPM_PRE_PMD),
321};
322
323static const struct snd_soc_dapm_route cs35l35_audio_map[] = {
324 {"VPMON ADC", NULL, "VP"},
325 {"VBSTMON ADC", NULL, "VBST"},
326 {"IMON ADC", NULL, "ISENSE"},
327 {"VMON ADC", NULL, "VSENSE"},
328 {"SDOUT", NULL, "IMON ADC"},
329 {"SDOUT", NULL, "VMON ADC"},
330 {"SDOUT", NULL, "VBSTMON ADC"},
331 {"SDOUT", NULL, "VPMON ADC"},
332 {"AMP Capture", NULL, "SDOUT"},
333
334 {"SDIN", NULL, "AMP Playback"},
335 {"CLASS H", NULL, "SDIN"},
336 {"Main AMP", NULL, "CLASS H"},
337 {"SPK", NULL, "Main AMP"},
338};
339
340static int cs35l35_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
341{
342 struct snd_soc_codec *codec = codec_dai->codec;
343 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
344
345 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
346 case SND_SOC_DAIFMT_CBM_CFM:
347 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
348 CS35L35_MS_MASK, 1 << CS35L35_MS_SHIFT);
349 cs35l35->slave_mode = false;
350 break;
351 case SND_SOC_DAIFMT_CBS_CFS:
352 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
353 CS35L35_MS_MASK, 0 << CS35L35_MS_SHIFT);
354 cs35l35->slave_mode = true;
355 break;
356 default:
357 return -EINVAL;
358 }
359
360 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
361 case SND_SOC_DAIFMT_I2S:
362 cs35l35->i2s_mode = true;
363 cs35l35->pdm_mode = false;
364 break;
365 case SND_SOC_DAIFMT_PDM:
366 cs35l35->pdm_mode = true;
367 cs35l35->i2s_mode = false;
368 break;
369 default:
370 return -EINVAL;
371 }
372
373 return 0;
374}
375
376struct cs35l35_sysclk_config {
377 int sysclk;
378 int srate;
379 u8 clk_cfg;
380};
381
382static struct cs35l35_sysclk_config cs35l35_clk_ctl[] = {
383
384 /* SYSCLK, Sample Rate, Serial Port Cfg */
385 {5644800, 44100, 0x00},
386 {5644800, 88200, 0x40},
387 {6144000, 48000, 0x10},
388 {6144000, 96000, 0x50},
389 {11289600, 44100, 0x01},
390 {11289600, 88200, 0x41},
391 {11289600, 176400, 0x81},
392 {12000000, 44100, 0x03},
393 {12000000, 48000, 0x13},
394 {12000000, 88200, 0x43},
395 {12000000, 96000, 0x53},
396 {12000000, 176400, 0x83},
397 {12000000, 192000, 0x93},
398 {12288000, 48000, 0x11},
399 {12288000, 96000, 0x51},
400 {12288000, 192000, 0x91},
401 {13000000, 44100, 0x07},
402 {13000000, 48000, 0x17},
403 {13000000, 88200, 0x47},
404 {13000000, 96000, 0x57},
405 {13000000, 176400, 0x87},
406 {13000000, 192000, 0x97},
407 {22579200, 44100, 0x02},
408 {22579200, 88200, 0x42},
409 {22579200, 176400, 0x82},
410 {24000000, 44100, 0x0B},
411 {24000000, 48000, 0x1B},
412 {24000000, 88200, 0x4B},
413 {24000000, 96000, 0x5B},
414 {24000000, 176400, 0x8B},
415 {24000000, 192000, 0x9B},
416 {24576000, 48000, 0x12},
417 {24576000, 96000, 0x52},
418 {24576000, 192000, 0x92},
419 {26000000, 44100, 0x0F},
420 {26000000, 48000, 0x1F},
421 {26000000, 88200, 0x4F},
422 {26000000, 96000, 0x5F},
423 {26000000, 176400, 0x8F},
424 {26000000, 192000, 0x9F},
425};
426
427static int cs35l35_get_clk_config(int sysclk, int srate)
428{
429 int i;
430
431 for (i = 0; i < ARRAY_SIZE(cs35l35_clk_ctl); i++) {
432 if (cs35l35_clk_ctl[i].sysclk == sysclk &&
433 cs35l35_clk_ctl[i].srate == srate)
434 return cs35l35_clk_ctl[i].clk_cfg;
435 }
436 return -EINVAL;
437}
438
439static int cs35l35_hw_params(struct snd_pcm_substream *substream,
440 struct snd_pcm_hw_params *params,
441 struct snd_soc_dai *dai)
442{
443 struct snd_soc_codec *codec = dai->codec;
444 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
445 struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
446 int srate = params_rate(params);
447 int ret = 0;
448 u8 sp_sclks;
449 int audin_format;
450 int errata_chk;
451
452 int clk_ctl = cs35l35_get_clk_config(cs35l35->sysclk, srate);
453
454 if (clk_ctl < 0) {
455 dev_err(codec->dev, "Invalid CLK:Rate %d:%d\n",
456 cs35l35->sysclk, srate);
457 return -EINVAL;
458 }
459
460 ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL2,
461 CS35L35_CLK_CTL2_MASK, clk_ctl);
462 if (ret != 0) {
463 dev_err(codec->dev, "Failed to set port config %d\n", ret);
464 return ret;
465 }
466
467 /*
468 * Rev A0 Errata
469 * When configured for the weak-drive detection path (CH_WKFET_DIS = 0)
470 * the Class H algorithm does not enable weak-drive operation for
471 * nonzero values of CH_WKFET_DELAY if SP_RATE = 01 or 10
472 */
473 errata_chk = clk_ctl & CS35L35_SP_RATE_MASK;
474
475 if (classh->classh_wk_fet_disable == 0x00 &&
476 (errata_chk == 0x01 || errata_chk == 0x03)) {
477 ret = regmap_update_bits(cs35l35->regmap,
478 CS35L35_CLASS_H_FET_DRIVE_CTL,
479 CS35L35_CH_WKFET_DEL_MASK,
480 0 << CS35L35_CH_WKFET_DEL_SHIFT);
481 if (ret != 0) {
482 dev_err(codec->dev, "Failed to set fet config %d\n",
483 ret);
484 return ret;
485 }
486 }
487
488 /*
489 * You can pull more Monitor data from the SDOUT pin than going to SDIN
490 * Just make sure your SCLK is fast enough to fill the frame
491 */
492 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
493 switch (params_width(params)) {
494 case 8:
495 audin_format = CS35L35_SDIN_DEPTH_8;
496 break;
497 case 16:
498 audin_format = CS35L35_SDIN_DEPTH_16;
499 break;
500 case 24:
501 audin_format = CS35L35_SDIN_DEPTH_24;
502 break;
503 default:
504 dev_err(codec->dev, "Unsupported Width %d\n",
505 params_width(params));
506 return -EINVAL;
507 }
508 regmap_update_bits(cs35l35->regmap,
509 CS35L35_AUDIN_DEPTH_CTL,
510 CS35L35_AUDIN_DEPTH_MASK,
511 audin_format <<
512 CS35L35_AUDIN_DEPTH_SHIFT);
513 if (cs35l35->pdata.stereo) {
514 regmap_update_bits(cs35l35->regmap,
515 CS35L35_AUDIN_DEPTH_CTL,
516 CS35L35_ADVIN_DEPTH_MASK,
517 audin_format <<
518 CS35L35_ADVIN_DEPTH_SHIFT);
519 }
520 }
521
522 if (cs35l35->i2s_mode) {
523 /* We have to take the SCLK to derive num sclks
524 * to configure the CLOCK_CTL3 register correctly
525 */
526 if ((cs35l35->sclk / srate) % 4) {
527 dev_err(codec->dev, "Unsupported sclk/fs ratio %d:%d\n",
528 cs35l35->sclk, srate);
529 return -EINVAL;
530 }
531 sp_sclks = ((cs35l35->sclk / srate) / 4) - 1;
532
533 /* Only certain ratios are supported in I2S Slave Mode */
534 if (cs35l35->slave_mode) {
535 switch (sp_sclks) {
536 case CS35L35_SP_SCLKS_32FS:
537 case CS35L35_SP_SCLKS_48FS:
538 case CS35L35_SP_SCLKS_64FS:
539 break;
540 default:
541 dev_err(codec->dev, "ratio not supported\n");
542 return -EINVAL;
f3a612a6 543 }
6387f866
BA		 544 } else {
545 /* Only certain ratios supported in I2S MASTER Mode */
546 switch (sp_sclks) {
547 case CS35L35_SP_SCLKS_32FS:
548 case CS35L35_SP_SCLKS_64FS:
549 break;
550 default:
551 dev_err(codec->dev, "ratio not supported\n");
552 return -EINVAL;
f3a612a6 553 }
6387f866
BA		 554 }
555 ret = regmap_update_bits(cs35l35->regmap,
556 CS35L35_CLK_CTL3,
557 CS35L35_SP_SCLKS_MASK, sp_sclks <<
558 CS35L35_SP_SCLKS_SHIFT);
559 if (ret != 0) {
560 dev_err(codec->dev, "Failed to set fsclk %d\n", ret);
561 return ret;
562 }
563 }
564
565 return ret;
566}
567
568static const unsigned int cs35l35_src_rates[] = {
569 44100, 48000, 88200, 96000, 176400, 192000
570};
571
572static const struct snd_pcm_hw_constraint_list cs35l35_constraints = {
573 .count = ARRAY_SIZE(cs35l35_src_rates),
574 .list = cs35l35_src_rates,
575};
576
577static int cs35l35_pcm_startup(struct snd_pcm_substream *substream,
578 struct snd_soc_dai *dai)
579{
580 struct snd_soc_codec *codec = dai->codec;
581 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
582
583 if (!substream->runtime)
584 return 0;
585
586 snd_pcm_hw_constraint_list(substream->runtime, 0,
587 SNDRV_PCM_HW_PARAM_RATE, &cs35l35_constraints);
588
589 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
590 CS35L35_PDM_MODE_MASK,
591 0 << CS35L35_PDM_MODE_SHIFT);
592
593 return 0;
594}
595
596static const unsigned int cs35l35_pdm_rates[] = {
597 44100, 48000, 88200, 96000
598};
599
600static const struct snd_pcm_hw_constraint_list cs35l35_pdm_constraints = {
601 .count = ARRAY_SIZE(cs35l35_pdm_rates),
602 .list = cs35l35_pdm_rates,
603};
604
605static int cs35l35_pdm_startup(struct snd_pcm_substream *substream,
606 struct snd_soc_dai *dai)
607{
608 struct snd_soc_codec *codec = dai->codec;
609 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
610
611 if (!substream->runtime)
612 return 0;
613
614 snd_pcm_hw_constraint_list(substream->runtime, 0,
615 SNDRV_PCM_HW_PARAM_RATE,
616 &cs35l35_pdm_constraints);
617
618 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
619 CS35L35_PDM_MODE_MASK,
620 1 << CS35L35_PDM_MODE_SHIFT);
621
622 return 0;
623}
624
625static int cs35l35_dai_set_sysclk(struct snd_soc_dai *dai,
626 int clk_id, unsigned int freq, int dir)
627{
628 struct snd_soc_codec *codec = dai->codec;
629 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
630
631 /* Need the SCLK Frequency regardless of sysclk source for I2S */
632 cs35l35->sclk = freq;
633
634 return 0;
635}
636
637static const struct snd_soc_dai_ops cs35l35_ops = {
638 .startup = cs35l35_pcm_startup,
639 .set_fmt = cs35l35_set_dai_fmt,
640 .hw_params = cs35l35_hw_params,
641 .set_sysclk = cs35l35_dai_set_sysclk,
642};
643
644static const struct snd_soc_dai_ops cs35l35_pdm_ops = {
645 .startup = cs35l35_pdm_startup,
646 .set_fmt = cs35l35_set_dai_fmt,
647 .hw_params = cs35l35_hw_params,
648};
649
650static struct snd_soc_dai_driver cs35l35_dai[] = {
651 {
652 .name = "cs35l35-pcm",
653 .id = 0,
654 .playback = {
655 .stream_name = "AMP Playback",
656 .channels_min = 1,
657 .channels_max = 8,
658 .rates = SNDRV_PCM_RATE_KNOT,
659 .formats = CS35L35_FORMATS,
660 },
661 .capture = {
662 .stream_name = "AMP Capture",
663 .channels_min = 1,
664 .channels_max = 8,
665 .rates = SNDRV_PCM_RATE_KNOT,
666 .formats = CS35L35_FORMATS,
667 },
668 .ops = &cs35l35_ops,
669 .symmetric_rates = 1,
670 },
671 {
672 .name = "cs35l35-pdm",
673 .id = 1,
674 .playback = {
675 .stream_name = "PDM Playback",
676 .channels_min = 1,
677 .channels_max = 2,
678 .rates = SNDRV_PCM_RATE_KNOT,
679 .formats = CS35L35_FORMATS,
680 },
681 .ops = &cs35l35_pdm_ops,
682 },
683};
684
685static int cs35l35_codec_set_sysclk(struct snd_soc_codec *codec,
686 int clk_id, int source, unsigned int freq,
687 int dir)
688{
689 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
690 int clksrc;
691 int ret = 0;
692
693 switch (clk_id) {
694 case 0:
695 clksrc = CS35L35_CLK_SOURCE_MCLK;
696 break;
697 case 1:
698 clksrc = CS35L35_CLK_SOURCE_SCLK;
699 break;
700 case 2:
701 clksrc = CS35L35_CLK_SOURCE_PDM;
702 break;
703 default:
704 dev_err(codec->dev, "Invalid CLK Source\n");
705 return -EINVAL;
f3a612a6 706 }
6387f866
BA		 707
708 switch (freq) {
709 case 5644800:
710 case 6144000:
711 case 11289600:
712 case 12000000:
713 case 12288000:
714 case 13000000:
715 case 22579200:
716 case 24000000:
717 case 24576000:
718 case 26000000:
719 cs35l35->sysclk = freq;
720 break;
721 default:
722 dev_err(codec->dev, "Invalid CLK Frequency Input : %d\n", freq);
723 return -EINVAL;
724 }
725
726 ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
727 CS35L35_CLK_SOURCE_MASK,
728 clksrc << CS35L35_CLK_SOURCE_SHIFT);
729 if (ret != 0) {
730 dev_err(codec->dev, "Failed to set sysclk %d\n", ret);
731 return ret;
732 }
733
734 return ret;
735}
736
737static int cs35l35_codec_probe(struct snd_soc_codec *codec)
738{
739 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
740 struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
741 struct monitor_cfg *monitor_config = &cs35l35->pdata.mon_cfg;
742 int ret;
743
744 cs35l35->codec = codec;
745
746 /* Set Platform Data */
747 if (cs35l35->pdata.bst_vctl)
748 regmap_update_bits(cs35l35->regmap, CS35L35_BST_CVTR_V_CTL,
749 CS35L35_BST_CTL_MASK,
750 cs35l35->pdata.bst_vctl);
751
752 if (cs35l35->pdata.bst_ipk)
753 regmap_update_bits(cs35l35->regmap, CS35L35_BST_PEAK_I,
754 CS35L35_BST_IPK_MASK,
755 cs35l35->pdata.bst_ipk <<
756 CS35L35_BST_IPK_SHIFT);
757
758 if (cs35l35->pdata.gain_zc)
759 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
760 CS35L35_AMP_GAIN_ZC_MASK,
761 cs35l35->pdata.gain_zc <<
762 CS35L35_AMP_GAIN_ZC_SHIFT);
763
764 if (cs35l35->pdata.aud_channel)
765 regmap_update_bits(cs35l35->regmap,
766 CS35L35_AUDIN_RXLOC_CTL,
767 CS35L35_AUD_IN_LR_MASK,
768 cs35l35->pdata.aud_channel <<
769 CS35L35_AUD_IN_LR_SHIFT);
770
771 if (cs35l35->pdata.stereo) {
772 regmap_update_bits(cs35l35->regmap,
773 CS35L35_ADVIN_RXLOC_CTL,
774 CS35L35_ADV_IN_LR_MASK,
775 cs35l35->pdata.adv_channel <<
776 CS35L35_ADV_IN_LR_SHIFT);
777 if (cs35l35->pdata.shared_bst)
778 regmap_update_bits(cs35l35->regmap, CS35L35_CLASS_H_CTL,
779 CS35L35_CH_STEREO_MASK,
780 1 << CS35L35_CH_STEREO_SHIFT);
781 ret = snd_soc_add_codec_controls(codec, cs35l35_adv_controls,
782 ARRAY_SIZE(cs35l35_adv_controls));
783 if (ret)
784 return ret;
785 }
786
787 if (cs35l35->pdata.sp_drv_str)
788 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
789 CS35L35_SP_DRV_MASK,
790 cs35l35->pdata.sp_drv_str <<
791 CS35L35_SP_DRV_SHIFT);
8d45f2d2
CK		 792 if (cs35l35->pdata.sp_drv_unused)
793 regmap_update_bits(cs35l35->regmap, CS35L35_SP_FMT_CTL3,
794 CS35L35_SP_I2S_DRV_MASK,
795 cs35l35->pdata.sp_drv_unused <<
796 CS35L35_SP_I2S_DRV_SHIFT);
6387f866
BA		 797
798 if (classh->classh_algo_enable) {
799 if (classh->classh_bst_override)
800 regmap_update_bits(cs35l35->regmap,
801 CS35L35_CLASS_H_CTL,
802 CS35L35_CH_BST_OVR_MASK,
803 classh->classh_bst_override <<
804 CS35L35_CH_BST_OVR_SHIFT);
805 if (classh->classh_bst_max_limit)
806 regmap_update_bits(cs35l35->regmap,
807 CS35L35_CLASS_H_CTL,
808 CS35L35_CH_BST_LIM_MASK,
809 classh->classh_bst_max_limit <<
810 CS35L35_CH_BST_LIM_SHIFT);
811 if (classh->classh_mem_depth)
812 regmap_update_bits(cs35l35->regmap,
813 CS35L35_CLASS_H_CTL,
814 CS35L35_CH_MEM_DEPTH_MASK,
815 classh->classh_mem_depth <<
816 CS35L35_CH_MEM_DEPTH_SHIFT);
817 if (classh->classh_headroom)
818 regmap_update_bits(cs35l35->regmap,
819 CS35L35_CLASS_H_HEADRM_CTL,
820 CS35L35_CH_HDRM_CTL_MASK,
821 classh->classh_headroom <<
822 CS35L35_CH_HDRM_CTL_SHIFT);
823 if (classh->classh_release_rate)
824 regmap_update_bits(cs35l35->regmap,
825 CS35L35_CLASS_H_RELEASE_RATE,
826 CS35L35_CH_REL_RATE_MASK,
827 classh->classh_release_rate <<
828 CS35L35_CH_REL_RATE_SHIFT);
829 if (classh->classh_wk_fet_disable)
830 regmap_update_bits(cs35l35->regmap,
831 CS35L35_CLASS_H_FET_DRIVE_CTL,
832 CS35L35_CH_WKFET_DIS_MASK,
833 classh->classh_wk_fet_disable <<
834 CS35L35_CH_WKFET_DIS_SHIFT);
835 if (classh->classh_wk_fet_delay)
836 regmap_update_bits(cs35l35->regmap,
837 CS35L35_CLASS_H_FET_DRIVE_CTL,
838 CS35L35_CH_WKFET_DEL_MASK,
839 classh->classh_wk_fet_delay <<
840 CS35L35_CH_WKFET_DEL_SHIFT);
841 if (classh->classh_wk_fet_thld)
842 regmap_update_bits(cs35l35->regmap,
843 CS35L35_CLASS_H_FET_DRIVE_CTL,
844 CS35L35_CH_WKFET_THLD_MASK,
845 classh->classh_wk_fet_thld <<
846 CS35L35_CH_WKFET_THLD_SHIFT);
847 if (classh->classh_vpch_auto)
848 regmap_update_bits(cs35l35->regmap,
849 CS35L35_CLASS_H_VP_CTL,
850 CS35L35_CH_VP_AUTO_MASK,
851 classh->classh_vpch_auto <<
852 CS35L35_CH_VP_AUTO_SHIFT);
853 if (classh->classh_vpch_rate)
854 regmap_update_bits(cs35l35->regmap,
855 CS35L35_CLASS_H_VP_CTL,
856 CS35L35_CH_VP_RATE_MASK,
857 classh->classh_vpch_rate <<
858 CS35L35_CH_VP_RATE_SHIFT);
859 if (classh->classh_vpch_man)
860 regmap_update_bits(cs35l35->regmap,
861 CS35L35_CLASS_H_VP_CTL,
862 CS35L35_CH_VP_MAN_MASK,
863 classh->classh_vpch_man <<
864 CS35L35_CH_VP_MAN_SHIFT);
865 }
866
867 if (monitor_config->is_present) {
868 if (monitor_config->vmon_specs) {
869 regmap_update_bits(cs35l35->regmap,
870 CS35L35_SPKMON_DEPTH_CTL,
871 CS35L35_VMON_DEPTH_MASK,
872 monitor_config->vmon_dpth <<
873 CS35L35_VMON_DEPTH_SHIFT);
874 regmap_update_bits(cs35l35->regmap,
875 CS35L35_VMON_TXLOC_CTL,
876 CS35L35_MON_TXLOC_MASK,
877 monitor_config->vmon_loc <<
878 CS35L35_MON_TXLOC_SHIFT);
879 regmap_update_bits(cs35l35->regmap,
880 CS35L35_VMON_TXLOC_CTL,
881 CS35L35_MON_FRM_MASK,
882 monitor_config->vmon_frm <<
883 CS35L35_MON_FRM_SHIFT);
884 }
885 if (monitor_config->imon_specs) {
886 regmap_update_bits(cs35l35->regmap,
887 CS35L35_SPKMON_DEPTH_CTL,
888 CS35L35_IMON_DEPTH_MASK,
889 monitor_config->imon_dpth <<
890 CS35L35_IMON_DEPTH_SHIFT);
891 regmap_update_bits(cs35l35->regmap,
892 CS35L35_IMON_TXLOC_CTL,
893 CS35L35_MON_TXLOC_MASK,
894 monitor_config->imon_loc <<
895 CS35L35_MON_TXLOC_SHIFT);
896 regmap_update_bits(cs35l35->regmap,
897 CS35L35_IMON_TXLOC_CTL,
898 CS35L35_MON_FRM_MASK,
899 monitor_config->imon_frm <<
900 CS35L35_MON_FRM_SHIFT);
901 }
902 if (monitor_config->vpmon_specs) {
903 regmap_update_bits(cs35l35->regmap,
904 CS35L35_SUPMON_DEPTH_CTL,
905 CS35L35_VPMON_DEPTH_MASK,
906 monitor_config->vpmon_dpth <<
907 CS35L35_VPMON_DEPTH_SHIFT);
908 regmap_update_bits(cs35l35->regmap,
909 CS35L35_VPMON_TXLOC_CTL,
910 CS35L35_MON_TXLOC_MASK,
911 monitor_config->vpmon_loc <<
912 CS35L35_MON_TXLOC_SHIFT);
913 regmap_update_bits(cs35l35->regmap,
914 CS35L35_VPMON_TXLOC_CTL,
915 CS35L35_MON_FRM_MASK,
916 monitor_config->vpmon_frm <<
917 CS35L35_MON_FRM_SHIFT);
918 }
919 if (monitor_config->vbstmon_specs) {
920 regmap_update_bits(cs35l35->regmap,
921 CS35L35_SUPMON_DEPTH_CTL,
922 CS35L35_VBSTMON_DEPTH_MASK,
923 monitor_config->vpmon_dpth <<
924 CS35L35_VBSTMON_DEPTH_SHIFT);
925 regmap_update_bits(cs35l35->regmap,
926 CS35L35_VBSTMON_TXLOC_CTL,
927 CS35L35_MON_TXLOC_MASK,
928 monitor_config->vbstmon_loc <<
929 CS35L35_MON_TXLOC_SHIFT);
930 regmap_update_bits(cs35l35->regmap,
931 CS35L35_VBSTMON_TXLOC_CTL,
932 CS35L35_MON_FRM_MASK,
933 monitor_config->vbstmon_frm <<
934 CS35L35_MON_FRM_SHIFT);
935 }
936 if (monitor_config->vpbrstat_specs) {
937 regmap_update_bits(cs35l35->regmap,
938 CS35L35_SUPMON_DEPTH_CTL,
939 CS35L35_VPBRSTAT_DEPTH_MASK,
940 monitor_config->vpbrstat_dpth <<
941 CS35L35_VPBRSTAT_DEPTH_SHIFT);
942 regmap_update_bits(cs35l35->regmap,
943 CS35L35_VPBR_STATUS_TXLOC_CTL,
944 CS35L35_MON_TXLOC_MASK,
945 monitor_config->vpbrstat_loc <<
946 CS35L35_MON_TXLOC_SHIFT);
947 regmap_update_bits(cs35l35->regmap,
948 CS35L35_VPBR_STATUS_TXLOC_CTL,
949 CS35L35_MON_FRM_MASK,
950 monitor_config->vpbrstat_frm <<
951 CS35L35_MON_FRM_SHIFT);
952 }
953 if (monitor_config->zerofill_specs) {
954 regmap_update_bits(cs35l35->regmap,
955 CS35L35_SUPMON_DEPTH_CTL,
956 CS35L35_ZEROFILL_DEPTH_MASK,
957 monitor_config->zerofill_dpth <<
958 CS35L35_ZEROFILL_DEPTH_SHIFT);
959 regmap_update_bits(cs35l35->regmap,
960 CS35L35_ZERO_FILL_LOC_CTL,
961 CS35L35_MON_TXLOC_MASK,
962 monitor_config->zerofill_loc <<
963 CS35L35_MON_TXLOC_SHIFT);
964 regmap_update_bits(cs35l35->regmap,
965 CS35L35_ZERO_FILL_LOC_CTL,
966 CS35L35_MON_FRM_MASK,
967 monitor_config->zerofill_frm <<
968 CS35L35_MON_FRM_SHIFT);
969 }
970 }
971
bfe41c67 972 return 0;
6387f866
BA		 973}
974
975static struct snd_soc_codec_driver soc_codec_dev_cs35l35 = {
976 .probe = cs35l35_codec_probe,
977 .set_sysclk = cs35l35_codec_set_sysclk,
978 .component_driver = {
979 .dapm_widgets = cs35l35_dapm_widgets,
980 .num_dapm_widgets = ARRAY_SIZE(cs35l35_dapm_widgets),
981
982 .dapm_routes = cs35l35_audio_map,
983 .num_dapm_routes = ARRAY_SIZE(cs35l35_audio_map),
984
985 .controls = cs35l35_aud_controls,
986 .num_controls = ARRAY_SIZE(cs35l35_aud_controls),
987 },
988
989};
990
991static struct regmap_config cs35l35_regmap = {
992 .reg_bits = 8,
993 .val_bits = 8,
994
995 .max_register = CS35L35_MAX_REGISTER,
996 .reg_defaults = cs35l35_reg,
997 .num_reg_defaults = ARRAY_SIZE(cs35l35_reg),
998 .volatile_reg = cs35l35_volatile_register,
999 .readable_reg = cs35l35_readable_register,
1000 .precious_reg = cs35l35_precious_register,
1001 .cache_type = REGCACHE_RBTREE,
1002};
1003
1004static irqreturn_t cs35l35_irq(int irq, void *data)
1005{
1006 struct cs35l35_private *cs35l35 = data;
1007 struct snd_soc_codec *codec = cs35l35->codec;
1008 unsigned int sticky1, sticky2, sticky3, sticky4;
1009 unsigned int mask1, mask2, mask3, mask4, current1;
1010
1011 /* ack the irq by reading all status registers */
1012 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_4, &sticky4);
1013 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_3, &sticky3);
1014 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_2, &sticky2);
1015 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_1, &sticky1);
1016
1017 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_4, &mask4);
1018 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_3, &mask3);
1019 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_2, &mask2);
1020 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_1, &mask1);
1021
1022 /* Check to see if unmasked bits are active */
1023 if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3)
1024 && !(sticky4 & ~mask4))
1025 return IRQ_NONE;
1026
1027 if (sticky2 & CS35L35_PDN_DONE)
1028 complete(&cs35l35->pdn_done);
1029
1030 /* read the current values */
1031 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_1, &current1);
1032
1033 /* handle the interrupts */
1034 if (sticky1 & CS35L35_CAL_ERR) {
1035 dev_crit(codec->dev, "Calibration Error\n");
1036
1037 /* error is no longer asserted; safe to reset */
1038 if (!(current1 & CS35L35_CAL_ERR)) {
1039 pr_debug("%s : Cal error release\n", __func__);
1040 regmap_update_bits(cs35l35->regmap,
1041 CS35L35_PROT_RELEASE_CTL,
1042 CS35L35_CAL_ERR_RLS, 0);
1043 regmap_update_bits(cs35l35->regmap,
1044 CS35L35_PROT_RELEASE_CTL,
1045 CS35L35_CAL_ERR_RLS,
1046 CS35L35_CAL_ERR_RLS);
1047 regmap_update_bits(cs35l35->regmap,
1048 CS35L35_PROT_RELEASE_CTL,
1049 CS35L35_CAL_ERR_RLS, 0);
1050 }
1051 }
1052
1053 if (sticky1 & CS35L35_AMP_SHORT) {
1054 dev_crit(codec->dev, "AMP Short Error\n");
1055 /* error is no longer asserted; safe to reset */
1056 if (!(current1 & CS35L35_AMP_SHORT)) {
1057 dev_dbg(codec->dev, "Amp short error release\n");
1058 regmap_update_bits(cs35l35->regmap,
1059 CS35L35_PROT_RELEASE_CTL,
1060 CS35L35_SHORT_RLS, 0);
1061 regmap_update_bits(cs35l35->regmap,
1062 CS35L35_PROT_RELEASE_CTL,
1063 CS35L35_SHORT_RLS,
1064 CS35L35_SHORT_RLS);
1065 regmap_update_bits(cs35l35->regmap,
1066 CS35L35_PROT_RELEASE_CTL,
1067 CS35L35_SHORT_RLS, 0);
1068 }
1069 }
1070
1071 if (sticky1 & CS35L35_OTW) {
1072 dev_warn(codec->dev, "Over temperature warning\n");
1073
1074 /* error is no longer asserted; safe to reset */
1075 if (!(current1 & CS35L35_OTW)) {
1076 dev_dbg(codec->dev, "Over temperature warn release\n");
1077 regmap_update_bits(cs35l35->regmap,
1078 CS35L35_PROT_RELEASE_CTL,
1079 CS35L35_OTW_RLS, 0);
1080 regmap_update_bits(cs35l35->regmap,
1081 CS35L35_PROT_RELEASE_CTL,
1082 CS35L35_OTW_RLS,
1083 CS35L35_OTW_RLS);
1084 regmap_update_bits(cs35l35->regmap,
1085 CS35L35_PROT_RELEASE_CTL,
1086 CS35L35_OTW_RLS, 0);
1087 }
1088 }
1089
1090 if (sticky1 & CS35L35_OTE) {
1091 dev_crit(codec->dev, "Over temperature error\n");
1092 /* error is no longer asserted; safe to reset */
1093 if (!(current1 & CS35L35_OTE)) {
1094 dev_dbg(codec->dev, "Over temperature error release\n");
1095 regmap_update_bits(cs35l35->regmap,
1096 CS35L35_PROT_RELEASE_CTL,
1097 CS35L35_OTE_RLS, 0);
1098 regmap_update_bits(cs35l35->regmap,
1099 CS35L35_PROT_RELEASE_CTL,
1100 CS35L35_OTE_RLS,
1101 CS35L35_OTE_RLS);
1102 regmap_update_bits(cs35l35->regmap,
1103 CS35L35_PROT_RELEASE_CTL,
1104 CS35L35_OTE_RLS, 0);
1105 }
1106 }
1107
1108 if (sticky3 & CS35L35_BST_HIGH) {
1109 dev_crit(codec->dev, "VBST error: powering off!\n");
1110 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1111 CS35L35_PDN_AMP, CS35L35_PDN_AMP);
1112 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
1113 CS35L35_PDN_ALL, CS35L35_PDN_ALL);
1114 }
1115
1116 if (sticky3 & CS35L35_LBST_SHORT) {
1117 dev_crit(codec->dev, "LBST error: powering off!\n");
1118 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1119 CS35L35_PDN_AMP, CS35L35_PDN_AMP);
1120 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
1121 CS35L35_PDN_ALL, CS35L35_PDN_ALL);
1122 }
1123
1124 if (sticky2 & CS35L35_VPBR_ERR)
1125 dev_dbg(codec->dev, "Error: Reactive Brownout\n");
1126
1127 if (sticky4 & CS35L35_VMON_OVFL)
1128 dev_dbg(codec->dev, "Error: VMON overflow\n");
1129
1130 if (sticky4 & CS35L35_IMON_OVFL)
1131 dev_dbg(codec->dev, "Error: IMON overflow\n");
1132
1133 return IRQ_HANDLED;
1134}
1135
1136
1137static int cs35l35_handle_of_data(struct i2c_client *i2c_client,
1138 struct cs35l35_platform_data *pdata)
1139{
1140 struct device_node *np = i2c_client->dev.of_node;
1141 struct device_node *classh, *signal_format;
1142 struct classh_cfg *classh_config = &pdata->classh_algo;
1143 struct monitor_cfg *monitor_config = &pdata->mon_cfg;
1144 unsigned int val32 = 0;
1145 u8 monitor_array[3];
1146 int ret = 0;
1147
1148 if (!np)
1149 return 0;
1150
1151 pdata->bst_pdn_fet_on = of_property_read_bool(np,
1152 "cirrus,boost-pdn-fet-on");
1153
1154 ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val32);
1155 if (ret >= 0) {
1156 if (val32 < 2600 || val32 > 9000) {
1157 dev_err(&i2c_client->dev,
1158 "Invalid Boost Voltage %d mV\n", val32);
1159 return -EINVAL;
1160 }
1161 pdata->bst_vctl = ((val32 - 2600) / 100) + 1;
1162 }
1163
1164 ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val32);
1165 if (ret >= 0) {
1166 if (val32 < 1680 || val32 > 4480) {
1167 dev_err(&i2c_client->dev,
1168 "Invalid Boost Peak Current %u mA\n", val32);
1169 return -EINVAL;
1170 }
1171
1172 pdata->bst_ipk = (val32 - 1680) / 110;
1173 }
1174
1175 if (of_property_read_u32(np, "cirrus,sp-drv-strength", &val32) >= 0)
1176 pdata->sp_drv_str = val32;
8d45f2d2
CK		 1177 if (of_property_read_u32(np, "cirrus,sp-drv-unused", &val32) >= 0)
1178 pdata->sp_drv_unused = val32 | CS35L35_VALID_PDATA;
6387f866
BA		 1179
1180 pdata->stereo = of_property_read_bool(np, "cirrus,stereo-config");
1181
1182 if (pdata->stereo) {
1183 ret = of_property_read_u32(np, "cirrus,audio-channel", &val32);
1184 if (ret >= 0)
1185 pdata->aud_channel = val32;
1186
1187 ret = of_property_read_u32(np, "cirrus,advisory-channel",
1188 &val32);
1189 if (ret >= 0)
1190 pdata->adv_channel = val32;
1191
1192 pdata->shared_bst = of_property_read_bool(np,
1193 "cirrus,shared-boost");
1194 }
1195
1196 pdata->gain_zc = of_property_read_bool(np, "cirrus,amp-gain-zc");
1197
1198 classh = of_get_child_by_name(np, "cirrus,classh-internal-algo");
1199 classh_config->classh_algo_enable = classh ? true : false;
1200
1201 if (classh_config->classh_algo_enable) {
1202 classh_config->classh_bst_override =
1203 of_property_read_bool(np, "cirrus,classh-bst-overide");
1204
1205 ret = of_property_read_u32(classh,
1206 "cirrus,classh-bst-max-limit",
1207 &val32);
1208 if (ret >= 0) {
1209 val32 |= CS35L35_VALID_PDATA;
1210 classh_config->classh_bst_max_limit = val32;
1211 }
1212
1213 ret = of_property_read_u32(classh,
1214 "cirrus,classh-bst-max-limit",
1215 &val32);
1216 if (ret >= 0) {
1217 val32 |= CS35L35_VALID_PDATA;
1218 classh_config->classh_bst_max_limit = val32;
1219 }
1220
1221 ret = of_property_read_u32(classh, "cirrus,classh-mem-depth",
1222 &val32);
1223 if (ret >= 0) {
1224 val32 |= CS35L35_VALID_PDATA;
1225 classh_config->classh_mem_depth = val32;
1226 }
1227
1228 ret = of_property_read_u32(classh, "cirrus,classh-release-rate",
1229 &val32);
1230 if (ret >= 0)
1231 classh_config->classh_release_rate = val32;
1232
1233 ret = of_property_read_u32(classh, "cirrus,classh-headroom",
1234 &val32);
1235 if (ret >= 0) {
1236 val32 |= CS35L35_VALID_PDATA;
1237 classh_config->classh_headroom = val32;
1238 }
1239
1240 ret = of_property_read_u32(classh,
1241 "cirrus,classh-wk-fet-disable",
1242 &val32);
1243 if (ret >= 0)
1244 classh_config->classh_wk_fet_disable = val32;
1245
1246 ret = of_property_read_u32(classh, "cirrus,classh-wk-fet-delay",
1247 &val32);
1248 if (ret >= 0) {
1249 val32 |= CS35L35_VALID_PDATA;
1250 classh_config->classh_wk_fet_delay = val32;
1251 }
1252
1253 ret = of_property_read_u32(classh, "cirrus,classh-wk-fet-thld",
1254 &val32);
1255 if (ret >= 0)
1256 classh_config->classh_wk_fet_thld = val32;
1257
1258 ret = of_property_read_u32(classh, "cirrus,classh-vpch-auto",
1259 &val32);
1260 if (ret >= 0) {
1261 val32 |= CS35L35_VALID_PDATA;
1262 classh_config->classh_vpch_auto = val32;
1263 }
1264
1265 ret = of_property_read_u32(classh, "cirrus,classh-vpch-rate",
1266 &val32);
1267 if (ret >= 0) {
1268 val32 |= CS35L35_VALID_PDATA;
1269 classh_config->classh_vpch_rate = val32;
1270 }
1271
1272 ret = of_property_read_u32(classh, "cirrus,classh-vpch-man",
1273 &val32);
1274 if (ret >= 0)
1275 classh_config->classh_vpch_man = val32;
1276 }
1277 of_node_put(classh);
1278
1279 /* frame depth location */
1280 signal_format = of_get_child_by_name(np, "cirrus,monitor-signal-format");
1281 monitor_config->is_present = signal_format ? true : false;
1282 if (monitor_config->is_present) {
1283 ret = of_property_read_u8_array(signal_format, "cirrus,imon",
1284 monitor_array, ARRAY_SIZE(monitor_array));
1285 if (!ret) {
1286 monitor_config->imon_specs = true;
1287 monitor_config->imon_dpth = monitor_array[0];
1288 monitor_config->imon_loc = monitor_array[1];
1289 monitor_config->imon_frm = monitor_array[2];
1290 }
1291 ret = of_property_read_u8_array(signal_format, "cirrus,vmon",
1292 monitor_array, ARRAY_SIZE(monitor_array));
1293 if (!ret) {
1294 monitor_config->vmon_specs = true;
1295 monitor_config->vmon_dpth = monitor_array[0];
1296 monitor_config->vmon_loc = monitor_array[1];
1297 monitor_config->vmon_frm = monitor_array[2];
1298 }
1299 ret = of_property_read_u8_array(signal_format, "cirrus,vpmon",
1300 monitor_array, ARRAY_SIZE(monitor_array));
1301 if (!ret) {
1302 monitor_config->vpmon_specs = true;
1303 monitor_config->vpmon_dpth = monitor_array[0];
1304 monitor_config->vpmon_loc = monitor_array[1];
1305 monitor_config->vpmon_frm = monitor_array[2];
1306 }
1307 ret = of_property_read_u8_array(signal_format, "cirrus,vbstmon",
1308 monitor_array, ARRAY_SIZE(monitor_array));
1309 if (!ret) {
1310 monitor_config->vbstmon_specs = true;
1311 monitor_config->vbstmon_dpth = monitor_array[0];
1312 monitor_config->vbstmon_loc = monitor_array[1];
1313 monitor_config->vbstmon_frm = monitor_array[2];
1314 }
1315 ret = of_property_read_u8_array(signal_format, "cirrus,vpbrstat",
1316 monitor_array, ARRAY_SIZE(monitor_array));
1317 if (!ret) {
1318 monitor_config->vpbrstat_specs = true;
1319 monitor_config->vpbrstat_dpth = monitor_array[0];
1320 monitor_config->vpbrstat_loc = monitor_array[1];
1321 monitor_config->vpbrstat_frm = monitor_array[2];
1322 }
1323 ret = of_property_read_u8_array(signal_format, "cirrus,zerofill",
1324 monitor_array, ARRAY_SIZE(monitor_array));
1325 if (!ret) {
1326 monitor_config->zerofill_specs = true;
1327 monitor_config->zerofill_dpth = monitor_array[0];
1328 monitor_config->zerofill_loc = monitor_array[1];
1329 monitor_config->zerofill_frm = monitor_array[2];
1330 }
1331 }
1332 of_node_put(signal_format);
1333
1334 return 0;
1335}
1336
1337/* Errata Rev A0 */
1338static const struct reg_sequence cs35l35_errata_patch[] = {
1339
1340 { 0x7F, 0x99 },
1341 { 0x00, 0x99 },
1342 { 0x52, 0x22 },
1343 { 0x04, 0x14 },
1344 { 0x6D, 0x44 },
1345 { 0x24, 0x10 },
1346 { 0x58, 0xC4 },
1347 { 0x00, 0x98 },
1348 { 0x18, 0x08 },
1349 { 0x00, 0x00 },
1350 { 0x7F, 0x00 },
1351};
1352
1353static int cs35l35_i2c_probe(struct i2c_client *i2c_client,
1354 const struct i2c_device_id *id)
1355{
1356 struct cs35l35_private *cs35l35;
1f758cd9
CK		 1357 struct device *dev = &i2c_client->dev;
1358 struct cs35l35_platform_data *pdata = dev_get_platdata(dev);
6387f866
BA		 1359 int i;
1360 int ret;
1361 unsigned int devid = 0;
1362 unsigned int reg;
1363
1f758cd9 1364 cs35l35 = devm_kzalloc(dev, sizeof(struct cs35l35_private), GFP_KERNEL);
6387f866
BA		 1365 if (!cs35l35)
1366 return -ENOMEM;
1367
1368 i2c_set_clientdata(i2c_client, cs35l35);
1369 cs35l35->regmap = devm_regmap_init_i2c(i2c_client, &cs35l35_regmap);
1370 if (IS_ERR(cs35l35->regmap)) {
1371 ret = PTR_ERR(cs35l35->regmap);
1f758cd9 1372 dev_err(dev, "regmap_init() failed: %d\n", ret);
6387f866
BA		 1373 goto err;
1374 }
1375
1376 for (i = 0; i < ARRAY_SIZE(cs35l35_supplies); i++)
1377 cs35l35->supplies[i].supply = cs35l35_supplies[i];
03ff570c
CIK		 1378
1379 cs35l35->num_supplies = ARRAY_SIZE(cs35l35_supplies);
6387f866 1380
1f758cd9
CK		 1381 ret = devm_regulator_bulk_get(dev, cs35l35->num_supplies,
1382 cs35l35->supplies);
6387f866 1383 if (ret != 0) {
1f758cd9 1384 dev_err(dev, "Failed to request core supplies: %d\n", ret);
6387f866
BA		 1385 return ret;
1386 }
1387
1388 if (pdata) {
1389 cs35l35->pdata = *pdata;
1390 } else {
1f758cd9
CK		 1391 pdata = devm_kzalloc(dev, sizeof(struct cs35l35_platform_data),
1392 GFP_KERNEL);
6387f866
BA		 1393 if (!pdata)
1394 return -ENOMEM;
1395 if (i2c_client->dev.of_node) {
1396 ret = cs35l35_handle_of_data(i2c_client, pdata);
1397 if (ret != 0)
1398 return ret;
1399
1400 }
1401 cs35l35->pdata = *pdata;
1402 }
1403
1404 ret = regulator_bulk_enable(cs35l35->num_supplies,
1405 cs35l35->supplies);
1406 if (ret != 0) {
1f758cd9 1407 dev_err(dev, "Failed to enable core supplies: %d\n", ret);
6387f866
BA		 1408 return ret;
1409 }
1410
1411 /* returning NULL can be valid if in stereo mode */
1f758cd9
CK		 1412 cs35l35->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1413 GPIOD_OUT_LOW);
6387f866
BA		 1414 if (IS_ERR(cs35l35->reset_gpio)) {
1415 ret = PTR_ERR(cs35l35->reset_gpio);
1416 if (ret == -EBUSY) {
1f758cd9 1417 dev_info(dev,
6387f866
BA		 1418 "Reset line busy, assuming shared reset\n");
1419 cs35l35->reset_gpio = NULL;
1420 } else {
1f758cd9 1421 dev_err(dev, "Failed to get reset GPIO: %d\n", ret);
6387f866
BA		 1422 goto err;
1423 }
1424 }
1425
1426 gpiod_set_value_cansleep(cs35l35->reset_gpio, 1);
1427
1428 init_completion(&cs35l35->pdn_done);
1429
1f758cd9 1430 ret = devm_request_threaded_irq(dev, i2c_client->irq, NULL, cs35l35_irq,
bf5043d6
CK		 1431 IRQF_ONESHOT | IRQF_TRIGGER_LOW |
1432 IRQF_SHARED, "cs35l35", cs35l35);
6387f866 1433 if (ret != 0) {
1f758cd9 1434 dev_err(dev, "Failed to request IRQ: %d\n", ret);
6387f866
BA		 1435 goto err;
1436 }
1437 /* initialize codec */
1438 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_AB, &reg);
1439
1440 devid = (reg & 0xFF) << 12;
1441 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_CD, &reg);
1442 devid |= (reg & 0xFF) << 4;
1443 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_E, &reg);
1444 devid |= (reg & 0xF0) >> 4;
1445
1446 if (devid != CS35L35_CHIP_ID) {
1f758cd9 1447 dev_err(dev, "CS35L35 Device ID (%X). Expected ID %X\n",
6387f866
BA		 1448 devid, CS35L35_CHIP_ID);
1449 ret = -ENODEV;
1450 goto err;
1451 }
1452
1453 ret = regmap_read(cs35l35->regmap, CS35L35_REV_ID, &reg);
1454 if (ret < 0) {
1f758cd9 1455 dev_err(dev, "Get Revision ID failed: %d\n", ret);
6387f866
BA		 1456 goto err;
1457 }
1458
1459 ret = regmap_register_patch(cs35l35->regmap, cs35l35_errata_patch,
1460 ARRAY_SIZE(cs35l35_errata_patch));
1461 if (ret < 0) {
1f758cd9 1462 dev_err(dev, "Failed to apply errata patch: %d\n", ret);
6387f866
BA		 1463 goto err;
1464 }
1465
1f758cd9 1466 dev_info(dev, "Cirrus Logic CS35L35 (%x), Revision: %02X\n",
82875163 1467 devid, reg & 0xFF);
6387f866
BA		 1468
1469 /* Set the INT Masks for critical errors */
1470 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_1,
1471 CS35L35_INT1_CRIT_MASK);
1472 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_2,
1473 CS35L35_INT2_CRIT_MASK);
1474 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_3,
1475 CS35L35_INT3_CRIT_MASK);
1476 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_4,
1477 CS35L35_INT4_CRIT_MASK);
1478
1479 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1480 CS35L35_PWR2_PDN_MASK,
1481 CS35L35_PWR2_PDN_MASK);
1482
1483 if (cs35l35->pdata.bst_pdn_fet_on)
1484 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1485 CS35L35_PDN_BST_MASK,
1486 1 << CS35L35_PDN_BST_FETON_SHIFT);
1487 else
1488 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
1489 CS35L35_PDN_BST_MASK,
1490 1 << CS35L35_PDN_BST_FETOFF_SHIFT);
1491
1492 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL3,
1493 CS35L35_PWR3_PDN_MASK,
1494 CS35L35_PWR3_PDN_MASK);
1495
1496 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
1497 CS35L35_AMP_MUTE_MASK, 1 << CS35L35_AMP_MUTE_SHIFT);
1498
1f758cd9
CK		 1499 ret = snd_soc_register_codec(dev, &soc_codec_dev_cs35l35, cs35l35_dai,
1500 ARRAY_SIZE(cs35l35_dai));
6387f866 1501 if (ret < 0) {
1f758cd9 1502 dev_err(dev, "Failed to register codec: %d\n", ret);
6387f866
BA		 1503 goto err;
1504 }
1505
1bb06ada
CK		 1506 return 0;
1507
6387f866
BA		 1508err:
1509 regulator_bulk_disable(cs35l35->num_supplies,
1510 cs35l35->supplies);
1511 gpiod_set_value_cansleep(cs35l35->reset_gpio, 0);
1512
1513 return ret;
1514}
1515
1516static int cs35l35_i2c_remove(struct i2c_client *client)
1517{
1518 snd_soc_unregister_codec(&client->dev);
1519 return 0;
1520}
1521
1522static const struct of_device_id cs35l35_of_match[] = {
1523 {.compatible = "cirrus,cs35l35"},
1524 {},
1525};
1526MODULE_DEVICE_TABLE(of, cs35l35_of_match);
1527
1528static const struct i2c_device_id cs35l35_id[] = {
1529 {"cs35l35", 0},
1530 {}
1531};
1532
1533MODULE_DEVICE_TABLE(i2c, cs35l35_id);
1534
1535static struct i2c_driver cs35l35_i2c_driver = {
1536 .driver = {
1537 .name = "cs35l35",
1538 .of_match_table = cs35l35_of_match,
1539 },
1540 .id_table = cs35l35_id,
1541 .probe = cs35l35_i2c_probe,
1542 .remove = cs35l35_i2c_remove,
1543};
1544
1545module_i2c_driver(cs35l35_i2c_driver);
1546
1547MODULE_DESCRIPTION("ASoC CS35L35 driver");
1548MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1549MODULE_LICENSE("GPL");
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