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82a5a936 PH |
1 | /* |
2 | * max98095.c -- MAX98095 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2011 Maxim Integrated Products | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <sound/core.h> | |
20 | #include <sound/pcm.h> | |
21 | #include <sound/pcm_params.h> | |
22 | #include <sound/soc.h> | |
23 | #include <sound/initval.h> | |
24 | #include <sound/tlv.h> | |
25 | #include <linux/slab.h> | |
26 | #include <asm/div64.h> | |
27 | #include <sound/max98095.h> | |
28 | #include "max98095.h" | |
29 | ||
30 | enum max98095_type { | |
31 | MAX98095, | |
32 | }; | |
33 | ||
34 | struct max98095_cdata { | |
35 | unsigned int rate; | |
36 | unsigned int fmt; | |
dad31ec1 PH |
37 | int eq_sel; |
38 | int bq_sel; | |
82a5a936 PH |
39 | }; |
40 | ||
41 | struct max98095_priv { | |
42 | enum max98095_type devtype; | |
82a5a936 PH |
43 | struct max98095_pdata *pdata; |
44 | unsigned int sysclk; | |
45 | struct max98095_cdata dai[3]; | |
dad31ec1 PH |
46 | const char **eq_texts; |
47 | const char **bq_texts; | |
48 | struct soc_enum eq_enum; | |
49 | struct soc_enum bq_enum; | |
50 | int eq_textcnt; | |
51 | int bq_textcnt; | |
82a5a936 PH |
52 | u8 lin_state; |
53 | unsigned int mic1pre; | |
54 | unsigned int mic2pre; | |
55 | }; | |
56 | ||
57 | static const u8 max98095_reg_def[M98095_REG_CNT] = { | |
58 | 0x00, /* 00 */ | |
59 | 0x00, /* 01 */ | |
60 | 0x00, /* 02 */ | |
61 | 0x00, /* 03 */ | |
62 | 0x00, /* 04 */ | |
63 | 0x00, /* 05 */ | |
64 | 0x00, /* 06 */ | |
65 | 0x00, /* 07 */ | |
66 | 0x00, /* 08 */ | |
67 | 0x00, /* 09 */ | |
68 | 0x00, /* 0A */ | |
69 | 0x00, /* 0B */ | |
70 | 0x00, /* 0C */ | |
71 | 0x00, /* 0D */ | |
72 | 0x00, /* 0E */ | |
73 | 0x00, /* 0F */ | |
74 | 0x00, /* 10 */ | |
75 | 0x00, /* 11 */ | |
76 | 0x00, /* 12 */ | |
77 | 0x00, /* 13 */ | |
78 | 0x00, /* 14 */ | |
79 | 0x00, /* 15 */ | |
80 | 0x00, /* 16 */ | |
81 | 0x00, /* 17 */ | |
82 | 0x00, /* 18 */ | |
83 | 0x00, /* 19 */ | |
84 | 0x00, /* 1A */ | |
85 | 0x00, /* 1B */ | |
86 | 0x00, /* 1C */ | |
87 | 0x00, /* 1D */ | |
88 | 0x00, /* 1E */ | |
89 | 0x00, /* 1F */ | |
90 | 0x00, /* 20 */ | |
91 | 0x00, /* 21 */ | |
92 | 0x00, /* 22 */ | |
93 | 0x00, /* 23 */ | |
94 | 0x00, /* 24 */ | |
95 | 0x00, /* 25 */ | |
96 | 0x00, /* 26 */ | |
97 | 0x00, /* 27 */ | |
98 | 0x00, /* 28 */ | |
99 | 0x00, /* 29 */ | |
100 | 0x00, /* 2A */ | |
101 | 0x00, /* 2B */ | |
102 | 0x00, /* 2C */ | |
103 | 0x00, /* 2D */ | |
104 | 0x00, /* 2E */ | |
105 | 0x00, /* 2F */ | |
106 | 0x00, /* 30 */ | |
107 | 0x00, /* 31 */ | |
108 | 0x00, /* 32 */ | |
109 | 0x00, /* 33 */ | |
110 | 0x00, /* 34 */ | |
111 | 0x00, /* 35 */ | |
112 | 0x00, /* 36 */ | |
113 | 0x00, /* 37 */ | |
114 | 0x00, /* 38 */ | |
115 | 0x00, /* 39 */ | |
116 | 0x00, /* 3A */ | |
117 | 0x00, /* 3B */ | |
118 | 0x00, /* 3C */ | |
119 | 0x00, /* 3D */ | |
120 | 0x00, /* 3E */ | |
121 | 0x00, /* 3F */ | |
122 | 0x00, /* 40 */ | |
123 | 0x00, /* 41 */ | |
124 | 0x00, /* 42 */ | |
125 | 0x00, /* 43 */ | |
126 | 0x00, /* 44 */ | |
127 | 0x00, /* 45 */ | |
128 | 0x00, /* 46 */ | |
129 | 0x00, /* 47 */ | |
130 | 0x00, /* 48 */ | |
131 | 0x00, /* 49 */ | |
132 | 0x00, /* 4A */ | |
133 | 0x00, /* 4B */ | |
134 | 0x00, /* 4C */ | |
135 | 0x00, /* 4D */ | |
136 | 0x00, /* 4E */ | |
137 | 0x00, /* 4F */ | |
138 | 0x00, /* 50 */ | |
139 | 0x00, /* 51 */ | |
140 | 0x00, /* 52 */ | |
141 | 0x00, /* 53 */ | |
142 | 0x00, /* 54 */ | |
143 | 0x00, /* 55 */ | |
144 | 0x00, /* 56 */ | |
145 | 0x00, /* 57 */ | |
146 | 0x00, /* 58 */ | |
147 | 0x00, /* 59 */ | |
148 | 0x00, /* 5A */ | |
149 | 0x00, /* 5B */ | |
150 | 0x00, /* 5C */ | |
151 | 0x00, /* 5D */ | |
152 | 0x00, /* 5E */ | |
153 | 0x00, /* 5F */ | |
154 | 0x00, /* 60 */ | |
155 | 0x00, /* 61 */ | |
156 | 0x00, /* 62 */ | |
157 | 0x00, /* 63 */ | |
158 | 0x00, /* 64 */ | |
159 | 0x00, /* 65 */ | |
160 | 0x00, /* 66 */ | |
161 | 0x00, /* 67 */ | |
162 | 0x00, /* 68 */ | |
163 | 0x00, /* 69 */ | |
164 | 0x00, /* 6A */ | |
165 | 0x00, /* 6B */ | |
166 | 0x00, /* 6C */ | |
167 | 0x00, /* 6D */ | |
168 | 0x00, /* 6E */ | |
169 | 0x00, /* 6F */ | |
170 | 0x00, /* 70 */ | |
171 | 0x00, /* 71 */ | |
172 | 0x00, /* 72 */ | |
173 | 0x00, /* 73 */ | |
174 | 0x00, /* 74 */ | |
175 | 0x00, /* 75 */ | |
176 | 0x00, /* 76 */ | |
177 | 0x00, /* 77 */ | |
178 | 0x00, /* 78 */ | |
179 | 0x00, /* 79 */ | |
180 | 0x00, /* 7A */ | |
181 | 0x00, /* 7B */ | |
182 | 0x00, /* 7C */ | |
183 | 0x00, /* 7D */ | |
184 | 0x00, /* 7E */ | |
185 | 0x00, /* 7F */ | |
186 | 0x00, /* 80 */ | |
187 | 0x00, /* 81 */ | |
188 | 0x00, /* 82 */ | |
189 | 0x00, /* 83 */ | |
190 | 0x00, /* 84 */ | |
191 | 0x00, /* 85 */ | |
192 | 0x00, /* 86 */ | |
193 | 0x00, /* 87 */ | |
194 | 0x00, /* 88 */ | |
195 | 0x00, /* 89 */ | |
196 | 0x00, /* 8A */ | |
197 | 0x00, /* 8B */ | |
198 | 0x00, /* 8C */ | |
199 | 0x00, /* 8D */ | |
200 | 0x00, /* 8E */ | |
201 | 0x00, /* 8F */ | |
202 | 0x00, /* 90 */ | |
203 | 0x00, /* 91 */ | |
204 | 0x30, /* 92 */ | |
205 | 0xF0, /* 93 */ | |
206 | 0x00, /* 94 */ | |
207 | 0x00, /* 95 */ | |
208 | 0x3F, /* 96 */ | |
209 | 0x00, /* 97 */ | |
210 | 0x00, /* 98 */ | |
211 | 0x00, /* 99 */ | |
212 | 0x00, /* 9A */ | |
213 | 0x00, /* 9B */ | |
214 | 0x00, /* 9C */ | |
215 | 0x00, /* 9D */ | |
216 | 0x00, /* 9E */ | |
217 | 0x00, /* 9F */ | |
218 | 0x00, /* A0 */ | |
219 | 0x00, /* A1 */ | |
220 | 0x00, /* A2 */ | |
221 | 0x00, /* A3 */ | |
222 | 0x00, /* A4 */ | |
223 | 0x00, /* A5 */ | |
224 | 0x00, /* A6 */ | |
225 | 0x00, /* A7 */ | |
226 | 0x00, /* A8 */ | |
227 | 0x00, /* A9 */ | |
228 | 0x00, /* AA */ | |
229 | 0x00, /* AB */ | |
230 | 0x00, /* AC */ | |
231 | 0x00, /* AD */ | |
232 | 0x00, /* AE */ | |
233 | 0x00, /* AF */ | |
234 | 0x00, /* B0 */ | |
235 | 0x00, /* B1 */ | |
236 | 0x00, /* B2 */ | |
237 | 0x00, /* B3 */ | |
238 | 0x00, /* B4 */ | |
239 | 0x00, /* B5 */ | |
240 | 0x00, /* B6 */ | |
241 | 0x00, /* B7 */ | |
242 | 0x00, /* B8 */ | |
243 | 0x00, /* B9 */ | |
244 | 0x00, /* BA */ | |
245 | 0x00, /* BB */ | |
246 | 0x00, /* BC */ | |
247 | 0x00, /* BD */ | |
248 | 0x00, /* BE */ | |
249 | 0x00, /* BF */ | |
250 | 0x00, /* C0 */ | |
251 | 0x00, /* C1 */ | |
252 | 0x00, /* C2 */ | |
253 | 0x00, /* C3 */ | |
254 | 0x00, /* C4 */ | |
255 | 0x00, /* C5 */ | |
256 | 0x00, /* C6 */ | |
257 | 0x00, /* C7 */ | |
258 | 0x00, /* C8 */ | |
259 | 0x00, /* C9 */ | |
260 | 0x00, /* CA */ | |
261 | 0x00, /* CB */ | |
262 | 0x00, /* CC */ | |
263 | 0x00, /* CD */ | |
264 | 0x00, /* CE */ | |
265 | 0x00, /* CF */ | |
266 | 0x00, /* D0 */ | |
267 | 0x00, /* D1 */ | |
268 | 0x00, /* D2 */ | |
269 | 0x00, /* D3 */ | |
270 | 0x00, /* D4 */ | |
271 | 0x00, /* D5 */ | |
272 | 0x00, /* D6 */ | |
273 | 0x00, /* D7 */ | |
274 | 0x00, /* D8 */ | |
275 | 0x00, /* D9 */ | |
276 | 0x00, /* DA */ | |
277 | 0x00, /* DB */ | |
278 | 0x00, /* DC */ | |
279 | 0x00, /* DD */ | |
280 | 0x00, /* DE */ | |
281 | 0x00, /* DF */ | |
282 | 0x00, /* E0 */ | |
283 | 0x00, /* E1 */ | |
284 | 0x00, /* E2 */ | |
285 | 0x00, /* E3 */ | |
286 | 0x00, /* E4 */ | |
287 | 0x00, /* E5 */ | |
288 | 0x00, /* E6 */ | |
289 | 0x00, /* E7 */ | |
290 | 0x00, /* E8 */ | |
291 | 0x00, /* E9 */ | |
292 | 0x00, /* EA */ | |
293 | 0x00, /* EB */ | |
294 | 0x00, /* EC */ | |
295 | 0x00, /* ED */ | |
296 | 0x00, /* EE */ | |
297 | 0x00, /* EF */ | |
298 | 0x00, /* F0 */ | |
299 | 0x00, /* F1 */ | |
300 | 0x00, /* F2 */ | |
301 | 0x00, /* F3 */ | |
302 | 0x00, /* F4 */ | |
303 | 0x00, /* F5 */ | |
304 | 0x00, /* F6 */ | |
305 | 0x00, /* F7 */ | |
306 | 0x00, /* F8 */ | |
307 | 0x00, /* F9 */ | |
308 | 0x00, /* FA */ | |
309 | 0x00, /* FB */ | |
310 | 0x00, /* FC */ | |
311 | 0x00, /* FD */ | |
312 | 0x00, /* FE */ | |
313 | 0x00, /* FF */ | |
314 | }; | |
315 | ||
316 | static struct { | |
317 | int readable; | |
318 | int writable; | |
319 | } max98095_access[M98095_REG_CNT] = { | |
320 | { 0x00, 0x00 }, /* 00 */ | |
321 | { 0xFF, 0x00 }, /* 01 */ | |
322 | { 0xFF, 0x00 }, /* 02 */ | |
323 | { 0xFF, 0x00 }, /* 03 */ | |
324 | { 0xFF, 0x00 }, /* 04 */ | |
325 | { 0xFF, 0x00 }, /* 05 */ | |
326 | { 0xFF, 0x00 }, /* 06 */ | |
327 | { 0xFF, 0x00 }, /* 07 */ | |
328 | { 0xFF, 0x00 }, /* 08 */ | |
329 | { 0xFF, 0x00 }, /* 09 */ | |
330 | { 0xFF, 0x00 }, /* 0A */ | |
331 | { 0xFF, 0x00 }, /* 0B */ | |
332 | { 0xFF, 0x00 }, /* 0C */ | |
333 | { 0xFF, 0x00 }, /* 0D */ | |
334 | { 0xFF, 0x00 }, /* 0E */ | |
335 | { 0xFF, 0x9F }, /* 0F */ | |
336 | { 0xFF, 0xFF }, /* 10 */ | |
337 | { 0xFF, 0xFF }, /* 11 */ | |
338 | { 0xFF, 0xFF }, /* 12 */ | |
339 | { 0xFF, 0xFF }, /* 13 */ | |
340 | { 0xFF, 0xFF }, /* 14 */ | |
341 | { 0xFF, 0xFF }, /* 15 */ | |
342 | { 0xFF, 0xFF }, /* 16 */ | |
343 | { 0xFF, 0xFF }, /* 17 */ | |
344 | { 0xFF, 0xFF }, /* 18 */ | |
345 | { 0xFF, 0xFF }, /* 19 */ | |
346 | { 0xFF, 0xFF }, /* 1A */ | |
347 | { 0xFF, 0xFF }, /* 1B */ | |
348 | { 0xFF, 0xFF }, /* 1C */ | |
349 | { 0xFF, 0xFF }, /* 1D */ | |
350 | { 0xFF, 0x77 }, /* 1E */ | |
351 | { 0xFF, 0x77 }, /* 1F */ | |
352 | { 0xFF, 0x77 }, /* 20 */ | |
353 | { 0xFF, 0x77 }, /* 21 */ | |
354 | { 0xFF, 0x77 }, /* 22 */ | |
355 | { 0xFF, 0x77 }, /* 23 */ | |
356 | { 0xFF, 0xFF }, /* 24 */ | |
357 | { 0xFF, 0x7F }, /* 25 */ | |
358 | { 0xFF, 0x31 }, /* 26 */ | |
359 | { 0xFF, 0xFF }, /* 27 */ | |
360 | { 0xFF, 0xFF }, /* 28 */ | |
361 | { 0xFF, 0xFF }, /* 29 */ | |
362 | { 0xFF, 0xF7 }, /* 2A */ | |
363 | { 0xFF, 0x2F }, /* 2B */ | |
364 | { 0xFF, 0xEF }, /* 2C */ | |
365 | { 0xFF, 0xFF }, /* 2D */ | |
366 | { 0xFF, 0xFF }, /* 2E */ | |
367 | { 0xFF, 0xFF }, /* 2F */ | |
368 | { 0xFF, 0xFF }, /* 30 */ | |
369 | { 0xFF, 0xFF }, /* 31 */ | |
370 | { 0xFF, 0xFF }, /* 32 */ | |
371 | { 0xFF, 0xFF }, /* 33 */ | |
372 | { 0xFF, 0xF7 }, /* 34 */ | |
373 | { 0xFF, 0x2F }, /* 35 */ | |
374 | { 0xFF, 0xCF }, /* 36 */ | |
375 | { 0xFF, 0xFF }, /* 37 */ | |
376 | { 0xFF, 0xFF }, /* 38 */ | |
377 | { 0xFF, 0xFF }, /* 39 */ | |
378 | { 0xFF, 0xFF }, /* 3A */ | |
379 | { 0xFF, 0xFF }, /* 3B */ | |
380 | { 0xFF, 0xFF }, /* 3C */ | |
381 | { 0xFF, 0xFF }, /* 3D */ | |
382 | { 0xFF, 0xF7 }, /* 3E */ | |
383 | { 0xFF, 0x2F }, /* 3F */ | |
384 | { 0xFF, 0xCF }, /* 40 */ | |
385 | { 0xFF, 0xFF }, /* 41 */ | |
386 | { 0xFF, 0x77 }, /* 42 */ | |
387 | { 0xFF, 0xFF }, /* 43 */ | |
388 | { 0xFF, 0xFF }, /* 44 */ | |
389 | { 0xFF, 0xFF }, /* 45 */ | |
390 | { 0xFF, 0xFF }, /* 46 */ | |
391 | { 0xFF, 0xFF }, /* 47 */ | |
392 | { 0xFF, 0xFF }, /* 48 */ | |
393 | { 0xFF, 0x0F }, /* 49 */ | |
394 | { 0xFF, 0xFF }, /* 4A */ | |
395 | { 0xFF, 0xFF }, /* 4B */ | |
396 | { 0xFF, 0x3F }, /* 4C */ | |
397 | { 0xFF, 0x3F }, /* 4D */ | |
398 | { 0xFF, 0x3F }, /* 4E */ | |
399 | { 0xFF, 0xFF }, /* 4F */ | |
400 | { 0xFF, 0x7F }, /* 50 */ | |
401 | { 0xFF, 0x7F }, /* 51 */ | |
402 | { 0xFF, 0x0F }, /* 52 */ | |
403 | { 0xFF, 0x3F }, /* 53 */ | |
404 | { 0xFF, 0x3F }, /* 54 */ | |
405 | { 0xFF, 0x3F }, /* 55 */ | |
406 | { 0xFF, 0xFF }, /* 56 */ | |
407 | { 0xFF, 0xFF }, /* 57 */ | |
408 | { 0xFF, 0xBF }, /* 58 */ | |
409 | { 0xFF, 0x1F }, /* 59 */ | |
410 | { 0xFF, 0xBF }, /* 5A */ | |
411 | { 0xFF, 0x1F }, /* 5B */ | |
412 | { 0xFF, 0xBF }, /* 5C */ | |
413 | { 0xFF, 0x3F }, /* 5D */ | |
414 | { 0xFF, 0x3F }, /* 5E */ | |
415 | { 0xFF, 0x7F }, /* 5F */ | |
416 | { 0xFF, 0x7F }, /* 60 */ | |
417 | { 0xFF, 0x47 }, /* 61 */ | |
418 | { 0xFF, 0x9F }, /* 62 */ | |
419 | { 0xFF, 0x9F }, /* 63 */ | |
420 | { 0xFF, 0x9F }, /* 64 */ | |
421 | { 0xFF, 0x9F }, /* 65 */ | |
422 | { 0xFF, 0x9F }, /* 66 */ | |
423 | { 0xFF, 0xBF }, /* 67 */ | |
424 | { 0xFF, 0xBF }, /* 68 */ | |
425 | { 0xFF, 0xFF }, /* 69 */ | |
426 | { 0xFF, 0xFF }, /* 6A */ | |
427 | { 0xFF, 0x7F }, /* 6B */ | |
428 | { 0xFF, 0xF7 }, /* 6C */ | |
429 | { 0xFF, 0xFF }, /* 6D */ | |
430 | { 0xFF, 0xFF }, /* 6E */ | |
431 | { 0xFF, 0x1F }, /* 6F */ | |
432 | { 0xFF, 0xF7 }, /* 70 */ | |
433 | { 0xFF, 0xFF }, /* 71 */ | |
434 | { 0xFF, 0xFF }, /* 72 */ | |
435 | { 0xFF, 0x1F }, /* 73 */ | |
436 | { 0xFF, 0xF7 }, /* 74 */ | |
437 | { 0xFF, 0xFF }, /* 75 */ | |
438 | { 0xFF, 0xFF }, /* 76 */ | |
439 | { 0xFF, 0x1F }, /* 77 */ | |
440 | { 0xFF, 0xF7 }, /* 78 */ | |
441 | { 0xFF, 0xFF }, /* 79 */ | |
442 | { 0xFF, 0xFF }, /* 7A */ | |
443 | { 0xFF, 0x1F }, /* 7B */ | |
444 | { 0xFF, 0xF7 }, /* 7C */ | |
445 | { 0xFF, 0xFF }, /* 7D */ | |
446 | { 0xFF, 0xFF }, /* 7E */ | |
447 | { 0xFF, 0x1F }, /* 7F */ | |
448 | { 0xFF, 0xF7 }, /* 80 */ | |
449 | { 0xFF, 0xFF }, /* 81 */ | |
450 | { 0xFF, 0xFF }, /* 82 */ | |
451 | { 0xFF, 0x1F }, /* 83 */ | |
452 | { 0xFF, 0x7F }, /* 84 */ | |
453 | { 0xFF, 0x0F }, /* 85 */ | |
454 | { 0xFF, 0xD8 }, /* 86 */ | |
455 | { 0xFF, 0xFF }, /* 87 */ | |
456 | { 0xFF, 0xEF }, /* 88 */ | |
457 | { 0xFF, 0xFE }, /* 89 */ | |
458 | { 0xFF, 0xFE }, /* 8A */ | |
459 | { 0xFF, 0xFF }, /* 8B */ | |
460 | { 0xFF, 0xFF }, /* 8C */ | |
461 | { 0xFF, 0x3F }, /* 8D */ | |
462 | { 0xFF, 0xFF }, /* 8E */ | |
463 | { 0xFF, 0x3F }, /* 8F */ | |
464 | { 0xFF, 0x8F }, /* 90 */ | |
465 | { 0xFF, 0xFF }, /* 91 */ | |
466 | { 0xFF, 0x3F }, /* 92 */ | |
467 | { 0xFF, 0xFF }, /* 93 */ | |
468 | { 0xFF, 0xFF }, /* 94 */ | |
469 | { 0xFF, 0x0F }, /* 95 */ | |
470 | { 0xFF, 0x3F }, /* 96 */ | |
471 | { 0xFF, 0x8C }, /* 97 */ | |
472 | { 0x00, 0x00 }, /* 98 */ | |
473 | { 0x00, 0x00 }, /* 99 */ | |
474 | { 0x00, 0x00 }, /* 9A */ | |
475 | { 0x00, 0x00 }, /* 9B */ | |
476 | { 0x00, 0x00 }, /* 9C */ | |
477 | { 0x00, 0x00 }, /* 9D */ | |
478 | { 0x00, 0x00 }, /* 9E */ | |
479 | { 0x00, 0x00 }, /* 9F */ | |
480 | { 0x00, 0x00 }, /* A0 */ | |
481 | { 0x00, 0x00 }, /* A1 */ | |
482 | { 0x00, 0x00 }, /* A2 */ | |
483 | { 0x00, 0x00 }, /* A3 */ | |
484 | { 0x00, 0x00 }, /* A4 */ | |
485 | { 0x00, 0x00 }, /* A5 */ | |
486 | { 0x00, 0x00 }, /* A6 */ | |
487 | { 0x00, 0x00 }, /* A7 */ | |
488 | { 0x00, 0x00 }, /* A8 */ | |
489 | { 0x00, 0x00 }, /* A9 */ | |
490 | { 0x00, 0x00 }, /* AA */ | |
491 | { 0x00, 0x00 }, /* AB */ | |
492 | { 0x00, 0x00 }, /* AC */ | |
493 | { 0x00, 0x00 }, /* AD */ | |
494 | { 0x00, 0x00 }, /* AE */ | |
495 | { 0x00, 0x00 }, /* AF */ | |
496 | { 0x00, 0x00 }, /* B0 */ | |
497 | { 0x00, 0x00 }, /* B1 */ | |
498 | { 0x00, 0x00 }, /* B2 */ | |
499 | { 0x00, 0x00 }, /* B3 */ | |
500 | { 0x00, 0x00 }, /* B4 */ | |
501 | { 0x00, 0x00 }, /* B5 */ | |
502 | { 0x00, 0x00 }, /* B6 */ | |
503 | { 0x00, 0x00 }, /* B7 */ | |
504 | { 0x00, 0x00 }, /* B8 */ | |
505 | { 0x00, 0x00 }, /* B9 */ | |
506 | { 0x00, 0x00 }, /* BA */ | |
507 | { 0x00, 0x00 }, /* BB */ | |
508 | { 0x00, 0x00 }, /* BC */ | |
509 | { 0x00, 0x00 }, /* BD */ | |
510 | { 0x00, 0x00 }, /* BE */ | |
511 | { 0x00, 0x00 }, /* BF */ | |
512 | { 0x00, 0x00 }, /* C0 */ | |
513 | { 0x00, 0x00 }, /* C1 */ | |
514 | { 0x00, 0x00 }, /* C2 */ | |
515 | { 0x00, 0x00 }, /* C3 */ | |
516 | { 0x00, 0x00 }, /* C4 */ | |
517 | { 0x00, 0x00 }, /* C5 */ | |
518 | { 0x00, 0x00 }, /* C6 */ | |
519 | { 0x00, 0x00 }, /* C7 */ | |
520 | { 0x00, 0x00 }, /* C8 */ | |
521 | { 0x00, 0x00 }, /* C9 */ | |
522 | { 0x00, 0x00 }, /* CA */ | |
523 | { 0x00, 0x00 }, /* CB */ | |
524 | { 0x00, 0x00 }, /* CC */ | |
525 | { 0x00, 0x00 }, /* CD */ | |
526 | { 0x00, 0x00 }, /* CE */ | |
527 | { 0x00, 0x00 }, /* CF */ | |
528 | { 0x00, 0x00 }, /* D0 */ | |
529 | { 0x00, 0x00 }, /* D1 */ | |
530 | { 0x00, 0x00 }, /* D2 */ | |
531 | { 0x00, 0x00 }, /* D3 */ | |
532 | { 0x00, 0x00 }, /* D4 */ | |
533 | { 0x00, 0x00 }, /* D5 */ | |
534 | { 0x00, 0x00 }, /* D6 */ | |
535 | { 0x00, 0x00 }, /* D7 */ | |
536 | { 0x00, 0x00 }, /* D8 */ | |
537 | { 0x00, 0x00 }, /* D9 */ | |
538 | { 0x00, 0x00 }, /* DA */ | |
539 | { 0x00, 0x00 }, /* DB */ | |
540 | { 0x00, 0x00 }, /* DC */ | |
541 | { 0x00, 0x00 }, /* DD */ | |
542 | { 0x00, 0x00 }, /* DE */ | |
543 | { 0x00, 0x00 }, /* DF */ | |
544 | { 0x00, 0x00 }, /* E0 */ | |
545 | { 0x00, 0x00 }, /* E1 */ | |
546 | { 0x00, 0x00 }, /* E2 */ | |
547 | { 0x00, 0x00 }, /* E3 */ | |
548 | { 0x00, 0x00 }, /* E4 */ | |
549 | { 0x00, 0x00 }, /* E5 */ | |
550 | { 0x00, 0x00 }, /* E6 */ | |
551 | { 0x00, 0x00 }, /* E7 */ | |
552 | { 0x00, 0x00 }, /* E8 */ | |
553 | { 0x00, 0x00 }, /* E9 */ | |
554 | { 0x00, 0x00 }, /* EA */ | |
555 | { 0x00, 0x00 }, /* EB */ | |
556 | { 0x00, 0x00 }, /* EC */ | |
557 | { 0x00, 0x00 }, /* ED */ | |
558 | { 0x00, 0x00 }, /* EE */ | |
559 | { 0x00, 0x00 }, /* EF */ | |
560 | { 0x00, 0x00 }, /* F0 */ | |
561 | { 0x00, 0x00 }, /* F1 */ | |
562 | { 0x00, 0x00 }, /* F2 */ | |
563 | { 0x00, 0x00 }, /* F3 */ | |
564 | { 0x00, 0x00 }, /* F4 */ | |
565 | { 0x00, 0x00 }, /* F5 */ | |
566 | { 0x00, 0x00 }, /* F6 */ | |
567 | { 0x00, 0x00 }, /* F7 */ | |
568 | { 0x00, 0x00 }, /* F8 */ | |
569 | { 0x00, 0x00 }, /* F9 */ | |
570 | { 0x00, 0x00 }, /* FA */ | |
571 | { 0x00, 0x00 }, /* FB */ | |
572 | { 0x00, 0x00 }, /* FC */ | |
573 | { 0x00, 0x00 }, /* FD */ | |
574 | { 0x00, 0x00 }, /* FE */ | |
575 | { 0xFF, 0x00 }, /* FF */ | |
576 | }; | |
577 | ||
578 | static int max98095_readable(struct snd_soc_codec *codec, unsigned int reg) | |
579 | { | |
580 | if (reg >= M98095_REG_CNT) | |
581 | return 0; | |
582 | return max98095_access[reg].readable != 0; | |
583 | } | |
584 | ||
585 | static int max98095_volatile(struct snd_soc_codec *codec, unsigned int reg) | |
586 | { | |
587 | if (reg > M98095_REG_MAX_CACHED) | |
588 | return 1; | |
589 | ||
590 | switch (reg) { | |
591 | case M98095_000_HOST_DATA: | |
592 | case M98095_001_HOST_INT_STS: | |
593 | case M98095_002_HOST_RSP_STS: | |
594 | case M98095_003_HOST_CMD_STS: | |
595 | case M98095_004_CODEC_STS: | |
596 | case M98095_005_DAI1_ALC_STS: | |
597 | case M98095_006_DAI2_ALC_STS: | |
598 | case M98095_007_JACK_AUTO_STS: | |
599 | case M98095_008_JACK_MANUAL_STS: | |
600 | case M98095_009_JACK_VBAT_STS: | |
601 | case M98095_00A_ACC_ADC_STS: | |
602 | case M98095_00B_MIC_NG_AGC_STS: | |
603 | case M98095_00C_SPK_L_VOLT_STS: | |
604 | case M98095_00D_SPK_R_VOLT_STS: | |
605 | case M98095_00E_TEMP_SENSOR_STS: | |
606 | return 1; | |
607 | } | |
608 | ||
609 | return 0; | |
610 | } | |
611 | ||
dad31ec1 PH |
612 | /* |
613 | * Filter coefficients are in a separate register segment | |
614 | * and they share the address space of the normal registers. | |
615 | * The coefficient registers do not need or share the cache. | |
616 | */ | |
617 | static int max98095_hw_write(struct snd_soc_codec *codec, unsigned int reg, | |
618 | unsigned int value) | |
619 | { | |
0d8d2938 | 620 | int ret; |
dad31ec1 | 621 | |
0d8d2938 AL |
622 | codec->cache_bypass = 1; |
623 | ret = snd_soc_write(codec, reg, value); | |
624 | codec->cache_bypass = 0; | |
625 | ||
626 | return ret ? -EIO : 0; | |
dad31ec1 PH |
627 | } |
628 | ||
629 | /* | |
630 | * Load equalizer DSP coefficient configurations registers | |
631 | */ | |
632 | static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai, | |
633 | unsigned int band, u16 *coefs) | |
634 | { | |
635 | unsigned int eq_reg; | |
636 | unsigned int i; | |
637 | ||
638 | BUG_ON(band > 4); | |
639 | BUG_ON(dai > 1); | |
640 | ||
641 | /* Load the base register address */ | |
642 | eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE; | |
643 | ||
644 | /* Add the band address offset, note adjustment for word address */ | |
645 | eq_reg += band * (M98095_COEFS_PER_BAND << 1); | |
646 | ||
647 | /* Step through the registers and coefs */ | |
648 | for (i = 0; i < M98095_COEFS_PER_BAND; i++) { | |
649 | max98095_hw_write(codec, eq_reg++, M98095_BYTE1(coefs[i])); | |
650 | max98095_hw_write(codec, eq_reg++, M98095_BYTE0(coefs[i])); | |
651 | } | |
652 | } | |
653 | ||
654 | /* | |
655 | * Load biquad filter coefficient configurations registers | |
656 | */ | |
657 | static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai, | |
658 | unsigned int band, u16 *coefs) | |
659 | { | |
660 | unsigned int bq_reg; | |
661 | unsigned int i; | |
662 | ||
663 | BUG_ON(band > 1); | |
664 | BUG_ON(dai > 1); | |
665 | ||
666 | /* Load the base register address */ | |
667 | bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE; | |
668 | ||
669 | /* Add the band address offset, note adjustment for word address */ | |
670 | bq_reg += band * (M98095_COEFS_PER_BAND << 1); | |
671 | ||
672 | /* Step through the registers and coefs */ | |
673 | for (i = 0; i < M98095_COEFS_PER_BAND; i++) { | |
674 | max98095_hw_write(codec, bq_reg++, M98095_BYTE1(coefs[i])); | |
675 | max98095_hw_write(codec, bq_reg++, M98095_BYTE0(coefs[i])); | |
676 | } | |
677 | } | |
678 | ||
82a5a936 PH |
679 | static const char * const max98095_fltr_mode[] = { "Voice", "Music" }; |
680 | static const struct soc_enum max98095_dai1_filter_mode_enum[] = { | |
681 | SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 7, 2, max98095_fltr_mode), | |
682 | }; | |
683 | static const struct soc_enum max98095_dai2_filter_mode_enum[] = { | |
684 | SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 7, 2, max98095_fltr_mode), | |
685 | }; | |
686 | ||
687 | static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" }; | |
688 | ||
689 | static const struct soc_enum max98095_extmic_enum = | |
690 | SOC_ENUM_SINGLE(M98095_087_CFG_MIC, 0, 3, max98095_extmic_text); | |
691 | ||
692 | static const struct snd_kcontrol_new max98095_extmic_mux = | |
693 | SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum); | |
694 | ||
695 | static const char * const max98095_linein_text[] = { "INA", "INB" }; | |
696 | ||
697 | static const struct soc_enum max98095_linein_enum = | |
698 | SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 6, 2, max98095_linein_text); | |
699 | ||
700 | static const struct snd_kcontrol_new max98095_linein_mux = | |
701 | SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum); | |
702 | ||
703 | static const char * const max98095_line_mode_text[] = { | |
704 | "Stereo", "Differential"}; | |
705 | ||
706 | static const struct soc_enum max98095_linein_mode_enum = | |
707 | SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 7, 2, max98095_line_mode_text); | |
708 | ||
709 | static const struct soc_enum max98095_lineout_mode_enum = | |
710 | SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 4, 2, max98095_line_mode_text); | |
711 | ||
712 | static const char * const max98095_dai_fltr[] = { | |
713 | "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k", | |
714 | "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"}; | |
715 | static const struct soc_enum max98095_dai1_dac_filter_enum[] = { | |
716 | SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 0, 6, max98095_dai_fltr), | |
717 | }; | |
718 | static const struct soc_enum max98095_dai2_dac_filter_enum[] = { | |
719 | SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 0, 6, max98095_dai_fltr), | |
720 | }; | |
721 | static const struct soc_enum max98095_dai3_dac_filter_enum[] = { | |
722 | SOC_ENUM_SINGLE(M98095_042_DAI3_FILTERS, 0, 6, max98095_dai_fltr), | |
723 | }; | |
724 | ||
725 | static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol, | |
726 | struct snd_ctl_elem_value *ucontrol) | |
727 | { | |
728 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
729 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
730 | unsigned int sel = ucontrol->value.integer.value[0]; | |
731 | ||
732 | max98095->mic1pre = sel; | |
733 | snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK, | |
734 | (1+sel)<<M98095_MICPRE_SHIFT); | |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
739 | static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol, | |
740 | struct snd_ctl_elem_value *ucontrol) | |
741 | { | |
742 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
743 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
744 | ||
745 | ucontrol->value.integer.value[0] = max98095->mic1pre; | |
746 | return 0; | |
747 | } | |
748 | ||
749 | static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol, | |
750 | struct snd_ctl_elem_value *ucontrol) | |
751 | { | |
752 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
753 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
754 | unsigned int sel = ucontrol->value.integer.value[0]; | |
755 | ||
756 | max98095->mic2pre = sel; | |
757 | snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK, | |
758 | (1+sel)<<M98095_MICPRE_SHIFT); | |
759 | ||
760 | return 0; | |
761 | } | |
762 | ||
763 | static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol, | |
764 | struct snd_ctl_elem_value *ucontrol) | |
765 | { | |
766 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
767 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
768 | ||
769 | ucontrol->value.integer.value[0] = max98095->mic2pre; | |
770 | return 0; | |
771 | } | |
772 | ||
773 | static const unsigned int max98095_micboost_tlv[] = { | |
774 | TLV_DB_RANGE_HEAD(2), | |
775 | 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), | |
776 | 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), | |
777 | }; | |
778 | ||
779 | static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0); | |
780 | static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0); | |
781 | static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0); | |
782 | ||
783 | static const unsigned int max98095_hp_tlv[] = { | |
784 | TLV_DB_RANGE_HEAD(5), | |
785 | 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), | |
786 | 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), | |
787 | 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), | |
788 | 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), | |
789 | 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0), | |
790 | }; | |
791 | ||
792 | static const unsigned int max98095_spk_tlv[] = { | |
793 | TLV_DB_RANGE_HEAD(4), | |
794 | 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0), | |
795 | 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0), | |
796 | 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0), | |
797 | 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0), | |
798 | }; | |
799 | ||
800 | static const unsigned int max98095_rcv_lout_tlv[] = { | |
801 | TLV_DB_RANGE_HEAD(5), | |
802 | 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), | |
803 | 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), | |
804 | 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), | |
805 | 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), | |
806 | 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0), | |
807 | }; | |
808 | ||
809 | static const unsigned int max98095_lin_tlv[] = { | |
810 | TLV_DB_RANGE_HEAD(3), | |
811 | 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0), | |
812 | 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0), | |
813 | 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0), | |
814 | }; | |
815 | ||
816 | static const struct snd_kcontrol_new max98095_snd_controls[] = { | |
817 | ||
818 | SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L, | |
819 | M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv), | |
820 | ||
821 | SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L, | |
822 | M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv), | |
823 | ||
824 | SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV, | |
825 | 0, 31, 0, max98095_rcv_lout_tlv), | |
826 | ||
827 | SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1, | |
828 | M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv), | |
829 | ||
830 | SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L, | |
831 | M98095_065_LVL_HP_R, 7, 1, 1), | |
832 | ||
833 | SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L, | |
834 | M98095_068_LVL_SPK_R, 7, 1, 1), | |
835 | ||
836 | SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1), | |
837 | ||
838 | SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1, | |
839 | M98095_063_LVL_LINEOUT2, 7, 1, 1), | |
840 | ||
841 | SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1, | |
842 | max98095_mic_tlv), | |
843 | ||
844 | SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1, | |
845 | max98095_mic_tlv), | |
846 | ||
847 | SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", | |
848 | M98095_05F_LVL_MIC1, 5, 2, 0, | |
849 | max98095_mic1pre_get, max98095_mic1pre_set, | |
850 | max98095_micboost_tlv), | |
851 | SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", | |
852 | M98095_060_LVL_MIC2, 5, 2, 0, | |
853 | max98095_mic2pre_get, max98095_mic2pre_set, | |
854 | max98095_micboost_tlv), | |
855 | ||
856 | SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1, | |
857 | max98095_lin_tlv), | |
858 | ||
859 | SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1, | |
860 | max98095_adc_tlv), | |
861 | SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1, | |
862 | max98095_adc_tlv), | |
863 | ||
864 | SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0, | |
865 | max98095_adcboost_tlv), | |
866 | SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0, | |
867 | max98095_adcboost_tlv), | |
868 | ||
dad31ec1 PH |
869 | SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0), |
870 | SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0), | |
871 | ||
872 | SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0), | |
873 | SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0), | |
874 | ||
82a5a936 PH |
875 | SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum), |
876 | SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum), | |
877 | SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum), | |
878 | SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum), | |
879 | SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum), | |
880 | ||
881 | SOC_ENUM("Linein Mode", max98095_linein_mode_enum), | |
882 | SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum), | |
883 | }; | |
884 | ||
885 | /* Left speaker mixer switch */ | |
886 | static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = { | |
887 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0), | |
888 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0), | |
889 | SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), | |
890 | SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), | |
891 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0), | |
892 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0), | |
893 | SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0), | |
894 | SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0), | |
895 | }; | |
896 | ||
897 | /* Right speaker mixer switch */ | |
898 | static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = { | |
899 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0), | |
900 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0), | |
901 | SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), | |
902 | SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), | |
903 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0), | |
904 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0), | |
905 | SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0), | |
906 | SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0), | |
907 | }; | |
908 | ||
909 | /* Left headphone mixer switch */ | |
910 | static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = { | |
911 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0), | |
912 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0), | |
913 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0), | |
914 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0), | |
915 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0), | |
916 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0), | |
917 | }; | |
918 | ||
919 | /* Right headphone mixer switch */ | |
920 | static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = { | |
921 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0), | |
922 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0), | |
923 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0), | |
924 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0), | |
925 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0), | |
926 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0), | |
927 | }; | |
928 | ||
929 | /* Receiver earpiece mixer switch */ | |
930 | static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = { | |
931 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0), | |
932 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0), | |
933 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0), | |
934 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0), | |
935 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0), | |
936 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0), | |
937 | }; | |
938 | ||
939 | /* Left lineout mixer switch */ | |
940 | static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = { | |
941 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0), | |
942 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0), | |
943 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0), | |
944 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0), | |
945 | SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0), | |
946 | SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0), | |
947 | }; | |
948 | ||
949 | /* Right lineout mixer switch */ | |
950 | static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = { | |
951 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0), | |
952 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0), | |
953 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0), | |
954 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0), | |
955 | SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0), | |
956 | SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0), | |
957 | }; | |
958 | ||
959 | /* Left ADC mixer switch */ | |
960 | static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = { | |
961 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0), | |
962 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0), | |
963 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0), | |
964 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0), | |
965 | }; | |
966 | ||
967 | /* Right ADC mixer switch */ | |
968 | static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = { | |
969 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0), | |
970 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0), | |
971 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0), | |
972 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0), | |
973 | }; | |
974 | ||
975 | static int max98095_mic_event(struct snd_soc_dapm_widget *w, | |
976 | struct snd_kcontrol *kcontrol, int event) | |
977 | { | |
978 | struct snd_soc_codec *codec = w->codec; | |
979 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
980 | ||
981 | switch (event) { | |
982 | case SND_SOC_DAPM_POST_PMU: | |
983 | if (w->reg == M98095_05F_LVL_MIC1) { | |
984 | snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, | |
985 | (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT); | |
986 | } else { | |
987 | snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, | |
988 | (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT); | |
989 | } | |
990 | break; | |
991 | case SND_SOC_DAPM_POST_PMD: | |
992 | snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0); | |
993 | break; | |
994 | default: | |
995 | return -EINVAL; | |
996 | } | |
997 | ||
998 | return 0; | |
999 | } | |
1000 | ||
1001 | /* | |
1002 | * The line inputs are stereo inputs with the left and right | |
1003 | * channels sharing a common PGA power control signal. | |
1004 | */ | |
1005 | static int max98095_line_pga(struct snd_soc_dapm_widget *w, | |
1006 | int event, u8 channel) | |
1007 | { | |
1008 | struct snd_soc_codec *codec = w->codec; | |
1009 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1010 | u8 *state; | |
1011 | ||
1012 | BUG_ON(!((channel == 1) || (channel == 2))); | |
1013 | ||
1014 | state = &max98095->lin_state; | |
1015 | ||
1016 | switch (event) { | |
1017 | case SND_SOC_DAPM_POST_PMU: | |
1018 | *state |= channel; | |
1019 | snd_soc_update_bits(codec, w->reg, | |
1020 | (1 << w->shift), (1 << w->shift)); | |
1021 | break; | |
1022 | case SND_SOC_DAPM_POST_PMD: | |
1023 | *state &= ~channel; | |
1024 | if (*state == 0) { | |
1025 | snd_soc_update_bits(codec, w->reg, | |
1026 | (1 << w->shift), 0); | |
1027 | } | |
1028 | break; | |
1029 | default: | |
1030 | return -EINVAL; | |
1031 | } | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w, | |
1037 | struct snd_kcontrol *k, int event) | |
1038 | { | |
1039 | return max98095_line_pga(w, event, 1); | |
1040 | } | |
1041 | ||
1042 | static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w, | |
1043 | struct snd_kcontrol *k, int event) | |
1044 | { | |
1045 | return max98095_line_pga(w, event, 2); | |
1046 | } | |
1047 | ||
1048 | /* | |
1049 | * The stereo line out mixer outputs to two stereo line outs. | |
1050 | * The 2nd pair has a separate set of enables. | |
1051 | */ | |
1052 | static int max98095_lineout_event(struct snd_soc_dapm_widget *w, | |
1053 | struct snd_kcontrol *kcontrol, int event) | |
1054 | { | |
1055 | struct snd_soc_codec *codec = w->codec; | |
1056 | ||
1057 | switch (event) { | |
1058 | case SND_SOC_DAPM_POST_PMU: | |
1059 | snd_soc_update_bits(codec, w->reg, | |
1060 | (1 << (w->shift+2)), (1 << (w->shift+2))); | |
1061 | break; | |
1062 | case SND_SOC_DAPM_POST_PMD: | |
1063 | snd_soc_update_bits(codec, w->reg, | |
1064 | (1 << (w->shift+2)), 0); | |
1065 | break; | |
1066 | default: | |
1067 | return -EINVAL; | |
1068 | } | |
1069 | ||
1070 | return 0; | |
1071 | } | |
1072 | ||
1073 | static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = { | |
1074 | ||
1075 | SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0), | |
1076 | SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0), | |
1077 | ||
1078 | SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", | |
1079 | M98095_091_PWR_EN_OUT, 0, 0), | |
1080 | SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", | |
1081 | M98095_091_PWR_EN_OUT, 1, 0), | |
1082 | SND_SOC_DAPM_DAC("DACM2", "Aux Playback", | |
1083 | M98095_091_PWR_EN_OUT, 2, 0), | |
1084 | SND_SOC_DAPM_DAC("DACM3", "Voice Playback", | |
1085 | M98095_091_PWR_EN_OUT, 2, 0), | |
1086 | ||
1087 | SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT, | |
1088 | 6, 0, NULL, 0), | |
1089 | SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT, | |
1090 | 7, 0, NULL, 0), | |
1091 | ||
1092 | SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT, | |
1093 | 4, 0, NULL, 0), | |
1094 | SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT, | |
1095 | 5, 0, NULL, 0), | |
1096 | ||
1097 | SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT, | |
1098 | 3, 0, NULL, 0), | |
1099 | ||
1100 | SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT, | |
1101 | 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), | |
1102 | SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT, | |
1103 | 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), | |
1104 | ||
1105 | SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, | |
1106 | &max98095_extmic_mux), | |
1107 | ||
1108 | SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0, | |
1109 | &max98095_linein_mux), | |
1110 | ||
1111 | SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, | |
1112 | &max98095_left_hp_mixer_controls[0], | |
1113 | ARRAY_SIZE(max98095_left_hp_mixer_controls)), | |
1114 | ||
1115 | SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, | |
1116 | &max98095_right_hp_mixer_controls[0], | |
1117 | ARRAY_SIZE(max98095_right_hp_mixer_controls)), | |
1118 | ||
1119 | SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, | |
1120 | &max98095_left_speaker_mixer_controls[0], | |
1121 | ARRAY_SIZE(max98095_left_speaker_mixer_controls)), | |
1122 | ||
1123 | SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, | |
1124 | &max98095_right_speaker_mixer_controls[0], | |
1125 | ARRAY_SIZE(max98095_right_speaker_mixer_controls)), | |
1126 | ||
1127 | SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0, | |
1128 | &max98095_mono_rcv_mixer_controls[0], | |
1129 | ARRAY_SIZE(max98095_mono_rcv_mixer_controls)), | |
1130 | ||
1131 | SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0, | |
1132 | &max98095_left_lineout_mixer_controls[0], | |
1133 | ARRAY_SIZE(max98095_left_lineout_mixer_controls)), | |
1134 | ||
1135 | SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0, | |
1136 | &max98095_right_lineout_mixer_controls[0], | |
1137 | ARRAY_SIZE(max98095_right_lineout_mixer_controls)), | |
1138 | ||
1139 | SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, | |
1140 | &max98095_left_ADC_mixer_controls[0], | |
1141 | ARRAY_SIZE(max98095_left_ADC_mixer_controls)), | |
1142 | ||
1143 | SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, | |
1144 | &max98095_right_ADC_mixer_controls[0], | |
1145 | ARRAY_SIZE(max98095_right_ADC_mixer_controls)), | |
1146 | ||
1147 | SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1, | |
1148 | 5, 0, NULL, 0, max98095_mic_event, | |
1149 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1150 | ||
1151 | SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2, | |
1152 | 5, 0, NULL, 0, max98095_mic_event, | |
1153 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1154 | ||
1155 | SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN, | |
1156 | 7, 0, NULL, 0, max98095_pga_in1_event, | |
1157 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1158 | ||
1159 | SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN, | |
1160 | 7, 0, NULL, 0, max98095_pga_in2_event, | |
1161 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1162 | ||
1163 | SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0), | |
1164 | SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0), | |
1165 | ||
1166 | SND_SOC_DAPM_OUTPUT("HPL"), | |
1167 | SND_SOC_DAPM_OUTPUT("HPR"), | |
1168 | SND_SOC_DAPM_OUTPUT("SPKL"), | |
1169 | SND_SOC_DAPM_OUTPUT("SPKR"), | |
1170 | SND_SOC_DAPM_OUTPUT("RCV"), | |
1171 | SND_SOC_DAPM_OUTPUT("OUT1"), | |
1172 | SND_SOC_DAPM_OUTPUT("OUT2"), | |
1173 | SND_SOC_DAPM_OUTPUT("OUT3"), | |
1174 | SND_SOC_DAPM_OUTPUT("OUT4"), | |
1175 | ||
1176 | SND_SOC_DAPM_INPUT("MIC1"), | |
1177 | SND_SOC_DAPM_INPUT("MIC2"), | |
1178 | SND_SOC_DAPM_INPUT("INA1"), | |
1179 | SND_SOC_DAPM_INPUT("INA2"), | |
1180 | SND_SOC_DAPM_INPUT("INB1"), | |
1181 | SND_SOC_DAPM_INPUT("INB2"), | |
1182 | }; | |
1183 | ||
1184 | static const struct snd_soc_dapm_route max98095_audio_map[] = { | |
1185 | /* Left headphone output mixer */ | |
1186 | {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"}, | |
1187 | {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"}, | |
1188 | {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1189 | {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1190 | {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"}, | |
1191 | {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"}, | |
1192 | ||
1193 | /* Right headphone output mixer */ | |
1194 | {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"}, | |
1195 | {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"}, | |
1196 | {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1197 | {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1198 | {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"}, | |
1199 | {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"}, | |
1200 | ||
1201 | /* Left speaker output mixer */ | |
1202 | {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"}, | |
1203 | {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"}, | |
1204 | {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, | |
1205 | {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, | |
1206 | {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1207 | {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1208 | {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"}, | |
1209 | {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"}, | |
1210 | ||
1211 | /* Right speaker output mixer */ | |
1212 | {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"}, | |
1213 | {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"}, | |
1214 | {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, | |
1215 | {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, | |
1216 | {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1217 | {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1218 | {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"}, | |
1219 | {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"}, | |
1220 | ||
1221 | /* Earpiece/Receiver output mixer */ | |
1222 | {"Receiver Mixer", "Left DAC1 Switch", "DACL1"}, | |
1223 | {"Receiver Mixer", "Right DAC1 Switch", "DACR1"}, | |
1224 | {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1225 | {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1226 | {"Receiver Mixer", "IN1 Switch", "IN1 Input"}, | |
1227 | {"Receiver Mixer", "IN2 Switch", "IN2 Input"}, | |
1228 | ||
1229 | /* Left Lineout output mixer */ | |
1230 | {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"}, | |
1231 | {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"}, | |
1232 | {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1233 | {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1234 | {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"}, | |
1235 | {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"}, | |
1236 | ||
1237 | /* Right lineout output mixer */ | |
1238 | {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"}, | |
1239 | {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"}, | |
1240 | {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1241 | {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1242 | {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"}, | |
1243 | {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"}, | |
1244 | ||
1245 | {"HP Left Out", NULL, "Left Headphone Mixer"}, | |
1246 | {"HP Right Out", NULL, "Right Headphone Mixer"}, | |
1247 | {"SPK Left Out", NULL, "Left Speaker Mixer"}, | |
1248 | {"SPK Right Out", NULL, "Right Speaker Mixer"}, | |
1249 | {"RCV Mono Out", NULL, "Receiver Mixer"}, | |
1250 | {"LINE Left Out", NULL, "Left Lineout Mixer"}, | |
1251 | {"LINE Right Out", NULL, "Right Lineout Mixer"}, | |
1252 | ||
1253 | {"HPL", NULL, "HP Left Out"}, | |
1254 | {"HPR", NULL, "HP Right Out"}, | |
1255 | {"SPKL", NULL, "SPK Left Out"}, | |
1256 | {"SPKR", NULL, "SPK Right Out"}, | |
1257 | {"RCV", NULL, "RCV Mono Out"}, | |
1258 | {"OUT1", NULL, "LINE Left Out"}, | |
1259 | {"OUT2", NULL, "LINE Right Out"}, | |
1260 | {"OUT3", NULL, "LINE Left Out"}, | |
1261 | {"OUT4", NULL, "LINE Right Out"}, | |
1262 | ||
1263 | /* Left ADC input mixer */ | |
1264 | {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1265 | {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1266 | {"Left ADC Mixer", "IN1 Switch", "IN1 Input"}, | |
1267 | {"Left ADC Mixer", "IN2 Switch", "IN2 Input"}, | |
1268 | ||
1269 | /* Right ADC input mixer */ | |
1270 | {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1271 | {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1272 | {"Right ADC Mixer", "IN1 Switch", "IN1 Input"}, | |
1273 | {"Right ADC Mixer", "IN2 Switch", "IN2 Input"}, | |
1274 | ||
1275 | /* Inputs */ | |
1276 | {"ADCL", NULL, "Left ADC Mixer"}, | |
1277 | {"ADCR", NULL, "Right ADC Mixer"}, | |
1278 | ||
1279 | {"IN1 Input", NULL, "INA1"}, | |
1280 | {"IN2 Input", NULL, "INA2"}, | |
1281 | ||
1282 | {"MIC1 Input", NULL, "MIC1"}, | |
1283 | {"MIC2 Input", NULL, "MIC2"}, | |
1284 | }; | |
1285 | ||
1286 | static int max98095_add_widgets(struct snd_soc_codec *codec) | |
1287 | { | |
1288 | snd_soc_add_controls(codec, max98095_snd_controls, | |
1289 | ARRAY_SIZE(max98095_snd_controls)); | |
1290 | ||
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | /* codec mclk clock divider coefficients */ | |
1295 | static const struct { | |
1296 | u32 rate; | |
1297 | u8 sr; | |
1298 | } rate_table[] = { | |
1299 | {8000, 0x01}, | |
1300 | {11025, 0x02}, | |
1301 | {16000, 0x03}, | |
1302 | {22050, 0x04}, | |
1303 | {24000, 0x05}, | |
1304 | {32000, 0x06}, | |
1305 | {44100, 0x07}, | |
1306 | {48000, 0x08}, | |
1307 | {88200, 0x09}, | |
1308 | {96000, 0x0A}, | |
1309 | }; | |
1310 | ||
1311 | static int rate_value(int rate, u8 *value) | |
1312 | { | |
1313 | int i; | |
1314 | ||
1315 | for (i = 0; i < ARRAY_SIZE(rate_table); i++) { | |
1316 | if (rate_table[i].rate >= rate) { | |
1317 | *value = rate_table[i].sr; | |
1318 | return 0; | |
1319 | } | |
1320 | } | |
1321 | *value = rate_table[0].sr; | |
1322 | return -EINVAL; | |
1323 | } | |
1324 | ||
1325 | static int max98095_dai1_hw_params(struct snd_pcm_substream *substream, | |
1326 | struct snd_pcm_hw_params *params, | |
1327 | struct snd_soc_dai *dai) | |
1328 | { | |
1329 | struct snd_soc_codec *codec = dai->codec; | |
1330 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1331 | struct max98095_cdata *cdata; | |
1332 | unsigned long long ni; | |
1333 | unsigned int rate; | |
1334 | u8 regval; | |
1335 | ||
1336 | cdata = &max98095->dai[0]; | |
1337 | ||
1338 | rate = params_rate(params); | |
1339 | ||
1340 | switch (params_format(params)) { | |
1341 | case SNDRV_PCM_FORMAT_S16_LE: | |
1342 | snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, | |
1343 | M98095_DAI_WS, 0); | |
1344 | break; | |
1345 | case SNDRV_PCM_FORMAT_S24_LE: | |
1346 | snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, | |
1347 | M98095_DAI_WS, M98095_DAI_WS); | |
1348 | break; | |
1349 | default: | |
1350 | return -EINVAL; | |
1351 | } | |
1352 | ||
1353 | if (rate_value(rate, ®val)) | |
1354 | return -EINVAL; | |
1355 | ||
1356 | snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE, | |
1357 | M98095_CLKMODE_MASK, regval); | |
1358 | cdata->rate = rate; | |
1359 | ||
1360 | /* Configure NI when operating as master */ | |
1361 | if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) { | |
1362 | if (max98095->sysclk == 0) { | |
1363 | dev_err(codec->dev, "Invalid system clock frequency\n"); | |
1364 | return -EINVAL; | |
1365 | } | |
1366 | ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) | |
1367 | * (unsigned long long int)rate; | |
1368 | do_div(ni, (unsigned long long int)max98095->sysclk); | |
1369 | snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, | |
1370 | (ni >> 8) & 0x7F); | |
1371 | snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, | |
1372 | ni & 0xFF); | |
1373 | } | |
1374 | ||
1375 | /* Update sample rate mode */ | |
1376 | if (rate < 50000) | |
1377 | snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, | |
1378 | M98095_DAI_DHF, 0); | |
1379 | else | |
1380 | snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, | |
1381 | M98095_DAI_DHF, M98095_DAI_DHF); | |
1382 | ||
1383 | return 0; | |
1384 | } | |
1385 | ||
1386 | static int max98095_dai2_hw_params(struct snd_pcm_substream *substream, | |
1387 | struct snd_pcm_hw_params *params, | |
1388 | struct snd_soc_dai *dai) | |
1389 | { | |
1390 | struct snd_soc_codec *codec = dai->codec; | |
1391 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1392 | struct max98095_cdata *cdata; | |
1393 | unsigned long long ni; | |
1394 | unsigned int rate; | |
1395 | u8 regval; | |
1396 | ||
1397 | cdata = &max98095->dai[1]; | |
1398 | ||
1399 | rate = params_rate(params); | |
1400 | ||
1401 | switch (params_format(params)) { | |
1402 | case SNDRV_PCM_FORMAT_S16_LE: | |
1403 | snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, | |
1404 | M98095_DAI_WS, 0); | |
1405 | break; | |
1406 | case SNDRV_PCM_FORMAT_S24_LE: | |
1407 | snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, | |
1408 | M98095_DAI_WS, M98095_DAI_WS); | |
1409 | break; | |
1410 | default: | |
1411 | return -EINVAL; | |
1412 | } | |
1413 | ||
1414 | if (rate_value(rate, ®val)) | |
1415 | return -EINVAL; | |
1416 | ||
1417 | snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE, | |
1418 | M98095_CLKMODE_MASK, regval); | |
1419 | cdata->rate = rate; | |
1420 | ||
1421 | /* Configure NI when operating as master */ | |
1422 | if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) { | |
1423 | if (max98095->sysclk == 0) { | |
1424 | dev_err(codec->dev, "Invalid system clock frequency\n"); | |
1425 | return -EINVAL; | |
1426 | } | |
1427 | ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) | |
1428 | * (unsigned long long int)rate; | |
1429 | do_div(ni, (unsigned long long int)max98095->sysclk); | |
1430 | snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, | |
1431 | (ni >> 8) & 0x7F); | |
1432 | snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, | |
1433 | ni & 0xFF); | |
1434 | } | |
1435 | ||
1436 | /* Update sample rate mode */ | |
1437 | if (rate < 50000) | |
1438 | snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, | |
1439 | M98095_DAI_DHF, 0); | |
1440 | else | |
1441 | snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, | |
1442 | M98095_DAI_DHF, M98095_DAI_DHF); | |
1443 | ||
1444 | return 0; | |
1445 | } | |
1446 | ||
1447 | static int max98095_dai3_hw_params(struct snd_pcm_substream *substream, | |
1448 | struct snd_pcm_hw_params *params, | |
1449 | struct snd_soc_dai *dai) | |
1450 | { | |
1451 | struct snd_soc_codec *codec = dai->codec; | |
1452 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1453 | struct max98095_cdata *cdata; | |
1454 | unsigned long long ni; | |
1455 | unsigned int rate; | |
1456 | u8 regval; | |
1457 | ||
1458 | cdata = &max98095->dai[2]; | |
1459 | ||
1460 | rate = params_rate(params); | |
1461 | ||
1462 | switch (params_format(params)) { | |
1463 | case SNDRV_PCM_FORMAT_S16_LE: | |
1464 | snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, | |
1465 | M98095_DAI_WS, 0); | |
1466 | break; | |
1467 | case SNDRV_PCM_FORMAT_S24_LE: | |
1468 | snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, | |
1469 | M98095_DAI_WS, M98095_DAI_WS); | |
1470 | break; | |
1471 | default: | |
1472 | return -EINVAL; | |
1473 | } | |
1474 | ||
1475 | if (rate_value(rate, ®val)) | |
1476 | return -EINVAL; | |
1477 | ||
1478 | snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE, | |
1479 | M98095_CLKMODE_MASK, regval); | |
1480 | cdata->rate = rate; | |
1481 | ||
1482 | /* Configure NI when operating as master */ | |
1483 | if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) { | |
1484 | if (max98095->sysclk == 0) { | |
1485 | dev_err(codec->dev, "Invalid system clock frequency\n"); | |
1486 | return -EINVAL; | |
1487 | } | |
1488 | ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) | |
1489 | * (unsigned long long int)rate; | |
1490 | do_div(ni, (unsigned long long int)max98095->sysclk); | |
1491 | snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, | |
1492 | (ni >> 8) & 0x7F); | |
1493 | snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, | |
1494 | ni & 0xFF); | |
1495 | } | |
1496 | ||
1497 | /* Update sample rate mode */ | |
1498 | if (rate < 50000) | |
1499 | snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, | |
1500 | M98095_DAI_DHF, 0); | |
1501 | else | |
1502 | snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, | |
1503 | M98095_DAI_DHF, M98095_DAI_DHF); | |
1504 | ||
1505 | return 0; | |
1506 | } | |
1507 | ||
1508 | static int max98095_dai_set_sysclk(struct snd_soc_dai *dai, | |
1509 | int clk_id, unsigned int freq, int dir) | |
1510 | { | |
1511 | struct snd_soc_codec *codec = dai->codec; | |
1512 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1513 | ||
1514 | /* Requested clock frequency is already setup */ | |
1515 | if (freq == max98095->sysclk) | |
1516 | return 0; | |
1517 | ||
82a5a936 PH |
1518 | /* Setup clocks for slave mode, and using the PLL |
1519 | * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) | |
1520 | * 0x02 (when master clk is 20MHz to 40MHz).. | |
1521 | * 0x03 (when master clk is 40MHz to 60MHz).. | |
1522 | */ | |
1523 | if ((freq >= 10000000) && (freq < 20000000)) { | |
1524 | snd_soc_write(codec, M98095_026_SYS_CLK, 0x10); | |
1525 | } else if ((freq >= 20000000) && (freq < 40000000)) { | |
1526 | snd_soc_write(codec, M98095_026_SYS_CLK, 0x20); | |
1527 | } else if ((freq >= 40000000) && (freq < 60000000)) { | |
1528 | snd_soc_write(codec, M98095_026_SYS_CLK, 0x30); | |
1529 | } else { | |
1530 | dev_err(codec->dev, "Invalid master clock frequency\n"); | |
1531 | return -EINVAL; | |
1532 | } | |
1533 | ||
1534 | dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); | |
1535 | ||
1536 | max98095->sysclk = freq; | |
1537 | return 0; | |
1538 | } | |
1539 | ||
1540 | static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai, | |
1541 | unsigned int fmt) | |
1542 | { | |
1543 | struct snd_soc_codec *codec = codec_dai->codec; | |
1544 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1545 | struct max98095_cdata *cdata; | |
1546 | u8 regval = 0; | |
1547 | ||
1548 | cdata = &max98095->dai[0]; | |
1549 | ||
1550 | if (fmt != cdata->fmt) { | |
1551 | cdata->fmt = fmt; | |
1552 | ||
1553 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1554 | case SND_SOC_DAIFMT_CBS_CFS: | |
1555 | /* Slave mode PLL */ | |
1556 | snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, | |
1557 | 0x80); | |
1558 | snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, | |
1559 | 0x00); | |
1560 | break; | |
1561 | case SND_SOC_DAIFMT_CBM_CFM: | |
1562 | /* Set to master mode */ | |
1563 | regval |= M98095_DAI_MAS; | |
1564 | break; | |
1565 | case SND_SOC_DAIFMT_CBS_CFM: | |
1566 | case SND_SOC_DAIFMT_CBM_CFS: | |
1567 | default: | |
1568 | dev_err(codec->dev, "Clock mode unsupported"); | |
1569 | return -EINVAL; | |
1570 | } | |
1571 | ||
1572 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1573 | case SND_SOC_DAIFMT_I2S: | |
1574 | regval |= M98095_DAI_DLY; | |
1575 | break; | |
1576 | case SND_SOC_DAIFMT_LEFT_J: | |
1577 | break; | |
1578 | default: | |
1579 | return -EINVAL; | |
1580 | } | |
1581 | ||
1582 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1583 | case SND_SOC_DAIFMT_NB_NF: | |
1584 | break; | |
1585 | case SND_SOC_DAIFMT_NB_IF: | |
1586 | regval |= M98095_DAI_WCI; | |
1587 | break; | |
1588 | case SND_SOC_DAIFMT_IB_NF: | |
1589 | regval |= M98095_DAI_BCI; | |
1590 | break; | |
1591 | case SND_SOC_DAIFMT_IB_IF: | |
1592 | regval |= M98095_DAI_BCI|M98095_DAI_WCI; | |
1593 | break; | |
1594 | default: | |
1595 | return -EINVAL; | |
1596 | } | |
1597 | ||
1598 | snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, | |
1599 | M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | | |
1600 | M98095_DAI_WCI, regval); | |
1601 | ||
1602 | snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64); | |
1603 | } | |
1604 | ||
1605 | return 0; | |
1606 | } | |
1607 | ||
1608 | static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai, | |
1609 | unsigned int fmt) | |
1610 | { | |
1611 | struct snd_soc_codec *codec = codec_dai->codec; | |
1612 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1613 | struct max98095_cdata *cdata; | |
1614 | u8 regval = 0; | |
1615 | ||
1616 | cdata = &max98095->dai[1]; | |
1617 | ||
1618 | if (fmt != cdata->fmt) { | |
1619 | cdata->fmt = fmt; | |
1620 | ||
1621 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1622 | case SND_SOC_DAIFMT_CBS_CFS: | |
1623 | /* Slave mode PLL */ | |
1624 | snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, | |
1625 | 0x80); | |
1626 | snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, | |
1627 | 0x00); | |
1628 | break; | |
1629 | case SND_SOC_DAIFMT_CBM_CFM: | |
1630 | /* Set to master mode */ | |
1631 | regval |= M98095_DAI_MAS; | |
1632 | break; | |
1633 | case SND_SOC_DAIFMT_CBS_CFM: | |
1634 | case SND_SOC_DAIFMT_CBM_CFS: | |
1635 | default: | |
1636 | dev_err(codec->dev, "Clock mode unsupported"); | |
1637 | return -EINVAL; | |
1638 | } | |
1639 | ||
1640 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1641 | case SND_SOC_DAIFMT_I2S: | |
1642 | regval |= M98095_DAI_DLY; | |
1643 | break; | |
1644 | case SND_SOC_DAIFMT_LEFT_J: | |
1645 | break; | |
1646 | default: | |
1647 | return -EINVAL; | |
1648 | } | |
1649 | ||
1650 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1651 | case SND_SOC_DAIFMT_NB_NF: | |
1652 | break; | |
1653 | case SND_SOC_DAIFMT_NB_IF: | |
1654 | regval |= M98095_DAI_WCI; | |
1655 | break; | |
1656 | case SND_SOC_DAIFMT_IB_NF: | |
1657 | regval |= M98095_DAI_BCI; | |
1658 | break; | |
1659 | case SND_SOC_DAIFMT_IB_IF: | |
1660 | regval |= M98095_DAI_BCI|M98095_DAI_WCI; | |
1661 | break; | |
1662 | default: | |
1663 | return -EINVAL; | |
1664 | } | |
1665 | ||
1666 | snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, | |
1667 | M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | | |
1668 | M98095_DAI_WCI, regval); | |
1669 | ||
1670 | snd_soc_write(codec, M98095_035_DAI2_CLOCK, | |
1671 | M98095_DAI_BSEL64); | |
1672 | } | |
1673 | ||
1674 | return 0; | |
1675 | } | |
1676 | ||
1677 | static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai, | |
1678 | unsigned int fmt) | |
1679 | { | |
1680 | struct snd_soc_codec *codec = codec_dai->codec; | |
1681 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1682 | struct max98095_cdata *cdata; | |
1683 | u8 regval = 0; | |
1684 | ||
1685 | cdata = &max98095->dai[2]; | |
1686 | ||
1687 | if (fmt != cdata->fmt) { | |
1688 | cdata->fmt = fmt; | |
1689 | ||
1690 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1691 | case SND_SOC_DAIFMT_CBS_CFS: | |
1692 | /* Slave mode PLL */ | |
1693 | snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, | |
1694 | 0x80); | |
1695 | snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, | |
1696 | 0x00); | |
1697 | break; | |
1698 | case SND_SOC_DAIFMT_CBM_CFM: | |
1699 | /* Set to master mode */ | |
1700 | regval |= M98095_DAI_MAS; | |
1701 | break; | |
1702 | case SND_SOC_DAIFMT_CBS_CFM: | |
1703 | case SND_SOC_DAIFMT_CBM_CFS: | |
1704 | default: | |
1705 | dev_err(codec->dev, "Clock mode unsupported"); | |
1706 | return -EINVAL; | |
1707 | } | |
1708 | ||
1709 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1710 | case SND_SOC_DAIFMT_I2S: | |
1711 | regval |= M98095_DAI_DLY; | |
1712 | break; | |
1713 | case SND_SOC_DAIFMT_LEFT_J: | |
1714 | break; | |
1715 | default: | |
1716 | return -EINVAL; | |
1717 | } | |
1718 | ||
1719 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1720 | case SND_SOC_DAIFMT_NB_NF: | |
1721 | break; | |
1722 | case SND_SOC_DAIFMT_NB_IF: | |
1723 | regval |= M98095_DAI_WCI; | |
1724 | break; | |
1725 | case SND_SOC_DAIFMT_IB_NF: | |
1726 | regval |= M98095_DAI_BCI; | |
1727 | break; | |
1728 | case SND_SOC_DAIFMT_IB_IF: | |
1729 | regval |= M98095_DAI_BCI|M98095_DAI_WCI; | |
1730 | break; | |
1731 | default: | |
1732 | return -EINVAL; | |
1733 | } | |
1734 | ||
1735 | snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, | |
1736 | M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | | |
1737 | M98095_DAI_WCI, regval); | |
1738 | ||
1739 | snd_soc_write(codec, M98095_03F_DAI3_CLOCK, | |
1740 | M98095_DAI_BSEL64); | |
1741 | } | |
1742 | ||
1743 | return 0; | |
1744 | } | |
1745 | ||
1746 | static int max98095_set_bias_level(struct snd_soc_codec *codec, | |
1747 | enum snd_soc_bias_level level) | |
1748 | { | |
1749 | int ret; | |
1750 | ||
1751 | switch (level) { | |
1752 | case SND_SOC_BIAS_ON: | |
1753 | break; | |
1754 | ||
1755 | case SND_SOC_BIAS_PREPARE: | |
1756 | break; | |
1757 | ||
1758 | case SND_SOC_BIAS_STANDBY: | |
1759 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { | |
1760 | ret = snd_soc_cache_sync(codec); | |
1761 | ||
1762 | if (ret != 0) { | |
1763 | dev_err(codec->dev, "Failed to sync cache: %d\n", ret); | |
1764 | return ret; | |
1765 | } | |
1766 | } | |
1767 | ||
1768 | snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, | |
1769 | M98095_MBEN, M98095_MBEN); | |
1770 | break; | |
1771 | ||
1772 | case SND_SOC_BIAS_OFF: | |
1773 | snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, | |
1774 | M98095_MBEN, 0); | |
1775 | codec->cache_sync = 1; | |
1776 | break; | |
1777 | } | |
1778 | codec->dapm.bias_level = level; | |
1779 | return 0; | |
1780 | } | |
1781 | ||
1782 | #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000 | |
1783 | #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) | |
1784 | ||
85e7652d | 1785 | static const struct snd_soc_dai_ops max98095_dai1_ops = { |
82a5a936 PH |
1786 | .set_sysclk = max98095_dai_set_sysclk, |
1787 | .set_fmt = max98095_dai1_set_fmt, | |
1788 | .hw_params = max98095_dai1_hw_params, | |
1789 | }; | |
1790 | ||
85e7652d | 1791 | static const struct snd_soc_dai_ops max98095_dai2_ops = { |
82a5a936 PH |
1792 | .set_sysclk = max98095_dai_set_sysclk, |
1793 | .set_fmt = max98095_dai2_set_fmt, | |
1794 | .hw_params = max98095_dai2_hw_params, | |
1795 | }; | |
1796 | ||
85e7652d | 1797 | static const struct snd_soc_dai_ops max98095_dai3_ops = { |
82a5a936 PH |
1798 | .set_sysclk = max98095_dai_set_sysclk, |
1799 | .set_fmt = max98095_dai3_set_fmt, | |
1800 | .hw_params = max98095_dai3_hw_params, | |
1801 | }; | |
1802 | ||
1803 | static struct snd_soc_dai_driver max98095_dai[] = { | |
1804 | { | |
1805 | .name = "HiFi", | |
1806 | .playback = { | |
1807 | .stream_name = "HiFi Playback", | |
1808 | .channels_min = 1, | |
1809 | .channels_max = 2, | |
1810 | .rates = MAX98095_RATES, | |
1811 | .formats = MAX98095_FORMATS, | |
1812 | }, | |
1813 | .capture = { | |
1814 | .stream_name = "HiFi Capture", | |
1815 | .channels_min = 1, | |
1816 | .channels_max = 2, | |
1817 | .rates = MAX98095_RATES, | |
1818 | .formats = MAX98095_FORMATS, | |
1819 | }, | |
1820 | .ops = &max98095_dai1_ops, | |
1821 | }, | |
1822 | { | |
1823 | .name = "Aux", | |
1824 | .playback = { | |
1825 | .stream_name = "Aux Playback", | |
1826 | .channels_min = 1, | |
1827 | .channels_max = 1, | |
1828 | .rates = MAX98095_RATES, | |
1829 | .formats = MAX98095_FORMATS, | |
1830 | }, | |
1831 | .ops = &max98095_dai2_ops, | |
1832 | }, | |
1833 | { | |
1834 | .name = "Voice", | |
1835 | .playback = { | |
1836 | .stream_name = "Voice Playback", | |
1837 | .channels_min = 1, | |
1838 | .channels_max = 1, | |
1839 | .rates = MAX98095_RATES, | |
1840 | .formats = MAX98095_FORMATS, | |
1841 | }, | |
1842 | .ops = &max98095_dai3_ops, | |
1843 | } | |
1844 | ||
1845 | }; | |
1846 | ||
dad31ec1 PH |
1847 | static int max98095_get_eq_channel(const char *name) |
1848 | { | |
1849 | if (strcmp(name, "EQ1 Mode") == 0) | |
1850 | return 0; | |
1851 | if (strcmp(name, "EQ2 Mode") == 0) | |
1852 | return 1; | |
1853 | return -EINVAL; | |
1854 | } | |
1855 | ||
1856 | static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol, | |
1857 | struct snd_ctl_elem_value *ucontrol) | |
1858 | { | |
1859 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
1860 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1861 | struct max98095_pdata *pdata = max98095->pdata; | |
1862 | int channel = max98095_get_eq_channel(kcontrol->id.name); | |
1863 | struct max98095_cdata *cdata; | |
1864 | int sel = ucontrol->value.integer.value[0]; | |
1865 | struct max98095_eq_cfg *coef_set; | |
1866 | int fs, best, best_val, i; | |
1867 | int regmask, regsave; | |
1868 | ||
1869 | BUG_ON(channel > 1); | |
1870 | ||
53949425 TH |
1871 | if (!pdata || !max98095->eq_textcnt) |
1872 | return 0; | |
dad31ec1 PH |
1873 | |
1874 | if (sel >= pdata->eq_cfgcnt) | |
1875 | return -EINVAL; | |
1876 | ||
53949425 | 1877 | cdata = &max98095->dai[channel]; |
dad31ec1 | 1878 | cdata->eq_sel = sel; |
dad31ec1 PH |
1879 | fs = cdata->rate; |
1880 | ||
1881 | /* Find the selected configuration with nearest sample rate */ | |
1882 | best = 0; | |
1883 | best_val = INT_MAX; | |
1884 | for (i = 0; i < pdata->eq_cfgcnt; i++) { | |
1885 | if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 && | |
1886 | abs(pdata->eq_cfg[i].rate - fs) < best_val) { | |
1887 | best = i; | |
1888 | best_val = abs(pdata->eq_cfg[i].rate - fs); | |
1889 | } | |
1890 | } | |
1891 | ||
1892 | dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", | |
1893 | pdata->eq_cfg[best].name, | |
1894 | pdata->eq_cfg[best].rate, fs); | |
1895 | ||
1896 | coef_set = &pdata->eq_cfg[best]; | |
1897 | ||
1898 | regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN; | |
1899 | ||
1900 | /* Disable filter while configuring, and save current on/off state */ | |
1901 | regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); | |
1902 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); | |
1903 | ||
1904 | mutex_lock(&codec->mutex); | |
1905 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); | |
1906 | m98095_eq_band(codec, channel, 0, coef_set->band1); | |
1907 | m98095_eq_band(codec, channel, 1, coef_set->band2); | |
1908 | m98095_eq_band(codec, channel, 2, coef_set->band3); | |
1909 | m98095_eq_band(codec, channel, 3, coef_set->band4); | |
1910 | m98095_eq_band(codec, channel, 4, coef_set->band5); | |
1911 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); | |
1912 | mutex_unlock(&codec->mutex); | |
1913 | ||
1914 | /* Restore the original on/off state */ | |
1915 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); | |
1916 | return 0; | |
1917 | } | |
1918 | ||
1919 | static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol, | |
1920 | struct snd_ctl_elem_value *ucontrol) | |
1921 | { | |
1922 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
1923 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1924 | int channel = max98095_get_eq_channel(kcontrol->id.name); | |
1925 | struct max98095_cdata *cdata; | |
1926 | ||
1927 | cdata = &max98095->dai[channel]; | |
1928 | ucontrol->value.enumerated.item[0] = cdata->eq_sel; | |
1929 | ||
1930 | return 0; | |
1931 | } | |
1932 | ||
1933 | static void max98095_handle_eq_pdata(struct snd_soc_codec *codec) | |
1934 | { | |
1935 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1936 | struct max98095_pdata *pdata = max98095->pdata; | |
1937 | struct max98095_eq_cfg *cfg; | |
1938 | unsigned int cfgcnt; | |
1939 | int i, j; | |
1940 | const char **t; | |
1941 | int ret; | |
1942 | ||
1943 | struct snd_kcontrol_new controls[] = { | |
1944 | SOC_ENUM_EXT("EQ1 Mode", | |
1945 | max98095->eq_enum, | |
1946 | max98095_get_eq_enum, | |
1947 | max98095_put_eq_enum), | |
1948 | SOC_ENUM_EXT("EQ2 Mode", | |
1949 | max98095->eq_enum, | |
1950 | max98095_get_eq_enum, | |
1951 | max98095_put_eq_enum), | |
1952 | }; | |
1953 | ||
1954 | cfg = pdata->eq_cfg; | |
1955 | cfgcnt = pdata->eq_cfgcnt; | |
1956 | ||
1957 | /* Setup an array of texts for the equalizer enum. | |
1958 | * This is based on Mark Brown's equalizer driver code. | |
1959 | */ | |
1960 | max98095->eq_textcnt = 0; | |
1961 | max98095->eq_texts = NULL; | |
1962 | for (i = 0; i < cfgcnt; i++) { | |
1963 | for (j = 0; j < max98095->eq_textcnt; j++) { | |
1964 | if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0) | |
1965 | break; | |
1966 | } | |
1967 | ||
1968 | if (j != max98095->eq_textcnt) | |
1969 | continue; | |
1970 | ||
1971 | /* Expand the array */ | |
1972 | t = krealloc(max98095->eq_texts, | |
1973 | sizeof(char *) * (max98095->eq_textcnt + 1), | |
1974 | GFP_KERNEL); | |
1975 | if (t == NULL) | |
1976 | continue; | |
1977 | ||
1978 | /* Store the new entry */ | |
1979 | t[max98095->eq_textcnt] = cfg[i].name; | |
1980 | max98095->eq_textcnt++; | |
1981 | max98095->eq_texts = t; | |
1982 | } | |
1983 | ||
1984 | /* Now point the soc_enum to .texts array items */ | |
1985 | max98095->eq_enum.texts = max98095->eq_texts; | |
1986 | max98095->eq_enum.max = max98095->eq_textcnt; | |
1987 | ||
1988 | ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls)); | |
1989 | if (ret != 0) | |
1990 | dev_err(codec->dev, "Failed to add EQ control: %d\n", ret); | |
1991 | } | |
1992 | ||
c855a1a7 RM |
1993 | static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"}; |
1994 | ||
1995 | static int max98095_get_bq_channel(struct snd_soc_codec *codec, | |
1996 | const char *name) | |
dad31ec1 | 1997 | { |
c855a1a7 RM |
1998 | int i; |
1999 | ||
2000 | for (i = 0; i < ARRAY_SIZE(bq_mode_name); i++) | |
2001 | if (strcmp(name, bq_mode_name[i]) == 0) | |
2002 | return i; | |
2003 | ||
2004 | /* Shouldn't happen */ | |
2005 | dev_err(codec->dev, "Bad biquad channel name '%s'\n", name); | |
dad31ec1 PH |
2006 | return -EINVAL; |
2007 | } | |
2008 | ||
2009 | static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol, | |
2010 | struct snd_ctl_elem_value *ucontrol) | |
2011 | { | |
2012 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
2013 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2014 | struct max98095_pdata *pdata = max98095->pdata; | |
c855a1a7 | 2015 | int channel = max98095_get_bq_channel(codec, kcontrol->id.name); |
dad31ec1 PH |
2016 | struct max98095_cdata *cdata; |
2017 | int sel = ucontrol->value.integer.value[0]; | |
2018 | struct max98095_biquad_cfg *coef_set; | |
2019 | int fs, best, best_val, i; | |
2020 | int regmask, regsave; | |
2021 | ||
c855a1a7 RM |
2022 | if (channel < 0) |
2023 | return channel; | |
dad31ec1 | 2024 | |
53949425 TH |
2025 | if (!pdata || !max98095->bq_textcnt) |
2026 | return 0; | |
dad31ec1 PH |
2027 | |
2028 | if (sel >= pdata->bq_cfgcnt) | |
2029 | return -EINVAL; | |
2030 | ||
53949425 | 2031 | cdata = &max98095->dai[channel]; |
dad31ec1 | 2032 | cdata->bq_sel = sel; |
dad31ec1 PH |
2033 | fs = cdata->rate; |
2034 | ||
2035 | /* Find the selected configuration with nearest sample rate */ | |
2036 | best = 0; | |
2037 | best_val = INT_MAX; | |
2038 | for (i = 0; i < pdata->bq_cfgcnt; i++) { | |
2039 | if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 && | |
2040 | abs(pdata->bq_cfg[i].rate - fs) < best_val) { | |
2041 | best = i; | |
2042 | best_val = abs(pdata->bq_cfg[i].rate - fs); | |
2043 | } | |
2044 | } | |
2045 | ||
2046 | dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", | |
2047 | pdata->bq_cfg[best].name, | |
2048 | pdata->bq_cfg[best].rate, fs); | |
2049 | ||
2050 | coef_set = &pdata->bq_cfg[best]; | |
2051 | ||
2052 | regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN; | |
2053 | ||
2054 | /* Disable filter while configuring, and save current on/off state */ | |
2055 | regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); | |
2056 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); | |
2057 | ||
2058 | mutex_lock(&codec->mutex); | |
2059 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); | |
2060 | m98095_biquad_band(codec, channel, 0, coef_set->band1); | |
2061 | m98095_biquad_band(codec, channel, 1, coef_set->band2); | |
2062 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); | |
2063 | mutex_unlock(&codec->mutex); | |
2064 | ||
2065 | /* Restore the original on/off state */ | |
2066 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); | |
2067 | return 0; | |
2068 | } | |
2069 | ||
2070 | static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol, | |
2071 | struct snd_ctl_elem_value *ucontrol) | |
2072 | { | |
2073 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
2074 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
c855a1a7 | 2075 | int channel = max98095_get_bq_channel(codec, kcontrol->id.name); |
dad31ec1 PH |
2076 | struct max98095_cdata *cdata; |
2077 | ||
c855a1a7 RM |
2078 | if (channel < 0) |
2079 | return channel; | |
2080 | ||
dad31ec1 PH |
2081 | cdata = &max98095->dai[channel]; |
2082 | ucontrol->value.enumerated.item[0] = cdata->bq_sel; | |
2083 | ||
2084 | return 0; | |
2085 | } | |
2086 | ||
2087 | static void max98095_handle_bq_pdata(struct snd_soc_codec *codec) | |
2088 | { | |
2089 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2090 | struct max98095_pdata *pdata = max98095->pdata; | |
2091 | struct max98095_biquad_cfg *cfg; | |
2092 | unsigned int cfgcnt; | |
2093 | int i, j; | |
2094 | const char **t; | |
2095 | int ret; | |
2096 | ||
2097 | struct snd_kcontrol_new controls[] = { | |
c855a1a7 | 2098 | SOC_ENUM_EXT((char *)bq_mode_name[0], |
dad31ec1 PH |
2099 | max98095->bq_enum, |
2100 | max98095_get_bq_enum, | |
2101 | max98095_put_bq_enum), | |
c855a1a7 | 2102 | SOC_ENUM_EXT((char *)bq_mode_name[1], |
dad31ec1 PH |
2103 | max98095->bq_enum, |
2104 | max98095_get_bq_enum, | |
2105 | max98095_put_bq_enum), | |
2106 | }; | |
c855a1a7 | 2107 | BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name)); |
dad31ec1 PH |
2108 | |
2109 | cfg = pdata->bq_cfg; | |
2110 | cfgcnt = pdata->bq_cfgcnt; | |
2111 | ||
2112 | /* Setup an array of texts for the biquad enum. | |
2113 | * This is based on Mark Brown's equalizer driver code. | |
2114 | */ | |
2115 | max98095->bq_textcnt = 0; | |
2116 | max98095->bq_texts = NULL; | |
2117 | for (i = 0; i < cfgcnt; i++) { | |
2118 | for (j = 0; j < max98095->bq_textcnt; j++) { | |
2119 | if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0) | |
2120 | break; | |
2121 | } | |
2122 | ||
2123 | if (j != max98095->bq_textcnt) | |
2124 | continue; | |
2125 | ||
2126 | /* Expand the array */ | |
2127 | t = krealloc(max98095->bq_texts, | |
2128 | sizeof(char *) * (max98095->bq_textcnt + 1), | |
2129 | GFP_KERNEL); | |
2130 | if (t == NULL) | |
2131 | continue; | |
2132 | ||
2133 | /* Store the new entry */ | |
2134 | t[max98095->bq_textcnt] = cfg[i].name; | |
2135 | max98095->bq_textcnt++; | |
2136 | max98095->bq_texts = t; | |
2137 | } | |
2138 | ||
2139 | /* Now point the soc_enum to .texts array items */ | |
2140 | max98095->bq_enum.texts = max98095->bq_texts; | |
2141 | max98095->bq_enum.max = max98095->bq_textcnt; | |
2142 | ||
2143 | ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls)); | |
2144 | if (ret != 0) | |
2145 | dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret); | |
2146 | } | |
2147 | ||
82a5a936 PH |
2148 | static void max98095_handle_pdata(struct snd_soc_codec *codec) |
2149 | { | |
2150 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2151 | struct max98095_pdata *pdata = max98095->pdata; | |
2152 | u8 regval = 0; | |
2153 | ||
2154 | if (!pdata) { | |
2155 | dev_dbg(codec->dev, "No platform data\n"); | |
2156 | return; | |
2157 | } | |
2158 | ||
2159 | /* Configure mic for analog/digital mic mode */ | |
2160 | if (pdata->digmic_left_mode) | |
2161 | regval |= M98095_DIGMIC_L; | |
2162 | ||
2163 | if (pdata->digmic_right_mode) | |
2164 | regval |= M98095_DIGMIC_R; | |
2165 | ||
2166 | snd_soc_write(codec, M98095_087_CFG_MIC, regval); | |
dad31ec1 PH |
2167 | |
2168 | /* Configure equalizers */ | |
2169 | if (pdata->eq_cfgcnt) | |
2170 | max98095_handle_eq_pdata(codec); | |
2171 | ||
2172 | /* Configure bi-quad filters */ | |
2173 | if (pdata->bq_cfgcnt) | |
2174 | max98095_handle_bq_pdata(codec); | |
82a5a936 PH |
2175 | } |
2176 | ||
2177 | #ifdef CONFIG_PM | |
2178 | static int max98095_suspend(struct snd_soc_codec *codec, pm_message_t state) | |
2179 | { | |
2180 | max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
2181 | ||
2182 | return 0; | |
2183 | } | |
2184 | ||
2185 | static int max98095_resume(struct snd_soc_codec *codec) | |
2186 | { | |
2187 | max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
2188 | ||
2189 | return 0; | |
2190 | } | |
2191 | #else | |
2192 | #define max98095_suspend NULL | |
2193 | #define max98095_resume NULL | |
2194 | #endif | |
2195 | ||
2196 | static int max98095_reset(struct snd_soc_codec *codec) | |
2197 | { | |
2198 | int i, ret; | |
2199 | ||
2200 | /* Gracefully reset the DSP core and the codec hardware | |
2201 | * in a proper sequence */ | |
2202 | ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0); | |
2203 | if (ret < 0) { | |
2204 | dev_err(codec->dev, "Failed to reset DSP: %d\n", ret); | |
2205 | return ret; | |
2206 | } | |
2207 | ||
2208 | ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0); | |
2209 | if (ret < 0) { | |
2210 | dev_err(codec->dev, "Failed to reset codec: %d\n", ret); | |
2211 | return ret; | |
2212 | } | |
2213 | ||
2214 | /* Reset to hardware default for registers, as there is not | |
2215 | * a soft reset hardware control register */ | |
2216 | for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) { | |
2217 | ret = snd_soc_write(codec, i, max98095_reg_def[i]); | |
2218 | if (ret < 0) { | |
2219 | dev_err(codec->dev, "Failed to reset: %d\n", ret); | |
2220 | return ret; | |
2221 | } | |
2222 | } | |
2223 | ||
2224 | return ret; | |
2225 | } | |
2226 | ||
2227 | static int max98095_probe(struct snd_soc_codec *codec) | |
2228 | { | |
2229 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2230 | struct max98095_cdata *cdata; | |
2231 | int ret = 0; | |
2232 | ||
2233 | ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); | |
2234 | if (ret != 0) { | |
2235 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
2236 | return ret; | |
2237 | } | |
2238 | ||
2239 | /* reset the codec, the DSP core, and disable all interrupts */ | |
2240 | max98095_reset(codec); | |
2241 | ||
2242 | /* initialize private data */ | |
2243 | ||
2244 | max98095->sysclk = (unsigned)-1; | |
dad31ec1 PH |
2245 | max98095->eq_textcnt = 0; |
2246 | max98095->bq_textcnt = 0; | |
82a5a936 PH |
2247 | |
2248 | cdata = &max98095->dai[0]; | |
2249 | cdata->rate = (unsigned)-1; | |
2250 | cdata->fmt = (unsigned)-1; | |
dad31ec1 PH |
2251 | cdata->eq_sel = 0; |
2252 | cdata->bq_sel = 0; | |
82a5a936 PH |
2253 | |
2254 | cdata = &max98095->dai[1]; | |
2255 | cdata->rate = (unsigned)-1; | |
2256 | cdata->fmt = (unsigned)-1; | |
dad31ec1 PH |
2257 | cdata->eq_sel = 0; |
2258 | cdata->bq_sel = 0; | |
82a5a936 PH |
2259 | |
2260 | cdata = &max98095->dai[2]; | |
2261 | cdata->rate = (unsigned)-1; | |
2262 | cdata->fmt = (unsigned)-1; | |
dad31ec1 PH |
2263 | cdata->eq_sel = 0; |
2264 | cdata->bq_sel = 0; | |
82a5a936 PH |
2265 | |
2266 | max98095->lin_state = 0; | |
2267 | max98095->mic1pre = 0; | |
2268 | max98095->mic2pre = 0; | |
2269 | ||
2270 | ret = snd_soc_read(codec, M98095_0FF_REV_ID); | |
2271 | if (ret < 0) { | |
bab3b59d | 2272 | dev_err(codec->dev, "Failure reading hardware revision: %d\n", |
82a5a936 PH |
2273 | ret); |
2274 | goto err_access; | |
2275 | } | |
bab3b59d | 2276 | dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A'); |
82a5a936 PH |
2277 | |
2278 | snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV); | |
2279 | ||
2280 | /* initialize registers cache to hardware default */ | |
2281 | max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
2282 | ||
2283 | snd_soc_write(codec, M98095_048_MIX_DAC_LR, | |
2284 | M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR); | |
2285 | ||
2286 | snd_soc_write(codec, M98095_049_MIX_DAC_M, | |
2287 | M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM); | |
2288 | ||
2289 | snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM); | |
2290 | snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL); | |
2291 | snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL); | |
2292 | ||
2293 | snd_soc_write(codec, M98095_02C_DAI1_IOCFG, | |
2294 | M98095_S1NORMAL|M98095_SDATA); | |
2295 | ||
2296 | snd_soc_write(codec, M98095_036_DAI2_IOCFG, | |
2297 | M98095_S2NORMAL|M98095_SDATA); | |
2298 | ||
2299 | snd_soc_write(codec, M98095_040_DAI3_IOCFG, | |
2300 | M98095_S3NORMAL|M98095_SDATA); | |
2301 | ||
2302 | max98095_handle_pdata(codec); | |
2303 | ||
2304 | /* take the codec out of the shut down */ | |
2305 | snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN, | |
2306 | M98095_SHDNRUN); | |
2307 | ||
2308 | max98095_add_widgets(codec); | |
2309 | ||
2310 | err_access: | |
2311 | return ret; | |
2312 | } | |
2313 | ||
2314 | static int max98095_remove(struct snd_soc_codec *codec) | |
2315 | { | |
2316 | max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
2317 | ||
2318 | return 0; | |
2319 | } | |
2320 | ||
2321 | static struct snd_soc_codec_driver soc_codec_dev_max98095 = { | |
2322 | .probe = max98095_probe, | |
2323 | .remove = max98095_remove, | |
2324 | .suspend = max98095_suspend, | |
2325 | .resume = max98095_resume, | |
2326 | .set_bias_level = max98095_set_bias_level, | |
2327 | .reg_cache_size = ARRAY_SIZE(max98095_reg_def), | |
2328 | .reg_word_size = sizeof(u8), | |
2329 | .reg_cache_default = max98095_reg_def, | |
2330 | .readable_register = max98095_readable, | |
2331 | .volatile_register = max98095_volatile, | |
2332 | .dapm_widgets = max98095_dapm_widgets, | |
2333 | .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets), | |
2334 | .dapm_routes = max98095_audio_map, | |
2335 | .num_dapm_routes = ARRAY_SIZE(max98095_audio_map), | |
2336 | }; | |
2337 | ||
2338 | static int max98095_i2c_probe(struct i2c_client *i2c, | |
2339 | const struct i2c_device_id *id) | |
2340 | { | |
2341 | struct max98095_priv *max98095; | |
2342 | int ret; | |
2343 | ||
2344 | max98095 = kzalloc(sizeof(struct max98095_priv), GFP_KERNEL); | |
2345 | if (max98095 == NULL) | |
2346 | return -ENOMEM; | |
2347 | ||
2348 | max98095->devtype = id->driver_data; | |
2349 | i2c_set_clientdata(i2c, max98095); | |
82a5a936 PH |
2350 | max98095->pdata = i2c->dev.platform_data; |
2351 | ||
bab3b59d TH |
2352 | ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98095, |
2353 | max98095_dai, ARRAY_SIZE(max98095_dai)); | |
82a5a936 PH |
2354 | if (ret < 0) |
2355 | kfree(max98095); | |
2356 | return ret; | |
2357 | } | |
2358 | ||
2359 | static int __devexit max98095_i2c_remove(struct i2c_client *client) | |
2360 | { | |
2361 | snd_soc_unregister_codec(&client->dev); | |
2362 | kfree(i2c_get_clientdata(client)); | |
2363 | ||
2364 | return 0; | |
2365 | } | |
2366 | ||
2367 | static const struct i2c_device_id max98095_i2c_id[] = { | |
2368 | { "max98095", MAX98095 }, | |
2369 | { } | |
2370 | }; | |
2371 | MODULE_DEVICE_TABLE(i2c, max98095_i2c_id); | |
2372 | ||
2373 | static struct i2c_driver max98095_i2c_driver = { | |
2374 | .driver = { | |
2375 | .name = "max98095", | |
2376 | .owner = THIS_MODULE, | |
2377 | }, | |
2378 | .probe = max98095_i2c_probe, | |
2379 | .remove = __devexit_p(max98095_i2c_remove), | |
2380 | .id_table = max98095_i2c_id, | |
2381 | }; | |
2382 | ||
2383 | static int __init max98095_init(void) | |
2384 | { | |
2385 | int ret; | |
2386 | ||
2387 | ret = i2c_add_driver(&max98095_i2c_driver); | |
2388 | if (ret) | |
2389 | pr_err("Failed to register max98095 I2C driver: %d\n", ret); | |
2390 | ||
2391 | return ret; | |
2392 | } | |
2393 | module_init(max98095_init); | |
2394 | ||
2395 | static void __exit max98095_exit(void) | |
2396 | { | |
2397 | i2c_del_driver(&max98095_i2c_driver); | |
2398 | } | |
2399 | module_exit(max98095_exit); | |
2400 | ||
2401 | MODULE_DESCRIPTION("ALSA SoC MAX98095 driver"); | |
2402 | MODULE_AUTHOR("Peter Hsiang"); | |
2403 | MODULE_LICENSE("GPL"); |