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82a5a936 PH |
1 | /* |
2 | * max98095.c -- MAX98095 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2011 Maxim Integrated Products | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <sound/core.h> | |
20 | #include <sound/pcm.h> | |
21 | #include <sound/pcm_params.h> | |
22 | #include <sound/soc.h> | |
23 | #include <sound/initval.h> | |
24 | #include <sound/tlv.h> | |
25 | #include <linux/slab.h> | |
26 | #include <asm/div64.h> | |
27 | #include <sound/max98095.h> | |
28 | #include "max98095.h" | |
29 | ||
30 | enum max98095_type { | |
31 | MAX98095, | |
32 | }; | |
33 | ||
34 | struct max98095_cdata { | |
35 | unsigned int rate; | |
36 | unsigned int fmt; | |
dad31ec1 PH |
37 | int eq_sel; |
38 | int bq_sel; | |
82a5a936 PH |
39 | }; |
40 | ||
41 | struct max98095_priv { | |
42 | enum max98095_type devtype; | |
82a5a936 PH |
43 | struct max98095_pdata *pdata; |
44 | unsigned int sysclk; | |
45 | struct max98095_cdata dai[3]; | |
dad31ec1 PH |
46 | const char **eq_texts; |
47 | const char **bq_texts; | |
48 | struct soc_enum eq_enum; | |
49 | struct soc_enum bq_enum; | |
50 | int eq_textcnt; | |
51 | int bq_textcnt; | |
82a5a936 PH |
52 | u8 lin_state; |
53 | unsigned int mic1pre; | |
54 | unsigned int mic2pre; | |
55 | }; | |
56 | ||
57 | static const u8 max98095_reg_def[M98095_REG_CNT] = { | |
58 | 0x00, /* 00 */ | |
59 | 0x00, /* 01 */ | |
60 | 0x00, /* 02 */ | |
61 | 0x00, /* 03 */ | |
62 | 0x00, /* 04 */ | |
63 | 0x00, /* 05 */ | |
64 | 0x00, /* 06 */ | |
65 | 0x00, /* 07 */ | |
66 | 0x00, /* 08 */ | |
67 | 0x00, /* 09 */ | |
68 | 0x00, /* 0A */ | |
69 | 0x00, /* 0B */ | |
70 | 0x00, /* 0C */ | |
71 | 0x00, /* 0D */ | |
72 | 0x00, /* 0E */ | |
73 | 0x00, /* 0F */ | |
74 | 0x00, /* 10 */ | |
75 | 0x00, /* 11 */ | |
76 | 0x00, /* 12 */ | |
77 | 0x00, /* 13 */ | |
78 | 0x00, /* 14 */ | |
79 | 0x00, /* 15 */ | |
80 | 0x00, /* 16 */ | |
81 | 0x00, /* 17 */ | |
82 | 0x00, /* 18 */ | |
83 | 0x00, /* 19 */ | |
84 | 0x00, /* 1A */ | |
85 | 0x00, /* 1B */ | |
86 | 0x00, /* 1C */ | |
87 | 0x00, /* 1D */ | |
88 | 0x00, /* 1E */ | |
89 | 0x00, /* 1F */ | |
90 | 0x00, /* 20 */ | |
91 | 0x00, /* 21 */ | |
92 | 0x00, /* 22 */ | |
93 | 0x00, /* 23 */ | |
94 | 0x00, /* 24 */ | |
95 | 0x00, /* 25 */ | |
96 | 0x00, /* 26 */ | |
97 | 0x00, /* 27 */ | |
98 | 0x00, /* 28 */ | |
99 | 0x00, /* 29 */ | |
100 | 0x00, /* 2A */ | |
101 | 0x00, /* 2B */ | |
102 | 0x00, /* 2C */ | |
103 | 0x00, /* 2D */ | |
104 | 0x00, /* 2E */ | |
105 | 0x00, /* 2F */ | |
106 | 0x00, /* 30 */ | |
107 | 0x00, /* 31 */ | |
108 | 0x00, /* 32 */ | |
109 | 0x00, /* 33 */ | |
110 | 0x00, /* 34 */ | |
111 | 0x00, /* 35 */ | |
112 | 0x00, /* 36 */ | |
113 | 0x00, /* 37 */ | |
114 | 0x00, /* 38 */ | |
115 | 0x00, /* 39 */ | |
116 | 0x00, /* 3A */ | |
117 | 0x00, /* 3B */ | |
118 | 0x00, /* 3C */ | |
119 | 0x00, /* 3D */ | |
120 | 0x00, /* 3E */ | |
121 | 0x00, /* 3F */ | |
122 | 0x00, /* 40 */ | |
123 | 0x00, /* 41 */ | |
124 | 0x00, /* 42 */ | |
125 | 0x00, /* 43 */ | |
126 | 0x00, /* 44 */ | |
127 | 0x00, /* 45 */ | |
128 | 0x00, /* 46 */ | |
129 | 0x00, /* 47 */ | |
130 | 0x00, /* 48 */ | |
131 | 0x00, /* 49 */ | |
132 | 0x00, /* 4A */ | |
133 | 0x00, /* 4B */ | |
134 | 0x00, /* 4C */ | |
135 | 0x00, /* 4D */ | |
136 | 0x00, /* 4E */ | |
137 | 0x00, /* 4F */ | |
138 | 0x00, /* 50 */ | |
139 | 0x00, /* 51 */ | |
140 | 0x00, /* 52 */ | |
141 | 0x00, /* 53 */ | |
142 | 0x00, /* 54 */ | |
143 | 0x00, /* 55 */ | |
144 | 0x00, /* 56 */ | |
145 | 0x00, /* 57 */ | |
146 | 0x00, /* 58 */ | |
147 | 0x00, /* 59 */ | |
148 | 0x00, /* 5A */ | |
149 | 0x00, /* 5B */ | |
150 | 0x00, /* 5C */ | |
151 | 0x00, /* 5D */ | |
152 | 0x00, /* 5E */ | |
153 | 0x00, /* 5F */ | |
154 | 0x00, /* 60 */ | |
155 | 0x00, /* 61 */ | |
156 | 0x00, /* 62 */ | |
157 | 0x00, /* 63 */ | |
158 | 0x00, /* 64 */ | |
159 | 0x00, /* 65 */ | |
160 | 0x00, /* 66 */ | |
161 | 0x00, /* 67 */ | |
162 | 0x00, /* 68 */ | |
163 | 0x00, /* 69 */ | |
164 | 0x00, /* 6A */ | |
165 | 0x00, /* 6B */ | |
166 | 0x00, /* 6C */ | |
167 | 0x00, /* 6D */ | |
168 | 0x00, /* 6E */ | |
169 | 0x00, /* 6F */ | |
170 | 0x00, /* 70 */ | |
171 | 0x00, /* 71 */ | |
172 | 0x00, /* 72 */ | |
173 | 0x00, /* 73 */ | |
174 | 0x00, /* 74 */ | |
175 | 0x00, /* 75 */ | |
176 | 0x00, /* 76 */ | |
177 | 0x00, /* 77 */ | |
178 | 0x00, /* 78 */ | |
179 | 0x00, /* 79 */ | |
180 | 0x00, /* 7A */ | |
181 | 0x00, /* 7B */ | |
182 | 0x00, /* 7C */ | |
183 | 0x00, /* 7D */ | |
184 | 0x00, /* 7E */ | |
185 | 0x00, /* 7F */ | |
186 | 0x00, /* 80 */ | |
187 | 0x00, /* 81 */ | |
188 | 0x00, /* 82 */ | |
189 | 0x00, /* 83 */ | |
190 | 0x00, /* 84 */ | |
191 | 0x00, /* 85 */ | |
192 | 0x00, /* 86 */ | |
193 | 0x00, /* 87 */ | |
194 | 0x00, /* 88 */ | |
195 | 0x00, /* 89 */ | |
196 | 0x00, /* 8A */ | |
197 | 0x00, /* 8B */ | |
198 | 0x00, /* 8C */ | |
199 | 0x00, /* 8D */ | |
200 | 0x00, /* 8E */ | |
201 | 0x00, /* 8F */ | |
202 | 0x00, /* 90 */ | |
203 | 0x00, /* 91 */ | |
204 | 0x30, /* 92 */ | |
205 | 0xF0, /* 93 */ | |
206 | 0x00, /* 94 */ | |
207 | 0x00, /* 95 */ | |
208 | 0x3F, /* 96 */ | |
209 | 0x00, /* 97 */ | |
210 | 0x00, /* 98 */ | |
211 | 0x00, /* 99 */ | |
212 | 0x00, /* 9A */ | |
213 | 0x00, /* 9B */ | |
214 | 0x00, /* 9C */ | |
215 | 0x00, /* 9D */ | |
216 | 0x00, /* 9E */ | |
217 | 0x00, /* 9F */ | |
218 | 0x00, /* A0 */ | |
219 | 0x00, /* A1 */ | |
220 | 0x00, /* A2 */ | |
221 | 0x00, /* A3 */ | |
222 | 0x00, /* A4 */ | |
223 | 0x00, /* A5 */ | |
224 | 0x00, /* A6 */ | |
225 | 0x00, /* A7 */ | |
226 | 0x00, /* A8 */ | |
227 | 0x00, /* A9 */ | |
228 | 0x00, /* AA */ | |
229 | 0x00, /* AB */ | |
230 | 0x00, /* AC */ | |
231 | 0x00, /* AD */ | |
232 | 0x00, /* AE */ | |
233 | 0x00, /* AF */ | |
234 | 0x00, /* B0 */ | |
235 | 0x00, /* B1 */ | |
236 | 0x00, /* B2 */ | |
237 | 0x00, /* B3 */ | |
238 | 0x00, /* B4 */ | |
239 | 0x00, /* B5 */ | |
240 | 0x00, /* B6 */ | |
241 | 0x00, /* B7 */ | |
242 | 0x00, /* B8 */ | |
243 | 0x00, /* B9 */ | |
244 | 0x00, /* BA */ | |
245 | 0x00, /* BB */ | |
246 | 0x00, /* BC */ | |
247 | 0x00, /* BD */ | |
248 | 0x00, /* BE */ | |
249 | 0x00, /* BF */ | |
250 | 0x00, /* C0 */ | |
251 | 0x00, /* C1 */ | |
252 | 0x00, /* C2 */ | |
253 | 0x00, /* C3 */ | |
254 | 0x00, /* C4 */ | |
255 | 0x00, /* C5 */ | |
256 | 0x00, /* C6 */ | |
257 | 0x00, /* C7 */ | |
258 | 0x00, /* C8 */ | |
259 | 0x00, /* C9 */ | |
260 | 0x00, /* CA */ | |
261 | 0x00, /* CB */ | |
262 | 0x00, /* CC */ | |
263 | 0x00, /* CD */ | |
264 | 0x00, /* CE */ | |
265 | 0x00, /* CF */ | |
266 | 0x00, /* D0 */ | |
267 | 0x00, /* D1 */ | |
268 | 0x00, /* D2 */ | |
269 | 0x00, /* D3 */ | |
270 | 0x00, /* D4 */ | |
271 | 0x00, /* D5 */ | |
272 | 0x00, /* D6 */ | |
273 | 0x00, /* D7 */ | |
274 | 0x00, /* D8 */ | |
275 | 0x00, /* D9 */ | |
276 | 0x00, /* DA */ | |
277 | 0x00, /* DB */ | |
278 | 0x00, /* DC */ | |
279 | 0x00, /* DD */ | |
280 | 0x00, /* DE */ | |
281 | 0x00, /* DF */ | |
282 | 0x00, /* E0 */ | |
283 | 0x00, /* E1 */ | |
284 | 0x00, /* E2 */ | |
285 | 0x00, /* E3 */ | |
286 | 0x00, /* E4 */ | |
287 | 0x00, /* E5 */ | |
288 | 0x00, /* E6 */ | |
289 | 0x00, /* E7 */ | |
290 | 0x00, /* E8 */ | |
291 | 0x00, /* E9 */ | |
292 | 0x00, /* EA */ | |
293 | 0x00, /* EB */ | |
294 | 0x00, /* EC */ | |
295 | 0x00, /* ED */ | |
296 | 0x00, /* EE */ | |
297 | 0x00, /* EF */ | |
298 | 0x00, /* F0 */ | |
299 | 0x00, /* F1 */ | |
300 | 0x00, /* F2 */ | |
301 | 0x00, /* F3 */ | |
302 | 0x00, /* F4 */ | |
303 | 0x00, /* F5 */ | |
304 | 0x00, /* F6 */ | |
305 | 0x00, /* F7 */ | |
306 | 0x00, /* F8 */ | |
307 | 0x00, /* F9 */ | |
308 | 0x00, /* FA */ | |
309 | 0x00, /* FB */ | |
310 | 0x00, /* FC */ | |
311 | 0x00, /* FD */ | |
312 | 0x00, /* FE */ | |
313 | 0x00, /* FF */ | |
314 | }; | |
315 | ||
316 | static struct { | |
317 | int readable; | |
318 | int writable; | |
319 | } max98095_access[M98095_REG_CNT] = { | |
320 | { 0x00, 0x00 }, /* 00 */ | |
321 | { 0xFF, 0x00 }, /* 01 */ | |
322 | { 0xFF, 0x00 }, /* 02 */ | |
323 | { 0xFF, 0x00 }, /* 03 */ | |
324 | { 0xFF, 0x00 }, /* 04 */ | |
325 | { 0xFF, 0x00 }, /* 05 */ | |
326 | { 0xFF, 0x00 }, /* 06 */ | |
327 | { 0xFF, 0x00 }, /* 07 */ | |
328 | { 0xFF, 0x00 }, /* 08 */ | |
329 | { 0xFF, 0x00 }, /* 09 */ | |
330 | { 0xFF, 0x00 }, /* 0A */ | |
331 | { 0xFF, 0x00 }, /* 0B */ | |
332 | { 0xFF, 0x00 }, /* 0C */ | |
333 | { 0xFF, 0x00 }, /* 0D */ | |
334 | { 0xFF, 0x00 }, /* 0E */ | |
335 | { 0xFF, 0x9F }, /* 0F */ | |
336 | { 0xFF, 0xFF }, /* 10 */ | |
337 | { 0xFF, 0xFF }, /* 11 */ | |
338 | { 0xFF, 0xFF }, /* 12 */ | |
339 | { 0xFF, 0xFF }, /* 13 */ | |
340 | { 0xFF, 0xFF }, /* 14 */ | |
341 | { 0xFF, 0xFF }, /* 15 */ | |
342 | { 0xFF, 0xFF }, /* 16 */ | |
343 | { 0xFF, 0xFF }, /* 17 */ | |
344 | { 0xFF, 0xFF }, /* 18 */ | |
345 | { 0xFF, 0xFF }, /* 19 */ | |
346 | { 0xFF, 0xFF }, /* 1A */ | |
347 | { 0xFF, 0xFF }, /* 1B */ | |
348 | { 0xFF, 0xFF }, /* 1C */ | |
349 | { 0xFF, 0xFF }, /* 1D */ | |
350 | { 0xFF, 0x77 }, /* 1E */ | |
351 | { 0xFF, 0x77 }, /* 1F */ | |
352 | { 0xFF, 0x77 }, /* 20 */ | |
353 | { 0xFF, 0x77 }, /* 21 */ | |
354 | { 0xFF, 0x77 }, /* 22 */ | |
355 | { 0xFF, 0x77 }, /* 23 */ | |
356 | { 0xFF, 0xFF }, /* 24 */ | |
357 | { 0xFF, 0x7F }, /* 25 */ | |
358 | { 0xFF, 0x31 }, /* 26 */ | |
359 | { 0xFF, 0xFF }, /* 27 */ | |
360 | { 0xFF, 0xFF }, /* 28 */ | |
361 | { 0xFF, 0xFF }, /* 29 */ | |
362 | { 0xFF, 0xF7 }, /* 2A */ | |
363 | { 0xFF, 0x2F }, /* 2B */ | |
364 | { 0xFF, 0xEF }, /* 2C */ | |
365 | { 0xFF, 0xFF }, /* 2D */ | |
366 | { 0xFF, 0xFF }, /* 2E */ | |
367 | { 0xFF, 0xFF }, /* 2F */ | |
368 | { 0xFF, 0xFF }, /* 30 */ | |
369 | { 0xFF, 0xFF }, /* 31 */ | |
370 | { 0xFF, 0xFF }, /* 32 */ | |
371 | { 0xFF, 0xFF }, /* 33 */ | |
372 | { 0xFF, 0xF7 }, /* 34 */ | |
373 | { 0xFF, 0x2F }, /* 35 */ | |
374 | { 0xFF, 0xCF }, /* 36 */ | |
375 | { 0xFF, 0xFF }, /* 37 */ | |
376 | { 0xFF, 0xFF }, /* 38 */ | |
377 | { 0xFF, 0xFF }, /* 39 */ | |
378 | { 0xFF, 0xFF }, /* 3A */ | |
379 | { 0xFF, 0xFF }, /* 3B */ | |
380 | { 0xFF, 0xFF }, /* 3C */ | |
381 | { 0xFF, 0xFF }, /* 3D */ | |
382 | { 0xFF, 0xF7 }, /* 3E */ | |
383 | { 0xFF, 0x2F }, /* 3F */ | |
384 | { 0xFF, 0xCF }, /* 40 */ | |
385 | { 0xFF, 0xFF }, /* 41 */ | |
386 | { 0xFF, 0x77 }, /* 42 */ | |
387 | { 0xFF, 0xFF }, /* 43 */ | |
388 | { 0xFF, 0xFF }, /* 44 */ | |
389 | { 0xFF, 0xFF }, /* 45 */ | |
390 | { 0xFF, 0xFF }, /* 46 */ | |
391 | { 0xFF, 0xFF }, /* 47 */ | |
392 | { 0xFF, 0xFF }, /* 48 */ | |
393 | { 0xFF, 0x0F }, /* 49 */ | |
394 | { 0xFF, 0xFF }, /* 4A */ | |
395 | { 0xFF, 0xFF }, /* 4B */ | |
396 | { 0xFF, 0x3F }, /* 4C */ | |
397 | { 0xFF, 0x3F }, /* 4D */ | |
398 | { 0xFF, 0x3F }, /* 4E */ | |
399 | { 0xFF, 0xFF }, /* 4F */ | |
400 | { 0xFF, 0x7F }, /* 50 */ | |
401 | { 0xFF, 0x7F }, /* 51 */ | |
402 | { 0xFF, 0x0F }, /* 52 */ | |
403 | { 0xFF, 0x3F }, /* 53 */ | |
404 | { 0xFF, 0x3F }, /* 54 */ | |
405 | { 0xFF, 0x3F }, /* 55 */ | |
406 | { 0xFF, 0xFF }, /* 56 */ | |
407 | { 0xFF, 0xFF }, /* 57 */ | |
408 | { 0xFF, 0xBF }, /* 58 */ | |
409 | { 0xFF, 0x1F }, /* 59 */ | |
410 | { 0xFF, 0xBF }, /* 5A */ | |
411 | { 0xFF, 0x1F }, /* 5B */ | |
412 | { 0xFF, 0xBF }, /* 5C */ | |
413 | { 0xFF, 0x3F }, /* 5D */ | |
414 | { 0xFF, 0x3F }, /* 5E */ | |
415 | { 0xFF, 0x7F }, /* 5F */ | |
416 | { 0xFF, 0x7F }, /* 60 */ | |
417 | { 0xFF, 0x47 }, /* 61 */ | |
418 | { 0xFF, 0x9F }, /* 62 */ | |
419 | { 0xFF, 0x9F }, /* 63 */ | |
420 | { 0xFF, 0x9F }, /* 64 */ | |
421 | { 0xFF, 0x9F }, /* 65 */ | |
422 | { 0xFF, 0x9F }, /* 66 */ | |
423 | { 0xFF, 0xBF }, /* 67 */ | |
424 | { 0xFF, 0xBF }, /* 68 */ | |
425 | { 0xFF, 0xFF }, /* 69 */ | |
426 | { 0xFF, 0xFF }, /* 6A */ | |
427 | { 0xFF, 0x7F }, /* 6B */ | |
428 | { 0xFF, 0xF7 }, /* 6C */ | |
429 | { 0xFF, 0xFF }, /* 6D */ | |
430 | { 0xFF, 0xFF }, /* 6E */ | |
431 | { 0xFF, 0x1F }, /* 6F */ | |
432 | { 0xFF, 0xF7 }, /* 70 */ | |
433 | { 0xFF, 0xFF }, /* 71 */ | |
434 | { 0xFF, 0xFF }, /* 72 */ | |
435 | { 0xFF, 0x1F }, /* 73 */ | |
436 | { 0xFF, 0xF7 }, /* 74 */ | |
437 | { 0xFF, 0xFF }, /* 75 */ | |
438 | { 0xFF, 0xFF }, /* 76 */ | |
439 | { 0xFF, 0x1F }, /* 77 */ | |
440 | { 0xFF, 0xF7 }, /* 78 */ | |
441 | { 0xFF, 0xFF }, /* 79 */ | |
442 | { 0xFF, 0xFF }, /* 7A */ | |
443 | { 0xFF, 0x1F }, /* 7B */ | |
444 | { 0xFF, 0xF7 }, /* 7C */ | |
445 | { 0xFF, 0xFF }, /* 7D */ | |
446 | { 0xFF, 0xFF }, /* 7E */ | |
447 | { 0xFF, 0x1F }, /* 7F */ | |
448 | { 0xFF, 0xF7 }, /* 80 */ | |
449 | { 0xFF, 0xFF }, /* 81 */ | |
450 | { 0xFF, 0xFF }, /* 82 */ | |
451 | { 0xFF, 0x1F }, /* 83 */ | |
452 | { 0xFF, 0x7F }, /* 84 */ | |
453 | { 0xFF, 0x0F }, /* 85 */ | |
454 | { 0xFF, 0xD8 }, /* 86 */ | |
455 | { 0xFF, 0xFF }, /* 87 */ | |
456 | { 0xFF, 0xEF }, /* 88 */ | |
457 | { 0xFF, 0xFE }, /* 89 */ | |
458 | { 0xFF, 0xFE }, /* 8A */ | |
459 | { 0xFF, 0xFF }, /* 8B */ | |
460 | { 0xFF, 0xFF }, /* 8C */ | |
461 | { 0xFF, 0x3F }, /* 8D */ | |
462 | { 0xFF, 0xFF }, /* 8E */ | |
463 | { 0xFF, 0x3F }, /* 8F */ | |
464 | { 0xFF, 0x8F }, /* 90 */ | |
465 | { 0xFF, 0xFF }, /* 91 */ | |
466 | { 0xFF, 0x3F }, /* 92 */ | |
467 | { 0xFF, 0xFF }, /* 93 */ | |
468 | { 0xFF, 0xFF }, /* 94 */ | |
469 | { 0xFF, 0x0F }, /* 95 */ | |
470 | { 0xFF, 0x3F }, /* 96 */ | |
471 | { 0xFF, 0x8C }, /* 97 */ | |
472 | { 0x00, 0x00 }, /* 98 */ | |
473 | { 0x00, 0x00 }, /* 99 */ | |
474 | { 0x00, 0x00 }, /* 9A */ | |
475 | { 0x00, 0x00 }, /* 9B */ | |
476 | { 0x00, 0x00 }, /* 9C */ | |
477 | { 0x00, 0x00 }, /* 9D */ | |
478 | { 0x00, 0x00 }, /* 9E */ | |
479 | { 0x00, 0x00 }, /* 9F */ | |
480 | { 0x00, 0x00 }, /* A0 */ | |
481 | { 0x00, 0x00 }, /* A1 */ | |
482 | { 0x00, 0x00 }, /* A2 */ | |
483 | { 0x00, 0x00 }, /* A3 */ | |
484 | { 0x00, 0x00 }, /* A4 */ | |
485 | { 0x00, 0x00 }, /* A5 */ | |
486 | { 0x00, 0x00 }, /* A6 */ | |
487 | { 0x00, 0x00 }, /* A7 */ | |
488 | { 0x00, 0x00 }, /* A8 */ | |
489 | { 0x00, 0x00 }, /* A9 */ | |
490 | { 0x00, 0x00 }, /* AA */ | |
491 | { 0x00, 0x00 }, /* AB */ | |
492 | { 0x00, 0x00 }, /* AC */ | |
493 | { 0x00, 0x00 }, /* AD */ | |
494 | { 0x00, 0x00 }, /* AE */ | |
495 | { 0x00, 0x00 }, /* AF */ | |
496 | { 0x00, 0x00 }, /* B0 */ | |
497 | { 0x00, 0x00 }, /* B1 */ | |
498 | { 0x00, 0x00 }, /* B2 */ | |
499 | { 0x00, 0x00 }, /* B3 */ | |
500 | { 0x00, 0x00 }, /* B4 */ | |
501 | { 0x00, 0x00 }, /* B5 */ | |
502 | { 0x00, 0x00 }, /* B6 */ | |
503 | { 0x00, 0x00 }, /* B7 */ | |
504 | { 0x00, 0x00 }, /* B8 */ | |
505 | { 0x00, 0x00 }, /* B9 */ | |
506 | { 0x00, 0x00 }, /* BA */ | |
507 | { 0x00, 0x00 }, /* BB */ | |
508 | { 0x00, 0x00 }, /* BC */ | |
509 | { 0x00, 0x00 }, /* BD */ | |
510 | { 0x00, 0x00 }, /* BE */ | |
511 | { 0x00, 0x00 }, /* BF */ | |
512 | { 0x00, 0x00 }, /* C0 */ | |
513 | { 0x00, 0x00 }, /* C1 */ | |
514 | { 0x00, 0x00 }, /* C2 */ | |
515 | { 0x00, 0x00 }, /* C3 */ | |
516 | { 0x00, 0x00 }, /* C4 */ | |
517 | { 0x00, 0x00 }, /* C5 */ | |
518 | { 0x00, 0x00 }, /* C6 */ | |
519 | { 0x00, 0x00 }, /* C7 */ | |
520 | { 0x00, 0x00 }, /* C8 */ | |
521 | { 0x00, 0x00 }, /* C9 */ | |
522 | { 0x00, 0x00 }, /* CA */ | |
523 | { 0x00, 0x00 }, /* CB */ | |
524 | { 0x00, 0x00 }, /* CC */ | |
525 | { 0x00, 0x00 }, /* CD */ | |
526 | { 0x00, 0x00 }, /* CE */ | |
527 | { 0x00, 0x00 }, /* CF */ | |
528 | { 0x00, 0x00 }, /* D0 */ | |
529 | { 0x00, 0x00 }, /* D1 */ | |
530 | { 0x00, 0x00 }, /* D2 */ | |
531 | { 0x00, 0x00 }, /* D3 */ | |
532 | { 0x00, 0x00 }, /* D4 */ | |
533 | { 0x00, 0x00 }, /* D5 */ | |
534 | { 0x00, 0x00 }, /* D6 */ | |
535 | { 0x00, 0x00 }, /* D7 */ | |
536 | { 0x00, 0x00 }, /* D8 */ | |
537 | { 0x00, 0x00 }, /* D9 */ | |
538 | { 0x00, 0x00 }, /* DA */ | |
539 | { 0x00, 0x00 }, /* DB */ | |
540 | { 0x00, 0x00 }, /* DC */ | |
541 | { 0x00, 0x00 }, /* DD */ | |
542 | { 0x00, 0x00 }, /* DE */ | |
543 | { 0x00, 0x00 }, /* DF */ | |
544 | { 0x00, 0x00 }, /* E0 */ | |
545 | { 0x00, 0x00 }, /* E1 */ | |
546 | { 0x00, 0x00 }, /* E2 */ | |
547 | { 0x00, 0x00 }, /* E3 */ | |
548 | { 0x00, 0x00 }, /* E4 */ | |
549 | { 0x00, 0x00 }, /* E5 */ | |
550 | { 0x00, 0x00 }, /* E6 */ | |
551 | { 0x00, 0x00 }, /* E7 */ | |
552 | { 0x00, 0x00 }, /* E8 */ | |
553 | { 0x00, 0x00 }, /* E9 */ | |
554 | { 0x00, 0x00 }, /* EA */ | |
555 | { 0x00, 0x00 }, /* EB */ | |
556 | { 0x00, 0x00 }, /* EC */ | |
557 | { 0x00, 0x00 }, /* ED */ | |
558 | { 0x00, 0x00 }, /* EE */ | |
559 | { 0x00, 0x00 }, /* EF */ | |
560 | { 0x00, 0x00 }, /* F0 */ | |
561 | { 0x00, 0x00 }, /* F1 */ | |
562 | { 0x00, 0x00 }, /* F2 */ | |
563 | { 0x00, 0x00 }, /* F3 */ | |
564 | { 0x00, 0x00 }, /* F4 */ | |
565 | { 0x00, 0x00 }, /* F5 */ | |
566 | { 0x00, 0x00 }, /* F6 */ | |
567 | { 0x00, 0x00 }, /* F7 */ | |
568 | { 0x00, 0x00 }, /* F8 */ | |
569 | { 0x00, 0x00 }, /* F9 */ | |
570 | { 0x00, 0x00 }, /* FA */ | |
571 | { 0x00, 0x00 }, /* FB */ | |
572 | { 0x00, 0x00 }, /* FC */ | |
573 | { 0x00, 0x00 }, /* FD */ | |
574 | { 0x00, 0x00 }, /* FE */ | |
575 | { 0xFF, 0x00 }, /* FF */ | |
576 | }; | |
577 | ||
578 | static int max98095_readable(struct snd_soc_codec *codec, unsigned int reg) | |
579 | { | |
580 | if (reg >= M98095_REG_CNT) | |
581 | return 0; | |
582 | return max98095_access[reg].readable != 0; | |
583 | } | |
584 | ||
585 | static int max98095_volatile(struct snd_soc_codec *codec, unsigned int reg) | |
586 | { | |
587 | if (reg > M98095_REG_MAX_CACHED) | |
588 | return 1; | |
589 | ||
590 | switch (reg) { | |
591 | case M98095_000_HOST_DATA: | |
592 | case M98095_001_HOST_INT_STS: | |
593 | case M98095_002_HOST_RSP_STS: | |
594 | case M98095_003_HOST_CMD_STS: | |
595 | case M98095_004_CODEC_STS: | |
596 | case M98095_005_DAI1_ALC_STS: | |
597 | case M98095_006_DAI2_ALC_STS: | |
598 | case M98095_007_JACK_AUTO_STS: | |
599 | case M98095_008_JACK_MANUAL_STS: | |
600 | case M98095_009_JACK_VBAT_STS: | |
601 | case M98095_00A_ACC_ADC_STS: | |
602 | case M98095_00B_MIC_NG_AGC_STS: | |
603 | case M98095_00C_SPK_L_VOLT_STS: | |
604 | case M98095_00D_SPK_R_VOLT_STS: | |
605 | case M98095_00E_TEMP_SENSOR_STS: | |
606 | return 1; | |
607 | } | |
608 | ||
609 | return 0; | |
610 | } | |
611 | ||
dad31ec1 PH |
612 | /* |
613 | * Filter coefficients are in a separate register segment | |
614 | * and they share the address space of the normal registers. | |
615 | * The coefficient registers do not need or share the cache. | |
616 | */ | |
617 | static int max98095_hw_write(struct snd_soc_codec *codec, unsigned int reg, | |
618 | unsigned int value) | |
619 | { | |
620 | u8 data[2]; | |
621 | ||
622 | data[0] = reg; | |
623 | data[1] = value; | |
624 | if (codec->hw_write(codec->control_data, data, 2) == 2) | |
625 | return 0; | |
626 | else | |
627 | return -EIO; | |
628 | } | |
629 | ||
630 | /* | |
631 | * Load equalizer DSP coefficient configurations registers | |
632 | */ | |
633 | static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai, | |
634 | unsigned int band, u16 *coefs) | |
635 | { | |
636 | unsigned int eq_reg; | |
637 | unsigned int i; | |
638 | ||
639 | BUG_ON(band > 4); | |
640 | BUG_ON(dai > 1); | |
641 | ||
642 | /* Load the base register address */ | |
643 | eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE; | |
644 | ||
645 | /* Add the band address offset, note adjustment for word address */ | |
646 | eq_reg += band * (M98095_COEFS_PER_BAND << 1); | |
647 | ||
648 | /* Step through the registers and coefs */ | |
649 | for (i = 0; i < M98095_COEFS_PER_BAND; i++) { | |
650 | max98095_hw_write(codec, eq_reg++, M98095_BYTE1(coefs[i])); | |
651 | max98095_hw_write(codec, eq_reg++, M98095_BYTE0(coefs[i])); | |
652 | } | |
653 | } | |
654 | ||
655 | /* | |
656 | * Load biquad filter coefficient configurations registers | |
657 | */ | |
658 | static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai, | |
659 | unsigned int band, u16 *coefs) | |
660 | { | |
661 | unsigned int bq_reg; | |
662 | unsigned int i; | |
663 | ||
664 | BUG_ON(band > 1); | |
665 | BUG_ON(dai > 1); | |
666 | ||
667 | /* Load the base register address */ | |
668 | bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE; | |
669 | ||
670 | /* Add the band address offset, note adjustment for word address */ | |
671 | bq_reg += band * (M98095_COEFS_PER_BAND << 1); | |
672 | ||
673 | /* Step through the registers and coefs */ | |
674 | for (i = 0; i < M98095_COEFS_PER_BAND; i++) { | |
675 | max98095_hw_write(codec, bq_reg++, M98095_BYTE1(coefs[i])); | |
676 | max98095_hw_write(codec, bq_reg++, M98095_BYTE0(coefs[i])); | |
677 | } | |
678 | } | |
679 | ||
82a5a936 PH |
680 | static const char * const max98095_fltr_mode[] = { "Voice", "Music" }; |
681 | static const struct soc_enum max98095_dai1_filter_mode_enum[] = { | |
682 | SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 7, 2, max98095_fltr_mode), | |
683 | }; | |
684 | static const struct soc_enum max98095_dai2_filter_mode_enum[] = { | |
685 | SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 7, 2, max98095_fltr_mode), | |
686 | }; | |
687 | ||
688 | static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" }; | |
689 | ||
690 | static const struct soc_enum max98095_extmic_enum = | |
691 | SOC_ENUM_SINGLE(M98095_087_CFG_MIC, 0, 3, max98095_extmic_text); | |
692 | ||
693 | static const struct snd_kcontrol_new max98095_extmic_mux = | |
694 | SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum); | |
695 | ||
696 | static const char * const max98095_linein_text[] = { "INA", "INB" }; | |
697 | ||
698 | static const struct soc_enum max98095_linein_enum = | |
699 | SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 6, 2, max98095_linein_text); | |
700 | ||
701 | static const struct snd_kcontrol_new max98095_linein_mux = | |
702 | SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum); | |
703 | ||
704 | static const char * const max98095_line_mode_text[] = { | |
705 | "Stereo", "Differential"}; | |
706 | ||
707 | static const struct soc_enum max98095_linein_mode_enum = | |
708 | SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 7, 2, max98095_line_mode_text); | |
709 | ||
710 | static const struct soc_enum max98095_lineout_mode_enum = | |
711 | SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 4, 2, max98095_line_mode_text); | |
712 | ||
713 | static const char * const max98095_dai_fltr[] = { | |
714 | "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k", | |
715 | "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"}; | |
716 | static const struct soc_enum max98095_dai1_dac_filter_enum[] = { | |
717 | SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 0, 6, max98095_dai_fltr), | |
718 | }; | |
719 | static const struct soc_enum max98095_dai2_dac_filter_enum[] = { | |
720 | SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 0, 6, max98095_dai_fltr), | |
721 | }; | |
722 | static const struct soc_enum max98095_dai3_dac_filter_enum[] = { | |
723 | SOC_ENUM_SINGLE(M98095_042_DAI3_FILTERS, 0, 6, max98095_dai_fltr), | |
724 | }; | |
725 | ||
726 | static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol, | |
727 | struct snd_ctl_elem_value *ucontrol) | |
728 | { | |
729 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
730 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
731 | unsigned int sel = ucontrol->value.integer.value[0]; | |
732 | ||
733 | max98095->mic1pre = sel; | |
734 | snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK, | |
735 | (1+sel)<<M98095_MICPRE_SHIFT); | |
736 | ||
737 | return 0; | |
738 | } | |
739 | ||
740 | static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol, | |
741 | struct snd_ctl_elem_value *ucontrol) | |
742 | { | |
743 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
744 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
745 | ||
746 | ucontrol->value.integer.value[0] = max98095->mic1pre; | |
747 | return 0; | |
748 | } | |
749 | ||
750 | static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol, | |
751 | struct snd_ctl_elem_value *ucontrol) | |
752 | { | |
753 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
754 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
755 | unsigned int sel = ucontrol->value.integer.value[0]; | |
756 | ||
757 | max98095->mic2pre = sel; | |
758 | snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK, | |
759 | (1+sel)<<M98095_MICPRE_SHIFT); | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol, | |
765 | struct snd_ctl_elem_value *ucontrol) | |
766 | { | |
767 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
768 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
769 | ||
770 | ucontrol->value.integer.value[0] = max98095->mic2pre; | |
771 | return 0; | |
772 | } | |
773 | ||
774 | static const unsigned int max98095_micboost_tlv[] = { | |
775 | TLV_DB_RANGE_HEAD(2), | |
776 | 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), | |
777 | 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), | |
778 | }; | |
779 | ||
780 | static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0); | |
781 | static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0); | |
782 | static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0); | |
783 | ||
784 | static const unsigned int max98095_hp_tlv[] = { | |
785 | TLV_DB_RANGE_HEAD(5), | |
786 | 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), | |
787 | 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), | |
788 | 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), | |
789 | 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), | |
790 | 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0), | |
791 | }; | |
792 | ||
793 | static const unsigned int max98095_spk_tlv[] = { | |
794 | TLV_DB_RANGE_HEAD(4), | |
795 | 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0), | |
796 | 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0), | |
797 | 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0), | |
798 | 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0), | |
799 | }; | |
800 | ||
801 | static const unsigned int max98095_rcv_lout_tlv[] = { | |
802 | TLV_DB_RANGE_HEAD(5), | |
803 | 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), | |
804 | 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), | |
805 | 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), | |
806 | 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), | |
807 | 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0), | |
808 | }; | |
809 | ||
810 | static const unsigned int max98095_lin_tlv[] = { | |
811 | TLV_DB_RANGE_HEAD(3), | |
812 | 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0), | |
813 | 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0), | |
814 | 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0), | |
815 | }; | |
816 | ||
817 | static const struct snd_kcontrol_new max98095_snd_controls[] = { | |
818 | ||
819 | SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L, | |
820 | M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv), | |
821 | ||
822 | SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L, | |
823 | M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv), | |
824 | ||
825 | SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV, | |
826 | 0, 31, 0, max98095_rcv_lout_tlv), | |
827 | ||
828 | SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1, | |
829 | M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv), | |
830 | ||
831 | SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L, | |
832 | M98095_065_LVL_HP_R, 7, 1, 1), | |
833 | ||
834 | SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L, | |
835 | M98095_068_LVL_SPK_R, 7, 1, 1), | |
836 | ||
837 | SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1), | |
838 | ||
839 | SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1, | |
840 | M98095_063_LVL_LINEOUT2, 7, 1, 1), | |
841 | ||
842 | SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1, | |
843 | max98095_mic_tlv), | |
844 | ||
845 | SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1, | |
846 | max98095_mic_tlv), | |
847 | ||
848 | SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", | |
849 | M98095_05F_LVL_MIC1, 5, 2, 0, | |
850 | max98095_mic1pre_get, max98095_mic1pre_set, | |
851 | max98095_micboost_tlv), | |
852 | SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", | |
853 | M98095_060_LVL_MIC2, 5, 2, 0, | |
854 | max98095_mic2pre_get, max98095_mic2pre_set, | |
855 | max98095_micboost_tlv), | |
856 | ||
857 | SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1, | |
858 | max98095_lin_tlv), | |
859 | ||
860 | SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1, | |
861 | max98095_adc_tlv), | |
862 | SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1, | |
863 | max98095_adc_tlv), | |
864 | ||
865 | SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0, | |
866 | max98095_adcboost_tlv), | |
867 | SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0, | |
868 | max98095_adcboost_tlv), | |
869 | ||
dad31ec1 PH |
870 | SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0), |
871 | SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0), | |
872 | ||
873 | SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0), | |
874 | SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0), | |
875 | ||
82a5a936 PH |
876 | SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum), |
877 | SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum), | |
878 | SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum), | |
879 | SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum), | |
880 | SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum), | |
881 | ||
882 | SOC_ENUM("Linein Mode", max98095_linein_mode_enum), | |
883 | SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum), | |
884 | }; | |
885 | ||
886 | /* Left speaker mixer switch */ | |
887 | static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = { | |
888 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0), | |
889 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0), | |
890 | SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), | |
891 | SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), | |
892 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0), | |
893 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0), | |
894 | SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0), | |
895 | SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0), | |
896 | }; | |
897 | ||
898 | /* Right speaker mixer switch */ | |
899 | static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = { | |
900 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0), | |
901 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0), | |
902 | SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), | |
903 | SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), | |
904 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0), | |
905 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0), | |
906 | SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0), | |
907 | SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0), | |
908 | }; | |
909 | ||
910 | /* Left headphone mixer switch */ | |
911 | static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = { | |
912 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0), | |
913 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0), | |
914 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0), | |
915 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0), | |
916 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0), | |
917 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0), | |
918 | }; | |
919 | ||
920 | /* Right headphone mixer switch */ | |
921 | static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = { | |
922 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0), | |
923 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0), | |
924 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0), | |
925 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0), | |
926 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0), | |
927 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0), | |
928 | }; | |
929 | ||
930 | /* Receiver earpiece mixer switch */ | |
931 | static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = { | |
932 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0), | |
933 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0), | |
934 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0), | |
935 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0), | |
936 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0), | |
937 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0), | |
938 | }; | |
939 | ||
940 | /* Left lineout mixer switch */ | |
941 | static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = { | |
942 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0), | |
943 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0), | |
944 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0), | |
945 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0), | |
946 | SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0), | |
947 | SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0), | |
948 | }; | |
949 | ||
950 | /* Right lineout mixer switch */ | |
951 | static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = { | |
952 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0), | |
953 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0), | |
954 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0), | |
955 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0), | |
956 | SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0), | |
957 | SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0), | |
958 | }; | |
959 | ||
960 | /* Left ADC mixer switch */ | |
961 | static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = { | |
962 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0), | |
963 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0), | |
964 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0), | |
965 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0), | |
966 | }; | |
967 | ||
968 | /* Right ADC mixer switch */ | |
969 | static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = { | |
970 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0), | |
971 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0), | |
972 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0), | |
973 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0), | |
974 | }; | |
975 | ||
976 | static int max98095_mic_event(struct snd_soc_dapm_widget *w, | |
977 | struct snd_kcontrol *kcontrol, int event) | |
978 | { | |
979 | struct snd_soc_codec *codec = w->codec; | |
980 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
981 | ||
982 | switch (event) { | |
983 | case SND_SOC_DAPM_POST_PMU: | |
984 | if (w->reg == M98095_05F_LVL_MIC1) { | |
985 | snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, | |
986 | (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT); | |
987 | } else { | |
988 | snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, | |
989 | (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT); | |
990 | } | |
991 | break; | |
992 | case SND_SOC_DAPM_POST_PMD: | |
993 | snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0); | |
994 | break; | |
995 | default: | |
996 | return -EINVAL; | |
997 | } | |
998 | ||
999 | return 0; | |
1000 | } | |
1001 | ||
1002 | /* | |
1003 | * The line inputs are stereo inputs with the left and right | |
1004 | * channels sharing a common PGA power control signal. | |
1005 | */ | |
1006 | static int max98095_line_pga(struct snd_soc_dapm_widget *w, | |
1007 | int event, u8 channel) | |
1008 | { | |
1009 | struct snd_soc_codec *codec = w->codec; | |
1010 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1011 | u8 *state; | |
1012 | ||
1013 | BUG_ON(!((channel == 1) || (channel == 2))); | |
1014 | ||
1015 | state = &max98095->lin_state; | |
1016 | ||
1017 | switch (event) { | |
1018 | case SND_SOC_DAPM_POST_PMU: | |
1019 | *state |= channel; | |
1020 | snd_soc_update_bits(codec, w->reg, | |
1021 | (1 << w->shift), (1 << w->shift)); | |
1022 | break; | |
1023 | case SND_SOC_DAPM_POST_PMD: | |
1024 | *state &= ~channel; | |
1025 | if (*state == 0) { | |
1026 | snd_soc_update_bits(codec, w->reg, | |
1027 | (1 << w->shift), 0); | |
1028 | } | |
1029 | break; | |
1030 | default: | |
1031 | return -EINVAL; | |
1032 | } | |
1033 | ||
1034 | return 0; | |
1035 | } | |
1036 | ||
1037 | static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w, | |
1038 | struct snd_kcontrol *k, int event) | |
1039 | { | |
1040 | return max98095_line_pga(w, event, 1); | |
1041 | } | |
1042 | ||
1043 | static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w, | |
1044 | struct snd_kcontrol *k, int event) | |
1045 | { | |
1046 | return max98095_line_pga(w, event, 2); | |
1047 | } | |
1048 | ||
1049 | /* | |
1050 | * The stereo line out mixer outputs to two stereo line outs. | |
1051 | * The 2nd pair has a separate set of enables. | |
1052 | */ | |
1053 | static int max98095_lineout_event(struct snd_soc_dapm_widget *w, | |
1054 | struct snd_kcontrol *kcontrol, int event) | |
1055 | { | |
1056 | struct snd_soc_codec *codec = w->codec; | |
1057 | ||
1058 | switch (event) { | |
1059 | case SND_SOC_DAPM_POST_PMU: | |
1060 | snd_soc_update_bits(codec, w->reg, | |
1061 | (1 << (w->shift+2)), (1 << (w->shift+2))); | |
1062 | break; | |
1063 | case SND_SOC_DAPM_POST_PMD: | |
1064 | snd_soc_update_bits(codec, w->reg, | |
1065 | (1 << (w->shift+2)), 0); | |
1066 | break; | |
1067 | default: | |
1068 | return -EINVAL; | |
1069 | } | |
1070 | ||
1071 | return 0; | |
1072 | } | |
1073 | ||
1074 | static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = { | |
1075 | ||
1076 | SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0), | |
1077 | SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0), | |
1078 | ||
1079 | SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", | |
1080 | M98095_091_PWR_EN_OUT, 0, 0), | |
1081 | SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", | |
1082 | M98095_091_PWR_EN_OUT, 1, 0), | |
1083 | SND_SOC_DAPM_DAC("DACM2", "Aux Playback", | |
1084 | M98095_091_PWR_EN_OUT, 2, 0), | |
1085 | SND_SOC_DAPM_DAC("DACM3", "Voice Playback", | |
1086 | M98095_091_PWR_EN_OUT, 2, 0), | |
1087 | ||
1088 | SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT, | |
1089 | 6, 0, NULL, 0), | |
1090 | SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT, | |
1091 | 7, 0, NULL, 0), | |
1092 | ||
1093 | SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT, | |
1094 | 4, 0, NULL, 0), | |
1095 | SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT, | |
1096 | 5, 0, NULL, 0), | |
1097 | ||
1098 | SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT, | |
1099 | 3, 0, NULL, 0), | |
1100 | ||
1101 | SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT, | |
1102 | 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), | |
1103 | SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT, | |
1104 | 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), | |
1105 | ||
1106 | SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, | |
1107 | &max98095_extmic_mux), | |
1108 | ||
1109 | SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0, | |
1110 | &max98095_linein_mux), | |
1111 | ||
1112 | SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, | |
1113 | &max98095_left_hp_mixer_controls[0], | |
1114 | ARRAY_SIZE(max98095_left_hp_mixer_controls)), | |
1115 | ||
1116 | SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, | |
1117 | &max98095_right_hp_mixer_controls[0], | |
1118 | ARRAY_SIZE(max98095_right_hp_mixer_controls)), | |
1119 | ||
1120 | SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, | |
1121 | &max98095_left_speaker_mixer_controls[0], | |
1122 | ARRAY_SIZE(max98095_left_speaker_mixer_controls)), | |
1123 | ||
1124 | SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, | |
1125 | &max98095_right_speaker_mixer_controls[0], | |
1126 | ARRAY_SIZE(max98095_right_speaker_mixer_controls)), | |
1127 | ||
1128 | SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0, | |
1129 | &max98095_mono_rcv_mixer_controls[0], | |
1130 | ARRAY_SIZE(max98095_mono_rcv_mixer_controls)), | |
1131 | ||
1132 | SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0, | |
1133 | &max98095_left_lineout_mixer_controls[0], | |
1134 | ARRAY_SIZE(max98095_left_lineout_mixer_controls)), | |
1135 | ||
1136 | SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0, | |
1137 | &max98095_right_lineout_mixer_controls[0], | |
1138 | ARRAY_SIZE(max98095_right_lineout_mixer_controls)), | |
1139 | ||
1140 | SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, | |
1141 | &max98095_left_ADC_mixer_controls[0], | |
1142 | ARRAY_SIZE(max98095_left_ADC_mixer_controls)), | |
1143 | ||
1144 | SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, | |
1145 | &max98095_right_ADC_mixer_controls[0], | |
1146 | ARRAY_SIZE(max98095_right_ADC_mixer_controls)), | |
1147 | ||
1148 | SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1, | |
1149 | 5, 0, NULL, 0, max98095_mic_event, | |
1150 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1151 | ||
1152 | SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2, | |
1153 | 5, 0, NULL, 0, max98095_mic_event, | |
1154 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1155 | ||
1156 | SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN, | |
1157 | 7, 0, NULL, 0, max98095_pga_in1_event, | |
1158 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1159 | ||
1160 | SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN, | |
1161 | 7, 0, NULL, 0, max98095_pga_in2_event, | |
1162 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1163 | ||
1164 | SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0), | |
1165 | SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0), | |
1166 | ||
1167 | SND_SOC_DAPM_OUTPUT("HPL"), | |
1168 | SND_SOC_DAPM_OUTPUT("HPR"), | |
1169 | SND_SOC_DAPM_OUTPUT("SPKL"), | |
1170 | SND_SOC_DAPM_OUTPUT("SPKR"), | |
1171 | SND_SOC_DAPM_OUTPUT("RCV"), | |
1172 | SND_SOC_DAPM_OUTPUT("OUT1"), | |
1173 | SND_SOC_DAPM_OUTPUT("OUT2"), | |
1174 | SND_SOC_DAPM_OUTPUT("OUT3"), | |
1175 | SND_SOC_DAPM_OUTPUT("OUT4"), | |
1176 | ||
1177 | SND_SOC_DAPM_INPUT("MIC1"), | |
1178 | SND_SOC_DAPM_INPUT("MIC2"), | |
1179 | SND_SOC_DAPM_INPUT("INA1"), | |
1180 | SND_SOC_DAPM_INPUT("INA2"), | |
1181 | SND_SOC_DAPM_INPUT("INB1"), | |
1182 | SND_SOC_DAPM_INPUT("INB2"), | |
1183 | }; | |
1184 | ||
1185 | static const struct snd_soc_dapm_route max98095_audio_map[] = { | |
1186 | /* Left headphone output mixer */ | |
1187 | {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"}, | |
1188 | {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"}, | |
1189 | {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1190 | {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1191 | {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"}, | |
1192 | {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"}, | |
1193 | ||
1194 | /* Right headphone output mixer */ | |
1195 | {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"}, | |
1196 | {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"}, | |
1197 | {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1198 | {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1199 | {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"}, | |
1200 | {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"}, | |
1201 | ||
1202 | /* Left speaker output mixer */ | |
1203 | {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"}, | |
1204 | {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"}, | |
1205 | {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, | |
1206 | {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, | |
1207 | {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1208 | {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1209 | {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"}, | |
1210 | {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"}, | |
1211 | ||
1212 | /* Right speaker output mixer */ | |
1213 | {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"}, | |
1214 | {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"}, | |
1215 | {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, | |
1216 | {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, | |
1217 | {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1218 | {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1219 | {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"}, | |
1220 | {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"}, | |
1221 | ||
1222 | /* Earpiece/Receiver output mixer */ | |
1223 | {"Receiver Mixer", "Left DAC1 Switch", "DACL1"}, | |
1224 | {"Receiver Mixer", "Right DAC1 Switch", "DACR1"}, | |
1225 | {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1226 | {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1227 | {"Receiver Mixer", "IN1 Switch", "IN1 Input"}, | |
1228 | {"Receiver Mixer", "IN2 Switch", "IN2 Input"}, | |
1229 | ||
1230 | /* Left Lineout output mixer */ | |
1231 | {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"}, | |
1232 | {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"}, | |
1233 | {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1234 | {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1235 | {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"}, | |
1236 | {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"}, | |
1237 | ||
1238 | /* Right lineout output mixer */ | |
1239 | {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"}, | |
1240 | {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"}, | |
1241 | {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1242 | {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1243 | {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"}, | |
1244 | {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"}, | |
1245 | ||
1246 | {"HP Left Out", NULL, "Left Headphone Mixer"}, | |
1247 | {"HP Right Out", NULL, "Right Headphone Mixer"}, | |
1248 | {"SPK Left Out", NULL, "Left Speaker Mixer"}, | |
1249 | {"SPK Right Out", NULL, "Right Speaker Mixer"}, | |
1250 | {"RCV Mono Out", NULL, "Receiver Mixer"}, | |
1251 | {"LINE Left Out", NULL, "Left Lineout Mixer"}, | |
1252 | {"LINE Right Out", NULL, "Right Lineout Mixer"}, | |
1253 | ||
1254 | {"HPL", NULL, "HP Left Out"}, | |
1255 | {"HPR", NULL, "HP Right Out"}, | |
1256 | {"SPKL", NULL, "SPK Left Out"}, | |
1257 | {"SPKR", NULL, "SPK Right Out"}, | |
1258 | {"RCV", NULL, "RCV Mono Out"}, | |
1259 | {"OUT1", NULL, "LINE Left Out"}, | |
1260 | {"OUT2", NULL, "LINE Right Out"}, | |
1261 | {"OUT3", NULL, "LINE Left Out"}, | |
1262 | {"OUT4", NULL, "LINE Right Out"}, | |
1263 | ||
1264 | /* Left ADC input mixer */ | |
1265 | {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1266 | {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1267 | {"Left ADC Mixer", "IN1 Switch", "IN1 Input"}, | |
1268 | {"Left ADC Mixer", "IN2 Switch", "IN2 Input"}, | |
1269 | ||
1270 | /* Right ADC input mixer */ | |
1271 | {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1272 | {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1273 | {"Right ADC Mixer", "IN1 Switch", "IN1 Input"}, | |
1274 | {"Right ADC Mixer", "IN2 Switch", "IN2 Input"}, | |
1275 | ||
1276 | /* Inputs */ | |
1277 | {"ADCL", NULL, "Left ADC Mixer"}, | |
1278 | {"ADCR", NULL, "Right ADC Mixer"}, | |
1279 | ||
1280 | {"IN1 Input", NULL, "INA1"}, | |
1281 | {"IN2 Input", NULL, "INA2"}, | |
1282 | ||
1283 | {"MIC1 Input", NULL, "MIC1"}, | |
1284 | {"MIC2 Input", NULL, "MIC2"}, | |
1285 | }; | |
1286 | ||
1287 | static int max98095_add_widgets(struct snd_soc_codec *codec) | |
1288 | { | |
1289 | snd_soc_add_controls(codec, max98095_snd_controls, | |
1290 | ARRAY_SIZE(max98095_snd_controls)); | |
1291 | ||
1292 | return 0; | |
1293 | } | |
1294 | ||
1295 | /* codec mclk clock divider coefficients */ | |
1296 | static const struct { | |
1297 | u32 rate; | |
1298 | u8 sr; | |
1299 | } rate_table[] = { | |
1300 | {8000, 0x01}, | |
1301 | {11025, 0x02}, | |
1302 | {16000, 0x03}, | |
1303 | {22050, 0x04}, | |
1304 | {24000, 0x05}, | |
1305 | {32000, 0x06}, | |
1306 | {44100, 0x07}, | |
1307 | {48000, 0x08}, | |
1308 | {88200, 0x09}, | |
1309 | {96000, 0x0A}, | |
1310 | }; | |
1311 | ||
1312 | static int rate_value(int rate, u8 *value) | |
1313 | { | |
1314 | int i; | |
1315 | ||
1316 | for (i = 0; i < ARRAY_SIZE(rate_table); i++) { | |
1317 | if (rate_table[i].rate >= rate) { | |
1318 | *value = rate_table[i].sr; | |
1319 | return 0; | |
1320 | } | |
1321 | } | |
1322 | *value = rate_table[0].sr; | |
1323 | return -EINVAL; | |
1324 | } | |
1325 | ||
1326 | static int max98095_dai1_hw_params(struct snd_pcm_substream *substream, | |
1327 | struct snd_pcm_hw_params *params, | |
1328 | struct snd_soc_dai *dai) | |
1329 | { | |
1330 | struct snd_soc_codec *codec = dai->codec; | |
1331 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1332 | struct max98095_cdata *cdata; | |
1333 | unsigned long long ni; | |
1334 | unsigned int rate; | |
1335 | u8 regval; | |
1336 | ||
1337 | cdata = &max98095->dai[0]; | |
1338 | ||
1339 | rate = params_rate(params); | |
1340 | ||
1341 | switch (params_format(params)) { | |
1342 | case SNDRV_PCM_FORMAT_S16_LE: | |
1343 | snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, | |
1344 | M98095_DAI_WS, 0); | |
1345 | break; | |
1346 | case SNDRV_PCM_FORMAT_S24_LE: | |
1347 | snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, | |
1348 | M98095_DAI_WS, M98095_DAI_WS); | |
1349 | break; | |
1350 | default: | |
1351 | return -EINVAL; | |
1352 | } | |
1353 | ||
1354 | if (rate_value(rate, ®val)) | |
1355 | return -EINVAL; | |
1356 | ||
1357 | snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE, | |
1358 | M98095_CLKMODE_MASK, regval); | |
1359 | cdata->rate = rate; | |
1360 | ||
1361 | /* Configure NI when operating as master */ | |
1362 | if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) { | |
1363 | if (max98095->sysclk == 0) { | |
1364 | dev_err(codec->dev, "Invalid system clock frequency\n"); | |
1365 | return -EINVAL; | |
1366 | } | |
1367 | ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) | |
1368 | * (unsigned long long int)rate; | |
1369 | do_div(ni, (unsigned long long int)max98095->sysclk); | |
1370 | snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, | |
1371 | (ni >> 8) & 0x7F); | |
1372 | snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, | |
1373 | ni & 0xFF); | |
1374 | } | |
1375 | ||
1376 | /* Update sample rate mode */ | |
1377 | if (rate < 50000) | |
1378 | snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, | |
1379 | M98095_DAI_DHF, 0); | |
1380 | else | |
1381 | snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, | |
1382 | M98095_DAI_DHF, M98095_DAI_DHF); | |
1383 | ||
1384 | return 0; | |
1385 | } | |
1386 | ||
1387 | static int max98095_dai2_hw_params(struct snd_pcm_substream *substream, | |
1388 | struct snd_pcm_hw_params *params, | |
1389 | struct snd_soc_dai *dai) | |
1390 | { | |
1391 | struct snd_soc_codec *codec = dai->codec; | |
1392 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1393 | struct max98095_cdata *cdata; | |
1394 | unsigned long long ni; | |
1395 | unsigned int rate; | |
1396 | u8 regval; | |
1397 | ||
1398 | cdata = &max98095->dai[1]; | |
1399 | ||
1400 | rate = params_rate(params); | |
1401 | ||
1402 | switch (params_format(params)) { | |
1403 | case SNDRV_PCM_FORMAT_S16_LE: | |
1404 | snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, | |
1405 | M98095_DAI_WS, 0); | |
1406 | break; | |
1407 | case SNDRV_PCM_FORMAT_S24_LE: | |
1408 | snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, | |
1409 | M98095_DAI_WS, M98095_DAI_WS); | |
1410 | break; | |
1411 | default: | |
1412 | return -EINVAL; | |
1413 | } | |
1414 | ||
1415 | if (rate_value(rate, ®val)) | |
1416 | return -EINVAL; | |
1417 | ||
1418 | snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE, | |
1419 | M98095_CLKMODE_MASK, regval); | |
1420 | cdata->rate = rate; | |
1421 | ||
1422 | /* Configure NI when operating as master */ | |
1423 | if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) { | |
1424 | if (max98095->sysclk == 0) { | |
1425 | dev_err(codec->dev, "Invalid system clock frequency\n"); | |
1426 | return -EINVAL; | |
1427 | } | |
1428 | ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) | |
1429 | * (unsigned long long int)rate; | |
1430 | do_div(ni, (unsigned long long int)max98095->sysclk); | |
1431 | snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, | |
1432 | (ni >> 8) & 0x7F); | |
1433 | snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, | |
1434 | ni & 0xFF); | |
1435 | } | |
1436 | ||
1437 | /* Update sample rate mode */ | |
1438 | if (rate < 50000) | |
1439 | snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, | |
1440 | M98095_DAI_DHF, 0); | |
1441 | else | |
1442 | snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, | |
1443 | M98095_DAI_DHF, M98095_DAI_DHF); | |
1444 | ||
1445 | return 0; | |
1446 | } | |
1447 | ||
1448 | static int max98095_dai3_hw_params(struct snd_pcm_substream *substream, | |
1449 | struct snd_pcm_hw_params *params, | |
1450 | struct snd_soc_dai *dai) | |
1451 | { | |
1452 | struct snd_soc_codec *codec = dai->codec; | |
1453 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1454 | struct max98095_cdata *cdata; | |
1455 | unsigned long long ni; | |
1456 | unsigned int rate; | |
1457 | u8 regval; | |
1458 | ||
1459 | cdata = &max98095->dai[2]; | |
1460 | ||
1461 | rate = params_rate(params); | |
1462 | ||
1463 | switch (params_format(params)) { | |
1464 | case SNDRV_PCM_FORMAT_S16_LE: | |
1465 | snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, | |
1466 | M98095_DAI_WS, 0); | |
1467 | break; | |
1468 | case SNDRV_PCM_FORMAT_S24_LE: | |
1469 | snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, | |
1470 | M98095_DAI_WS, M98095_DAI_WS); | |
1471 | break; | |
1472 | default: | |
1473 | return -EINVAL; | |
1474 | } | |
1475 | ||
1476 | if (rate_value(rate, ®val)) | |
1477 | return -EINVAL; | |
1478 | ||
1479 | snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE, | |
1480 | M98095_CLKMODE_MASK, regval); | |
1481 | cdata->rate = rate; | |
1482 | ||
1483 | /* Configure NI when operating as master */ | |
1484 | if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) { | |
1485 | if (max98095->sysclk == 0) { | |
1486 | dev_err(codec->dev, "Invalid system clock frequency\n"); | |
1487 | return -EINVAL; | |
1488 | } | |
1489 | ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) | |
1490 | * (unsigned long long int)rate; | |
1491 | do_div(ni, (unsigned long long int)max98095->sysclk); | |
1492 | snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, | |
1493 | (ni >> 8) & 0x7F); | |
1494 | snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, | |
1495 | ni & 0xFF); | |
1496 | } | |
1497 | ||
1498 | /* Update sample rate mode */ | |
1499 | if (rate < 50000) | |
1500 | snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, | |
1501 | M98095_DAI_DHF, 0); | |
1502 | else | |
1503 | snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, | |
1504 | M98095_DAI_DHF, M98095_DAI_DHF); | |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | ||
1509 | static int max98095_dai_set_sysclk(struct snd_soc_dai *dai, | |
1510 | int clk_id, unsigned int freq, int dir) | |
1511 | { | |
1512 | struct snd_soc_codec *codec = dai->codec; | |
1513 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1514 | ||
1515 | /* Requested clock frequency is already setup */ | |
1516 | if (freq == max98095->sysclk) | |
1517 | return 0; | |
1518 | ||
82a5a936 PH |
1519 | /* Setup clocks for slave mode, and using the PLL |
1520 | * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) | |
1521 | * 0x02 (when master clk is 20MHz to 40MHz).. | |
1522 | * 0x03 (when master clk is 40MHz to 60MHz).. | |
1523 | */ | |
1524 | if ((freq >= 10000000) && (freq < 20000000)) { | |
1525 | snd_soc_write(codec, M98095_026_SYS_CLK, 0x10); | |
1526 | } else if ((freq >= 20000000) && (freq < 40000000)) { | |
1527 | snd_soc_write(codec, M98095_026_SYS_CLK, 0x20); | |
1528 | } else if ((freq >= 40000000) && (freq < 60000000)) { | |
1529 | snd_soc_write(codec, M98095_026_SYS_CLK, 0x30); | |
1530 | } else { | |
1531 | dev_err(codec->dev, "Invalid master clock frequency\n"); | |
1532 | return -EINVAL; | |
1533 | } | |
1534 | ||
1535 | dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); | |
1536 | ||
1537 | max98095->sysclk = freq; | |
1538 | return 0; | |
1539 | } | |
1540 | ||
1541 | static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai, | |
1542 | unsigned int fmt) | |
1543 | { | |
1544 | struct snd_soc_codec *codec = codec_dai->codec; | |
1545 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1546 | struct max98095_cdata *cdata; | |
1547 | u8 regval = 0; | |
1548 | ||
1549 | cdata = &max98095->dai[0]; | |
1550 | ||
1551 | if (fmt != cdata->fmt) { | |
1552 | cdata->fmt = fmt; | |
1553 | ||
1554 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1555 | case SND_SOC_DAIFMT_CBS_CFS: | |
1556 | /* Slave mode PLL */ | |
1557 | snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, | |
1558 | 0x80); | |
1559 | snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, | |
1560 | 0x00); | |
1561 | break; | |
1562 | case SND_SOC_DAIFMT_CBM_CFM: | |
1563 | /* Set to master mode */ | |
1564 | regval |= M98095_DAI_MAS; | |
1565 | break; | |
1566 | case SND_SOC_DAIFMT_CBS_CFM: | |
1567 | case SND_SOC_DAIFMT_CBM_CFS: | |
1568 | default: | |
1569 | dev_err(codec->dev, "Clock mode unsupported"); | |
1570 | return -EINVAL; | |
1571 | } | |
1572 | ||
1573 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1574 | case SND_SOC_DAIFMT_I2S: | |
1575 | regval |= M98095_DAI_DLY; | |
1576 | break; | |
1577 | case SND_SOC_DAIFMT_LEFT_J: | |
1578 | break; | |
1579 | default: | |
1580 | return -EINVAL; | |
1581 | } | |
1582 | ||
1583 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1584 | case SND_SOC_DAIFMT_NB_NF: | |
1585 | break; | |
1586 | case SND_SOC_DAIFMT_NB_IF: | |
1587 | regval |= M98095_DAI_WCI; | |
1588 | break; | |
1589 | case SND_SOC_DAIFMT_IB_NF: | |
1590 | regval |= M98095_DAI_BCI; | |
1591 | break; | |
1592 | case SND_SOC_DAIFMT_IB_IF: | |
1593 | regval |= M98095_DAI_BCI|M98095_DAI_WCI; | |
1594 | break; | |
1595 | default: | |
1596 | return -EINVAL; | |
1597 | } | |
1598 | ||
1599 | snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, | |
1600 | M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | | |
1601 | M98095_DAI_WCI, regval); | |
1602 | ||
1603 | snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64); | |
1604 | } | |
1605 | ||
1606 | return 0; | |
1607 | } | |
1608 | ||
1609 | static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai, | |
1610 | unsigned int fmt) | |
1611 | { | |
1612 | struct snd_soc_codec *codec = codec_dai->codec; | |
1613 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1614 | struct max98095_cdata *cdata; | |
1615 | u8 regval = 0; | |
1616 | ||
1617 | cdata = &max98095->dai[1]; | |
1618 | ||
1619 | if (fmt != cdata->fmt) { | |
1620 | cdata->fmt = fmt; | |
1621 | ||
1622 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1623 | case SND_SOC_DAIFMT_CBS_CFS: | |
1624 | /* Slave mode PLL */ | |
1625 | snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, | |
1626 | 0x80); | |
1627 | snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, | |
1628 | 0x00); | |
1629 | break; | |
1630 | case SND_SOC_DAIFMT_CBM_CFM: | |
1631 | /* Set to master mode */ | |
1632 | regval |= M98095_DAI_MAS; | |
1633 | break; | |
1634 | case SND_SOC_DAIFMT_CBS_CFM: | |
1635 | case SND_SOC_DAIFMT_CBM_CFS: | |
1636 | default: | |
1637 | dev_err(codec->dev, "Clock mode unsupported"); | |
1638 | return -EINVAL; | |
1639 | } | |
1640 | ||
1641 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1642 | case SND_SOC_DAIFMT_I2S: | |
1643 | regval |= M98095_DAI_DLY; | |
1644 | break; | |
1645 | case SND_SOC_DAIFMT_LEFT_J: | |
1646 | break; | |
1647 | default: | |
1648 | return -EINVAL; | |
1649 | } | |
1650 | ||
1651 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1652 | case SND_SOC_DAIFMT_NB_NF: | |
1653 | break; | |
1654 | case SND_SOC_DAIFMT_NB_IF: | |
1655 | regval |= M98095_DAI_WCI; | |
1656 | break; | |
1657 | case SND_SOC_DAIFMT_IB_NF: | |
1658 | regval |= M98095_DAI_BCI; | |
1659 | break; | |
1660 | case SND_SOC_DAIFMT_IB_IF: | |
1661 | regval |= M98095_DAI_BCI|M98095_DAI_WCI; | |
1662 | break; | |
1663 | default: | |
1664 | return -EINVAL; | |
1665 | } | |
1666 | ||
1667 | snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, | |
1668 | M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | | |
1669 | M98095_DAI_WCI, regval); | |
1670 | ||
1671 | snd_soc_write(codec, M98095_035_DAI2_CLOCK, | |
1672 | M98095_DAI_BSEL64); | |
1673 | } | |
1674 | ||
1675 | return 0; | |
1676 | } | |
1677 | ||
1678 | static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai, | |
1679 | unsigned int fmt) | |
1680 | { | |
1681 | struct snd_soc_codec *codec = codec_dai->codec; | |
1682 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1683 | struct max98095_cdata *cdata; | |
1684 | u8 regval = 0; | |
1685 | ||
1686 | cdata = &max98095->dai[2]; | |
1687 | ||
1688 | if (fmt != cdata->fmt) { | |
1689 | cdata->fmt = fmt; | |
1690 | ||
1691 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1692 | case SND_SOC_DAIFMT_CBS_CFS: | |
1693 | /* Slave mode PLL */ | |
1694 | snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, | |
1695 | 0x80); | |
1696 | snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, | |
1697 | 0x00); | |
1698 | break; | |
1699 | case SND_SOC_DAIFMT_CBM_CFM: | |
1700 | /* Set to master mode */ | |
1701 | regval |= M98095_DAI_MAS; | |
1702 | break; | |
1703 | case SND_SOC_DAIFMT_CBS_CFM: | |
1704 | case SND_SOC_DAIFMT_CBM_CFS: | |
1705 | default: | |
1706 | dev_err(codec->dev, "Clock mode unsupported"); | |
1707 | return -EINVAL; | |
1708 | } | |
1709 | ||
1710 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1711 | case SND_SOC_DAIFMT_I2S: | |
1712 | regval |= M98095_DAI_DLY; | |
1713 | break; | |
1714 | case SND_SOC_DAIFMT_LEFT_J: | |
1715 | break; | |
1716 | default: | |
1717 | return -EINVAL; | |
1718 | } | |
1719 | ||
1720 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1721 | case SND_SOC_DAIFMT_NB_NF: | |
1722 | break; | |
1723 | case SND_SOC_DAIFMT_NB_IF: | |
1724 | regval |= M98095_DAI_WCI; | |
1725 | break; | |
1726 | case SND_SOC_DAIFMT_IB_NF: | |
1727 | regval |= M98095_DAI_BCI; | |
1728 | break; | |
1729 | case SND_SOC_DAIFMT_IB_IF: | |
1730 | regval |= M98095_DAI_BCI|M98095_DAI_WCI; | |
1731 | break; | |
1732 | default: | |
1733 | return -EINVAL; | |
1734 | } | |
1735 | ||
1736 | snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, | |
1737 | M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | | |
1738 | M98095_DAI_WCI, regval); | |
1739 | ||
1740 | snd_soc_write(codec, M98095_03F_DAI3_CLOCK, | |
1741 | M98095_DAI_BSEL64); | |
1742 | } | |
1743 | ||
1744 | return 0; | |
1745 | } | |
1746 | ||
1747 | static int max98095_set_bias_level(struct snd_soc_codec *codec, | |
1748 | enum snd_soc_bias_level level) | |
1749 | { | |
1750 | int ret; | |
1751 | ||
1752 | switch (level) { | |
1753 | case SND_SOC_BIAS_ON: | |
1754 | break; | |
1755 | ||
1756 | case SND_SOC_BIAS_PREPARE: | |
1757 | break; | |
1758 | ||
1759 | case SND_SOC_BIAS_STANDBY: | |
1760 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { | |
1761 | ret = snd_soc_cache_sync(codec); | |
1762 | ||
1763 | if (ret != 0) { | |
1764 | dev_err(codec->dev, "Failed to sync cache: %d\n", ret); | |
1765 | return ret; | |
1766 | } | |
1767 | } | |
1768 | ||
1769 | snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, | |
1770 | M98095_MBEN, M98095_MBEN); | |
1771 | break; | |
1772 | ||
1773 | case SND_SOC_BIAS_OFF: | |
1774 | snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, | |
1775 | M98095_MBEN, 0); | |
1776 | codec->cache_sync = 1; | |
1777 | break; | |
1778 | } | |
1779 | codec->dapm.bias_level = level; | |
1780 | return 0; | |
1781 | } | |
1782 | ||
1783 | #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000 | |
1784 | #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) | |
1785 | ||
1786 | static struct snd_soc_dai_ops max98095_dai1_ops = { | |
1787 | .set_sysclk = max98095_dai_set_sysclk, | |
1788 | .set_fmt = max98095_dai1_set_fmt, | |
1789 | .hw_params = max98095_dai1_hw_params, | |
1790 | }; | |
1791 | ||
1792 | static struct snd_soc_dai_ops max98095_dai2_ops = { | |
1793 | .set_sysclk = max98095_dai_set_sysclk, | |
1794 | .set_fmt = max98095_dai2_set_fmt, | |
1795 | .hw_params = max98095_dai2_hw_params, | |
1796 | }; | |
1797 | ||
1798 | static struct snd_soc_dai_ops max98095_dai3_ops = { | |
1799 | .set_sysclk = max98095_dai_set_sysclk, | |
1800 | .set_fmt = max98095_dai3_set_fmt, | |
1801 | .hw_params = max98095_dai3_hw_params, | |
1802 | }; | |
1803 | ||
1804 | static struct snd_soc_dai_driver max98095_dai[] = { | |
1805 | { | |
1806 | .name = "HiFi", | |
1807 | .playback = { | |
1808 | .stream_name = "HiFi Playback", | |
1809 | .channels_min = 1, | |
1810 | .channels_max = 2, | |
1811 | .rates = MAX98095_RATES, | |
1812 | .formats = MAX98095_FORMATS, | |
1813 | }, | |
1814 | .capture = { | |
1815 | .stream_name = "HiFi Capture", | |
1816 | .channels_min = 1, | |
1817 | .channels_max = 2, | |
1818 | .rates = MAX98095_RATES, | |
1819 | .formats = MAX98095_FORMATS, | |
1820 | }, | |
1821 | .ops = &max98095_dai1_ops, | |
1822 | }, | |
1823 | { | |
1824 | .name = "Aux", | |
1825 | .playback = { | |
1826 | .stream_name = "Aux Playback", | |
1827 | .channels_min = 1, | |
1828 | .channels_max = 1, | |
1829 | .rates = MAX98095_RATES, | |
1830 | .formats = MAX98095_FORMATS, | |
1831 | }, | |
1832 | .ops = &max98095_dai2_ops, | |
1833 | }, | |
1834 | { | |
1835 | .name = "Voice", | |
1836 | .playback = { | |
1837 | .stream_name = "Voice Playback", | |
1838 | .channels_min = 1, | |
1839 | .channels_max = 1, | |
1840 | .rates = MAX98095_RATES, | |
1841 | .formats = MAX98095_FORMATS, | |
1842 | }, | |
1843 | .ops = &max98095_dai3_ops, | |
1844 | } | |
1845 | ||
1846 | }; | |
1847 | ||
dad31ec1 PH |
1848 | static int max98095_get_eq_channel(const char *name) |
1849 | { | |
1850 | if (strcmp(name, "EQ1 Mode") == 0) | |
1851 | return 0; | |
1852 | if (strcmp(name, "EQ2 Mode") == 0) | |
1853 | return 1; | |
1854 | return -EINVAL; | |
1855 | } | |
1856 | ||
1857 | static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol, | |
1858 | struct snd_ctl_elem_value *ucontrol) | |
1859 | { | |
1860 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
1861 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1862 | struct max98095_pdata *pdata = max98095->pdata; | |
1863 | int channel = max98095_get_eq_channel(kcontrol->id.name); | |
1864 | struct max98095_cdata *cdata; | |
1865 | int sel = ucontrol->value.integer.value[0]; | |
1866 | struct max98095_eq_cfg *coef_set; | |
1867 | int fs, best, best_val, i; | |
1868 | int regmask, regsave; | |
1869 | ||
1870 | BUG_ON(channel > 1); | |
1871 | ||
53949425 TH |
1872 | if (!pdata || !max98095->eq_textcnt) |
1873 | return 0; | |
dad31ec1 PH |
1874 | |
1875 | if (sel >= pdata->eq_cfgcnt) | |
1876 | return -EINVAL; | |
1877 | ||
53949425 | 1878 | cdata = &max98095->dai[channel]; |
dad31ec1 | 1879 | cdata->eq_sel = sel; |
dad31ec1 PH |
1880 | fs = cdata->rate; |
1881 | ||
1882 | /* Find the selected configuration with nearest sample rate */ | |
1883 | best = 0; | |
1884 | best_val = INT_MAX; | |
1885 | for (i = 0; i < pdata->eq_cfgcnt; i++) { | |
1886 | if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 && | |
1887 | abs(pdata->eq_cfg[i].rate - fs) < best_val) { | |
1888 | best = i; | |
1889 | best_val = abs(pdata->eq_cfg[i].rate - fs); | |
1890 | } | |
1891 | } | |
1892 | ||
1893 | dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", | |
1894 | pdata->eq_cfg[best].name, | |
1895 | pdata->eq_cfg[best].rate, fs); | |
1896 | ||
1897 | coef_set = &pdata->eq_cfg[best]; | |
1898 | ||
1899 | regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN; | |
1900 | ||
1901 | /* Disable filter while configuring, and save current on/off state */ | |
1902 | regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); | |
1903 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); | |
1904 | ||
1905 | mutex_lock(&codec->mutex); | |
1906 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); | |
1907 | m98095_eq_band(codec, channel, 0, coef_set->band1); | |
1908 | m98095_eq_band(codec, channel, 1, coef_set->band2); | |
1909 | m98095_eq_band(codec, channel, 2, coef_set->band3); | |
1910 | m98095_eq_band(codec, channel, 3, coef_set->band4); | |
1911 | m98095_eq_band(codec, channel, 4, coef_set->band5); | |
1912 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); | |
1913 | mutex_unlock(&codec->mutex); | |
1914 | ||
1915 | /* Restore the original on/off state */ | |
1916 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); | |
1917 | return 0; | |
1918 | } | |
1919 | ||
1920 | static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol, | |
1921 | struct snd_ctl_elem_value *ucontrol) | |
1922 | { | |
1923 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
1924 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1925 | int channel = max98095_get_eq_channel(kcontrol->id.name); | |
1926 | struct max98095_cdata *cdata; | |
1927 | ||
1928 | cdata = &max98095->dai[channel]; | |
1929 | ucontrol->value.enumerated.item[0] = cdata->eq_sel; | |
1930 | ||
1931 | return 0; | |
1932 | } | |
1933 | ||
1934 | static void max98095_handle_eq_pdata(struct snd_soc_codec *codec) | |
1935 | { | |
1936 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1937 | struct max98095_pdata *pdata = max98095->pdata; | |
1938 | struct max98095_eq_cfg *cfg; | |
1939 | unsigned int cfgcnt; | |
1940 | int i, j; | |
1941 | const char **t; | |
1942 | int ret; | |
1943 | ||
1944 | struct snd_kcontrol_new controls[] = { | |
1945 | SOC_ENUM_EXT("EQ1 Mode", | |
1946 | max98095->eq_enum, | |
1947 | max98095_get_eq_enum, | |
1948 | max98095_put_eq_enum), | |
1949 | SOC_ENUM_EXT("EQ2 Mode", | |
1950 | max98095->eq_enum, | |
1951 | max98095_get_eq_enum, | |
1952 | max98095_put_eq_enum), | |
1953 | }; | |
1954 | ||
1955 | cfg = pdata->eq_cfg; | |
1956 | cfgcnt = pdata->eq_cfgcnt; | |
1957 | ||
1958 | /* Setup an array of texts for the equalizer enum. | |
1959 | * This is based on Mark Brown's equalizer driver code. | |
1960 | */ | |
1961 | max98095->eq_textcnt = 0; | |
1962 | max98095->eq_texts = NULL; | |
1963 | for (i = 0; i < cfgcnt; i++) { | |
1964 | for (j = 0; j < max98095->eq_textcnt; j++) { | |
1965 | if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0) | |
1966 | break; | |
1967 | } | |
1968 | ||
1969 | if (j != max98095->eq_textcnt) | |
1970 | continue; | |
1971 | ||
1972 | /* Expand the array */ | |
1973 | t = krealloc(max98095->eq_texts, | |
1974 | sizeof(char *) * (max98095->eq_textcnt + 1), | |
1975 | GFP_KERNEL); | |
1976 | if (t == NULL) | |
1977 | continue; | |
1978 | ||
1979 | /* Store the new entry */ | |
1980 | t[max98095->eq_textcnt] = cfg[i].name; | |
1981 | max98095->eq_textcnt++; | |
1982 | max98095->eq_texts = t; | |
1983 | } | |
1984 | ||
1985 | /* Now point the soc_enum to .texts array items */ | |
1986 | max98095->eq_enum.texts = max98095->eq_texts; | |
1987 | max98095->eq_enum.max = max98095->eq_textcnt; | |
1988 | ||
1989 | ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls)); | |
1990 | if (ret != 0) | |
1991 | dev_err(codec->dev, "Failed to add EQ control: %d\n", ret); | |
1992 | } | |
1993 | ||
1994 | static int max98095_get_bq_channel(const char *name) | |
1995 | { | |
1996 | if (strcmp(name, "Biquad1 Mode") == 0) | |
1997 | return 0; | |
1998 | if (strcmp(name, "Biquad2 Mode") == 0) | |
1999 | return 1; | |
2000 | return -EINVAL; | |
2001 | } | |
2002 | ||
2003 | static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol, | |
2004 | struct snd_ctl_elem_value *ucontrol) | |
2005 | { | |
2006 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
2007 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2008 | struct max98095_pdata *pdata = max98095->pdata; | |
2009 | int channel = max98095_get_bq_channel(kcontrol->id.name); | |
2010 | struct max98095_cdata *cdata; | |
2011 | int sel = ucontrol->value.integer.value[0]; | |
2012 | struct max98095_biquad_cfg *coef_set; | |
2013 | int fs, best, best_val, i; | |
2014 | int regmask, regsave; | |
2015 | ||
2016 | BUG_ON(channel > 1); | |
2017 | ||
53949425 TH |
2018 | if (!pdata || !max98095->bq_textcnt) |
2019 | return 0; | |
dad31ec1 PH |
2020 | |
2021 | if (sel >= pdata->bq_cfgcnt) | |
2022 | return -EINVAL; | |
2023 | ||
53949425 | 2024 | cdata = &max98095->dai[channel]; |
dad31ec1 | 2025 | cdata->bq_sel = sel; |
dad31ec1 PH |
2026 | fs = cdata->rate; |
2027 | ||
2028 | /* Find the selected configuration with nearest sample rate */ | |
2029 | best = 0; | |
2030 | best_val = INT_MAX; | |
2031 | for (i = 0; i < pdata->bq_cfgcnt; i++) { | |
2032 | if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 && | |
2033 | abs(pdata->bq_cfg[i].rate - fs) < best_val) { | |
2034 | best = i; | |
2035 | best_val = abs(pdata->bq_cfg[i].rate - fs); | |
2036 | } | |
2037 | } | |
2038 | ||
2039 | dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", | |
2040 | pdata->bq_cfg[best].name, | |
2041 | pdata->bq_cfg[best].rate, fs); | |
2042 | ||
2043 | coef_set = &pdata->bq_cfg[best]; | |
2044 | ||
2045 | regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN; | |
2046 | ||
2047 | /* Disable filter while configuring, and save current on/off state */ | |
2048 | regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); | |
2049 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); | |
2050 | ||
2051 | mutex_lock(&codec->mutex); | |
2052 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); | |
2053 | m98095_biquad_band(codec, channel, 0, coef_set->band1); | |
2054 | m98095_biquad_band(codec, channel, 1, coef_set->band2); | |
2055 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); | |
2056 | mutex_unlock(&codec->mutex); | |
2057 | ||
2058 | /* Restore the original on/off state */ | |
2059 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); | |
2060 | return 0; | |
2061 | } | |
2062 | ||
2063 | static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol, | |
2064 | struct snd_ctl_elem_value *ucontrol) | |
2065 | { | |
2066 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
2067 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2068 | int channel = max98095_get_bq_channel(kcontrol->id.name); | |
2069 | struct max98095_cdata *cdata; | |
2070 | ||
2071 | cdata = &max98095->dai[channel]; | |
2072 | ucontrol->value.enumerated.item[0] = cdata->bq_sel; | |
2073 | ||
2074 | return 0; | |
2075 | } | |
2076 | ||
2077 | static void max98095_handle_bq_pdata(struct snd_soc_codec *codec) | |
2078 | { | |
2079 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2080 | struct max98095_pdata *pdata = max98095->pdata; | |
2081 | struct max98095_biquad_cfg *cfg; | |
2082 | unsigned int cfgcnt; | |
2083 | int i, j; | |
2084 | const char **t; | |
2085 | int ret; | |
2086 | ||
2087 | struct snd_kcontrol_new controls[] = { | |
2088 | SOC_ENUM_EXT("Biquad1 Mode", | |
2089 | max98095->bq_enum, | |
2090 | max98095_get_bq_enum, | |
2091 | max98095_put_bq_enum), | |
2092 | SOC_ENUM_EXT("Biquad2 Mode", | |
2093 | max98095->bq_enum, | |
2094 | max98095_get_bq_enum, | |
2095 | max98095_put_bq_enum), | |
2096 | }; | |
2097 | ||
2098 | cfg = pdata->bq_cfg; | |
2099 | cfgcnt = pdata->bq_cfgcnt; | |
2100 | ||
2101 | /* Setup an array of texts for the biquad enum. | |
2102 | * This is based on Mark Brown's equalizer driver code. | |
2103 | */ | |
2104 | max98095->bq_textcnt = 0; | |
2105 | max98095->bq_texts = NULL; | |
2106 | for (i = 0; i < cfgcnt; i++) { | |
2107 | for (j = 0; j < max98095->bq_textcnt; j++) { | |
2108 | if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0) | |
2109 | break; | |
2110 | } | |
2111 | ||
2112 | if (j != max98095->bq_textcnt) | |
2113 | continue; | |
2114 | ||
2115 | /* Expand the array */ | |
2116 | t = krealloc(max98095->bq_texts, | |
2117 | sizeof(char *) * (max98095->bq_textcnt + 1), | |
2118 | GFP_KERNEL); | |
2119 | if (t == NULL) | |
2120 | continue; | |
2121 | ||
2122 | /* Store the new entry */ | |
2123 | t[max98095->bq_textcnt] = cfg[i].name; | |
2124 | max98095->bq_textcnt++; | |
2125 | max98095->bq_texts = t; | |
2126 | } | |
2127 | ||
2128 | /* Now point the soc_enum to .texts array items */ | |
2129 | max98095->bq_enum.texts = max98095->bq_texts; | |
2130 | max98095->bq_enum.max = max98095->bq_textcnt; | |
2131 | ||
2132 | ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls)); | |
2133 | if (ret != 0) | |
2134 | dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret); | |
2135 | } | |
2136 | ||
82a5a936 PH |
2137 | static void max98095_handle_pdata(struct snd_soc_codec *codec) |
2138 | { | |
2139 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2140 | struct max98095_pdata *pdata = max98095->pdata; | |
2141 | u8 regval = 0; | |
2142 | ||
2143 | if (!pdata) { | |
2144 | dev_dbg(codec->dev, "No platform data\n"); | |
2145 | return; | |
2146 | } | |
2147 | ||
2148 | /* Configure mic for analog/digital mic mode */ | |
2149 | if (pdata->digmic_left_mode) | |
2150 | regval |= M98095_DIGMIC_L; | |
2151 | ||
2152 | if (pdata->digmic_right_mode) | |
2153 | regval |= M98095_DIGMIC_R; | |
2154 | ||
2155 | snd_soc_write(codec, M98095_087_CFG_MIC, regval); | |
dad31ec1 PH |
2156 | |
2157 | /* Configure equalizers */ | |
2158 | if (pdata->eq_cfgcnt) | |
2159 | max98095_handle_eq_pdata(codec); | |
2160 | ||
2161 | /* Configure bi-quad filters */ | |
2162 | if (pdata->bq_cfgcnt) | |
2163 | max98095_handle_bq_pdata(codec); | |
82a5a936 PH |
2164 | } |
2165 | ||
2166 | #ifdef CONFIG_PM | |
2167 | static int max98095_suspend(struct snd_soc_codec *codec, pm_message_t state) | |
2168 | { | |
2169 | max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
2170 | ||
2171 | return 0; | |
2172 | } | |
2173 | ||
2174 | static int max98095_resume(struct snd_soc_codec *codec) | |
2175 | { | |
2176 | max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
2177 | ||
2178 | return 0; | |
2179 | } | |
2180 | #else | |
2181 | #define max98095_suspend NULL | |
2182 | #define max98095_resume NULL | |
2183 | #endif | |
2184 | ||
2185 | static int max98095_reset(struct snd_soc_codec *codec) | |
2186 | { | |
2187 | int i, ret; | |
2188 | ||
2189 | /* Gracefully reset the DSP core and the codec hardware | |
2190 | * in a proper sequence */ | |
2191 | ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0); | |
2192 | if (ret < 0) { | |
2193 | dev_err(codec->dev, "Failed to reset DSP: %d\n", ret); | |
2194 | return ret; | |
2195 | } | |
2196 | ||
2197 | ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0); | |
2198 | if (ret < 0) { | |
2199 | dev_err(codec->dev, "Failed to reset codec: %d\n", ret); | |
2200 | return ret; | |
2201 | } | |
2202 | ||
2203 | /* Reset to hardware default for registers, as there is not | |
2204 | * a soft reset hardware control register */ | |
2205 | for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) { | |
2206 | ret = snd_soc_write(codec, i, max98095_reg_def[i]); | |
2207 | if (ret < 0) { | |
2208 | dev_err(codec->dev, "Failed to reset: %d\n", ret); | |
2209 | return ret; | |
2210 | } | |
2211 | } | |
2212 | ||
2213 | return ret; | |
2214 | } | |
2215 | ||
2216 | static int max98095_probe(struct snd_soc_codec *codec) | |
2217 | { | |
2218 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2219 | struct max98095_cdata *cdata; | |
2220 | int ret = 0; | |
2221 | ||
2222 | ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); | |
2223 | if (ret != 0) { | |
2224 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
2225 | return ret; | |
2226 | } | |
2227 | ||
2228 | /* reset the codec, the DSP core, and disable all interrupts */ | |
2229 | max98095_reset(codec); | |
2230 | ||
2231 | /* initialize private data */ | |
2232 | ||
2233 | max98095->sysclk = (unsigned)-1; | |
dad31ec1 PH |
2234 | max98095->eq_textcnt = 0; |
2235 | max98095->bq_textcnt = 0; | |
82a5a936 PH |
2236 | |
2237 | cdata = &max98095->dai[0]; | |
2238 | cdata->rate = (unsigned)-1; | |
2239 | cdata->fmt = (unsigned)-1; | |
dad31ec1 PH |
2240 | cdata->eq_sel = 0; |
2241 | cdata->bq_sel = 0; | |
82a5a936 PH |
2242 | |
2243 | cdata = &max98095->dai[1]; | |
2244 | cdata->rate = (unsigned)-1; | |
2245 | cdata->fmt = (unsigned)-1; | |
dad31ec1 PH |
2246 | cdata->eq_sel = 0; |
2247 | cdata->bq_sel = 0; | |
82a5a936 PH |
2248 | |
2249 | cdata = &max98095->dai[2]; | |
2250 | cdata->rate = (unsigned)-1; | |
2251 | cdata->fmt = (unsigned)-1; | |
dad31ec1 PH |
2252 | cdata->eq_sel = 0; |
2253 | cdata->bq_sel = 0; | |
82a5a936 PH |
2254 | |
2255 | max98095->lin_state = 0; | |
2256 | max98095->mic1pre = 0; | |
2257 | max98095->mic2pre = 0; | |
2258 | ||
2259 | ret = snd_soc_read(codec, M98095_0FF_REV_ID); | |
2260 | if (ret < 0) { | |
bab3b59d | 2261 | dev_err(codec->dev, "Failure reading hardware revision: %d\n", |
82a5a936 PH |
2262 | ret); |
2263 | goto err_access; | |
2264 | } | |
bab3b59d | 2265 | dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A'); |
82a5a936 PH |
2266 | |
2267 | snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV); | |
2268 | ||
2269 | /* initialize registers cache to hardware default */ | |
2270 | max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
2271 | ||
2272 | snd_soc_write(codec, M98095_048_MIX_DAC_LR, | |
2273 | M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR); | |
2274 | ||
2275 | snd_soc_write(codec, M98095_049_MIX_DAC_M, | |
2276 | M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM); | |
2277 | ||
2278 | snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM); | |
2279 | snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL); | |
2280 | snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL); | |
2281 | ||
2282 | snd_soc_write(codec, M98095_02C_DAI1_IOCFG, | |
2283 | M98095_S1NORMAL|M98095_SDATA); | |
2284 | ||
2285 | snd_soc_write(codec, M98095_036_DAI2_IOCFG, | |
2286 | M98095_S2NORMAL|M98095_SDATA); | |
2287 | ||
2288 | snd_soc_write(codec, M98095_040_DAI3_IOCFG, | |
2289 | M98095_S3NORMAL|M98095_SDATA); | |
2290 | ||
2291 | max98095_handle_pdata(codec); | |
2292 | ||
2293 | /* take the codec out of the shut down */ | |
2294 | snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN, | |
2295 | M98095_SHDNRUN); | |
2296 | ||
2297 | max98095_add_widgets(codec); | |
2298 | ||
2299 | err_access: | |
2300 | return ret; | |
2301 | } | |
2302 | ||
2303 | static int max98095_remove(struct snd_soc_codec *codec) | |
2304 | { | |
2305 | max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
2306 | ||
2307 | return 0; | |
2308 | } | |
2309 | ||
2310 | static struct snd_soc_codec_driver soc_codec_dev_max98095 = { | |
2311 | .probe = max98095_probe, | |
2312 | .remove = max98095_remove, | |
2313 | .suspend = max98095_suspend, | |
2314 | .resume = max98095_resume, | |
2315 | .set_bias_level = max98095_set_bias_level, | |
2316 | .reg_cache_size = ARRAY_SIZE(max98095_reg_def), | |
2317 | .reg_word_size = sizeof(u8), | |
2318 | .reg_cache_default = max98095_reg_def, | |
2319 | .readable_register = max98095_readable, | |
2320 | .volatile_register = max98095_volatile, | |
2321 | .dapm_widgets = max98095_dapm_widgets, | |
2322 | .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets), | |
2323 | .dapm_routes = max98095_audio_map, | |
2324 | .num_dapm_routes = ARRAY_SIZE(max98095_audio_map), | |
2325 | }; | |
2326 | ||
2327 | static int max98095_i2c_probe(struct i2c_client *i2c, | |
2328 | const struct i2c_device_id *id) | |
2329 | { | |
2330 | struct max98095_priv *max98095; | |
2331 | int ret; | |
2332 | ||
2333 | max98095 = kzalloc(sizeof(struct max98095_priv), GFP_KERNEL); | |
2334 | if (max98095 == NULL) | |
2335 | return -ENOMEM; | |
2336 | ||
2337 | max98095->devtype = id->driver_data; | |
2338 | i2c_set_clientdata(i2c, max98095); | |
82a5a936 PH |
2339 | max98095->pdata = i2c->dev.platform_data; |
2340 | ||
bab3b59d TH |
2341 | ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98095, |
2342 | max98095_dai, ARRAY_SIZE(max98095_dai)); | |
82a5a936 PH |
2343 | if (ret < 0) |
2344 | kfree(max98095); | |
2345 | return ret; | |
2346 | } | |
2347 | ||
2348 | static int __devexit max98095_i2c_remove(struct i2c_client *client) | |
2349 | { | |
2350 | snd_soc_unregister_codec(&client->dev); | |
2351 | kfree(i2c_get_clientdata(client)); | |
2352 | ||
2353 | return 0; | |
2354 | } | |
2355 | ||
2356 | static const struct i2c_device_id max98095_i2c_id[] = { | |
2357 | { "max98095", MAX98095 }, | |
2358 | { } | |
2359 | }; | |
2360 | MODULE_DEVICE_TABLE(i2c, max98095_i2c_id); | |
2361 | ||
2362 | static struct i2c_driver max98095_i2c_driver = { | |
2363 | .driver = { | |
2364 | .name = "max98095", | |
2365 | .owner = THIS_MODULE, | |
2366 | }, | |
2367 | .probe = max98095_i2c_probe, | |
2368 | .remove = __devexit_p(max98095_i2c_remove), | |
2369 | .id_table = max98095_i2c_id, | |
2370 | }; | |
2371 | ||
2372 | static int __init max98095_init(void) | |
2373 | { | |
2374 | int ret; | |
2375 | ||
2376 | ret = i2c_add_driver(&max98095_i2c_driver); | |
2377 | if (ret) | |
2378 | pr_err("Failed to register max98095 I2C driver: %d\n", ret); | |
2379 | ||
2380 | return ret; | |
2381 | } | |
2382 | module_init(max98095_init); | |
2383 | ||
2384 | static void __exit max98095_exit(void) | |
2385 | { | |
2386 | i2c_del_driver(&max98095_i2c_driver); | |
2387 | } | |
2388 | module_exit(max98095_exit); | |
2389 | ||
2390 | MODULE_DESCRIPTION("ALSA SoC MAX98095 driver"); | |
2391 | MODULE_AUTHOR("Peter Hsiang"); | |
2392 | MODULE_LICENSE("GPL"); |