]>
Commit | Line | Data |
---|---|---|
82a5a936 PH |
1 | /* |
2 | * max98095.c -- MAX98095 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2011 Maxim Integrated Products | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/i2c.h> | |
82a5a936 PH |
18 | #include <sound/core.h> |
19 | #include <sound/pcm.h> | |
20 | #include <sound/pcm_params.h> | |
21 | #include <sound/soc.h> | |
22 | #include <sound/initval.h> | |
23 | #include <sound/tlv.h> | |
24 | #include <linux/slab.h> | |
25 | #include <asm/div64.h> | |
26 | #include <sound/max98095.h> | |
9dd90c5d | 27 | #include <sound/jack.h> |
82a5a936 PH |
28 | #include "max98095.h" |
29 | ||
30 | enum max98095_type { | |
31 | MAX98095, | |
32 | }; | |
33 | ||
34 | struct max98095_cdata { | |
35 | unsigned int rate; | |
36 | unsigned int fmt; | |
dad31ec1 PH |
37 | int eq_sel; |
38 | int bq_sel; | |
82a5a936 PH |
39 | }; |
40 | ||
41 | struct max98095_priv { | |
42 | enum max98095_type devtype; | |
82a5a936 PH |
43 | struct max98095_pdata *pdata; |
44 | unsigned int sysclk; | |
45 | struct max98095_cdata dai[3]; | |
dad31ec1 PH |
46 | const char **eq_texts; |
47 | const char **bq_texts; | |
48 | struct soc_enum eq_enum; | |
49 | struct soc_enum bq_enum; | |
50 | int eq_textcnt; | |
51 | int bq_textcnt; | |
82a5a936 PH |
52 | u8 lin_state; |
53 | unsigned int mic1pre; | |
54 | unsigned int mic2pre; | |
9dd90c5d RK |
55 | struct snd_soc_jack *headphone_jack; |
56 | struct snd_soc_jack *mic_jack; | |
82a5a936 PH |
57 | }; |
58 | ||
59 | static const u8 max98095_reg_def[M98095_REG_CNT] = { | |
60 | 0x00, /* 00 */ | |
61 | 0x00, /* 01 */ | |
62 | 0x00, /* 02 */ | |
63 | 0x00, /* 03 */ | |
64 | 0x00, /* 04 */ | |
65 | 0x00, /* 05 */ | |
66 | 0x00, /* 06 */ | |
67 | 0x00, /* 07 */ | |
68 | 0x00, /* 08 */ | |
69 | 0x00, /* 09 */ | |
70 | 0x00, /* 0A */ | |
71 | 0x00, /* 0B */ | |
72 | 0x00, /* 0C */ | |
73 | 0x00, /* 0D */ | |
74 | 0x00, /* 0E */ | |
75 | 0x00, /* 0F */ | |
76 | 0x00, /* 10 */ | |
77 | 0x00, /* 11 */ | |
78 | 0x00, /* 12 */ | |
79 | 0x00, /* 13 */ | |
80 | 0x00, /* 14 */ | |
81 | 0x00, /* 15 */ | |
82 | 0x00, /* 16 */ | |
83 | 0x00, /* 17 */ | |
84 | 0x00, /* 18 */ | |
85 | 0x00, /* 19 */ | |
86 | 0x00, /* 1A */ | |
87 | 0x00, /* 1B */ | |
88 | 0x00, /* 1C */ | |
89 | 0x00, /* 1D */ | |
90 | 0x00, /* 1E */ | |
91 | 0x00, /* 1F */ | |
92 | 0x00, /* 20 */ | |
93 | 0x00, /* 21 */ | |
94 | 0x00, /* 22 */ | |
95 | 0x00, /* 23 */ | |
96 | 0x00, /* 24 */ | |
97 | 0x00, /* 25 */ | |
98 | 0x00, /* 26 */ | |
99 | 0x00, /* 27 */ | |
100 | 0x00, /* 28 */ | |
101 | 0x00, /* 29 */ | |
102 | 0x00, /* 2A */ | |
103 | 0x00, /* 2B */ | |
104 | 0x00, /* 2C */ | |
105 | 0x00, /* 2D */ | |
106 | 0x00, /* 2E */ | |
107 | 0x00, /* 2F */ | |
108 | 0x00, /* 30 */ | |
109 | 0x00, /* 31 */ | |
110 | 0x00, /* 32 */ | |
111 | 0x00, /* 33 */ | |
112 | 0x00, /* 34 */ | |
113 | 0x00, /* 35 */ | |
114 | 0x00, /* 36 */ | |
115 | 0x00, /* 37 */ | |
116 | 0x00, /* 38 */ | |
117 | 0x00, /* 39 */ | |
118 | 0x00, /* 3A */ | |
119 | 0x00, /* 3B */ | |
120 | 0x00, /* 3C */ | |
121 | 0x00, /* 3D */ | |
122 | 0x00, /* 3E */ | |
123 | 0x00, /* 3F */ | |
124 | 0x00, /* 40 */ | |
125 | 0x00, /* 41 */ | |
126 | 0x00, /* 42 */ | |
127 | 0x00, /* 43 */ | |
128 | 0x00, /* 44 */ | |
129 | 0x00, /* 45 */ | |
130 | 0x00, /* 46 */ | |
131 | 0x00, /* 47 */ | |
132 | 0x00, /* 48 */ | |
133 | 0x00, /* 49 */ | |
134 | 0x00, /* 4A */ | |
135 | 0x00, /* 4B */ | |
136 | 0x00, /* 4C */ | |
137 | 0x00, /* 4D */ | |
138 | 0x00, /* 4E */ | |
139 | 0x00, /* 4F */ | |
140 | 0x00, /* 50 */ | |
141 | 0x00, /* 51 */ | |
142 | 0x00, /* 52 */ | |
143 | 0x00, /* 53 */ | |
144 | 0x00, /* 54 */ | |
145 | 0x00, /* 55 */ | |
146 | 0x00, /* 56 */ | |
147 | 0x00, /* 57 */ | |
148 | 0x00, /* 58 */ | |
149 | 0x00, /* 59 */ | |
150 | 0x00, /* 5A */ | |
151 | 0x00, /* 5B */ | |
152 | 0x00, /* 5C */ | |
153 | 0x00, /* 5D */ | |
154 | 0x00, /* 5E */ | |
155 | 0x00, /* 5F */ | |
156 | 0x00, /* 60 */ | |
157 | 0x00, /* 61 */ | |
158 | 0x00, /* 62 */ | |
159 | 0x00, /* 63 */ | |
160 | 0x00, /* 64 */ | |
161 | 0x00, /* 65 */ | |
162 | 0x00, /* 66 */ | |
163 | 0x00, /* 67 */ | |
164 | 0x00, /* 68 */ | |
165 | 0x00, /* 69 */ | |
166 | 0x00, /* 6A */ | |
167 | 0x00, /* 6B */ | |
168 | 0x00, /* 6C */ | |
169 | 0x00, /* 6D */ | |
170 | 0x00, /* 6E */ | |
171 | 0x00, /* 6F */ | |
172 | 0x00, /* 70 */ | |
173 | 0x00, /* 71 */ | |
174 | 0x00, /* 72 */ | |
175 | 0x00, /* 73 */ | |
176 | 0x00, /* 74 */ | |
177 | 0x00, /* 75 */ | |
178 | 0x00, /* 76 */ | |
179 | 0x00, /* 77 */ | |
180 | 0x00, /* 78 */ | |
181 | 0x00, /* 79 */ | |
182 | 0x00, /* 7A */ | |
183 | 0x00, /* 7B */ | |
184 | 0x00, /* 7C */ | |
185 | 0x00, /* 7D */ | |
186 | 0x00, /* 7E */ | |
187 | 0x00, /* 7F */ | |
188 | 0x00, /* 80 */ | |
189 | 0x00, /* 81 */ | |
190 | 0x00, /* 82 */ | |
191 | 0x00, /* 83 */ | |
192 | 0x00, /* 84 */ | |
193 | 0x00, /* 85 */ | |
194 | 0x00, /* 86 */ | |
195 | 0x00, /* 87 */ | |
196 | 0x00, /* 88 */ | |
197 | 0x00, /* 89 */ | |
198 | 0x00, /* 8A */ | |
199 | 0x00, /* 8B */ | |
200 | 0x00, /* 8C */ | |
201 | 0x00, /* 8D */ | |
202 | 0x00, /* 8E */ | |
203 | 0x00, /* 8F */ | |
204 | 0x00, /* 90 */ | |
205 | 0x00, /* 91 */ | |
206 | 0x30, /* 92 */ | |
207 | 0xF0, /* 93 */ | |
208 | 0x00, /* 94 */ | |
209 | 0x00, /* 95 */ | |
210 | 0x3F, /* 96 */ | |
211 | 0x00, /* 97 */ | |
212 | 0x00, /* 98 */ | |
213 | 0x00, /* 99 */ | |
214 | 0x00, /* 9A */ | |
215 | 0x00, /* 9B */ | |
216 | 0x00, /* 9C */ | |
217 | 0x00, /* 9D */ | |
218 | 0x00, /* 9E */ | |
219 | 0x00, /* 9F */ | |
220 | 0x00, /* A0 */ | |
221 | 0x00, /* A1 */ | |
222 | 0x00, /* A2 */ | |
223 | 0x00, /* A3 */ | |
224 | 0x00, /* A4 */ | |
225 | 0x00, /* A5 */ | |
226 | 0x00, /* A6 */ | |
227 | 0x00, /* A7 */ | |
228 | 0x00, /* A8 */ | |
229 | 0x00, /* A9 */ | |
230 | 0x00, /* AA */ | |
231 | 0x00, /* AB */ | |
232 | 0x00, /* AC */ | |
233 | 0x00, /* AD */ | |
234 | 0x00, /* AE */ | |
235 | 0x00, /* AF */ | |
236 | 0x00, /* B0 */ | |
237 | 0x00, /* B1 */ | |
238 | 0x00, /* B2 */ | |
239 | 0x00, /* B3 */ | |
240 | 0x00, /* B4 */ | |
241 | 0x00, /* B5 */ | |
242 | 0x00, /* B6 */ | |
243 | 0x00, /* B7 */ | |
244 | 0x00, /* B8 */ | |
245 | 0x00, /* B9 */ | |
246 | 0x00, /* BA */ | |
247 | 0x00, /* BB */ | |
248 | 0x00, /* BC */ | |
249 | 0x00, /* BD */ | |
250 | 0x00, /* BE */ | |
251 | 0x00, /* BF */ | |
252 | 0x00, /* C0 */ | |
253 | 0x00, /* C1 */ | |
254 | 0x00, /* C2 */ | |
255 | 0x00, /* C3 */ | |
256 | 0x00, /* C4 */ | |
257 | 0x00, /* C5 */ | |
258 | 0x00, /* C6 */ | |
259 | 0x00, /* C7 */ | |
260 | 0x00, /* C8 */ | |
261 | 0x00, /* C9 */ | |
262 | 0x00, /* CA */ | |
263 | 0x00, /* CB */ | |
264 | 0x00, /* CC */ | |
265 | 0x00, /* CD */ | |
266 | 0x00, /* CE */ | |
267 | 0x00, /* CF */ | |
268 | 0x00, /* D0 */ | |
269 | 0x00, /* D1 */ | |
270 | 0x00, /* D2 */ | |
271 | 0x00, /* D3 */ | |
272 | 0x00, /* D4 */ | |
273 | 0x00, /* D5 */ | |
274 | 0x00, /* D6 */ | |
275 | 0x00, /* D7 */ | |
276 | 0x00, /* D8 */ | |
277 | 0x00, /* D9 */ | |
278 | 0x00, /* DA */ | |
279 | 0x00, /* DB */ | |
280 | 0x00, /* DC */ | |
281 | 0x00, /* DD */ | |
282 | 0x00, /* DE */ | |
283 | 0x00, /* DF */ | |
284 | 0x00, /* E0 */ | |
285 | 0x00, /* E1 */ | |
286 | 0x00, /* E2 */ | |
287 | 0x00, /* E3 */ | |
288 | 0x00, /* E4 */ | |
289 | 0x00, /* E5 */ | |
290 | 0x00, /* E6 */ | |
291 | 0x00, /* E7 */ | |
292 | 0x00, /* E8 */ | |
293 | 0x00, /* E9 */ | |
294 | 0x00, /* EA */ | |
295 | 0x00, /* EB */ | |
296 | 0x00, /* EC */ | |
297 | 0x00, /* ED */ | |
298 | 0x00, /* EE */ | |
299 | 0x00, /* EF */ | |
300 | 0x00, /* F0 */ | |
301 | 0x00, /* F1 */ | |
302 | 0x00, /* F2 */ | |
303 | 0x00, /* F3 */ | |
304 | 0x00, /* F4 */ | |
305 | 0x00, /* F5 */ | |
306 | 0x00, /* F6 */ | |
307 | 0x00, /* F7 */ | |
308 | 0x00, /* F8 */ | |
309 | 0x00, /* F9 */ | |
310 | 0x00, /* FA */ | |
311 | 0x00, /* FB */ | |
312 | 0x00, /* FC */ | |
313 | 0x00, /* FD */ | |
314 | 0x00, /* FE */ | |
315 | 0x00, /* FF */ | |
316 | }; | |
317 | ||
318 | static struct { | |
319 | int readable; | |
320 | int writable; | |
321 | } max98095_access[M98095_REG_CNT] = { | |
322 | { 0x00, 0x00 }, /* 00 */ | |
323 | { 0xFF, 0x00 }, /* 01 */ | |
324 | { 0xFF, 0x00 }, /* 02 */ | |
325 | { 0xFF, 0x00 }, /* 03 */ | |
326 | { 0xFF, 0x00 }, /* 04 */ | |
327 | { 0xFF, 0x00 }, /* 05 */ | |
328 | { 0xFF, 0x00 }, /* 06 */ | |
329 | { 0xFF, 0x00 }, /* 07 */ | |
330 | { 0xFF, 0x00 }, /* 08 */ | |
331 | { 0xFF, 0x00 }, /* 09 */ | |
332 | { 0xFF, 0x00 }, /* 0A */ | |
333 | { 0xFF, 0x00 }, /* 0B */ | |
334 | { 0xFF, 0x00 }, /* 0C */ | |
335 | { 0xFF, 0x00 }, /* 0D */ | |
336 | { 0xFF, 0x00 }, /* 0E */ | |
337 | { 0xFF, 0x9F }, /* 0F */ | |
338 | { 0xFF, 0xFF }, /* 10 */ | |
339 | { 0xFF, 0xFF }, /* 11 */ | |
340 | { 0xFF, 0xFF }, /* 12 */ | |
341 | { 0xFF, 0xFF }, /* 13 */ | |
342 | { 0xFF, 0xFF }, /* 14 */ | |
343 | { 0xFF, 0xFF }, /* 15 */ | |
344 | { 0xFF, 0xFF }, /* 16 */ | |
345 | { 0xFF, 0xFF }, /* 17 */ | |
346 | { 0xFF, 0xFF }, /* 18 */ | |
347 | { 0xFF, 0xFF }, /* 19 */ | |
348 | { 0xFF, 0xFF }, /* 1A */ | |
349 | { 0xFF, 0xFF }, /* 1B */ | |
350 | { 0xFF, 0xFF }, /* 1C */ | |
351 | { 0xFF, 0xFF }, /* 1D */ | |
352 | { 0xFF, 0x77 }, /* 1E */ | |
353 | { 0xFF, 0x77 }, /* 1F */ | |
354 | { 0xFF, 0x77 }, /* 20 */ | |
355 | { 0xFF, 0x77 }, /* 21 */ | |
356 | { 0xFF, 0x77 }, /* 22 */ | |
357 | { 0xFF, 0x77 }, /* 23 */ | |
358 | { 0xFF, 0xFF }, /* 24 */ | |
359 | { 0xFF, 0x7F }, /* 25 */ | |
360 | { 0xFF, 0x31 }, /* 26 */ | |
361 | { 0xFF, 0xFF }, /* 27 */ | |
362 | { 0xFF, 0xFF }, /* 28 */ | |
363 | { 0xFF, 0xFF }, /* 29 */ | |
364 | { 0xFF, 0xF7 }, /* 2A */ | |
365 | { 0xFF, 0x2F }, /* 2B */ | |
366 | { 0xFF, 0xEF }, /* 2C */ | |
367 | { 0xFF, 0xFF }, /* 2D */ | |
368 | { 0xFF, 0xFF }, /* 2E */ | |
369 | { 0xFF, 0xFF }, /* 2F */ | |
370 | { 0xFF, 0xFF }, /* 30 */ | |
371 | { 0xFF, 0xFF }, /* 31 */ | |
372 | { 0xFF, 0xFF }, /* 32 */ | |
373 | { 0xFF, 0xFF }, /* 33 */ | |
374 | { 0xFF, 0xF7 }, /* 34 */ | |
375 | { 0xFF, 0x2F }, /* 35 */ | |
376 | { 0xFF, 0xCF }, /* 36 */ | |
377 | { 0xFF, 0xFF }, /* 37 */ | |
378 | { 0xFF, 0xFF }, /* 38 */ | |
379 | { 0xFF, 0xFF }, /* 39 */ | |
380 | { 0xFF, 0xFF }, /* 3A */ | |
381 | { 0xFF, 0xFF }, /* 3B */ | |
382 | { 0xFF, 0xFF }, /* 3C */ | |
383 | { 0xFF, 0xFF }, /* 3D */ | |
384 | { 0xFF, 0xF7 }, /* 3E */ | |
385 | { 0xFF, 0x2F }, /* 3F */ | |
386 | { 0xFF, 0xCF }, /* 40 */ | |
387 | { 0xFF, 0xFF }, /* 41 */ | |
388 | { 0xFF, 0x77 }, /* 42 */ | |
389 | { 0xFF, 0xFF }, /* 43 */ | |
390 | { 0xFF, 0xFF }, /* 44 */ | |
391 | { 0xFF, 0xFF }, /* 45 */ | |
392 | { 0xFF, 0xFF }, /* 46 */ | |
393 | { 0xFF, 0xFF }, /* 47 */ | |
394 | { 0xFF, 0xFF }, /* 48 */ | |
395 | { 0xFF, 0x0F }, /* 49 */ | |
396 | { 0xFF, 0xFF }, /* 4A */ | |
397 | { 0xFF, 0xFF }, /* 4B */ | |
398 | { 0xFF, 0x3F }, /* 4C */ | |
399 | { 0xFF, 0x3F }, /* 4D */ | |
400 | { 0xFF, 0x3F }, /* 4E */ | |
401 | { 0xFF, 0xFF }, /* 4F */ | |
402 | { 0xFF, 0x7F }, /* 50 */ | |
403 | { 0xFF, 0x7F }, /* 51 */ | |
404 | { 0xFF, 0x0F }, /* 52 */ | |
405 | { 0xFF, 0x3F }, /* 53 */ | |
406 | { 0xFF, 0x3F }, /* 54 */ | |
407 | { 0xFF, 0x3F }, /* 55 */ | |
408 | { 0xFF, 0xFF }, /* 56 */ | |
409 | { 0xFF, 0xFF }, /* 57 */ | |
410 | { 0xFF, 0xBF }, /* 58 */ | |
411 | { 0xFF, 0x1F }, /* 59 */ | |
412 | { 0xFF, 0xBF }, /* 5A */ | |
413 | { 0xFF, 0x1F }, /* 5B */ | |
414 | { 0xFF, 0xBF }, /* 5C */ | |
415 | { 0xFF, 0x3F }, /* 5D */ | |
416 | { 0xFF, 0x3F }, /* 5E */ | |
417 | { 0xFF, 0x7F }, /* 5F */ | |
418 | { 0xFF, 0x7F }, /* 60 */ | |
419 | { 0xFF, 0x47 }, /* 61 */ | |
420 | { 0xFF, 0x9F }, /* 62 */ | |
421 | { 0xFF, 0x9F }, /* 63 */ | |
422 | { 0xFF, 0x9F }, /* 64 */ | |
423 | { 0xFF, 0x9F }, /* 65 */ | |
424 | { 0xFF, 0x9F }, /* 66 */ | |
425 | { 0xFF, 0xBF }, /* 67 */ | |
426 | { 0xFF, 0xBF }, /* 68 */ | |
427 | { 0xFF, 0xFF }, /* 69 */ | |
428 | { 0xFF, 0xFF }, /* 6A */ | |
429 | { 0xFF, 0x7F }, /* 6B */ | |
430 | { 0xFF, 0xF7 }, /* 6C */ | |
431 | { 0xFF, 0xFF }, /* 6D */ | |
432 | { 0xFF, 0xFF }, /* 6E */ | |
433 | { 0xFF, 0x1F }, /* 6F */ | |
434 | { 0xFF, 0xF7 }, /* 70 */ | |
435 | { 0xFF, 0xFF }, /* 71 */ | |
436 | { 0xFF, 0xFF }, /* 72 */ | |
437 | { 0xFF, 0x1F }, /* 73 */ | |
438 | { 0xFF, 0xF7 }, /* 74 */ | |
439 | { 0xFF, 0xFF }, /* 75 */ | |
440 | { 0xFF, 0xFF }, /* 76 */ | |
441 | { 0xFF, 0x1F }, /* 77 */ | |
442 | { 0xFF, 0xF7 }, /* 78 */ | |
443 | { 0xFF, 0xFF }, /* 79 */ | |
444 | { 0xFF, 0xFF }, /* 7A */ | |
445 | { 0xFF, 0x1F }, /* 7B */ | |
446 | { 0xFF, 0xF7 }, /* 7C */ | |
447 | { 0xFF, 0xFF }, /* 7D */ | |
448 | { 0xFF, 0xFF }, /* 7E */ | |
449 | { 0xFF, 0x1F }, /* 7F */ | |
450 | { 0xFF, 0xF7 }, /* 80 */ | |
451 | { 0xFF, 0xFF }, /* 81 */ | |
452 | { 0xFF, 0xFF }, /* 82 */ | |
453 | { 0xFF, 0x1F }, /* 83 */ | |
454 | { 0xFF, 0x7F }, /* 84 */ | |
455 | { 0xFF, 0x0F }, /* 85 */ | |
456 | { 0xFF, 0xD8 }, /* 86 */ | |
457 | { 0xFF, 0xFF }, /* 87 */ | |
458 | { 0xFF, 0xEF }, /* 88 */ | |
459 | { 0xFF, 0xFE }, /* 89 */ | |
460 | { 0xFF, 0xFE }, /* 8A */ | |
461 | { 0xFF, 0xFF }, /* 8B */ | |
462 | { 0xFF, 0xFF }, /* 8C */ | |
463 | { 0xFF, 0x3F }, /* 8D */ | |
464 | { 0xFF, 0xFF }, /* 8E */ | |
465 | { 0xFF, 0x3F }, /* 8F */ | |
466 | { 0xFF, 0x8F }, /* 90 */ | |
467 | { 0xFF, 0xFF }, /* 91 */ | |
468 | { 0xFF, 0x3F }, /* 92 */ | |
469 | { 0xFF, 0xFF }, /* 93 */ | |
470 | { 0xFF, 0xFF }, /* 94 */ | |
471 | { 0xFF, 0x0F }, /* 95 */ | |
472 | { 0xFF, 0x3F }, /* 96 */ | |
473 | { 0xFF, 0x8C }, /* 97 */ | |
474 | { 0x00, 0x00 }, /* 98 */ | |
475 | { 0x00, 0x00 }, /* 99 */ | |
476 | { 0x00, 0x00 }, /* 9A */ | |
477 | { 0x00, 0x00 }, /* 9B */ | |
478 | { 0x00, 0x00 }, /* 9C */ | |
479 | { 0x00, 0x00 }, /* 9D */ | |
480 | { 0x00, 0x00 }, /* 9E */ | |
481 | { 0x00, 0x00 }, /* 9F */ | |
482 | { 0x00, 0x00 }, /* A0 */ | |
483 | { 0x00, 0x00 }, /* A1 */ | |
484 | { 0x00, 0x00 }, /* A2 */ | |
485 | { 0x00, 0x00 }, /* A3 */ | |
486 | { 0x00, 0x00 }, /* A4 */ | |
487 | { 0x00, 0x00 }, /* A5 */ | |
488 | { 0x00, 0x00 }, /* A6 */ | |
489 | { 0x00, 0x00 }, /* A7 */ | |
490 | { 0x00, 0x00 }, /* A8 */ | |
491 | { 0x00, 0x00 }, /* A9 */ | |
492 | { 0x00, 0x00 }, /* AA */ | |
493 | { 0x00, 0x00 }, /* AB */ | |
494 | { 0x00, 0x00 }, /* AC */ | |
495 | { 0x00, 0x00 }, /* AD */ | |
496 | { 0x00, 0x00 }, /* AE */ | |
497 | { 0x00, 0x00 }, /* AF */ | |
498 | { 0x00, 0x00 }, /* B0 */ | |
499 | { 0x00, 0x00 }, /* B1 */ | |
500 | { 0x00, 0x00 }, /* B2 */ | |
501 | { 0x00, 0x00 }, /* B3 */ | |
502 | { 0x00, 0x00 }, /* B4 */ | |
503 | { 0x00, 0x00 }, /* B5 */ | |
504 | { 0x00, 0x00 }, /* B6 */ | |
505 | { 0x00, 0x00 }, /* B7 */ | |
506 | { 0x00, 0x00 }, /* B8 */ | |
507 | { 0x00, 0x00 }, /* B9 */ | |
508 | { 0x00, 0x00 }, /* BA */ | |
509 | { 0x00, 0x00 }, /* BB */ | |
510 | { 0x00, 0x00 }, /* BC */ | |
511 | { 0x00, 0x00 }, /* BD */ | |
512 | { 0x00, 0x00 }, /* BE */ | |
513 | { 0x00, 0x00 }, /* BF */ | |
514 | { 0x00, 0x00 }, /* C0 */ | |
515 | { 0x00, 0x00 }, /* C1 */ | |
516 | { 0x00, 0x00 }, /* C2 */ | |
517 | { 0x00, 0x00 }, /* C3 */ | |
518 | { 0x00, 0x00 }, /* C4 */ | |
519 | { 0x00, 0x00 }, /* C5 */ | |
520 | { 0x00, 0x00 }, /* C6 */ | |
521 | { 0x00, 0x00 }, /* C7 */ | |
522 | { 0x00, 0x00 }, /* C8 */ | |
523 | { 0x00, 0x00 }, /* C9 */ | |
524 | { 0x00, 0x00 }, /* CA */ | |
525 | { 0x00, 0x00 }, /* CB */ | |
526 | { 0x00, 0x00 }, /* CC */ | |
527 | { 0x00, 0x00 }, /* CD */ | |
528 | { 0x00, 0x00 }, /* CE */ | |
529 | { 0x00, 0x00 }, /* CF */ | |
530 | { 0x00, 0x00 }, /* D0 */ | |
531 | { 0x00, 0x00 }, /* D1 */ | |
532 | { 0x00, 0x00 }, /* D2 */ | |
533 | { 0x00, 0x00 }, /* D3 */ | |
534 | { 0x00, 0x00 }, /* D4 */ | |
535 | { 0x00, 0x00 }, /* D5 */ | |
536 | { 0x00, 0x00 }, /* D6 */ | |
537 | { 0x00, 0x00 }, /* D7 */ | |
538 | { 0x00, 0x00 }, /* D8 */ | |
539 | { 0x00, 0x00 }, /* D9 */ | |
540 | { 0x00, 0x00 }, /* DA */ | |
541 | { 0x00, 0x00 }, /* DB */ | |
542 | { 0x00, 0x00 }, /* DC */ | |
543 | { 0x00, 0x00 }, /* DD */ | |
544 | { 0x00, 0x00 }, /* DE */ | |
545 | { 0x00, 0x00 }, /* DF */ | |
546 | { 0x00, 0x00 }, /* E0 */ | |
547 | { 0x00, 0x00 }, /* E1 */ | |
548 | { 0x00, 0x00 }, /* E2 */ | |
549 | { 0x00, 0x00 }, /* E3 */ | |
550 | { 0x00, 0x00 }, /* E4 */ | |
551 | { 0x00, 0x00 }, /* E5 */ | |
552 | { 0x00, 0x00 }, /* E6 */ | |
553 | { 0x00, 0x00 }, /* E7 */ | |
554 | { 0x00, 0x00 }, /* E8 */ | |
555 | { 0x00, 0x00 }, /* E9 */ | |
556 | { 0x00, 0x00 }, /* EA */ | |
557 | { 0x00, 0x00 }, /* EB */ | |
558 | { 0x00, 0x00 }, /* EC */ | |
559 | { 0x00, 0x00 }, /* ED */ | |
560 | { 0x00, 0x00 }, /* EE */ | |
561 | { 0x00, 0x00 }, /* EF */ | |
562 | { 0x00, 0x00 }, /* F0 */ | |
563 | { 0x00, 0x00 }, /* F1 */ | |
564 | { 0x00, 0x00 }, /* F2 */ | |
565 | { 0x00, 0x00 }, /* F3 */ | |
566 | { 0x00, 0x00 }, /* F4 */ | |
567 | { 0x00, 0x00 }, /* F5 */ | |
568 | { 0x00, 0x00 }, /* F6 */ | |
569 | { 0x00, 0x00 }, /* F7 */ | |
570 | { 0x00, 0x00 }, /* F8 */ | |
571 | { 0x00, 0x00 }, /* F9 */ | |
572 | { 0x00, 0x00 }, /* FA */ | |
573 | { 0x00, 0x00 }, /* FB */ | |
574 | { 0x00, 0x00 }, /* FC */ | |
575 | { 0x00, 0x00 }, /* FD */ | |
576 | { 0x00, 0x00 }, /* FE */ | |
577 | { 0xFF, 0x00 }, /* FF */ | |
578 | }; | |
579 | ||
580 | static int max98095_readable(struct snd_soc_codec *codec, unsigned int reg) | |
581 | { | |
582 | if (reg >= M98095_REG_CNT) | |
583 | return 0; | |
584 | return max98095_access[reg].readable != 0; | |
585 | } | |
586 | ||
587 | static int max98095_volatile(struct snd_soc_codec *codec, unsigned int reg) | |
588 | { | |
589 | if (reg > M98095_REG_MAX_CACHED) | |
590 | return 1; | |
591 | ||
592 | switch (reg) { | |
593 | case M98095_000_HOST_DATA: | |
594 | case M98095_001_HOST_INT_STS: | |
595 | case M98095_002_HOST_RSP_STS: | |
596 | case M98095_003_HOST_CMD_STS: | |
597 | case M98095_004_CODEC_STS: | |
598 | case M98095_005_DAI1_ALC_STS: | |
599 | case M98095_006_DAI2_ALC_STS: | |
600 | case M98095_007_JACK_AUTO_STS: | |
601 | case M98095_008_JACK_MANUAL_STS: | |
602 | case M98095_009_JACK_VBAT_STS: | |
603 | case M98095_00A_ACC_ADC_STS: | |
604 | case M98095_00B_MIC_NG_AGC_STS: | |
605 | case M98095_00C_SPK_L_VOLT_STS: | |
606 | case M98095_00D_SPK_R_VOLT_STS: | |
607 | case M98095_00E_TEMP_SENSOR_STS: | |
608 | return 1; | |
609 | } | |
610 | ||
611 | return 0; | |
612 | } | |
613 | ||
dad31ec1 PH |
614 | /* |
615 | * Filter coefficients are in a separate register segment | |
616 | * and they share the address space of the normal registers. | |
617 | * The coefficient registers do not need or share the cache. | |
618 | */ | |
619 | static int max98095_hw_write(struct snd_soc_codec *codec, unsigned int reg, | |
620 | unsigned int value) | |
621 | { | |
0d8d2938 | 622 | int ret; |
dad31ec1 | 623 | |
0d8d2938 AL |
624 | codec->cache_bypass = 1; |
625 | ret = snd_soc_write(codec, reg, value); | |
626 | codec->cache_bypass = 0; | |
627 | ||
628 | return ret ? -EIO : 0; | |
dad31ec1 PH |
629 | } |
630 | ||
631 | /* | |
632 | * Load equalizer DSP coefficient configurations registers | |
633 | */ | |
634 | static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai, | |
635 | unsigned int band, u16 *coefs) | |
636 | { | |
637 | unsigned int eq_reg; | |
638 | unsigned int i; | |
639 | ||
640 | BUG_ON(band > 4); | |
641 | BUG_ON(dai > 1); | |
642 | ||
643 | /* Load the base register address */ | |
644 | eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE; | |
645 | ||
646 | /* Add the band address offset, note adjustment for word address */ | |
647 | eq_reg += band * (M98095_COEFS_PER_BAND << 1); | |
648 | ||
649 | /* Step through the registers and coefs */ | |
650 | for (i = 0; i < M98095_COEFS_PER_BAND; i++) { | |
651 | max98095_hw_write(codec, eq_reg++, M98095_BYTE1(coefs[i])); | |
652 | max98095_hw_write(codec, eq_reg++, M98095_BYTE0(coefs[i])); | |
653 | } | |
654 | } | |
655 | ||
656 | /* | |
657 | * Load biquad filter coefficient configurations registers | |
658 | */ | |
659 | static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai, | |
660 | unsigned int band, u16 *coefs) | |
661 | { | |
662 | unsigned int bq_reg; | |
663 | unsigned int i; | |
664 | ||
665 | BUG_ON(band > 1); | |
666 | BUG_ON(dai > 1); | |
667 | ||
668 | /* Load the base register address */ | |
669 | bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE; | |
670 | ||
671 | /* Add the band address offset, note adjustment for word address */ | |
672 | bq_reg += band * (M98095_COEFS_PER_BAND << 1); | |
673 | ||
674 | /* Step through the registers and coefs */ | |
675 | for (i = 0; i < M98095_COEFS_PER_BAND; i++) { | |
676 | max98095_hw_write(codec, bq_reg++, M98095_BYTE1(coefs[i])); | |
677 | max98095_hw_write(codec, bq_reg++, M98095_BYTE0(coefs[i])); | |
678 | } | |
679 | } | |
680 | ||
82a5a936 PH |
681 | static const char * const max98095_fltr_mode[] = { "Voice", "Music" }; |
682 | static const struct soc_enum max98095_dai1_filter_mode_enum[] = { | |
683 | SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 7, 2, max98095_fltr_mode), | |
684 | }; | |
685 | static const struct soc_enum max98095_dai2_filter_mode_enum[] = { | |
686 | SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 7, 2, max98095_fltr_mode), | |
687 | }; | |
688 | ||
689 | static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" }; | |
690 | ||
691 | static const struct soc_enum max98095_extmic_enum = | |
692 | SOC_ENUM_SINGLE(M98095_087_CFG_MIC, 0, 3, max98095_extmic_text); | |
693 | ||
694 | static const struct snd_kcontrol_new max98095_extmic_mux = | |
695 | SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum); | |
696 | ||
697 | static const char * const max98095_linein_text[] = { "INA", "INB" }; | |
698 | ||
699 | static const struct soc_enum max98095_linein_enum = | |
700 | SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 6, 2, max98095_linein_text); | |
701 | ||
702 | static const struct snd_kcontrol_new max98095_linein_mux = | |
703 | SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum); | |
704 | ||
705 | static const char * const max98095_line_mode_text[] = { | |
706 | "Stereo", "Differential"}; | |
707 | ||
708 | static const struct soc_enum max98095_linein_mode_enum = | |
709 | SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 7, 2, max98095_line_mode_text); | |
710 | ||
711 | static const struct soc_enum max98095_lineout_mode_enum = | |
712 | SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 4, 2, max98095_line_mode_text); | |
713 | ||
714 | static const char * const max98095_dai_fltr[] = { | |
715 | "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k", | |
716 | "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"}; | |
717 | static const struct soc_enum max98095_dai1_dac_filter_enum[] = { | |
718 | SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 0, 6, max98095_dai_fltr), | |
719 | }; | |
720 | static const struct soc_enum max98095_dai2_dac_filter_enum[] = { | |
721 | SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 0, 6, max98095_dai_fltr), | |
722 | }; | |
723 | static const struct soc_enum max98095_dai3_dac_filter_enum[] = { | |
724 | SOC_ENUM_SINGLE(M98095_042_DAI3_FILTERS, 0, 6, max98095_dai_fltr), | |
725 | }; | |
726 | ||
727 | static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol, | |
728 | struct snd_ctl_elem_value *ucontrol) | |
729 | { | |
730 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
731 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
732 | unsigned int sel = ucontrol->value.integer.value[0]; | |
733 | ||
734 | max98095->mic1pre = sel; | |
735 | snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK, | |
736 | (1+sel)<<M98095_MICPRE_SHIFT); | |
737 | ||
738 | return 0; | |
739 | } | |
740 | ||
741 | static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol, | |
742 | struct snd_ctl_elem_value *ucontrol) | |
743 | { | |
744 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
745 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
746 | ||
747 | ucontrol->value.integer.value[0] = max98095->mic1pre; | |
748 | return 0; | |
749 | } | |
750 | ||
751 | static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol, | |
752 | struct snd_ctl_elem_value *ucontrol) | |
753 | { | |
754 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
755 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
756 | unsigned int sel = ucontrol->value.integer.value[0]; | |
757 | ||
758 | max98095->mic2pre = sel; | |
759 | snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK, | |
760 | (1+sel)<<M98095_MICPRE_SHIFT); | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol, | |
766 | struct snd_ctl_elem_value *ucontrol) | |
767 | { | |
768 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
769 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
770 | ||
771 | ucontrol->value.integer.value[0] = max98095->mic2pre; | |
772 | return 0; | |
773 | } | |
774 | ||
775 | static const unsigned int max98095_micboost_tlv[] = { | |
776 | TLV_DB_RANGE_HEAD(2), | |
777 | 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), | |
778 | 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), | |
779 | }; | |
780 | ||
781 | static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0); | |
782 | static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0); | |
783 | static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0); | |
784 | ||
785 | static const unsigned int max98095_hp_tlv[] = { | |
786 | TLV_DB_RANGE_HEAD(5), | |
787 | 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), | |
788 | 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), | |
789 | 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), | |
790 | 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), | |
791 | 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0), | |
792 | }; | |
793 | ||
794 | static const unsigned int max98095_spk_tlv[] = { | |
795 | TLV_DB_RANGE_HEAD(4), | |
796 | 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0), | |
797 | 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0), | |
798 | 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0), | |
799 | 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0), | |
800 | }; | |
801 | ||
802 | static const unsigned int max98095_rcv_lout_tlv[] = { | |
803 | TLV_DB_RANGE_HEAD(5), | |
804 | 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), | |
805 | 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), | |
806 | 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), | |
807 | 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), | |
808 | 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0), | |
809 | }; | |
810 | ||
811 | static const unsigned int max98095_lin_tlv[] = { | |
812 | TLV_DB_RANGE_HEAD(3), | |
813 | 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0), | |
814 | 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0), | |
815 | 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0), | |
816 | }; | |
817 | ||
818 | static const struct snd_kcontrol_new max98095_snd_controls[] = { | |
819 | ||
820 | SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L, | |
821 | M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv), | |
822 | ||
823 | SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L, | |
824 | M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv), | |
825 | ||
826 | SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV, | |
827 | 0, 31, 0, max98095_rcv_lout_tlv), | |
828 | ||
829 | SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1, | |
830 | M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv), | |
831 | ||
832 | SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L, | |
833 | M98095_065_LVL_HP_R, 7, 1, 1), | |
834 | ||
835 | SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L, | |
836 | M98095_068_LVL_SPK_R, 7, 1, 1), | |
837 | ||
838 | SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1), | |
839 | ||
840 | SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1, | |
841 | M98095_063_LVL_LINEOUT2, 7, 1, 1), | |
842 | ||
843 | SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1, | |
844 | max98095_mic_tlv), | |
845 | ||
846 | SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1, | |
847 | max98095_mic_tlv), | |
848 | ||
849 | SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", | |
850 | M98095_05F_LVL_MIC1, 5, 2, 0, | |
851 | max98095_mic1pre_get, max98095_mic1pre_set, | |
852 | max98095_micboost_tlv), | |
853 | SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", | |
854 | M98095_060_LVL_MIC2, 5, 2, 0, | |
855 | max98095_mic2pre_get, max98095_mic2pre_set, | |
856 | max98095_micboost_tlv), | |
857 | ||
858 | SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1, | |
859 | max98095_lin_tlv), | |
860 | ||
861 | SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1, | |
862 | max98095_adc_tlv), | |
863 | SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1, | |
864 | max98095_adc_tlv), | |
865 | ||
866 | SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0, | |
867 | max98095_adcboost_tlv), | |
868 | SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0, | |
869 | max98095_adcboost_tlv), | |
870 | ||
dad31ec1 PH |
871 | SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0), |
872 | SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0), | |
873 | ||
874 | SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0), | |
875 | SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0), | |
876 | ||
82a5a936 PH |
877 | SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum), |
878 | SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum), | |
879 | SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum), | |
880 | SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum), | |
881 | SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum), | |
882 | ||
883 | SOC_ENUM("Linein Mode", max98095_linein_mode_enum), | |
884 | SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum), | |
885 | }; | |
886 | ||
887 | /* Left speaker mixer switch */ | |
888 | static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = { | |
889 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0), | |
890 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0), | |
891 | SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), | |
892 | SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), | |
893 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0), | |
894 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0), | |
895 | SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0), | |
896 | SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0), | |
897 | }; | |
898 | ||
899 | /* Right speaker mixer switch */ | |
900 | static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = { | |
901 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0), | |
902 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0), | |
903 | SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), | |
904 | SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), | |
905 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0), | |
906 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0), | |
907 | SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0), | |
908 | SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0), | |
909 | }; | |
910 | ||
911 | /* Left headphone mixer switch */ | |
912 | static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = { | |
913 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0), | |
914 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0), | |
915 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0), | |
916 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0), | |
917 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0), | |
918 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0), | |
919 | }; | |
920 | ||
921 | /* Right headphone mixer switch */ | |
922 | static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = { | |
923 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0), | |
924 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0), | |
925 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0), | |
926 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0), | |
927 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0), | |
928 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0), | |
929 | }; | |
930 | ||
931 | /* Receiver earpiece mixer switch */ | |
932 | static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = { | |
933 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0), | |
934 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0), | |
935 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0), | |
936 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0), | |
937 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0), | |
938 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0), | |
939 | }; | |
940 | ||
941 | /* Left lineout mixer switch */ | |
942 | static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = { | |
943 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0), | |
944 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0), | |
945 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0), | |
946 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0), | |
947 | SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0), | |
948 | SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0), | |
949 | }; | |
950 | ||
951 | /* Right lineout mixer switch */ | |
952 | static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = { | |
953 | SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0), | |
954 | SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0), | |
955 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0), | |
956 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0), | |
957 | SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0), | |
958 | SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0), | |
959 | }; | |
960 | ||
961 | /* Left ADC mixer switch */ | |
962 | static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = { | |
963 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0), | |
964 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0), | |
965 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0), | |
966 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0), | |
967 | }; | |
968 | ||
969 | /* Right ADC mixer switch */ | |
970 | static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = { | |
971 | SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0), | |
972 | SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0), | |
973 | SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0), | |
974 | SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0), | |
975 | }; | |
976 | ||
977 | static int max98095_mic_event(struct snd_soc_dapm_widget *w, | |
978 | struct snd_kcontrol *kcontrol, int event) | |
979 | { | |
980 | struct snd_soc_codec *codec = w->codec; | |
981 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
982 | ||
983 | switch (event) { | |
984 | case SND_SOC_DAPM_POST_PMU: | |
985 | if (w->reg == M98095_05F_LVL_MIC1) { | |
986 | snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, | |
987 | (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT); | |
988 | } else { | |
989 | snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, | |
990 | (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT); | |
991 | } | |
992 | break; | |
993 | case SND_SOC_DAPM_POST_PMD: | |
994 | snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0); | |
995 | break; | |
996 | default: | |
997 | return -EINVAL; | |
998 | } | |
999 | ||
1000 | return 0; | |
1001 | } | |
1002 | ||
1003 | /* | |
1004 | * The line inputs are stereo inputs with the left and right | |
1005 | * channels sharing a common PGA power control signal. | |
1006 | */ | |
1007 | static int max98095_line_pga(struct snd_soc_dapm_widget *w, | |
1008 | int event, u8 channel) | |
1009 | { | |
1010 | struct snd_soc_codec *codec = w->codec; | |
1011 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1012 | u8 *state; | |
1013 | ||
1014 | BUG_ON(!((channel == 1) || (channel == 2))); | |
1015 | ||
1016 | state = &max98095->lin_state; | |
1017 | ||
1018 | switch (event) { | |
1019 | case SND_SOC_DAPM_POST_PMU: | |
1020 | *state |= channel; | |
1021 | snd_soc_update_bits(codec, w->reg, | |
1022 | (1 << w->shift), (1 << w->shift)); | |
1023 | break; | |
1024 | case SND_SOC_DAPM_POST_PMD: | |
1025 | *state &= ~channel; | |
1026 | if (*state == 0) { | |
1027 | snd_soc_update_bits(codec, w->reg, | |
1028 | (1 << w->shift), 0); | |
1029 | } | |
1030 | break; | |
1031 | default: | |
1032 | return -EINVAL; | |
1033 | } | |
1034 | ||
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w, | |
1039 | struct snd_kcontrol *k, int event) | |
1040 | { | |
1041 | return max98095_line_pga(w, event, 1); | |
1042 | } | |
1043 | ||
1044 | static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w, | |
1045 | struct snd_kcontrol *k, int event) | |
1046 | { | |
1047 | return max98095_line_pga(w, event, 2); | |
1048 | } | |
1049 | ||
1050 | /* | |
1051 | * The stereo line out mixer outputs to two stereo line outs. | |
1052 | * The 2nd pair has a separate set of enables. | |
1053 | */ | |
1054 | static int max98095_lineout_event(struct snd_soc_dapm_widget *w, | |
1055 | struct snd_kcontrol *kcontrol, int event) | |
1056 | { | |
1057 | struct snd_soc_codec *codec = w->codec; | |
1058 | ||
1059 | switch (event) { | |
1060 | case SND_SOC_DAPM_POST_PMU: | |
1061 | snd_soc_update_bits(codec, w->reg, | |
1062 | (1 << (w->shift+2)), (1 << (w->shift+2))); | |
1063 | break; | |
1064 | case SND_SOC_DAPM_POST_PMD: | |
1065 | snd_soc_update_bits(codec, w->reg, | |
1066 | (1 << (w->shift+2)), 0); | |
1067 | break; | |
1068 | default: | |
1069 | return -EINVAL; | |
1070 | } | |
1071 | ||
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = { | |
1076 | ||
1077 | SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0), | |
1078 | SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0), | |
1079 | ||
1080 | SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", | |
1081 | M98095_091_PWR_EN_OUT, 0, 0), | |
1082 | SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", | |
1083 | M98095_091_PWR_EN_OUT, 1, 0), | |
1084 | SND_SOC_DAPM_DAC("DACM2", "Aux Playback", | |
1085 | M98095_091_PWR_EN_OUT, 2, 0), | |
1086 | SND_SOC_DAPM_DAC("DACM3", "Voice Playback", | |
1087 | M98095_091_PWR_EN_OUT, 2, 0), | |
1088 | ||
1089 | SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT, | |
1090 | 6, 0, NULL, 0), | |
1091 | SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT, | |
1092 | 7, 0, NULL, 0), | |
1093 | ||
1094 | SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT, | |
1095 | 4, 0, NULL, 0), | |
1096 | SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT, | |
1097 | 5, 0, NULL, 0), | |
1098 | ||
1099 | SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT, | |
1100 | 3, 0, NULL, 0), | |
1101 | ||
1102 | SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT, | |
1103 | 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), | |
1104 | SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT, | |
1105 | 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), | |
1106 | ||
1107 | SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, | |
1108 | &max98095_extmic_mux), | |
1109 | ||
1110 | SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0, | |
1111 | &max98095_linein_mux), | |
1112 | ||
1113 | SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, | |
1114 | &max98095_left_hp_mixer_controls[0], | |
1115 | ARRAY_SIZE(max98095_left_hp_mixer_controls)), | |
1116 | ||
1117 | SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, | |
1118 | &max98095_right_hp_mixer_controls[0], | |
1119 | ARRAY_SIZE(max98095_right_hp_mixer_controls)), | |
1120 | ||
1121 | SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, | |
1122 | &max98095_left_speaker_mixer_controls[0], | |
1123 | ARRAY_SIZE(max98095_left_speaker_mixer_controls)), | |
1124 | ||
1125 | SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, | |
1126 | &max98095_right_speaker_mixer_controls[0], | |
1127 | ARRAY_SIZE(max98095_right_speaker_mixer_controls)), | |
1128 | ||
1129 | SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0, | |
1130 | &max98095_mono_rcv_mixer_controls[0], | |
1131 | ARRAY_SIZE(max98095_mono_rcv_mixer_controls)), | |
1132 | ||
1133 | SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0, | |
1134 | &max98095_left_lineout_mixer_controls[0], | |
1135 | ARRAY_SIZE(max98095_left_lineout_mixer_controls)), | |
1136 | ||
1137 | SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0, | |
1138 | &max98095_right_lineout_mixer_controls[0], | |
1139 | ARRAY_SIZE(max98095_right_lineout_mixer_controls)), | |
1140 | ||
1141 | SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, | |
1142 | &max98095_left_ADC_mixer_controls[0], | |
1143 | ARRAY_SIZE(max98095_left_ADC_mixer_controls)), | |
1144 | ||
1145 | SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, | |
1146 | &max98095_right_ADC_mixer_controls[0], | |
1147 | ARRAY_SIZE(max98095_right_ADC_mixer_controls)), | |
1148 | ||
1149 | SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1, | |
1150 | 5, 0, NULL, 0, max98095_mic_event, | |
1151 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1152 | ||
1153 | SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2, | |
1154 | 5, 0, NULL, 0, max98095_mic_event, | |
1155 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1156 | ||
1157 | SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN, | |
1158 | 7, 0, NULL, 0, max98095_pga_in1_event, | |
1159 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1160 | ||
1161 | SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN, | |
1162 | 7, 0, NULL, 0, max98095_pga_in2_event, | |
1163 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1164 | ||
1165 | SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0), | |
1166 | SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0), | |
1167 | ||
1168 | SND_SOC_DAPM_OUTPUT("HPL"), | |
1169 | SND_SOC_DAPM_OUTPUT("HPR"), | |
1170 | SND_SOC_DAPM_OUTPUT("SPKL"), | |
1171 | SND_SOC_DAPM_OUTPUT("SPKR"), | |
1172 | SND_SOC_DAPM_OUTPUT("RCV"), | |
1173 | SND_SOC_DAPM_OUTPUT("OUT1"), | |
1174 | SND_SOC_DAPM_OUTPUT("OUT2"), | |
1175 | SND_SOC_DAPM_OUTPUT("OUT3"), | |
1176 | SND_SOC_DAPM_OUTPUT("OUT4"), | |
1177 | ||
1178 | SND_SOC_DAPM_INPUT("MIC1"), | |
1179 | SND_SOC_DAPM_INPUT("MIC2"), | |
1180 | SND_SOC_DAPM_INPUT("INA1"), | |
1181 | SND_SOC_DAPM_INPUT("INA2"), | |
1182 | SND_SOC_DAPM_INPUT("INB1"), | |
1183 | SND_SOC_DAPM_INPUT("INB2"), | |
1184 | }; | |
1185 | ||
1186 | static const struct snd_soc_dapm_route max98095_audio_map[] = { | |
1187 | /* Left headphone output mixer */ | |
1188 | {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"}, | |
1189 | {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"}, | |
1190 | {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1191 | {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1192 | {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"}, | |
1193 | {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"}, | |
1194 | ||
1195 | /* Right headphone output mixer */ | |
1196 | {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"}, | |
1197 | {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"}, | |
1198 | {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1199 | {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1200 | {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"}, | |
1201 | {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"}, | |
1202 | ||
1203 | /* Left speaker output mixer */ | |
1204 | {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"}, | |
1205 | {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"}, | |
1206 | {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, | |
1207 | {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, | |
1208 | {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1209 | {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1210 | {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"}, | |
1211 | {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"}, | |
1212 | ||
1213 | /* Right speaker output mixer */ | |
1214 | {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"}, | |
1215 | {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"}, | |
1216 | {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, | |
1217 | {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, | |
1218 | {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1219 | {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1220 | {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"}, | |
1221 | {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"}, | |
1222 | ||
1223 | /* Earpiece/Receiver output mixer */ | |
1224 | {"Receiver Mixer", "Left DAC1 Switch", "DACL1"}, | |
1225 | {"Receiver Mixer", "Right DAC1 Switch", "DACR1"}, | |
1226 | {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1227 | {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1228 | {"Receiver Mixer", "IN1 Switch", "IN1 Input"}, | |
1229 | {"Receiver Mixer", "IN2 Switch", "IN2 Input"}, | |
1230 | ||
1231 | /* Left Lineout output mixer */ | |
1232 | {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"}, | |
1233 | {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"}, | |
1234 | {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1235 | {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1236 | {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"}, | |
1237 | {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"}, | |
1238 | ||
1239 | /* Right lineout output mixer */ | |
1240 | {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"}, | |
1241 | {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"}, | |
1242 | {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1243 | {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1244 | {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"}, | |
1245 | {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"}, | |
1246 | ||
1247 | {"HP Left Out", NULL, "Left Headphone Mixer"}, | |
1248 | {"HP Right Out", NULL, "Right Headphone Mixer"}, | |
1249 | {"SPK Left Out", NULL, "Left Speaker Mixer"}, | |
1250 | {"SPK Right Out", NULL, "Right Speaker Mixer"}, | |
1251 | {"RCV Mono Out", NULL, "Receiver Mixer"}, | |
1252 | {"LINE Left Out", NULL, "Left Lineout Mixer"}, | |
1253 | {"LINE Right Out", NULL, "Right Lineout Mixer"}, | |
1254 | ||
1255 | {"HPL", NULL, "HP Left Out"}, | |
1256 | {"HPR", NULL, "HP Right Out"}, | |
1257 | {"SPKL", NULL, "SPK Left Out"}, | |
1258 | {"SPKR", NULL, "SPK Right Out"}, | |
1259 | {"RCV", NULL, "RCV Mono Out"}, | |
1260 | {"OUT1", NULL, "LINE Left Out"}, | |
1261 | {"OUT2", NULL, "LINE Right Out"}, | |
1262 | {"OUT3", NULL, "LINE Left Out"}, | |
1263 | {"OUT4", NULL, "LINE Right Out"}, | |
1264 | ||
1265 | /* Left ADC input mixer */ | |
1266 | {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1267 | {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1268 | {"Left ADC Mixer", "IN1 Switch", "IN1 Input"}, | |
1269 | {"Left ADC Mixer", "IN2 Switch", "IN2 Input"}, | |
1270 | ||
1271 | /* Right ADC input mixer */ | |
1272 | {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1273 | {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1274 | {"Right ADC Mixer", "IN1 Switch", "IN1 Input"}, | |
1275 | {"Right ADC Mixer", "IN2 Switch", "IN2 Input"}, | |
1276 | ||
1277 | /* Inputs */ | |
1278 | {"ADCL", NULL, "Left ADC Mixer"}, | |
1279 | {"ADCR", NULL, "Right ADC Mixer"}, | |
1280 | ||
1281 | {"IN1 Input", NULL, "INA1"}, | |
1282 | {"IN2 Input", NULL, "INA2"}, | |
1283 | ||
1284 | {"MIC1 Input", NULL, "MIC1"}, | |
1285 | {"MIC2 Input", NULL, "MIC2"}, | |
1286 | }; | |
1287 | ||
1288 | static int max98095_add_widgets(struct snd_soc_codec *codec) | |
1289 | { | |
022658be | 1290 | snd_soc_add_codec_controls(codec, max98095_snd_controls, |
82a5a936 PH |
1291 | ARRAY_SIZE(max98095_snd_controls)); |
1292 | ||
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | /* codec mclk clock divider coefficients */ | |
1297 | static const struct { | |
1298 | u32 rate; | |
1299 | u8 sr; | |
1300 | } rate_table[] = { | |
1301 | {8000, 0x01}, | |
1302 | {11025, 0x02}, | |
1303 | {16000, 0x03}, | |
1304 | {22050, 0x04}, | |
1305 | {24000, 0x05}, | |
1306 | {32000, 0x06}, | |
1307 | {44100, 0x07}, | |
1308 | {48000, 0x08}, | |
1309 | {88200, 0x09}, | |
1310 | {96000, 0x0A}, | |
1311 | }; | |
1312 | ||
1313 | static int rate_value(int rate, u8 *value) | |
1314 | { | |
1315 | int i; | |
1316 | ||
1317 | for (i = 0; i < ARRAY_SIZE(rate_table); i++) { | |
1318 | if (rate_table[i].rate >= rate) { | |
1319 | *value = rate_table[i].sr; | |
1320 | return 0; | |
1321 | } | |
1322 | } | |
1323 | *value = rate_table[0].sr; | |
1324 | return -EINVAL; | |
1325 | } | |
1326 | ||
1327 | static int max98095_dai1_hw_params(struct snd_pcm_substream *substream, | |
1328 | struct snd_pcm_hw_params *params, | |
1329 | struct snd_soc_dai *dai) | |
1330 | { | |
1331 | struct snd_soc_codec *codec = dai->codec; | |
1332 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1333 | struct max98095_cdata *cdata; | |
1334 | unsigned long long ni; | |
1335 | unsigned int rate; | |
1336 | u8 regval; | |
1337 | ||
1338 | cdata = &max98095->dai[0]; | |
1339 | ||
1340 | rate = params_rate(params); | |
1341 | ||
1342 | switch (params_format(params)) { | |
1343 | case SNDRV_PCM_FORMAT_S16_LE: | |
1344 | snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, | |
1345 | M98095_DAI_WS, 0); | |
1346 | break; | |
1347 | case SNDRV_PCM_FORMAT_S24_LE: | |
1348 | snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, | |
1349 | M98095_DAI_WS, M98095_DAI_WS); | |
1350 | break; | |
1351 | default: | |
1352 | return -EINVAL; | |
1353 | } | |
1354 | ||
1355 | if (rate_value(rate, ®val)) | |
1356 | return -EINVAL; | |
1357 | ||
1358 | snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE, | |
1359 | M98095_CLKMODE_MASK, regval); | |
1360 | cdata->rate = rate; | |
1361 | ||
1362 | /* Configure NI when operating as master */ | |
1363 | if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) { | |
1364 | if (max98095->sysclk == 0) { | |
1365 | dev_err(codec->dev, "Invalid system clock frequency\n"); | |
1366 | return -EINVAL; | |
1367 | } | |
1368 | ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) | |
1369 | * (unsigned long long int)rate; | |
1370 | do_div(ni, (unsigned long long int)max98095->sysclk); | |
1371 | snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, | |
1372 | (ni >> 8) & 0x7F); | |
1373 | snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, | |
1374 | ni & 0xFF); | |
1375 | } | |
1376 | ||
1377 | /* Update sample rate mode */ | |
1378 | if (rate < 50000) | |
1379 | snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, | |
1380 | M98095_DAI_DHF, 0); | |
1381 | else | |
1382 | snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, | |
1383 | M98095_DAI_DHF, M98095_DAI_DHF); | |
1384 | ||
1385 | return 0; | |
1386 | } | |
1387 | ||
1388 | static int max98095_dai2_hw_params(struct snd_pcm_substream *substream, | |
1389 | struct snd_pcm_hw_params *params, | |
1390 | struct snd_soc_dai *dai) | |
1391 | { | |
1392 | struct snd_soc_codec *codec = dai->codec; | |
1393 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1394 | struct max98095_cdata *cdata; | |
1395 | unsigned long long ni; | |
1396 | unsigned int rate; | |
1397 | u8 regval; | |
1398 | ||
1399 | cdata = &max98095->dai[1]; | |
1400 | ||
1401 | rate = params_rate(params); | |
1402 | ||
1403 | switch (params_format(params)) { | |
1404 | case SNDRV_PCM_FORMAT_S16_LE: | |
1405 | snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, | |
1406 | M98095_DAI_WS, 0); | |
1407 | break; | |
1408 | case SNDRV_PCM_FORMAT_S24_LE: | |
1409 | snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, | |
1410 | M98095_DAI_WS, M98095_DAI_WS); | |
1411 | break; | |
1412 | default: | |
1413 | return -EINVAL; | |
1414 | } | |
1415 | ||
1416 | if (rate_value(rate, ®val)) | |
1417 | return -EINVAL; | |
1418 | ||
1419 | snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE, | |
1420 | M98095_CLKMODE_MASK, regval); | |
1421 | cdata->rate = rate; | |
1422 | ||
1423 | /* Configure NI when operating as master */ | |
1424 | if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) { | |
1425 | if (max98095->sysclk == 0) { | |
1426 | dev_err(codec->dev, "Invalid system clock frequency\n"); | |
1427 | return -EINVAL; | |
1428 | } | |
1429 | ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) | |
1430 | * (unsigned long long int)rate; | |
1431 | do_div(ni, (unsigned long long int)max98095->sysclk); | |
1432 | snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, | |
1433 | (ni >> 8) & 0x7F); | |
1434 | snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, | |
1435 | ni & 0xFF); | |
1436 | } | |
1437 | ||
1438 | /* Update sample rate mode */ | |
1439 | if (rate < 50000) | |
1440 | snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, | |
1441 | M98095_DAI_DHF, 0); | |
1442 | else | |
1443 | snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, | |
1444 | M98095_DAI_DHF, M98095_DAI_DHF); | |
1445 | ||
1446 | return 0; | |
1447 | } | |
1448 | ||
1449 | static int max98095_dai3_hw_params(struct snd_pcm_substream *substream, | |
1450 | struct snd_pcm_hw_params *params, | |
1451 | struct snd_soc_dai *dai) | |
1452 | { | |
1453 | struct snd_soc_codec *codec = dai->codec; | |
1454 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1455 | struct max98095_cdata *cdata; | |
1456 | unsigned long long ni; | |
1457 | unsigned int rate; | |
1458 | u8 regval; | |
1459 | ||
1460 | cdata = &max98095->dai[2]; | |
1461 | ||
1462 | rate = params_rate(params); | |
1463 | ||
1464 | switch (params_format(params)) { | |
1465 | case SNDRV_PCM_FORMAT_S16_LE: | |
1466 | snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, | |
1467 | M98095_DAI_WS, 0); | |
1468 | break; | |
1469 | case SNDRV_PCM_FORMAT_S24_LE: | |
1470 | snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, | |
1471 | M98095_DAI_WS, M98095_DAI_WS); | |
1472 | break; | |
1473 | default: | |
1474 | return -EINVAL; | |
1475 | } | |
1476 | ||
1477 | if (rate_value(rate, ®val)) | |
1478 | return -EINVAL; | |
1479 | ||
1480 | snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE, | |
1481 | M98095_CLKMODE_MASK, regval); | |
1482 | cdata->rate = rate; | |
1483 | ||
1484 | /* Configure NI when operating as master */ | |
1485 | if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) { | |
1486 | if (max98095->sysclk == 0) { | |
1487 | dev_err(codec->dev, "Invalid system clock frequency\n"); | |
1488 | return -EINVAL; | |
1489 | } | |
1490 | ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) | |
1491 | * (unsigned long long int)rate; | |
1492 | do_div(ni, (unsigned long long int)max98095->sysclk); | |
1493 | snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, | |
1494 | (ni >> 8) & 0x7F); | |
1495 | snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, | |
1496 | ni & 0xFF); | |
1497 | } | |
1498 | ||
1499 | /* Update sample rate mode */ | |
1500 | if (rate < 50000) | |
1501 | snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, | |
1502 | M98095_DAI_DHF, 0); | |
1503 | else | |
1504 | snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, | |
1505 | M98095_DAI_DHF, M98095_DAI_DHF); | |
1506 | ||
1507 | return 0; | |
1508 | } | |
1509 | ||
1510 | static int max98095_dai_set_sysclk(struct snd_soc_dai *dai, | |
1511 | int clk_id, unsigned int freq, int dir) | |
1512 | { | |
1513 | struct snd_soc_codec *codec = dai->codec; | |
1514 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1515 | ||
1516 | /* Requested clock frequency is already setup */ | |
1517 | if (freq == max98095->sysclk) | |
1518 | return 0; | |
1519 | ||
82a5a936 PH |
1520 | /* Setup clocks for slave mode, and using the PLL |
1521 | * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) | |
1522 | * 0x02 (when master clk is 20MHz to 40MHz).. | |
1523 | * 0x03 (when master clk is 40MHz to 60MHz).. | |
1524 | */ | |
1525 | if ((freq >= 10000000) && (freq < 20000000)) { | |
1526 | snd_soc_write(codec, M98095_026_SYS_CLK, 0x10); | |
1527 | } else if ((freq >= 20000000) && (freq < 40000000)) { | |
1528 | snd_soc_write(codec, M98095_026_SYS_CLK, 0x20); | |
1529 | } else if ((freq >= 40000000) && (freq < 60000000)) { | |
1530 | snd_soc_write(codec, M98095_026_SYS_CLK, 0x30); | |
1531 | } else { | |
1532 | dev_err(codec->dev, "Invalid master clock frequency\n"); | |
1533 | return -EINVAL; | |
1534 | } | |
1535 | ||
1536 | dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); | |
1537 | ||
1538 | max98095->sysclk = freq; | |
1539 | return 0; | |
1540 | } | |
1541 | ||
1542 | static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai, | |
1543 | unsigned int fmt) | |
1544 | { | |
1545 | struct snd_soc_codec *codec = codec_dai->codec; | |
1546 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1547 | struct max98095_cdata *cdata; | |
1548 | u8 regval = 0; | |
1549 | ||
1550 | cdata = &max98095->dai[0]; | |
1551 | ||
1552 | if (fmt != cdata->fmt) { | |
1553 | cdata->fmt = fmt; | |
1554 | ||
1555 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1556 | case SND_SOC_DAIFMT_CBS_CFS: | |
1557 | /* Slave mode PLL */ | |
1558 | snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, | |
1559 | 0x80); | |
1560 | snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, | |
1561 | 0x00); | |
1562 | break; | |
1563 | case SND_SOC_DAIFMT_CBM_CFM: | |
1564 | /* Set to master mode */ | |
1565 | regval |= M98095_DAI_MAS; | |
1566 | break; | |
1567 | case SND_SOC_DAIFMT_CBS_CFM: | |
1568 | case SND_SOC_DAIFMT_CBM_CFS: | |
1569 | default: | |
1570 | dev_err(codec->dev, "Clock mode unsupported"); | |
1571 | return -EINVAL; | |
1572 | } | |
1573 | ||
1574 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1575 | case SND_SOC_DAIFMT_I2S: | |
1576 | regval |= M98095_DAI_DLY; | |
1577 | break; | |
1578 | case SND_SOC_DAIFMT_LEFT_J: | |
1579 | break; | |
1580 | default: | |
1581 | return -EINVAL; | |
1582 | } | |
1583 | ||
1584 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1585 | case SND_SOC_DAIFMT_NB_NF: | |
1586 | break; | |
1587 | case SND_SOC_DAIFMT_NB_IF: | |
1588 | regval |= M98095_DAI_WCI; | |
1589 | break; | |
1590 | case SND_SOC_DAIFMT_IB_NF: | |
1591 | regval |= M98095_DAI_BCI; | |
1592 | break; | |
1593 | case SND_SOC_DAIFMT_IB_IF: | |
1594 | regval |= M98095_DAI_BCI|M98095_DAI_WCI; | |
1595 | break; | |
1596 | default: | |
1597 | return -EINVAL; | |
1598 | } | |
1599 | ||
1600 | snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, | |
1601 | M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | | |
1602 | M98095_DAI_WCI, regval); | |
1603 | ||
1604 | snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64); | |
1605 | } | |
1606 | ||
1607 | return 0; | |
1608 | } | |
1609 | ||
1610 | static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai, | |
1611 | unsigned int fmt) | |
1612 | { | |
1613 | struct snd_soc_codec *codec = codec_dai->codec; | |
1614 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1615 | struct max98095_cdata *cdata; | |
1616 | u8 regval = 0; | |
1617 | ||
1618 | cdata = &max98095->dai[1]; | |
1619 | ||
1620 | if (fmt != cdata->fmt) { | |
1621 | cdata->fmt = fmt; | |
1622 | ||
1623 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1624 | case SND_SOC_DAIFMT_CBS_CFS: | |
1625 | /* Slave mode PLL */ | |
1626 | snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, | |
1627 | 0x80); | |
1628 | snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, | |
1629 | 0x00); | |
1630 | break; | |
1631 | case SND_SOC_DAIFMT_CBM_CFM: | |
1632 | /* Set to master mode */ | |
1633 | regval |= M98095_DAI_MAS; | |
1634 | break; | |
1635 | case SND_SOC_DAIFMT_CBS_CFM: | |
1636 | case SND_SOC_DAIFMT_CBM_CFS: | |
1637 | default: | |
1638 | dev_err(codec->dev, "Clock mode unsupported"); | |
1639 | return -EINVAL; | |
1640 | } | |
1641 | ||
1642 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1643 | case SND_SOC_DAIFMT_I2S: | |
1644 | regval |= M98095_DAI_DLY; | |
1645 | break; | |
1646 | case SND_SOC_DAIFMT_LEFT_J: | |
1647 | break; | |
1648 | default: | |
1649 | return -EINVAL; | |
1650 | } | |
1651 | ||
1652 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1653 | case SND_SOC_DAIFMT_NB_NF: | |
1654 | break; | |
1655 | case SND_SOC_DAIFMT_NB_IF: | |
1656 | regval |= M98095_DAI_WCI; | |
1657 | break; | |
1658 | case SND_SOC_DAIFMT_IB_NF: | |
1659 | regval |= M98095_DAI_BCI; | |
1660 | break; | |
1661 | case SND_SOC_DAIFMT_IB_IF: | |
1662 | regval |= M98095_DAI_BCI|M98095_DAI_WCI; | |
1663 | break; | |
1664 | default: | |
1665 | return -EINVAL; | |
1666 | } | |
1667 | ||
1668 | snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, | |
1669 | M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | | |
1670 | M98095_DAI_WCI, regval); | |
1671 | ||
1672 | snd_soc_write(codec, M98095_035_DAI2_CLOCK, | |
1673 | M98095_DAI_BSEL64); | |
1674 | } | |
1675 | ||
1676 | return 0; | |
1677 | } | |
1678 | ||
1679 | static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai, | |
1680 | unsigned int fmt) | |
1681 | { | |
1682 | struct snd_soc_codec *codec = codec_dai->codec; | |
1683 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1684 | struct max98095_cdata *cdata; | |
1685 | u8 regval = 0; | |
1686 | ||
1687 | cdata = &max98095->dai[2]; | |
1688 | ||
1689 | if (fmt != cdata->fmt) { | |
1690 | cdata->fmt = fmt; | |
1691 | ||
1692 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1693 | case SND_SOC_DAIFMT_CBS_CFS: | |
1694 | /* Slave mode PLL */ | |
1695 | snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, | |
1696 | 0x80); | |
1697 | snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, | |
1698 | 0x00); | |
1699 | break; | |
1700 | case SND_SOC_DAIFMT_CBM_CFM: | |
1701 | /* Set to master mode */ | |
1702 | regval |= M98095_DAI_MAS; | |
1703 | break; | |
1704 | case SND_SOC_DAIFMT_CBS_CFM: | |
1705 | case SND_SOC_DAIFMT_CBM_CFS: | |
1706 | default: | |
1707 | dev_err(codec->dev, "Clock mode unsupported"); | |
1708 | return -EINVAL; | |
1709 | } | |
1710 | ||
1711 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1712 | case SND_SOC_DAIFMT_I2S: | |
1713 | regval |= M98095_DAI_DLY; | |
1714 | break; | |
1715 | case SND_SOC_DAIFMT_LEFT_J: | |
1716 | break; | |
1717 | default: | |
1718 | return -EINVAL; | |
1719 | } | |
1720 | ||
1721 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1722 | case SND_SOC_DAIFMT_NB_NF: | |
1723 | break; | |
1724 | case SND_SOC_DAIFMT_NB_IF: | |
1725 | regval |= M98095_DAI_WCI; | |
1726 | break; | |
1727 | case SND_SOC_DAIFMT_IB_NF: | |
1728 | regval |= M98095_DAI_BCI; | |
1729 | break; | |
1730 | case SND_SOC_DAIFMT_IB_IF: | |
1731 | regval |= M98095_DAI_BCI|M98095_DAI_WCI; | |
1732 | break; | |
1733 | default: | |
1734 | return -EINVAL; | |
1735 | } | |
1736 | ||
1737 | snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, | |
1738 | M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | | |
1739 | M98095_DAI_WCI, regval); | |
1740 | ||
1741 | snd_soc_write(codec, M98095_03F_DAI3_CLOCK, | |
1742 | M98095_DAI_BSEL64); | |
1743 | } | |
1744 | ||
1745 | return 0; | |
1746 | } | |
1747 | ||
1748 | static int max98095_set_bias_level(struct snd_soc_codec *codec, | |
1749 | enum snd_soc_bias_level level) | |
1750 | { | |
1751 | int ret; | |
1752 | ||
1753 | switch (level) { | |
1754 | case SND_SOC_BIAS_ON: | |
1755 | break; | |
1756 | ||
1757 | case SND_SOC_BIAS_PREPARE: | |
1758 | break; | |
1759 | ||
1760 | case SND_SOC_BIAS_STANDBY: | |
1761 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { | |
1762 | ret = snd_soc_cache_sync(codec); | |
1763 | ||
1764 | if (ret != 0) { | |
1765 | dev_err(codec->dev, "Failed to sync cache: %d\n", ret); | |
1766 | return ret; | |
1767 | } | |
1768 | } | |
1769 | ||
1770 | snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, | |
1771 | M98095_MBEN, M98095_MBEN); | |
1772 | break; | |
1773 | ||
1774 | case SND_SOC_BIAS_OFF: | |
1775 | snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, | |
1776 | M98095_MBEN, 0); | |
1777 | codec->cache_sync = 1; | |
1778 | break; | |
1779 | } | |
1780 | codec->dapm.bias_level = level; | |
1781 | return 0; | |
1782 | } | |
1783 | ||
1784 | #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000 | |
1785 | #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) | |
1786 | ||
85e7652d | 1787 | static const struct snd_soc_dai_ops max98095_dai1_ops = { |
82a5a936 PH |
1788 | .set_sysclk = max98095_dai_set_sysclk, |
1789 | .set_fmt = max98095_dai1_set_fmt, | |
1790 | .hw_params = max98095_dai1_hw_params, | |
1791 | }; | |
1792 | ||
85e7652d | 1793 | static const struct snd_soc_dai_ops max98095_dai2_ops = { |
82a5a936 PH |
1794 | .set_sysclk = max98095_dai_set_sysclk, |
1795 | .set_fmt = max98095_dai2_set_fmt, | |
1796 | .hw_params = max98095_dai2_hw_params, | |
1797 | }; | |
1798 | ||
85e7652d | 1799 | static const struct snd_soc_dai_ops max98095_dai3_ops = { |
82a5a936 PH |
1800 | .set_sysclk = max98095_dai_set_sysclk, |
1801 | .set_fmt = max98095_dai3_set_fmt, | |
1802 | .hw_params = max98095_dai3_hw_params, | |
1803 | }; | |
1804 | ||
1805 | static struct snd_soc_dai_driver max98095_dai[] = { | |
1806 | { | |
1807 | .name = "HiFi", | |
1808 | .playback = { | |
1809 | .stream_name = "HiFi Playback", | |
1810 | .channels_min = 1, | |
1811 | .channels_max = 2, | |
1812 | .rates = MAX98095_RATES, | |
1813 | .formats = MAX98095_FORMATS, | |
1814 | }, | |
1815 | .capture = { | |
1816 | .stream_name = "HiFi Capture", | |
1817 | .channels_min = 1, | |
1818 | .channels_max = 2, | |
1819 | .rates = MAX98095_RATES, | |
1820 | .formats = MAX98095_FORMATS, | |
1821 | }, | |
1822 | .ops = &max98095_dai1_ops, | |
1823 | }, | |
1824 | { | |
1825 | .name = "Aux", | |
1826 | .playback = { | |
1827 | .stream_name = "Aux Playback", | |
1828 | .channels_min = 1, | |
1829 | .channels_max = 1, | |
1830 | .rates = MAX98095_RATES, | |
1831 | .formats = MAX98095_FORMATS, | |
1832 | }, | |
1833 | .ops = &max98095_dai2_ops, | |
1834 | }, | |
1835 | { | |
1836 | .name = "Voice", | |
1837 | .playback = { | |
1838 | .stream_name = "Voice Playback", | |
1839 | .channels_min = 1, | |
1840 | .channels_max = 1, | |
1841 | .rates = MAX98095_RATES, | |
1842 | .formats = MAX98095_FORMATS, | |
1843 | }, | |
1844 | .ops = &max98095_dai3_ops, | |
1845 | } | |
1846 | ||
1847 | }; | |
1848 | ||
dad31ec1 PH |
1849 | static int max98095_get_eq_channel(const char *name) |
1850 | { | |
1851 | if (strcmp(name, "EQ1 Mode") == 0) | |
1852 | return 0; | |
1853 | if (strcmp(name, "EQ2 Mode") == 0) | |
1854 | return 1; | |
1855 | return -EINVAL; | |
1856 | } | |
1857 | ||
1858 | static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol, | |
1859 | struct snd_ctl_elem_value *ucontrol) | |
1860 | { | |
1861 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
1862 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1863 | struct max98095_pdata *pdata = max98095->pdata; | |
1864 | int channel = max98095_get_eq_channel(kcontrol->id.name); | |
1865 | struct max98095_cdata *cdata; | |
f8d7b13e | 1866 | unsigned int sel = ucontrol->value.integer.value[0]; |
dad31ec1 PH |
1867 | struct max98095_eq_cfg *coef_set; |
1868 | int fs, best, best_val, i; | |
1869 | int regmask, regsave; | |
1870 | ||
1871 | BUG_ON(channel > 1); | |
1872 | ||
53949425 TH |
1873 | if (!pdata || !max98095->eq_textcnt) |
1874 | return 0; | |
dad31ec1 PH |
1875 | |
1876 | if (sel >= pdata->eq_cfgcnt) | |
1877 | return -EINVAL; | |
1878 | ||
53949425 | 1879 | cdata = &max98095->dai[channel]; |
dad31ec1 | 1880 | cdata->eq_sel = sel; |
dad31ec1 PH |
1881 | fs = cdata->rate; |
1882 | ||
1883 | /* Find the selected configuration with nearest sample rate */ | |
1884 | best = 0; | |
1885 | best_val = INT_MAX; | |
1886 | for (i = 0; i < pdata->eq_cfgcnt; i++) { | |
1887 | if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 && | |
1888 | abs(pdata->eq_cfg[i].rate - fs) < best_val) { | |
1889 | best = i; | |
1890 | best_val = abs(pdata->eq_cfg[i].rate - fs); | |
1891 | } | |
1892 | } | |
1893 | ||
1894 | dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", | |
1895 | pdata->eq_cfg[best].name, | |
1896 | pdata->eq_cfg[best].rate, fs); | |
1897 | ||
1898 | coef_set = &pdata->eq_cfg[best]; | |
1899 | ||
1900 | regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN; | |
1901 | ||
1902 | /* Disable filter while configuring, and save current on/off state */ | |
1903 | regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); | |
1904 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); | |
1905 | ||
1906 | mutex_lock(&codec->mutex); | |
1907 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); | |
1908 | m98095_eq_band(codec, channel, 0, coef_set->band1); | |
1909 | m98095_eq_band(codec, channel, 1, coef_set->band2); | |
1910 | m98095_eq_band(codec, channel, 2, coef_set->band3); | |
1911 | m98095_eq_band(codec, channel, 3, coef_set->band4); | |
1912 | m98095_eq_band(codec, channel, 4, coef_set->band5); | |
1913 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); | |
1914 | mutex_unlock(&codec->mutex); | |
1915 | ||
1916 | /* Restore the original on/off state */ | |
1917 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); | |
1918 | return 0; | |
1919 | } | |
1920 | ||
1921 | static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol, | |
1922 | struct snd_ctl_elem_value *ucontrol) | |
1923 | { | |
1924 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
1925 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1926 | int channel = max98095_get_eq_channel(kcontrol->id.name); | |
1927 | struct max98095_cdata *cdata; | |
1928 | ||
1929 | cdata = &max98095->dai[channel]; | |
1930 | ucontrol->value.enumerated.item[0] = cdata->eq_sel; | |
1931 | ||
1932 | return 0; | |
1933 | } | |
1934 | ||
1935 | static void max98095_handle_eq_pdata(struct snd_soc_codec *codec) | |
1936 | { | |
1937 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
1938 | struct max98095_pdata *pdata = max98095->pdata; | |
1939 | struct max98095_eq_cfg *cfg; | |
1940 | unsigned int cfgcnt; | |
1941 | int i, j; | |
1942 | const char **t; | |
1943 | int ret; | |
1944 | ||
1945 | struct snd_kcontrol_new controls[] = { | |
1946 | SOC_ENUM_EXT("EQ1 Mode", | |
1947 | max98095->eq_enum, | |
1948 | max98095_get_eq_enum, | |
1949 | max98095_put_eq_enum), | |
1950 | SOC_ENUM_EXT("EQ2 Mode", | |
1951 | max98095->eq_enum, | |
1952 | max98095_get_eq_enum, | |
1953 | max98095_put_eq_enum), | |
1954 | }; | |
1955 | ||
1956 | cfg = pdata->eq_cfg; | |
1957 | cfgcnt = pdata->eq_cfgcnt; | |
1958 | ||
1959 | /* Setup an array of texts for the equalizer enum. | |
1960 | * This is based on Mark Brown's equalizer driver code. | |
1961 | */ | |
1962 | max98095->eq_textcnt = 0; | |
1963 | max98095->eq_texts = NULL; | |
1964 | for (i = 0; i < cfgcnt; i++) { | |
1965 | for (j = 0; j < max98095->eq_textcnt; j++) { | |
1966 | if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0) | |
1967 | break; | |
1968 | } | |
1969 | ||
1970 | if (j != max98095->eq_textcnt) | |
1971 | continue; | |
1972 | ||
1973 | /* Expand the array */ | |
1974 | t = krealloc(max98095->eq_texts, | |
1975 | sizeof(char *) * (max98095->eq_textcnt + 1), | |
1976 | GFP_KERNEL); | |
1977 | if (t == NULL) | |
1978 | continue; | |
1979 | ||
1980 | /* Store the new entry */ | |
1981 | t[max98095->eq_textcnt] = cfg[i].name; | |
1982 | max98095->eq_textcnt++; | |
1983 | max98095->eq_texts = t; | |
1984 | } | |
1985 | ||
1986 | /* Now point the soc_enum to .texts array items */ | |
1987 | max98095->eq_enum.texts = max98095->eq_texts; | |
1988 | max98095->eq_enum.max = max98095->eq_textcnt; | |
1989 | ||
022658be | 1990 | ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); |
dad31ec1 PH |
1991 | if (ret != 0) |
1992 | dev_err(codec->dev, "Failed to add EQ control: %d\n", ret); | |
1993 | } | |
1994 | ||
c855a1a7 RM |
1995 | static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"}; |
1996 | ||
1997 | static int max98095_get_bq_channel(struct snd_soc_codec *codec, | |
1998 | const char *name) | |
dad31ec1 | 1999 | { |
c855a1a7 RM |
2000 | int i; |
2001 | ||
2002 | for (i = 0; i < ARRAY_SIZE(bq_mode_name); i++) | |
2003 | if (strcmp(name, bq_mode_name[i]) == 0) | |
2004 | return i; | |
2005 | ||
2006 | /* Shouldn't happen */ | |
2007 | dev_err(codec->dev, "Bad biquad channel name '%s'\n", name); | |
dad31ec1 PH |
2008 | return -EINVAL; |
2009 | } | |
2010 | ||
2011 | static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol, | |
2012 | struct snd_ctl_elem_value *ucontrol) | |
2013 | { | |
2014 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
2015 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2016 | struct max98095_pdata *pdata = max98095->pdata; | |
c855a1a7 | 2017 | int channel = max98095_get_bq_channel(codec, kcontrol->id.name); |
dad31ec1 | 2018 | struct max98095_cdata *cdata; |
f8d7b13e | 2019 | unsigned int sel = ucontrol->value.integer.value[0]; |
dad31ec1 PH |
2020 | struct max98095_biquad_cfg *coef_set; |
2021 | int fs, best, best_val, i; | |
2022 | int regmask, regsave; | |
2023 | ||
c855a1a7 RM |
2024 | if (channel < 0) |
2025 | return channel; | |
dad31ec1 | 2026 | |
53949425 TH |
2027 | if (!pdata || !max98095->bq_textcnt) |
2028 | return 0; | |
dad31ec1 PH |
2029 | |
2030 | if (sel >= pdata->bq_cfgcnt) | |
2031 | return -EINVAL; | |
2032 | ||
53949425 | 2033 | cdata = &max98095->dai[channel]; |
dad31ec1 | 2034 | cdata->bq_sel = sel; |
dad31ec1 PH |
2035 | fs = cdata->rate; |
2036 | ||
2037 | /* Find the selected configuration with nearest sample rate */ | |
2038 | best = 0; | |
2039 | best_val = INT_MAX; | |
2040 | for (i = 0; i < pdata->bq_cfgcnt; i++) { | |
2041 | if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 && | |
2042 | abs(pdata->bq_cfg[i].rate - fs) < best_val) { | |
2043 | best = i; | |
2044 | best_val = abs(pdata->bq_cfg[i].rate - fs); | |
2045 | } | |
2046 | } | |
2047 | ||
2048 | dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", | |
2049 | pdata->bq_cfg[best].name, | |
2050 | pdata->bq_cfg[best].rate, fs); | |
2051 | ||
2052 | coef_set = &pdata->bq_cfg[best]; | |
2053 | ||
2054 | regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN; | |
2055 | ||
2056 | /* Disable filter while configuring, and save current on/off state */ | |
2057 | regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); | |
2058 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); | |
2059 | ||
2060 | mutex_lock(&codec->mutex); | |
2061 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); | |
2062 | m98095_biquad_band(codec, channel, 0, coef_set->band1); | |
2063 | m98095_biquad_band(codec, channel, 1, coef_set->band2); | |
2064 | snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); | |
2065 | mutex_unlock(&codec->mutex); | |
2066 | ||
2067 | /* Restore the original on/off state */ | |
2068 | snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); | |
2069 | return 0; | |
2070 | } | |
2071 | ||
2072 | static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol, | |
2073 | struct snd_ctl_elem_value *ucontrol) | |
2074 | { | |
2075 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
2076 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
c855a1a7 | 2077 | int channel = max98095_get_bq_channel(codec, kcontrol->id.name); |
dad31ec1 PH |
2078 | struct max98095_cdata *cdata; |
2079 | ||
c855a1a7 RM |
2080 | if (channel < 0) |
2081 | return channel; | |
2082 | ||
dad31ec1 PH |
2083 | cdata = &max98095->dai[channel]; |
2084 | ucontrol->value.enumerated.item[0] = cdata->bq_sel; | |
2085 | ||
2086 | return 0; | |
2087 | } | |
2088 | ||
2089 | static void max98095_handle_bq_pdata(struct snd_soc_codec *codec) | |
2090 | { | |
2091 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2092 | struct max98095_pdata *pdata = max98095->pdata; | |
2093 | struct max98095_biquad_cfg *cfg; | |
2094 | unsigned int cfgcnt; | |
2095 | int i, j; | |
2096 | const char **t; | |
2097 | int ret; | |
2098 | ||
2099 | struct snd_kcontrol_new controls[] = { | |
c855a1a7 | 2100 | SOC_ENUM_EXT((char *)bq_mode_name[0], |
dad31ec1 PH |
2101 | max98095->bq_enum, |
2102 | max98095_get_bq_enum, | |
2103 | max98095_put_bq_enum), | |
c855a1a7 | 2104 | SOC_ENUM_EXT((char *)bq_mode_name[1], |
dad31ec1 PH |
2105 | max98095->bq_enum, |
2106 | max98095_get_bq_enum, | |
2107 | max98095_put_bq_enum), | |
2108 | }; | |
c855a1a7 | 2109 | BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name)); |
dad31ec1 PH |
2110 | |
2111 | cfg = pdata->bq_cfg; | |
2112 | cfgcnt = pdata->bq_cfgcnt; | |
2113 | ||
2114 | /* Setup an array of texts for the biquad enum. | |
2115 | * This is based on Mark Brown's equalizer driver code. | |
2116 | */ | |
2117 | max98095->bq_textcnt = 0; | |
2118 | max98095->bq_texts = NULL; | |
2119 | for (i = 0; i < cfgcnt; i++) { | |
2120 | for (j = 0; j < max98095->bq_textcnt; j++) { | |
2121 | if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0) | |
2122 | break; | |
2123 | } | |
2124 | ||
2125 | if (j != max98095->bq_textcnt) | |
2126 | continue; | |
2127 | ||
2128 | /* Expand the array */ | |
2129 | t = krealloc(max98095->bq_texts, | |
2130 | sizeof(char *) * (max98095->bq_textcnt + 1), | |
2131 | GFP_KERNEL); | |
2132 | if (t == NULL) | |
2133 | continue; | |
2134 | ||
2135 | /* Store the new entry */ | |
2136 | t[max98095->bq_textcnt] = cfg[i].name; | |
2137 | max98095->bq_textcnt++; | |
2138 | max98095->bq_texts = t; | |
2139 | } | |
2140 | ||
2141 | /* Now point the soc_enum to .texts array items */ | |
2142 | max98095->bq_enum.texts = max98095->bq_texts; | |
2143 | max98095->bq_enum.max = max98095->bq_textcnt; | |
2144 | ||
022658be | 2145 | ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); |
dad31ec1 PH |
2146 | if (ret != 0) |
2147 | dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret); | |
2148 | } | |
2149 | ||
82a5a936 PH |
2150 | static void max98095_handle_pdata(struct snd_soc_codec *codec) |
2151 | { | |
2152 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2153 | struct max98095_pdata *pdata = max98095->pdata; | |
2154 | u8 regval = 0; | |
2155 | ||
2156 | if (!pdata) { | |
2157 | dev_dbg(codec->dev, "No platform data\n"); | |
2158 | return; | |
2159 | } | |
2160 | ||
2161 | /* Configure mic for analog/digital mic mode */ | |
2162 | if (pdata->digmic_left_mode) | |
2163 | regval |= M98095_DIGMIC_L; | |
2164 | ||
2165 | if (pdata->digmic_right_mode) | |
2166 | regval |= M98095_DIGMIC_R; | |
2167 | ||
2168 | snd_soc_write(codec, M98095_087_CFG_MIC, regval); | |
dad31ec1 PH |
2169 | |
2170 | /* Configure equalizers */ | |
2171 | if (pdata->eq_cfgcnt) | |
2172 | max98095_handle_eq_pdata(codec); | |
2173 | ||
2174 | /* Configure bi-quad filters */ | |
2175 | if (pdata->bq_cfgcnt) | |
2176 | max98095_handle_bq_pdata(codec); | |
82a5a936 PH |
2177 | } |
2178 | ||
9dd90c5d RK |
2179 | static irqreturn_t max98095_report_jack(int irq, void *data) |
2180 | { | |
2181 | struct snd_soc_codec *codec = data; | |
2182 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2183 | unsigned int value; | |
2184 | int hp_report = 0; | |
2185 | int mic_report = 0; | |
2186 | ||
2187 | /* Read the Jack Status Register */ | |
2188 | value = snd_soc_read(codec, M98095_007_JACK_AUTO_STS); | |
2189 | ||
2190 | /* If ddone is not set, then detection isn't finished yet */ | |
2191 | if ((value & M98095_DDONE) == 0) | |
2192 | return IRQ_NONE; | |
2193 | ||
2194 | /* if hp, check its bit, and if set, clear it */ | |
2195 | if ((value & M98095_HP_IN || value & M98095_LO_IN) && | |
2196 | max98095->headphone_jack) | |
2197 | hp_report |= SND_JACK_HEADPHONE; | |
2198 | ||
2199 | /* if mic, check its bit, and if set, clear it */ | |
2200 | if ((value & M98095_MIC_IN) && max98095->mic_jack) | |
2201 | mic_report |= SND_JACK_MICROPHONE; | |
2202 | ||
2203 | if (max98095->headphone_jack == max98095->mic_jack) { | |
2204 | snd_soc_jack_report(max98095->headphone_jack, | |
2205 | hp_report | mic_report, | |
2206 | SND_JACK_HEADSET); | |
2207 | } else { | |
2208 | if (max98095->headphone_jack) | |
2209 | snd_soc_jack_report(max98095->headphone_jack, | |
2210 | hp_report, SND_JACK_HEADPHONE); | |
2211 | if (max98095->mic_jack) | |
2212 | snd_soc_jack_report(max98095->mic_jack, | |
2213 | mic_report, SND_JACK_MICROPHONE); | |
2214 | } | |
2215 | ||
2216 | return IRQ_HANDLED; | |
2217 | } | |
2218 | ||
a265367c | 2219 | static int max98095_jack_detect_enable(struct snd_soc_codec *codec) |
9dd90c5d RK |
2220 | { |
2221 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2222 | int ret = 0; | |
2223 | int detect_enable = M98095_JDEN; | |
2224 | unsigned int slew = M98095_DEFAULT_SLEW_DELAY; | |
2225 | ||
2226 | if (max98095->pdata->jack_detect_pin5en) | |
2227 | detect_enable |= M98095_PIN5EN; | |
2228 | ||
0841b04a MB |
2229 | if (max98095->pdata->jack_detect_delay) |
2230 | slew = max98095->pdata->jack_detect_delay; | |
9dd90c5d RK |
2231 | |
2232 | ret = snd_soc_write(codec, M98095_08E_JACK_DC_SLEW, slew); | |
2233 | if (ret < 0) { | |
2234 | dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret); | |
2235 | return ret; | |
2236 | } | |
2237 | ||
2238 | /* configure auto detection to be enabled */ | |
2239 | ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, detect_enable); | |
2240 | if (ret < 0) { | |
2241 | dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret); | |
2242 | return ret; | |
2243 | } | |
2244 | ||
2245 | return ret; | |
2246 | } | |
2247 | ||
a265367c | 2248 | static int max98095_jack_detect_disable(struct snd_soc_codec *codec) |
9dd90c5d RK |
2249 | { |
2250 | int ret = 0; | |
2251 | ||
2252 | /* configure auto detection to be disabled */ | |
2253 | ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, 0x0); | |
2254 | if (ret < 0) { | |
2255 | dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret); | |
2256 | return ret; | |
2257 | } | |
2258 | ||
2259 | return ret; | |
2260 | } | |
2261 | ||
2262 | int max98095_jack_detect(struct snd_soc_codec *codec, | |
2263 | struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack) | |
2264 | { | |
2265 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2266 | struct i2c_client *client = to_i2c_client(codec->dev); | |
2267 | int ret = 0; | |
2268 | ||
2269 | max98095->headphone_jack = hp_jack; | |
2270 | max98095->mic_jack = mic_jack; | |
2271 | ||
2272 | /* only progress if we have at least 1 jack pointer */ | |
2273 | if (!hp_jack && !mic_jack) | |
2274 | return -EINVAL; | |
2275 | ||
2276 | max98095_jack_detect_enable(codec); | |
2277 | ||
2278 | /* enable interrupts for headphone jack detection */ | |
2279 | ret = snd_soc_update_bits(codec, M98095_013_JACK_INT_EN, | |
2280 | M98095_IDDONE, M98095_IDDONE); | |
2281 | if (ret < 0) { | |
2282 | dev_err(codec->dev, "Failed to cfg jack irqs %d\n", ret); | |
2283 | return ret; | |
2284 | } | |
2285 | ||
2286 | max98095_report_jack(client->irq, codec); | |
2287 | return 0; | |
2288 | } | |
a265367c | 2289 | EXPORT_SYMBOL_GPL(max98095_jack_detect); |
9dd90c5d | 2290 | |
82a5a936 | 2291 | #ifdef CONFIG_PM |
84b315ee | 2292 | static int max98095_suspend(struct snd_soc_codec *codec) |
82a5a936 | 2293 | { |
9dd90c5d RK |
2294 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
2295 | ||
2296 | if (max98095->headphone_jack || max98095->mic_jack) | |
2297 | max98095_jack_detect_disable(codec); | |
2298 | ||
82a5a936 PH |
2299 | max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); |
2300 | ||
2301 | return 0; | |
2302 | } | |
2303 | ||
2304 | static int max98095_resume(struct snd_soc_codec *codec) | |
2305 | { | |
9dd90c5d RK |
2306 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
2307 | struct i2c_client *client = to_i2c_client(codec->dev); | |
2308 | ||
82a5a936 PH |
2309 | max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
2310 | ||
9dd90c5d RK |
2311 | if (max98095->headphone_jack || max98095->mic_jack) { |
2312 | max98095_jack_detect_enable(codec); | |
2313 | max98095_report_jack(client->irq, codec); | |
2314 | } | |
2315 | ||
82a5a936 PH |
2316 | return 0; |
2317 | } | |
2318 | #else | |
2319 | #define max98095_suspend NULL | |
2320 | #define max98095_resume NULL | |
2321 | #endif | |
2322 | ||
2323 | static int max98095_reset(struct snd_soc_codec *codec) | |
2324 | { | |
2325 | int i, ret; | |
2326 | ||
2327 | /* Gracefully reset the DSP core and the codec hardware | |
2328 | * in a proper sequence */ | |
2329 | ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0); | |
2330 | if (ret < 0) { | |
2331 | dev_err(codec->dev, "Failed to reset DSP: %d\n", ret); | |
2332 | return ret; | |
2333 | } | |
2334 | ||
2335 | ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0); | |
2336 | if (ret < 0) { | |
2337 | dev_err(codec->dev, "Failed to reset codec: %d\n", ret); | |
2338 | return ret; | |
2339 | } | |
2340 | ||
2341 | /* Reset to hardware default for registers, as there is not | |
2342 | * a soft reset hardware control register */ | |
2343 | for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) { | |
2344 | ret = snd_soc_write(codec, i, max98095_reg_def[i]); | |
2345 | if (ret < 0) { | |
2346 | dev_err(codec->dev, "Failed to reset: %d\n", ret); | |
2347 | return ret; | |
2348 | } | |
2349 | } | |
2350 | ||
2351 | return ret; | |
2352 | } | |
2353 | ||
2354 | static int max98095_probe(struct snd_soc_codec *codec) | |
2355 | { | |
2356 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); | |
2357 | struct max98095_cdata *cdata; | |
9dd90c5d | 2358 | struct i2c_client *client; |
82a5a936 PH |
2359 | int ret = 0; |
2360 | ||
2361 | ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); | |
2362 | if (ret != 0) { | |
2363 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
2364 | return ret; | |
2365 | } | |
2366 | ||
2367 | /* reset the codec, the DSP core, and disable all interrupts */ | |
2368 | max98095_reset(codec); | |
2369 | ||
9dd90c5d RK |
2370 | client = to_i2c_client(codec->dev); |
2371 | ||
82a5a936 PH |
2372 | /* initialize private data */ |
2373 | ||
2374 | max98095->sysclk = (unsigned)-1; | |
dad31ec1 PH |
2375 | max98095->eq_textcnt = 0; |
2376 | max98095->bq_textcnt = 0; | |
82a5a936 PH |
2377 | |
2378 | cdata = &max98095->dai[0]; | |
2379 | cdata->rate = (unsigned)-1; | |
2380 | cdata->fmt = (unsigned)-1; | |
dad31ec1 PH |
2381 | cdata->eq_sel = 0; |
2382 | cdata->bq_sel = 0; | |
82a5a936 PH |
2383 | |
2384 | cdata = &max98095->dai[1]; | |
2385 | cdata->rate = (unsigned)-1; | |
2386 | cdata->fmt = (unsigned)-1; | |
dad31ec1 PH |
2387 | cdata->eq_sel = 0; |
2388 | cdata->bq_sel = 0; | |
82a5a936 PH |
2389 | |
2390 | cdata = &max98095->dai[2]; | |
2391 | cdata->rate = (unsigned)-1; | |
2392 | cdata->fmt = (unsigned)-1; | |
dad31ec1 PH |
2393 | cdata->eq_sel = 0; |
2394 | cdata->bq_sel = 0; | |
82a5a936 PH |
2395 | |
2396 | max98095->lin_state = 0; | |
2397 | max98095->mic1pre = 0; | |
2398 | max98095->mic2pre = 0; | |
2399 | ||
9dd90c5d RK |
2400 | if (client->irq) { |
2401 | /* register an audio interrupt */ | |
2402 | ret = request_threaded_irq(client->irq, NULL, | |
2403 | max98095_report_jack, | |
2404 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | |
2405 | "max98095", codec); | |
2406 | if (ret) { | |
2407 | dev_err(codec->dev, "Failed to request IRQ: %d\n", ret); | |
2408 | goto err_access; | |
2409 | } | |
2410 | } | |
2411 | ||
82a5a936 PH |
2412 | ret = snd_soc_read(codec, M98095_0FF_REV_ID); |
2413 | if (ret < 0) { | |
bab3b59d | 2414 | dev_err(codec->dev, "Failure reading hardware revision: %d\n", |
82a5a936 | 2415 | ret); |
9dd90c5d | 2416 | goto err_irq; |
82a5a936 | 2417 | } |
bab3b59d | 2418 | dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A'); |
82a5a936 PH |
2419 | |
2420 | snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV); | |
2421 | ||
2422 | /* initialize registers cache to hardware default */ | |
2423 | max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
2424 | ||
2425 | snd_soc_write(codec, M98095_048_MIX_DAC_LR, | |
2426 | M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR); | |
2427 | ||
2428 | snd_soc_write(codec, M98095_049_MIX_DAC_M, | |
2429 | M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM); | |
2430 | ||
2431 | snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM); | |
2432 | snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL); | |
2433 | snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL); | |
2434 | ||
2435 | snd_soc_write(codec, M98095_02C_DAI1_IOCFG, | |
2436 | M98095_S1NORMAL|M98095_SDATA); | |
2437 | ||
2438 | snd_soc_write(codec, M98095_036_DAI2_IOCFG, | |
2439 | M98095_S2NORMAL|M98095_SDATA); | |
2440 | ||
2441 | snd_soc_write(codec, M98095_040_DAI3_IOCFG, | |
2442 | M98095_S3NORMAL|M98095_SDATA); | |
2443 | ||
2444 | max98095_handle_pdata(codec); | |
2445 | ||
2446 | /* take the codec out of the shut down */ | |
2447 | snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN, | |
2448 | M98095_SHDNRUN); | |
2449 | ||
2450 | max98095_add_widgets(codec); | |
2451 | ||
9dd90c5d RK |
2452 | return 0; |
2453 | ||
2454 | err_irq: | |
2455 | if (client->irq) | |
2456 | free_irq(client->irq, codec); | |
82a5a936 PH |
2457 | err_access: |
2458 | return ret; | |
2459 | } | |
2460 | ||
2461 | static int max98095_remove(struct snd_soc_codec *codec) | |
2462 | { | |
9dd90c5d RK |
2463 | struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); |
2464 | struct i2c_client *client = to_i2c_client(codec->dev); | |
2465 | ||
82a5a936 PH |
2466 | max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); |
2467 | ||
9dd90c5d RK |
2468 | if (max98095->headphone_jack || max98095->mic_jack) |
2469 | max98095_jack_detect_disable(codec); | |
2470 | ||
2471 | if (client->irq) | |
2472 | free_irq(client->irq, codec); | |
2473 | ||
82a5a936 PH |
2474 | return 0; |
2475 | } | |
2476 | ||
2477 | static struct snd_soc_codec_driver soc_codec_dev_max98095 = { | |
2478 | .probe = max98095_probe, | |
2479 | .remove = max98095_remove, | |
2480 | .suspend = max98095_suspend, | |
2481 | .resume = max98095_resume, | |
2482 | .set_bias_level = max98095_set_bias_level, | |
2483 | .reg_cache_size = ARRAY_SIZE(max98095_reg_def), | |
2484 | .reg_word_size = sizeof(u8), | |
2485 | .reg_cache_default = max98095_reg_def, | |
2486 | .readable_register = max98095_readable, | |
2487 | .volatile_register = max98095_volatile, | |
2488 | .dapm_widgets = max98095_dapm_widgets, | |
2489 | .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets), | |
2490 | .dapm_routes = max98095_audio_map, | |
2491 | .num_dapm_routes = ARRAY_SIZE(max98095_audio_map), | |
2492 | }; | |
2493 | ||
2494 | static int max98095_i2c_probe(struct i2c_client *i2c, | |
2495 | const struct i2c_device_id *id) | |
2496 | { | |
2497 | struct max98095_priv *max98095; | |
2498 | int ret; | |
2499 | ||
b1b54882 AL |
2500 | max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv), |
2501 | GFP_KERNEL); | |
82a5a936 PH |
2502 | if (max98095 == NULL) |
2503 | return -ENOMEM; | |
2504 | ||
2505 | max98095->devtype = id->driver_data; | |
2506 | i2c_set_clientdata(i2c, max98095); | |
82a5a936 PH |
2507 | max98095->pdata = i2c->dev.platform_data; |
2508 | ||
bab3b59d TH |
2509 | ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98095, |
2510 | max98095_dai, ARRAY_SIZE(max98095_dai)); | |
82a5a936 PH |
2511 | return ret; |
2512 | } | |
2513 | ||
7a79e94e | 2514 | static int max98095_i2c_remove(struct i2c_client *client) |
82a5a936 PH |
2515 | { |
2516 | snd_soc_unregister_codec(&client->dev); | |
82a5a936 PH |
2517 | return 0; |
2518 | } | |
2519 | ||
2520 | static const struct i2c_device_id max98095_i2c_id[] = { | |
2521 | { "max98095", MAX98095 }, | |
2522 | { } | |
2523 | }; | |
2524 | MODULE_DEVICE_TABLE(i2c, max98095_i2c_id); | |
2525 | ||
2526 | static struct i2c_driver max98095_i2c_driver = { | |
2527 | .driver = { | |
2528 | .name = "max98095", | |
2529 | .owner = THIS_MODULE, | |
2530 | }, | |
2531 | .probe = max98095_i2c_probe, | |
7a79e94e | 2532 | .remove = max98095_i2c_remove, |
82a5a936 PH |
2533 | .id_table = max98095_i2c_id, |
2534 | }; | |
2535 | ||
a8af02cf | 2536 | module_i2c_driver(max98095_i2c_driver); |
82a5a936 PH |
2537 | |
2538 | MODULE_DESCRIPTION("ALSA SoC MAX98095 driver"); | |
2539 | MODULE_AUTHOR("Peter Hsiang"); | |
2540 | MODULE_LICENSE("GPL"); |