projects / mirror_ubuntu-hirsute-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 3f22e31d JH |
1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | // Copyright (c) 2016, The Linux Foundation. All rights reserved. | |
| 3 | ||
| 585e881e SK |
4 | #include <linux/module.h> |
| 5 | #include <linux/err.h> | |
| 6 | #include <linux/kernel.h> | |
| 7 | #include <linux/delay.h> | |
| 8 | #include <linux/regulator/consumer.h> | |
| 9 | #include <linux/types.h> | |
| 10 | #include <linux/clk.h> | |
| 11 | #include <linux/of.h> | |
| 12 | #include <linux/platform_device.h> | |
| 13 | #include <linux/regmap.h> | |
| 14 | #include <sound/soc.h> | |
| 15 | #include <sound/pcm.h> | |
| 16 | #include <sound/pcm_params.h> | |
| 17 | #include <sound/tlv.h> | |
| de66b345 | 18 | #include <sound/jack.h> |
| 585e881e SK |
19 | |
| 20 | #define CDC_D_REVISION1 (0xf000) | |
| 21 | #define CDC_D_PERPH_SUBTYPE (0xf005) | |
| ff69c97e SK |
22 | #define CDC_D_INT_EN_SET (0xf015) |
| 23 | #define CDC_D_INT_EN_CLR (0xf016) | |
| de66b345 SK |
24 | #define MBHC_SWITCH_INT BIT(7) |
| 25 | #define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6) | |
| 26 | #define MBHC_BUTTON_PRESS_DET BIT(5) | |
| 27 | #define MBHC_BUTTON_RELEASE_DET BIT(4) | |
| 585e881e SK |
28 | #define CDC_D_CDC_RST_CTL (0xf046) |
| 29 | #define RST_CTL_DIG_SW_RST_N_MASK BIT(7) | |
| 30 | #define RST_CTL_DIG_SW_RST_N_RESET 0 | |
| 31 | #define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7) | |
| 32 | ||
| 33 | #define CDC_D_CDC_TOP_CLK_CTL (0xf048) | |
| 34 | #define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3)) | |
| 35 | #define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2) | |
| 36 | #define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3) | |
| 37 | ||
| 38 | #define CDC_D_CDC_ANA_CLK_CTL (0xf049) | |
| 39 | #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0) | |
| 40 | #define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0) | |
| 41 | #define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1) | |
| 42 | #define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4) | |
| 43 | #define ANA_CLK_CTL_SPKR_CLK_EN BIT(4) | |
| 44 | #define ANA_CLK_CTL_TXA_CLK25_EN BIT(5) | |
| 45 | ||
| 46 | #define CDC_D_CDC_DIG_CLK_CTL (0xf04A) | |
| 47 | #define DIG_CLK_CTL_RXD1_CLK_EN BIT(0) | |
| 48 | #define DIG_CLK_CTL_RXD2_CLK_EN BIT(1) | |
| deab4563 | 49 | #define DIG_CLK_CTL_RXD3_CLK_EN BIT(2) |
| de66b345 SK |
50 | #define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK BIT(3) |
| 51 | #define DIG_CLK_CTL_D_MBHC_CLK_EN BIT(3) | |
| 585e881e SK |
52 | #define DIG_CLK_CTL_TXD_CLK_EN BIT(4) |
| 53 | #define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6) | |
| 54 | #define DIG_CLK_CTL_NCP_CLK_EN BIT(6) | |
| 55 | #define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7) | |
| 56 | #define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7) | |
| 57 | ||
| 58 | #define CDC_D_CDC_CONN_TX1_CTL (0xf050) | |
| 59 | #define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0) | |
| 60 | #define CONN_TX1_SERIAL_TX1_ADC_1 0x0 | |
| 61 | #define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1 | |
| 62 | #define CONN_TX1_SERIAL_TX1_ZERO 0x2 | |
| 63 | ||
| 64 | #define CDC_D_CDC_CONN_TX2_CTL (0xf051) | |
| 65 | #define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0) | |
| 66 | #define CONN_TX2_SERIAL_TX2_ADC_2 0x0 | |
| 67 | #define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1 | |
| 68 | #define CONN_TX2_SERIAL_TX2_ZERO 0x2 | |
| 69 | #define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052) | |
| 70 | #define CDC_D_CDC_CONN_RX1_CTL (0xf053) | |
| 71 | #define CDC_D_CDC_CONN_RX2_CTL (0xf054) | |
| 72 | #define CDC_D_CDC_CONN_RX3_CTL (0xf055) | |
| 73 | #define CDC_D_CDC_CONN_RX_LB_CTL (0xf056) | |
| 74 | #define CDC_D_SEC_ACCESS (0xf0D0) | |
| 75 | #define CDC_D_PERPH_RESET_CTL3 (0xf0DA) | |
| 76 | #define CDC_D_PERPH_RESET_CTL4 (0xf0DB) | |
| 77 | #define CDC_A_REVISION1 (0xf100) | |
| 78 | #define CDC_A_REVISION2 (0xf101) | |
| 79 | #define CDC_A_REVISION3 (0xf102) | |
| 80 | #define CDC_A_REVISION4 (0xf103) | |
| 81 | #define CDC_A_PERPH_TYPE (0xf104) | |
| 82 | #define CDC_A_PERPH_SUBTYPE (0xf105) | |
| 83 | #define CDC_A_INT_RT_STS (0xf110) | |
| 84 | #define CDC_A_INT_SET_TYPE (0xf111) | |
| 85 | #define CDC_A_INT_POLARITY_HIGH (0xf112) | |
| 86 | #define CDC_A_INT_POLARITY_LOW (0xf113) | |
| 87 | #define CDC_A_INT_LATCHED_CLR (0xf114) | |
| 88 | #define CDC_A_INT_EN_SET (0xf115) | |
| 89 | #define CDC_A_INT_EN_CLR (0xf116) | |
| 90 | #define CDC_A_INT_LATCHED_STS (0xf118) | |
| 91 | #define CDC_A_INT_PENDING_STS (0xf119) | |
| 92 | #define CDC_A_INT_MID_SEL (0xf11A) | |
| 93 | #define CDC_A_INT_PRIORITY (0xf11B) | |
| 94 | #define CDC_A_MICB_1_EN (0xf140) | |
| 95 | #define MICB_1_EN_MICB_ENABLE BIT(7) | |
| 96 | #define MICB_1_EN_BYP_CAP_MASK BIT(6) | |
| 97 | #define MICB_1_EN_NO_EXT_BYP_CAP BIT(6) | |
| 98 | #define MICB_1_EN_EXT_BYP_CAP 0 | |
| 99 | #define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5) | |
| 100 | #define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5) | |
| 101 | #define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1) | |
| 102 | #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4) | |
| 103 | #define MICB_1_EN_PULL_UP_EN_MASK BIT(4) | |
| 104 | #define MICB_1_EN_TX3_GND_SEL_MASK BIT(0) | |
| 105 | #define MICB_1_EN_TX3_GND_SEL_TX_GND 0 | |
| 106 | ||
| 107 | #define CDC_A_MICB_1_VAL (0xf141) | |
| e269998d SK |
108 | #define MICB_MIN_VAL 1600 |
| 109 | #define MICB_STEP_SIZE 50 | |
| 664611e7 | 110 | #define MICB_VOLTAGE_REGVAL(v) (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3) |
| 585e881e SK |
111 | #define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3) |
| 112 | #define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3) | |
| e269998d | 113 | #define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3) |
| 585e881e SK |
114 | #define CDC_A_MICB_1_CTL (0xf142) |
| 115 | ||
| 116 | #define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1) | |
| 117 | #define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1) | |
| 118 | #define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5) | |
| 119 | #define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5) | |
| 120 | #define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6) | |
| 121 | #define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6) | |
| 122 | ||
| 123 | #define CDC_A_MICB_1_INT_RBIAS (0xf143) | |
| 124 | #define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7) | |
| 125 | #define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7) | |
| 126 | #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0 | |
| 127 | ||
| 128 | #define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6) | |
| 129 | #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6) | |
| 130 | #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0 | |
| 131 | ||
| 132 | #define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4) | |
| 133 | #define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4) | |
| 134 | #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0 | |
| 135 | #define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3) | |
| 136 | #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3) | |
| 137 | #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0 | |
| 138 | ||
| 139 | #define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1) | |
| 140 | #define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1) | |
| 141 | #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0 | |
| 142 | #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0) | |
| 143 | #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0) | |
| 144 | #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0 | |
| 145 | ||
| 146 | #define CDC_A_MICB_2_EN (0xf144) | |
| de66b345 SK |
147 | #define CDC_A_MICB_2_EN_ENABLE BIT(7) |
| 148 | #define CDC_A_MICB_2_PULL_DOWN_EN_MASK BIT(5) | |
| 149 | #define CDC_A_MICB_2_PULL_DOWN_EN BIT(5) | |
| 585e881e SK |
150 | #define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145) |
| 151 | #define CDC_A_MASTER_BIAS_CTL (0xf146) | |
| de66b345 SK |
152 | #define CDC_A_MBHC_DET_CTL_1 (0xf147) |
| 153 | #define CDC_A_MBHC_DET_CTL_L_DET_EN BIT(7) | |
| 154 | #define CDC_A_MBHC_DET_CTL_GND_DET_EN BIT(6) | |
| 155 | #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION BIT(5) | |
| 156 | #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0) | |
| 157 | #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK BIT(5) | |
| 158 | #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT (5) | |
| 159 | #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO BIT(4) | |
| 160 | #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL BIT(3) | |
| 161 | #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK GENMASK(4, 3) | |
| 162 | #define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN BIT(2) | |
| 163 | #define CDC_A_MBHC_DET_CTL_2 (0xf150) | |
| 164 | #define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 (BIT(7) | BIT(6)) | |
| 165 | #define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5) | |
| 166 | #define CDC_A_PLUG_TYPE_MASK GENMASK(4, 3) | |
| 167 | #define CDC_A_HPHL_PLUG_TYPE_NO BIT(4) | |
| 168 | #define CDC_A_GND_PLUG_TYPE_NO BIT(3) | |
| 169 | #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0) | |
| 170 | #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0) | |
| 171 | #define CDC_A_MBHC_FSM_CTL (0xf151) | |
| 172 | #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN BIT(7) | |
| 173 | #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK BIT(7) | |
| 174 | #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4) | |
| 175 | #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK GENMASK(6, 4) | |
| 176 | #define CDC_A_MBHC_DBNC_TIMER (0xf152) | |
| 177 | #define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS BIT(3) | |
| 178 | #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4) | |
| 179 | #define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153) | |
| 180 | #define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154) | |
| 181 | #define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155) | |
| 182 | #define CDC_A_MBHC_BTN3_CTL (0xf156) | |
| 183 | #define CDC_A_MBHC_BTN4_CTL (0xf157) | |
| 184 | #define CDC_A_MBHC_BTN_VREF_FINE_SHIFT (2) | |
| 185 | #define CDC_A_MBHC_BTN_VREF_FINE_MASK GENMASK(4, 2) | |
| 186 | #define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5) | |
| 187 | #define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5) | |
| 188 | #define CDC_A_MBHC_BTN_VREF_MASK (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \ | |
| 189 | CDC_A_MBHC_BTN_VREF_FINE_MASK) | |
| 190 | #define CDC_A_MBHC_RESULT_1 (0xf158) | |
| 191 | #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0) | |
| 585e881e SK |
192 | #define CDC_A_TX_1_EN (0xf160) |
| 193 | #define CDC_A_TX_2_EN (0xf161) | |
| 194 | #define CDC_A_TX_1_2_TEST_CTL_1 (0xf162) | |
| 195 | #define CDC_A_TX_1_2_TEST_CTL_2 (0xf163) | |
| 196 | #define CDC_A_TX_1_2_ATEST_CTL (0xf164) | |
| 197 | #define CDC_A_TX_1_2_OPAMP_BIAS (0xf165) | |
| 198 | #define CDC_A_TX_3_EN (0xf167) | |
| 199 | #define CDC_A_NCP_EN (0xf180) | |
| 200 | #define CDC_A_NCP_CLK (0xf181) | |
| 201 | #define CDC_A_NCP_FBCTRL (0xf183) | |
| 202 | #define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5) | |
| 203 | #define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5) | |
| 204 | #define CDC_A_NCP_BIAS (0xf184) | |
| 205 | #define CDC_A_NCP_VCTRL (0xf185) | |
| 206 | #define CDC_A_NCP_TEST (0xf186) | |
| 207 | #define CDC_A_NCP_CLIM_ADDR (0xf187) | |
| 208 | #define CDC_A_RX_CLOCK_DIVIDER (0xf190) | |
| 209 | #define CDC_A_RX_COM_OCP_CTL (0xf191) | |
| 210 | #define CDC_A_RX_COM_OCP_COUNT (0xf192) | |
| 211 | #define CDC_A_RX_COM_BIAS_DAC (0xf193) | |
| 212 | #define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7) | |
| 213 | #define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7) | |
| 214 | #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0) | |
| 215 | #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0) | |
| 216 | ||
| 217 | #define CDC_A_RX_HPH_BIAS_PA (0xf194) | |
| 218 | #define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195) | |
| 219 | #define CDC_A_RX_HPH_BIAS_CNP (0xf196) | |
| 220 | #define CDC_A_RX_HPH_CNP_EN (0xf197) | |
| 221 | #define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B) | |
| 222 | #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1) | |
| 223 | #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1) | |
| 224 | #define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D) | |
| 225 | #define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1) | |
| 226 | #define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1) | |
| 227 | ||
| 228 | #define CDC_A_RX_EAR_CTL (0xf19E) | |
| 229 | #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0) | |
| 230 | #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0) | |
| 7d2f70f2 SG |
231 | #define RX_EAR_CTL_PA_EAR_PA_EN_MASK BIT(6) |
| 232 | #define RX_EAR_CTL_PA_EAR_PA_EN_ENABLE BIT(6) | |
| 233 | #define RX_EAR_CTL_PA_SEL_MASK BIT(7) | |
| 234 | #define RX_EAR_CTL_PA_SEL BIT(7) | |
| 585e881e SK |
235 | |
| 236 | #define CDC_A_SPKR_DAC_CTL (0xf1B0) | |
| 237 | #define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4) | |
| 238 | #define SPKR_DAC_CTL_DAC_RESET_NORMAL 0 | |
| 239 | ||
| 240 | #define CDC_A_SPKR_DRV_CTL (0xf1B2) | |
| 241 | #define SPKR_DRV_CTL_DEF_MASK 0xEF | |
| 242 | #define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7) | |
| 243 | #define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7) | |
| 244 | #define SPKR_DRV_CAL_EN BIT(6) | |
| 245 | #define SPKR_DRV_SETTLE_EN BIT(5) | |
| 246 | #define SPKR_DRV_FW_EN BIT(3) | |
| 247 | #define SPKR_DRV_BOOST_SET BIT(2) | |
| 248 | #define SPKR_DRV_CMFB_SET BIT(1) | |
| 249 | #define SPKR_DRV_GAIN_SET BIT(0) | |
| 250 | #define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \ | |
| 251 | SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \ | |
| 252 | SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \ | |
| 253 | SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET) | |
| 254 | #define CDC_A_SPKR_OCP_CTL (0xf1B4) | |
| 255 | #define CDC_A_SPKR_PWRSTG_CTL (0xf1B5) | |
| 256 | #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0) | |
| 257 | #define SPKR_PWRSTG_CTL_DAC_EN BIT(0) | |
| 258 | #define SPKR_PWRSTG_CTL_MASK 0xE0 | |
| 259 | #define SPKR_PWRSTG_CTL_BBM_MASK BIT(7) | |
| 260 | #define SPKR_PWRSTG_CTL_BBM_EN BIT(7) | |
| 261 | #define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6) | |
| 262 | #define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6) | |
| 263 | #define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5) | |
| 264 | #define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5) | |
| 265 | ||
| 266 | #define CDC_A_SPKR_DRV_DBG (0xf1B7) | |
| 267 | #define CDC_A_CURRENT_LIMIT (0xf1C0) | |
| 268 | #define CDC_A_BOOST_EN_CTL (0xf1C3) | |
| 269 | #define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4) | |
| 270 | #define CDC_A_SEC_ACCESS (0xf1D0) | |
| 271 | #define CDC_A_PERPH_RESET_CTL3 (0xf1DA) | |
| 272 | #define CDC_A_PERPH_RESET_CTL4 (0xf1DB) | |
| 273 | ||
| 274 | #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ | |
| 275 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000) | |
| 276 | #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
| 51f493ae | 277 | SNDRV_PCM_FMTBIT_S32_LE) |
| 585e881e | 278 | |
| de66b345 SK |
279 | static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | |
| 280 | SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4; | |
| 281 | static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET; | |
| 282 | ||
| 585e881e SK |
283 | static const char * const supply_names[] = { |
| 284 | "vdd-cdc-io", | |
| 285 | "vdd-cdc-tx-rx-cx", | |
| 286 | }; | |
| 287 | ||
| de66b345 SK |
288 | #define MBHC_MAX_BUTTONS (5) |
| 289 | ||
| 585e881e SK |
290 | struct pm8916_wcd_analog_priv { |
| 291 | u16 pmic_rev; | |
| 292 | u16 codec_version; | |
| de66b345 SK |
293 | bool mbhc_btn_enabled; |
| 294 | /* special event to detect accessory type */ | |
| d430a7e3 | 295 | int mbhc_btn0_released; |
| de66b345 | 296 | bool detect_accessory_type; |
| 585e881e | 297 | struct clk *mclk; |
| 732ae454 | 298 | struct snd_soc_component *component; |
| 585e881e | 299 | struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; |
| de66b345 SK |
300 | struct snd_soc_jack *jack; |
| 301 | bool hphl_jack_type_normally_open; | |
| 302 | bool gnd_jack_type_normally_open; | |
| 303 | /* Voltage threshold when internal current source of 100uA is used */ | |
| 304 | u32 vref_btn_cs[MBHC_MAX_BUTTONS]; | |
| 305 | /* Voltage threshold when microphone bias is ON */ | |
| 306 | u32 vref_btn_micb[MBHC_MAX_BUTTONS]; | |
| 9f3b777f TS |
307 | unsigned int micbias1_cap_mode; |
| 308 | unsigned int micbias2_cap_mode; | |
| e269998d | 309 | unsigned int micbias_mv; |
| 585e881e SK |
310 | }; |
| 311 | ||
| 312 | static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" }; | |
| 9110d1b0 | 313 | static const char *const rdac2_mux_text[] = { "RX1", "RX2" }; |
| 585e881e SK |
314 | static const char *const hph_text[] = { "ZERO", "Switch", }; |
| 315 | ||
| 316 | static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT( | |
| 317 | ARRAY_SIZE(hph_text), hph_text); | |
| 318 | ||
| 7d2f70f2 | 319 | static const struct snd_kcontrol_new ear_mux = SOC_DAPM_ENUM("EAR_S", hph_enum); |
| 585e881e SK |
320 | static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum); |
| 321 | static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum); | |
| 322 | ||
| 323 | /* ADC2 MUX */ | |
| 324 | static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT( | |
| 325 | ARRAY_SIZE(adc2_mux_text), adc2_mux_text); | |
| 326 | ||
| 327 | /* RDAC2 MUX */ | |
| 328 | static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE( | |
| 9110d1b0 | 329 | CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 2, rdac2_mux_text); |
| 585e881e SK |
330 | |
| 331 | static const struct snd_kcontrol_new spkr_switch[] = { | |
| 332 | SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0) | |
| 333 | }; | |
| 334 | ||
| 335 | static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM( | |
| 336 | "RDAC2 MUX Mux", rdac2_mux_enum); | |
| 337 | static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM( | |
| 338 | "ADC2 MUX Mux", adc2_enum); | |
| 339 | ||
| 340 | /* Analog Gain control 0 dB to +24 dB in 6 dB steps */ | |
| 341 | static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0); | |
| 342 | ||
| 343 | static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = { | |
| 344 | SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain), | |
| 345 | SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain), | |
| 346 | SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain), | |
| 347 | }; | |
| 348 | ||
| 732ae454 | 349 | static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component) |
| 585e881e | 350 | { |
| 732ae454 | 351 | struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); |
| e269998d | 352 | |
| 732ae454 | 353 | snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, |
| 585e881e SK |
354 | MICB_1_CTL_EXT_PRECHARG_EN_MASK | |
| 355 | MICB_1_CTL_INT_PRECHARG_BYP_MASK, | |
| 356 | MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL | |
| 357 | | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE); | |
| 358 | ||
| e269998d | 359 | if (wcd->micbias_mv) { |
| 732ae454 | 360 | snd_soc_component_update_bits(component, CDC_A_MICB_1_VAL, |
| 664611e7 JFT |
361 | MICB_1_VAL_MICB_OUT_VAL_MASK, |
| 362 | MICB_VOLTAGE_REGVAL(wcd->micbias_mv)); | |
| e269998d SK |
363 | /* |
| 364 | * Special headset needs MICBIAS as 2.7V so wait for | |
| 365 | * 50 msec for the MICBIAS to reach 2.7 volts. | |
| 366 | */ | |
| 367 | if (wcd->micbias_mv >= 2700) | |
| 368 | msleep(50); | |
| 369 | } | |
| 370 | ||
| 732ae454 | 371 | snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, |
| 585e881e SK |
372 | MICB_1_CTL_EXT_PRECHARG_EN_MASK | |
| 373 | MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0); | |
| 374 | ||
| 375 | } | |
| 376 | ||
| 65fe457e SG |
377 | static int pm8916_wcd_analog_enable_micbias(struct snd_soc_component *component, |
| 378 | int event, unsigned int cap_mode) | |
| 585e881e SK |
379 | { |
| 380 | switch (event) { | |
| 381 | case SND_SOC_DAPM_POST_PMU: | |
| 732ae454 KM |
382 | pm8916_wcd_analog_micbias_enable(component); |
| 383 | snd_soc_component_update_bits(component, CDC_A_MICB_1_EN, | |
| 585e881e SK |
384 | MICB_1_EN_BYP_CAP_MASK, cap_mode); |
| 385 | break; | |
| 386 | } | |
| 387 | ||
| 388 | return 0; | |
| 389 | } | |
| 390 | ||
| 65fe457e SG |
391 | static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_dapm_widget *w, |
| 392 | struct snd_kcontrol *kcontrol, | |
| 393 | int event) | |
| 585e881e | 394 | { |
| 65fe457e | 395 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
| 585e881e SK |
396 | |
| 397 | switch (event) { | |
| 398 | case SND_SOC_DAPM_PRE_PMU: | |
| 732ae454 | 399 | snd_soc_component_update_bits(component, CDC_A_MICB_1_EN, |
| 585e881e SK |
400 | MICB_1_EN_OPA_STG2_TAIL_CURR_MASK, |
| 401 | MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA); | |
| 585e881e SK |
402 | break; |
| 403 | } | |
| 404 | ||
| 405 | return 0; | |
| 406 | } | |
| 407 | ||
| 65fe457e SG |
408 | static int pm8916_wcd_analog_enable_micbias1(struct snd_soc_dapm_widget *w, |
| 409 | struct snd_kcontrol *kcontrol, | |
| 410 | int event) | |
| 585e881e | 411 | { |
| 732ae454 KM |
412 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
| 413 | struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); | |
| 585e881e | 414 | |
| 65fe457e SG |
415 | return pm8916_wcd_analog_enable_micbias(component, event, |
| 416 | wcd->micbias1_cap_mode); | |
| 585e881e SK |
417 | } |
| 418 | ||
| 65fe457e SG |
419 | static int pm8916_wcd_analog_enable_micbias2(struct snd_soc_dapm_widget *w, |
| 420 | struct snd_kcontrol *kcontrol, | |
| 421 | int event) | |
| 585e881e | 422 | { |
| 732ae454 KM |
423 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
| 424 | struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); | |
| 585e881e | 425 | |
| 65fe457e SG |
426 | return pm8916_wcd_analog_enable_micbias(component, event, |
| 427 | wcd->micbias2_cap_mode); | |
| 057efcf9 | 428 | |
| 585e881e SK |
429 | } |
| 430 | ||
| de66b345 SK |
431 | static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv, |
| 432 | bool micbias2_enabled) | |
| 433 | { | |
| 732ae454 | 434 | struct snd_soc_component *component = priv->component; |
| de66b345 SK |
435 | u32 coarse, fine, reg_val, reg_addr; |
| 436 | int *vrefs, i; | |
| 437 | ||
| 438 | if (!micbias2_enabled) { /* use internal 100uA Current source */ | |
| 439 | /* Enable internal 2.2k Internal Rbias Resistor */ | |
| 732ae454 | 440 | snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS, |
| de66b345 SK |
441 | MICB_1_INT_TX2_INT_RBIAS_EN_MASK, |
| 442 | MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE); | |
| 443 | /* Remove pull down on MIC BIAS2 */ | |
| 732ae454 | 444 | snd_soc_component_update_bits(component, CDC_A_MICB_2_EN, |
| de66b345 SK |
445 | CDC_A_MICB_2_PULL_DOWN_EN_MASK, |
| 446 | 0); | |
| 447 | /* enable 100uA internal current source */ | |
| 732ae454 | 448 | snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL, |
| de66b345 SK |
449 | CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK, |
| 450 | CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA); | |
| 451 | } | |
| 732ae454 | 452 | snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL, |
| de66b345 SK |
453 | CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK, |
| 454 | CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN); | |
| 455 | ||
| 456 | if (micbias2_enabled) | |
| 457 | vrefs = &priv->vref_btn_micb[0]; | |
| 458 | else | |
| 459 | vrefs = &priv->vref_btn_cs[0]; | |
| 460 | ||
| 461 | /* program vref ranges for all the buttons */ | |
| 462 | reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0; | |
| 463 | for (i = 0; i < MBHC_MAX_BUTTONS; i++) { | |
| 464 | /* split mv in to coarse parts of 100mv & fine parts of 12mv */ | |
| 465 | coarse = (vrefs[i] / 100); | |
| 466 | fine = ((vrefs[i] % 100) / 12); | |
| 467 | reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) | | |
| 468 | (fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT); | |
| 732ae454 | 469 | snd_soc_component_update_bits(component, reg_addr, |
| de66b345 SK |
470 | CDC_A_MBHC_BTN_VREF_MASK, |
| 471 | reg_val); | |
| 472 | reg_addr++; | |
| 473 | } | |
| 474 | ||
| 475 | return 0; | |
| 476 | } | |
| 477 | ||
| 79f01fe6 DR |
478 | static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd) |
| 479 | { | |
| 732ae454 | 480 | struct snd_soc_component *component = wcd->component; |
| 79f01fe6 DR |
481 | bool micbias_enabled = false; |
| 482 | u32 plug_type = 0; | |
| 483 | u32 int_en_mask; | |
| 484 | ||
| 732ae454 | 485 | snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_1, |
| 79f01fe6 DR |
486 | CDC_A_MBHC_DET_CTL_L_DET_EN | |
| 487 | CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION | | |
| 488 | CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO | | |
| 489 | CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN); | |
| 490 | ||
| 491 | if (wcd->hphl_jack_type_normally_open) | |
| 492 | plug_type |= CDC_A_HPHL_PLUG_TYPE_NO; | |
| 493 | ||
| 494 | if (wcd->gnd_jack_type_normally_open) | |
| 495 | plug_type |= CDC_A_GND_PLUG_TYPE_NO; | |
| 496 | ||
| 732ae454 | 497 | snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_2, |
| 79f01fe6 DR |
498 | CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 | |
| 499 | CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD | | |
| 500 | plug_type | | |
| 501 | CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN); | |
| 502 | ||
| 503 | ||
| 732ae454 | 504 | snd_soc_component_write(component, CDC_A_MBHC_DBNC_TIMER, |
| 79f01fe6 DR |
505 | CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS | |
| 506 | CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS); | |
| 507 | ||
| 508 | /* enable MBHC clock */ | |
| 732ae454 | 509 | snd_soc_component_update_bits(component, CDC_D_CDC_DIG_CLK_CTL, |
| 79f01fe6 DR |
510 | DIG_CLK_CTL_D_MBHC_CLK_EN_MASK, |
| 511 | DIG_CLK_CTL_D_MBHC_CLK_EN); | |
| 512 | ||
| a6f80d99 | 513 | if (snd_soc_component_read(component, CDC_A_MICB_2_EN) & CDC_A_MICB_2_EN_ENABLE) |
| 79f01fe6 DR |
514 | micbias_enabled = true; |
| 515 | ||
| 516 | pm8916_mbhc_configure_bias(wcd, micbias_enabled); | |
| 517 | ||
| 518 | int_en_mask = MBHC_SWITCH_INT; | |
| 519 | if (wcd->mbhc_btn_enabled) | |
| 520 | int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET; | |
| 521 | ||
| 732ae454 KM |
522 | snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0); |
| 523 | snd_soc_component_update_bits(component, CDC_D_INT_EN_SET, int_en_mask, int_en_mask); | |
| 79f01fe6 DR |
524 | wcd->mbhc_btn0_released = false; |
| 525 | wcd->detect_accessory_type = true; | |
| 526 | } | |
| 527 | ||
| b4f89a0c | 528 | static int pm8916_wcd_analog_enable_micbias_int2(struct |
| 585e881e SK |
529 | snd_soc_dapm_widget |
| 530 | *w, struct snd_kcontrol | |
| 531 | *kcontrol, int event) | |
| 532 | { | |
| 732ae454 KM |
533 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
| 534 | struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); | |
| 585e881e | 535 | |
| de66b345 | 536 | switch (event) { |
| 057efcf9 | 537 | case SND_SOC_DAPM_PRE_PMU: |
| 65fe457e SG |
538 | snd_soc_component_update_bits(component, CDC_A_MICB_2_EN, |
| 539 | CDC_A_MICB_2_PULL_DOWN_EN_MASK, 0); | |
| 057efcf9 | 540 | break; |
| de66b345 SK |
541 | case SND_SOC_DAPM_POST_PMU: |
| 542 | pm8916_mbhc_configure_bias(wcd, true); | |
| 543 | break; | |
| 544 | case SND_SOC_DAPM_POST_PMD: | |
| 545 | pm8916_mbhc_configure_bias(wcd, false); | |
| 546 | break; | |
| 547 | } | |
| 548 | ||
| 65fe457e | 549 | return pm8916_wcd_analog_enable_micbias_int(w, kcontrol, event); |
| 585e881e SK |
550 | } |
| 551 | ||
| 552 | static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w, | |
| 553 | struct snd_kcontrol *kcontrol, | |
| 554 | int event) | |
| 555 | { | |
| 732ae454 | 556 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
| 585e881e SK |
557 | u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2; |
| 558 | u8 init_bit_shift; | |
| 559 | ||
| 560 | if (w->reg == CDC_A_TX_1_EN) | |
| 561 | init_bit_shift = 5; | |
| 562 | else | |
| 563 | init_bit_shift = 4; | |
| 564 | ||
| 565 | switch (event) { | |
| 566 | case SND_SOC_DAPM_PRE_PMU: | |
| 567 | if (w->reg == CDC_A_TX_2_EN) | |
| 732ae454 | 568 | snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, |
| 585e881e SK |
569 | MICB_1_CTL_CFILT_REF_SEL_MASK, |
| 570 | MICB_1_CTL_CFILT_REF_SEL_HPF_REF); | |
| 571 | /* | |
| 572 | * Add delay of 10 ms to give sufficient time for the voltage | |
| 573 | * to shoot up and settle so that the txfe init does not | |
| 574 | * happen when the input voltage is changing too much. | |
| 575 | */ | |
| 576 | usleep_range(10000, 10010); | |
| 732ae454 | 577 | snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, |
| 585e881e SK |
578 | 1 << init_bit_shift); |
| 579 | switch (w->reg) { | |
| 580 | case CDC_A_TX_1_EN: | |
| 732ae454 | 581 | snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL, |
| 585e881e SK |
582 | CONN_TX1_SERIAL_TX1_MUX, |
| 583 | CONN_TX1_SERIAL_TX1_ADC_1); | |
| 584 | break; | |
| 585 | case CDC_A_TX_2_EN: | |
| 586 | case CDC_A_TX_3_EN: | |
| 732ae454 | 587 | snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL, |
| 585e881e SK |
588 | CONN_TX2_SERIAL_TX2_MUX, |
| 589 | CONN_TX2_SERIAL_TX2_ADC_2); | |
| 590 | break; | |
| 591 | } | |
| 592 | break; | |
| 593 | case SND_SOC_DAPM_POST_PMU: | |
| 594 | /* | |
| 595 | * Add delay of 12 ms before deasserting the init | |
| 596 | * to reduce the tx pop | |
| 597 | */ | |
| 598 | usleep_range(12000, 12010); | |
| 732ae454 | 599 | snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00); |
| 585e881e SK |
600 | break; |
| 601 | case SND_SOC_DAPM_POST_PMD: | |
| 602 | switch (w->reg) { | |
| 603 | case CDC_A_TX_1_EN: | |
| 732ae454 | 604 | snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL, |
| 585e881e SK |
605 | CONN_TX1_SERIAL_TX1_MUX, |
| 606 | CONN_TX1_SERIAL_TX1_ZERO); | |
| 607 | break; | |
| 608 | case CDC_A_TX_2_EN: | |
| 732ae454 | 609 | snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, |
| 585e881e | 610 | MICB_1_CTL_CFILT_REF_SEL_MASK, 0); |
| 3e146b55 | 611 | fallthrough; |
| 585e881e | 612 | case CDC_A_TX_3_EN: |
| 732ae454 | 613 | snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL, |
| 585e881e SK |
614 | CONN_TX2_SERIAL_TX2_MUX, |
| 615 | CONN_TX2_SERIAL_TX2_ZERO); | |
| 616 | break; | |
| 617 | } | |
| 618 | ||
| 619 | ||
| 620 | break; | |
| 621 | } | |
| 622 | return 0; | |
| 623 | } | |
| 624 | ||
| 625 | static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w, | |
| 626 | struct snd_kcontrol *kcontrol, | |
| 627 | int event) | |
| 628 | { | |
| 732ae454 | 629 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
| 585e881e SK |
630 | |
| 631 | switch (event) { | |
| 632 | case SND_SOC_DAPM_PRE_PMU: | |
| 732ae454 | 633 | snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL, |
| 585e881e SK |
634 | SPKR_PWRSTG_CTL_DAC_EN_MASK | |
| 635 | SPKR_PWRSTG_CTL_BBM_MASK | | |
| 636 | SPKR_PWRSTG_CTL_HBRDGE_EN_MASK | | |
| 637 | SPKR_PWRSTG_CTL_CLAMP_EN_MASK, | |
| 638 | SPKR_PWRSTG_CTL_DAC_EN| | |
| 639 | SPKR_PWRSTG_CTL_BBM_EN | | |
| 640 | SPKR_PWRSTG_CTL_HBRDGE_EN | | |
| 641 | SPKR_PWRSTG_CTL_CLAMP_EN); | |
| 642 | ||
| 732ae454 | 643 | snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, |
| 585e881e SK |
644 | RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, |
| 645 | RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE); | |
| 646 | break; | |
| 647 | case SND_SOC_DAPM_POST_PMU: | |
| 732ae454 | 648 | snd_soc_component_update_bits(component, CDC_A_SPKR_DRV_CTL, |
| 585e881e SK |
649 | SPKR_DRV_CTL_DEF_MASK, |
| 650 | SPKR_DRV_CTL_DEF_VAL); | |
| 732ae454 | 651 | snd_soc_component_update_bits(component, w->reg, |
| 585e881e SK |
652 | SPKR_DRV_CLASSD_PA_EN_MASK, |
| 653 | SPKR_DRV_CLASSD_PA_EN_ENABLE); | |
| 654 | break; | |
| 655 | case SND_SOC_DAPM_POST_PMD: | |
| 732ae454 | 656 | snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL, |
| 585e881e SK |
657 | SPKR_PWRSTG_CTL_DAC_EN_MASK| |
| 658 | SPKR_PWRSTG_CTL_BBM_MASK | | |
| 659 | SPKR_PWRSTG_CTL_HBRDGE_EN_MASK | | |
| 660 | SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0); | |
| 661 | ||
| 732ae454 | 662 | snd_soc_component_update_bits(component, CDC_A_SPKR_DAC_CTL, |
| 585e881e SK |
663 | SPKR_DAC_CTL_DAC_RESET_MASK, |
| 664 | SPKR_DAC_CTL_DAC_RESET_NORMAL); | |
| 732ae454 | 665 | snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, |
| 585e881e SK |
666 | RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0); |
| 667 | break; | |
| 668 | } | |
| 669 | return 0; | |
| 670 | } | |
| 671 | ||
| 7d2f70f2 SG |
672 | static int pm8916_wcd_analog_enable_ear_pa(struct snd_soc_dapm_widget *w, |
| 673 | struct snd_kcontrol *kcontrol, | |
| 674 | int event) | |
| 675 | { | |
| 676 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); | |
| 677 | ||
| 678 | switch (event) { | |
| 679 | case SND_SOC_DAPM_PRE_PMU: | |
| 680 | snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, | |
| 681 | RX_EAR_CTL_PA_SEL_MASK, RX_EAR_CTL_PA_SEL); | |
| 682 | break; | |
| 683 | case SND_SOC_DAPM_POST_PMU: | |
| 684 | snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, | |
| 685 | RX_EAR_CTL_PA_EAR_PA_EN_MASK, | |
| 686 | RX_EAR_CTL_PA_EAR_PA_EN_ENABLE); | |
| 687 | break; | |
| 688 | case SND_SOC_DAPM_POST_PMD: | |
| 689 | snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, | |
| 690 | RX_EAR_CTL_PA_EAR_PA_EN_MASK, 0); | |
| 691 | /* Delay to reduce ear turn off pop */ | |
| 692 | usleep_range(7000, 7100); | |
| 693 | snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, | |
| 694 | RX_EAR_CTL_PA_SEL_MASK, 0); | |
| 695 | break; | |
| 696 | } | |
| 697 | return 0; | |
| 698 | } | |
| 699 | ||
| 585e881e SK |
700 | static const struct reg_default wcd_reg_defaults_2_0[] = { |
| 701 | {CDC_A_RX_COM_OCP_CTL, 0xD1}, | |
| 702 | {CDC_A_RX_COM_OCP_COUNT, 0xFF}, | |
| 703 | {CDC_D_SEC_ACCESS, 0xA5}, | |
| 704 | {CDC_D_PERPH_RESET_CTL3, 0x0F}, | |
| 705 | {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F}, | |
| 706 | {CDC_A_NCP_FBCTRL, 0x28}, | |
| 707 | {CDC_A_SPKR_DRV_CTL, 0x69}, | |
| 708 | {CDC_A_SPKR_DRV_DBG, 0x01}, | |
| 709 | {CDC_A_BOOST_EN_CTL, 0x5F}, | |
| 710 | {CDC_A_SLOPE_COMP_IP_ZERO, 0x88}, | |
| 711 | {CDC_A_SEC_ACCESS, 0xA5}, | |
| 712 | {CDC_A_PERPH_RESET_CTL3, 0x0F}, | |
| 713 | {CDC_A_CURRENT_LIMIT, 0x82}, | |
| 714 | {CDC_A_SPKR_DAC_CTL, 0x03}, | |
| 715 | {CDC_A_SPKR_OCP_CTL, 0xE1}, | |
| 716 | {CDC_A_MASTER_BIAS_CTL, 0x30}, | |
| 717 | }; | |
| 718 | ||
| 732ae454 | 719 | static int pm8916_wcd_analog_probe(struct snd_soc_component *component) |
| 585e881e | 720 | { |
| 732ae454 | 721 | struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev); |
| 585e881e SK |
722 | int err, reg; |
| 723 | ||
| 724 | err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); | |
| 725 | if (err != 0) { | |
| 732ae454 | 726 | dev_err(component->dev, "failed to enable regulators (%d)\n", err); |
| 585e881e SK |
727 | return err; |
| 728 | } | |
| 729 | ||
| 732ae454 KM |
730 | snd_soc_component_init_regmap(component, |
| 731 | dev_get_regmap(component->dev->parent, NULL)); | |
| 732 | snd_soc_component_set_drvdata(component, priv); | |
| a6f80d99 KM |
733 | priv->pmic_rev = snd_soc_component_read(component, CDC_D_REVISION1); |
| 734 | priv->codec_version = snd_soc_component_read(component, CDC_D_PERPH_SUBTYPE); | |
| 585e881e | 735 | |
| 732ae454 | 736 | dev_info(component->dev, "PMIC REV: %d\t CODEC Version: %d\n", |
| 585e881e SK |
737 | priv->pmic_rev, priv->codec_version); |
| 738 | ||
| 732ae454 KM |
739 | snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01); |
| 740 | snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01); | |
| 585e881e SK |
741 | |
| 742 | for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++) | |
| 732ae454 | 743 | snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg, |
| 585e881e SK |
744 | wcd_reg_defaults_2_0[reg].def); |
| 745 | ||
| 732ae454 | 746 | priv->component = component; |
| de66b345 | 747 | |
| 732ae454 | 748 | snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL, |
| 52981e29 SK |
749 | RST_CTL_DIG_SW_RST_N_MASK, |
| 750 | RST_CTL_DIG_SW_RST_N_REMOVE_RESET); | |
| de66b345 SK |
751 | |
| 752 | pm8916_wcd_setup_mbhc(priv); | |
| 753 | ||
| 585e881e SK |
754 | return 0; |
| 755 | } | |
| 756 | ||
| 732ae454 | 757 | static void pm8916_wcd_analog_remove(struct snd_soc_component *component) |
| 585e881e | 758 | { |
| 732ae454 | 759 | struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev); |
| 585e881e | 760 | |
| 732ae454 | 761 | snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL, |
| 52981e29 SK |
762 | RST_CTL_DIG_SW_RST_N_MASK, 0); |
| 763 | ||
| 732ae454 | 764 | regulator_bulk_disable(ARRAY_SIZE(priv->supplies), |
| 585e881e SK |
765 | priv->supplies); |
| 766 | } | |
| 767 | ||
| 768 | static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = { | |
| 769 | ||
| 770 | {"PDM_RX1", NULL, "PDM Playback"}, | |
| 771 | {"PDM_RX2", NULL, "PDM Playback"}, | |
| 772 | {"PDM_RX3", NULL, "PDM Playback"}, | |
| 773 | {"PDM Capture", NULL, "PDM_TX"}, | |
| 774 | ||
| 775 | /* ADC Connections */ | |
| 776 | {"PDM_TX", NULL, "ADC2"}, | |
| 777 | {"PDM_TX", NULL, "ADC3"}, | |
| 778 | {"ADC2", NULL, "ADC2 MUX"}, | |
| 779 | {"ADC3", NULL, "ADC2 MUX"}, | |
| 780 | {"ADC2 MUX", "INP2", "ADC2_INP2"}, | |
| 781 | {"ADC2 MUX", "INP3", "ADC2_INP3"}, | |
| 782 | ||
| 783 | {"PDM_TX", NULL, "ADC1"}, | |
| 784 | {"ADC1", NULL, "AMIC1"}, | |
| 785 | {"ADC2_INP2", NULL, "AMIC2"}, | |
| 786 | {"ADC2_INP3", NULL, "AMIC3"}, | |
| 787 | ||
| 788 | /* RDAC Connections */ | |
| 789 | {"HPHR DAC", NULL, "RDAC2 MUX"}, | |
| 790 | {"RDAC2 MUX", "RX1", "PDM_RX1"}, | |
| 791 | {"RDAC2 MUX", "RX2", "PDM_RX2"}, | |
| 792 | {"HPHL DAC", NULL, "PDM_RX1"}, | |
| 793 | {"PDM_RX1", NULL, "RXD1_CLK"}, | |
| 794 | {"PDM_RX2", NULL, "RXD2_CLK"}, | |
| 795 | {"PDM_RX3", NULL, "RXD3_CLK"}, | |
| 796 | ||
| 797 | {"PDM_RX1", NULL, "RXD_PDM_CLK"}, | |
| 798 | {"PDM_RX2", NULL, "RXD_PDM_CLK"}, | |
| 799 | {"PDM_RX3", NULL, "RXD_PDM_CLK"}, | |
| 800 | ||
| 801 | {"ADC1", NULL, "TXD_CLK"}, | |
| 802 | {"ADC2", NULL, "TXD_CLK"}, | |
| 803 | {"ADC3", NULL, "TXD_CLK"}, | |
| 804 | ||
| 805 | {"ADC1", NULL, "TXA_CLK25"}, | |
| 806 | {"ADC2", NULL, "TXA_CLK25"}, | |
| 807 | {"ADC3", NULL, "TXA_CLK25"}, | |
| 808 | ||
| 809 | {"PDM_RX1", NULL, "A_MCLK2"}, | |
| 810 | {"PDM_RX2", NULL, "A_MCLK2"}, | |
| 811 | {"PDM_RX3", NULL, "A_MCLK2"}, | |
| 812 | ||
| 813 | {"PDM_TX", NULL, "A_MCLK2"}, | |
| 814 | {"A_MCLK2", NULL, "A_MCLK"}, | |
| 815 | ||
| 7d2f70f2 SG |
816 | /* Earpiece (RX MIX1) */ |
| 817 | {"EAR", NULL, "EAR_S"}, | |
| 818 | {"EAR_S", "Switch", "EAR PA"}, | |
| 819 | {"EAR PA", NULL, "RX_BIAS"}, | |
| 820 | {"EAR PA", NULL, "HPHL DAC"}, | |
| 821 | {"EAR PA", NULL, "HPHR DAC"}, | |
| 822 | {"EAR PA", NULL, "EAR CP"}, | |
| 823 | ||
| 585e881e SK |
824 | /* Headset (RX MIX1 and RX MIX2) */ |
| 825 | {"HEADPHONE", NULL, "HPHL PA"}, | |
| 826 | {"HEADPHONE", NULL, "HPHR PA"}, | |
| 827 | ||
| 7d2f70f2 SG |
828 | {"HPHL DAC", NULL, "EAR_HPHL_CLK"}, |
| 829 | {"HPHR DAC", NULL, "EAR_HPHR_CLK"}, | |
| 585e881e SK |
830 | |
| 831 | {"CP", NULL, "NCP_CLK"}, | |
| 832 | ||
| 833 | {"HPHL PA", NULL, "HPHL"}, | |
| 834 | {"HPHR PA", NULL, "HPHR"}, | |
| 835 | {"HPHL PA", NULL, "CP"}, | |
| 836 | {"HPHL PA", NULL, "RX_BIAS"}, | |
| 837 | {"HPHR PA", NULL, "CP"}, | |
| 838 | {"HPHR PA", NULL, "RX_BIAS"}, | |
| 839 | {"HPHL", "Switch", "HPHL DAC"}, | |
| 840 | {"HPHR", "Switch", "HPHR DAC"}, | |
| 841 | ||
| 842 | {"RX_BIAS", NULL, "DAC_REF"}, | |
| 843 | ||
| 844 | {"SPK_OUT", NULL, "SPK PA"}, | |
| 845 | {"SPK PA", NULL, "RX_BIAS"}, | |
| 846 | {"SPK PA", NULL, "SPKR_CLK"}, | |
| 847 | {"SPK PA", NULL, "SPK DAC"}, | |
| 848 | {"SPK DAC", "Switch", "PDM_RX3"}, | |
| 849 | ||
| 65fe457e SG |
850 | {"MIC_BIAS1", NULL, "INT_LDO_H"}, |
| 851 | {"MIC_BIAS2", NULL, "INT_LDO_H"}, | |
| 852 | {"MIC_BIAS1", NULL, "vdd-micbias"}, | |
| 853 | {"MIC_BIAS2", NULL, "vdd-micbias"}, | |
| 854 | ||
| 855 | {"MIC BIAS External1", NULL, "MIC_BIAS1"}, | |
| 856 | {"MIC BIAS Internal1", NULL, "MIC_BIAS1"}, | |
| 857 | {"MIC BIAS External2", NULL, "MIC_BIAS2"}, | |
| 858 | {"MIC BIAS Internal2", NULL, "MIC_BIAS2"}, | |
| 00d85232 | 859 | {"MIC BIAS Internal3", NULL, "MIC_BIAS1"}, |
| 585e881e SK |
860 | }; |
| 861 | ||
| 862 | static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = { | |
| 863 | ||
| 864 | SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0), | |
| 865 | SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0), | |
| 866 | SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0), | |
| 867 | SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0), | |
| 868 | ||
| 869 | SND_SOC_DAPM_INPUT("AMIC1"), | |
| 870 | SND_SOC_DAPM_INPUT("AMIC3"), | |
| 871 | SND_SOC_DAPM_INPUT("AMIC2"), | |
| 7d2f70f2 | 872 | SND_SOC_DAPM_OUTPUT("EAR"), |
| 585e881e SK |
873 | SND_SOC_DAPM_OUTPUT("HEADPHONE"), |
| 874 | ||
| 875 | /* RX stuff */ | |
| 876 | SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0), | |
| 877 | ||
| 7d2f70f2 SG |
878 | SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM, |
| 879 | 0, 0, NULL, 0, | |
| 880 | pm8916_wcd_analog_enable_ear_pa, | |
| 881 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
| 882 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
| 883 | SND_SOC_DAPM_MUX("EAR_S", SND_SOC_NOPM, 0, 0, &ear_mux), | |
| 884 | SND_SOC_DAPM_SUPPLY("EAR CP", CDC_A_NCP_EN, 4, 0, NULL, 0), | |
| 885 | ||
| 585e881e SK |
886 | SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0), |
| 887 | SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux), | |
| 888 | SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL, | |
| 889 | 0), | |
| 890 | SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0), | |
| 891 | SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux), | |
| 892 | SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL, | |
| 893 | 0), | |
| 894 | SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0, | |
| 895 | spkr_switch, ARRAY_SIZE(spkr_switch)), | |
| 896 | ||
| 897 | /* Speaker */ | |
| 898 | SND_SOC_DAPM_OUTPUT("SPK_OUT"), | |
| 899 | SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL, | |
| 900 | 6, 0, NULL, 0, | |
| 901 | pm8916_wcd_analog_enable_spk_pa, | |
| 902 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
| 903 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
| 904 | SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0), | |
| 905 | SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0), | |
| 906 | ||
| 907 | SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0), | |
| 908 | SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0), | |
| 909 | ||
| 910 | /* TX */ | |
| 65fe457e SG |
911 | SND_SOC_DAPM_SUPPLY("MIC_BIAS1", CDC_A_MICB_1_EN, 7, 0, |
| 912 | pm8916_wcd_analog_enable_micbias1, | |
| 913 | SND_SOC_DAPM_POST_PMU), | |
| 914 | SND_SOC_DAPM_SUPPLY("MIC_BIAS2", CDC_A_MICB_2_EN, 7, 0, | |
| 915 | pm8916_wcd_analog_enable_micbias2, | |
| 916 | SND_SOC_DAPM_POST_PMU), | |
| 917 | ||
| 918 | SND_SOC_DAPM_SUPPLY("MIC BIAS External1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
| 919 | SND_SOC_DAPM_SUPPLY("MIC BIAS External2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
| 920 | ||
| 921 | SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_INT_RBIAS, 7, 0, | |
| 922 | pm8916_wcd_analog_enable_micbias_int, | |
| 923 | SND_SOC_DAPM_PRE_PMU), | |
| 924 | SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_1_INT_RBIAS, 4, 0, | |
| 585e881e SK |
925 | pm8916_wcd_analog_enable_micbias_int2, |
| 926 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
| 927 | SND_SOC_DAPM_POST_PMD), | |
| 00d85232 SG |
928 | SND_SOC_DAPM_SUPPLY("MIC BIAS Internal3", CDC_A_MICB_1_INT_RBIAS, 1, 0, |
| 929 | pm8916_wcd_analog_enable_micbias_int, | |
| 930 | SND_SOC_DAPM_PRE_PMU), | |
| 585e881e | 931 | |
| 585e881e SK |
932 | SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0, |
| 933 | pm8916_wcd_analog_enable_adc, | |
| 934 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
| 935 | SND_SOC_DAPM_POST_PMD), | |
| 936 | SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0, | |
| 937 | pm8916_wcd_analog_enable_adc, | |
| 938 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
| 939 | SND_SOC_DAPM_POST_PMD), | |
| 940 | SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0, | |
| 941 | pm8916_wcd_analog_enable_adc, | |
| 942 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
| 943 | SND_SOC_DAPM_POST_PMD), | |
| 944 | ||
| 945 | SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
| 946 | SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), | |
| 947 | ||
| 948 | SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), | |
| 949 | SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux), | |
| 950 | ||
| 951 | /* Analog path clocks */ | |
| 952 | SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL, | |
| 953 | 0), | |
| 954 | SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL, | |
| 955 | 0), | |
| 956 | SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0), | |
| 957 | SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0), | |
| 958 | ||
| 959 | /* Digital path clocks */ | |
| 960 | ||
| 961 | SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0), | |
| 962 | SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0), | |
| 963 | SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0), | |
| 964 | ||
| 965 | SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0), | |
| 966 | SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0), | |
| 967 | SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL, | |
| 968 | 0), | |
| 969 | ||
| 970 | /* System Clock source */ | |
| 971 | SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0), | |
| 972 | /* TX ADC and RX DAC Clock source. */ | |
| 973 | SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0), | |
| 974 | }; | |
| 975 | ||
| 732ae454 | 976 | static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component, |
| de66b345 SK |
977 | struct snd_soc_jack *jack, |
| 978 | void *data) | |
| 979 | { | |
| 732ae454 | 980 | struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); |
| de66b345 SK |
981 | |
| 982 | wcd->jack = jack; | |
| 983 | ||
| 984 | return 0; | |
| 985 | } | |
| 986 | ||
| de66b345 SK |
987 | static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg) |
| 988 | { | |
| 989 | struct pm8916_wcd_analog_priv *priv = arg; | |
| 990 | ||
| 991 | if (priv->detect_accessory_type) { | |
| 732ae454 | 992 | struct snd_soc_component *component = priv->component; |
| a6f80d99 | 993 | u32 val = snd_soc_component_read(component, CDC_A_MBHC_RESULT_1); |
| de66b345 SK |
994 | |
| 995 | /* check if its BTN0 thats released */ | |
| 56026714 | 996 | if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK)) |
| d430a7e3 | 997 | priv->mbhc_btn0_released = true; |
| de66b345 SK |
998 | |
| 999 | } else { | |
| 1000 | snd_soc_jack_report(priv->jack, 0, btn_mask); | |
| 1001 | } | |
| 1002 | ||
| 1003 | return IRQ_HANDLED; | |
| 1004 | } | |
| 1005 | ||
| 1006 | static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg) | |
| 1007 | { | |
| 1008 | struct pm8916_wcd_analog_priv *priv = arg; | |
| 732ae454 | 1009 | struct snd_soc_component *component = priv->component; |
| de66b345 SK |
1010 | u32 btn_result; |
| 1011 | ||
| a6f80d99 | 1012 | btn_result = snd_soc_component_read(component, CDC_A_MBHC_RESULT_1) & |
| de66b345 SK |
1013 | CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK; |
| 1014 | ||
| 1015 | switch (btn_result) { | |
| 1016 | case 0xf: | |
| 1017 | snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask); | |
| 1018 | break; | |
| 1019 | case 0x7: | |
| 1020 | snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask); | |
| 1021 | break; | |
| 1022 | case 0x3: | |
| 1023 | snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask); | |
| 1024 | break; | |
| 1025 | case 0x1: | |
| 1026 | snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask); | |
| 1027 | break; | |
| 1028 | case 0x0: | |
| 1029 | /* handle BTN_0 specially for type detection */ | |
| d430a7e3 | 1030 | if (!priv->detect_accessory_type) |
| de66b345 SK |
1031 | snd_soc_jack_report(priv->jack, |
| 1032 | SND_JACK_BTN_0, btn_mask); | |
| 1033 | break; | |
| 1034 | default: | |
| 732ae454 | 1035 | dev_err(component->dev, |
| de66b345 SK |
1036 | "Unexpected button press result (%x)", btn_result); |
| 1037 | break; | |
| 1038 | } | |
| 1039 | ||
| 1040 | return IRQ_HANDLED; | |
| 1041 | } | |
| 1042 | ||
| de66b345 SK |
1043 | static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg) |
| 1044 | { | |
| 1045 | struct pm8916_wcd_analog_priv *priv = arg; | |
| 732ae454 | 1046 | struct snd_soc_component *component = priv->component; |
| de66b345 SK |
1047 | bool ins = false; |
| 1048 | ||
| a6f80d99 | 1049 | if (snd_soc_component_read(component, CDC_A_MBHC_DET_CTL_1) & |
| de66b345 SK |
1050 | CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK) |
| 1051 | ins = true; | |
| 1052 | ||
| 1053 | /* Set the detection type appropriately */ | |
| 732ae454 | 1054 | snd_soc_component_update_bits(component, CDC_A_MBHC_DET_CTL_1, |
| de66b345 SK |
1055 | CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK, |
| 1056 | (!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT)); | |
| 1057 | ||
| 1058 | ||
| 1059 | if (ins) { /* hs insertion */ | |
| 1060 | bool micbias_enabled = false; | |
| 1061 | ||
| a6f80d99 | 1062 | if (snd_soc_component_read(component, CDC_A_MICB_2_EN) & |
| de66b345 SK |
1063 | CDC_A_MICB_2_EN_ENABLE) |
| 1064 | micbias_enabled = true; | |
| 1065 | ||
| 1066 | pm8916_mbhc_configure_bias(priv, micbias_enabled); | |
| 1067 | ||
| 1068 | /* | |
| 1069 | * if only a btn0 press event is receive just before | |
| 1070 | * insert event then its a 3 pole headphone else if | |
| 1071 | * both press and release event received then its | |
| 1072 | * a headset. | |
| 1073 | */ | |
| d430a7e3 | 1074 | if (priv->mbhc_btn0_released) |
| de66b345 | 1075 | snd_soc_jack_report(priv->jack, |
| d430a7e3 | 1076 | SND_JACK_HEADSET, hs_jack_mask); |
| de66b345 SK |
1077 | else |
| 1078 | snd_soc_jack_report(priv->jack, | |
| d430a7e3 | 1079 | SND_JACK_HEADPHONE, hs_jack_mask); |
| de66b345 SK |
1080 | |
| 1081 | priv->detect_accessory_type = false; | |
| 1082 | ||
| 1083 | } else { /* removal */ | |
| 1084 | snd_soc_jack_report(priv->jack, 0, hs_jack_mask); | |
| 1085 | priv->detect_accessory_type = true; | |
| d430a7e3 | 1086 | priv->mbhc_btn0_released = false; |
| de66b345 SK |
1087 | } |
| 1088 | ||
| 1089 | return IRQ_HANDLED; | |
| 1090 | } | |
| 1091 | ||
| 585e881e SK |
1092 | static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = { |
| 1093 | [0] = { | |
| 1094 | .name = "pm8916_wcd_analog_pdm_rx", | |
| 1095 | .id = 0, | |
| 1096 | .playback = { | |
| 1097 | .stream_name = "PDM Playback", | |
| 1098 | .rates = MSM8916_WCD_ANALOG_RATES, | |
| 1099 | .formats = MSM8916_WCD_ANALOG_FORMATS, | |
| 1100 | .channels_min = 1, | |
| 1101 | .channels_max = 3, | |
| 1102 | }, | |
| 585e881e SK |
1103 | }, |
| 1104 | [1] = { | |
| 1105 | .name = "pm8916_wcd_analog_pdm_tx", | |
| 1106 | .id = 1, | |
| 1107 | .capture = { | |
| 1108 | .stream_name = "PDM Capture", | |
| 1109 | .rates = MSM8916_WCD_ANALOG_RATES, | |
| 1110 | .formats = MSM8916_WCD_ANALOG_FORMATS, | |
| 1111 | .channels_min = 1, | |
| 1112 | .channels_max = 4, | |
| 1113 | }, | |
| 585e881e SK |
1114 | }, |
| 1115 | }; | |
| 1116 | ||
| 732ae454 KM |
1117 | static const struct snd_soc_component_driver pm8916_wcd_analog = { |
| 1118 | .probe = pm8916_wcd_analog_probe, | |
| 1119 | .remove = pm8916_wcd_analog_remove, | |
| 1120 | .set_jack = pm8916_wcd_analog_set_jack, | |
| 1121 | .controls = pm8916_wcd_analog_snd_controls, | |
| 1122 | .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls), | |
| 1123 | .dapm_widgets = pm8916_wcd_analog_dapm_widgets, | |
| 1124 | .num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets), | |
| 1125 | .dapm_routes = pm8916_wcd_analog_audio_map, | |
| 1126 | .num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map), | |
| 1127 | .idle_bias_on = 1, | |
| 1128 | .use_pmdown_time = 1, | |
| 1129 | .endianness = 1, | |
| 1130 | .non_legacy_dai_naming = 1, | |
| 585e881e SK |
1131 | }; |
| 1132 | ||
| 1133 | static int pm8916_wcd_analog_parse_dt(struct device *dev, | |
| 1134 | struct pm8916_wcd_analog_priv *priv) | |
| 1135 | { | |
| de66b345 | 1136 | int rval; |
| 585e881e SK |
1137 | |
| 1138 | if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap")) | |
| 1139 | priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP; | |
| 1140 | else | |
| 1141 | priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP; | |
| 1142 | ||
| 1143 | if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap")) | |
| 1144 | priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP; | |
| 1145 | else | |
| 1146 | priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP; | |
| 1147 | ||
| e269998d SK |
1148 | of_property_read_u32(dev->of_node, "qcom,micbias-lvl", |
| 1149 | &priv->micbias_mv); | |
| 1150 | ||
| de66b345 SK |
1151 | if (of_property_read_bool(dev->of_node, |
| 1152 | "qcom,hphl-jack-type-normally-open")) | |
| 1153 | priv->hphl_jack_type_normally_open = true; | |
| 1154 | else | |
| 1155 | priv->hphl_jack_type_normally_open = false; | |
| 1156 | ||
| 1157 | if (of_property_read_bool(dev->of_node, | |
| 1158 | "qcom,gnd-jack-type-normally-open")) | |
| 1159 | priv->gnd_jack_type_normally_open = true; | |
| 1160 | else | |
| 1161 | priv->gnd_jack_type_normally_open = false; | |
| 1162 | ||
| 1163 | priv->mbhc_btn_enabled = true; | |
| 1164 | rval = of_property_read_u32_array(dev->of_node, | |
| 1165 | "qcom,mbhc-vthreshold-low", | |
| 1166 | &priv->vref_btn_cs[0], | |
| 1167 | MBHC_MAX_BUTTONS); | |
| 1168 | if (rval < 0) { | |
| 1169 | priv->mbhc_btn_enabled = false; | |
| 1170 | } else { | |
| 1171 | rval = of_property_read_u32_array(dev->of_node, | |
| 1172 | "qcom,mbhc-vthreshold-high", | |
| 1173 | &priv->vref_btn_micb[0], | |
| 1174 | MBHC_MAX_BUTTONS); | |
| 1175 | if (rval < 0) | |
| 1176 | priv->mbhc_btn_enabled = false; | |
| 1177 | } | |
| 1178 | ||
| 1179 | if (!priv->mbhc_btn_enabled) | |
| 1180 | dev_err(dev, | |
| 1181 | "DT property missing, MBHC btn detection disabled\n"); | |
| 1182 | ||
| 1183 | ||
| 585e881e SK |
1184 | return 0; |
| 1185 | } | |
| 1186 | ||
| 1187 | static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev) | |
| 1188 | { | |
| 1189 | struct pm8916_wcd_analog_priv *priv; | |
| 1190 | struct device *dev = &pdev->dev; | |
| de66b345 | 1191 | int ret, i, irq; |
| 585e881e SK |
1192 | |
| 1193 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
| 1194 | if (!priv) | |
| 1195 | return -ENOMEM; | |
| 1196 | ||
| 1197 | ret = pm8916_wcd_analog_parse_dt(dev, priv); | |
| 1198 | if (ret < 0) | |
| 1199 | return ret; | |
| 1200 | ||
| 4323ec25 SK |
1201 | priv->mclk = devm_clk_get(dev, "mclk"); |
| 1202 | if (IS_ERR(priv->mclk)) { | |
| 1203 | dev_err(dev, "failed to get mclk\n"); | |
| 1204 | return PTR_ERR(priv->mclk); | |
| 1205 | } | |
| 1206 | ||
| 1207 | for (i = 0; i < ARRAY_SIZE(supply_names); i++) | |
| 1208 | priv->supplies[i].supply = supply_names[i]; | |
| 1209 | ||
| 1210 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies), | |
| 1211 | priv->supplies); | |
| 1212 | if (ret) { | |
| 1213 | dev_err(dev, "Failed to get regulator supplies %d\n", ret); | |
| 1214 | return ret; | |
| 1215 | } | |
| 1216 | ||
| 585e881e SK |
1217 | ret = clk_prepare_enable(priv->mclk); |
| 1218 | if (ret < 0) { | |
| 1219 | dev_err(dev, "failed to enable mclk %d\n", ret); | |
| 1220 | return ret; | |
| 1221 | } | |
| 1222 | ||
| de66b345 | 1223 | irq = platform_get_irq_byname(pdev, "mbhc_switch_int"); |
| cf9441ad | 1224 | if (irq < 0) |
| de66b345 | 1225 | return irq; |
| de66b345 | 1226 | |
| a8419a0c SK |
1227 | ret = devm_request_threaded_irq(dev, irq, NULL, |
| 1228 | pm8916_mbhc_switch_irq_handler, | |
| de66b345 SK |
1229 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | |
| 1230 | IRQF_ONESHOT, | |
| 1231 | "mbhc switch irq", priv); | |
| 1232 | if (ret) | |
| 1233 | dev_err(dev, "cannot request mbhc switch irq\n"); | |
| 1234 | ||
| 1235 | if (priv->mbhc_btn_enabled) { | |
| 1236 | irq = platform_get_irq_byname(pdev, "mbhc_but_press_det"); | |
| cf9441ad | 1237 | if (irq < 0) |
| de66b345 | 1238 | return irq; |
| de66b345 | 1239 | |
| a8419a0c SK |
1240 | ret = devm_request_threaded_irq(dev, irq, NULL, |
| 1241 | mbhc_btn_press_irq_handler, | |
| de66b345 SK |
1242 | IRQF_TRIGGER_RISING | |
| 1243 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, | |
| 1244 | "mbhc btn press irq", priv); | |
| 1245 | if (ret) | |
| 1246 | dev_err(dev, "cannot request mbhc button press irq\n"); | |
| 1247 | ||
| 1248 | irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det"); | |
| cf9441ad | 1249 | if (irq < 0) |
| de66b345 | 1250 | return irq; |
| de66b345 | 1251 | |
| a8419a0c SK |
1252 | ret = devm_request_threaded_irq(dev, irq, NULL, |
| 1253 | mbhc_btn_release_irq_handler, | |
| de66b345 SK |
1254 | IRQF_TRIGGER_RISING | |
| 1255 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, | |
| 1256 | "mbhc btn release irq", priv); | |
| 1257 | if (ret) | |
| 1258 | dev_err(dev, "cannot request mbhc button release irq\n"); | |
| 1259 | ||
| 1260 | } | |
| 1261 | ||
| 585e881e SK |
1262 | dev_set_drvdata(dev, priv); |
| 1263 | ||
| 732ae454 | 1264 | return devm_snd_soc_register_component(dev, &pm8916_wcd_analog, |
| 585e881e SK |
1265 | pm8916_wcd_analog_dai, |
| 1266 | ARRAY_SIZE(pm8916_wcd_analog_dai)); | |
| 1267 | } | |
| 1268 | ||
| 1269 | static int pm8916_wcd_analog_spmi_remove(struct platform_device *pdev) | |
| 1270 | { | |
| 1271 | struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(&pdev->dev); | |
| 1272 | ||
| 585e881e SK |
1273 | clk_disable_unprepare(priv->mclk); |
| 1274 | ||
| 1275 | return 0; | |
| 1276 | } | |
| 1277 | ||
| 1278 | static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = { | |
| 1279 | { .compatible = "qcom,pm8916-wcd-analog-codec", }, | |
| 1280 | { } | |
| 1281 | }; | |
| 1282 | ||
| 46d69e14 ND |
1283 | MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table); |
| 1284 | ||
| 585e881e SK |
1285 | static struct platform_driver pm8916_wcd_analog_spmi_driver = { |
| 1286 | .driver = { | |
| 1287 | .name = "qcom,pm8916-wcd-spmi-codec", | |
| 1288 | .of_match_table = pm8916_wcd_analog_spmi_match_table, | |
| 1289 | }, | |
| 1290 | .probe = pm8916_wcd_analog_spmi_probe, | |
| 1291 | .remove = pm8916_wcd_analog_spmi_remove, | |
| 1292 | }; | |
| 1293 | ||
| 1294 | module_platform_driver(pm8916_wcd_analog_spmi_driver); | |
| 1295 | ||
| 1296 | MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>"); | |
| 1297 | MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver"); | |
| 1298 | MODULE_LICENSE("GPL v2"); |