]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - sound/soc/codecs/nau8540.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: nau8540: reset state machine for channel phase sync
[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / nau8540.c
CommitLineData
c1644e3d
JH		 1/*
2 * NAU85L40 ALSA SoC audio driver
3 *
4 * Copyright 2016 Nuvoton Technology Corp.
5 * Author: John Hsu <KCHSU0@nuvoton.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/regmap.h>
19#include <linux/regulator/consumer.h>
20#include <linux/spi/spi.h>
21#include <linux/slab.h>
22#include <linux/of_device.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30#include "nau8540.h"
31
32
33#define NAU_FREF_MAX 13500000
34#define NAU_FVCO_MAX 100000000
35#define NAU_FVCO_MIN 90000000
36
37/* the maximum frequency of CLK_ADC */
38#define CLK_ADC_MAX 6144000
39
40/* scaling for mclk from sysclk_src output */
41static const struct nau8540_fll_attr mclk_src_scaling[] = {
babd6585
JH		 42 { 1, 0x0 },
43 { 2, 0x2 },
44 { 4, 0x3 },
45 { 8, 0x4 },
46 { 16, 0x5 },
47 { 32, 0x6 },
48 { 3, 0x7 },
49 { 6, 0xa },
50 { 12, 0xb },
51 { 24, 0xc },
c1644e3d
JH		 52};
53
54/* ratio for input clk freq */
55static const struct nau8540_fll_attr fll_ratio[] = {
babd6585
JH		 56 { 512000, 0x01 },
57 { 256000, 0x02 },
58 { 128000, 0x04 },
59 { 64000, 0x08 },
60 { 32000, 0x10 },
61 { 8000, 0x20 },
62 { 4000, 0x40 },
c1644e3d
JH		 63};
64
65static const struct nau8540_fll_attr fll_pre_scalar[] = {
babd6585
JH		 66 { 1, 0x0 },
67 { 2, 0x1 },
68 { 4, 0x2 },
69 { 8, 0x3 },
c1644e3d
JH		 70};
71
72/* over sampling rate */
73static const struct nau8540_osr_attr osr_adc_sel[] = {
babd6585
JH		 74 { 32, 3 }, /* OSR 32, SRC 1/8 */
75 { 64, 2 }, /* OSR 64, SRC 1/4 */
76 { 128, 1 }, /* OSR 128, SRC 1/2 */
77 { 256, 0 }, /* OSR 256, SRC 1 */
c1644e3d
JH		 78};
79
80static const struct reg_default nau8540_reg_defaults[] = {
babd6585
JH		 81 {NAU8540_REG_POWER_MANAGEMENT, 0x0000},
82 {NAU8540_REG_CLOCK_CTRL, 0x0000},
83 {NAU8540_REG_CLOCK_SRC, 0x0000},
84 {NAU8540_REG_FLL1, 0x0001},
85 {NAU8540_REG_FLL2, 0x3126},
86 {NAU8540_REG_FLL3, 0x0008},
87 {NAU8540_REG_FLL4, 0x0010},
88 {NAU8540_REG_FLL5, 0xC000},
89 {NAU8540_REG_FLL6, 0x6000},
90 {NAU8540_REG_FLL_VCO_RSV, 0xF13C},
91 {NAU8540_REG_PCM_CTRL0, 0x000B},
92 {NAU8540_REG_PCM_CTRL1, 0x3010},
93 {NAU8540_REG_PCM_CTRL2, 0x0800},
94 {NAU8540_REG_PCM_CTRL3, 0x0000},
95 {NAU8540_REG_PCM_CTRL4, 0x000F},
96 {NAU8540_REG_ALC_CONTROL_1, 0x0000},
97 {NAU8540_REG_ALC_CONTROL_2, 0x700B},
98 {NAU8540_REG_ALC_CONTROL_3, 0x0022},
99 {NAU8540_REG_ALC_CONTROL_4, 0x1010},
100 {NAU8540_REG_ALC_CONTROL_5, 0x1010},
101 {NAU8540_REG_NOTCH_FIL1_CH1, 0x0000},
102 {NAU8540_REG_NOTCH_FIL2_CH1, 0x0000},
103 {NAU8540_REG_NOTCH_FIL1_CH2, 0x0000},
104 {NAU8540_REG_NOTCH_FIL2_CH2, 0x0000},
105 {NAU8540_REG_NOTCH_FIL1_CH3, 0x0000},
106 {NAU8540_REG_NOTCH_FIL2_CH3, 0x0000},
107 {NAU8540_REG_NOTCH_FIL1_CH4, 0x0000},
108 {NAU8540_REG_NOTCH_FIL2_CH4, 0x0000},
109 {NAU8540_REG_HPF_FILTER_CH12, 0x0000},
110 {NAU8540_REG_HPF_FILTER_CH34, 0x0000},
111 {NAU8540_REG_ADC_SAMPLE_RATE, 0x0002},
112 {NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400},
113 {NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400},
114 {NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400},
115 {NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400},
116 {NAU8540_REG_DIGITAL_MUX, 0x00E4},
117 {NAU8540_REG_GPIO_CTRL, 0x0000},
118 {NAU8540_REG_MISC_CTRL, 0x0000},
119 {NAU8540_REG_I2C_CTRL, 0xEFFF},
120 {NAU8540_REG_VMID_CTRL, 0x0000},
121 {NAU8540_REG_MUTE, 0x0000},
122 {NAU8540_REG_ANALOG_ADC1, 0x0011},
123 {NAU8540_REG_ANALOG_ADC2, 0x0020},
124 {NAU8540_REG_ANALOG_PWR, 0x0000},
125 {NAU8540_REG_MIC_BIAS, 0x0004},
126 {NAU8540_REG_REFERENCE, 0x0000},
127 {NAU8540_REG_FEPGA1, 0x0000},
128 {NAU8540_REG_FEPGA2, 0x0000},
129 {NAU8540_REG_FEPGA3, 0x0101},
130 {NAU8540_REG_FEPGA4, 0x0101},
131 {NAU8540_REG_PWR, 0x0000},
c1644e3d
JH		 132};
133
134static bool nau8540_readable_reg(struct device *dev, unsigned int reg)
135{
babd6585
JH		 136 switch (reg) {
137 case NAU8540_REG_POWER_MANAGEMENT ... NAU8540_REG_FLL_VCO_RSV:
138 case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
139 case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
140 case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ADC_SAMPLE_RATE:
141 case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
142 case NAU8540_REG_P2P_CH1 ... NAU8540_REG_I2C_CTRL:
143 case NAU8540_REG_I2C_DEVICE_ID:
144 case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
145 case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
146 return true;
147 default:
148 return false;
149 }
c1644e3d
JH		 150
151}
152
153static bool nau8540_writeable_reg(struct device *dev, unsigned int reg)
154{
babd6585
JH		 155 switch (reg) {
156 case NAU8540_REG_SW_RESET ... NAU8540_REG_FLL_VCO_RSV:
157 case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4:
158 case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5:
159 case NAU8540_REG_NOTCH_FIL1_CH1 ... NAU8540_REG_ADC_SAMPLE_RATE:
160 case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX:
161 case NAU8540_REG_GPIO_CTRL ... NAU8540_REG_I2C_CTRL:
162 case NAU8540_REG_RST:
163 case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE:
164 case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR:
165 return true;
166 default:
167 return false;
168 }
c1644e3d
JH		 169}
170
171static bool nau8540_volatile_reg(struct device *dev, unsigned int reg)
172{
babd6585
JH		 173 switch (reg) {
174 case NAU8540_REG_SW_RESET:
175 case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ALC_STATUS:
176 case NAU8540_REG_P2P_CH1 ... NAU8540_REG_PEAK_CH4:
177 case NAU8540_REG_I2C_DEVICE_ID:
178 case NAU8540_REG_RST:
179 return true;
180 default:
181 return false;
182 }
c1644e3d
JH		 183}
184
185
186static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
187static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
188
189static const struct snd_kcontrol_new nau8540_snd_controls[] = {
babd6585
JH		 190 SOC_SINGLE_TLV("Mic1 Volume", NAU8540_REG_DIGITAL_GAIN_CH1,
191 0, 0x520, 0, adc_vol_tlv),
192 SOC_SINGLE_TLV("Mic2 Volume", NAU8540_REG_DIGITAL_GAIN_CH2,
193 0, 0x520, 0, adc_vol_tlv),
194 SOC_SINGLE_TLV("Mic3 Volume", NAU8540_REG_DIGITAL_GAIN_CH3,
195 0, 0x520, 0, adc_vol_tlv),
196 SOC_SINGLE_TLV("Mic4 Volume", NAU8540_REG_DIGITAL_GAIN_CH4,
197 0, 0x520, 0, adc_vol_tlv),
198
199 SOC_SINGLE_TLV("Frontend PGA1 Volume", NAU8540_REG_FEPGA3,
200 0, 0x25, 0, fepga_gain_tlv),
201 SOC_SINGLE_TLV("Frontend PGA2 Volume", NAU8540_REG_FEPGA3,
202 8, 0x25, 0, fepga_gain_tlv),
203 SOC_SINGLE_TLV("Frontend PGA3 Volume", NAU8540_REG_FEPGA4,
204 0, 0x25, 0, fepga_gain_tlv),
205 SOC_SINGLE_TLV("Frontend PGA4 Volume", NAU8540_REG_FEPGA4,
206 8, 0x25, 0, fepga_gain_tlv),
c1644e3d
JH		 207};
208
209static const char * const adc_channel[] = {
babd6585 210 "ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4"
c1644e3d
JH		 211};
212static SOC_ENUM_SINGLE_DECL(
babd6585 213 digital_ch4_enum, NAU8540_REG_DIGITAL_MUX, 6, adc_channel);
c1644e3d
JH		 214
215static const struct snd_kcontrol_new digital_ch4_mux =
babd6585 216 SOC_DAPM_ENUM("Digital CH4 Select", digital_ch4_enum);
c1644e3d
JH		 217
218static SOC_ENUM_SINGLE_DECL(
babd6585 219 digital_ch3_enum, NAU8540_REG_DIGITAL_MUX, 4, adc_channel);
c1644e3d
JH		 220
221static const struct snd_kcontrol_new digital_ch3_mux =
babd6585 222 SOC_DAPM_ENUM("Digital CH3 Select", digital_ch3_enum);
c1644e3d
JH		 223
224static SOC_ENUM_SINGLE_DECL(
babd6585 225 digital_ch2_enum, NAU8540_REG_DIGITAL_MUX, 2, adc_channel);
c1644e3d
JH		 226
227static const struct snd_kcontrol_new digital_ch2_mux =
babd6585 228 SOC_DAPM_ENUM("Digital CH2 Select", digital_ch2_enum);
c1644e3d
JH		 229
230static SOC_ENUM_SINGLE_DECL(
babd6585 231 digital_ch1_enum, NAU8540_REG_DIGITAL_MUX, 0, adc_channel);
c1644e3d
JH		 232
233static const struct snd_kcontrol_new digital_ch1_mux =
babd6585 234 SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum);
c1644e3d 235
e4d0db60
JH		 236static int aiftx_power_control(struct snd_soc_dapm_widget *w,
237 struct snd_kcontrol *k, int event)
238{
239 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
240 struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
241
242 if (SND_SOC_DAPM_EVENT_OFF(event)) {
243 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);
244 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);
245 }
246 return 0;
247}
248
c1644e3d 249static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = {
babd6585
JH		 250 SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),
251 SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
252
253 SND_SOC_DAPM_INPUT("MIC1"),
254 SND_SOC_DAPM_INPUT("MIC2"),
255 SND_SOC_DAPM_INPUT("MIC3"),
256 SND_SOC_DAPM_INPUT("MIC4"),
257
258 SND_SOC_DAPM_PGA("Frontend PGA1", NAU8540_REG_PWR, 12, 0, NULL, 0),
259 SND_SOC_DAPM_PGA("Frontend PGA2", NAU8540_REG_PWR, 13, 0, NULL, 0),
260 SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0),
261 SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0),
262
263 SND_SOC_DAPM_ADC("ADC1", NULL,
264 NAU8540_REG_POWER_MANAGEMENT, 0, 0),
265 SND_SOC_DAPM_ADC("ADC2", NULL,
266 NAU8540_REG_POWER_MANAGEMENT, 1, 0),
267 SND_SOC_DAPM_ADC("ADC3", NULL,
268 NAU8540_REG_POWER_MANAGEMENT, 2, 0),
269 SND_SOC_DAPM_ADC("ADC4", NULL,
270 NAU8540_REG_POWER_MANAGEMENT, 3, 0),
271
272 SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
273 SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
274 SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0),
275 SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0),
276
277 SND_SOC_DAPM_MUX("Digital CH4 Mux",
278 SND_SOC_NOPM, 0, 0, &digital_ch4_mux),
279 SND_SOC_DAPM_MUX("Digital CH3 Mux",
280 SND_SOC_NOPM, 0, 0, &digital_ch3_mux),
281 SND_SOC_DAPM_MUX("Digital CH2 Mux",
282 SND_SOC_NOPM, 0, 0, &digital_ch2_mux),
283 SND_SOC_DAPM_MUX("Digital CH1 Mux",
284 SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
285
e4d0db60
JH		 286 SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0,
287 aiftx_power_control, SND_SOC_DAPM_POST_PMD),
c1644e3d
JH		 288};
289
290static const struct snd_soc_dapm_route nau8540_dapm_routes[] = {
babd6585
JH		 291 {"Frontend PGA1", NULL, "MIC1"},
292 {"Frontend PGA2", NULL, "MIC2"},
293 {"Frontend PGA3", NULL, "MIC3"},
294 {"Frontend PGA4", NULL, "MIC4"},
295
296 {"ADC1", NULL, "Frontend PGA1"},
297 {"ADC2", NULL, "Frontend PGA2"},
298 {"ADC3", NULL, "Frontend PGA3"},
299 {"ADC4", NULL, "Frontend PGA4"},
300
301 {"ADC CH1", NULL, "ADC1"},
302 {"ADC CH2", NULL, "ADC2"},
303 {"ADC CH3", NULL, "ADC3"},
304 {"ADC CH4", NULL, "ADC4"},
305
306 {"ADC1", NULL, "MICBIAS1"},
307 {"ADC2", NULL, "MICBIAS1"},
308 {"ADC3", NULL, "MICBIAS2"},
309 {"ADC4", NULL, "MICBIAS2"},
310
311 {"Digital CH1 Mux", "ADC channel 1", "ADC CH1"},
312 {"Digital CH1 Mux", "ADC channel 2", "ADC CH2"},
313 {"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
314 {"Digital CH1 Mux", "ADC channel 4", "ADC CH4"},
315
316 {"Digital CH2 Mux", "ADC channel 1", "ADC CH1"},
317 {"Digital CH2 Mux", "ADC channel 2", "ADC CH2"},
318 {"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
319 {"Digital CH2 Mux", "ADC channel 4", "ADC CH4"},
320
321 {"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
322 {"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
323 {"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
324 {"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
325
326 {"Digital CH4 Mux", "ADC channel 1", "ADC CH1"},
327 {"Digital CH4 Mux", "ADC channel 2", "ADC CH2"},
328 {"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
329 {"Digital CH4 Mux", "ADC channel 4", "ADC CH4"},
330
331 {"AIFTX", NULL, "Digital CH1 Mux"},
332 {"AIFTX", NULL, "Digital CH2 Mux"},
333 {"AIFTX", NULL, "Digital CH3 Mux"},
334 {"AIFTX", NULL, "Digital CH4 Mux"},
c1644e3d
JH		 335};
336
337static int nau8540_clock_check(struct nau8540 *nau8540, int rate, int osr)
338{
babd6585 339 int osrate;
c1644e3d 340
babd6585
JH		 341 if (osr >= ARRAY_SIZE(osr_adc_sel))
342 return -EINVAL;
343 osrate = osr_adc_sel[osr].osr;
c1644e3d 344
babd6585
JH		 345 if (rate * osr > CLK_ADC_MAX) {
346 dev_err(nau8540->dev, "exceed the maximum frequency of CLK_ADC\n");
347 return -EINVAL;
348 }
c1644e3d 349
babd6585 350 return 0;
c1644e3d
JH		 351}
352
353static int nau8540_hw_params(struct snd_pcm_substream *substream,
babd6585 354 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
c1644e3d 355{
babd6585
JH		 356 struct snd_soc_codec *codec = dai->codec;
357 struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
358 unsigned int val_len = 0, osr;
359
360 /* CLK_ADC = OSR * FS
361 * ADC clock frequency is defined as Over Sampling Rate (OSR)
362 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
363 * values must be selected such that the maximum frequency is less
364 * than 6.144 MHz.
365 */
366 regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);
367 osr &= NAU8540_ADC_OSR_MASK;
368 if (nau8540_clock_check(nau8540, params_rate(params), osr))
369 return -EINVAL;
370 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
371 NAU8540_CLK_ADC_SRC_MASK,
372 osr_adc_sel[osr].clk_src << NAU8540_CLK_ADC_SRC_SFT);
373
374 switch (params_width(params)) {
375 case 16:
376 val_len |= NAU8540_I2S_DL_16;
377 break;
378 case 20:
379 val_len |= NAU8540_I2S_DL_20;
380 break;
381 case 24:
382 val_len |= NAU8540_I2S_DL_24;
383 break;
384 case 32:
385 val_len |= NAU8540_I2S_DL_32;
386 break;
387 default:
388 return -EINVAL;
389 }
390
391 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
392 NAU8540_I2S_DL_MASK, val_len);
393
394 return 0;
c1644e3d
JH		 395}
396
397static int nau8540_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
398{
babd6585
JH		 399 struct snd_soc_codec *codec = dai->codec;
400 struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
401 unsigned int ctrl1_val = 0, ctrl2_val = 0;
402
403 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
404 case SND_SOC_DAIFMT_CBM_CFM:
405 ctrl2_val |= NAU8540_I2S_MS_MASTER;
406 break;
407 case SND_SOC_DAIFMT_CBS_CFS:
408 break;
409 default:
410 return -EINVAL;
411 }
412
413 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
414 case SND_SOC_DAIFMT_NB_NF:
415 break;
416 case SND_SOC_DAIFMT_IB_NF:
417 ctrl1_val |= NAU8540_I2S_BP_INV;
418 break;
419 default:
420 return -EINVAL;
421 }
422
423 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
424 case SND_SOC_DAIFMT_I2S:
425 ctrl1_val |= NAU8540_I2S_DF_I2S;
426 break;
427 case SND_SOC_DAIFMT_LEFT_J:
428 ctrl1_val |= NAU8540_I2S_DF_LEFT;
429 break;
430 case SND_SOC_DAIFMT_RIGHT_J:
431 ctrl1_val |= NAU8540_I2S_DF_RIGTH;
432 break;
433 case SND_SOC_DAIFMT_DSP_A:
434 ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
435 break;
436 case SND_SOC_DAIFMT_DSP_B:
437 ctrl1_val |= NAU8540_I2S_DF_PCM_AB;
438 ctrl1_val |= NAU8540_I2S_PCMB_EN;
439 break;
440 default:
441 return -EINVAL;
442 }
443
444 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
445 NAU8540_I2S_DL_MASK | NAU8540_I2S_DF_MASK |
446 NAU8540_I2S_BP_INV | NAU8540_I2S_PCMB_EN, ctrl1_val);
447 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
448 NAU8540_I2S_MS_MASK | NAU8540_I2S_DO12_OE, ctrl2_val);
449 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
450 NAU8540_I2S_DO34_OE, 0);
451
452 return 0;
c1644e3d
JH		 453}
454
455/**
456 * nau8540_set_tdm_slot - configure DAI TX TDM.
457 * @dai: DAI
458 * @tx_mask: bitmask representing active TX slots. Ex.
459 * 0xf for normal 4 channel TDM.
460 * 0xf0 for shifted 4 channel TDM
461 * @rx_mask: no used.
462 * @slots: Number of slots in use.
463 * @slot_width: Width in bits for each slot.
464 *
465 * Configures a DAI for TDM operation. Only support 4 slots TDM.
466 */
467static int nau8540_set_tdm_slot(struct snd_soc_dai *dai,
babd6585 468 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
c1644e3d 469{
babd6585
JH		 470 struct snd_soc_codec *codec = dai->codec;
471 struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
472 unsigned int ctrl2_val = 0, ctrl4_val = 0;
473
474 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)))
475 return -EINVAL;
476
477 ctrl4_val |= (NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN);
478 if (tx_mask & 0xf0) {
479 ctrl2_val = 4 * slot_width;
480 ctrl4_val |= (tx_mask >> 4);
481 } else {
482 ctrl4_val |= tx_mask;
483 }
484 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,
485 NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN |
486 NAU8540_TDM_TX_MASK, ctrl4_val);
487 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
488 NAU8540_I2S_DO12_OE, NAU8540_I2S_DO12_OE);
489 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
490 NAU8540_I2S_DO34_OE | NAU8540_I2S_TSLOT_L_MASK,
491 NAU8540_I2S_DO34_OE | ctrl2_val);
492
493 return 0;
c1644e3d
JH		 494}
495
496
497static const struct snd_soc_dai_ops nau8540_dai_ops = {
babd6585
JH		 498 .hw_params = nau8540_hw_params,
499 .set_fmt = nau8540_set_fmt,
500 .set_tdm_slot = nau8540_set_tdm_slot,
c1644e3d
JH		 501};
502
503#define NAU8540_RATES SNDRV_PCM_RATE_8000_48000
504#define NAU8540_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
babd6585 505 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
c1644e3d
JH		 506
507static struct snd_soc_dai_driver nau8540_dai = {
babd6585
JH		 508 .name = "nau8540-hifi",
509 .capture = {
510 .stream_name = "Capture",
511 .channels_min = 1,
512 .channels_max = 4,
513 .rates = NAU8540_RATES,
514 .formats = NAU8540_FORMATS,
515 },
516 .ops = &nau8540_dai_ops,
c1644e3d
JH		 517};
518
519/**
520 * nau8540_calc_fll_param - Calculate FLL parameters.
521 * @fll_in: external clock provided to codec.
522 * @fs: sampling rate.
523 * @fll_param: Pointer to structure of FLL parameters.
524 *
525 * Calculate FLL parameters to configure codec.
526 *
527 * Returns 0 for success or negative error code.
528 */
529static int nau8540_calc_fll_param(unsigned int fll_in,
babd6585 530 unsigned int fs, struct nau8540_fll *fll_param)
c1644e3d 531{
babd6585
JH		 532 u64 fvco, fvco_max;
533 unsigned int fref, i, fvco_sel;
534
535 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
536 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
537 * FREF = freq_in / NAU8540_FLL_REF_DIV_MASK
538 */
539 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
540 fref = fll_in / fll_pre_scalar[i].param;
541 if (fref <= NAU_FREF_MAX)
542 break;
543 }
544 if (i == ARRAY_SIZE(fll_pre_scalar))
545 return -EINVAL;
546 fll_param->clk_ref_div = fll_pre_scalar[i].val;
547
548 /* Choose the FLL ratio based on FREF */
549 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
550 if (fref >= fll_ratio[i].param)
551 break;
552 }
553 if (i == ARRAY_SIZE(fll_ratio))
554 return -EINVAL;
555 fll_param->ratio = fll_ratio[i].val;
556
557 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
558 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
559 * guaranteed across the full range of operation.
560 * FDCO = freq_out * 2 * mclk_src_scaling
561 */
562 fvco_max = 0;
563 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
564 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
565 fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
566 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
567 fvco_max < fvco) {
568 fvco_max = fvco;
569 fvco_sel = i;
570 }
571 }
572 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
573 return -EINVAL;
574 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
575
576 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
577 * input based on FDCO, FREF and FLL ratio.
578 */
579 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
580 fll_param->fll_int = (fvco >> 16) & 0x3FF;
581 fll_param->fll_frac = fvco & 0xFFFF;
582 return 0;
c1644e3d
JH		 583}
584
585static void nau8540_fll_apply(struct regmap *regmap,
babd6585 586 struct nau8540_fll *fll_param)
c1644e3d 587{
babd6585
JH		 588 regmap_update_bits(regmap, NAU8540_REG_CLOCK_SRC,
589 NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK,
590 NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);
591 regmap_update_bits(regmap, NAU8540_REG_FLL1,
592 NAU8540_FLL_RATIO_MASK, fll_param->ratio);
593 /* FLL 16-bit fractional input */
594 regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);
595 /* FLL 10-bit integer input */
596 regmap_update_bits(regmap, NAU8540_REG_FLL3,
597 NAU8540_FLL_INTEGER_MASK, fll_param->fll_int);
598 /* FLL pre-scaler */
599 regmap_update_bits(regmap, NAU8540_REG_FLL4,
600 NAU8540_FLL_REF_DIV_MASK,
601 fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT);
602 regmap_update_bits(regmap, NAU8540_REG_FLL5,
603 NAU8540_FLL_CLK_SW_MASK, NAU8540_FLL_CLK_SW_REF);
604 regmap_update_bits(regmap,
605 NAU8540_REG_FLL6, NAU8540_DCO_EN, 0);
606 if (fll_param->fll_frac) {
607 regmap_update_bits(regmap, NAU8540_REG_FLL5,
608 NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
609 NAU8540_FLL_FTR_SW_MASK,
610 NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
611 NAU8540_FLL_FTR_SW_FILTER);
612 regmap_update_bits(regmap, NAU8540_REG_FLL6,
613 NAU8540_SDM_EN, NAU8540_SDM_EN);
614 } else {
615 regmap_update_bits(regmap, NAU8540_REG_FLL5,
616 NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN |
617 NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU);
618 regmap_update_bits(regmap,
619 NAU8540_REG_FLL6, NAU8540_SDM_EN, 0);
620 }
c1644e3d
JH		 621}
622
623/* freq_out must be 256*Fs in order to achieve the best performance */
624static int nau8540_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
babd6585 625 unsigned int freq_in, unsigned int freq_out)
c1644e3d 626{
babd6585
JH		 627 struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
628 struct nau8540_fll fll_param;
629 int ret, fs;
630
631 switch (pll_id) {
632 case NAU8540_CLK_FLL_MCLK:
633 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
634 NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_MCLK);
635 break;
636
637 case NAU8540_CLK_FLL_BLK:
638 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
639 NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_BLK);
640 break;
641
642 case NAU8540_CLK_FLL_FS:
643 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
644 NAU8540_FLL_CLK_SRC_MASK, NAU8540_FLL_CLK_SRC_FS);
645 break;
646
647 default:
648 dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);
649 return -EINVAL;
650 }
651 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
652 freq_out, pll_id);
653
654 fs = freq_out / 256;
655 ret = nau8540_calc_fll_param(freq_in, fs, &fll_param);
656 if (ret < 0) {
657 dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);
658 return ret;
659 }
660 dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
661 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
662 fll_param.fll_int, fll_param.clk_ref_div);
663
664 nau8540_fll_apply(nau8540->regmap, &fll_param);
665 mdelay(2);
666 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
667 NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
668
669 return 0;
c1644e3d
JH		 670}
671
672static int nau8540_set_sysclk(struct snd_soc_codec *codec,
babd6585 673 int clk_id, int source, unsigned int freq, int dir)
c1644e3d 674{
babd6585
JH		 675 struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
676
677 switch (clk_id) {
678 case NAU8540_CLK_DIS:
679 case NAU8540_CLK_MCLK:
680 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
681 NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_MCLK);
682 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
683 NAU8540_DCO_EN, 0);
684 break;
685
686 case NAU8540_CLK_INTERNAL:
687 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
688 NAU8540_DCO_EN, NAU8540_DCO_EN);
689 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
690 NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO);
691 break;
692
693 default:
694 dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);
695 return -EINVAL;
696 }
697
698 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
699 freq, clk_id);
700
701 return 0;
c1644e3d
JH		 702}
703
704static void nau8540_reset_chip(struct regmap *regmap)
705{
babd6585
JH		 706 regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
707 regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00);
c1644e3d
JH		 708}
709
710static void nau8540_init_regs(struct nau8540 *nau8540)
711{
babd6585
JH		 712 struct regmap *regmap = nau8540->regmap;
713
714 /* Enable Bias/VMID/VMID Tieoff */
715 regmap_update_bits(regmap, NAU8540_REG_VMID_CTRL,
716 NAU8540_VMID_EN | NAU8540_VMID_SEL_MASK,
717 NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT));
718 regmap_update_bits(regmap, NAU8540_REG_REFERENCE,
719 NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN,
720 NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN);
721 mdelay(2);
722 regmap_update_bits(regmap, NAU8540_REG_MIC_BIAS,
723 NAU8540_PU_PRE, NAU8540_PU_PRE);
724 regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL,
725 NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN,
726 NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN);
e4d0db60
JH		 727 /* ADC OSR selection, CLK_ADC = Fs * OSR;
728 * Channel time alignment enable.
729 */
babd6585 730 regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE,
e4d0db60
JH		 731 NAU8540_CH_SYNC | NAU8540_ADC_OSR_MASK,
732 NAU8540_CH_SYNC | NAU8540_ADC_OSR_64);
c1644e3d
JH		 733}
734
735static int __maybe_unused nau8540_suspend(struct snd_soc_codec *codec)
736{
babd6585 737 struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
c1644e3d 738
babd6585
JH		 739 regcache_cache_only(nau8540->regmap, true);
740 regcache_mark_dirty(nau8540->regmap);
c1644e3d 741
babd6585 742 return 0;
c1644e3d
JH		 743}
744
745static int __maybe_unused nau8540_resume(struct snd_soc_codec *codec)
746{
babd6585 747 struct nau8540 *nau8540 = snd_soc_codec_get_drvdata(codec);
c1644e3d 748
babd6585
JH		 749 regcache_cache_only(nau8540->regmap, false);
750 regcache_sync(nau8540->regmap);
c1644e3d 751
babd6585 752 return 0;
c1644e3d
JH		 753}
754
a180ba45 755static const struct snd_soc_codec_driver nau8540_codec_driver = {
babd6585
JH		 756 .set_sysclk = nau8540_set_sysclk,
757 .set_pll = nau8540_set_pll,
758 .suspend = nau8540_suspend,
759 .resume = nau8540_resume,
760 .suspend_bias_off = true,
761
762 .component_driver = {
763 .controls = nau8540_snd_controls,
764 .num_controls = ARRAY_SIZE(nau8540_snd_controls),
765 .dapm_widgets = nau8540_dapm_widgets,
766 .num_dapm_widgets = ARRAY_SIZE(nau8540_dapm_widgets),
767 .dapm_routes = nau8540_dapm_routes,
768 .num_dapm_routes = ARRAY_SIZE(nau8540_dapm_routes),
769 },
c1644e3d
JH		 770};
771
772static const struct regmap_config nau8540_regmap_config = {
babd6585
JH		 773 .val_bits = 16,
774 .reg_bits = 16,
c1644e3d 775
babd6585
JH		 776 .max_register = NAU8540_REG_MAX,
777 .readable_reg = nau8540_readable_reg,
778 .writeable_reg = nau8540_writeable_reg,
779 .volatile_reg = nau8540_volatile_reg,
c1644e3d 780
babd6585
JH		 781 .cache_type = REGCACHE_RBTREE,
782 .reg_defaults = nau8540_reg_defaults,
783 .num_reg_defaults = ARRAY_SIZE(nau8540_reg_defaults),
c1644e3d
JH		 784};
785
786static int nau8540_i2c_probe(struct i2c_client *i2c,
babd6585 787 const struct i2c_device_id *id)
c1644e3d 788{
babd6585
JH		 789 struct device *dev = &i2c->dev;
790 struct nau8540 *nau8540 = dev_get_platdata(dev);
791 int ret, value;
792
793 if (!nau8540) {
794 nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL);
795 if (!nau8540)
796 return -ENOMEM;
797 }
798 i2c_set_clientdata(i2c, nau8540);
799
800 nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);
801 if (IS_ERR(nau8540->regmap))
802 return PTR_ERR(nau8540->regmap);
803 ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);
804 if (ret < 0) {
805 dev_err(dev, "Failed to read device id from the NAU85L40: %d\n",
806 ret);
807 return ret;
808 }
809
810 nau8540->dev = dev;
811 nau8540_reset_chip(nau8540->regmap);
812 nau8540_init_regs(nau8540);
813
814 return snd_soc_register_codec(dev,
815 &nau8540_codec_driver, &nau8540_dai, 1);
c1644e3d
JH		 816}
817
818static int nau8540_i2c_remove(struct i2c_client *client)
819{
babd6585
JH		 820 snd_soc_unregister_codec(&client->dev);
821 return 0;
c1644e3d
JH		 822}
823
824
825static const struct i2c_device_id nau8540_i2c_ids[] = {
babd6585
JH		 826 { "nau8540", 0 },
827 { }
c1644e3d
JH		 828};
829MODULE_DEVICE_TABLE(i2c, nau8540_i2c_ids);
830
831#ifdef CONFIG_OF
832static const struct of_device_id nau8540_of_ids[] = {
babd6585
JH		 833 { .compatible = "nuvoton,nau8540", },
834 {}
c1644e3d
JH		 835};
836MODULE_DEVICE_TABLE(of, nau8540_of_ids);
837#endif
838
839static struct i2c_driver nau8540_i2c_driver = {
babd6585
JH		 840 .driver = {
841 .name = "nau8540",
842 .of_match_table = of_match_ptr(nau8540_of_ids),
843 },
844 .probe = nau8540_i2c_probe,
845 .remove = nau8540_i2c_remove,
846 .id_table = nau8540_i2c_ids,
c1644e3d
JH		 847};
848module_i2c_driver(nau8540_i2c_driver);
849
850MODULE_DESCRIPTION("ASoC NAU85L40 driver");
851MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>");
852MODULE_LICENSE("GPL v2");
Ubuntu Hirsute Linux kernel mirror