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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
dfeabded JH |
2 | /* |
3 | * NAU88L24 ALSA SoC audio driver | |
4 | * | |
5 | * Copyright 2016 Nuvoton Technology Corp. | |
6 | * Author: John Hsu <KCHSU0@nuvoton.com> | |
dfeabded JH |
7 | */ |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/i2c.h> | |
13 | #include <linux/regmap.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/acpi.h> | |
17 | #include <linux/math64.h> | |
18 | #include <linux/semaphore.h> | |
19 | ||
20 | #include <sound/initval.h> | |
21 | #include <sound/tlv.h> | |
22 | #include <sound/core.h> | |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/soc.h> | |
26 | #include <sound/jack.h> | |
27 | ||
28 | #include "nau8824.h" | |
29 | ||
30 | ||
31 | static int nau8824_config_sysclk(struct nau8824 *nau8824, | |
32 | int clk_id, unsigned int freq); | |
33 | static bool nau8824_is_jack_inserted(struct nau8824 *nau8824); | |
34 | ||
35 | /* the ADC threshold of headset */ | |
36 | #define DMIC_CLK 3072000 | |
37 | ||
38 | /* the ADC threshold of headset */ | |
39 | #define HEADSET_SARADC_THD 0x80 | |
40 | ||
41 | /* the parameter threshold of FLL */ | |
42 | #define NAU_FREF_MAX 13500000 | |
080f773d | 43 | #define NAU_FVCO_MAX 100000000 |
dfeabded JH |
44 | #define NAU_FVCO_MIN 90000000 |
45 | ||
46 | /* scaling for mclk from sysclk_src output */ | |
47 | static const struct nau8824_fll_attr mclk_src_scaling[] = { | |
48 | { 1, 0x0 }, | |
49 | { 2, 0x2 }, | |
50 | { 4, 0x3 }, | |
51 | { 8, 0x4 }, | |
52 | { 16, 0x5 }, | |
53 | { 32, 0x6 }, | |
54 | { 3, 0x7 }, | |
55 | { 6, 0xa }, | |
56 | { 12, 0xb }, | |
57 | { 24, 0xc }, | |
58 | }; | |
59 | ||
60 | /* ratio for input clk freq */ | |
61 | static const struct nau8824_fll_attr fll_ratio[] = { | |
62 | { 512000, 0x01 }, | |
63 | { 256000, 0x02 }, | |
64 | { 128000, 0x04 }, | |
65 | { 64000, 0x08 }, | |
66 | { 32000, 0x10 }, | |
67 | { 8000, 0x20 }, | |
68 | { 4000, 0x40 }, | |
69 | }; | |
70 | ||
71 | static const struct nau8824_fll_attr fll_pre_scalar[] = { | |
72 | { 1, 0x0 }, | |
73 | { 2, 0x1 }, | |
74 | { 4, 0x2 }, | |
75 | { 8, 0x3 }, | |
76 | }; | |
77 | ||
78 | /* the maximum frequency of CLK_ADC and CLK_DAC */ | |
79 | #define CLK_DA_AD_MAX 6144000 | |
80 | ||
81 | /* over sampling rate */ | |
82 | static const struct nau8824_osr_attr osr_dac_sel[] = { | |
83 | { 64, 2 }, /* OSR 64, SRC 1/4 */ | |
84 | { 256, 0 }, /* OSR 256, SRC 1 */ | |
85 | { 128, 1 }, /* OSR 128, SRC 1/2 */ | |
86 | { 0, 0 }, | |
87 | { 32, 3 }, /* OSR 32, SRC 1/8 */ | |
88 | }; | |
89 | ||
90 | static const struct nau8824_osr_attr osr_adc_sel[] = { | |
91 | { 32, 3 }, /* OSR 32, SRC 1/8 */ | |
92 | { 64, 2 }, /* OSR 64, SRC 1/4 */ | |
93 | { 128, 1 }, /* OSR 128, SRC 1/2 */ | |
94 | { 256, 0 }, /* OSR 256, SRC 1 */ | |
95 | }; | |
96 | ||
97 | static const struct reg_default nau8824_reg_defaults[] = { | |
98 | { NAU8824_REG_ENA_CTRL, 0x0000 }, | |
99 | { NAU8824_REG_CLK_GATING_ENA, 0x0000 }, | |
100 | { NAU8824_REG_CLK_DIVIDER, 0x0000 }, | |
101 | { NAU8824_REG_FLL1, 0x0000 }, | |
102 | { NAU8824_REG_FLL2, 0x3126 }, | |
103 | { NAU8824_REG_FLL3, 0x0008 }, | |
104 | { NAU8824_REG_FLL4, 0x0010 }, | |
105 | { NAU8824_REG_FLL5, 0xC000 }, | |
106 | { NAU8824_REG_FLL6, 0x6000 }, | |
107 | { NAU8824_REG_FLL_VCO_RSV, 0xF13C }, | |
108 | { NAU8824_REG_JACK_DET_CTRL, 0x0000 }, | |
109 | { NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 }, | |
110 | { NAU8824_REG_IRQ, 0x0000 }, | |
111 | { NAU8824_REG_CLEAR_INT_REG, 0x0000 }, | |
112 | { NAU8824_REG_INTERRUPT_SETTING, 0x1000 }, | |
113 | { NAU8824_REG_SAR_ADC, 0x0015 }, | |
114 | { NAU8824_REG_VDET_COEFFICIENT, 0x0110 }, | |
115 | { NAU8824_REG_VDET_THRESHOLD_1, 0x0000 }, | |
116 | { NAU8824_REG_VDET_THRESHOLD_2, 0x0000 }, | |
117 | { NAU8824_REG_VDET_THRESHOLD_3, 0x0000 }, | |
118 | { NAU8824_REG_VDET_THRESHOLD_4, 0x0000 }, | |
119 | { NAU8824_REG_GPIO_SEL, 0x0000 }, | |
120 | { NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B }, | |
121 | { NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 }, | |
122 | { NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 }, | |
123 | { NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 }, | |
124 | { NAU8824_REG_TDM_CTRL, 0x0000 }, | |
125 | { NAU8824_REG_ADC_HPF_FILTER, 0x0000 }, | |
126 | { NAU8824_REG_ADC_FILTER_CTRL, 0x0002 }, | |
127 | { NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 }, | |
128 | { NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 }, | |
129 | { NAU8824_REG_NOTCH_FILTER_1, 0x0000 }, | |
130 | { NAU8824_REG_NOTCH_FILTER_2, 0x0000 }, | |
131 | { NAU8824_REG_EQ1_LOW, 0x112C }, | |
132 | { NAU8824_REG_EQ2_EQ3, 0x2C2C }, | |
133 | { NAU8824_REG_EQ4_EQ5, 0x2C2C }, | |
134 | { NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 }, | |
135 | { NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 }, | |
136 | { NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 }, | |
137 | { NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 }, | |
138 | { NAU8824_REG_DAC_MUTE_CTRL, 0x0000 }, | |
139 | { NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 }, | |
140 | { NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 }, | |
141 | { NAU8824_REG_ADC_TO_DAC_ST, 0x0000 }, | |
142 | { NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 }, | |
143 | { NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 }, | |
144 | { NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF }, | |
145 | { NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 }, | |
146 | { NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 }, | |
147 | { NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 }, | |
148 | { NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF }, | |
149 | { NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 }, | |
150 | { NAU8824_REG_DRC_GAINL_ADC0, 0x0200 }, | |
151 | { NAU8824_REG_DRC_GAINL_ADC1, 0x0200 }, | |
152 | { NAU8824_REG_DRC_GAINL_ADC2, 0x0200 }, | |
153 | { NAU8824_REG_DRC_GAINL_ADC3, 0x0200 }, | |
154 | { NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 }, | |
155 | { NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 }, | |
156 | { NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 }, | |
157 | { NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 }, | |
158 | { NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 }, | |
159 | { NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 }, | |
160 | { NAU8824_REG_MODE, 0x0000 }, | |
161 | { NAU8824_REG_MODE1, 0x0000 }, | |
162 | { NAU8824_REG_MODE2, 0x0000 }, | |
163 | { NAU8824_REG_CLASSG, 0x0000 }, | |
164 | { NAU8824_REG_OTP_EFUSE, 0x0000 }, | |
165 | { NAU8824_REG_OTPDOUT_1, 0x0000 }, | |
166 | { NAU8824_REG_OTPDOUT_2, 0x0000 }, | |
167 | { NAU8824_REG_MISC_CTRL, 0x0000 }, | |
168 | { NAU8824_REG_I2C_TIMEOUT, 0xEFFF }, | |
169 | { NAU8824_REG_TEST_MODE, 0x0000 }, | |
170 | { NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 }, | |
171 | { NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF }, | |
172 | { NAU8824_REG_BIAS_ADJ, 0x0000 }, | |
173 | { NAU8824_REG_PGA_GAIN, 0x0000 }, | |
174 | { NAU8824_REG_TRIM_SETTINGS, 0x0000 }, | |
175 | { NAU8824_REG_ANALOG_CONTROL_1, 0x0000 }, | |
176 | { NAU8824_REG_ANALOG_CONTROL_2, 0x0000 }, | |
177 | { NAU8824_REG_ENABLE_LO, 0x0000 }, | |
178 | { NAU8824_REG_GAIN_LO, 0x0000 }, | |
179 | { NAU8824_REG_CLASSD_GAIN_1, 0x0000 }, | |
180 | { NAU8824_REG_CLASSD_GAIN_2, 0x0000 }, | |
181 | { NAU8824_REG_ANALOG_ADC_1, 0x0011 }, | |
182 | { NAU8824_REG_ANALOG_ADC_2, 0x0020 }, | |
183 | { NAU8824_REG_RDAC, 0x0008 }, | |
184 | { NAU8824_REG_MIC_BIAS, 0x0006 }, | |
185 | { NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 }, | |
186 | { NAU8824_REG_BOOST, 0x0000 }, | |
187 | { NAU8824_REG_FEPGA, 0x0000 }, | |
188 | { NAU8824_REG_FEPGA_II, 0x0000 }, | |
189 | { NAU8824_REG_FEPGA_SE, 0x0000 }, | |
190 | { NAU8824_REG_FEPGA_ATTENUATION, 0x0000 }, | |
191 | { NAU8824_REG_ATT_PORT0, 0x0000 }, | |
192 | { NAU8824_REG_ATT_PORT1, 0x0000 }, | |
193 | { NAU8824_REG_POWER_UP_CONTROL, 0x0000 }, | |
194 | { NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 }, | |
195 | { NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 }, | |
196 | }; | |
197 | ||
198 | static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout) | |
199 | { | |
200 | int ret; | |
201 | ||
202 | if (timeout) { | |
203 | ret = down_timeout(&nau8824->jd_sem, timeout); | |
204 | if (ret < 0) | |
2ce7eb25 | 205 | dev_warn(nau8824->dev, "Acquire semaphore timeout\n"); |
dfeabded JH |
206 | } else { |
207 | ret = down_interruptible(&nau8824->jd_sem); | |
208 | if (ret < 0) | |
2ce7eb25 | 209 | dev_warn(nau8824->dev, "Acquire semaphore fail\n"); |
dfeabded JH |
210 | } |
211 | ||
212 | return ret; | |
213 | } | |
214 | ||
215 | static inline void nau8824_sema_release(struct nau8824 *nau8824) | |
216 | { | |
217 | up(&nau8824->jd_sem); | |
218 | } | |
219 | ||
220 | static bool nau8824_readable_reg(struct device *dev, unsigned int reg) | |
221 | { | |
222 | switch (reg) { | |
223 | case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV: | |
224 | case NAU8824_REG_JACK_DET_CTRL: | |
225 | case NAU8824_REG_INTERRUPT_SETTING_1: | |
226 | case NAU8824_REG_IRQ: | |
227 | case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4: | |
228 | case NAU8824_REG_GPIO_SEL: | |
229 | case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL: | |
230 | case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5: | |
231 | case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST: | |
232 | case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3: | |
233 | case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1: | |
234 | case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE: | |
235 | case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2: | |
236 | case NAU8824_REG_I2C_TIMEOUT: | |
237 | case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT: | |
238 | case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2: | |
239 | case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1: | |
240 | case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT: | |
241 | return true; | |
242 | default: | |
243 | return false; | |
244 | } | |
245 | ||
246 | } | |
247 | ||
248 | static bool nau8824_writeable_reg(struct device *dev, unsigned int reg) | |
249 | { | |
250 | switch (reg) { | |
251 | case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV: | |
252 | case NAU8824_REG_JACK_DET_CTRL: | |
253 | case NAU8824_REG_INTERRUPT_SETTING_1: | |
254 | case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4: | |
255 | case NAU8824_REG_GPIO_SEL: | |
256 | case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL: | |
257 | case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5: | |
258 | case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST: | |
259 | case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01: | |
260 | case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01: | |
261 | case NAU8824_REG_DRC_SLOPE_ADC_CH01: | |
262 | case NAU8824_REG_DRC_ATKDCY_ADC_CH01: | |
263 | case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23: | |
264 | case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23: | |
265 | case NAU8824_REG_DRC_SLOPE_ADC_CH23: | |
266 | case NAU8824_REG_DRC_ATKDCY_ADC_CH23: | |
267 | case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC: | |
268 | case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE: | |
269 | case NAU8824_REG_I2C_TIMEOUT: | |
270 | case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2: | |
271 | case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1: | |
272 | case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL: | |
273 | return true; | |
274 | default: | |
275 | return false; | |
276 | } | |
277 | } | |
278 | ||
279 | static bool nau8824_volatile_reg(struct device *dev, unsigned int reg) | |
280 | { | |
281 | switch (reg) { | |
282 | case NAU8824_REG_RESET: | |
283 | case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG: | |
284 | case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3: | |
285 | case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1: | |
286 | case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2: | |
287 | case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT: | |
288 | case NAU8824_REG_CHARGE_PUMP_INPUT: | |
289 | return true; | |
290 | default: | |
291 | return false; | |
292 | } | |
293 | } | |
294 | ||
295 | static const char * const nau8824_companding[] = { | |
296 | "Off", "NC", "u-law", "A-law" }; | |
297 | ||
298 | static const struct soc_enum nau8824_companding_adc_enum = | |
299 | SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12, | |
300 | ARRAY_SIZE(nau8824_companding), nau8824_companding); | |
301 | ||
302 | static const struct soc_enum nau8824_companding_dac_enum = | |
303 | SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14, | |
304 | ARRAY_SIZE(nau8824_companding), nau8824_companding); | |
305 | ||
306 | static const char * const nau8824_adc_decimation[] = { | |
307 | "32", "64", "128", "256" }; | |
308 | ||
309 | static const struct soc_enum nau8824_adc_decimation_enum = | |
310 | SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0, | |
311 | ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation); | |
312 | ||
313 | static const char * const nau8824_dac_oversampl[] = { | |
314 | "64", "256", "128", "", "32" }; | |
315 | ||
316 | static const struct soc_enum nau8824_dac_oversampl_enum = | |
317 | SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0, | |
318 | ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl); | |
319 | ||
320 | static const char * const nau8824_input_channel[] = { | |
321 | "Input CH0", "Input CH1", "Input CH2", "Input CH3" }; | |
322 | ||
323 | static const struct soc_enum nau8824_adc_ch0_enum = | |
324 | SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9, | |
325 | ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); | |
326 | ||
327 | static const struct soc_enum nau8824_adc_ch1_enum = | |
328 | SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9, | |
329 | ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); | |
330 | ||
331 | static const struct soc_enum nau8824_adc_ch2_enum = | |
332 | SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9, | |
333 | ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); | |
334 | ||
335 | static const struct soc_enum nau8824_adc_ch3_enum = | |
336 | SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9, | |
337 | ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel); | |
338 | ||
339 | static const char * const nau8824_tdm_slot[] = { | |
340 | "Slot 0", "Slot 1", "Slot 2", "Slot 3" }; | |
341 | ||
342 | static const struct soc_enum nau8824_dac_left_sel_enum = | |
343 | SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6, | |
344 | ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot); | |
345 | ||
346 | static const struct soc_enum nau8824_dac_right_sel_enum = | |
347 | SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4, | |
348 | ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot); | |
349 | ||
350 | static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400); | |
351 | static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0); | |
352 | static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0); | |
353 | static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0); | |
354 | ||
355 | static const struct snd_kcontrol_new nau8824_snd_controls[] = { | |
356 | SOC_ENUM("ADC Companding", nau8824_companding_adc_enum), | |
357 | SOC_ENUM("DAC Companding", nau8824_companding_dac_enum), | |
358 | ||
359 | SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum), | |
360 | SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum), | |
361 | ||
25535f7e | 362 | SOC_SINGLE_TLV("Speaker Right DACR Volume", |
dfeabded | 363 | NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv), |
25535f7e | 364 | SOC_SINGLE_TLV("Speaker Left DACL Volume", |
dfeabded | 365 | NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv), |
25535f7e | 366 | SOC_SINGLE_TLV("Speaker Left DACR Volume", |
dfeabded | 367 | NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv), |
25535f7e | 368 | SOC_SINGLE_TLV("Speaker Right DACL Volume", |
dfeabded JH |
369 | NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv), |
370 | ||
25535f7e | 371 | SOC_SINGLE_TLV("Headphone Right DACR Volume", |
dfeabded | 372 | NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv), |
25535f7e | 373 | SOC_SINGLE_TLV("Headphone Left DACL Volume", |
dfeabded | 374 | NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv), |
25535f7e | 375 | SOC_SINGLE_TLV("Headphone Right DACL Volume", |
dfeabded | 376 | NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv), |
25535f7e | 377 | SOC_SINGLE_TLV("Headphone Left DACR Volume", |
dfeabded JH |
378 | NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv), |
379 | ||
25535f7e | 380 | SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II, |
dfeabded | 381 | NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv), |
25535f7e | 382 | SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II, |
dfeabded JH |
383 | NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv), |
384 | ||
385 | SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL, | |
386 | 0, 0x164, 0, dmic_vol_tlv), | |
387 | SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL, | |
388 | 0, 0x164, 0, dmic_vol_tlv), | |
389 | SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL, | |
390 | 0, 0x164, 0, dmic_vol_tlv), | |
391 | SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL, | |
392 | 0, 0x164, 0, dmic_vol_tlv), | |
393 | ||
394 | SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum), | |
395 | SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum), | |
396 | SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum), | |
397 | SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum), | |
398 | ||
399 | SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0), | |
400 | SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0), | |
401 | SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0), | |
402 | SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0), | |
403 | ||
404 | SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum), | |
405 | SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum), | |
406 | ||
407 | SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0), | |
408 | SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0), | |
7b0037fa JH |
409 | |
410 | SOC_SINGLE("THD for key media", | |
411 | NAU8824_REG_VDET_THRESHOLD_1, 8, 0xff, 0), | |
412 | SOC_SINGLE("THD for key voice command", | |
413 | NAU8824_REG_VDET_THRESHOLD_1, 0, 0xff, 0), | |
414 | SOC_SINGLE("THD for key volume up", | |
415 | NAU8824_REG_VDET_THRESHOLD_2, 8, 0xff, 0), | |
416 | SOC_SINGLE("THD for key volume down", | |
417 | NAU8824_REG_VDET_THRESHOLD_2, 0, 0xff, 0), | |
dfeabded JH |
418 | }; |
419 | ||
420 | static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w, | |
421 | struct snd_kcontrol *kcontrol, int event) | |
422 | { | |
12a72f91 KM |
423 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
424 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); | |
dfeabded JH |
425 | |
426 | switch (event) { | |
427 | case SND_SOC_DAPM_PRE_PMU: | |
428 | /* Disables the TESTDAC to let DAC signal pass through. */ | |
429 | regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO, | |
430 | NAU8824_TEST_DAC_EN, 0); | |
431 | break; | |
432 | case SND_SOC_DAPM_POST_PMD: | |
433 | regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO, | |
434 | NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN); | |
435 | break; | |
436 | default: | |
437 | return -EINVAL; | |
438 | } | |
439 | ||
440 | return 0; | |
441 | } | |
442 | ||
443 | static int nau8824_spk_event(struct snd_soc_dapm_widget *w, | |
444 | struct snd_kcontrol *kcontrol, int event) | |
445 | { | |
12a72f91 KM |
446 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
447 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); | |
dfeabded JH |
448 | |
449 | switch (event) { | |
450 | case SND_SOC_DAPM_PRE_PMU: | |
451 | regmap_update_bits(nau8824->regmap, | |
452 | NAU8824_REG_ANALOG_CONTROL_2, | |
453 | NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS); | |
454 | break; | |
455 | case SND_SOC_DAPM_POST_PMD: | |
456 | regmap_update_bits(nau8824->regmap, | |
457 | NAU8824_REG_ANALOG_CONTROL_2, | |
458 | NAU8824_CLASSD_CLAMP_DIS, 0); | |
459 | break; | |
460 | default: | |
461 | return -EINVAL; | |
462 | } | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | static int nau8824_pump_event(struct snd_soc_dapm_widget *w, | |
468 | struct snd_kcontrol *kcontrol, int event) | |
469 | { | |
12a72f91 KM |
470 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
471 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); | |
dfeabded JH |
472 | |
473 | switch (event) { | |
474 | case SND_SOC_DAPM_POST_PMU: | |
475 | /* Prevent startup click by letting charge pump to ramp up */ | |
476 | msleep(10); | |
477 | regmap_update_bits(nau8824->regmap, | |
478 | NAU8824_REG_CHARGE_PUMP_CONTROL, | |
479 | NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW); | |
480 | break; | |
481 | case SND_SOC_DAPM_PRE_PMD: | |
482 | regmap_update_bits(nau8824->regmap, | |
483 | NAU8824_REG_CHARGE_PUMP_CONTROL, | |
484 | NAU8824_JAMNODCLOW, 0); | |
485 | break; | |
486 | default: | |
487 | return -EINVAL; | |
488 | } | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
493 | static int system_clock_control(struct snd_soc_dapm_widget *w, | |
494 | struct snd_kcontrol *k, int event) | |
495 | { | |
12a72f91 KM |
496 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
497 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); | |
b53117c0 JH |
498 | struct regmap *regmap = nau8824->regmap; |
499 | unsigned int value; | |
500 | bool clk_fll, error; | |
dfeabded JH |
501 | |
502 | if (SND_SOC_DAPM_EVENT_OFF(event)) { | |
b53117c0 | 503 | dev_dbg(nau8824->dev, "system clock control : POWER OFF\n"); |
dfeabded JH |
504 | /* Set clock source to disable or internal clock before the |
505 | * playback or capture end. Codec needs clock for Jack | |
506 | * detection and button press if jack inserted; otherwise, | |
507 | * the clock should be closed. | |
508 | */ | |
509 | if (nau8824_is_jack_inserted(nau8824)) { | |
510 | nau8824_config_sysclk(nau8824, | |
511 | NAU8824_CLK_INTERNAL, 0); | |
512 | } else { | |
513 | nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); | |
514 | } | |
b53117c0 JH |
515 | } else { |
516 | dev_dbg(nau8824->dev, "system clock control : POWER ON\n"); | |
517 | /* Check the clock source setting is proper or not | |
518 | * no matter the source is from FLL or MCLK. | |
519 | */ | |
520 | regmap_read(regmap, NAU8824_REG_FLL1, &value); | |
521 | clk_fll = value & NAU8824_FLL_RATIO_MASK; | |
522 | /* It's error to use internal clock when playback */ | |
523 | regmap_read(regmap, NAU8824_REG_FLL6, &value); | |
524 | error = value & NAU8824_DCO_EN; | |
525 | if (!error) { | |
526 | /* Check error depending on source is FLL or MCLK. */ | |
527 | regmap_read(regmap, NAU8824_REG_CLK_DIVIDER, &value); | |
528 | if (clk_fll) | |
529 | error = !(value & NAU8824_CLK_SRC_VCO); | |
530 | else | |
531 | error = value & NAU8824_CLK_SRC_VCO; | |
532 | } | |
533 | /* Recover the clock source setting if error. */ | |
534 | if (error) { | |
535 | if (clk_fll) { | |
536 | regmap_update_bits(regmap, | |
537 | NAU8824_REG_FLL6, NAU8824_DCO_EN, 0); | |
538 | regmap_update_bits(regmap, | |
539 | NAU8824_REG_CLK_DIVIDER, | |
540 | NAU8824_CLK_SRC_MASK, | |
541 | NAU8824_CLK_SRC_VCO); | |
542 | } else { | |
543 | nau8824_config_sysclk(nau8824, | |
544 | NAU8824_CLK_MCLK, 0); | |
545 | } | |
546 | } | |
dfeabded | 547 | } |
b53117c0 | 548 | |
dfeabded JH |
549 | return 0; |
550 | } | |
551 | ||
552 | static int dmic_clock_control(struct snd_soc_dapm_widget *w, | |
553 | struct snd_kcontrol *k, int event) | |
554 | { | |
12a72f91 KM |
555 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
556 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); | |
dfeabded JH |
557 | int src; |
558 | ||
559 | /* The DMIC clock is gotten from system clock (256fs) divided by | |
560 | * DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or | |
561 | * less than 3.072 MHz. | |
562 | */ | |
563 | for (src = 0; src < 5; src++) { | |
564 | if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK) | |
565 | break; | |
566 | } | |
567 | dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256); | |
568 | regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, | |
569 | NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT)); | |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
574 | static const struct snd_kcontrol_new nau8824_adc_ch0_dmic = | |
575 | SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, | |
576 | NAU8824_ADC_CH0_DMIC_SFT, 1, 0); | |
577 | ||
578 | static const struct snd_kcontrol_new nau8824_adc_ch1_dmic = | |
579 | SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, | |
580 | NAU8824_ADC_CH1_DMIC_SFT, 1, 0); | |
581 | ||
582 | static const struct snd_kcontrol_new nau8824_adc_ch2_dmic = | |
583 | SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, | |
584 | NAU8824_ADC_CH2_DMIC_SFT, 1, 0); | |
585 | ||
586 | static const struct snd_kcontrol_new nau8824_adc_ch3_dmic = | |
587 | SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL, | |
588 | NAU8824_ADC_CH3_DMIC_SFT, 1, 0); | |
589 | ||
590 | static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = { | |
591 | SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA, | |
592 | NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0), | |
593 | SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA, | |
594 | NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0), | |
595 | }; | |
596 | ||
597 | static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = { | |
598 | SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA, | |
599 | NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0), | |
600 | SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA, | |
601 | NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0), | |
602 | }; | |
603 | ||
604 | static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = { | |
605 | SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO, | |
606 | NAU8824_DACR_HPL_EN_SFT, 1, 0), | |
607 | SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO, | |
608 | NAU8824_DACL_HPL_EN_SFT, 1, 0), | |
609 | }; | |
610 | ||
611 | static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = { | |
612 | SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO, | |
613 | NAU8824_DACL_HPR_EN_SFT, 1, 0), | |
614 | SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO, | |
615 | NAU8824_DACR_HPR_EN_SFT, 1, 0), | |
616 | }; | |
617 | ||
618 | static const char * const nau8824_dac_src[] = { "DACL", "DACR" }; | |
619 | ||
620 | static SOC_ENUM_SINGLE_DECL( | |
621 | nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL, | |
622 | NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src); | |
623 | ||
624 | static SOC_ENUM_SINGLE_DECL( | |
625 | nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL, | |
626 | NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src); | |
627 | ||
628 | static const struct snd_kcontrol_new nau8824_dacl_mux = | |
629 | SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum); | |
630 | ||
631 | static const struct snd_kcontrol_new nau8824_dacr_mux = | |
632 | SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum); | |
633 | ||
634 | ||
635 | static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = { | |
636 | SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, | |
b53117c0 JH |
637 | system_clock_control, SND_SOC_DAPM_POST_PMD | |
638 | SND_SOC_DAPM_POST_PMU), | |
dfeabded JH |
639 | |
640 | SND_SOC_DAPM_INPUT("HSMIC1"), | |
641 | SND_SOC_DAPM_INPUT("HSMIC2"), | |
642 | SND_SOC_DAPM_INPUT("MIC1"), | |
643 | SND_SOC_DAPM_INPUT("MIC2"), | |
644 | SND_SOC_DAPM_INPUT("DMIC1"), | |
645 | SND_SOC_DAPM_INPUT("DMIC2"), | |
646 | SND_SOC_DAPM_INPUT("DMIC3"), | |
647 | SND_SOC_DAPM_INPUT("DMIC4"), | |
648 | ||
649 | SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC, | |
650 | NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0), | |
651 | SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS, | |
652 | NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0), | |
653 | SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ, | |
654 | NAU8824_DMIC1_EN_SFT, 0, NULL, 0), | |
655 | SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ, | |
656 | NAU8824_DMIC2_EN_SFT, 0, NULL, 0), | |
657 | SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0, | |
658 | dmic_clock_control, SND_SOC_DAPM_POST_PMU), | |
659 | ||
660 | SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM, | |
661 | 0, 0, &nau8824_adc_ch0_dmic), | |
662 | SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM, | |
663 | 0, 0, &nau8824_adc_ch1_dmic), | |
664 | SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM, | |
665 | 0, 0, &nau8824_adc_ch2_dmic), | |
666 | SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM, | |
667 | 0, 0, &nau8824_adc_ch3_dmic), | |
668 | ||
669 | SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL, | |
670 | 12, 0, nau8824_adc_left_mixer, | |
671 | ARRAY_SIZE(nau8824_adc_left_mixer)), | |
672 | SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL, | |
673 | 13, 0, nau8824_adc_right_mixer, | |
674 | ARRAY_SIZE(nau8824_adc_right_mixer)), | |
675 | ||
676 | SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2, | |
677 | NAU8824_ADCL_EN_SFT, 0), | |
678 | SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2, | |
679 | NAU8824_ADCR_EN_SFT, 0), | |
680 | ||
844a4a36 JH |
681 | SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0), |
682 | SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0), | |
dfeabded JH |
683 | |
684 | SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC, | |
685 | NAU8824_DACL_EN_SFT, 0), | |
686 | SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC, | |
687 | NAU8824_DACL_CLK_SFT, 0, NULL, 0), | |
688 | SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC, | |
689 | NAU8824_DACR_EN_SFT, 0), | |
690 | SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC, | |
691 | NAU8824_DACR_CLK_SFT, 0, NULL, 0), | |
692 | ||
693 | SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux), | |
694 | SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux), | |
695 | ||
696 | SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL, | |
697 | 8, 1, nau8824_output_dac_event, | |
698 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
699 | SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL, | |
700 | 9, 1, nau8824_output_dac_event, | |
701 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
702 | ||
703 | SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1, | |
704 | NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event, | |
705 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
706 | ||
707 | SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG, | |
708 | NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer, | |
709 | ARRAY_SIZE(nau8824_hp_left_mixer)), | |
710 | SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG, | |
711 | NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer, | |
712 | ARRAY_SIZE(nau8824_hp_right_mixer)), | |
713 | SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL, | |
714 | NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event, | |
715 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
716 | SND_SOC_DAPM_PGA("Output Driver L", | |
717 | NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0), | |
718 | SND_SOC_DAPM_PGA("Output Driver R", | |
719 | NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0), | |
720 | SND_SOC_DAPM_PGA("Main Driver L", | |
721 | NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0), | |
722 | SND_SOC_DAPM_PGA("Main Driver R", | |
723 | NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0), | |
724 | SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST, | |
725 | NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0), | |
726 | SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG, | |
727 | NAU8824_CLASSG_EN_SFT, 0, NULL, 0), | |
728 | ||
729 | SND_SOC_DAPM_OUTPUT("SPKOUTL"), | |
730 | SND_SOC_DAPM_OUTPUT("SPKOUTR"), | |
731 | SND_SOC_DAPM_OUTPUT("HPOL"), | |
732 | SND_SOC_DAPM_OUTPUT("HPOR"), | |
733 | }; | |
734 | ||
735 | static const struct snd_soc_dapm_route nau8824_dapm_routes[] = { | |
736 | {"DMIC1 Enable", "Switch", "DMIC1"}, | |
737 | {"DMIC2 Enable", "Switch", "DMIC2"}, | |
738 | {"DMIC3 Enable", "Switch", "DMIC3"}, | |
739 | {"DMIC4 Enable", "Switch", "DMIC4"}, | |
740 | ||
741 | {"DMIC1", NULL, "DMIC12 Power"}, | |
742 | {"DMIC2", NULL, "DMIC12 Power"}, | |
743 | {"DMIC3", NULL, "DMIC34 Power"}, | |
744 | {"DMIC4", NULL, "DMIC34 Power"}, | |
745 | {"DMIC12 Power", NULL, "DMIC Clock"}, | |
746 | {"DMIC34 Power", NULL, "DMIC Clock"}, | |
747 | ||
748 | {"Left ADC", "MIC Switch", "MIC1"}, | |
749 | {"Left ADC", "HSMIC Switch", "HSMIC1"}, | |
750 | {"Right ADC", "MIC Switch", "MIC2"}, | |
751 | {"Right ADC", "HSMIC Switch", "HSMIC2"}, | |
752 | ||
753 | {"ADCL", NULL, "Left ADC"}, | |
754 | {"ADCR", NULL, "Right ADC"}, | |
755 | ||
756 | {"AIFTX", NULL, "MICBIAS"}, | |
757 | {"AIFTX", NULL, "ADCL"}, | |
758 | {"AIFTX", NULL, "ADCR"}, | |
759 | {"AIFTX", NULL, "DMIC1 Enable"}, | |
760 | {"AIFTX", NULL, "DMIC2 Enable"}, | |
761 | {"AIFTX", NULL, "DMIC3 Enable"}, | |
762 | {"AIFTX", NULL, "DMIC4 Enable"}, | |
763 | ||
764 | {"AIFTX", NULL, "System Clock"}, | |
765 | {"AIFRX", NULL, "System Clock"}, | |
766 | ||
767 | {"DACL", NULL, "AIFRX"}, | |
768 | {"DACL", NULL, "DACL Clock"}, | |
769 | {"DACR", NULL, "AIFRX"}, | |
770 | {"DACR", NULL, "DACR Clock"}, | |
771 | ||
772 | {"DACL Mux", "DACL", "DACL"}, | |
773 | {"DACL Mux", "DACR", "DACR"}, | |
774 | {"DACR Mux", "DACL", "DACL"}, | |
775 | {"DACR Mux", "DACR", "DACR"}, | |
776 | ||
777 | {"Output DACL", NULL, "DACL Mux"}, | |
778 | {"Output DACR", NULL, "DACR Mux"}, | |
779 | ||
780 | {"ClassD", NULL, "Output DACL"}, | |
781 | {"ClassD", NULL, "Output DACR"}, | |
782 | ||
783 | {"Left Headphone", "DAC Left Switch", "Output DACL"}, | |
784 | {"Left Headphone", "DAC Right Switch", "Output DACR"}, | |
785 | {"Right Headphone", "DAC Left Switch", "Output DACL"}, | |
786 | {"Right Headphone", "DAC Right Switch", "Output DACR"}, | |
787 | ||
788 | {"Charge Pump", NULL, "Left Headphone"}, | |
789 | {"Charge Pump", NULL, "Right Headphone"}, | |
790 | {"Output Driver L", NULL, "Charge Pump"}, | |
791 | {"Output Driver R", NULL, "Charge Pump"}, | |
792 | {"Main Driver L", NULL, "Output Driver L"}, | |
793 | {"Main Driver R", NULL, "Output Driver R"}, | |
794 | {"Class G", NULL, "Main Driver L"}, | |
795 | {"Class G", NULL, "Main Driver R"}, | |
796 | {"HP Boost Driver", NULL, "Class G"}, | |
797 | ||
798 | {"SPKOUTL", NULL, "ClassD"}, | |
799 | {"SPKOUTR", NULL, "ClassD"}, | |
800 | {"HPOL", NULL, "HP Boost Driver"}, | |
801 | {"HPOR", NULL, "HP Boost Driver"}, | |
802 | }; | |
803 | ||
804 | static bool nau8824_is_jack_inserted(struct nau8824 *nau8824) | |
805 | { | |
806 | struct snd_soc_jack *jack = nau8824->jack; | |
290da7a7 | 807 | bool insert = false; |
dfeabded JH |
808 | |
809 | if (nau8824->irq && jack) | |
810 | insert = jack->status & SND_JACK_HEADPHONE; | |
811 | ||
812 | return insert; | |
813 | } | |
814 | ||
815 | static void nau8824_int_status_clear_all(struct regmap *regmap) | |
816 | { | |
817 | int active_irq, clear_irq, i; | |
818 | ||
819 | /* Reset the intrruption status from rightmost bit if the corres- | |
820 | * ponding irq event occurs. | |
821 | */ | |
822 | regmap_read(regmap, NAU8824_REG_IRQ, &active_irq); | |
823 | for (i = 0; i < NAU8824_REG_DATA_LEN; i++) { | |
824 | clear_irq = (0x1 << i); | |
825 | if (active_irq & clear_irq) | |
826 | regmap_write(regmap, | |
827 | NAU8824_REG_CLEAR_INT_REG, clear_irq); | |
828 | } | |
829 | } | |
830 | ||
844a4a36 JH |
831 | static void nau8824_dapm_disable_pin(struct nau8824 *nau8824, const char *pin) |
832 | { | |
833 | struct snd_soc_dapm_context *dapm = nau8824->dapm; | |
834 | const char *prefix = dapm->component->name_prefix; | |
835 | char prefixed_pin[80]; | |
836 | ||
837 | if (prefix) { | |
838 | snprintf(prefixed_pin, sizeof(prefixed_pin), "%s %s", | |
839 | prefix, pin); | |
840 | snd_soc_dapm_disable_pin(dapm, prefixed_pin); | |
841 | } else { | |
842 | snd_soc_dapm_disable_pin(dapm, pin); | |
843 | } | |
844 | } | |
845 | ||
846 | static void nau8824_dapm_enable_pin(struct nau8824 *nau8824, const char *pin) | |
847 | { | |
848 | struct snd_soc_dapm_context *dapm = nau8824->dapm; | |
849 | const char *prefix = dapm->component->name_prefix; | |
850 | char prefixed_pin[80]; | |
851 | ||
852 | if (prefix) { | |
853 | snprintf(prefixed_pin, sizeof(prefixed_pin), "%s %s", | |
854 | prefix, pin); | |
855 | snd_soc_dapm_force_enable_pin(dapm, prefixed_pin); | |
856 | } else { | |
857 | snd_soc_dapm_force_enable_pin(dapm, pin); | |
858 | } | |
859 | } | |
860 | ||
dfeabded JH |
861 | static void nau8824_eject_jack(struct nau8824 *nau8824) |
862 | { | |
863 | struct snd_soc_dapm_context *dapm = nau8824->dapm; | |
864 | struct regmap *regmap = nau8824->regmap; | |
865 | ||
866 | /* Clear all interruption status */ | |
867 | nau8824_int_status_clear_all(regmap); | |
868 | ||
844a4a36 JH |
869 | nau8824_dapm_disable_pin(nau8824, "SAR"); |
870 | nau8824_dapm_disable_pin(nau8824, "MICBIAS"); | |
dfeabded JH |
871 | snd_soc_dapm_sync(dapm); |
872 | ||
873 | /* Enable the insertion interruption, disable the ejection | |
874 | * interruption, and then bypass de-bounce circuit. | |
875 | */ | |
876 | regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, | |
877 | NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS | | |
878 | NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, | |
879 | NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS | | |
880 | NAU8824_IRQ_EJECT_DIS); | |
881 | regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1, | |
882 | NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN, | |
883 | NAU8824_IRQ_INSERT_EN); | |
884 | regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, | |
885 | NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); | |
886 | ||
887 | /* Close clock for jack type detection at manual mode */ | |
a2eb62ed JH |
888 | if (dapm->bias_level < SND_SOC_BIAS_PREPARE) |
889 | nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); | |
dfeabded JH |
890 | } |
891 | ||
892 | static void nau8824_jdet_work(struct work_struct *work) | |
893 | { | |
894 | struct nau8824 *nau8824 = container_of( | |
895 | work, struct nau8824, jdet_work); | |
896 | struct snd_soc_dapm_context *dapm = nau8824->dapm; | |
897 | struct regmap *regmap = nau8824->regmap; | |
898 | int adc_value, event = 0, event_mask = 0; | |
899 | ||
844a4a36 JH |
900 | nau8824_dapm_enable_pin(nau8824, "MICBIAS"); |
901 | nau8824_dapm_enable_pin(nau8824, "SAR"); | |
dfeabded JH |
902 | snd_soc_dapm_sync(dapm); |
903 | ||
904 | msleep(100); | |
905 | ||
906 | regmap_read(regmap, NAU8824_REG_SAR_ADC_DATA_OUT, &adc_value); | |
907 | adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK; | |
908 | dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value); | |
909 | if (adc_value < HEADSET_SARADC_THD) { | |
910 | event |= SND_JACK_HEADPHONE; | |
911 | ||
844a4a36 JH |
912 | nau8824_dapm_disable_pin(nau8824, "SAR"); |
913 | nau8824_dapm_disable_pin(nau8824, "MICBIAS"); | |
dfeabded JH |
914 | snd_soc_dapm_sync(dapm); |
915 | } else { | |
916 | event |= SND_JACK_HEADSET; | |
917 | } | |
918 | event_mask |= SND_JACK_HEADSET; | |
919 | snd_soc_jack_report(nau8824->jack, event, event_mask); | |
920 | ||
cf6b68d1 JH |
921 | /* Enable short key press and release interruption. */ |
922 | regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, | |
923 | NAU8824_IRQ_KEY_RELEASE_DIS | | |
924 | NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0); | |
925 | ||
dfeabded JH |
926 | nau8824_sema_release(nau8824); |
927 | } | |
928 | ||
929 | static void nau8824_setup_auto_irq(struct nau8824 *nau8824) | |
930 | { | |
931 | struct regmap *regmap = nau8824->regmap; | |
932 | ||
cf6b68d1 | 933 | /* Enable jack ejection interruption. */ |
dfeabded JH |
934 | regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1, |
935 | NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN, | |
936 | NAU8824_IRQ_EJECT_EN); | |
937 | regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING, | |
cf6b68d1 | 938 | NAU8824_IRQ_EJECT_DIS, 0); |
dfeabded | 939 | /* Enable internal VCO needed for interruptions */ |
a2eb62ed JH |
940 | if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE) |
941 | nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0); | |
dfeabded JH |
942 | regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, |
943 | NAU8824_JD_SLEEP_MODE, 0); | |
944 | } | |
945 | ||
946 | static int nau8824_button_decode(int value) | |
947 | { | |
948 | int buttons = 0; | |
949 | ||
950 | /* The chip supports up to 8 buttons, but ALSA defines | |
951 | * only 6 buttons. | |
952 | */ | |
953 | if (value & BIT(0)) | |
954 | buttons |= SND_JACK_BTN_0; | |
955 | if (value & BIT(1)) | |
956 | buttons |= SND_JACK_BTN_1; | |
957 | if (value & BIT(2)) | |
958 | buttons |= SND_JACK_BTN_2; | |
959 | if (value & BIT(3)) | |
960 | buttons |= SND_JACK_BTN_3; | |
961 | if (value & BIT(4)) | |
962 | buttons |= SND_JACK_BTN_4; | |
963 | if (value & BIT(5)) | |
964 | buttons |= SND_JACK_BTN_5; | |
965 | ||
966 | return buttons; | |
967 | } | |
968 | ||
969 | #define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \ | |
970 | SND_JACK_BTN_2 | SND_JACK_BTN_3) | |
971 | ||
972 | static irqreturn_t nau8824_interrupt(int irq, void *data) | |
973 | { | |
974 | struct nau8824 *nau8824 = (struct nau8824 *)data; | |
975 | struct regmap *regmap = nau8824->regmap; | |
976 | int active_irq, clear_irq = 0, event = 0, event_mask = 0; | |
977 | ||
978 | if (regmap_read(regmap, NAU8824_REG_IRQ, &active_irq)) { | |
979 | dev_err(nau8824->dev, "failed to read irq status\n"); | |
980 | return IRQ_NONE; | |
981 | } | |
982 | dev_dbg(nau8824->dev, "IRQ %x\n", active_irq); | |
983 | ||
984 | if (active_irq & NAU8824_JACK_EJECTION_DETECTED) { | |
985 | nau8824_eject_jack(nau8824); | |
986 | event_mask |= SND_JACK_HEADSET; | |
987 | clear_irq = NAU8824_JACK_EJECTION_DETECTED; | |
988 | /* release semaphore held after resume, | |
989 | * and cancel jack detection | |
990 | */ | |
991 | nau8824_sema_release(nau8824); | |
992 | cancel_work_sync(&nau8824->jdet_work); | |
993 | } else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) { | |
994 | int key_status, button_pressed; | |
995 | ||
996 | regmap_read(regmap, NAU8824_REG_CLEAR_INT_REG, | |
997 | &key_status); | |
998 | ||
999 | /* lower 8 bits of the register are for pressed keys */ | |
1000 | button_pressed = nau8824_button_decode(key_status); | |
1001 | ||
1002 | event |= button_pressed; | |
1003 | dev_dbg(nau8824->dev, "button %x pressed\n", event); | |
1004 | event_mask |= NAU8824_BUTTONS; | |
1005 | clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ; | |
1006 | } else if (active_irq & NAU8824_KEY_RELEASE_IRQ) { | |
1007 | event_mask = NAU8824_BUTTONS; | |
1008 | clear_irq = NAU8824_KEY_RELEASE_IRQ; | |
1009 | } else if (active_irq & NAU8824_JACK_INSERTION_DETECTED) { | |
1010 | /* Turn off insertion interruption at manual mode */ | |
1011 | regmap_update_bits(regmap, | |
1012 | NAU8824_REG_INTERRUPT_SETTING, | |
1013 | NAU8824_IRQ_INSERT_DIS, | |
1014 | NAU8824_IRQ_INSERT_DIS); | |
1015 | regmap_update_bits(regmap, | |
1016 | NAU8824_REG_INTERRUPT_SETTING_1, | |
1017 | NAU8824_IRQ_INSERT_EN, 0); | |
1018 | /* detect microphone and jack type */ | |
1019 | cancel_work_sync(&nau8824->jdet_work); | |
1020 | schedule_work(&nau8824->jdet_work); | |
1021 | ||
1022 | /* Enable interruption for jack type detection at audo | |
1023 | * mode which can detect microphone and jack type. | |
1024 | */ | |
1025 | nau8824_setup_auto_irq(nau8824); | |
1026 | } | |
1027 | ||
1028 | if (!clear_irq) | |
1029 | clear_irq = active_irq; | |
1030 | /* clears the rightmost interruption */ | |
1031 | regmap_write(regmap, NAU8824_REG_CLEAR_INT_REG, clear_irq); | |
1032 | ||
1033 | if (event_mask) | |
1034 | snd_soc_jack_report(nau8824->jack, event, event_mask); | |
1035 | ||
1036 | return IRQ_HANDLED; | |
1037 | } | |
1038 | ||
1039 | static int nau8824_clock_check(struct nau8824 *nau8824, | |
1040 | int stream, int rate, int osr) | |
1041 | { | |
1042 | int osrate; | |
1043 | ||
1044 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
1045 | if (osr >= ARRAY_SIZE(osr_dac_sel)) | |
1046 | return -EINVAL; | |
1047 | osrate = osr_dac_sel[osr].osr; | |
1048 | } else { | |
1049 | if (osr >= ARRAY_SIZE(osr_adc_sel)) | |
1050 | return -EINVAL; | |
1051 | osrate = osr_adc_sel[osr].osr; | |
1052 | } | |
1053 | ||
1054 | if (!osrate || rate * osr > CLK_DA_AD_MAX) { | |
1055 | dev_err(nau8824->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n"); | |
1056 | return -EINVAL; | |
1057 | } | |
1058 | ||
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | static int nau8824_hw_params(struct snd_pcm_substream *substream, | |
1063 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
1064 | { | |
12a72f91 KM |
1065 | struct snd_soc_component *component = dai->component; |
1066 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); | |
dfeabded JH |
1067 | unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div; |
1068 | ||
1069 | nau8824_sema_acquire(nau8824, HZ); | |
1070 | ||
1071 | /* CLK_DAC or CLK_ADC = OSR * FS | |
1072 | * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) | |
1073 | * multiplied by the audio sample rate (Fs). Note that the OSR and Fs | |
1074 | * values must be selected such that the maximum frequency is less | |
1075 | * than 6.144 MHz. | |
1076 | */ | |
1077 | nau8824->fs = params_rate(params); | |
1078 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
1079 | regmap_read(nau8824->regmap, | |
1080 | NAU8824_REG_DAC_FILTER_CTRL_1, &osr); | |
1081 | osr &= NAU8824_DAC_OVERSAMPLE_MASK; | |
1082 | if (nau8824_clock_check(nau8824, substream->stream, | |
1083 | nau8824->fs, osr)) | |
1084 | return -EINVAL; | |
1085 | regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, | |
1086 | NAU8824_CLK_DAC_SRC_MASK, | |
1087 | osr_dac_sel[osr].clk_src << NAU8824_CLK_DAC_SRC_SFT); | |
1088 | } else { | |
1089 | regmap_read(nau8824->regmap, | |
1090 | NAU8824_REG_ADC_FILTER_CTRL, &osr); | |
1091 | osr &= NAU8824_ADC_SYNC_DOWN_MASK; | |
1092 | if (nau8824_clock_check(nau8824, substream->stream, | |
1093 | nau8824->fs, osr)) | |
1094 | return -EINVAL; | |
1095 | regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, | |
1096 | NAU8824_CLK_ADC_SRC_MASK, | |
1097 | osr_adc_sel[osr].clk_src << NAU8824_CLK_ADC_SRC_SFT); | |
1098 | } | |
1099 | ||
1100 | /* make BCLK and LRC divde configuration if the codec as master. */ | |
1101 | regmap_read(nau8824->regmap, | |
1102 | NAU8824_REG_PORT0_I2S_PCM_CTRL_2, &ctrl_val); | |
1103 | if (ctrl_val & NAU8824_I2S_MS_MASTER) { | |
1104 | /* get the bclk and fs ratio */ | |
1105 | bclk_fs = snd_soc_params_to_bclk(params) / nau8824->fs; | |
1106 | if (bclk_fs <= 32) | |
1107 | bclk_div = 0x3; | |
1108 | else if (bclk_fs <= 64) | |
1109 | bclk_div = 0x2; | |
1110 | else if (bclk_fs <= 128) | |
1111 | bclk_div = 0x1; | |
1112 | else if (bclk_fs <= 256) | |
1113 | bclk_div = 0; | |
1114 | else | |
1115 | return -EINVAL; | |
1116 | regmap_update_bits(nau8824->regmap, | |
1117 | NAU8824_REG_PORT0_I2S_PCM_CTRL_2, | |
1118 | NAU8824_I2S_LRC_DIV_MASK | NAU8824_I2S_BLK_DIV_MASK, | |
1119 | (bclk_div << NAU8824_I2S_LRC_DIV_SFT) | bclk_div); | |
1120 | } | |
1121 | ||
1122 | switch (params_width(params)) { | |
1123 | case 16: | |
1124 | val_len |= NAU8824_I2S_DL_16; | |
1125 | break; | |
1126 | case 20: | |
1127 | val_len |= NAU8824_I2S_DL_20; | |
1128 | break; | |
1129 | case 24: | |
1130 | val_len |= NAU8824_I2S_DL_24; | |
1131 | break; | |
1132 | case 32: | |
1133 | val_len |= NAU8824_I2S_DL_32; | |
1134 | break; | |
1135 | default: | |
1136 | return -EINVAL; | |
1137 | } | |
1138 | ||
1139 | regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1, | |
1140 | NAU8824_I2S_DL_MASK, val_len); | |
1141 | ||
1142 | nau8824_sema_release(nau8824); | |
1143 | ||
1144 | return 0; | |
1145 | } | |
1146 | ||
1147 | static int nau8824_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
1148 | { | |
12a72f91 KM |
1149 | struct snd_soc_component *component = dai->component; |
1150 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); | |
dfeabded JH |
1151 | unsigned int ctrl1_val = 0, ctrl2_val = 0; |
1152 | ||
1153 | nau8824_sema_acquire(nau8824, HZ); | |
1154 | ||
1155 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1156 | case SND_SOC_DAIFMT_CBM_CFM: | |
1157 | ctrl2_val |= NAU8824_I2S_MS_MASTER; | |
1158 | break; | |
1159 | case SND_SOC_DAIFMT_CBS_CFS: | |
1160 | break; | |
1161 | default: | |
1162 | return -EINVAL; | |
1163 | } | |
1164 | ||
1165 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1166 | case SND_SOC_DAIFMT_NB_NF: | |
1167 | break; | |
1168 | case SND_SOC_DAIFMT_IB_NF: | |
1169 | ctrl1_val |= NAU8824_I2S_BP_INV; | |
1170 | break; | |
1171 | default: | |
1172 | return -EINVAL; | |
1173 | } | |
1174 | ||
1175 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1176 | case SND_SOC_DAIFMT_I2S: | |
1177 | ctrl1_val |= NAU8824_I2S_DF_I2S; | |
1178 | break; | |
1179 | case SND_SOC_DAIFMT_LEFT_J: | |
1180 | ctrl1_val |= NAU8824_I2S_DF_LEFT; | |
1181 | break; | |
1182 | case SND_SOC_DAIFMT_RIGHT_J: | |
1183 | ctrl1_val |= NAU8824_I2S_DF_RIGTH; | |
1184 | break; | |
1185 | case SND_SOC_DAIFMT_DSP_A: | |
1186 | ctrl1_val |= NAU8824_I2S_DF_PCM_AB; | |
1187 | break; | |
1188 | case SND_SOC_DAIFMT_DSP_B: | |
1189 | ctrl1_val |= NAU8824_I2S_DF_PCM_AB; | |
1190 | ctrl1_val |= NAU8824_I2S_PCMB_EN; | |
1191 | break; | |
1192 | default: | |
1193 | return -EINVAL; | |
1194 | } | |
1195 | ||
1196 | regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1, | |
1197 | NAU8824_I2S_DF_MASK | NAU8824_I2S_BP_MASK | | |
1198 | NAU8824_I2S_PCMB_EN, ctrl1_val); | |
1199 | regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2, | |
1200 | NAU8824_I2S_MS_MASK, ctrl2_val); | |
1201 | ||
1202 | nau8824_sema_release(nau8824); | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | ||
fa101430 JH |
1207 | /** |
1208 | * nau8824_set_tdm_slot - configure DAI TDM. | |
1209 | * @dai: DAI | |
1210 | * @tx_mask: Bitmask representing active TX slots. Ex. | |
1211 | * 0xf for normal 4 channel TDM. | |
1212 | * 0xf0 for shifted 4 channel TDM | |
1213 | * @rx_mask: Bitmask [0:1] representing active DACR RX slots. | |
1214 | * Bitmask [2:3] representing active DACL RX slots. | |
1215 | * 00=CH0,01=CH1,10=CH2,11=CH3. Ex. | |
1216 | * 0xf for DACL/R selecting TDM CH3. | |
1217 | * 0xf0 for DACL/R selecting shifted TDM CH3. | |
1218 | * @slots: Number of slots in use. | |
1219 | * @slot_width: Width in bits for each slot. | |
1220 | * | |
1221 | * Configures a DAI for TDM operation. Only support 4 slots TDM. | |
1222 | */ | |
1223 | static int nau8824_set_tdm_slot(struct snd_soc_dai *dai, | |
1224 | unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) | |
1225 | { | |
12a72f91 KM |
1226 | struct snd_soc_component *component = dai->component; |
1227 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); | |
fa101430 JH |
1228 | unsigned int tslot_l = 0, ctrl_val = 0; |
1229 | ||
1230 | if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)) || | |
1231 | ((rx_mask & 0xf0) && (rx_mask & 0xf)) || | |
1232 | ((rx_mask & 0xf0) && (tx_mask & 0xf)) || | |
1233 | ((rx_mask & 0xf) && (tx_mask & 0xf0))) | |
1234 | return -EINVAL; | |
1235 | ||
1236 | ctrl_val |= (NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN); | |
1237 | if (tx_mask & 0xf0) { | |
1238 | tslot_l = 4 * slot_width; | |
1239 | ctrl_val |= (tx_mask >> 4); | |
1240 | } else { | |
1241 | ctrl_val |= tx_mask; | |
1242 | } | |
1243 | if (rx_mask & 0xf0) | |
1244 | ctrl_val |= ((rx_mask >> 4) << NAU8824_TDM_DACR_RX_SFT); | |
1245 | else | |
1246 | ctrl_val |= (rx_mask << NAU8824_TDM_DACR_RX_SFT); | |
1247 | ||
1248 | regmap_update_bits(nau8824->regmap, NAU8824_REG_TDM_CTRL, | |
1249 | NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN | | |
1250 | NAU8824_TDM_DACL_RX_MASK | NAU8824_TDM_DACR_RX_MASK | | |
1251 | NAU8824_TDM_TX_MASK, ctrl_val); | |
1252 | regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT, | |
1253 | NAU8824_TSLOT_L_MASK, tslot_l); | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
dfeabded JH |
1258 | /** |
1259 | * nau8824_calc_fll_param - Calculate FLL parameters. | |
1260 | * @fll_in: external clock provided to codec. | |
1261 | * @fs: sampling rate. | |
1262 | * @fll_param: Pointer to structure of FLL parameters. | |
1263 | * | |
1264 | * Calculate FLL parameters to configure codec. | |
1265 | * | |
1266 | * Returns 0 for success or negative error code. | |
1267 | */ | |
1268 | static int nau8824_calc_fll_param(unsigned int fll_in, | |
1269 | unsigned int fs, struct nau8824_fll *fll_param) | |
1270 | { | |
1271 | u64 fvco, fvco_max; | |
1272 | unsigned int fref, i, fvco_sel; | |
1273 | ||
1274 | /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing | |
1275 | * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. | |
1276 | * FREF = freq_in / NAU8824_FLL_REF_DIV_MASK | |
1277 | */ | |
1278 | for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { | |
1279 | fref = fll_in / fll_pre_scalar[i].param; | |
1280 | if (fref <= NAU_FREF_MAX) | |
1281 | break; | |
1282 | } | |
1283 | if (i == ARRAY_SIZE(fll_pre_scalar)) | |
1284 | return -EINVAL; | |
1285 | fll_param->clk_ref_div = fll_pre_scalar[i].val; | |
1286 | ||
1287 | /* Choose the FLL ratio based on FREF */ | |
1288 | for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { | |
1289 | if (fref >= fll_ratio[i].param) | |
1290 | break; | |
1291 | } | |
1292 | if (i == ARRAY_SIZE(fll_ratio)) | |
1293 | return -EINVAL; | |
1294 | fll_param->ratio = fll_ratio[i].val; | |
1295 | ||
1296 | /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. | |
1297 | * FDCO must be within the 90MHz - 124MHz or the FFL cannot be | |
1298 | * guaranteed across the full range of operation. | |
1299 | * FDCO = freq_out * 2 * mclk_src_scaling | |
1300 | */ | |
1301 | fvco_max = 0; | |
1302 | fvco_sel = ARRAY_SIZE(mclk_src_scaling); | |
1303 | for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { | |
f7ddff54 | 1304 | fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; |
dfeabded JH |
1305 | if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && |
1306 | fvco_max < fvco) { | |
1307 | fvco_max = fvco; | |
1308 | fvco_sel = i; | |
1309 | } | |
1310 | } | |
1311 | if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) | |
1312 | return -EINVAL; | |
1313 | fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; | |
1314 | ||
1315 | /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional | |
1316 | * input based on FDCO, FREF and FLL ratio. | |
1317 | */ | |
1318 | fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); | |
1319 | fll_param->fll_int = (fvco >> 16) & 0x3FF; | |
1320 | fll_param->fll_frac = fvco & 0xFFFF; | |
1321 | return 0; | |
1322 | } | |
1323 | ||
1324 | static void nau8824_fll_apply(struct regmap *regmap, | |
1325 | struct nau8824_fll *fll_param) | |
1326 | { | |
1327 | regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, | |
1328 | NAU8824_CLK_SRC_MASK | NAU8824_CLK_MCLK_SRC_MASK, | |
1329 | NAU8824_CLK_SRC_MCLK | fll_param->mclk_src); | |
1330 | regmap_update_bits(regmap, NAU8824_REG_FLL1, | |
1331 | NAU8824_FLL_RATIO_MASK, fll_param->ratio); | |
1332 | /* FLL 16-bit fractional input */ | |
1333 | regmap_write(regmap, NAU8824_REG_FLL2, fll_param->fll_frac); | |
1334 | /* FLL 10-bit integer input */ | |
1335 | regmap_update_bits(regmap, NAU8824_REG_FLL3, | |
1336 | NAU8824_FLL_INTEGER_MASK, fll_param->fll_int); | |
1337 | /* FLL pre-scaler */ | |
1338 | regmap_update_bits(regmap, NAU8824_REG_FLL4, | |
1339 | NAU8824_FLL_REF_DIV_MASK, | |
1340 | fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT); | |
1341 | /* select divided VCO input */ | |
1342 | regmap_update_bits(regmap, NAU8824_REG_FLL5, | |
1343 | NAU8824_FLL_CLK_SW_MASK, NAU8824_FLL_CLK_SW_REF); | |
1344 | /* Disable free-running mode */ | |
1345 | regmap_update_bits(regmap, | |
1346 | NAU8824_REG_FLL6, NAU8824_DCO_EN, 0); | |
1347 | if (fll_param->fll_frac) { | |
1348 | regmap_update_bits(regmap, NAU8824_REG_FLL5, | |
1349 | NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | | |
1350 | NAU8824_FLL_FTR_SW_MASK, | |
1351 | NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | | |
1352 | NAU8824_FLL_FTR_SW_FILTER); | |
1353 | regmap_update_bits(regmap, NAU8824_REG_FLL6, | |
1354 | NAU8824_SDM_EN, NAU8824_SDM_EN); | |
1355 | } else { | |
1356 | regmap_update_bits(regmap, NAU8824_REG_FLL5, | |
1357 | NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN | | |
1358 | NAU8824_FLL_FTR_SW_MASK, NAU8824_FLL_FTR_SW_ACCU); | |
1359 | regmap_update_bits(regmap, | |
1360 | NAU8824_REG_FLL6, NAU8824_SDM_EN, 0); | |
1361 | } | |
1362 | } | |
1363 | ||
1364 | /* freq_out must be 256*Fs in order to achieve the best performance */ | |
12a72f91 | 1365 | static int nau8824_set_pll(struct snd_soc_component *component, int pll_id, int source, |
dfeabded JH |
1366 | unsigned int freq_in, unsigned int freq_out) |
1367 | { | |
12a72f91 | 1368 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); |
dfeabded JH |
1369 | struct nau8824_fll fll_param; |
1370 | int ret, fs; | |
1371 | ||
1372 | fs = freq_out / 256; | |
1373 | ret = nau8824_calc_fll_param(freq_in, fs, &fll_param); | |
1374 | if (ret < 0) { | |
1375 | dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in); | |
1376 | return ret; | |
1377 | } | |
1378 | dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", | |
1379 | fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac, | |
1380 | fll_param.fll_int, fll_param.clk_ref_div); | |
1381 | ||
1382 | nau8824_fll_apply(nau8824->regmap, &fll_param); | |
1383 | mdelay(2); | |
1384 | regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, | |
1385 | NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO); | |
1386 | ||
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | static int nau8824_config_sysclk(struct nau8824 *nau8824, | |
1391 | int clk_id, unsigned int freq) | |
1392 | { | |
1393 | struct regmap *regmap = nau8824->regmap; | |
1394 | ||
1395 | switch (clk_id) { | |
1396 | case NAU8824_CLK_DIS: | |
1397 | regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, | |
1398 | NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK); | |
1399 | regmap_update_bits(regmap, NAU8824_REG_FLL6, | |
1400 | NAU8824_DCO_EN, 0); | |
1401 | break; | |
1402 | ||
1403 | case NAU8824_CLK_MCLK: | |
1404 | nau8824_sema_acquire(nau8824, HZ); | |
1405 | regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, | |
1406 | NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK); | |
1407 | regmap_update_bits(regmap, NAU8824_REG_FLL6, | |
1408 | NAU8824_DCO_EN, 0); | |
1409 | nau8824_sema_release(nau8824); | |
1410 | break; | |
1411 | ||
1412 | case NAU8824_CLK_INTERNAL: | |
1413 | regmap_update_bits(regmap, NAU8824_REG_FLL6, | |
1414 | NAU8824_DCO_EN, NAU8824_DCO_EN); | |
1415 | regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, | |
1416 | NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO); | |
1417 | break; | |
1418 | ||
1419 | case NAU8824_CLK_FLL_MCLK: | |
1420 | nau8824_sema_acquire(nau8824, HZ); | |
1421 | regmap_update_bits(regmap, NAU8824_REG_FLL3, | |
1422 | NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_MCLK); | |
1423 | nau8824_sema_release(nau8824); | |
1424 | break; | |
1425 | ||
1426 | case NAU8824_CLK_FLL_BLK: | |
1427 | nau8824_sema_acquire(nau8824, HZ); | |
1428 | regmap_update_bits(regmap, NAU8824_REG_FLL3, | |
1429 | NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_BLK); | |
1430 | nau8824_sema_release(nau8824); | |
1431 | break; | |
1432 | ||
1433 | case NAU8824_CLK_FLL_FS: | |
1434 | nau8824_sema_acquire(nau8824, HZ); | |
1435 | regmap_update_bits(regmap, NAU8824_REG_FLL3, | |
1436 | NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_FS); | |
1437 | nau8824_sema_release(nau8824); | |
1438 | break; | |
1439 | ||
1440 | default: | |
1441 | dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id); | |
1442 | return -EINVAL; | |
1443 | } | |
1444 | ||
1445 | dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq, | |
1446 | clk_id); | |
1447 | ||
1448 | return 0; | |
1449 | } | |
1450 | ||
12a72f91 | 1451 | static int nau8824_set_sysclk(struct snd_soc_component *component, |
dfeabded JH |
1452 | int clk_id, int source, unsigned int freq, int dir) |
1453 | { | |
12a72f91 | 1454 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); |
dfeabded JH |
1455 | |
1456 | return nau8824_config_sysclk(nau8824, clk_id, freq); | |
1457 | } | |
1458 | ||
1459 | static void nau8824_resume_setup(struct nau8824 *nau8824) | |
1460 | { | |
1461 | nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); | |
1462 | if (nau8824->irq) { | |
1463 | /* Clear all interruption status */ | |
1464 | nau8824_int_status_clear_all(nau8824->regmap); | |
1465 | /* Enable jack detection at sleep mode, insertion detection, | |
1466 | * and ejection detection. | |
1467 | */ | |
1468 | regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL, | |
1469 | NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); | |
1470 | regmap_update_bits(nau8824->regmap, | |
1471 | NAU8824_REG_INTERRUPT_SETTING_1, | |
1472 | NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, | |
1473 | NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN); | |
1474 | regmap_update_bits(nau8824->regmap, | |
1475 | NAU8824_REG_INTERRUPT_SETTING, | |
1476 | NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 0); | |
1477 | } | |
1478 | } | |
1479 | ||
12a72f91 | 1480 | static int nau8824_set_bias_level(struct snd_soc_component *component, |
dfeabded JH |
1481 | enum snd_soc_bias_level level) |
1482 | { | |
12a72f91 | 1483 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); |
dfeabded JH |
1484 | |
1485 | switch (level) { | |
1486 | case SND_SOC_BIAS_ON: | |
1487 | break; | |
1488 | ||
1489 | case SND_SOC_BIAS_PREPARE: | |
1490 | break; | |
1491 | ||
1492 | case SND_SOC_BIAS_STANDBY: | |
12a72f91 | 1493 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { |
dfeabded JH |
1494 | /* Setup codec configuration after resume */ |
1495 | nau8824_resume_setup(nau8824); | |
1496 | } | |
1497 | break; | |
1498 | ||
1499 | case SND_SOC_BIAS_OFF: | |
1500 | regmap_update_bits(nau8824->regmap, | |
1501 | NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff); | |
1502 | regmap_update_bits(nau8824->regmap, | |
1503 | NAU8824_REG_INTERRUPT_SETTING_1, | |
1504 | NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0); | |
1505 | break; | |
1506 | } | |
1507 | ||
1508 | return 0; | |
1509 | } | |
1510 | ||
12a72f91 | 1511 | static int nau8824_component_probe(struct snd_soc_component *component) |
dfeabded | 1512 | { |
12a72f91 KM |
1513 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); |
1514 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); | |
dfeabded JH |
1515 | |
1516 | nau8824->dapm = dapm; | |
1517 | ||
1518 | return 0; | |
1519 | } | |
1520 | ||
12a72f91 | 1521 | static int __maybe_unused nau8824_suspend(struct snd_soc_component *component) |
dfeabded | 1522 | { |
12a72f91 | 1523 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); |
dfeabded JH |
1524 | |
1525 | if (nau8824->irq) { | |
1526 | disable_irq(nau8824->irq); | |
12a72f91 | 1527 | snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); |
dfeabded JH |
1528 | } |
1529 | regcache_cache_only(nau8824->regmap, true); | |
1530 | regcache_mark_dirty(nau8824->regmap); | |
1531 | ||
1532 | return 0; | |
1533 | } | |
1534 | ||
12a72f91 | 1535 | static int __maybe_unused nau8824_resume(struct snd_soc_component *component) |
dfeabded | 1536 | { |
12a72f91 | 1537 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); |
dfeabded JH |
1538 | |
1539 | regcache_cache_only(nau8824->regmap, false); | |
1540 | regcache_sync(nau8824->regmap); | |
1541 | if (nau8824->irq) { | |
1542 | /* Hold semaphore to postpone playback happening | |
1543 | * until jack detection done. | |
1544 | */ | |
1545 | nau8824_sema_acquire(nau8824, 0); | |
1546 | enable_irq(nau8824->irq); | |
1547 | } | |
1548 | ||
1549 | return 0; | |
1550 | } | |
1551 | ||
12a72f91 KM |
1552 | static const struct snd_soc_component_driver nau8824_component_driver = { |
1553 | .probe = nau8824_component_probe, | |
1554 | .set_sysclk = nau8824_set_sysclk, | |
1555 | .set_pll = nau8824_set_pll, | |
1556 | .set_bias_level = nau8824_set_bias_level, | |
1557 | .suspend = nau8824_suspend, | |
1558 | .resume = nau8824_resume, | |
1559 | .controls = nau8824_snd_controls, | |
1560 | .num_controls = ARRAY_SIZE(nau8824_snd_controls), | |
1561 | .dapm_widgets = nau8824_dapm_widgets, | |
1562 | .num_dapm_widgets = ARRAY_SIZE(nau8824_dapm_widgets), | |
1563 | .dapm_routes = nau8824_dapm_routes, | |
1564 | .num_dapm_routes = ARRAY_SIZE(nau8824_dapm_routes), | |
1565 | .suspend_bias_off = 1, | |
1566 | .idle_bias_on = 1, | |
1567 | .use_pmdown_time = 1, | |
1568 | .endianness = 1, | |
1569 | .non_legacy_dai_naming = 1, | |
dfeabded JH |
1570 | }; |
1571 | ||
1572 | static const struct snd_soc_dai_ops nau8824_dai_ops = { | |
1573 | .hw_params = nau8824_hw_params, | |
1574 | .set_fmt = nau8824_set_fmt, | |
fa101430 | 1575 | .set_tdm_slot = nau8824_set_tdm_slot, |
dfeabded JH |
1576 | }; |
1577 | ||
1578 | #define NAU8824_RATES SNDRV_PCM_RATE_8000_192000 | |
1579 | #define NAU8824_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ | |
1580 | | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) | |
1581 | ||
1582 | static struct snd_soc_dai_driver nau8824_dai = { | |
1583 | .name = NAU8824_CODEC_DAI, | |
1584 | .playback = { | |
1585 | .stream_name = "Playback", | |
1586 | .channels_min = 1, | |
1587 | .channels_max = 2, | |
1588 | .rates = NAU8824_RATES, | |
1589 | .formats = NAU8824_FORMATS, | |
1590 | }, | |
1591 | .capture = { | |
1592 | .stream_name = "Capture", | |
1593 | .channels_min = 1, | |
1594 | .channels_max = 2, | |
1595 | .rates = NAU8824_RATES, | |
1596 | .formats = NAU8824_FORMATS, | |
1597 | }, | |
1598 | .ops = &nau8824_dai_ops, | |
1599 | }; | |
1600 | ||
1601 | static const struct regmap_config nau8824_regmap_config = { | |
1602 | .val_bits = NAU8824_REG_ADDR_LEN, | |
1603 | .reg_bits = NAU8824_REG_DATA_LEN, | |
1604 | ||
1605 | .max_register = NAU8824_REG_MAX, | |
1606 | .readable_reg = nau8824_readable_reg, | |
1607 | .writeable_reg = nau8824_writeable_reg, | |
1608 | .volatile_reg = nau8824_volatile_reg, | |
1609 | ||
1610 | .cache_type = REGCACHE_RBTREE, | |
1611 | .reg_defaults = nau8824_reg_defaults, | |
1612 | .num_reg_defaults = ARRAY_SIZE(nau8824_reg_defaults), | |
1613 | }; | |
1614 | ||
1615 | /** | |
1616 | * nau8824_enable_jack_detect - Specify a jack for event reporting | |
1617 | * | |
1618 | * @component: component to register the jack with | |
1619 | * @jack: jack to use to report headset and button events on | |
1620 | * | |
1621 | * After this function has been called the headset insert/remove and button | |
1622 | * events will be routed to the given jack. Jack can be null to stop | |
1623 | * reporting. | |
1624 | */ | |
12a72f91 | 1625 | int nau8824_enable_jack_detect(struct snd_soc_component *component, |
dfeabded JH |
1626 | struct snd_soc_jack *jack) |
1627 | { | |
12a72f91 | 1628 | struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); |
dfeabded JH |
1629 | int ret; |
1630 | ||
1631 | nau8824->jack = jack; | |
1632 | /* Initiate jack detection work queue */ | |
1633 | INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work); | |
1634 | ret = devm_request_threaded_irq(nau8824->dev, nau8824->irq, NULL, | |
1635 | nau8824_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, | |
1636 | "nau8824", nau8824); | |
1637 | if (ret) { | |
1638 | dev_err(nau8824->dev, "Cannot request irq %d (%d)\n", | |
1639 | nau8824->irq, ret); | |
1640 | } | |
1641 | ||
1642 | return ret; | |
1643 | } | |
1644 | EXPORT_SYMBOL_GPL(nau8824_enable_jack_detect); | |
1645 | ||
1646 | static void nau8824_reset_chip(struct regmap *regmap) | |
1647 | { | |
1648 | regmap_write(regmap, NAU8824_REG_RESET, 0x00); | |
1649 | regmap_write(regmap, NAU8824_REG_RESET, 0x00); | |
1650 | } | |
1651 | ||
1652 | static void nau8824_setup_buttons(struct nau8824 *nau8824) | |
1653 | { | |
1654 | struct regmap *regmap = nau8824->regmap; | |
1655 | ||
1656 | regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, | |
1657 | NAU8824_SAR_TRACKING_GAIN_MASK, | |
1658 | nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT); | |
1659 | regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, | |
1660 | NAU8824_SAR_COMPARE_TIME_MASK, | |
1661 | nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT); | |
1662 | regmap_update_bits(regmap, NAU8824_REG_SAR_ADC, | |
1663 | NAU8824_SAR_SAMPLING_TIME_MASK, | |
1664 | nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT); | |
1665 | ||
1666 | regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, | |
1667 | NAU8824_LEVELS_NR_MASK, | |
1668 | (nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT); | |
1669 | regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, | |
1670 | NAU8824_HYSTERESIS_MASK, | |
1671 | nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT); | |
1672 | regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT, | |
1673 | NAU8824_SHORTKEY_DEBOUNCE_MASK, | |
1674 | nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT); | |
1675 | ||
1676 | regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_1, | |
1677 | (nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]); | |
1678 | regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_2, | |
1679 | (nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]); | |
1680 | regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_3, | |
1681 | (nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]); | |
1682 | regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_4, | |
1683 | (nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]); | |
1684 | } | |
1685 | ||
1686 | static void nau8824_init_regs(struct nau8824 *nau8824) | |
1687 | { | |
1688 | struct regmap *regmap = nau8824->regmap; | |
1689 | ||
1690 | /* Enable Bias/VMID/VMID Tieoff */ | |
1691 | regmap_update_bits(regmap, NAU8824_REG_BIAS_ADJ, | |
1692 | NAU8824_VMID | NAU8824_VMID_SEL_MASK, NAU8824_VMID | | |
1693 | (nau8824->vref_impedance << NAU8824_VMID_SEL_SFT)); | |
1694 | regmap_update_bits(regmap, NAU8824_REG_BOOST, | |
1695 | NAU8824_GLOBAL_BIAS_EN, NAU8824_GLOBAL_BIAS_EN); | |
1696 | mdelay(2); | |
1697 | regmap_update_bits(regmap, NAU8824_REG_MIC_BIAS, | |
1698 | NAU8824_MICBIAS_VOLTAGE_MASK, nau8824->micbias_voltage); | |
1699 | /* Disable Boost Driver, Automatic Short circuit protection enable */ | |
1700 | regmap_update_bits(regmap, NAU8824_REG_BOOST, | |
1701 | NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS | | |
1702 | NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN, | |
1703 | NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS | | |
1704 | NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN); | |
1705 | /* Scaling for ADC and DAC clock */ | |
1706 | regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER, | |
1707 | NAU8824_CLK_ADC_SRC_MASK | NAU8824_CLK_DAC_SRC_MASK, | |
1708 | (0x1 << NAU8824_CLK_ADC_SRC_SFT) | | |
1709 | (0x1 << NAU8824_CLK_DAC_SRC_SFT)); | |
1710 | regmap_update_bits(regmap, NAU8824_REG_DAC_MUTE_CTRL, | |
1711 | NAU8824_DAC_ZC_EN, NAU8824_DAC_ZC_EN); | |
1712 | regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL, | |
1713 | NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN | | |
1714 | NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN | | |
1715 | NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN, | |
1716 | NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN | | |
1717 | NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN | | |
1718 | NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN); | |
1719 | regmap_update_bits(regmap, NAU8824_REG_CLK_GATING_ENA, | |
1720 | NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN | | |
1721 | NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN | | |
1722 | NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN | | |
1723 | NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN, | |
1724 | NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN | | |
1725 | NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN | | |
1726 | NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN | | |
1727 | NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN); | |
1728 | /* Class G timer 64ms */ | |
1729 | regmap_update_bits(regmap, NAU8824_REG_CLASSG, | |
1730 | NAU8824_CLASSG_TIMER_MASK, | |
1731 | 0x20 << NAU8824_CLASSG_TIMER_SFT); | |
1732 | regmap_update_bits(regmap, NAU8824_REG_TRIM_SETTINGS, | |
1733 | NAU8824_DRV_CURR_INC, NAU8824_DRV_CURR_INC); | |
1734 | /* Disable DACR/L power */ | |
1735 | regmap_update_bits(regmap, NAU8824_REG_CHARGE_PUMP_CONTROL, | |
1736 | NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN | | |
1737 | NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL, | |
1738 | NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN | | |
1739 | NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL); | |
1740 | /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input | |
1741 | * signal to avoid any glitches due to power up transients in both | |
1742 | * the analog and digital DAC circuit. | |
1743 | */ | |
1744 | regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO, | |
1745 | NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN); | |
1746 | /* Config L/R channel */ | |
1747 | regmap_update_bits(regmap, NAU8824_REG_DAC_CH0_DGAIN_CTRL, | |
1748 | NAU8824_DAC_CH0_SEL_MASK, NAU8824_DAC_CH0_SEL_I2S0); | |
1749 | regmap_update_bits(regmap, NAU8824_REG_DAC_CH1_DGAIN_CTRL, | |
1750 | NAU8824_DAC_CH1_SEL_MASK, NAU8824_DAC_CH1_SEL_I2S1); | |
1751 | regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO, | |
1752 | NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN, | |
1753 | NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN); | |
1754 | /* Default oversampling/decimations settings are unusable | |
1755 | * (audible hiss). Set it to something better. | |
1756 | */ | |
1757 | regmap_update_bits(regmap, NAU8824_REG_ADC_FILTER_CTRL, | |
1758 | NAU8824_ADC_SYNC_DOWN_MASK, NAU8824_ADC_SYNC_DOWN_64); | |
1759 | regmap_update_bits(regmap, NAU8824_REG_DAC_FILTER_CTRL_1, | |
1760 | NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_MASK, | |
1761 | NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_64); | |
dfeabded JH |
1762 | /* DAC clock delay 2ns, VREF */ |
1763 | regmap_update_bits(regmap, NAU8824_REG_RDAC, | |
1764 | NAU8824_RDAC_CLK_DELAY_MASK | NAU8824_RDAC_VREF_MASK, | |
1765 | (0x2 << NAU8824_RDAC_CLK_DELAY_SFT) | | |
1766 | (0x3 << NAU8824_RDAC_VREF_SFT)); | |
1767 | /* PGA input mode selection */ | |
1768 | regmap_update_bits(regmap, NAU8824_REG_FEPGA, | |
1769 | NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN, | |
1770 | NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN); | |
1771 | /* Digital microphone control */ | |
1772 | regmap_update_bits(regmap, NAU8824_REG_ANALOG_CONTROL_1, | |
1773 | NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST, | |
1774 | NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST); | |
1775 | regmap_update_bits(regmap, NAU8824_REG_JACK_DET_CTRL, | |
1776 | NAU8824_JACK_LOGIC, | |
1777 | /* jkdet_polarity - 1 is for active-low */ | |
1778 | nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC); | |
1779 | regmap_update_bits(regmap, | |
1780 | NAU8824_REG_JACK_DET_CTRL, NAU8824_JACK_EJECT_DT_MASK, | |
1781 | (nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT)); | |
1782 | if (nau8824->sar_threshold_num) | |
1783 | nau8824_setup_buttons(nau8824); | |
1784 | } | |
1785 | ||
1786 | static int nau8824_setup_irq(struct nau8824 *nau8824) | |
1787 | { | |
1788 | /* Disable interruption before codec initiation done */ | |
1789 | regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL, | |
1790 | NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE); | |
1791 | regmap_update_bits(nau8824->regmap, | |
1792 | NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff); | |
1793 | regmap_update_bits(nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1, | |
1794 | NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0); | |
1795 | ||
1796 | return 0; | |
1797 | } | |
1798 | ||
1799 | static void nau8824_print_device_properties(struct nau8824 *nau8824) | |
1800 | { | |
1801 | struct device *dev = nau8824->dev; | |
1802 | int i; | |
1803 | ||
1804 | dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity); | |
1805 | dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage); | |
1806 | dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance); | |
1807 | ||
1808 | dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num); | |
1809 | for (i = 0; i < nau8824->sar_threshold_num; i++) | |
1810 | dev_dbg(dev, "sar-threshold[%d]=%x\n", i, | |
1811 | nau8824->sar_threshold[i]); | |
1812 | ||
1813 | dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis); | |
1814 | dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage); | |
1815 | dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time); | |
1816 | dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time); | |
1817 | dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce); | |
1818 | dev_dbg(dev, "jack-eject-debounce: %d\n", | |
1819 | nau8824->jack_eject_debounce); | |
1820 | } | |
1821 | ||
1822 | static int nau8824_read_device_properties(struct device *dev, | |
1823 | struct nau8824 *nau8824) { | |
1824 | int ret; | |
1825 | ||
1826 | ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", | |
1827 | &nau8824->jkdet_polarity); | |
1828 | if (ret) | |
1829 | nau8824->jkdet_polarity = 1; | |
1830 | ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", | |
1831 | &nau8824->micbias_voltage); | |
1832 | if (ret) | |
1833 | nau8824->micbias_voltage = 6; | |
1834 | ret = device_property_read_u32(dev, "nuvoton,vref-impedance", | |
1835 | &nau8824->vref_impedance); | |
1836 | if (ret) | |
1837 | nau8824->vref_impedance = 2; | |
1838 | ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num", | |
1839 | &nau8824->sar_threshold_num); | |
1840 | if (ret) | |
1841 | nau8824->sar_threshold_num = 4; | |
1842 | ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold", | |
1843 | nau8824->sar_threshold, nau8824->sar_threshold_num); | |
1844 | if (ret) { | |
1845 | nau8824->sar_threshold[0] = 0x0a; | |
1846 | nau8824->sar_threshold[1] = 0x14; | |
1847 | nau8824->sar_threshold[2] = 0x26; | |
1848 | nau8824->sar_threshold[3] = 0x73; | |
1849 | } | |
1850 | ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis", | |
1851 | &nau8824->sar_hysteresis); | |
1852 | if (ret) | |
1853 | nau8824->sar_hysteresis = 0; | |
1854 | ret = device_property_read_u32(dev, "nuvoton,sar-voltage", | |
1855 | &nau8824->sar_voltage); | |
1856 | if (ret) | |
1857 | nau8824->sar_voltage = 6; | |
1858 | ret = device_property_read_u32(dev, "nuvoton,sar-compare-time", | |
1859 | &nau8824->sar_compare_time); | |
1860 | if (ret) | |
1861 | nau8824->sar_compare_time = 1; | |
1862 | ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time", | |
1863 | &nau8824->sar_sampling_time); | |
1864 | if (ret) | |
1865 | nau8824->sar_sampling_time = 1; | |
1866 | ret = device_property_read_u32(dev, "nuvoton,short-key-debounce", | |
1867 | &nau8824->key_debounce); | |
1868 | if (ret) | |
1869 | nau8824->key_debounce = 0; | |
1870 | ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", | |
1871 | &nau8824->jack_eject_debounce); | |
1872 | if (ret) | |
1873 | nau8824->jack_eject_debounce = 1; | |
1874 | ||
1875 | return 0; | |
1876 | } | |
1877 | ||
1878 | static int nau8824_i2c_probe(struct i2c_client *i2c, | |
1879 | const struct i2c_device_id *id) | |
1880 | { | |
1881 | struct device *dev = &i2c->dev; | |
1882 | struct nau8824 *nau8824 = dev_get_platdata(dev); | |
1883 | int ret, value; | |
1884 | ||
1885 | if (!nau8824) { | |
1886 | nau8824 = devm_kzalloc(dev, sizeof(*nau8824), GFP_KERNEL); | |
1887 | if (!nau8824) | |
1888 | return -ENOMEM; | |
1889 | ret = nau8824_read_device_properties(dev, nau8824); | |
1890 | if (ret) | |
1891 | return ret; | |
1892 | } | |
1893 | i2c_set_clientdata(i2c, nau8824); | |
1894 | ||
1895 | nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config); | |
1896 | if (IS_ERR(nau8824->regmap)) | |
1897 | return PTR_ERR(nau8824->regmap); | |
1898 | nau8824->dev = dev; | |
1899 | nau8824->irq = i2c->irq; | |
1900 | sema_init(&nau8824->jd_sem, 1); | |
1901 | ||
1902 | nau8824_print_device_properties(nau8824); | |
1903 | ||
1904 | ret = regmap_read(nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, &value); | |
1905 | if (ret < 0) { | |
1906 | dev_err(dev, "Failed to read device id from the NAU8824: %d\n", | |
1907 | ret); | |
1908 | return ret; | |
1909 | } | |
1910 | nau8824_reset_chip(nau8824->regmap); | |
1911 | nau8824_init_regs(nau8824); | |
1912 | ||
1913 | if (i2c->irq) | |
1914 | nau8824_setup_irq(nau8824); | |
1915 | ||
12a72f91 KM |
1916 | return devm_snd_soc_register_component(dev, |
1917 | &nau8824_component_driver, &nau8824_dai, 1); | |
dfeabded JH |
1918 | } |
1919 | ||
1920 | static const struct i2c_device_id nau8824_i2c_ids[] = { | |
1921 | { "nau8824", 0 }, | |
1922 | { } | |
1923 | }; | |
1924 | MODULE_DEVICE_TABLE(i2c, nau8824_i2c_ids); | |
1925 | ||
1926 | #ifdef CONFIG_OF | |
1927 | static const struct of_device_id nau8824_of_ids[] = { | |
1928 | { .compatible = "nuvoton,nau8824", }, | |
1929 | {} | |
1930 | }; | |
1931 | MODULE_DEVICE_TABLE(of, nau8824_of_ids); | |
1932 | #endif | |
1933 | ||
1934 | #ifdef CONFIG_ACPI | |
1935 | static const struct acpi_device_id nau8824_acpi_match[] = { | |
1936 | { "10508824", 0 }, | |
1937 | {}, | |
1938 | }; | |
1939 | MODULE_DEVICE_TABLE(acpi, nau8824_acpi_match); | |
1940 | #endif | |
1941 | ||
1942 | static struct i2c_driver nau8824_i2c_driver = { | |
1943 | .driver = { | |
1944 | .name = "nau8824", | |
1945 | .of_match_table = of_match_ptr(nau8824_of_ids), | |
1946 | .acpi_match_table = ACPI_PTR(nau8824_acpi_match), | |
1947 | }, | |
1948 | .probe = nau8824_i2c_probe, | |
dfeabded JH |
1949 | .id_table = nau8824_i2c_ids, |
1950 | }; | |
1951 | module_i2c_driver(nau8824_i2c_driver); | |
1952 | ||
1953 | ||
1954 | MODULE_DESCRIPTION("ASoC NAU88L24 driver"); | |
1955 | MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>"); | |
1956 | MODULE_LICENSE("GPL v2"); |