]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - sound/soc/codecs/nau8825.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: core: Allow topology to override machine driver FE DAI link config.
[mirror_ubuntu-jammy-kernel.git] / sound / soc / codecs / nau8825.c
CommitLineData
34ca27f3
AP		 1/*
2 * Nuvoton NAU8825 audio codec driver
3 *
4 * Copyright 2015 Google Chromium project.
5 * Author: Anatol Pomozov <anatol@chromium.org>
6 * Copyright 2015 Nuvoton Technology Corp.
7 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
8 *
9 * Licensed under the GPL-2.
10 */
11
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/i2c.h>
16#include <linux/regmap.h>
17#include <linux/slab.h>
18#include <linux/clk.h>
b3681308 19#include <linux/acpi.h>
c86ba612 20#include <linux/math64.h>
b50455fa 21#include <linux/semaphore.h>
34ca27f3
AP		 22
23#include <sound/initval.h>
24#include <sound/tlv.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/jack.h>
30
31
32#include "nau8825.h"
33
2ec30f60
JH		 34
35#define NUVOTON_CODEC_DAI "nau8825-hifi"
36
c86ba612 37#define NAU_FREF_MAX 13500000
407c71b6 38#define NAU_FVCO_MAX 124000000
c86ba612
BZ		 39#define NAU_FVCO_MIN 90000000
40
b50455fa
JH		 41/* cross talk suppression detection */
42#define LOG10_MAGIC 646456993
43#define GAIN_AUGMENT 22500
44#define SIDETONE_BASE 207000
45
d6d19745
JH		 46/* the maximum frequency of CLK_ADC and CLK_DAC */
47#define CLK_DA_AD_MAX 6144000
b50455fa 48
2ec30f60
JH		 49static int nau8825_configure_sysclk(struct nau8825 *nau8825,
50 int clk_id, unsigned int freq);
51
c86ba612
BZ		 52struct nau8825_fll {
53 int mclk_src;
54 int ratio;
55 int fll_frac;
56 int fll_int;
57 int clk_ref_div;
58};
59
60struct nau8825_fll_attr {
61 unsigned int param;
62 unsigned int val;
63};
64
65/* scaling for mclk from sysclk_src output */
66static const struct nau8825_fll_attr mclk_src_scaling[] = {
67 { 1, 0x0 },
68 { 2, 0x2 },
69 { 4, 0x3 },
70 { 8, 0x4 },
71 { 16, 0x5 },
72 { 32, 0x6 },
73 { 3, 0x7 },
74 { 6, 0xa },
75 { 12, 0xb },
76 { 24, 0xc },
77 { 48, 0xd },
78 { 96, 0xe },
79 { 5, 0xf },
80};
81
82/* ratio for input clk freq */
83static const struct nau8825_fll_attr fll_ratio[] = {
84 { 512000, 0x01 },
85 { 256000, 0x02 },
86 { 128000, 0x04 },
87 { 64000, 0x08 },
88 { 32000, 0x10 },
89 { 8000, 0x20 },
90 { 4000, 0x40 },
91};
92
93static const struct nau8825_fll_attr fll_pre_scalar[] = {
94 { 1, 0x0 },
95 { 2, 0x1 },
96 { 4, 0x2 },
97 { 8, 0x3 },
98};
99
d6d19745
JH		 100/* over sampling rate */
101struct nau8825_osr_attr {
102 unsigned int osr;
103 unsigned int clk_src;
104};
105
106static const struct nau8825_osr_attr osr_dac_sel[] = {
107 { 64, 2 }, /* OSR 64, SRC 1/4 */
108 { 256, 0 }, /* OSR 256, SRC 1 */
109 { 128, 1 }, /* OSR 128, SRC 1/2 */
110 { 0, 0 },
111 { 32, 3 }, /* OSR 32, SRC 1/8 */
112};
113
114static const struct nau8825_osr_attr osr_adc_sel[] = {
115 { 32, 3 }, /* OSR 32, SRC 1/8 */
116 { 64, 2 }, /* OSR 64, SRC 1/4 */
117 { 128, 1 }, /* OSR 128, SRC 1/2 */
118 { 256, 0 }, /* OSR 256, SRC 1 */
119};
120
34ca27f3
AP		 121static const struct reg_default nau8825_reg_defaults[] = {
122 { NAU8825_REG_ENA_CTRL, 0x00ff },
45d5eb3a 123 { NAU8825_REG_IIC_ADDR_SET, 0x0 },
34ca27f3
AP		 124 { NAU8825_REG_CLK_DIVIDER, 0x0050 },
125 { NAU8825_REG_FLL1, 0x0 },
126 { NAU8825_REG_FLL2, 0x3126 },
127 { NAU8825_REG_FLL3, 0x0008 },
128 { NAU8825_REG_FLL4, 0x0010 },
129 { NAU8825_REG_FLL5, 0x0 },
130 { NAU8825_REG_FLL6, 0x6000 },
131 { NAU8825_REG_FLL_VCO_RSV, 0xf13c },
132 { NAU8825_REG_HSD_CTRL, 0x000c },
133 { NAU8825_REG_JACK_DET_CTRL, 0x0 },
134 { NAU8825_REG_INTERRUPT_MASK, 0x0 },
135 { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff },
136 { NAU8825_REG_SAR_CTRL, 0x0015 },
137 { NAU8825_REG_KEYDET_CTRL, 0x0110 },
138 { NAU8825_REG_VDET_THRESHOLD_1, 0x0 },
139 { NAU8825_REG_VDET_THRESHOLD_2, 0x0 },
140 { NAU8825_REG_VDET_THRESHOLD_3, 0x0 },
141 { NAU8825_REG_VDET_THRESHOLD_4, 0x0 },
142 { NAU8825_REG_GPIO34_CTRL, 0x0 },
143 { NAU8825_REG_GPIO12_CTRL, 0x0 },
144 { NAU8825_REG_TDM_CTRL, 0x0 },
145 { NAU8825_REG_I2S_PCM_CTRL1, 0x000b },
146 { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 },
147 { NAU8825_REG_LEFT_TIME_SLOT, 0x0 },
148 { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 },
149 { NAU8825_REG_BIQ_CTRL, 0x0 },
150 { NAU8825_REG_BIQ_COF1, 0x0 },
151 { NAU8825_REG_BIQ_COF2, 0x0 },
152 { NAU8825_REG_BIQ_COF3, 0x0 },
153 { NAU8825_REG_BIQ_COF4, 0x0 },
154 { NAU8825_REG_BIQ_COF5, 0x0 },
155 { NAU8825_REG_BIQ_COF6, 0x0 },
156 { NAU8825_REG_BIQ_COF7, 0x0 },
157 { NAU8825_REG_BIQ_COF8, 0x0 },
158 { NAU8825_REG_BIQ_COF9, 0x0 },
159 { NAU8825_REG_BIQ_COF10, 0x0 },
160 { NAU8825_REG_ADC_RATE, 0x0010 },
161 { NAU8825_REG_DAC_CTRL1, 0x0001 },
162 { NAU8825_REG_DAC_CTRL2, 0x0 },
163 { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 },
164 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
165 { NAU8825_REG_MUTE_CTRL, 0x0 },
166 { NAU8825_REG_HSVOL_CTRL, 0x0 },
167 { NAU8825_REG_DACL_CTRL, 0x02cf },
168 { NAU8825_REG_DACR_CTRL, 0x00cf },
169 { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 },
170 { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 },
171 { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff },
172 { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 },
173 { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 },
174 { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 },
175 { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 },
176 { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 },
177 { NAU8825_REG_IMM_MODE_CTRL, 0x0 },
178 { NAU8825_REG_CLASSG_CTRL, 0x0 },
179 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
180 { NAU8825_REG_MISC_CTRL, 0x0 },
181 { NAU8825_REG_BIAS_ADJ, 0x0 },
182 { NAU8825_REG_TRIM_SETTINGS, 0x0 },
183 { NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
184 { NAU8825_REG_ANALOG_CONTROL_2, 0x0 },
185 { NAU8825_REG_ANALOG_ADC_1, 0x0011 },
186 { NAU8825_REG_ANALOG_ADC_2, 0x0020 },
187 { NAU8825_REG_RDAC, 0x0008 },
188 { NAU8825_REG_MIC_BIAS, 0x0006 },
189 { NAU8825_REG_BOOST, 0x0 },
190 { NAU8825_REG_FEPGA, 0x0 },
191 { NAU8825_REG_POWER_UP_CONTROL, 0x0 },
192 { NAU8825_REG_CHARGE_PUMP, 0x0 },
193};
194
b50455fa
JH		 195/* register backup table when cross talk detection */
196static struct reg_default nau8825_xtalk_baktab[] = {
fa25b4f5 197 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
b50455fa 198 { NAU8825_REG_HSVOL_CTRL, 0 },
fa25b4f5
JH		 199 { NAU8825_REG_DACL_CTRL, 0x00cf },
200 { NAU8825_REG_DACR_CTRL, 0x02cf },
b50455fa
JH		 201};
202
203static const unsigned short logtable[256] = {
204 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7,
205 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508,
206 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6,
207 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37,
208 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f,
209 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41,
210 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1,
211 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142,
212 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68,
213 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355,
214 0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c,
215 0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490,
216 0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3,
217 0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507,
218 0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe,
219 0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca,
220 0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c,
221 0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7,
222 0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c,
223 0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c,
224 0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a,
225 0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065,
226 0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730,
227 0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc,
228 0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469,
229 0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9,
230 0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c,
231 0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765,
232 0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83,
233 0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387,
234 0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973,
235 0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47
236};
237
b50455fa
JH		 238/**
239 * nau8825_sema_acquire - acquire the semaphore of nau88l25
240 * @nau8825: component to register the codec private data with
241 * @timeout: how long in jiffies to wait before failure or zero to wait
242 * until release
243 *
244 * Attempts to acquire the semaphore with number of jiffies. If no more
245 * tasks are allowed to acquire the semaphore, calling this function will
246 * put the task to sleep. If the semaphore is not released within the
247 * specified number of jiffies, this function returns.
06746c67 248 * If the semaphore is not released within the specified number of jiffies,
70424d8e
JH		 249 * this function returns -ETIME. If the sleep is interrupted by a signal,
250 * this function will return -EINTR. It returns 0 if the semaphore was
251 * acquired successfully.
252 *
253 * Acquires the semaphore without jiffies. Try to acquire the semaphore
254 * atomically. Returns 0 if the semaphore has been acquired successfully
255 * or 1 if it it cannot be acquired.
b50455fa 256 */
06746c67 257static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout)
b50455fa
JH		 258{
259 int ret;
260
06746c67 261 if (timeout) {
b50455fa 262 ret = down_timeout(&nau8825->xtalk_sem, timeout);
06746c67 263 if (ret < 0)
3dfcd346 264 dev_warn(nau8825->dev, "Acquire semaphore timeout\n");
06746c67 265 } else {
70424d8e
JH		 266 ret = down_trylock(&nau8825->xtalk_sem);
267 if (ret)
3dfcd346 268 dev_warn(nau8825->dev, "Acquire semaphore fail\n");
06746c67 269 }
b50455fa 270
06746c67 271 return ret;
b50455fa
JH		 272}
273
274/**
275 * nau8825_sema_release - release the semaphore of nau88l25
276 * @nau8825: component to register the codec private data with
277 *
278 * Release the semaphore which may be called from any context and
279 * even by tasks which have never called down().
280 */
281static inline void nau8825_sema_release(struct nau8825 *nau8825)
282{
283 up(&nau8825->xtalk_sem);
284}
285
286/**
287 * nau8825_sema_reset - reset the semaphore for nau88l25
288 * @nau8825: component to register the codec private data with
289 *
290 * Reset the counter of the semaphore. Call this function to restart
291 * a new round task management.
292 */
293static inline void nau8825_sema_reset(struct nau8825 *nau8825)
294{
295 nau8825->xtalk_sem.count = 1;
296}
297
298/**
299 * Ramp up the headphone volume change gradually to target level.
300 *
301 * @nau8825: component to register the codec private data with
302 * @vol_from: the volume to start up
303 * @vol_to: the target volume
304 * @step: the volume span to move on
305 *
306 * The headphone volume is from 0dB to minimum -54dB and -1dB per step.
307 * If the volume changes sharp, there is a pop noise heard in headphone. We
308 * provide the function to ramp up the volume up or down by delaying 10ms
309 * per step.
310 */
311static void nau8825_hpvol_ramp(struct nau8825 *nau8825,
312 unsigned int vol_from, unsigned int vol_to, unsigned int step)
313{
314 unsigned int value, volume, ramp_up, from, to;
315
316 if (vol_from == vol_to || step == 0) {
317 return;
318 } else if (vol_from < vol_to) {
319 ramp_up = true;
320 from = vol_from;
321 to = vol_to;
322 } else {
323 ramp_up = false;
324 from = vol_to;
325 to = vol_from;
326 }
327 /* only handle volume from 0dB to minimum -54dB */
328 if (to > NAU8825_HP_VOL_MIN)
329 to = NAU8825_HP_VOL_MIN;
330
331 for (volume = from; volume < to; volume += step) {
332 if (ramp_up)
333 value = volume;
334 else
335 value = to - volume + from;
336 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
337 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
338 (value << NAU8825_HPL_VOL_SFT) | value);
339 usleep_range(10000, 10500);
340 }
341 if (ramp_up)
342 value = to;
343 else
344 value = from;
345 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
346 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
347 (value << NAU8825_HPL_VOL_SFT) | value);
348}
349
350/**
351 * Computes log10 of a value; the result is round off to 3 decimal. This func-
352 * tion takes reference to dvb-math. The source code locates as the following.
353 * Linux/drivers/media/dvb-core/dvb_math.c
354 *
355 * return log10(value) * 1000
356 */
357static u32 nau8825_intlog10_dec3(u32 value)
358{
359 u32 msb, logentry, significand, interpolation, log10val;
360 u64 log2val;
361
362 /* first detect the msb (count begins at 0) */
363 msb = fls(value) - 1;
364 /**
365 * now we use a logtable after the following method:
366 *
367 * log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24
368 * where x = msb and therefore 1 <= y < 2
369 * first y is determined by shifting the value left
370 * so that msb is bit 31
371 * 0x00231f56 -> 0x8C7D5800
372 * the result is y * 2^31 -> "significand"
373 * then the highest 9 bits are used for a table lookup
374 * the highest bit is discarded because it's always set
375 * the highest nine bits in our example are 100011000
376 * so we would use the entry 0x18
377 */
378 significand = value << (31 - msb);
379 logentry = (significand >> 23) & 0xff;
380 /**
381 * last step we do is interpolation because of the
382 * limitations of the log table the error is that part of
383 * the significand which isn't used for lookup then we
384 * compute the ratio between the error and the next table entry
385 * and interpolate it between the log table entry used and the
386 * next one the biggest error possible is 0x7fffff
387 * (in our example it's 0x7D5800)
388 * needed value for next table entry is 0x800000
389 * so the interpolation is
390 * (error / 0x800000) * (logtable_next - logtable_current)
391 * in the implementation the division is moved to the end for
392 * better accuracy there is also an overflow correction if
393 * logtable_next is 256
394 */
395 interpolation = ((significand & 0x7fffff) *
396 ((logtable[(logentry + 1) & 0xff] -
397 logtable[logentry]) & 0xffff)) >> 15;
398
399 log2val = ((msb << 24) + (logtable[logentry] << 8) + interpolation);
400 /**
401 * log10(x) = log2(x) * log10(2)
402 */
403 log10val = (log2val * LOG10_MAGIC) >> 31;
404 /**
405 * the result is round off to 3 decimal
406 */
407 return log10val / ((1 << 24) / 1000);
408}
409
410/**
411 * computes cross talk suppression sidetone gain.
412 *
413 * @sig_org: orignal signal level
414 * @sig_cros: cross talk signal level
415 *
416 * The orignal and cross talk signal vlues need to be characterized.
417 * Once these values have been characterized, this sidetone value
418 * can be converted to decibel with the equation below.
419 * sidetone = 20 * log (original signal level / crosstalk signal level)
420 *
421 * return cross talk sidetone gain
422 */
423static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros)
424{
425 u32 gain, sidetone;
426
427 if (unlikely(sig_org == 0) || unlikely(sig_cros == 0)) {
428 WARN_ON(1);
429 return 0;
430 }
431
432 sig_org = nau8825_intlog10_dec3(sig_org);
433 sig_cros = nau8825_intlog10_dec3(sig_cros);
434 if (sig_org >= sig_cros)
435 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT;
436 else
437 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT;
438 sidetone = SIDETONE_BASE - gain * 2;
439 sidetone /= 1000;
440
441 return sidetone;
442}
443
444static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg)
445{
446 int index;
447
448 for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++)
449 if (nau8825_xtalk_baktab[index].reg == reg)
450 return index;
451 return -EINVAL;
452}
453
454static void nau8825_xtalk_backup(struct nau8825 *nau8825)
455{
456 int i;
457
fa25b4f5
JH		 458 if (nau8825->xtalk_baktab_initialized)
459 return;
460
b50455fa
JH		 461 /* Backup some register values to backup table */
462 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++)
463 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
464 &nau8825_xtalk_baktab[i].def);
fa25b4f5
JH		 465
466 nau8825->xtalk_baktab_initialized = true;
b50455fa
JH		 467}
468
fa25b4f5 469static void nau8825_xtalk_restore(struct nau8825 *nau8825, bool cause_cancel)
b50455fa
JH		 470{
471 int i, volume;
472
fa25b4f5
JH		 473 if (!nau8825->xtalk_baktab_initialized)
474 return;
475
b50455fa 476 /* Restore register values from backup table; When the driver restores
fa25b4f5
JH		 477 * the headphone volume in XTALK_DONE state, it needs recover to
478 * original level gradually with 3dB per step for less pop noise.
479 * Otherwise, the restore should do ASAP.
b50455fa
JH		 480 */
481 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) {
fa25b4f5
JH		 482 if (!cause_cancel && nau8825_xtalk_baktab[i].reg ==
483 NAU8825_REG_HSVOL_CTRL) {
b50455fa
JH		 484 /* Ramping up the volume change to reduce pop noise */
485 volume = nau8825_xtalk_baktab[i].def &
486 NAU8825_HPR_VOL_MASK;
487 nau8825_hpvol_ramp(nau8825, 0, volume, 3);
488 continue;
489 }
490 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
491 nau8825_xtalk_baktab[i].def);
492 }
fa25b4f5
JH		 493
494 nau8825->xtalk_baktab_initialized = false;
b50455fa
JH		 495}
496
497static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825)
498{
499 /* Enable power of DAC path */
500 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
501 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
502 NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK |
503 NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR |
504 NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC |
505 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK);
506 /* Prevent startup click by letting charge pump to ramp up and
507 * change bump enable
508 */
509 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
510 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN,
511 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN);
512 /* Enable clock sync of DAC and DAC clock */
513 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
514 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN |
515 NAU8825_RDAC_FS_BCLK_ENB,
516 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN);
517 /* Power up output driver with 2 stage */
518 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
519 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
520 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L,
521 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
522 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L);
523 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
524 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L,
525 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L);
526 /* HP outputs not shouted to ground */
527 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
528 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0);
529 /* Enable HP boost driver */
530 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
531 NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS);
532 /* Enable class G compare path to supply 1.8V or 0.9V. */
533 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL,
534 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN,
535 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN);
536}
537
538static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825)
539{
540 /* Power up left ADC and raise 5dB than Vmid for Vref */
541 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
542 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK,
543 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB);
544}
545
546static void nau8825_xtalk_clock(struct nau8825 *nau8825)
547{
548 /* Recover FLL default value */
549 regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0);
550 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126);
551 regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008);
552 regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010);
553 regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0);
554 regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000);
555 /* Enable internal VCO clock for detection signal generated */
556 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
557 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
558 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
559 NAU8825_DCO_EN);
560 /* Given specific clock frequency of internal clock to
561 * generate signal.
562 */
563 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
564 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
565 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
566 NAU8825_FLL_RATIO_MASK, 0x10);
567}
568
569static void nau8825_xtalk_prepare(struct nau8825 *nau8825)
570{
571 int volume, index;
572
573 /* Backup those registers changed by cross talk detection */
574 nau8825_xtalk_backup(nau8825);
575 /* Config IIS as master to output signal by codec */
576 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
a33b56a6 577 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
b50455fa 578 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER |
a33b56a6 579 (0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1);
b50455fa
JH		 580 /* Ramp up headphone volume to 0dB to get better performance and
581 * avoid pop noise in headphone.
582 */
583 index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL);
584 if (index != -EINVAL) {
585 volume = nau8825_xtalk_baktab[index].def &
586 NAU8825_HPR_VOL_MASK;
587 nau8825_hpvol_ramp(nau8825, volume, 0, 3);
588 }
589 nau8825_xtalk_clock(nau8825);
590 nau8825_xtalk_prepare_dac(nau8825);
591 nau8825_xtalk_prepare_adc(nau8825);
592 /* Config channel path and digital gain */
593 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
594 NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK,
595 NAU8825_DACL_CH_SEL_L | 0xab);
596 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
597 NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK,
598 NAU8825_DACR_CH_SEL_R | 0xab);
599 /* Config cross talk parameters and generate the 23Hz sine wave with
600 * 1/16 full scale of signal level for impedance measurement.
601 */
602 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
603 NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK |
604 NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK,
605 (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th |
606 NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN);
607 /* RMS intrruption enable */
608 regmap_update_bits(nau8825->regmap,
609 NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0);
610 /* Power up left and right DAC */
611 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
612 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
613}
614
615static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825)
616{
617 /* Disable HP boost driver */
618 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
619 NAU8825_HP_BOOST_DIS, 0);
620 /* HP outputs shouted to ground */
621 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
622 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
623 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
624 /* Power down left and right DAC */
625 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
626 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
627 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
628 /* Enable the TESTDAC and disable L/R HP impedance */
629 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
630 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP |
631 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
632 /* Power down output driver with 2 stage */
633 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
634 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0);
635 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
636 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
637 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0);
638 /* Disable clock sync of DAC and DAC clock */
639 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
640 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0);
641 /* Disable charge pump ramp up function and change bump */
642 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
643 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0);
644 /* Disable power of DAC path */
645 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
646 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
647 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0);
648 if (!nau8825->irq)
649 regmap_update_bits(nau8825->regmap,
650 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
651}
652
653static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825)
654{
655 /* Power down left ADC and restore voltage to Vmid */
656 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
657 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0);
658}
659
fa25b4f5 660static void nau8825_xtalk_clean(struct nau8825 *nau8825, bool cause_cancel)
b50455fa
JH		 661{
662 /* Enable internal VCO needed for interruptions */
663 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
664 nau8825_xtalk_clean_dac(nau8825);
665 nau8825_xtalk_clean_adc(nau8825);
666 /* Clear cross talk parameters and disable */
667 regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0);
668 /* RMS intrruption disable */
669 regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK,
670 NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN);
671 /* Recover default value for IIS */
672 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
a33b56a6 673 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
b50455fa
JH		 674 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
675 /* Restore value of specific register for cross talk */
fa25b4f5 676 nau8825_xtalk_restore(nau8825, cause_cancel);
b50455fa
JH		 677}
678
679static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol)
680{
681 /* Apply ADC volume for better cross talk performance */
682 regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL,
683 NAU8825_ADC_DIG_VOL_MASK, vol);
684 /* Disables JKTIP(HPL) DAC channel for right to left measurement.
685 * Do it before sending signal in order to erase pop noise.
686 */
687 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
688 NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN,
689 NAU8825_BIAS_TESTDACL_EN);
690 switch (nau8825->xtalk_state) {
691 case NAU8825_XTALK_HPR_R2L:
692 /* Enable right headphone impedance */
693 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
694 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
695 NAU8825_BIAS_HPR_IMP);
696 break;
697 case NAU8825_XTALK_HPL_R2L:
698 /* Enable left headphone impedance */
699 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
700 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
701 NAU8825_BIAS_HPL_IMP);
702 break;
703 default:
704 break;
705 }
706 msleep(100);
707 /* Impedance measurement mode enable */
708 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
709 NAU8825_IMM_EN, NAU8825_IMM_EN);
710}
711
712static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825)
713{
714 /* Impedance measurement mode disable */
715 regmap_update_bits(nau8825->regmap,
716 NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0);
717}
718
719/* The cross talk measurement function can reduce cross talk across the
720 * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal
721 * level to determine what cross talk reduction gain is. This system works by
722 * sending a 23Hz -24dBV sine wave into the headset output DAC and through
723 * the PGA. The output of the PGA is then connected to an internal current
724 * sense which measures the attenuated 23Hz signal and passing the output to
725 * an ADC which converts the measurement to a binary code. With two separated
726 * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data
727 * can be separated read in IMM_RMS_L for HSR and HSL after each measurement.
728 * Thus, the measurement function has four states to complete whole sequence.
729 * 1. Prepare state : Prepare the resource for detection and transfer to HPR
730 * IMM stat to make JKR1(HPR) impedance measure.
731 * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer
732 * to HPL IMM state to make JKTIP(HPL) impedance measure.
733 * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and
734 * transfer to IMM state to determine suppression sidetone gain.
735 * 4. IMM state : Computes cross talk suppression sidetone gain with orignal
736 * and cross talk signal level. Apply this gain and then restore codec
737 * configuration. Then transfer to Done state for ending.
738 */
739static void nau8825_xtalk_measure(struct nau8825 *nau8825)
740{
741 u32 sidetone;
742
743 switch (nau8825->xtalk_state) {
744 case NAU8825_XTALK_PREPARE:
745 /* In prepare state, set up clock, intrruption, DAC path, ADC
746 * path and cross talk detection parameters for preparation.
747 */
748 nau8825_xtalk_prepare(nau8825);
749 msleep(280);
750 /* Trigger right headphone impedance detection */
751 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L;
752 nau8825_xtalk_imm_start(nau8825, 0x00d2);
753 break;
754 case NAU8825_XTALK_HPR_R2L:
755 /* In right headphone IMM state, read out right headphone
756 * impedance measure result, and then start up left side.
757 */
758 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
759 &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
760 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n",
761 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
762 /* Disable then re-enable IMM mode to update */
763 nau8825_xtalk_imm_stop(nau8825);
764 /* Trigger left headphone impedance detection */
765 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L;
766 nau8825_xtalk_imm_start(nau8825, 0x00ff);
767 break;
768 case NAU8825_XTALK_HPL_R2L:
769 /* In left headphone IMM state, read out left headphone
770 * impedance measure result, and delay some time to wait
771 * detection sine wave output finish. Then, we can calculate
772 * the cross talk suppresstion side tone according to the L/R
773 * headphone imedance.
774 */
775 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
776 &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
777 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n",
778 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
779 nau8825_xtalk_imm_stop(nau8825);
780 msleep(150);
781 nau8825->xtalk_state = NAU8825_XTALK_IMM;
782 break;
783 case NAU8825_XTALK_IMM:
784 /* In impedance measure state, the orignal and cross talk
785 * signal level vlues are ready. The side tone gain is deter-
786 * mined with these signal level. After all, restore codec
787 * configuration.
788 */
789 sidetone = nau8825_xtalk_sidetone(
790 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L],
791 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
792 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone);
793 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL,
794 (sidetone << 8) | sidetone);
fa25b4f5 795 nau8825_xtalk_clean(nau8825, false);
b50455fa
JH		 796 nau8825->xtalk_state = NAU8825_XTALK_DONE;
797 break;
798 default:
799 break;
800 }
801}
802
803static void nau8825_xtalk_work(struct work_struct *work)
804{
805 struct nau8825 *nau8825 = container_of(
806 work, struct nau8825, xtalk_work);
807
808 nau8825_xtalk_measure(nau8825);
809 /* To determine the cross talk side tone gain when reach
810 * the impedance measure state.
811 */
812 if (nau8825->xtalk_state == NAU8825_XTALK_IMM)
813 nau8825_xtalk_measure(nau8825);
814
815 /* Delay jack report until cross talk detection process
816 * completed. It can avoid application to do playback
817 * preparation before cross talk detection is still working.
818 * Meanwhile, the protection of the cross talk detection
819 * is released.
820 */
821 if (nau8825->xtalk_state == NAU8825_XTALK_DONE) {
822 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event,
823 nau8825->xtalk_event_mask);
824 nau8825_sema_release(nau8825);
825 nau8825->xtalk_protect = false;
826 }
827}
828
829static void nau8825_xtalk_cancel(struct nau8825 *nau8825)
830{
226d7449
JH		 831 /* If the crosstalk is eanbled and the process is on going,
832 * the driver forces to cancel the crosstalk task and
b50455fa
JH		 833 * restores the configuration to original status.
834 */
226d7449
JH		 835 if (nau8825->xtalk_enable && nau8825->xtalk_state !=
836 NAU8825_XTALK_DONE) {
b50455fa 837 cancel_work_sync(&nau8825->xtalk_work);
fa25b4f5 838 nau8825_xtalk_clean(nau8825, true);
b50455fa
JH		 839 }
840 /* Reset parameters for cross talk suppression function */
841 nau8825_sema_reset(nau8825);
842 nau8825->xtalk_state = NAU8825_XTALK_DONE;
843 nau8825->xtalk_protect = false;
844}
845
34ca27f3
AP		 846static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
847{
848 switch (reg) {
45d5eb3a 849 case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
34ca27f3
AP		 850 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
851 case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL:
852 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
853 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
854 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
855 case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
856 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
857 case NAU8825_REG_MISC_CTRL:
858 case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS:
859 case NAU8825_REG_BIAS_ADJ:
860 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
861 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
862 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
863 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS:
864 return true;
865 default:
866 return false;
867 }
868
869}
870
871static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
872{
873 switch (reg) {
45d5eb3a 874 case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV:
34ca27f3
AP		 875 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
876 case NAU8825_REG_INTERRUPT_MASK:
877 case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL:
878 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
879 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
880 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
881 case NAU8825_REG_IMM_MODE_CTRL:
882 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
883 case NAU8825_REG_MISC_CTRL:
884 case NAU8825_REG_BIAS_ADJ:
885 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
886 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
887 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
888 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP:
889 return true;
890 default:
891 return false;
892 }
893}
894
895static bool nau8825_volatile_reg(struct device *dev, unsigned int reg)
896{
897 switch (reg) {
898 case NAU8825_REG_RESET:
899 case NAU8825_REG_IRQ_STATUS:
900 case NAU8825_REG_INT_CLR_KEY_STATUS:
901 case NAU8825_REG_IMM_RMS_L:
902 case NAU8825_REG_IMM_RMS_R:
903 case NAU8825_REG_I2C_DEVICE_ID:
904 case NAU8825_REG_SARDOUT_RAM_STATUS:
905 case NAU8825_REG_CHARGE_PUMP_INPUT_READ:
906 case NAU8825_REG_GENERAL_STATUS:
18d8306d 907 case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10:
34ca27f3
AP		 908 return true;
909 default:
910 return false;
911 }
912}
913
eeef16ac
JH		 914static int nau8825_adc_event(struct snd_soc_dapm_widget *w,
915 struct snd_kcontrol *kcontrol, int event)
916{
45101122
KM		 917 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
918 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
eeef16ac
JH		 919
920 switch (event) {
921 case SND_SOC_DAPM_POST_PMU:
d070f7c7 922 msleep(125);
eeef16ac
JH		 923 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
924 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
925 break;
926 case SND_SOC_DAPM_POST_PMD:
927 if (!nau8825->irq)
928 regmap_update_bits(nau8825->regmap,
929 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
930 break;
931 default:
932 return -EINVAL;
933 }
934
935 return 0;
936}
937
34ca27f3
AP		 938static int nau8825_pump_event(struct snd_soc_dapm_widget *w,
939 struct snd_kcontrol *kcontrol, int event)
940{
45101122
KM		 941 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
942 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
45d5eb3a 943
34ca27f3
AP		 944 switch (event) {
945 case SND_SOC_DAPM_POST_PMU:
946 /* Prevent startup click by letting charge pump to ramp up */
947 msleep(10);
45d5eb3a
JH		 948 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
949 NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW);
950 break;
951 case SND_SOC_DAPM_PRE_PMD:
952 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
953 NAU8825_JAMNODCLOW, 0);
954 break;
955 default:
956 return -EINVAL;
957 }
958
959 return 0;
960}
961
962static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w,
963 struct snd_kcontrol *kcontrol, int event)
964{
45101122
KM		 965 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
966 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
45d5eb3a
JH		 967
968 switch (event) {
969 case SND_SOC_DAPM_PRE_PMU:
970 /* Disables the TESTDAC to let DAC signal pass through. */
971 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
972 NAU8825_BIAS_TESTDAC_EN, 0);
973 break;
974 case SND_SOC_DAPM_POST_PMD:
975 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
976 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
34ca27f3
AP		 977 break;
978 default:
979 return -EINVAL;
980 }
981
982 return 0;
983}
984
18d8306d
JH		 985static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol,
986 struct snd_ctl_elem_value *ucontrol)
987{
988 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
989 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
990
991 if (!component->regmap)
992 return -EINVAL;
993
994 regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1,
995 ucontrol->value.bytes.data, params->max);
996 return 0;
997}
998
999static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1001{
1002 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1003 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
1004 void *data;
1005
1006 if (!component->regmap)
1007 return -EINVAL;
1008
1009 data = kmemdup(ucontrol->value.bytes.data,
1010 params->max, GFP_KERNEL | GFP_DMA);
1011 if (!data)
1012 return -ENOMEM;
1013
1014 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
1015 NAU8825_BIQ_WRT_EN, 0);
1016 regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1,
1017 data, params->max);
1018 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
1019 NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN);
1020
1021 kfree(data);
1022 return 0;
1023}
1024
1025static const char * const nau8825_biq_path[] = {
1026 "ADC", "DAC"
1027};
1028
1029static const struct soc_enum nau8825_biq_path_enum =
1030 SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT,
1031 ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path);
1032
34ca27f3
AP		 1033static const char * const nau8825_adc_decimation[] = {
1034 "32", "64", "128", "256"
1035};
1036
1037static const struct soc_enum nau8825_adc_decimation_enum =
1038 SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT,
1039 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation);
1040
1041static const char * const nau8825_dac_oversampl[] = {
1042 "64", "256", "128", "", "32"
1043};
1044
1045static const struct soc_enum nau8825_dac_oversampl_enum =
1046 SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT,
1047 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl);
1048
1049static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
1050static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
1051static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
1052static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
1053static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
1054
1055static const struct snd_kcontrol_new nau8825_controls[] = {
1056 SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1057 0, 0xff, 0, adc_vol_tlv),
1058 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1059 12, 8, 0x0f, 0, sidetone_vol_tlv),
1060 SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL,
1061 6, 0, 0x3f, 1, dac_vol_tlv),
1062 SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL,
1063 8, 37, 0, fepga_gain_tlv),
1064 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL,
1065 0, 8, 0xff, 0, crosstalk_vol_tlv),
1066
1067 SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum),
1068 SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum),
18d8306d
JH		 1069 /* programmable biquad filter */
1070 SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum),
0cbeccdf 1071 SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
18d8306d 1072 nau8825_biq_coeff_get, nau8825_biq_coeff_put),
34ca27f3
AP		 1073};
1074
1075/* DAC Mux 0x33[9] and 0x34[9] */
1076static const char * const nau8825_dac_src[] = {
1077 "DACL", "DACR",
1078};
1079
1080static SOC_ENUM_SINGLE_DECL(
1081 nau8825_dacl_enum, NAU8825_REG_DACL_CTRL,
1082 NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src);
1083
1084static SOC_ENUM_SINGLE_DECL(
1085 nau8825_dacr_enum, NAU8825_REG_DACR_CTRL,
1086 NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src);
1087
1088static const struct snd_kcontrol_new nau8825_dacl_mux =
1089 SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum);
1090
1091static const struct snd_kcontrol_new nau8825_dacr_mux =
1092 SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum);
1093
1094
1095static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = {
1096 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2,
1097 15, 1),
1098
1099 SND_SOC_DAPM_INPUT("MIC"),
1100 SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0),
1101
1102 SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0,
1103 NULL, 0),
1104
eeef16ac
JH		 1105 SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0,
1106 nau8825_adc_event, SND_SOC_DAPM_POST_PMU |
1107 SND_SOC_DAPM_POST_PMD),
34ca27f3
AP		 1108 SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
1109 SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
1110 0),
1111
e6cee900
BZ		 1112 /* ADC for button press detection. A dapm supply widget is used to
1113 * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON
1114 * during suspend.
1115 */
1116 SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL,
1117 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0),
34ca27f3 1118
45d5eb3a
JH		 1119 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
1120 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
1121 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0),
1122 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0),
34ca27f3
AP		 1123
1124 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
1125 NAU8825_ENABLE_DACR_SFT, 0),
1126 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
1127 NAU8825_ENABLE_DACL_SFT, 0),
1128 SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
1129
1130 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux),
1131 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux),
1132
45d5eb3a
JH		 1133 SND_SOC_DAPM_PGA_S("HP amp L", 0,
1134 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0),
1135 SND_SOC_DAPM_PGA_S("HP amp R", 0,
1136 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0),
34ca27f3 1137
45d5eb3a
JH		 1138 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0,
1139 nau8825_pump_event, SND_SOC_DAPM_POST_PMU |
1140 SND_SOC_DAPM_PRE_PMD),
34ca27f3 1141
45d5eb3a 1142 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
34ca27f3 1143 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0),
45d5eb3a 1144 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
34ca27f3 1145 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0),
45d5eb3a 1146 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
34ca27f3 1147 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
45d5eb3a 1148 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
34ca27f3 1149 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
45d5eb3a 1150 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
34ca27f3 1151 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
45d5eb3a 1152 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
34ca27f3
AP		 1153 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
1154
45d5eb3a
JH		 1155 SND_SOC_DAPM_PGA_S("Output DACL", 7,
1156 NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event,
1157 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1158 SND_SOC_DAPM_PGA_S("Output DACR", 7,
1159 NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event,
1160 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1161
1162 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
1163 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
1164 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0),
1165 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
1166 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0),
1167
1168 /* High current HPOL/R boost driver */
1169 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
1170 NAU8825_REG_BOOST, 9, 1, NULL, 0),
1171
1172 /* Class G operation control*/
1173 SND_SOC_DAPM_PGA_S("Class G", 10,
1174 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0),
34ca27f3
AP		 1175
1176 SND_SOC_DAPM_OUTPUT("HPOL"),
1177 SND_SOC_DAPM_OUTPUT("HPOR"),
1178};
1179
1180static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
1181 {"Frontend PGA", NULL, "MIC"},
1182 {"ADC", NULL, "Frontend PGA"},
1183 {"ADC", NULL, "ADC Clock"},
1184 {"ADC", NULL, "ADC Power"},
1185 {"AIFTX", NULL, "ADC"},
1186
1187 {"DDACL", NULL, "Playback"},
1188 {"DDACR", NULL, "Playback"},
1189 {"DDACL", NULL, "DDAC Clock"},
1190 {"DDACR", NULL, "DDAC Clock"},
1191 {"DACL Mux", "DACL", "DDACL"},
1192 {"DACL Mux", "DACR", "DDACR"},
1193 {"DACR Mux", "DACL", "DDACL"},
1194 {"DACR Mux", "DACR", "DDACR"},
1195 {"HP amp L", NULL, "DACL Mux"},
1196 {"HP amp R", NULL, "DACR Mux"},
45d5eb3a
JH		 1197 {"Charge Pump", NULL, "HP amp L"},
1198 {"Charge Pump", NULL, "HP amp R"},
1199 {"ADACL", NULL, "Charge Pump"},
1200 {"ADACR", NULL, "Charge Pump"},
1201 {"ADACL Clock", NULL, "ADACL"},
1202 {"ADACR Clock", NULL, "ADACR"},
1203 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
1204 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
34ca27f3
AP		 1205 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
1206 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
1207 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
1208 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
1209 {"Output DACL", NULL, "Output Driver L Stage 3"},
1210 {"Output DACR", NULL, "Output Driver R Stage 3"},
45d5eb3a
JH		 1211 {"HPOL Pulldown", NULL, "Output DACL"},
1212 {"HPOR Pulldown", NULL, "Output DACR"},
1213 {"HP Boost Driver", NULL, "HPOL Pulldown"},
1214 {"HP Boost Driver", NULL, "HPOR Pulldown"},
1215 {"Class G", NULL, "HP Boost Driver"},
1216 {"HPOL", NULL, "Class G"},
1217 {"HPOR", NULL, "Class G"},
34ca27f3
AP		 1218};
1219
d6d19745
JH		 1220static int nau8825_clock_check(struct nau8825 *nau8825,
1221 int stream, int rate, int osr)
1222{
1223 int osrate;
1224
1225 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1226 if (osr >= ARRAY_SIZE(osr_dac_sel))
1227 return -EINVAL;
1228 osrate = osr_dac_sel[osr].osr;
1229 } else {
1230 if (osr >= ARRAY_SIZE(osr_adc_sel))
1231 return -EINVAL;
1232 osrate = osr_adc_sel[osr].osr;
1233 }
1234
1235 if (!osrate || rate * osr > CLK_DA_AD_MAX) {
1236 dev_err(nau8825->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n");
1237 return -EINVAL;
1238 }
1239
1240 return 0;
1241}
1242
34ca27f3
AP		 1243static int nau8825_hw_params(struct snd_pcm_substream *substream,
1244 struct snd_pcm_hw_params *params,
1245 struct snd_soc_dai *dai)
1246{
45101122
KM		 1247 struct snd_soc_component *component = dai->component;
1248 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
1e561f61 1249 unsigned int val_len = 0, osr, ctrl_val, bclk_fs, bclk_div;
34ca27f3 1250
2263fddc 1251 nau8825_sema_acquire(nau8825, 3 * HZ);
ca6ac305 1252
d6d19745
JH		 1253 /* CLK_DAC or CLK_ADC = OSR * FS
1254 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
1255 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
1256 * values must be selected such that the maximum frequency is less
1257 * than 6.144 MHz.
1258 */
1259 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1260 regmap_read(nau8825->regmap, NAU8825_REG_DAC_CTRL1, &osr);
1261 osr &= NAU8825_DAC_OVERSAMPLE_MASK;
1262 if (nau8825_clock_check(nau8825, substream->stream,
70424d8e
JH		 1263 params_rate(params), osr)) {
1264 nau8825_sema_release(nau8825);
d6d19745 1265 return -EINVAL;
70424d8e 1266 }
d6d19745
JH		 1267 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1268 NAU8825_CLK_DAC_SRC_MASK,
1269 osr_dac_sel[osr].clk_src << NAU8825_CLK_DAC_SRC_SFT);
1270 } else {
1271 regmap_read(nau8825->regmap, NAU8825_REG_ADC_RATE, &osr);
1272 osr &= NAU8825_ADC_SYNC_DOWN_MASK;
1273 if (nau8825_clock_check(nau8825, substream->stream,
70424d8e
JH		 1274 params_rate(params), osr)) {
1275 nau8825_sema_release(nau8825);
d6d19745 1276 return -EINVAL;
70424d8e 1277 }
d6d19745
JH		 1278 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1279 NAU8825_CLK_ADC_SRC_MASK,
1280 osr_adc_sel[osr].clk_src << NAU8825_CLK_ADC_SRC_SFT);
1281 }
1282
1e561f61
JH		 1283 /* make BCLK and LRC divde configuration if the codec as master. */
1284 regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, &ctrl_val);
1285 if (ctrl_val & NAU8825_I2S_MS_MASTER) {
1286 /* get the bclk and fs ratio */
1287 bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
1288 if (bclk_fs <= 32)
1289 bclk_div = 2;
1290 else if (bclk_fs <= 64)
1291 bclk_div = 1;
1292 else if (bclk_fs <= 128)
1293 bclk_div = 0;
70424d8e
JH		 1294 else {
1295 nau8825_sema_release(nau8825);
1e561f61 1296 return -EINVAL;
70424d8e 1297 }
1e561f61
JH		 1298 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1299 NAU8825_I2S_LRC_DIV_MASK | NAU8825_I2S_BLK_DIV_MASK,
1300 ((bclk_div + 1) << NAU8825_I2S_LRC_DIV_SFT) | bclk_div);
1301 }
1302
34ca27f3
AP		 1303 switch (params_width(params)) {
1304 case 16:
1305 val_len |= NAU8825_I2S_DL_16;
1306 break;
1307 case 20:
1308 val_len |= NAU8825_I2S_DL_20;
1309 break;
1310 case 24:
1311 val_len |= NAU8825_I2S_DL_24;
1312 break;
1313 case 32:
1314 val_len |= NAU8825_I2S_DL_32;
1315 break;
1316 default:
70424d8e 1317 nau8825_sema_release(nau8825);
34ca27f3
AP		 1318 return -EINVAL;
1319 }
1320
1321 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1322 NAU8825_I2S_DL_MASK, val_len);
1323
3dfcd346 1324 /* Release the semaphore. */
ca6ac305
JH		 1325 nau8825_sema_release(nau8825);
1326
34ca27f3
AP		 1327 return 0;
1328}
1329
1330static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1331{
45101122
KM		 1332 struct snd_soc_component *component = codec_dai->component;
1333 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
34ca27f3
AP		 1334 unsigned int ctrl1_val = 0, ctrl2_val = 0;
1335
1336 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1337 case SND_SOC_DAIFMT_CBM_CFM:
1338 ctrl2_val |= NAU8825_I2S_MS_MASTER;
1339 break;
1340 case SND_SOC_DAIFMT_CBS_CFS:
1341 break;
1342 default:
1343 return -EINVAL;
1344 }
1345
1346 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1347 case SND_SOC_DAIFMT_NB_NF:
1348 break;
1349 case SND_SOC_DAIFMT_IB_NF:
1350 ctrl1_val |= NAU8825_I2S_BP_INV;
1351 break;
1352 default:
1353 return -EINVAL;
1354 }
1355
1356 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1357 case SND_SOC_DAIFMT_I2S:
1358 ctrl1_val |= NAU8825_I2S_DF_I2S;
1359 break;
1360 case SND_SOC_DAIFMT_LEFT_J:
1361 ctrl1_val |= NAU8825_I2S_DF_LEFT;
1362 break;
1363 case SND_SOC_DAIFMT_RIGHT_J:
1364 ctrl1_val |= NAU8825_I2S_DF_RIGTH;
1365 break;
1366 case SND_SOC_DAIFMT_DSP_A:
1367 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1368 break;
1369 case SND_SOC_DAIFMT_DSP_B:
1370 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1371 ctrl1_val |= NAU8825_I2S_PCMB_EN;
1372 break;
1373 default:
1374 return -EINVAL;
1375 }
1376
70424d8e
JH		 1377 nau8825_sema_acquire(nau8825, 3 * HZ);
1378
34ca27f3
AP		 1379 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1380 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
1381 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
1382 ctrl1_val);
1383 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1384 NAU8825_I2S_MS_MASK, ctrl2_val);
1385
3dfcd346 1386 /* Release the semaphore. */
ca6ac305
JH		 1387 nau8825_sema_release(nau8825);
1388
34ca27f3
AP		 1389 return 0;
1390}
1391
1392static const struct snd_soc_dai_ops nau8825_dai_ops = {
1393 .hw_params = nau8825_hw_params,
1394 .set_fmt = nau8825_set_dai_fmt,
1395};
1396
1397#define NAU8825_RATES SNDRV_PCM_RATE_8000_192000
1398#define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1399 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1400
1401static struct snd_soc_dai_driver nau8825_dai = {
1402 .name = "nau8825-hifi",
1403 .playback = {
1404 .stream_name = "Playback",
1405 .channels_min = 1,
1406 .channels_max = 2,
1407 .rates = NAU8825_RATES,
1408 .formats = NAU8825_FORMATS,
1409 },
1410 .capture = {
1411 .stream_name = "Capture",
1412 .channels_min = 1,
1413 .channels_max = 1,
1414 .rates = NAU8825_RATES,
1415 .formats = NAU8825_FORMATS,
1416 },
1417 .ops = &nau8825_dai_ops,
1418};
1419
1420/**
1421 * nau8825_enable_jack_detect - Specify a jack for event reporting
1422 *
1423 * @component: component to register the jack with
1424 * @jack: jack to use to report headset and button events on
1425 *
1426 * After this function has been called the headset insert/remove and button
1427 * events will be routed to the given jack. Jack can be null to stop
1428 * reporting.
1429 */
45101122 1430int nau8825_enable_jack_detect(struct snd_soc_component *component,
34ca27f3
AP		 1431 struct snd_soc_jack *jack)
1432{
45101122 1433 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
34ca27f3
AP		 1434 struct regmap *regmap = nau8825->regmap;
1435
1436 nau8825->jack = jack;
1437
1438 /* Ground HP Outputs[1:0], needed for headset auto detection
1439 * Enable Automatic Mic/Gnd switching reading on insert interrupt[6]
1440 */
1441 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1442 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
1443 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
1444
34ca27f3
AP		 1445 return 0;
1446}
1447EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect);
1448
1449
1450static bool nau8825_is_jack_inserted(struct regmap *regmap)
1451{
bff03e81
JH		 1452 bool active_high, is_high;
1453 int status, jkdet;
34ca27f3 1454
bff03e81 1455 regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet);
308e3e0b 1456 active_high = jkdet & NAU8825_JACK_POLARITY;
34ca27f3 1457 regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status);
308e3e0b 1458 is_high = status & NAU8825_GPIO2JD1;
bff03e81
JH		 1459 /* return jack connection status according to jack insertion logic
1460 * active high or active low.
1461 */
1462 return active_high == is_high;
34ca27f3
AP		 1463}
1464
1465static void nau8825_restart_jack_detection(struct regmap *regmap)
1466{
1467 /* this will restart the entire jack detection process including MIC/GND
1468 * switching and create interrupts. We have to go from 0 to 1 and back
1469 * to 0 to restart.
1470 */
1471 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1472 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART);
1473 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1474 NAU8825_JACK_DET_RESTART, 0);
1475}
1476
2ec30f60
JH		 1477static void nau8825_int_status_clear_all(struct regmap *regmap)
1478{
1479 int active_irq, clear_irq, i;
1480
1481 /* Reset the intrruption status from rightmost bit if the corres-
1482 * ponding irq event occurs.
1483 */
1484 regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq);
1485 for (i = 0; i < NAU8825_REG_DATA_LEN; i++) {
1486 clear_irq = (0x1 << i);
1487 if (active_irq & clear_irq)
1488 regmap_write(regmap,
1489 NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1490 }
1491}
1492
34ca27f3
AP		 1493static void nau8825_eject_jack(struct nau8825 *nau8825)
1494{
1495 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1496 struct regmap *regmap = nau8825->regmap;
1497
b50455fa
JH		 1498 /* Force to cancel the cross talk detection process */
1499 nau8825_xtalk_cancel(nau8825);
1500
34ca27f3
AP		 1501 snd_soc_dapm_disable_pin(dapm, "SAR");
1502 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
1503 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
1504 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1505 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
1506 /* ground HPL/HPR, MICGRND1/2 */
1507 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf);
1508
1509 snd_soc_dapm_sync(dapm);
2ec30f60
JH		 1510
1511 /* Clear all interruption status */
1512 nau8825_int_status_clear_all(regmap);
1513
1514 /* Enable the insertion interruption, disable the ejection inter-
1515 * ruption, and then bypass de-bounce circuit.
1516 */
1517 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
1518 NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS,
1519 NAU8825_IRQ_EJECT_DIS);
1520 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1521 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1522 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN,
1523 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1524 NAU8825_IRQ_HEADSET_COMPLETE_EN);
1525 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1526 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
1527
1528 /* Disable ADC needed for interruptions at audo mode */
1529 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1530 NAU8825_ENABLE_ADC, 0);
1531
1532 /* Close clock for jack type detection at manual mode */
1533 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
1534}
1535
1536/* Enable audo mode interruptions with internal clock. */
1537static void nau8825_setup_auto_irq(struct nau8825 *nau8825)
1538{
1539 struct regmap *regmap = nau8825->regmap;
1540
1541 /* Enable headset jack type detection complete interruption and
1542 * jack ejection interruption.
1543 */
1544 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1545 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0);
1546
1547 /* Enable internal VCO needed for interruptions */
1548 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
1549
1550 /* Enable ADC needed for interruptions */
1551 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1552 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
1553
1554 /* Chip needs one FSCLK cycle in order to generate interruptions,
1555 * as we cannot guarantee one will be provided by the system. Turning
1556 * master mode on then off enables us to generate that FSCLK cycle
1557 * with a minimum of contention on the clock bus.
1558 */
1559 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1560 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
1561 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1562 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
1563
1564 /* Not bypass de-bounce circuit */
1565 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1566 NAU8825_JACK_DET_DB_BYPASS, 0);
1567
1568 /* Unmask all interruptions */
1569 regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0);
1570
1571 /* Restart the jack detection process at auto mode */
1572 nau8825_restart_jack_detection(regmap);
34ca27f3
AP		 1573}
1574
1575static int nau8825_button_decode(int value)
1576{
1577 int buttons = 0;
1578
1579 /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */
1580 if (value & BIT(0))
1581 buttons |= SND_JACK_BTN_0;
1582 if (value & BIT(1))
1583 buttons |= SND_JACK_BTN_1;
1584 if (value & BIT(2))
1585 buttons |= SND_JACK_BTN_2;
1586 if (value & BIT(3))
1587 buttons |= SND_JACK_BTN_3;
1588 if (value & BIT(4))
1589 buttons |= SND_JACK_BTN_4;
1590 if (value & BIT(5))
1591 buttons |= SND_JACK_BTN_5;
1592
1593 return buttons;
1594}
1595
1596static int nau8825_jack_insert(struct nau8825 *nau8825)
1597{
1598 struct regmap *regmap = nau8825->regmap;
1599 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1600 int jack_status_reg, mic_detected;
1601 int type = 0;
1602
1603 regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg);
1604 mic_detected = (jack_status_reg >> 10) & 3;
b50455fa
JH		 1605 /* The JKSLV and JKR2 all detected in high impedance headset */
1606 if (mic_detected == 0x3)
1607 nau8825->high_imped = true;
1608 else
1609 nau8825->high_imped = false;
34ca27f3
AP		 1610
1611 switch (mic_detected) {
1612 case 0:
1613 /* no mic */
1614 type = SND_JACK_HEADPHONE;
1615 break;
1616 case 1:
1617 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
1618 type = SND_JACK_HEADSET;
1619
1620 /* Unground MICGND1 */
1621 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1622 1 << 2);
1623 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
1624 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1625 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1626 NAU8825_MICBIAS_JKR2);
1627 /* Attach SARADC to MICGND1 */
1628 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1629 NAU8825_SAR_INPUT_MASK,
1630 NAU8825_SAR_INPUT_JKR2);
1631
1632 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1633 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1634 snd_soc_dapm_sync(dapm);
1635 break;
1636 case 2:
34ca27f3
AP		 1637 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
1638 type = SND_JACK_HEADSET;
1639
1640 /* Unground MICGND2 */
1641 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1642 2 << 2);
1643 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
1644 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1645 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1646 NAU8825_MICBIAS_JKSLV);
1647 /* Attach SARADC to MICGND2 */
1648 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1649 NAU8825_SAR_INPUT_MASK,
1650 NAU8825_SAR_INPUT_JKSLV);
1651
1652 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1653 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1654 snd_soc_dapm_sync(dapm);
1655 break;
8fe19795
JH		 1656 case 3:
1657 /* detect error case */
1658 dev_err(nau8825->dev, "detection error; disable mic function\n");
1659 type = SND_JACK_HEADPHONE;
1660 break;
34ca27f3
AP		 1661 }
1662
45d5eb3a
JH		 1663 /* Leaving HPOL/R grounded after jack insert by default. They will be
1664 * ungrounded as part of the widget power up sequence at the beginning
1665 * of playback to reduce pop.
1666 */
34ca27f3
AP		 1667 return type;
1668}
1669
1670#define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
1671 SND_JACK_BTN_2 | SND_JACK_BTN_3)
1672
1673static irqreturn_t nau8825_interrupt(int irq, void *data)
1674{
1675 struct nau8825 *nau8825 = (struct nau8825 *)data;
1676 struct regmap *regmap = nau8825->regmap;
1677 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1678
e6cee900
BZ		 1679 if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) {
1680 dev_err(nau8825->dev, "failed to read irq status\n");
1681 return IRQ_NONE;
1682 }
34ca27f3
AP		 1683
1684 if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
1685 NAU8825_JACK_EJECTION_DETECTED) {
1686
1687 nau8825_eject_jack(nau8825);
1688 event_mask |= SND_JACK_HEADSET;
1689 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
1690 } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) {
1691 int key_status;
1692
1693 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS,
1694 &key_status);
1695
1696 /* upper 8 bits of the register are for short pressed keys,
1697 * lower 8 bits - for long pressed buttons
1698 */
1699 nau8825->button_pressed = nau8825_button_decode(
1700 key_status >> 8);
1701
1702 event |= nau8825->button_pressed;
1703 event_mask |= NAU8825_BUTTONS;
1704 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
1705 } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) {
1706 event_mask = NAU8825_BUTTONS;
1707 clear_irq = NAU8825_KEY_RELEASE_IRQ;
1708 } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
1709 if (nau8825_is_jack_inserted(regmap)) {
1710 event |= nau8825_jack_insert(nau8825);
226d7449 1711 if (nau8825->xtalk_enable && !nau8825->high_imped) {
b50455fa
JH		 1712 /* Apply the cross talk suppression in the
1713 * headset without high impedance.
1714 */
1715 if (!nau8825->xtalk_protect) {
1716 /* Raise protection for cross talk de-
1717 * tection if no protection before.
1718 * The driver has to cancel the pro-
1719 * cess and restore changes if process
1720 * is ongoing when ejection.
1721 */
06746c67 1722 int ret;
b50455fa 1723 nau8825->xtalk_protect = true;
06746c67 1724 ret = nau8825_sema_acquire(nau8825, 0);
70424d8e 1725 if (ret)
06746c67 1726 nau8825->xtalk_protect = false;
b50455fa
JH		 1727 }
1728 /* Startup cross talk detection process */
fa25b4f5
JH		 1729 if (nau8825->xtalk_protect) {
1730 nau8825->xtalk_state =
1731 NAU8825_XTALK_PREPARE;
1732 schedule_work(&nau8825->xtalk_work);
1733 }
b50455fa
JH		 1734 } else {
1735 /* The cross talk suppression shouldn't apply
1736 * in the headset with high impedance. Thus,
1737 * relieve the protection raised before.
1738 */
1739 if (nau8825->xtalk_protect) {
1740 nau8825_sema_release(nau8825);
1741 nau8825->xtalk_protect = false;
1742 }
1743 }
34ca27f3
AP		 1744 } else {
1745 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
1746 nau8825_eject_jack(nau8825);
1747 }
1748
1749 event_mask |= SND_JACK_HEADSET;
1750 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
b50455fa
JH		 1751 /* Record the interruption report event for driver to report
1752 * the event later. The jack report will delay until cross
1753 * talk detection process is done.
1754 */
1755 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) {
1756 nau8825->xtalk_event = event;
1757 nau8825->xtalk_event_mask = event_mask;
1758 }
1759 } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) {
fa25b4f5
JH		 1760 /* crosstalk detection enable and process on going */
1761 if (nau8825->xtalk_enable && nau8825->xtalk_protect)
226d7449 1762 schedule_work(&nau8825->xtalk_work);
b50455fa 1763 clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ;
2ec30f60
JH		 1764 } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) ==
1765 NAU8825_JACK_INSERTION_DETECTED) {
1766 /* One more step to check GPIO status directly. Thus, the
1767 * driver can confirm the real insertion interruption because
1768 * the intrruption at manual mode has bypassed debounce
1769 * circuit which can get rid of unstable status.
1770 */
1771 if (nau8825_is_jack_inserted(regmap)) {
1772 /* Turn off insertion interruption at manual mode */
1773 regmap_update_bits(regmap,
1774 NAU8825_REG_INTERRUPT_DIS_CTRL,
1775 NAU8825_IRQ_INSERT_DIS,
1776 NAU8825_IRQ_INSERT_DIS);
1777 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1778 NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN);
1779 /* Enable interruption for jack type detection at audo
1780 * mode which can detect microphone and jack type.
1781 */
1782 nau8825_setup_auto_irq(nau8825);
1783 }
34ca27f3
AP		 1784 }
1785
1786 if (!clear_irq)
1787 clear_irq = active_irq;
1788 /* clears the rightmost interruption */
1789 regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1790
b50455fa
JH		 1791 /* Delay jack report until cross talk detection is done. It can avoid
1792 * application to do playback preparation when cross talk detection
1793 * process is still working. Otherwise, the resource like clock and
1794 * power will be issued by them at the same time and conflict happens.
1795 */
1796 if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE)
34ca27f3
AP		 1797 snd_soc_jack_report(nau8825->jack, event, event_mask);
1798
1799 return IRQ_HANDLED;
1800}
1801
1802static void nau8825_setup_buttons(struct nau8825 *nau8825)
1803{
1804 struct regmap *regmap = nau8825->regmap;
1805
1806 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1807 NAU8825_SAR_TRACKING_GAIN_MASK,
1808 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
1809 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1810 NAU8825_SAR_COMPARE_TIME_MASK,
1811 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
1812 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1813 NAU8825_SAR_SAMPLING_TIME_MASK,
1814 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
1815
1816 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1817 NAU8825_KEYDET_LEVELS_NR_MASK,
1818 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
1819 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1820 NAU8825_KEYDET_HYSTERESIS_MASK,
1821 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
1822 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1823 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK,
1824 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
1825
1826 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1,
1827 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
1828 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2,
1829 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
1830 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3,
1831 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
1832 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4,
1833 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
1834
1835 /* Enable short press and release interruptions */
1836 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1837 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN,
1838 0);
1839}
1840
1841static void nau8825_init_regs(struct nau8825 *nau8825)
1842{
1843 struct regmap *regmap = nau8825->regmap;
1844
45d5eb3a
JH		 1845 /* Latch IIC LSB value */
1846 regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001);
34ca27f3
AP		 1847 /* Enable Bias/Vmid */
1848 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1849 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID);
1850 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
1851 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN);
1852
1853 /* VMID Tieoff */
1854 regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ,
1855 NAU8825_BIAS_VMID_SEL_MASK,
1856 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
1857 /* Disable Boost Driver, Automatic Short circuit protection enable */
1858 regmap_update_bits(regmap, NAU8825_REG_BOOST,
45d5eb3a
JH		 1859 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1860 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN,
1861 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1862 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN);
34ca27f3
AP		 1863
1864 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1865 NAU8825_JKDET_OUTPUT_EN,
1866 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
1867 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1868 NAU8825_JKDET_PULL_EN,
1869 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
1870 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1871 NAU8825_JKDET_PULL_UP,
1872 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
1873 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1874 NAU8825_JACK_POLARITY,
1875 /* jkdet_polarity - 1 is for active-low */
1876 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
1877
1878 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1879 NAU8825_JACK_INSERT_DEBOUNCE_MASK,
1880 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
1881 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1882 NAU8825_JACK_EJECT_DEBOUNCE_MASK,
1883 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
1884
1885 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1886 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff);
1887
1888 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1889 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
1890
1891 if (nau8825->sar_threshold_num)
1892 nau8825_setup_buttons(nau8825);
1893
1894 /* Default oversampling/decimations settings are unusable
1895 * (audible hiss). Set it to something better.
1896 */
1897 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
5f1516d5
JH		 1898 NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN,
1899 NAU8825_ADC_SYNC_DOWN_64);
34ca27f3 1900 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
d6d19745 1901 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64);
45d5eb3a
JH		 1902 /* Disable DACR/L power */
1903 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
1904 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
1905 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
1906 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
1907 * signal to avoid any glitches due to power up transients in both
1908 * the analog and digital DAC circuit.
1909 */
1910 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1911 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
1912 /* CICCLP off */
1913 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1914 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF);
1915
1916 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
1917 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2,
1918 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1919 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB,
1920 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1921 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB);
1922 /* Class G timer 64ms */
1923 regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL,
1924 NAU8825_CLASSG_TIMER_MASK,
1925 0x20 << NAU8825_CLASSG_TIMER_SFT);
1926 /* DAC clock delay 2ns, VREF */
1927 regmap_update_bits(regmap, NAU8825_REG_RDAC,
1928 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK,
1929 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) |
1930 (0x3 << NAU8825_RDAC_VREF_SFT));
3f039169
JH		 1931 /* Config L/R channel */
1932 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
1933 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L);
1934 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
1935 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R);
93dfec75
JH		 1936 /* Disable short Frame Sync detection logic */
1937 regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT,
1938 NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET);
34ca27f3
AP		 1939}
1940
1941static const struct regmap_config nau8825_regmap_config = {
2ec30f60
JH		 1942 .val_bits = NAU8825_REG_DATA_LEN,
1943 .reg_bits = NAU8825_REG_ADDR_LEN,
34ca27f3
AP		 1944
1945 .max_register = NAU8825_REG_MAX,
1946 .readable_reg = nau8825_readable_reg,
1947 .writeable_reg = nau8825_writeable_reg,
1948 .volatile_reg = nau8825_volatile_reg,
1949
1950 .cache_type = REGCACHE_RBTREE,
1951 .reg_defaults = nau8825_reg_defaults,
1952 .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults),
1953};
1954
45101122 1955static int nau8825_component_probe(struct snd_soc_component *component)
34ca27f3 1956{
45101122
KM		 1957 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
1958 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
34ca27f3
AP		 1959
1960 nau8825->dapm = dapm;
1961
34ca27f3
AP		 1962 return 0;
1963}
1964
45101122 1965static void nau8825_component_remove(struct snd_soc_component *component)
b50455fa 1966{
45101122 1967 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
b50455fa
JH		 1968
1969 /* Cancel and reset cross tak suppresstion detection funciton */
1970 nau8825_xtalk_cancel(nau8825);
b50455fa
JH		 1971}
1972
c86ba612
BZ		 1973/**
1974 * nau8825_calc_fll_param - Calculate FLL parameters.
1975 * @fll_in: external clock provided to codec.
1976 * @fs: sampling rate.
1977 * @fll_param: Pointer to structure of FLL parameters.
1978 *
1979 * Calculate FLL parameters to configure codec.
1980 *
1981 * Returns 0 for success or negative error code.
1982 */
1983static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
1984 struct nau8825_fll *fll_param)
1985{
407c71b6
JH		 1986 u64 fvco, fvco_max;
1987 unsigned int fref, i, fvco_sel;
c86ba612
BZ		 1988
1989 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
1990 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1991 * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
1992 */
1993 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1994 fref = fll_in / fll_pre_scalar[i].param;
1995 if (fref <= NAU_FREF_MAX)
1996 break;
1997 }
1998 if (i == ARRAY_SIZE(fll_pre_scalar))
1999 return -EINVAL;
2000 fll_param->clk_ref_div = fll_pre_scalar[i].val;
2001
2002 /* Choose the FLL ratio based on FREF */
2003 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
2004 if (fref >= fll_ratio[i].param)
2005 break;
2006 }
2007 if (i == ARRAY_SIZE(fll_ratio))
2008 return -EINVAL;
2009 fll_param->ratio = fll_ratio[i].val;
2010
2011 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
407c71b6 2012 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
c86ba612
BZ		 2013 * guaranteed across the full range of operation.
2014 * FDCO = freq_out * 2 * mclk_src_scaling
2015 */
407c71b6
JH		 2016 fvco_max = 0;
2017 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
c86ba612
BZ		 2018 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
2019 fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
407c71b6
JH		 2020 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
2021 fvco_max < fvco) {
2022 fvco_max = fvco;
2023 fvco_sel = i;
2024 }
c86ba612 2025 }
407c71b6 2026 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
c86ba612 2027 return -EINVAL;
407c71b6 2028 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
c86ba612
BZ		 2029
2030 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
2031 * input based on FDCO, FREF and FLL ratio.
2032 */
a8961cae 2033 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
c86ba612
BZ		 2034 fll_param->fll_int = (fvco >> 16) & 0x3FF;
2035 fll_param->fll_frac = fvco & 0xFFFF;
2036 return 0;
2037}
2038
2039static void nau8825_fll_apply(struct nau8825 *nau8825,
2040 struct nau8825_fll *fll_param)
2041{
2042 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
407c71b6
JH		 2043 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK,
2044 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src);
aee02c75 2045 /* Make DSP operate at high speed for better performance. */
c86ba612 2046 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
aee02c75
JH		 2047 NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK,
2048 fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT));
c86ba612
BZ		 2049 /* FLL 16-bit fractional input */
2050 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
2051 /* FLL 10-bit integer input */
2052 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
2053 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
2054 /* FLL pre-scaler */
2055 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
a1792cda
JH		 2056 NAU8825_FLL_REF_DIV_MASK,
2057 fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT);
c86ba612
BZ		 2058 /* select divided VCO input */
2059 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
407c71b6
JH		 2060 NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF);
2061 /* Disable free-running mode */
2062 regmap_update_bits(nau8825->regmap,
2063 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
2064 if (fll_param->fll_frac) {
aee02c75 2065 /* set FLL loop filter enable and cutoff frequency at 500Khz */
407c71b6
JH		 2066 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2067 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2068 NAU8825_FLL_FTR_SW_MASK,
2069 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2070 NAU8825_FLL_FTR_SW_FILTER);
2071 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
aee02c75
JH		 2072 NAU8825_SDM_EN | NAU8825_CUTOFF500,
2073 NAU8825_SDM_EN | NAU8825_CUTOFF500);
407c71b6 2074 } else {
aee02c75 2075 /* disable FLL loop filter and cutoff frequency */
407c71b6
JH		 2076 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2077 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2078 NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU);
aee02c75
JH		 2079 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
2080 NAU8825_SDM_EN | NAU8825_CUTOFF500, 0);
407c71b6 2081 }
c86ba612
BZ		 2082}
2083
2084/* freq_out must be 256*Fs in order to achieve the best performance */
45101122 2085static int nau8825_set_pll(struct snd_soc_component *component, int pll_id, int source,
c86ba612
BZ		 2086 unsigned int freq_in, unsigned int freq_out)
2087{
45101122 2088 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
c86ba612
BZ		 2089 struct nau8825_fll fll_param;
2090 int ret, fs;
2091
2092 fs = freq_out / 256;
2093 ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
2094 if (ret < 0) {
45101122 2095 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
c86ba612
BZ		 2096 return ret;
2097 }
45101122 2098 dev_dbg(component->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
c86ba612
BZ		 2099 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
2100 fll_param.fll_int, fll_param.clk_ref_div);
2101
2102 nau8825_fll_apply(nau8825, &fll_param);
2103 mdelay(2);
2104 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
2105 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2106 return 0;
2107}
2108
70543c30
JH		 2109static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
2110{
2111 int ret = 0;
2112
2113 nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
2114 if (IS_ERR(nau8825->mclk)) {
2115 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
2116 return 0;
2117 }
2118
2119 if (!nau8825->mclk_freq) {
2120 ret = clk_prepare_enable(nau8825->mclk);
2121 if (ret) {
2122 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2123 return ret;
2124 }
2125 }
2126
2127 if (nau8825->mclk_freq != freq) {
2128 freq = clk_round_rate(nau8825->mclk, freq);
2129 ret = clk_set_rate(nau8825->mclk, freq);
2130 if (ret) {
2131 dev_err(nau8825->dev, "Unable to set mclk rate\n");
2132 return ret;
2133 }
2134 nau8825->mclk_freq = freq;
2135 }
2136
2137 return 0;
2138}
2139
2ec30f60
JH		 2140static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap)
2141{
2142 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2143 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
2144 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2145 NAU8825_DCO_EN, 0);
aee02c75
JH		 2146 /* Make DSP operate as default setting for power saving. */
2147 regmap_update_bits(regmap, NAU8825_REG_FLL1,
2148 NAU8825_ICTRL_LATCH_MASK, 0);
2ec30f60
JH		 2149}
2150
34ca27f3
AP		 2151static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
2152 unsigned int freq)
2153{
2154 struct regmap *regmap = nau8825->regmap;
2155 int ret;
2156
2157 switch (clk_id) {
2ec30f60
JH		 2158 case NAU8825_CLK_DIS:
2159 /* Clock provided externally and disable internal VCO clock */
2160 nau8825_configure_mclk_as_sysclk(regmap);
2161 if (nau8825->mclk_freq) {
2162 clk_disable_unprepare(nau8825->mclk);
2163 nau8825->mclk_freq = 0;
2164 }
2165
2166 break;
34ca27f3 2167 case NAU8825_CLK_MCLK:
3dfcd346 2168 /* Acquire the semaphore to synchronize the playback and
b50455fa
JH		 2169 * interrupt handler. In order to avoid the playback inter-
2170 * fered by cross talk process, the driver make the playback
2171 * preparation halted until cross talk process finish.
2172 */
2263fddc 2173 nau8825_sema_acquire(nau8825, 3 * HZ);
2ec30f60 2174 nau8825_configure_mclk_as_sysclk(regmap);
3a561035
JH		 2175 /* MCLK not changed by clock tree */
2176 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2177 NAU8825_CLK_MCLK_SRC_MASK, 0);
3dfcd346 2178 /* Release the semaphore. */
b50455fa
JH		 2179 nau8825_sema_release(nau8825);
2180
70543c30
JH		 2181 ret = nau8825_mclk_prepare(nau8825, freq);
2182 if (ret)
2183 return ret;
34ca27f3
AP		 2184
2185 break;
2186 case NAU8825_CLK_INTERNAL:
2ec30f60
JH		 2187 if (nau8825_is_jack_inserted(nau8825->regmap)) {
2188 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2189 NAU8825_DCO_EN, NAU8825_DCO_EN);
2190 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2191 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
aee02c75
JH		 2192 /* Decrease the VCO frequency and make DSP operate
2193 * as default setting for power saving.
2194 */
2ec30f60
JH		 2195 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2196 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
2197 regmap_update_bits(regmap, NAU8825_REG_FLL1,
aee02c75 2198 NAU8825_ICTRL_LATCH_MASK |
2ec30f60
JH		 2199 NAU8825_FLL_RATIO_MASK, 0x10);
2200 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2201 NAU8825_SDM_EN, NAU8825_SDM_EN);
2202 } else {
2203 /* The clock turns off intentionally for power saving
2204 * when no headset connected.
2205 */
2206 nau8825_configure_mclk_as_sysclk(regmap);
2207 dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n");
2208 }
70543c30
JH		 2209 if (nau8825->mclk_freq) {
2210 clk_disable_unprepare(nau8825->mclk);
2211 nau8825->mclk_freq = 0;
2212 }
2213
2214 break;
2215 case NAU8825_CLK_FLL_MCLK:
3dfcd346 2216 /* Acquire the semaphore to synchronize the playback and
b50455fa
JH		 2217 * interrupt handler. In order to avoid the playback inter-
2218 * fered by cross talk process, the driver make the playback
2219 * preparation halted until cross talk process finish.
2220 */
2263fddc 2221 nau8825_sema_acquire(nau8825, 3 * HZ);
aee02c75
JH		 2222 /* Higher FLL reference input frequency can only set lower
2223 * gain error, such as 0000 for input reference from MCLK
2224 * 12.288Mhz.
2225 */
70543c30 2226 regmap_update_bits(regmap, NAU8825_REG_FLL3,
aee02c75
JH		 2227 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2228 NAU8825_FLL_CLK_SRC_MCLK | 0);
3dfcd346 2229 /* Release the semaphore. */
b50455fa
JH		 2230 nau8825_sema_release(nau8825);
2231
70543c30
JH		 2232 ret = nau8825_mclk_prepare(nau8825, freq);
2233 if (ret)
2234 return ret;
2235
2236 break;
2237 case NAU8825_CLK_FLL_BLK:
3dfcd346 2238 /* Acquire the semaphore to synchronize the playback and
b50455fa
JH		 2239 * interrupt handler. In order to avoid the playback inter-
2240 * fered by cross talk process, the driver make the playback
2241 * preparation halted until cross talk process finish.
2242 */
2263fddc 2243 nau8825_sema_acquire(nau8825, 3 * HZ);
aee02c75
JH		 2244 /* If FLL reference input is from low frequency source,
2245 * higher error gain can apply such as 0xf which has
2246 * the most sensitive gain error correction threshold,
2247 * Therefore, FLL has the most accurate DCO to
2248 * target frequency.
2249 */
70543c30 2250 regmap_update_bits(regmap, NAU8825_REG_FLL3,
aee02c75
JH		 2251 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2252 NAU8825_FLL_CLK_SRC_BLK |
2253 (0xf << NAU8825_GAIN_ERR_SFT));
3dfcd346 2254 /* Release the semaphore. */
b50455fa
JH		 2255 nau8825_sema_release(nau8825);
2256
70543c30
JH		 2257 if (nau8825->mclk_freq) {
2258 clk_disable_unprepare(nau8825->mclk);
2259 nau8825->mclk_freq = 0;
2260 }
34ca27f3 2261
70543c30
JH		 2262 break;
2263 case NAU8825_CLK_FLL_FS:
3dfcd346 2264 /* Acquire the semaphore to synchronize the playback and
b50455fa
JH		 2265 * interrupt handler. In order to avoid the playback inter-
2266 * fered by cross talk process, the driver make the playback
2267 * preparation halted until cross talk process finish.
2268 */
2263fddc 2269 nau8825_sema_acquire(nau8825, 3 * HZ);
aee02c75
JH		 2270 /* If FLL reference input is from low frequency source,
2271 * higher error gain can apply such as 0xf which has
2272 * the most sensitive gain error correction threshold,
2273 * Therefore, FLL has the most accurate DCO to
2274 * target frequency.
2275 */
70543c30 2276 regmap_update_bits(regmap, NAU8825_REG_FLL3,
aee02c75
JH		 2277 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2278 NAU8825_FLL_CLK_SRC_FS |
2279 (0xf << NAU8825_GAIN_ERR_SFT));
3dfcd346 2280 /* Release the semaphore. */
b50455fa
JH		 2281 nau8825_sema_release(nau8825);
2282
34ca27f3
AP		 2283 if (nau8825->mclk_freq) {
2284 clk_disable_unprepare(nau8825->mclk);
2285 nau8825->mclk_freq = 0;
2286 }
2287
2288 break;
2289 default:
2290 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
2291 return -EINVAL;
2292 }
2293
2294 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
2295 clk_id);
2296 return 0;
2297}
2298
45101122 2299static int nau8825_set_sysclk(struct snd_soc_component *component, int clk_id,
34ca27f3
AP		 2300 int source, unsigned int freq, int dir)
2301{
45101122 2302 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
34ca27f3
AP		 2303
2304 return nau8825_configure_sysclk(nau8825, clk_id, freq);
2305}
2306
2ec30f60
JH		 2307static int nau8825_resume_setup(struct nau8825 *nau8825)
2308{
2309 struct regmap *regmap = nau8825->regmap;
2310
2311 /* Close clock when jack type detection at manual mode */
2312 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
2313
2314 /* Clear all interruption status */
2315 nau8825_int_status_clear_all(regmap);
2316
2317 /* Enable both insertion and ejection interruptions, and then
2318 * bypass de-bounce circuit.
2319 */
2320 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
2321 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN |
2322 NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN,
2323 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN);
2324 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
2325 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
2326 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
2327 NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0);
2328
2329 return 0;
2330}
2331
45101122 2332static int nau8825_set_bias_level(struct snd_soc_component *component,
34ca27f3
AP		 2333 enum snd_soc_bias_level level)
2334{
45101122 2335 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
34ca27f3
AP		 2336 int ret;
2337
2338 switch (level) {
2339 case SND_SOC_BIAS_ON:
2340 break;
2341
2342 case SND_SOC_BIAS_PREPARE:
2343 break;
2344
2345 case SND_SOC_BIAS_STANDBY:
45101122 2346 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
34ca27f3
AP		 2347 if (nau8825->mclk_freq) {
2348 ret = clk_prepare_enable(nau8825->mclk);
2349 if (ret) {
45101122 2350 dev_err(nau8825->dev, "Unable to prepare component mclk\n");
34ca27f3
AP		 2351 return ret;
2352 }
2353 }
2ec30f60
JH		 2354 /* Setup codec configuration after resume */
2355 nau8825_resume_setup(nau8825);
34ca27f3 2356 }
34ca27f3
AP		 2357 break;
2358
2359 case SND_SOC_BIAS_OFF:
8fe19795
JH		 2360 /* Reset the configuration of jack type for detection */
2361 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
2362 regmap_update_bits(nau8825->regmap, NAU8825_REG_MIC_BIAS,
2363 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
2364 /* ground HPL/HPR, MICGRND1/2 */
2365 regmap_update_bits(nau8825->regmap,
2366 NAU8825_REG_HSD_CTRL, 0xf, 0xf);
b50455fa
JH		 2367 /* Cancel and reset cross talk detection funciton */
2368 nau8825_xtalk_cancel(nau8825);
2ec30f60
JH		 2369 /* Turn off all interruptions before system shutdown. Keep the
2370 * interruption quiet before resume setup completes.
2371 */
2372 regmap_write(nau8825->regmap,
2373 NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff);
2374 /* Disable ADC needed for interruptions at audo mode */
2375 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
2376 NAU8825_ENABLE_ADC, 0);
34ca27f3
AP		 2377 if (nau8825->mclk_freq)
2378 clk_disable_unprepare(nau8825->mclk);
34ca27f3
AP		 2379 break;
2380 }
2381 return 0;
2382}
2383
45101122 2384static int __maybe_unused nau8825_suspend(struct snd_soc_component *component)
e6cee900 2385{
45101122 2386 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
e6cee900
BZ		 2387
2388 disable_irq(nau8825->irq);
45101122 2389 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
8fe19795
JH		 2390 /* Power down codec power; don't suppoet button wakeup */
2391 snd_soc_dapm_disable_pin(nau8825->dapm, "SAR");
2392 snd_soc_dapm_disable_pin(nau8825->dapm, "MICBIAS");
2393 snd_soc_dapm_sync(nau8825->dapm);
e6cee900
BZ		 2394 regcache_cache_only(nau8825->regmap, true);
2395 regcache_mark_dirty(nau8825->regmap);
2396
2397 return 0;
2398}
2399
45101122 2400static int __maybe_unused nau8825_resume(struct snd_soc_component *component)
e6cee900 2401{
45101122 2402 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
06746c67 2403 int ret;
e6cee900 2404
e6cee900
BZ		 2405 regcache_cache_only(nau8825->regmap, false);
2406 regcache_sync(nau8825->regmap);
ca6ac305 2407 nau8825->xtalk_protect = true;
06746c67 2408 ret = nau8825_sema_acquire(nau8825, 0);
70424d8e 2409 if (ret)
06746c67 2410 nau8825->xtalk_protect = false;
e6cee900
BZ		 2411 enable_irq(nau8825->irq);
2412
e6cee900
BZ		 2413 return 0;
2414}
e6cee900 2415
45101122
KM		 2416static const struct snd_soc_component_driver nau8825_component_driver = {
2417 .probe = nau8825_component_probe,
2418 .remove = nau8825_component_remove,
2419 .set_sysclk = nau8825_set_sysclk,
2420 .set_pll = nau8825_set_pll,
2421 .set_bias_level = nau8825_set_bias_level,
2422 .suspend = nau8825_suspend,
2423 .resume = nau8825_resume,
2424 .controls = nau8825_controls,
2425 .num_controls = ARRAY_SIZE(nau8825_controls),
2426 .dapm_widgets = nau8825_dapm_widgets,
2427 .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets),
2428 .dapm_routes = nau8825_dapm_routes,
2429 .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes),
2430 .suspend_bias_off = 1,
2431 .idle_bias_on = 1,
2432 .use_pmdown_time = 1,
2433 .endianness = 1,
2434 .non_legacy_dai_naming = 1,
34ca27f3
AP		 2435};
2436
2437static void nau8825_reset_chip(struct regmap *regmap)
2438{
2439 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2440 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2441}
2442
218d2ce2
BZ		 2443static void nau8825_print_device_properties(struct nau8825 *nau8825)
2444{
2445 int i;
2446 struct device *dev = nau8825->dev;
2447
2448 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable);
2449 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable);
2450 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up);
2451 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity);
2452 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage);
2453 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance);
2454
2455 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num);
2456 for (i = 0; i < nau8825->sar_threshold_num; i++)
2457 dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
2458 nau8825->sar_threshold[i]);
2459
2460 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis);
2461 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage);
2462 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time);
2463 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time);
2464 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce);
2465 dev_dbg(dev, "jack-insert-debounce: %d\n",
2466 nau8825->jack_insert_debounce);
2467 dev_dbg(dev, "jack-eject-debounce: %d\n",
2468 nau8825->jack_eject_debounce);
226d7449
JH		 2469 dev_dbg(dev, "crosstalk-enable: %d\n",
2470 nau8825->xtalk_enable);
218d2ce2
BZ		 2471}
2472
34ca27f3
AP		 2473static int nau8825_read_device_properties(struct device *dev,
2474 struct nau8825 *nau8825) {
403d2fef 2475 int ret;
34ca27f3
AP		 2476
2477 nau8825->jkdet_enable = device_property_read_bool(dev,
2478 "nuvoton,jkdet-enable");
2479 nau8825->jkdet_pull_enable = device_property_read_bool(dev,
2480 "nuvoton,jkdet-pull-enable");
2481 nau8825->jkdet_pull_up = device_property_read_bool(dev,
2482 "nuvoton,jkdet-pull-up");
403d2fef 2483 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
34ca27f3 2484 &nau8825->jkdet_polarity);
403d2fef
JH		 2485 if (ret)
2486 nau8825->jkdet_polarity = 1;
2487 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
34ca27f3 2488 &nau8825->micbias_voltage);
403d2fef
JH		 2489 if (ret)
2490 nau8825->micbias_voltage = 6;
2491 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
34ca27f3 2492 &nau8825->vref_impedance);
403d2fef
JH		 2493 if (ret)
2494 nau8825->vref_impedance = 2;
2495 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",
34ca27f3 2496 &nau8825->sar_threshold_num);
403d2fef
JH		 2497 if (ret)
2498 nau8825->sar_threshold_num = 4;
2499 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",
34ca27f3 2500 nau8825->sar_threshold, nau8825->sar_threshold_num);
403d2fef
JH		 2501 if (ret) {
2502 nau8825->sar_threshold[0] = 0x08;
2503 nau8825->sar_threshold[1] = 0x12;
2504 nau8825->sar_threshold[2] = 0x26;
2505 nau8825->sar_threshold[3] = 0x73;
2506 }
2507 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",
34ca27f3 2508 &nau8825->sar_hysteresis);
403d2fef
JH		 2509 if (ret)
2510 nau8825->sar_hysteresis = 0;
2511 ret = device_property_read_u32(dev, "nuvoton,sar-voltage",
34ca27f3 2512 &nau8825->sar_voltage);
403d2fef
JH		 2513 if (ret)
2514 nau8825->sar_voltage = 6;
2515 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",
34ca27f3 2516 &nau8825->sar_compare_time);
403d2fef
JH		 2517 if (ret)
2518 nau8825->sar_compare_time = 1;
2519 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",
34ca27f3 2520 &nau8825->sar_sampling_time);
403d2fef
JH		 2521 if (ret)
2522 nau8825->sar_sampling_time = 1;
2523 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",
34ca27f3 2524 &nau8825->key_debounce);
403d2fef
JH		 2525 if (ret)
2526 nau8825->key_debounce = 3;
2527 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
34ca27f3 2528 &nau8825->jack_insert_debounce);
403d2fef
JH		 2529 if (ret)
2530 nau8825->jack_insert_debounce = 7;
2531 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
34ca27f3 2532 &nau8825->jack_eject_debounce);
403d2fef
JH		 2533 if (ret)
2534 nau8825->jack_eject_debounce = 0;
226d7449
JH		 2535 nau8825->xtalk_enable = device_property_read_bool(dev,
2536 "nuvoton,crosstalk-enable");
34ca27f3
AP		 2537
2538 nau8825->mclk = devm_clk_get(dev, "mclk");
2539 if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) {
2540 return -EPROBE_DEFER;
2541 } else if (PTR_ERR(nau8825->mclk) == -ENOENT) {
2542 /* The MCLK is managed externally or not used at all */
2543 nau8825->mclk = NULL;
2544 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally");
2545 } else if (IS_ERR(nau8825->mclk)) {
2546 return -EINVAL;
2547 }
2548
2549 return 0;
2550}
2551
2552static int nau8825_setup_irq(struct nau8825 *nau8825)
2553{
34ca27f3
AP		 2554 int ret;
2555
34ca27f3
AP		 2556 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
2557 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
2558 "nau8825", nau8825);
2559
2560 if (ret) {
2561 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
2562 nau8825->irq, ret);
2563 return ret;
2564 }
2565
2566 return 0;
2567}
2568
2569static int nau8825_i2c_probe(struct i2c_client *i2c,
2570 const struct i2c_device_id *id)
2571{
2572 struct device *dev = &i2c->dev;
2573 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
2574 int ret, value;
2575
2576 if (!nau8825) {
2577 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL);
2578 if (!nau8825)
2579 return -ENOMEM;
2580 ret = nau8825_read_device_properties(dev, nau8825);
2581 if (ret)
2582 return ret;
2583 }
2584
2585 i2c_set_clientdata(i2c, nau8825);
2586
2587 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
2588 if (IS_ERR(nau8825->regmap))
2589 return PTR_ERR(nau8825->regmap);
2590 nau8825->dev = dev;
2591 nau8825->irq = i2c->irq;
3dfcd346 2592 /* Initiate parameters, semaphore and work queue which are needed in
b50455fa
JH		 2593 * cross talk suppression measurment function.
2594 */
2595 nau8825->xtalk_state = NAU8825_XTALK_DONE;
2596 nau8825->xtalk_protect = false;
fa25b4f5 2597 nau8825->xtalk_baktab_initialized = false;
b50455fa
JH		 2598 sema_init(&nau8825->xtalk_sem, 1);
2599 INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work);
34ca27f3 2600
218d2ce2
BZ		 2601 nau8825_print_device_properties(nau8825);
2602
34ca27f3
AP		 2603 nau8825_reset_chip(nau8825->regmap);
2604 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
2605 if (ret < 0) {
2606 dev_err(dev, "Failed to read device id from the NAU8825: %d\n",
2607 ret);
2608 return ret;
2609 }
2610 if ((value & NAU8825_SOFTWARE_ID_MASK) !=
2611 NAU8825_SOFTWARE_ID_NAU8825) {
2612 dev_err(dev, "Not a NAU8825 chip\n");
2613 return -ENODEV;
2614 }
2615
2616 nau8825_init_regs(nau8825);
2617
2618 if (i2c->irq)
2619 nau8825_setup_irq(nau8825);
2620
45101122
KM		 2621 return devm_snd_soc_register_component(&i2c->dev,
2622 &nau8825_component_driver,
34ca27f3
AP		 2623 &nau8825_dai, 1);
2624}
2625
2626static int nau8825_i2c_remove(struct i2c_client *client)
2627{
34ca27f3
AP		 2628 return 0;
2629}
2630
2631static const struct i2c_device_id nau8825_i2c_ids[] = {
2632 { "nau8825", 0 },
2633 { }
2634};
ffd72505 2635MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids);
34ca27f3
AP		 2636
2637#ifdef CONFIG_OF
2638static const struct of_device_id nau8825_of_ids[] = {
2639 { .compatible = "nuvoton,nau8825", },
2640 {}
2641};
2642MODULE_DEVICE_TABLE(of, nau8825_of_ids);
2643#endif
2644
b3681308
FY		 2645#ifdef CONFIG_ACPI
2646static const struct acpi_device_id nau8825_acpi_match[] = {
2647 { "10508825", 0 },
2648 {},
2649};
2650MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match);
2651#endif
2652
34ca27f3
AP		 2653static struct i2c_driver nau8825_driver = {
2654 .driver = {
2655 .name = "nau8825",
34ca27f3 2656 .of_match_table = of_match_ptr(nau8825_of_ids),
b3681308 2657 .acpi_match_table = ACPI_PTR(nau8825_acpi_match),
34ca27f3
AP		 2658 },
2659 .probe = nau8825_i2c_probe,
2660 .remove = nau8825_i2c_remove,
2661 .id_table = nau8825_i2c_ids,
2662};
2663module_i2c_driver(nau8825_driver);
2664
2665MODULE_DESCRIPTION("ASoC nau8825 driver");
2666MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
2667MODULE_LICENSE("GPL");
Ubuntu Jammy Linux kernel mirror