[mirror_ubuntu-hirsute-kernel.git] / sound / soc / codecs / nau8825.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * NAU8825 ALSA SoC audio driver
 *
 * Copyright 2015 Google Inc.
 * Author: Anatol Pomozov <anatol.pomozov@chrominium.org>
 */

#ifndef __NAU8825_H__
#define __NAU8825_H__

#define NAU8825_REG_RESET		0x00
#define NAU8825_REG_ENA_CTRL		0x01
#define NAU8825_REG_IIC_ADDR_SET		0x02
#define NAU8825_REG_CLK_DIVIDER		0x03
#define NAU8825_REG_FLL1		0x04
#define NAU8825_REG_FLL2		0x05
#define NAU8825_REG_FLL3		0x06
#define NAU8825_REG_FLL4		0x07
#define NAU8825_REG_FLL5		0x08
#define NAU8825_REG_FLL6		0x09
#define NAU8825_REG_FLL_VCO_RSV		0x0a
#define NAU8825_REG_HSD_CTRL		0x0c
#define NAU8825_REG_JACK_DET_CTRL		0x0d
#define NAU8825_REG_INTERRUPT_MASK		0x0f
#define NAU8825_REG_IRQ_STATUS		0x10
#define NAU8825_REG_INT_CLR_KEY_STATUS		0x11
#define NAU8825_REG_INTERRUPT_DIS_CTRL		0x12
#define NAU8825_REG_SAR_CTRL		0x13
#define NAU8825_REG_KEYDET_CTRL		0x14
#define NAU8825_REG_VDET_THRESHOLD_1		0x15
#define NAU8825_REG_VDET_THRESHOLD_2		0x16
#define NAU8825_REG_VDET_THRESHOLD_3		0x17
#define NAU8825_REG_VDET_THRESHOLD_4		0x18
#define NAU8825_REG_GPIO34_CTRL		0x19
#define NAU8825_REG_GPIO12_CTRL		0x1a
#define NAU8825_REG_TDM_CTRL		0x1b
#define NAU8825_REG_I2S_PCM_CTRL1		0x1c
#define NAU8825_REG_I2S_PCM_CTRL2		0x1d
#define NAU8825_REG_LEFT_TIME_SLOT		0x1e
#define NAU8825_REG_RIGHT_TIME_SLOT		0x1f
#define NAU8825_REG_BIQ_CTRL		0x20
#define NAU8825_REG_BIQ_COF1		0x21
#define NAU8825_REG_BIQ_COF2		0x22
#define NAU8825_REG_BIQ_COF3		0x23
#define NAU8825_REG_BIQ_COF4		0x24
#define NAU8825_REG_BIQ_COF5		0x25
#define NAU8825_REG_BIQ_COF6		0x26
#define NAU8825_REG_BIQ_COF7		0x27
#define NAU8825_REG_BIQ_COF8		0x28
#define NAU8825_REG_BIQ_COF9		0x29
#define NAU8825_REG_BIQ_COF10		0x2a
#define NAU8825_REG_ADC_RATE		0x2b
#define NAU8825_REG_DAC_CTRL1		0x2c
#define NAU8825_REG_DAC_CTRL2		0x2d
#define NAU8825_REG_DAC_DGAIN_CTRL		0x2f
#define NAU8825_REG_ADC_DGAIN_CTRL		0x30
#define NAU8825_REG_MUTE_CTRL		0x31
#define NAU8825_REG_HSVOL_CTRL		0x32
#define NAU8825_REG_DACL_CTRL		0x33
#define NAU8825_REG_DACR_CTRL		0x34
#define NAU8825_REG_ADC_DRC_KNEE_IP12		0x38
#define NAU8825_REG_ADC_DRC_KNEE_IP34		0x39
#define NAU8825_REG_ADC_DRC_SLOPES		0x3a
#define NAU8825_REG_ADC_DRC_ATKDCY		0x3b
#define NAU8825_REG_DAC_DRC_KNEE_IP12		0x45
#define NAU8825_REG_DAC_DRC_KNEE_IP34		0x46
#define NAU8825_REG_DAC_DRC_SLOPES		0x47
#define NAU8825_REG_DAC_DRC_ATKDCY		0x48
#define NAU8825_REG_IMM_MODE_CTRL		0x4c
#define NAU8825_REG_IMM_RMS_L		0x4d
#define NAU8825_REG_IMM_RMS_R		0x4e
#define NAU8825_REG_CLASSG_CTRL		0x50
#define NAU8825_REG_OPT_EFUSE_CTRL		0x51
#define NAU8825_REG_MISC_CTRL		0x55
#define NAU8825_REG_I2C_DEVICE_ID		0x58
#define NAU8825_REG_SARDOUT_RAM_STATUS		0x59
#define NAU8825_REG_BIAS_ADJ		0x66
#define NAU8825_REG_TRIM_SETTINGS		0x68
#define NAU8825_REG_ANALOG_CONTROL_1		0x69
#define NAU8825_REG_ANALOG_CONTROL_2		0x6a
#define NAU8825_REG_ANALOG_ADC_1		0x71
#define NAU8825_REG_ANALOG_ADC_2		0x72
#define NAU8825_REG_RDAC		0x73
#define NAU8825_REG_MIC_BIAS		0x74
#define NAU8825_REG_BOOST		0x76
#define NAU8825_REG_FEPGA		0x77
#define NAU8825_REG_POWER_UP_CONTROL		0x7f
#define NAU8825_REG_CHARGE_PUMP		0x80
#define NAU8825_REG_CHARGE_PUMP_INPUT_READ		0x81
#define NAU8825_REG_GENERAL_STATUS		0x82
#define NAU8825_REG_MAX		NAU8825_REG_GENERAL_STATUS
/* 16-bit control register address, and 16-bits control register data */
#define NAU8825_REG_ADDR_LEN		16
#define NAU8825_REG_DATA_LEN		16

/* ENA_CTRL (0x1) */
#define NAU8825_ENABLE_DACR_SFT	10
#define NAU8825_ENABLE_DACR	(1 << NAU8825_ENABLE_DACR_SFT)
#define NAU8825_ENABLE_DACL_SFT	9
#define NAU8825_ENABLE_DACL		(1 << NAU8825_ENABLE_DACL_SFT)
#define NAU8825_ENABLE_ADC_SFT	8
#define NAU8825_ENABLE_ADC		(1 << NAU8825_ENABLE_ADC_SFT)
#define NAU8825_ENABLE_ADC_CLK_SFT	7
#define NAU8825_ENABLE_ADC_CLK	(1 << NAU8825_ENABLE_ADC_CLK_SFT)
#define NAU8825_ENABLE_DAC_CLK_SFT	6
#define NAU8825_ENABLE_DAC_CLK	(1 << NAU8825_ENABLE_DAC_CLK_SFT)
#define NAU8825_ENABLE_SAR_SFT	1

/* CLK_DIVIDER (0x3) */
#define NAU8825_CLK_SRC_SFT			15
#define NAU8825_CLK_SRC_MASK			(1 << NAU8825_CLK_SRC_SFT)
#define NAU8825_CLK_SRC_VCO			(1 << NAU8825_CLK_SRC_SFT)
#define NAU8825_CLK_SRC_MCLK			(0 << NAU8825_CLK_SRC_SFT)
#define NAU8825_CLK_ADC_SRC_SFT		6
#define NAU8825_CLK_ADC_SRC_MASK		(0x3 << NAU8825_CLK_ADC_SRC_SFT)
#define NAU8825_CLK_DAC_SRC_SFT		4
#define NAU8825_CLK_DAC_SRC_MASK		(0x3 << NAU8825_CLK_DAC_SRC_SFT)
#define NAU8825_CLK_MCLK_SRC_MASK		(0xf << 0)

/* FLL1 (0x04) */
#define NAU8825_ICTRL_LATCH_SFT	10
#define NAU8825_ICTRL_LATCH_MASK	(0x7 << NAU8825_ICTRL_LATCH_SFT)
#define NAU8825_FLL_RATIO_MASK			(0x7f << 0)

/* FLL3 (0x06) */
#define NAU8825_GAIN_ERR_SFT			12
#define NAU8825_GAIN_ERR_MASK			(0xf << NAU8825_GAIN_ERR_SFT)
#define NAU8825_FLL_INTEGER_MASK		(0x3ff << 0)
#define NAU8825_FLL_CLK_SRC_SFT		10
#define NAU8825_FLL_CLK_SRC_MASK		(0x3 << NAU8825_FLL_CLK_SRC_SFT)
#define NAU8825_FLL_CLK_SRC_MCLK		(0 << NAU8825_FLL_CLK_SRC_SFT)
#define NAU8825_FLL_CLK_SRC_BLK		(0x2 << NAU8825_FLL_CLK_SRC_SFT)
#define NAU8825_FLL_CLK_SRC_FS			(0x3 << NAU8825_FLL_CLK_SRC_SFT)

/* FLL4 (0x07) */
#define NAU8825_FLL_REF_DIV_SFT	10
#define NAU8825_FLL_REF_DIV_MASK	(0x3 << NAU8825_FLL_REF_DIV_SFT)

/* FLL5 (0x08) */
#define NAU8825_FLL_PDB_DAC_EN		(0x1 << 15)
#define NAU8825_FLL_LOOP_FTR_EN		(0x1 << 14)
#define NAU8825_FLL_CLK_SW_MASK		(0x1 << 13)
#define NAU8825_FLL_CLK_SW_N2			(0x1 << 13)
#define NAU8825_FLL_CLK_SW_REF		(0x0 << 13)
#define NAU8825_FLL_FTR_SW_MASK		(0x1 << 12)
#define NAU8825_FLL_FTR_SW_ACCU		(0x1 << 12)
#define NAU8825_FLL_FTR_SW_FILTER		(0x0 << 12)

/* FLL6 (0x9) */
#define NAU8825_DCO_EN				(0x1 << 15)
#define NAU8825_SDM_EN				(0x1 << 14)
#define NAU8825_CUTOFF500			(0x1 << 13)

/* HSD_CTRL (0xc) */
#define NAU8825_HSD_AUTO_MODE	(1 << 6)
/* 0 - open, 1 - short to GND */
#define NAU8825_SPKR_DWN1R	(1 << 1)
#define NAU8825_SPKR_DWN1L	(1 << 0)

/* JACK_DET_CTRL (0xd) */
#define NAU8825_JACK_DET_RESTART	(1 << 9)
#define NAU8825_JACK_DET_DB_BYPASS	(1 << 8)
#define NAU8825_JACK_INSERT_DEBOUNCE_SFT	5
#define NAU8825_JACK_INSERT_DEBOUNCE_MASK	(0x7 << NAU8825_JACK_INSERT_DEBOUNCE_SFT)
#define NAU8825_JACK_EJECT_DEBOUNCE_SFT		2
#define NAU8825_JACK_EJECT_DEBOUNCE_MASK	(0x7 << NAU8825_JACK_EJECT_DEBOUNCE_SFT)
#define NAU8825_JACK_POLARITY	(1 << 1) /* 0 - active low, 1 - active high */

/* INTERRUPT_MASK (0xf) */
#define NAU8825_IRQ_OUTPUT_EN (1 << 11)
#define NAU8825_IRQ_HEADSET_COMPLETE_EN (1 << 10)
#define NAU8825_IRQ_RMS_EN (1 << 8)
#define NAU8825_IRQ_KEY_RELEASE_EN (1 << 7)
#define NAU8825_IRQ_KEY_SHORT_PRESS_EN (1 << 5)
#define NAU8825_IRQ_EJECT_EN (1 << 2)
#define NAU8825_IRQ_INSERT_EN (1 << 0)

/* IRQ_STATUS (0x10) */
#define NAU8825_HEADSET_COMPLETION_IRQ	(1 << 10)
#define NAU8825_SHORT_CIRCUIT_IRQ	(1 << 9)
#define NAU8825_IMPEDANCE_MEAS_IRQ	(1 << 8)
#define NAU8825_KEY_IRQ_MASK	(0x7 << 5)
#define NAU8825_KEY_RELEASE_IRQ	(1 << 7)
#define NAU8825_KEY_LONG_PRESS_IRQ	(1 << 6)
#define NAU8825_KEY_SHORT_PRESS_IRQ	(1 << 5)
#define NAU8825_MIC_DETECTION_IRQ	(1 << 4)
#define NAU8825_JACK_EJECTION_IRQ_MASK	(3 << 2)
#define NAU8825_JACK_EJECTION_DETECTED	(1 << 2)
#define NAU8825_JACK_INSERTION_IRQ_MASK	(3 << 0)
#define NAU8825_JACK_INSERTION_DETECTED	(1 << 0)

/* INTERRUPT_DIS_CTRL (0x12) */
#define NAU8825_IRQ_HEADSET_COMPLETE_DIS (1 << 10)
#define NAU8825_IRQ_KEY_RELEASE_DIS (1 << 7)
#define NAU8825_IRQ_KEY_SHORT_PRESS_DIS (1 << 5)
#define NAU8825_IRQ_EJECT_DIS (1 << 2)
#define NAU8825_IRQ_INSERT_DIS (1 << 0)

/* SAR_CTRL (0x13) */
#define NAU8825_SAR_ADC_EN_SFT	12
#define NAU8825_SAR_ADC_EN	(1 << NAU8825_SAR_ADC_EN_SFT)
#define NAU8825_SAR_INPUT_MASK	(1 << 11)
#define NAU8825_SAR_INPUT_JKSLV	(1 << 11)
#define NAU8825_SAR_INPUT_JKR2	(0 << 11)
#define NAU8825_SAR_TRACKING_GAIN_SFT	8
#define NAU8825_SAR_TRACKING_GAIN_MASK	(0x7 << NAU8825_SAR_TRACKING_GAIN_SFT)
#define NAU8825_SAR_COMPARE_TIME_SFT	2
#define NAU8825_SAR_COMPARE_TIME_MASK	(3 << 2)
#define NAU8825_SAR_SAMPLING_TIME_SFT	0
#define NAU8825_SAR_SAMPLING_TIME_MASK	(3 << 0)

/* KEYDET_CTRL (0x14) */
#define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT	12
#define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK	(0x3 << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT)
#define NAU8825_KEYDET_LEVELS_NR_SFT	8
#define NAU8825_KEYDET_LEVELS_NR_MASK	(0x7 << 8)
#define NAU8825_KEYDET_HYSTERESIS_SFT	0
#define NAU8825_KEYDET_HYSTERESIS_MASK	0xf

/* GPIO12_CTRL (0x1a) */
#define NAU8825_JKDET_PULL_UP	(1 << 11) /* 0 - pull down, 1 - pull up */
#define NAU8825_JKDET_PULL_EN	(1 << 9) /* 0 - enable pull, 1 - disable */
#define NAU8825_JKDET_OUTPUT_EN	(1 << 8) /* 0 - enable input, 1 - enable output */

/* I2S_PCM_CTRL1 (0x1c) */
#define NAU8825_I2S_BP_SFT	7
#define NAU8825_I2S_BP_MASK	(1 << NAU8825_I2S_BP_SFT)
#define NAU8825_I2S_BP_INV	(1 << NAU8825_I2S_BP_SFT)
#define NAU8825_I2S_PCMB_SFT	6
#define NAU8825_I2S_PCMB_MASK	(1 << NAU8825_I2S_PCMB_SFT)
#define NAU8825_I2S_PCMB_EN	(1 << NAU8825_I2S_PCMB_SFT)
#define NAU8825_I2S_DL_SFT	2
#define NAU8825_I2S_DL_MASK	(0x3 << NAU8825_I2S_DL_SFT)
#define NAU8825_I2S_DL_16	(0 << NAU8825_I2S_DL_SFT)
#define NAU8825_I2S_DL_20	(1 << NAU8825_I2S_DL_SFT)
#define NAU8825_I2S_DL_24	(2 << NAU8825_I2S_DL_SFT)
#define NAU8825_I2S_DL_32	(3 << NAU8825_I2S_DL_SFT)
#define NAU8825_I2S_DF_SFT	0
#define NAU8825_I2S_DF_MASK	(0x3 << NAU8825_I2S_DF_SFT)
#define NAU8825_I2S_DF_RIGTH	(0 << NAU8825_I2S_DF_SFT)
#define NAU8825_I2S_DF_LEFT	(1 << NAU8825_I2S_DF_SFT)
#define NAU8825_I2S_DF_I2S	(2 << NAU8825_I2S_DF_SFT)
#define NAU8825_I2S_DF_PCM_AB	(3 << NAU8825_I2S_DF_SFT)

/* I2S_PCM_CTRL2 (0x1d) */
#define NAU8825_I2S_TRISTATE	(1 << 15) /* 0 - normal mode, 1 - Hi-Z output */
#define NAU8825_I2S_LRC_DIV_SFT	12
#define NAU8825_I2S_LRC_DIV_MASK	(0x3 << NAU8825_I2S_LRC_DIV_SFT)
#define NAU8825_I2S_MS_SFT	3
#define NAU8825_I2S_MS_MASK	(1 << NAU8825_I2S_MS_SFT)
#define NAU8825_I2S_MS_MASTER	(1 << NAU8825_I2S_MS_SFT)
#define NAU8825_I2S_MS_SLAVE	(0 << NAU8825_I2S_MS_SFT)
#define NAU8825_I2S_BLK_DIV_MASK	0x7

/* LEFT_TIME_SLOT (0x1e) */
#define NAU8825_FS_ERR_CMP_SEL_SFT	14
#define NAU8825_FS_ERR_CMP_SEL_MASK	(0x3 << NAU8825_FS_ERR_CMP_SEL_SFT)
#define NAU8825_DIS_FS_SHORT_DET	(1 << 13)

/* BIQ_CTRL (0x20) */
#define NAU8825_BIQ_WRT_SFT   4
#define NAU8825_BIQ_WRT_EN     (1 << NAU8825_BIQ_WRT_SFT)
#define NAU8825_BIQ_PATH_SFT   0
#define NAU8825_BIQ_PATH_MASK  (1 << NAU8825_BIQ_PATH_SFT)
#define NAU8825_BIQ_PATH_ADC   (0 << NAU8825_BIQ_PATH_SFT)
#define NAU8825_BIQ_PATH_DAC   (1 << NAU8825_BIQ_PATH_SFT)

/* ADC_RATE (0x2b) */
#define NAU8825_ADC_SINC4_SFT		4
#define NAU8825_ADC_SINC4_EN		(1 << NAU8825_ADC_SINC4_SFT)
#define NAU8825_ADC_SYNC_DOWN_SFT	0
#define NAU8825_ADC_SYNC_DOWN_MASK	0x3
#define NAU8825_ADC_SYNC_DOWN_32	0
#define NAU8825_ADC_SYNC_DOWN_64	1
#define NAU8825_ADC_SYNC_DOWN_128	2
#define NAU8825_ADC_SYNC_DOWN_256	3

/* DAC_CTRL1 (0x2c) */
#define NAU8825_DAC_CLIP_OFF	(1 << 7)
#define NAU8825_DAC_OVERSAMPLE_SFT	0
#define NAU8825_DAC_OVERSAMPLE_MASK	0x7
#define NAU8825_DAC_OVERSAMPLE_64	0
#define NAU8825_DAC_OVERSAMPLE_256	1
#define NAU8825_DAC_OVERSAMPLE_128	2
#define NAU8825_DAC_OVERSAMPLE_32	4

/* ADC_DGAIN_CTRL (0x30) */
#define NAU8825_ADC_DIG_VOL_MASK	0xff

/* MUTE_CTRL (0x31) */
#define NAU8825_DAC_ZERO_CROSSING_EN	(1 << 9)
#define NAU8825_DAC_SOFT_MUTE	(1 << 9)

/* HSVOL_CTRL (0x32) */
#define NAU8825_HP_MUTE	(1 << 15)
#define NAU8825_HP_MUTE_AUTO	(1 << 14)
#define NAU8825_HPL_MUTE	(1 << 13)
#define NAU8825_HPR_MUTE	(1 << 12)
#define NAU8825_HPL_VOL_SFT	6
#define NAU8825_HPL_VOL_MASK	(0x3f << NAU8825_HPL_VOL_SFT)
#define NAU8825_HPR_VOL_SFT	0
#define NAU8825_HPR_VOL_MASK	(0x3f << NAU8825_HPR_VOL_SFT)
#define NAU8825_HP_VOL_MIN	0x36

/* DACL_CTRL (0x33) */
#define NAU8825_DACL_CH_SEL_SFT	9
#define NAU8825_DACL_CH_SEL_MASK (0x1 << NAU8825_DACL_CH_SEL_SFT)
#define NAU8825_DACL_CH_SEL_L    (0x0 << NAU8825_DACL_CH_SEL_SFT)
#define NAU8825_DACL_CH_SEL_R    (0x1 << NAU8825_DACL_CH_SEL_SFT)
#define NAU8825_DACL_CH_VOL_MASK	0xff

/* DACR_CTRL (0x34) */
#define NAU8825_DACR_CH_SEL_SFT	9
#define NAU8825_DACR_CH_SEL_MASK (0x1 << NAU8825_DACR_CH_SEL_SFT)
#define NAU8825_DACR_CH_SEL_L    (0x0 << NAU8825_DACR_CH_SEL_SFT)
#define NAU8825_DACR_CH_SEL_R    (0x1 << NAU8825_DACR_CH_SEL_SFT)
#define NAU8825_DACR_CH_VOL_MASK	0xff

/* IMM_MODE_CTRL (0x4C) */
#define NAU8825_IMM_THD_SFT		8
#define NAU8825_IMM_THD_MASK		(0x3f << NAU8825_IMM_THD_SFT)
#define NAU8825_IMM_GEN_VOL_SFT	6
#define NAU8825_IMM_GEN_VOL_MASK	(0x3 << NAU8825_IMM_GEN_VOL_SFT)
#define NAU8825_IMM_GEN_VOL_1_2nd	(0x0 << NAU8825_IMM_GEN_VOL_SFT)
#define NAU8825_IMM_GEN_VOL_1_4th	(0x1 << NAU8825_IMM_GEN_VOL_SFT)
#define NAU8825_IMM_GEN_VOL_1_8th	(0x2 << NAU8825_IMM_GEN_VOL_SFT)
#define NAU8825_IMM_GEN_VOL_1_16th	(0x3 << NAU8825_IMM_GEN_VOL_SFT)

#define NAU8825_IMM_CYC_SFT		4
#define NAU8825_IMM_CYC_MASK		(0x3 << NAU8825_IMM_CYC_SFT)
#define NAU8825_IMM_CYC_1024		(0x0 << NAU8825_IMM_CYC_SFT)
#define NAU8825_IMM_CYC_2048		(0x1 << NAU8825_IMM_CYC_SFT)
#define NAU8825_IMM_CYC_4096		(0x2 << NAU8825_IMM_CYC_SFT)
#define NAU8825_IMM_CYC_8192		(0x3 << NAU8825_IMM_CYC_SFT)
#define NAU8825_IMM_EN			(1 << 3)
#define NAU8825_IMM_DAC_SRC_MASK	0x7
#define NAU8825_IMM_DAC_SRC_BIQ	0x0
#define NAU8825_IMM_DAC_SRC_DRC	0x1
#define NAU8825_IMM_DAC_SRC_MIX	0x2
#define NAU8825_IMM_DAC_SRC_SIN	0x3

/* CLASSG_CTRL (0x50) */
#define NAU8825_CLASSG_TIMER_SFT	8
#define NAU8825_CLASSG_TIMER_MASK	(0x3f << NAU8825_CLASSG_TIMER_SFT)
#define NAU8825_CLASSG_TIMER_1ms	(0x1 << NAU8825_CLASSG_TIMER_SFT)
#define NAU8825_CLASSG_TIMER_2ms	(0x2 << NAU8825_CLASSG_TIMER_SFT)
#define NAU8825_CLASSG_TIMER_8ms	(0x4 << NAU8825_CLASSG_TIMER_SFT)
#define NAU8825_CLASSG_TIMER_16ms	(0x8 << NAU8825_CLASSG_TIMER_SFT)
#define NAU8825_CLASSG_TIMER_32ms	(0x10 << NAU8825_CLASSG_TIMER_SFT)
#define NAU8825_CLASSG_TIMER_64ms	(0x20 << NAU8825_CLASSG_TIMER_SFT)
#define NAU8825_CLASSG_LDAC_EN		(0x1 << 2)
#define NAU8825_CLASSG_RDAC_EN		(0x1 << 1)
#define NAU8825_CLASSG_EN		(1 << 0)

/* I2C_DEVICE_ID (0x58) */
#define NAU8825_GPIO2JD1	(1 << 7)
#define NAU8825_SOFTWARE_ID_MASK	0x3
#define NAU8825_SOFTWARE_ID_NAU8825	0x0

/* BIAS_ADJ (0x66) */
#define NAU8825_BIAS_HPR_IMP		(1 << 15)
#define NAU8825_BIAS_HPL_IMP		(1 << 14)
#define NAU8825_BIAS_TESTDAC_SFT	8
#define NAU8825_BIAS_TESTDAC_EN	(0x3 << NAU8825_BIAS_TESTDAC_SFT)
#define NAU8825_BIAS_TESTDACR_EN	(0x2 << NAU8825_BIAS_TESTDAC_SFT)
#define NAU8825_BIAS_TESTDACL_EN	(0x1 << NAU8825_BIAS_TESTDAC_SFT)
#define NAU8825_BIAS_VMID	(1 << 6)
#define NAU8825_BIAS_VMID_SEL_SFT	4
#define NAU8825_BIAS_VMID_SEL_MASK	(3 << NAU8825_BIAS_VMID_SEL_SFT)

/* ANALOG_CONTROL_2 (0x6a) */
#define NAU8825_HP_NON_CLASSG_CURRENT_2xADJ (1 << 12)
#define NAU8825_DAC_CAPACITOR_MSB (1 << 1)
#define NAU8825_DAC_CAPACITOR_LSB (1 << 0)

/* ANALOG_ADC_2 (0x72) */
#define NAU8825_ADC_VREFSEL_MASK	(0x3 << 8)
#define NAU8825_ADC_VREFSEL_ANALOG	(0 << 8)
#define NAU8825_ADC_VREFSEL_VMID	(1 << 8)
#define NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB	(2 << 8)
#define NAU8825_ADC_VREFSEL_VMID_PLUS_1DB	(3 << 8)
#define NAU8825_POWERUP_ADCL	(1 << 6)

/* RDAC (0x73) */
#define NAU8825_RDAC_FS_BCLK_ENB	(1 << 15)
#define NAU8825_RDAC_EN_SFT		12
#define NAU8825_RDAC_EN		(0x3 << NAU8825_RDAC_EN_SFT)
#define NAU8825_RDAC_CLK_EN_SFT	8
#define NAU8825_RDAC_CLK_EN		(0x3 << NAU8825_RDAC_CLK_EN_SFT)
#define NAU8825_RDAC_CLK_DELAY_SFT	4
#define NAU8825_RDAC_CLK_DELAY_MASK	(0x7 << NAU8825_RDAC_CLK_DELAY_SFT)
#define NAU8825_RDAC_VREF_SFT	2
#define NAU8825_RDAC_VREF_MASK	(0x3 << NAU8825_RDAC_VREF_SFT)

/* MIC_BIAS (0x74) */
#define NAU8825_MICBIAS_JKSLV	(1 << 14)
#define NAU8825_MICBIAS_JKR2	(1 << 12)
#define NAU8825_MICBIAS_POWERUP_SFT	8
#define NAU8825_MICBIAS_VOLTAGE_SFT	0
#define NAU8825_MICBIAS_VOLTAGE_MASK	0x7

/* BOOST (0x76) */
#define NAU8825_PRECHARGE_DIS	(1 << 13)
#define NAU8825_GLOBAL_BIAS_EN	(1 << 12)
#define NAU8825_HP_BOOST_DIS		(1 << 9)
#define NAU8825_HP_BOOST_G_DIS	(1 << 8)
#define NAU8825_SHORT_SHUTDOWN_EN	(1 << 6)

/* POWER_UP_CONTROL (0x7f) */
#define NAU8825_POWERUP_INTEGR_R	(1 << 5)
#define NAU8825_POWERUP_INTEGR_L	(1 << 4)
#define NAU8825_POWERUP_DRV_IN_R	(1 << 3)
#define NAU8825_POWERUP_DRV_IN_L	(1 << 2)
#define NAU8825_POWERUP_HP_DRV_R	(1 << 1)
#define NAU8825_POWERUP_HP_DRV_L	(1 << 0)

/* CHARGE_PUMP (0x80) */
#define NAU8825_JAMNODCLOW	(1 << 10)
#define NAU8825_POWER_DOWN_DACR	(1 << 9)
#define NAU8825_POWER_DOWN_DACL	(1 << 8)
#define NAU8825_CHANRGE_PUMP_EN	(1 << 5)


/* System Clock Source */
enum {
	NAU8825_CLK_DIS = 0,
	NAU8825_CLK_MCLK,
	NAU8825_CLK_INTERNAL,
	NAU8825_CLK_FLL_MCLK,
	NAU8825_CLK_FLL_BLK,
	NAU8825_CLK_FLL_FS,
};

/* Cross talk detection state */
enum {
	NAU8825_XTALK_PREPARE = 0,
	NAU8825_XTALK_HPR_R2L,
	NAU8825_XTALK_HPL_R2L,
	NAU8825_XTALK_IMM,
	NAU8825_XTALK_DONE,
};

struct nau8825 {
	struct device *dev;
	struct regmap *regmap;
	struct snd_soc_dapm_context *dapm;
	struct snd_soc_jack *jack;
	struct clk *mclk;
	struct work_struct xtalk_work;
	struct semaphore xtalk_sem;
	int irq;
	int mclk_freq; /* 0 - mclk is disabled */
	int button_pressed;
	int micbias_voltage;
	int vref_impedance;
	bool jkdet_enable;
	bool jkdet_pull_enable;
	bool jkdet_pull_up;
	int jkdet_polarity;
	int sar_threshold_num;
	int sar_threshold[8];
	int sar_hysteresis;
	int sar_voltage;
	int sar_compare_time;
	int sar_sampling_time;
	int key_debounce;
	int jack_insert_debounce;
	int jack_eject_debounce;
	int high_imped;
	int xtalk_state;
	int xtalk_event;
	int xtalk_event_mask;
	bool xtalk_protect;
	int imp_rms[NAU8825_XTALK_IMM];
	int xtalk_enable;
	bool xtalk_baktab_initialized; /* True if initialized. */
};

int nau8825_enable_jack_detect(struct snd_soc_component *component,
				struct snd_soc_jack *jack);


#endif  /* __NAU8825_H__ */
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
34ca27f3 AP	2	/*
	3	* NAU8825 ALSA SoC audio driver
	4	*
	5	* Copyright 2015 Google Inc.
	6	* Author: Anatol Pomozov <anatol.pomozov@chrominium.org>
34ca27f3 AP	7	*/
	8
	9	#ifndef __NAU8825_H__
	10	#define __NAU8825_H__
	11
	12	#define NAU8825_REG_RESET 0x00
	13	#define NAU8825_REG_ENA_CTRL 0x01
45d5eb3a	14	#define NAU8825_REG_IIC_ADDR_SET 0x02
34ca27f3 AP	15	#define NAU8825_REG_CLK_DIVIDER 0x03
	16	#define NAU8825_REG_FLL1 0x04
	17	#define NAU8825_REG_FLL2 0x05
	18	#define NAU8825_REG_FLL3 0x06
	19	#define NAU8825_REG_FLL4 0x07
	20	#define NAU8825_REG_FLL5 0x08
	21	#define NAU8825_REG_FLL6 0x09
	22	#define NAU8825_REG_FLL_VCO_RSV 0x0a
	23	#define NAU8825_REG_HSD_CTRL 0x0c
	24	#define NAU8825_REG_JACK_DET_CTRL 0x0d
	25	#define NAU8825_REG_INTERRUPT_MASK 0x0f
	26	#define NAU8825_REG_IRQ_STATUS 0x10
	27	#define NAU8825_REG_INT_CLR_KEY_STATUS 0x11
	28	#define NAU8825_REG_INTERRUPT_DIS_CTRL 0x12
	29	#define NAU8825_REG_SAR_CTRL 0x13
	30	#define NAU8825_REG_KEYDET_CTRL 0x14
	31	#define NAU8825_REG_VDET_THRESHOLD_1 0x15
	32	#define NAU8825_REG_VDET_THRESHOLD_2 0x16
	33	#define NAU8825_REG_VDET_THRESHOLD_3 0x17
	34	#define NAU8825_REG_VDET_THRESHOLD_4 0x18
	35	#define NAU8825_REG_GPIO34_CTRL 0x19
	36	#define NAU8825_REG_GPIO12_CTRL 0x1a
	37	#define NAU8825_REG_TDM_CTRL 0x1b
	38	#define NAU8825_REG_I2S_PCM_CTRL1 0x1c
	39	#define NAU8825_REG_I2S_PCM_CTRL2 0x1d
	40	#define NAU8825_REG_LEFT_TIME_SLOT 0x1e
	41	#define NAU8825_REG_RIGHT_TIME_SLOT 0x1f
	42	#define NAU8825_REG_BIQ_CTRL 0x20
	43	#define NAU8825_REG_BIQ_COF1 0x21
	44	#define NAU8825_REG_BIQ_COF2 0x22
	45	#define NAU8825_REG_BIQ_COF3 0x23
	46	#define NAU8825_REG_BIQ_COF4 0x24
	47	#define NAU8825_REG_BIQ_COF5 0x25
	48	#define NAU8825_REG_BIQ_COF6 0x26
	49	#define NAU8825_REG_BIQ_COF7 0x27
	50	#define NAU8825_REG_BIQ_COF8 0x28
	51	#define NAU8825_REG_BIQ_COF9 0x29
	52	#define NAU8825_REG_BIQ_COF10 0x2a
	53	#define NAU8825_REG_ADC_RATE 0x2b
	54	#define NAU8825_REG_DAC_CTRL1 0x2c
	55	#define NAU8825_REG_DAC_CTRL2 0x2d
	56	#define NAU8825_REG_DAC_DGAIN_CTRL 0x2f
	57	#define NAU8825_REG_ADC_DGAIN_CTRL 0x30
	58	#define NAU8825_REG_MUTE_CTRL 0x31
	59	#define NAU8825_REG_HSVOL_CTRL 0x32
	60	#define NAU8825_REG_DACL_CTRL 0x33
	61	#define NAU8825_REG_DACR_CTRL 0x34
	62	#define NAU8825_REG_ADC_DRC_KNEE_IP12 0x38
	63	#define NAU8825_REG_ADC_DRC_KNEE_IP34 0x39
	64	#define NAU8825_REG_ADC_DRC_SLOPES 0x3a
	65	#define NAU8825_REG_ADC_DRC_ATKDCY 0x3b
	66	#define NAU8825_REG_DAC_DRC_KNEE_IP12 0x45
	67	#define NAU8825_REG_DAC_DRC_KNEE_IP34 0x46
	68	#define NAU8825_REG_DAC_DRC_SLOPES 0x47
	69	#define NAU8825_REG_DAC_DRC_ATKDCY 0x48
	70	#define NAU8825_REG_IMM_MODE_CTRL 0x4c
	71	#define NAU8825_REG_IMM_RMS_L 0x4d
	72	#define NAU8825_REG_IMM_RMS_R 0x4e
	73	#define NAU8825_REG_CLASSG_CTRL 0x50
	74	#define NAU8825_REG_OPT_EFUSE_CTRL 0x51
	75	#define NAU8825_REG_MISC_CTRL 0x55
	76	#define NAU8825_REG_I2C_DEVICE_ID 0x58
	77	#define NAU8825_REG_SARDOUT_RAM_STATUS 0x59
	78	#define NAU8825_REG_BIAS_ADJ 0x66
79	#define NAU8825_REG_TRIM_SETTINGS 0x68
80	#define NAU8825_REG_ANALOG_CONTROL_1 0x69
81	#define NAU8825_REG_ANALOG_CONTROL_2 0x6a
82	#define NAU8825_REG_ANALOG_ADC_1 0x71
83	#define NAU8825_REG_ANALOG_ADC_2 0x72
84	#define NAU8825_REG_RDAC 0x73
85	#define NAU8825_REG_MIC_BIAS 0x74
86	#define NAU8825_REG_BOOST 0x76
87	#define NAU8825_REG_FEPGA 0x77
88	#define NAU8825_REG_POWER_UP_CONTROL 0x7f
89	#define NAU8825_REG_CHARGE_PUMP 0x80
90	#define NAU8825_REG_CHARGE_PUMP_INPUT_READ 0x81
91	#define NAU8825_REG_GENERAL_STATUS 0x82
92	#define NAU8825_REG_MAX NAU8825_REG_GENERAL_STATUS
2ec30f60 JH	93	/* 16-bit control register address, and 16-bits control register data */
	94	#define NAU8825_REG_ADDR_LEN 16
	95	#define NAU8825_REG_DATA_LEN 16
34ca27f3 AP	96
	97	/* ENA_CTRL (0x1) */
	98	#define NAU8825_ENABLE_DACR_SFT 10
	99	#define NAU8825_ENABLE_DACR (1 << NAU8825_ENABLE_DACR_SFT)
	100	#define NAU8825_ENABLE_DACL_SFT 9
b50455fa	101	#define NAU8825_ENABLE_DACL (1 << NAU8825_ENABLE_DACL_SFT)
34ca27f3	102	#define NAU8825_ENABLE_ADC_SFT 8
eeef16ac	103	#define NAU8825_ENABLE_ADC (1 << NAU8825_ENABLE_ADC_SFT)
b50455fa JH	104	#define NAU8825_ENABLE_ADC_CLK_SFT 7
	105	#define NAU8825_ENABLE_ADC_CLK (1 << NAU8825_ENABLE_ADC_CLK_SFT)
	106	#define NAU8825_ENABLE_DAC_CLK_SFT 6
	107	#define NAU8825_ENABLE_DAC_CLK (1 << NAU8825_ENABLE_DAC_CLK_SFT)
34ca27f3 AP	108	#define NAU8825_ENABLE_SAR_SFT 1
	109
	110	/* CLK_DIVIDER (0x3) */
c86ba612 BZ	111	#define NAU8825_CLK_SRC_SFT 15
	112	#define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT)
	113	#define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT)
	114	#define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT)
d6d19745 JH	115	#define NAU8825_CLK_ADC_SRC_SFT 6
	116	#define NAU8825_CLK_ADC_SRC_MASK (0x3 << NAU8825_CLK_ADC_SRC_SFT)
	117	#define NAU8825_CLK_DAC_SRC_SFT 4
	118	#define NAU8825_CLK_DAC_SRC_MASK (0x3 << NAU8825_CLK_DAC_SRC_SFT)
c86ba612 BZ	119	#define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0)
	120
	121	/* FLL1 (0x04) */
aee02c75 JH	122	#define NAU8825_ICTRL_LATCH_SFT 10
aee02c75 JH	123	#define NAU8825_ICTRL_LATCH_MASK (0x7 << NAU8825_ICTRL_LATCH_SFT)
c86ba612 BZ	124	#define NAU8825_FLL_RATIO_MASK (0x7f << 0)
	125
	126	/* FLL3 (0x06) */
aee02c75 JH	127	#define NAU8825_GAIN_ERR_SFT 12
aee02c75 JH	128	#define NAU8825_GAIN_ERR_MASK (0xf << NAU8825_GAIN_ERR_SFT)
c86ba612	129	#define NAU8825_FLL_INTEGER_MASK (0x3ff << 0)
70543c30 JH	130	#define NAU8825_FLL_CLK_SRC_SFT 10
	131	#define NAU8825_FLL_CLK_SRC_MASK (0x3 << NAU8825_FLL_CLK_SRC_SFT)
	132	#define NAU8825_FLL_CLK_SRC_MCLK (0 << NAU8825_FLL_CLK_SRC_SFT)
	133	#define NAU8825_FLL_CLK_SRC_BLK (0x2 << NAU8825_FLL_CLK_SRC_SFT)
	134	#define NAU8825_FLL_CLK_SRC_FS (0x3 << NAU8825_FLL_CLK_SRC_SFT)
c86ba612 BZ	135
c86ba612 BZ	136	/* FLL4 (0x07) */
a1792cda JH	137	#define NAU8825_FLL_REF_DIV_SFT 10
a1792cda JH	138	#define NAU8825_FLL_REF_DIV_MASK (0x3 << NAU8825_FLL_REF_DIV_SFT)
c86ba612 BZ	139
c86ba612 BZ	140	/* FLL5 (0x08) */
407c71b6 JH	141	#define NAU8825_FLL_PDB_DAC_EN (0x1 << 15)
	142	#define NAU8825_FLL_LOOP_FTR_EN (0x1 << 14)
	143	#define NAU8825_FLL_CLK_SW_MASK (0x1 << 13)
	144	#define NAU8825_FLL_CLK_SW_N2 (0x1 << 13)
	145	#define NAU8825_FLL_CLK_SW_REF (0x0 << 13)
	146	#define NAU8825_FLL_FTR_SW_MASK (0x1 << 12)
	147	#define NAU8825_FLL_FTR_SW_ACCU (0x1 << 12)
	148	#define NAU8825_FLL_FTR_SW_FILTER (0x0 << 12)
34ca27f3 AP	149
34ca27f3 AP	150	/* FLL6 (0x9) */
c86ba612	151	#define NAU8825_DCO_EN (0x1 << 15)
c86ba612	152	#define NAU8825_SDM_EN (0x1 << 14)
aee02c75	153	#define NAU8825_CUTOFF500 (0x1 << 13)
34ca27f3 AP	154
	155	/* HSD_CTRL (0xc) */
	156	#define NAU8825_HSD_AUTO_MODE (1 << 6)
45d5eb3a	157	/* 0 - open, 1 - short to GND */
34ca27f3 AP	158	#define NAU8825_SPKR_DWN1R (1 << 1)
	159	#define NAU8825_SPKR_DWN1L (1 << 0)
	160
	161	/* JACK_DET_CTRL (0xd) */
	162	#define NAU8825_JACK_DET_RESTART (1 << 9)
2ec30f60	163	#define NAU8825_JACK_DET_DB_BYPASS (1 << 8)
34ca27f3 AP	164	#define NAU8825_JACK_INSERT_DEBOUNCE_SFT 5
	165	#define NAU8825_JACK_INSERT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_INSERT_DEBOUNCE_SFT)
	166	#define NAU8825_JACK_EJECT_DEBOUNCE_SFT 2
	167	#define NAU8825_JACK_EJECT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_EJECT_DEBOUNCE_SFT)
	168	#define NAU8825_JACK_POLARITY (1 << 1) /* 0 - active low, 1 - active high */
	169
	170	/* INTERRUPT_MASK (0xf) */
	171	#define NAU8825_IRQ_OUTPUT_EN (1 << 11)
	172	#define NAU8825_IRQ_HEADSET_COMPLETE_EN (1 << 10)
b50455fa	173	#define NAU8825_IRQ_RMS_EN (1 << 8)
34ca27f3 AP	174	#define NAU8825_IRQ_KEY_RELEASE_EN (1 << 7)
	175	#define NAU8825_IRQ_KEY_SHORT_PRESS_EN (1 << 5)
	176	#define NAU8825_IRQ_EJECT_EN (1 << 2)
2ec30f60	177	#define NAU8825_IRQ_INSERT_EN (1 << 0)
34ca27f3 AP	178
	179	/* IRQ_STATUS (0x10) */
	180	#define NAU8825_HEADSET_COMPLETION_IRQ (1 << 10)
	181	#define NAU8825_SHORT_CIRCUIT_IRQ (1 << 9)
	182	#define NAU8825_IMPEDANCE_MEAS_IRQ (1 << 8)
	183	#define NAU8825_KEY_IRQ_MASK (0x7 << 5)
	184	#define NAU8825_KEY_RELEASE_IRQ (1 << 7)
	185	#define NAU8825_KEY_LONG_PRESS_IRQ (1 << 6)
	186	#define NAU8825_KEY_SHORT_PRESS_IRQ (1 << 5)
	187	#define NAU8825_MIC_DETECTION_IRQ (1 << 4)
	188	#define NAU8825_JACK_EJECTION_IRQ_MASK (3 << 2)
	189	#define NAU8825_JACK_EJECTION_DETECTED (1 << 2)
	190	#define NAU8825_JACK_INSERTION_IRQ_MASK (3 << 0)
	191	#define NAU8825_JACK_INSERTION_DETECTED (1 << 0)
	192
	193	/* INTERRUPT_DIS_CTRL (0x12) */
	194	#define NAU8825_IRQ_HEADSET_COMPLETE_DIS (1 << 10)
	195	#define NAU8825_IRQ_KEY_RELEASE_DIS (1 << 7)
	196	#define NAU8825_IRQ_KEY_SHORT_PRESS_DIS (1 << 5)
	197	#define NAU8825_IRQ_EJECT_DIS (1 << 2)
2ec30f60	198	#define NAU8825_IRQ_INSERT_DIS (1 << 0)
34ca27f3 AP	199
	200	/* SAR_CTRL (0x13) */
	201	#define NAU8825_SAR_ADC_EN_SFT 12
	202	#define NAU8825_SAR_ADC_EN (1 << NAU8825_SAR_ADC_EN_SFT)
	203	#define NAU8825_SAR_INPUT_MASK (1 << 11)
	204	#define NAU8825_SAR_INPUT_JKSLV (1 << 11)
	205	#define NAU8825_SAR_INPUT_JKR2 (0 << 11)
	206	#define NAU8825_SAR_TRACKING_GAIN_SFT 8
	207	#define NAU8825_SAR_TRACKING_GAIN_MASK (0x7 << NAU8825_SAR_TRACKING_GAIN_SFT)
	208	#define NAU8825_SAR_COMPARE_TIME_SFT 2
	209	#define NAU8825_SAR_COMPARE_TIME_MASK (3 << 2)
	210	#define NAU8825_SAR_SAMPLING_TIME_SFT 0
	211	#define NAU8825_SAR_SAMPLING_TIME_MASK (3 << 0)
	212
	213	/* KEYDET_CTRL (0x14) */
	214	#define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT 12
	215	#define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK (0x3 << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT)
	216	#define NAU8825_KEYDET_LEVELS_NR_SFT 8
	217	#define NAU8825_KEYDET_LEVELS_NR_MASK (0x7 << 8)
	218	#define NAU8825_KEYDET_HYSTERESIS_SFT 0
	219	#define NAU8825_KEYDET_HYSTERESIS_MASK 0xf
	220
	221	/* GPIO12_CTRL (0x1a) */
	222	#define NAU8825_JKDET_PULL_UP (1 << 11) /* 0 - pull down, 1 - pull up */
	223	#define NAU8825_JKDET_PULL_EN (1 << 9) /* 0 - enable pull, 1 - disable */
	224	#define NAU8825_JKDET_OUTPUT_EN (1 << 8) /* 0 - enable input, 1 - enable output */
	225
	226	/* I2S_PCM_CTRL1 (0x1c) */
	227	#define NAU8825_I2S_BP_SFT 7
	228	#define NAU8825_I2S_BP_MASK (1 << NAU8825_I2S_BP_SFT)
	229	#define NAU8825_I2S_BP_INV (1 << NAU8825_I2S_BP_SFT)
	230	#define NAU8825_I2S_PCMB_SFT 6
	231	#define NAU8825_I2S_PCMB_MASK (1 << NAU8825_I2S_PCMB_SFT)
	232	#define NAU8825_I2S_PCMB_EN (1 << NAU8825_I2S_PCMB_SFT)
	233	#define NAU8825_I2S_DL_SFT 2
	234	#define NAU8825_I2S_DL_MASK (0x3 << NAU8825_I2S_DL_SFT)
	235	#define NAU8825_I2S_DL_16 (0 << NAU8825_I2S_DL_SFT)
	236	#define NAU8825_I2S_DL_20 (1 << NAU8825_I2S_DL_SFT)
	237	#define NAU8825_I2S_DL_24 (2 << NAU8825_I2S_DL_SFT)
	238	#define NAU8825_I2S_DL_32 (3 << NAU8825_I2S_DL_SFT)
	239	#define NAU8825_I2S_DF_SFT 0
	240	#define NAU8825_I2S_DF_MASK (0x3 << NAU8825_I2S_DF_SFT)
	241	#define NAU8825_I2S_DF_RIGTH (0 << NAU8825_I2S_DF_SFT)
	242	#define NAU8825_I2S_DF_LEFT (1 << NAU8825_I2S_DF_SFT)
	243	#define NAU8825_I2S_DF_I2S (2 << NAU8825_I2S_DF_SFT)
	244	#define NAU8825_I2S_DF_PCM_AB (3 << NAU8825_I2S_DF_SFT)
	245
	246	/* I2S_PCM_CTRL2 (0x1d) */
	247	#define NAU8825_I2S_TRISTATE (1 << 15) /* 0 - normal mode, 1 - Hi-Z output */
a33b56a6 JH	248	#define NAU8825_I2S_LRC_DIV_SFT 12
a33b56a6 JH	249	#define NAU8825_I2S_LRC_DIV_MASK (0x3 << NAU8825_I2S_LRC_DIV_SFT)
34ca27f3 AP	250	#define NAU8825_I2S_MS_SFT 3
	251	#define NAU8825_I2S_MS_MASK (1 << NAU8825_I2S_MS_SFT)
	252	#define NAU8825_I2S_MS_MASTER (1 << NAU8825_I2S_MS_SFT)
	253	#define NAU8825_I2S_MS_SLAVE (0 << NAU8825_I2S_MS_SFT)
b50455fa	254	#define NAU8825_I2S_BLK_DIV_MASK 0x7
34ca27f3	255
93dfec75 JH	256	/* LEFT_TIME_SLOT (0x1e) */
	257	#define NAU8825_FS_ERR_CMP_SEL_SFT 14
	258	#define NAU8825_FS_ERR_CMP_SEL_MASK (0x3 << NAU8825_FS_ERR_CMP_SEL_SFT)
	259	#define NAU8825_DIS_FS_SHORT_DET (1 << 13)
	260
18d8306d JH	261	/* BIQ_CTRL (0x20) */
	262	#define NAU8825_BIQ_WRT_SFT 4
	263	#define NAU8825_BIQ_WRT_EN (1 << NAU8825_BIQ_WRT_SFT)
	264	#define NAU8825_BIQ_PATH_SFT 0
	265	#define NAU8825_BIQ_PATH_MASK (1 << NAU8825_BIQ_PATH_SFT)
	266	#define NAU8825_BIQ_PATH_ADC (0 << NAU8825_BIQ_PATH_SFT)
	267	#define NAU8825_BIQ_PATH_DAC (1 << NAU8825_BIQ_PATH_SFT)
	268
34ca27f3	269	/* ADC_RATE (0x2b) */
5f1516d5 JH	270	#define NAU8825_ADC_SINC4_SFT 4
5f1516d5 JH	271	#define NAU8825_ADC_SINC4_EN (1 << NAU8825_ADC_SINC4_SFT)
34ca27f3 AP	272	#define NAU8825_ADC_SYNC_DOWN_SFT 0
	273	#define NAU8825_ADC_SYNC_DOWN_MASK 0x3
	274	#define NAU8825_ADC_SYNC_DOWN_32 0
	275	#define NAU8825_ADC_SYNC_DOWN_64 1
	276	#define NAU8825_ADC_SYNC_DOWN_128 2
	277	#define NAU8825_ADC_SYNC_DOWN_256 3
	278
	279	/* DAC_CTRL1 (0x2c) */
	280	#define NAU8825_DAC_CLIP_OFF (1 << 7)
	281	#define NAU8825_DAC_OVERSAMPLE_SFT 0
	282	#define NAU8825_DAC_OVERSAMPLE_MASK 0x7
	283	#define NAU8825_DAC_OVERSAMPLE_64 0
	284	#define NAU8825_DAC_OVERSAMPLE_256 1
	285	#define NAU8825_DAC_OVERSAMPLE_128 2
	286	#define NAU8825_DAC_OVERSAMPLE_32 4
	287
b50455fa JH	288	/* ADC_DGAIN_CTRL (0x30) */
	289	#define NAU8825_ADC_DIG_VOL_MASK 0xff
	290
34ca27f3 AP	291	/* MUTE_CTRL (0x31) */
	292	#define NAU8825_DAC_ZERO_CROSSING_EN (1 << 9)
	293	#define NAU8825_DAC_SOFT_MUTE (1 << 9)
	294
	295	/* HSVOL_CTRL (0x32) */
	296	#define NAU8825_HP_MUTE (1 << 15)
b50455fa JH	297	#define NAU8825_HP_MUTE_AUTO (1 << 14)
	298	#define NAU8825_HPL_MUTE (1 << 13)
	299	#define NAU8825_HPR_MUTE (1 << 12)
	300	#define NAU8825_HPL_VOL_SFT 6
	301	#define NAU8825_HPL_VOL_MASK (0x3f << NAU8825_HPL_VOL_SFT)
	302	#define NAU8825_HPR_VOL_SFT 0
	303	#define NAU8825_HPR_VOL_MASK (0x3f << NAU8825_HPR_VOL_SFT)
	304	#define NAU8825_HP_VOL_MIN 0x36
34ca27f3 AP	305
	306	/* DACL_CTRL (0x33) */
	307	#define NAU8825_DACL_CH_SEL_SFT 9
3f039169 JH	308	#define NAU8825_DACL_CH_SEL_MASK (0x1 << NAU8825_DACL_CH_SEL_SFT)
	309	#define NAU8825_DACL_CH_SEL_L (0x0 << NAU8825_DACL_CH_SEL_SFT)
	310	#define NAU8825_DACL_CH_SEL_R (0x1 << NAU8825_DACL_CH_SEL_SFT)
b50455fa	311	#define NAU8825_DACL_CH_VOL_MASK 0xff
34ca27f3 AP	312
	313	/* DACR_CTRL (0x34) */
	314	#define NAU8825_DACR_CH_SEL_SFT 9
3f039169 JH	315	#define NAU8825_DACR_CH_SEL_MASK (0x1 << NAU8825_DACR_CH_SEL_SFT)
	316	#define NAU8825_DACR_CH_SEL_L (0x0 << NAU8825_DACR_CH_SEL_SFT)
	317	#define NAU8825_DACR_CH_SEL_R (0x1 << NAU8825_DACR_CH_SEL_SFT)
b50455fa JH	318	#define NAU8825_DACR_CH_VOL_MASK 0xff
	319
	320	/* IMM_MODE_CTRL (0x4C) */
	321	#define NAU8825_IMM_THD_SFT 8
	322	#define NAU8825_IMM_THD_MASK (0x3f << NAU8825_IMM_THD_SFT)
	323	#define NAU8825_IMM_GEN_VOL_SFT 6
	324	#define NAU8825_IMM_GEN_VOL_MASK (0x3 << NAU8825_IMM_GEN_VOL_SFT)
	325	#define NAU8825_IMM_GEN_VOL_1_2nd (0x0 << NAU8825_IMM_GEN_VOL_SFT)
	326	#define NAU8825_IMM_GEN_VOL_1_4th (0x1 << NAU8825_IMM_GEN_VOL_SFT)
	327	#define NAU8825_IMM_GEN_VOL_1_8th (0x2 << NAU8825_IMM_GEN_VOL_SFT)
	328	#define NAU8825_IMM_GEN_VOL_1_16th (0x3 << NAU8825_IMM_GEN_VOL_SFT)
	329
	330	#define NAU8825_IMM_CYC_SFT 4
	331	#define NAU8825_IMM_CYC_MASK (0x3 << NAU8825_IMM_CYC_SFT)
	332	#define NAU8825_IMM_CYC_1024 (0x0 << NAU8825_IMM_CYC_SFT)
	333	#define NAU8825_IMM_CYC_2048 (0x1 << NAU8825_IMM_CYC_SFT)
	334	#define NAU8825_IMM_CYC_4096 (0x2 << NAU8825_IMM_CYC_SFT)
	335	#define NAU8825_IMM_CYC_8192 (0x3 << NAU8825_IMM_CYC_SFT)
	336	#define NAU8825_IMM_EN (1 << 3)
	337	#define NAU8825_IMM_DAC_SRC_MASK 0x7
	338	#define NAU8825_IMM_DAC_SRC_BIQ 0x0
	339	#define NAU8825_IMM_DAC_SRC_DRC 0x1
	340	#define NAU8825_IMM_DAC_SRC_MIX 0x2
	341	#define NAU8825_IMM_DAC_SRC_SIN 0x3
34ca27f3	342
45d5eb3a JH	343	/* CLASSG_CTRL (0x50) */
	344	#define NAU8825_CLASSG_TIMER_SFT 8
	345	#define NAU8825_CLASSG_TIMER_MASK (0x3f << NAU8825_CLASSG_TIMER_SFT)
b50455fa JH	346	#define NAU8825_CLASSG_TIMER_1ms (0x1 << NAU8825_CLASSG_TIMER_SFT)
	347	#define NAU8825_CLASSG_TIMER_2ms (0x2 << NAU8825_CLASSG_TIMER_SFT)
	348	#define NAU8825_CLASSG_TIMER_8ms (0x4 << NAU8825_CLASSG_TIMER_SFT)
	349	#define NAU8825_CLASSG_TIMER_16ms (0x8 << NAU8825_CLASSG_TIMER_SFT)
	350	#define NAU8825_CLASSG_TIMER_32ms (0x10 << NAU8825_CLASSG_TIMER_SFT)
	351	#define NAU8825_CLASSG_TIMER_64ms (0x20 << NAU8825_CLASSG_TIMER_SFT)
	352	#define NAU8825_CLASSG_LDAC_EN (0x1 << 2)
	353	#define NAU8825_CLASSG_RDAC_EN (0x1 << 1)
45d5eb3a JH	354	#define NAU8825_CLASSG_EN (1 << 0)
45d5eb3a JH	355
34ca27f3 AP	356	/* I2C_DEVICE_ID (0x58) */
	357	#define NAU8825_GPIO2JD1 (1 << 7)
	358	#define NAU8825_SOFTWARE_ID_MASK 0x3
	359	#define NAU8825_SOFTWARE_ID_NAU8825 0x0
	360
	361	/* BIAS_ADJ (0x66) */
b50455fa JH	362	#define NAU8825_BIAS_HPR_IMP (1 << 15)
	363	#define NAU8825_BIAS_HPL_IMP (1 << 14)
	364	#define NAU8825_BIAS_TESTDAC_SFT 8
	365	#define NAU8825_BIAS_TESTDAC_EN (0x3 << NAU8825_BIAS_TESTDAC_SFT)
	366	#define NAU8825_BIAS_TESTDACR_EN (0x2 << NAU8825_BIAS_TESTDAC_SFT)
	367	#define NAU8825_BIAS_TESTDACL_EN (0x1 << NAU8825_BIAS_TESTDAC_SFT)
34ca27f3 AP	368	#define NAU8825_BIAS_VMID (1 << 6)
	369	#define NAU8825_BIAS_VMID_SEL_SFT 4
	370	#define NAU8825_BIAS_VMID_SEL_MASK (3 << NAU8825_BIAS_VMID_SEL_SFT)
	371
	372	/* ANALOG_CONTROL_2 (0x6a) */
	373	#define NAU8825_HP_NON_CLASSG_CURRENT_2xADJ (1 << 12)
	374	#define NAU8825_DAC_CAPACITOR_MSB (1 << 1)
	375	#define NAU8825_DAC_CAPACITOR_LSB (1 << 0)
	376
	377	/* ANALOG_ADC_2 (0x72) */
	378	#define NAU8825_ADC_VREFSEL_MASK (0x3 << 8)
	379	#define NAU8825_ADC_VREFSEL_ANALOG (0 << 8)
	380	#define NAU8825_ADC_VREFSEL_VMID (1 << 8)
	381	#define NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB (2 << 8)
	382	#define NAU8825_ADC_VREFSEL_VMID_PLUS_1DB (3 << 8)
	383	#define NAU8825_POWERUP_ADCL (1 << 6)
	384
45d5eb3a	385	/* RDAC (0x73) */
b50455fa JH	386	#define NAU8825_RDAC_FS_BCLK_ENB (1 << 15)
	387	#define NAU8825_RDAC_EN_SFT 12
	388	#define NAU8825_RDAC_EN (0x3 << NAU8825_RDAC_EN_SFT)
	389	#define NAU8825_RDAC_CLK_EN_SFT 8
	390	#define NAU8825_RDAC_CLK_EN (0x3 << NAU8825_RDAC_CLK_EN_SFT)
45d5eb3a JH	391	#define NAU8825_RDAC_CLK_DELAY_SFT 4
	392	#define NAU8825_RDAC_CLK_DELAY_MASK (0x7 << NAU8825_RDAC_CLK_DELAY_SFT)
	393	#define NAU8825_RDAC_VREF_SFT 2
	394	#define NAU8825_RDAC_VREF_MASK (0x3 << NAU8825_RDAC_VREF_SFT)
	395
34ca27f3 AP	396	/* MIC_BIAS (0x74) */
	397	#define NAU8825_MICBIAS_JKSLV (1 << 14)
	398	#define NAU8825_MICBIAS_JKR2 (1 << 12)
	399	#define NAU8825_MICBIAS_POWERUP_SFT 8
	400	#define NAU8825_MICBIAS_VOLTAGE_SFT 0
	401	#define NAU8825_MICBIAS_VOLTAGE_MASK 0x7
	402
	403	/* BOOST (0x76) */
	404	#define NAU8825_PRECHARGE_DIS (1 << 13)
	405	#define NAU8825_GLOBAL_BIAS_EN (1 << 12)
45d5eb3a	406	#define NAU8825_HP_BOOST_DIS (1 << 9)
34ca27f3 AP	407	#define NAU8825_HP_BOOST_G_DIS (1 << 8)
	408	#define NAU8825_SHORT_SHUTDOWN_EN (1 << 6)
	409
	410	/* POWER_UP_CONTROL (0x7f) */
	411	#define NAU8825_POWERUP_INTEGR_R (1 << 5)
	412	#define NAU8825_POWERUP_INTEGR_L (1 << 4)
	413	#define NAU8825_POWERUP_DRV_IN_R (1 << 3)
	414	#define NAU8825_POWERUP_DRV_IN_L (1 << 2)
	415	#define NAU8825_POWERUP_HP_DRV_R (1 << 1)
	416	#define NAU8825_POWERUP_HP_DRV_L (1 << 0)
	417
	418	/* CHARGE_PUMP (0x80) */
	419	#define NAU8825_JAMNODCLOW (1 << 10)
	420	#define NAU8825_POWER_DOWN_DACR (1 << 9)
	421	#define NAU8825_POWER_DOWN_DACL (1 << 8)
	422	#define NAU8825_CHANRGE_PUMP_EN (1 << 5)
	423
	424
	425	/* System Clock Source */
	426	enum {
2ec30f60 JH	427	NAU8825_CLK_DIS = 0,
2ec30f60 JH	428	NAU8825_CLK_MCLK,
34ca27f3	429	NAU8825_CLK_INTERNAL,
70543c30 JH	430	NAU8825_CLK_FLL_MCLK,
	431	NAU8825_CLK_FLL_BLK,
	432	NAU8825_CLK_FLL_FS,
34ca27f3 AP	433	};
34ca27f3 AP	434
b50455fa JH	435	/* Cross talk detection state */
	436	enum {
	437	NAU8825_XTALK_PREPARE = 0,
	438	NAU8825_XTALK_HPR_R2L,
	439	NAU8825_XTALK_HPL_R2L,
	440	NAU8825_XTALK_IMM,
	441	NAU8825_XTALK_DONE,
	442	};
	443
34ca27f3 AP	444	struct nau8825 {
	445	struct device *dev;
	446	struct regmap *regmap;
	447	struct snd_soc_dapm_context *dapm;
	448	struct snd_soc_jack *jack;
	449	struct clk *mclk;
b50455fa JH	450	struct work_struct xtalk_work;
b50455fa JH	451	struct semaphore xtalk_sem;
34ca27f3 AP	452	int irq;
	453	int mclk_freq; /* 0 - mclk is disabled */
	454	int button_pressed;
	455	int micbias_voltage;
	456	int vref_impedance;
	457	bool jkdet_enable;
	458	bool jkdet_pull_enable;
	459	bool jkdet_pull_up;
	460	int jkdet_polarity;
	461	int sar_threshold_num;
	462	int sar_threshold[8];
	463	int sar_hysteresis;
	464	int sar_voltage;
	465	int sar_compare_time;
	466	int sar_sampling_time;
	467	int key_debounce;
	468	int jack_insert_debounce;
	469	int jack_eject_debounce;
b50455fa JH	470	int high_imped;
	471	int xtalk_state;
	472	int xtalk_event;
	473	int xtalk_event_mask;
	474	bool xtalk_protect;
	475	int imp_rms[NAU8825_XTALK_IMM];
226d7449	476	int xtalk_enable;
fa25b4f5	477	bool xtalk_baktab_initialized; /* True if initialized. */
34ca27f3 AP	478	};
34ca27f3 AP	479
45101122	480	int nau8825_enable_jack_detect(struct snd_soc_component *component,
34ca27f3 AP	481	struct snd_soc_jack *jack);
	482
	483
	484	#endif /* __NAU8825_H__ */